NAND Flash Controller Module Registers (AXI Slave) Address Map

Registers in the NAND Flash Controller module accessible via its register AXI slave

Base Address: 0xFFB80000

Configuration registers

Register Offset Width Access Reset Value Description
device_reset 0x0 32 RW 0x0
transfer_spare_reg 0x10 32 RW 0x0
load_wait_cnt 0x20 32 RW 0x1F4
program_wait_cnt 0x30 32 RW 0x1F4
erase_wait_cnt 0x40 32 RW 0x1F4
int_mon_cyccnt 0x50 32 RW 0x1F4
rb_pin_enabled 0x60 32 RW 0x1
multiplane_operation 0x70 32 RW 0x0
multiplane_read_enable 0x80 32 RW 0x0
copyback_disable 0x90 32 RW 0x0
cache_write_enable 0xA0 32 RW 0x0
cache_read_enable 0xB0 32 RW 0x0
prefetch_mode 0xC0 32 RW 0x1
chip_enable_dont_care 0xD0 32 RW 0x0
ecc_enable 0xE0 32 RW 0x1
global_int_enable 0xF0 32 RW 0x0
twhr2_and_we_2_re 0x100 32 RW 0x1432
tcwaw_and_addr_2_data 0x110 32 RW 0x1432
re_2_we 0x120 32 RW 0x32
acc_clks 0x130 32 RW 0x0
number_of_planes 0x140 32 RW 0x0
pages_per_block 0x150 32 RW 0x0
device_width 0x160 32 RW 0x3
device_main_area_size 0x170 32 RW 0x0
device_spare_area_size 0x180 32 RW 0x0
two_row_addr_cycles 0x190 32 RW 0x0
multiplane_addr_restrict 0x1A0 32 RW 0x0
ecc_correction 0x1B0 32 RW 0x8
read_mode 0x1C0 32 RW 0x0
write_mode 0x1D0 32 RW 0x0
copyback_mode 0x1E0 32 RW 0x0
rdwr_en_lo_cnt 0x1F0 32 RW 0x12
rdwr_en_hi_cnt 0x200 32 RW 0xC
max_rd_delay 0x210 32 RW 0x0
cs_setup_cnt 0x220 32 RW 0x3
spare_area_skip_bytes 0x230 32 RW 0x0
spare_area_marker 0x240 32 RW 0xFFFF
devices_connected 0x250 32 RW 0x0
die_mask 0x260 32 RW 0x0
first_block_of_next_plane 0x270 32 RW 0x1
write_protect 0x280 32 RW 0x1
re_2_re 0x290 32 RW 0x32
por_reset_count 0x2A0 32 RW 0x13B
watchdog_reset_count 0x2B0 32 RW 0x5B9A

Device parameters

Register Offset Width Access Reset Value Description
manufacturer_id 0x300 32 RW 0x0
device_id 0x310 32 RO 0x0
device_param_0 0x320 32 RO 0x0
device_param_1 0x330 32 RO 0x0
device_param_2 0x340 32 RO 0x0
logical_page_data_size 0x350 32 RO 0x0
logical_page_spare_size 0x360 32 RO 0x0
revision 0x370 32 RO 0x5
onfi_device_features 0x380 32 RO 0x0
onfi_optional_commands 0x390 32 RO 0x0
onfi_timing_mode 0x3A0 32 RO 0x0
onfi_pgm_cache_timing_mode 0x3B0 32 RO 0x0
onfi_device_no_of_luns 0x3C0 32 RW 0x0
onfi_device_no_of_blocks_per_lun_l 0x3D0 32 RO 0x0
onfi_device_no_of_blocks_per_lun_u 0x3E0 32 RO 0x0
features 0x3F0 32 RO 0x841

Interrupt and Status Registers

Register Offset Width Access Reset Value Description
transfer_mode 0x400 32 RO 0x0
intr_status0 0x410 32 RW 0x0
intr_en0 0x420 32 RW 0x2000
page_cnt0 0x430 32 RO 0x0
err_page_addr0 0x440 32 RO 0x0
err_block_addr0 0x450 32 RO 0x0
intr_status1 0x460 32 RW 0x0
intr_en1 0x470 32 RW 0x2000
page_cnt1 0x480 32 RO 0x0
err_page_addr1 0x490 32 RO 0x0
err_block_addr1 0x4A0 32 RO 0x0
intr_status2 0x4B0 32 RW 0x0
intr_en2 0x4C0 32 RW 0x2000
page_cnt2 0x4D0 32 RO 0x0
err_page_addr2 0x4E0 32 RO 0x0
err_block_addr2 0x4F0 32 RO 0x0
intr_status3 0x500 32 RW 0x0
intr_en3 0x510 32 RW 0x2000
page_cnt3 0x520 32 RO 0x0
err_page_addr3 0x530 32 RO 0x0
err_block_addr3 0x540 32 RO 0x0

ECC registers

Register Offset Width Access Reset Value Description
ECCCorInfo_b01 0x650 32 RO 0x0
ECCCorInfo_b23 0x660 32 RO 0x0

DMA registers

Register Offset Width Access Reset Value Description
dma_enable 0x700 32 RW 0x0
dma_intr 0x720 32 RW 0x0
dma_intr_en 0x730 32 RW 0x0
target_err_addr_lo 0x740 32 RO 0x0
target_err_addr_hi 0x750 32 RO 0x0
flash_burst_length 0x770 32 RW 0x1
chip_interleave_enable_and_allow_int_reads 0x780 32 RW 0x10
no_of_blocks_per_lun 0x790 32 RW 0xF
lun_status_cmd 0x7A0 32 RW 0x7878