tcwaw_and_addr_2_data

Module Instance	Base Address	Register Address
`nandregs`	`0xFFB80000`	`0xFFB80110`

Offset: 0x110

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`		`tcwaw` `RW 0x14`						`Reserved`		`addr_2_data` `RW 0x32`

tcwaw_and_addr_2_data Fields

Bit	Name	Description	Access	Reset
13:8	`tcwaw`	Signifies the number of controller clocks that should be introduced between the command cycle of a random data input command to the address cycle of the random data input command.	`RW`	`0x14`
5:0	`addr_2_data`	Signifies the number of bus interface nand_mp_clk clocks that should be introduced between address latch enable going low to write enable going low. The number of clocks is the function of device parameter Tadl and controller clock frequency.	`RW`	`0x32`