On-chip RAM Register Descriptions Registers associated with the On-chip RAM master. This master is used to access the contents of the On-chip RAM. Offset: 0x25000 fn_mod_bm_iss Sets the issuing capability of the preceding switch arbitration scheme to multiple or single outstanding transactions. wr_tidemark Controls the release of the transaction in the write data FIFO. fn_mod Sets the block issuing capability to multiple or single outstanding transactions. Related reference L4 MAIN Register Descriptions L4 SP Register Descriptions L4 MP Register Descriptions L4 OSC1 Register Descriptions L4 SPIM Register Descriptions STM Register Descriptions LWHPS2FPGA Register Descriptions USB1 Register Descriptions NANDDATA Register Descriptions USB0 Register Descriptions NANDREGS Register Descriptions QSPIDATA Register Descriptions FPGAMGRDATA Register Descriptions HPS2FPGA Register Descriptions ACP Register Descriptions Boot ROM Register Descriptions