Peripheral PLL Group Register Descriptions Contains registers with settings for the Peripheral PLL. Offset: 0x80 vco Contains settings that control the Peripheral PLL VCO. The VCO output frequency is the input frequency multiplied by the numerator (M+1) and divided by the denominator (N+1). Fields are only reset by a cold reset. misc Contains VCO control signals and other PLL control signals need to be controllable through register. Fields are only reset by a cold reset. emac0clk Contains settings that control clock emac0_clk generated from the C0 output of the Peripheral PLL. Only reset by a cold reset. emac1clk Contains settings that control clock emac1_clk generated from the C1 output of the Peripheral PLL. Only reset by a cold reset. perqspiclk Contains settings that control clock periph_qspi_clk generated from the C2 output of the Peripheral PLL. Only reset by a cold reset. pernandsdmmcclk Contains settings that control clock periph_nand_sdmmc_clk generated from the C3 output of the Peripheral PLL. Only reset by a cold reset. perbaseclk Contains settings that control clock periph_base_clk generated from the C4 output of the Peripheral PLL. Only reset by a cold reset. s2fuser1clk Contains settings that control clock s2f_user1_clk generated from the C5 output of the Peripheral PLL. and user documentation refer to s2f_user1_clk as h2f_user1_clk. Only reset by a cold reset. en Contains fields that control clock enables for clocks derived from the Peripheral PLL 1: The clock is enabled. 0: The clock is disabled. Fields are only reset by a cold reset. div Contains fields that control clock dividers for clocks derived from the Peripheral PLL Fields are only reset by a cold reset. gpiodiv Contains a field that controls the clock divider for the GPIO De-bounce clock. Only reset by a cold reset. src Contains fields that select the source clocks for the flash controllers. Fields are only reset by a cold reset. stat Contains Output Clock Counter Reset acknowledge status.