IF1MCTR

The Interface 1 Message Control Register is one of two registers sets that define and provide status for CPU read and write accesses to the Message RAM. The IF1MCTR register displays message status and controls message interrupt enables and transfer configuration.
Module Instance Base Address Register Address
can0 0xFFC00000 0xFFC0010C
can1 0xFFC01000 0xFFC0110C

Offset: 0x10C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

NewDat

RW 0x0

MsgLst

RW 0x0

IntPnd

RW 0x0

UMask

RW 0x0

TxIE

RW 0x0

RxIE

RW 0x0

RmtEn

RW 0x0

TxRqst

RW 0x0

EoB

RW 0x0

Reserved

DLC

RW 0x0

IF1MCTR Fields

Bit Name Description Access Reset
15 NewDat

New Data

Value Description
0x0 No new data has been written into the data portion of this Message Object by the Message Handler since last time this flag was cleared by the CPU.
0x1 The Message Handler or the CPU has written new data into the data portion of this Message Object.
RW 0x0
14 MsgLst

Message Lost

Value Description
0x0 No message lost since last time this bit was reset by the CPU.
0x1 The Message Handler stored a new message into this object when NewDat was still set, the CPU has lost a message.
RW 0x0
13 IntPnd

Interrupt Pending

Value Description
0x0 This message object is not the source of an interrupt.
0x1 This message object is the source of an interrupt. The Interrupt Identifier in the Interrupt Register will point to this message object if there is no other interrupt source with higher priority.
RW 0x0
12 UMask

Use Acceptance Mask

Value Description
0x0 Acceptance formula1: (RTRRx == ~DIR) && (IDERx == IDE) && (IDRx == ID)
0x1 (Msk28-0, MXtd, and MDir) for acceptance filtering, formula: ((RTRRx & MDIR) == (~DIR & MDIR)) && ((IDERx & MXtd) == (IDE & MXtd)) && ((IDRx & Msk) == (ID & Msk)) Note: If the UMask bit is set to one, the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal is set to one.
RW 0x0
11 TxIE

Transmit Interrupt Enable

Value Description
0x0 IntPnd will be left unchanged after the successful transmission of a frame.
0x1 IntPnd will be set after a successful transmission of a frame.
RW 0x0
10 RxIE

Receive Interrupt Enable

Value Description
0x0 IntPnd will be left unchanged after the successful reception of a frame.
0x1 IntPnd will be set after a successful reception of a frame.
RW 0x0
9 RmtEn

Remote Enable

Value Description
0x0 At the reception of a Remote Frame, TxRqst is left unchanged.
0x1 At the reception of a Remote Frame, TxRqst is set.
RW 0x0
8 TxRqst

Transmit Request

Value Description
0x0 This Message Object is not waiting for transmission.
0x1 The transmission of this Message Object is requested and is not yet done.
RW 0x0
7 EoB

Note: This bit is used to concatenate two or more Message Objects (up to 128) to build a FIFO Buffer. For single Message Objects (not belonging to a FIFO Buffer) this bit must always be set to one.

Value Description
0x0 Message Object belongs to a FIFO Buffer Block and is not the last Message Object of that FIFO Buffer Block.
0x1 Single Message Object or last Message Object of a FIFO Buffer Block.
RW 0x0
3:0 DLC

0-8 Data Frame has 0-8 data bytes. 9-15 Data Frame has 8 data bytes. Note: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes. When the Message Handler stores a data frame, it will write the DLC to the value given by the received message.

RW 0x0