CSTS

Status Register
Module Instance Base Address Register Address
can0 0xFFC00000 0xFFC00004
can1 0xFFC01000 0xFFC01004

Offset: 0x4

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

PER

RO 0x0

BOff

RO 0x0

EWarn

RO 0x0

EPASS

RO 0x0

RxOK

RO 0x0

TxOK

RO 0x0

LEC

RO 0x7

CSTS Fields

Bit Name Description Access Reset
8 PER

Parity Error Detected

Value Description
0x0 No parity error detected since last read access.
0x1 The Parity CheckMechanism has detected a parity error in the Message RAM, this bit will be reset if Status Register is read
RO 0x0
7 BOff

Bus_Off Status

Value Description
0x0 The CAN module is not Bus_Off.
0x1 The CAN module is in Bus_Off state.
RO 0x0
6 EWarn

Warning Status

Value Description
0x0 Both error counters are below the error warning limit of 96.
0x1 At least one of the error counters in the EML has reached the error warning limit of 96.
RO 0x0
5 EPASS

Error Passive

Value Description
0x0 The CAN Core is in the error active state. It normally takes part in bus communication and sends an active error flag when an error has been detected.
0x1 The CAN Core is in the error passive state as defined in the CAN Specification.
RO 0x0
4 RxOK

Received a Message Successfully

Value Description
0x0 Since this bit was read by the CPU, no message has been successfully received. This bit is never reset by CAN internal events.
0x1 Since this bit was last reset by a read access of the CPU, a message has been successfully received (independently of the result of acceptance filtering). This bit will be reset by reading the Status Register.
RO 0x0
3 TxOK

Transmitted a Message Successfully

Value Description
0x0 Since this bit was last read by the CPU, no message has been successfully transmitted. This bit is never reset by CAN internal events.
0x1 Since this bit was last reset by a read access of the CPU, a message has been successfully (error free and acknowledged by at least one other node) transmitted. This bit will be reset by reading the Status Register.
RO 0x0
2:0 LEC

The LEC field holds a code which indicates the type of the last error to occur on the CAN bus. This field will be cleared to 0 when a message has been transferred (reception or transmission) without error.

Value Description
0x0 Set together with CSTS.RxOK or CSTS.TxOK.
0x1 More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed.
0x2 A fixed format part of a received frame has the wrong format.
0x3 The message this CAN Core transmitted was not acknowledged by another node.
0x4 During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value 1), but the monitored bus value was dominant.
0x5 During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value 0), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the CPU to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed).
0x6 The CRC checksum was incorrect in the message received, the CRC received for an incoming message does not match with the calculated CRC for the received data.
0x7 Any read access to the Status Register re initializes the LEC to 7. When the LEC shows the value 7, no CAN bus event was detected since the last CPU read access to the Status Register.
RO 0x7