doepctl14

Out Endpoint 14.
Module Instance Base Address Register Address
usb0 0xFFB00000 0xFFB00CC0
usb1 0xFFB40000 0xFFB40CC0

Offset: 0xCC0

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

epena

RO 0x0

epdis

RO 0x0

setd1pid

WO 0x0

setd0pid

WO 0x0

snak

WO 0x0

cnak

WO 0x0

Reserved

stall

RO 0x0

snp

RW 0x0

eptype

RW 0x0

naksts

RO 0x0

dpid

RO 0x0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

usbactep

RW 0x0

Reserved

mps

RW 0x0

doepctl14 Fields

Bit Name Description Access Reset
31 epena

Applies to IN and OUT endpoints. -When Scatter/Gather DMA mode is enabled, -for IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. -for OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup. -When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode: - for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint. - for OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB. - The core clears this bit before setting any of the following interrupts on this endpoint: -SETUP Phase Done -Endpoint Disabled -Transfer Completed for control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

Value Description
0x0 Endpoint Enable inactive
0x1 Endpoint Enable active
RO 0x0
30 epdis

Applies to IN and OUT endpoints. The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

Value Description
0x0 No Endpoint Disable
0x1 Endpoint Disable
RO 0x0
29 setd1pid

Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.

Value Description
0x0 Disables Set DATA1 PID
0x1 Enables Set DATA1 PID
WO 0x0
28 setd0pid

Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Value Description
0x0 Disables Set DATA0 PID
0x1 Enables Endpoint Data PID to DATA0)
WO 0x0
27 snak

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

Value Description
0x0 No Set NAK
0x1 Set NAK
WO 0x0
26 cnak

A write to this bit clears the NAK bit for the endpoint.

Value Description
0x0 No Clear NAK
0x1 Clear NAK
WO 0x0
21 stall

Applies to non-control, non-isochronous IN and OUT endpoints only. The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only. The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Value Description
0x0 STALL All Tokens not active
0x1 STALL All Tokens active
RO 0x0
20 snp

Applies to OUT endpoints only. This bit configures the endpoint to Snoop mode. In Snoop mode, the core does not check the correctness of OUT packets before transferring them to application memory.

Value Description
0x0 Disable Snoop Mode
0x1 Enable Snoop Mode
RW 0x0
19:18 eptype

This is the transfer type supported by this logical endpoint.

Value Description
0x0 Control
0x1 Isochronous
0x2 Bulk
0x3 Interrupt
RW 0x0
17 naksts

When either the application or the core sets this bit: -The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. -for non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. -for isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Value Description
0x0 The core is transmitting non-NAK handshakes based on the FIFO status
0x1 The core is transmitting NAK handshakes on this endpoint
RO 0x0
16 dpid

Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather DMA mode: Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro) frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register. 0: Even (micro)frame 1: Odd (micro)frame When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Value Description
0x0 Endpoint Data PID not active
0x1 Endpoint Data PID active
RO 0x0
15 usbactep

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Value Description
0x0 Not Active
0x1 USB Active Endpoint
RW 0x0
10:0 mps

Applies to IN and OUT endpoints. The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

RW 0x0