gahbcfg

This register can be used to configure the core after power-on or a change in mode. This register mainly contains AHB system-related configuration parameters. Do not change this register after the initial programming. The application must program this register before starting any transactions on either the AHB or the USB.

Module Instance	Base Address	Register Address
`usb0`	`0xFFB00000`	`0xFFB00008`
`usb1`	`0xFFB40000`	`0xFFB40008`

Offset: 0x8

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.

Bit Fields
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16
`Reserved`									`notialldmawrit` `RW 0x0`	`remmemsupp` `RW 0x0`	`Reserved`
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
`Reserved`							`ptxfemplvl` `RW 0x0`	`nptxfemplvl` `RW 0x0`	`Reserved`	`dmaen` `RW 0x0`	`hbstlen` `RW 0x0`				`glblintrmsk` `RW 0x0`

gahbcfg Fields

Bit

Name

Description

Access

Reset

notialldmawrit

This bit is programmed to enable the System DMA Done functionality for all the DMA write Transactions corresponding to the Channel/Endpoint. This bit is valid only when GAHBCFG.RemMemSupp is set to 1.

Value	Description
0x1	HSOTG core asserts int_dma_req for all the DMA write transactions on the AHB interface along with int_dma_done, chep_last_transact and chep_number signal informations. The core waits for sys_dma_done signal for all the DMA write transactions in order to complete the transfer of a particular Channel/Endpoint
0x0	HSOTG core asserts int_dma_req signal only for the last transaction of DMA write transfer corresponding to a particular Channel/Endpoint. Similarly, the core waits for sys_dma_done signal only for that transaction of DMA write to complete the transfer of a particular Channel/Endpoint

RW

0x0

remmemsupp

This bit is programmed to enable/disable the functionality to wait for the system DMA Done Signal for the DMA Write Transfers. -The int_dma_req output signal is asserted when HSOTG DMA starts write transfer to the external memory. When the core is done with the Transfers it asserts int_dma_done signal to flag the completion of DMA writes from HSOTG. The core then waits for sys_dma_done signal from the system to proceed further and complete the Data Transfer corresponding to a particular Channel/Endpoint. -The int_dma_req and int_dma_done signals are not asserted and the core proceeds with the assertion of the XferComp interrupt as soon as wait for the system DMA Done Signal for the DMA Write Transfers the DMA write transfer is done at the HSOTG Core Boundary and it doesn't wait for the sys_dma_done signal to complete the DATA

Value	Description
0x0	Disable wait for system DMA Done Signal
0x1	Enable wait for the system DMA Done Signal for the DMA Write Transfers

RW

0x0

ptxfemplvl

Mode:Host only. Indicates when the Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.PTxFEmp) is triggered. This bit is used only in Slave mode.

Value	Description
0x0	GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty
0x1	GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty

RW

0x0

nptxfemplvl

Mode:Host and device. This bit is used only in Slave mode. In host mode and with Shared FIFO with device mode, this bit indicates when the Non-Periodic TxFIFO Empty Interrupt bit in the Core Interrupt register (GINTSTS.NPTxFEmp) is triggered. With dedicated FIFO in device mode, this bit indicates when IN endpoint Transmit FIFO empty interrupt (DIEPINTn.TxFEmp) is triggered. Host mode and with Shared FIFO with device mode:

Value	Description
0x0	DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
0x1	GINTSTS.NPTxFEmp interrupt indicates that the Non-Periodic TxFIFO is completely empty or DIEPINTn.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty

RW

0x0

dmaen

Mode:Host and device. Enables switching from DMA mode to slave mode.

Value	Description
0x0	Core operates in Slave mode
0x1	Core operates in a DMA mode

RW

0x0

4:1

hbstlen

Mode:Host and device. This field is used in Internal DMA modes.

Value	Description
0x0	1 word or single
0x1	4 word or incr
0x2	8 word
0x3	16 word or incr4
0x4	32 word
0x5	64 word or incr8
0x6	128 word
0x7	256 word or incr16
0x8	Others reserved

RW

0x0

glblintrmsk

Mode: Host and device. The application uses this bit to mask or unmask the interrupt line assertion to itself. Irrespective of this bits setting, the interrupt status registers are updated by the core.

Value	Description
0x0	Mask the interrupt assertion to the application
0x1	Unmask the interrupt assertion to the application.

RW

0x0