idsts

Sets Internal DMAC Status Fields
Module Instance Base Address Register Address
sdmmc 0xFF704000 0xFF70408C

Offset: 0x8C

Access: RW

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved

fsm

RO 0x0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

fsm

RO 0x0

eb

RO 0x0

ais

RW 0x0

nis

RW 0x0

Reserved

ces

RW 0x0

du

RW 0x0

Reserved

fbe

RW 0x0

ri

RW 0x0

ti

RW 0x0

idsts Fields

Bit Name Description Access Reset
16:13 fsm

DMAC FSM present state.

Value Description
0x0 DMA IDLE
0x1 DMA SUSPEND
0x2 DESC_RD
0x3 DESC_CHK
0x4 DMA RD REQ WAIT
0x5 DMA WR REQ WAIT
0x6 DMA RD
0x7 DMA WR
0x8 DESC CLOSE
RO 0x0
12:10 eb

Indicates the type of error that caused a Bus Error. Valid only with Fatal Bus Error bit (IDSTS[2]) set. This field does not generate an interrupt.

Value Description
0x1 Host Abort during transmission Status Bit
0x2 Host Abort received during reception Status Bit
RO 0x0
9 ais

Logical OR of the following: IDSTS[2] - Fatal Bus Interrupt IDSTS[4] - DU bit Interrupt IDSTS[5] - Card Error Summary Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes AIS to be set is cleared.

Value Description
0x1 Clears Abnormal Summary Interrupt Status Bit
0x0 No Clear Abnormal Summary Interrupt Status Bit
RW 0x0
8 nis

Logical OR of the following: IDSTS[0] - Transmit Interrupt IDSTS[1] - Receive Interrupt Only unmasked bits affect this bit. This is a sticky bit and must be cleared each time a corresponding bit that causes NIS to be set is cleared.

Value Description
0x1 Clears Normal Interrupt Summary Status Bit
0x0 No Clear Normal Interrupt Summary Status Bit
RW 0x0
5 ces

Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits: EBE - End Bit Error RTO - Response Timeout/Boot Ack Timeout RCRC - Response CRC SBE - Start Bit Error DRTO - Data Read Timeout/BDS timeout DCRC - Data CRC for Receive RE - Response Error

Value Description
0x1 Clears Card Error Summary Interrupt Status Bit
0x0 No Clear Card Error Summary Interrupt Status Bit
RW 0x0
4 du

This status bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0).

Value Description
0x1 Clears Descriptor Unavailable Interrupt Status Bit
0x0 No Clear of Descriptor Unavailable Interrupt Status Bit
RW 0x0
2 fbe

Indicates that a Bus Error occurred (IDSTS[12:10]). When setthe DMA disables all its bus accesses.

Value Description
0x1 Clears Fatal Bus Error Interrupt Status Bit
0x0 No Clear of Fatal Bus Error Interrupt Status Bit
RW 0x0
1 ri

Indicates the completion of data reception for a descriptor

Value Description
0x1 Clears Receive Interrupt Status Bit
0x0 No Clear of Receive Interrupt Status Bit
RW 0x0
0 ti

Indicates that data transmission is finished for a descriptor.

Value Description
0x1 Clears Transmit Interrupt Status Bit
0x0 No Clear of Transmit Interrupt Status Bit
RW 0x0