MPU L2 Cache Controller (L2C-310) Module Address Map

This address space is allocated to the MPU L2 cache controller. For detailed information about the use of this address space, click here to access the documentation for the L2C-310.

Table 1. MPU L2 Cache Controller Address Range
Module Instance	Start Address	End Address
`MPUL2`	`0xFFFEF000`	`0xFFFEFFFF`

Table 2. MPU L2 Cache Controller Register Range
Register Group	Description	Start Address	End Address
`Cache ID and Cache Type`	This address space is allocated for the cache ID and cache type registers.	`0xFFFEF000`	`0xFFFEF0FF`
`Control`	This is the address space for the cache control registers.	`0xFFFEF100`	`0xFFFEF1FF`
`Interrupt/Counter Control`	This address space is allocated for the Interrupt/Counter control registers.	`0xFFFEF200`	`0xFFFEF2FF`
`Reserved`	This address space is reserved.	`0xFFFEF300`	`0xFFFEF6FF`
`Cache Maintenance Operations`	This is the address space is allocated for the cache maintenance operation registers.	`0xFFFEF700`	`0xFFFEF7FF`
`Reserved`	This address space is reserved.	`0xFFFEF800`	`0xFFFEF8FF`
`Cache Lockdown`	This addres space is allocated for cache lockdown registers.	`0xFFFEF900`	`0xFFFEF9FF`
`Reserved`	This address space is reserved.	`0xFFFEFA00`	`0xFFFEFBFF`
`Address Filtering`	This address space is allocated for address filtering registers.	`0xFFFEFC00`	`0xFFFEFCFF`
`Reserved`	This address space is reserved.	`0xFFFEFD00`	`0xFFFEFEFF`
`Debug, Prefetch, Power`	This address space is allocated for debug, prefetch and power registers.	`0xFFFEFF00`	`0xFFFEFFFF`