l3master
Controls the L3 master HPROT AHB-Lite signal.
These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation
All fields are reset by a cold or warm reset.
| Module Instance | Base Address | Register Address |
|---|---|---|
| sysmgr | 0xFFD08000 | 0xFFD0810C |
Offset: 0x10C
Access: RW
Important: To prevent indeterminate
system behavior, reserved areas of memory must not be accessed by software or
hardware. Any area of the memory map that is not explicitly defined as a register
space or accessible memory is considered reserved.
| Bit Fields | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 |
Reserved |
|||||||||||||||
| 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved |
hprotcache_0 RW 0x0 |
hprotbuff_0 RW 0x0 |
hprotpriv_0 RW 0x1 |
hprotdata_0 RW 0x1 |
|||||||||||
l3master Fields
| Bit | Name | Description | Access | Reset | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 3 | hprotcache_0 | If 1, L3 master accesses for the SD/MMC module are cacheable. |
RW | 0x0 | ||||||
| 2 | hprotbuff_0 | If 1, L3 master accesses for the SD/MMC module are bufferable. |
RW | 0x0 | ||||||
| 1 | hprotpriv_0 | If 1, L3 master accesses for the SD/MMC module are privileged. |
RW | 0x1 | ||||||
| 0 | hprotdata_0 | Specifies if the L3 master access is for data or opcode for the SD/MMC module.
|
RW | 0x1 |