bootinfo

Provides access to boot configuration information.
Module Instance Base Address Register Address
sysmgr 0xFFD08000 0xFFD08014

Offset: 0x14

Access: RO

Important: To prevent indeterminate system behavior, reserved areas of memory must not be accessed by software or hardware. Any area of the memory map that is not explicitly defined as a register space or accessible memory is considered reserved.
Bit Fields
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reserved

pincsel

RO 0x0

pinbsel

RO 0x0

csel

RO 0x0

bsel

RO 0x0

bootinfo Fields

Bit Name Description Access Reset
9:8 pincsel

Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are sampled upon deassertion of cold reset.

 RO 0x0
7:5 pinbsel

Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are sampled upon deassertion of cold reset.

 RO 0x0
4:3 csel

The clock select field specifies clock information for booting. The clock select encoding is a function of the CSEL value. The clock select field is read by the Boot ROM code on a cold or warm reset when booting from a flash device to get information about how to setup the HPS clocking to boot from the specified clock device. The encoding of the clock select field is specified by the enum associated with this field. The HPS CSEL pins value are sampled upon deassertion of cold reset.

Value Description
0x0 QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk divided by 4, NAND device operation is osc1_clk divided by 25
0x1 QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk divided by 1, NAND device operation is osc1_clk multiplied by 20/25
0x2 QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk divided by 2, NAND device operation is osc1_clk multiplied by 10/25
0x3 QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk divided by 4, NAND device operation is osc1_clk multiplied by 5/25
RO 0x0
2:0 bsel

The boot select field specifies the boot source. It is read by the Boot ROM code on a cold or warm reset to determine the boot source. The HPS BSEL pins value are sampled upon deassertion of cold reset.

Value Description
0x0 Reserved
0x1 FPGA (HPS2FPGA Bridge)
0x2 NAND Flash (1.8v)
0x3 NAND Flash (3.0v)
0x4 SD/MMC External Transceiver (1.8v)
0x5 SD/MMC Internal Transceiver (3.0v)
0x6 QSPI Flash (1.8v)
0x7 QSPI Flash (3.0v)
RO 0x0