Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - hdsken

Description

The CTRL register is used by software to control reset behavior.It includes fields for enable hardware handshake with other modules before warm reset.

Register Layout

Bits Access Reset Description
[0] RW 0x0 SDRAM Self-Refresh Enable
[1] RW 0x0 FPGA Manager Handshake Enable
[2] RW 0x0 FPGA Handshake Enable
[3] RW 0x0 ETR (Embedded Trace Router) Handshake Enable
[31:4] ??? Unknown UNDEFINED

Field : SDRAM Self-Refresh Enable - sdrselfrefen

This field controls whether the contents of SDRAM devices survive a hardware sequenced warm reset. If set to 1, the Reset Manager makes a request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before asserting warm reset signals. However, if SDRAM is already in warm reset, Handshake with SDRAM is not performed.

Field Access Macros:

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB   0
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB   0
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH   1
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK   0x00000001
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET   0x0
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : FPGA Manager Handshake Enable - fpgamgrhsen

Enables a handshake between the Reset Manager and FPGA Manager before a warm reset. The handshake is used to warn the FPGA Manager that a warm reset it coming so it can prepare for it. When the FPGA Manager receives a warm reset handshake, the FPGA Manager drives its output clock to a quiescent state to avoid glitches.

If set to 1, the Manager makes a request to the FPGA Managerbefore asserting warm reset signals. However if the FPGA Manager is already in warm reset, the handshake is skipped.

If set to 0, the handshake is skipped.

Field Access Macros:

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_LSB   1
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_MSB   1
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_WIDTH   1
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK   0x00000002
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_RESET   0x0
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET(value)   (((value) << 1) & 0x00000002)
 

Field : FPGA Handshake Enable - fpgahsen

This field controls whether to perform handshake with FPGA before asserting warm reset.

If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm reset signals. However if FPGA is already in warm reset state, the handshake is not performed.

If set to 0, the handshake is not performed

Field Access Macros:

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB   2
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB   2
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH   1
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK   0x00000004
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET   0x0
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value)   (((value) << 2) & 0x00000004)
 

Field : ETR (Embedded Trace Router) Handshake Enable - etrstallen

Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect.

Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.

Field Access Macros:

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB   3
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB   3
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH   1
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK   0x00000008
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET   0x0
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value)   (((value) << 3) & 0x00000008)
 

Data Structures

struct  ALT_RSTMGR_HDSKEN_s
 

Macros

#define ALT_RSTMGR_HDSKEN_RESET   0x00100000
 
#define ALT_RSTMGR_HDSKEN_OFST   0x10
 

Typedefs

typedef struct ALT_RSTMGR_HDSKEN_s ALT_RSTMGR_HDSKEN_t
 

Data Structure Documentation

struct ALT_RSTMGR_HDSKEN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_HDSKEN.

Data Fields
uint32_t sdrselfrefen: 1 SDRAM Self-Refresh Enable
uint32_t fpgamgrhsen: 1 FPGA Manager Handshake Enable
uint32_t fpgahsen: 1 FPGA Handshake Enable
uint32_t etrstallen: 1 ETR (Embedded Trace Router) Handshake Enable
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_HDSKEN_SDRSELFREFEN field value from a register.

#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_HDSKEN_SDRSELFREFEN register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_HDSKEN_FPGAMGRHSEN field value from a register.

#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_HDSKEN_FPGAMGRHSEN register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_HDSKEN_FPGAHSEN register field value.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKEN_FPGAHSEN register field.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_HDSKEN_FPGAHSEN field value from a register.

#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_HDSKEN_FPGAHSEN register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKEN_ETRSTALLEN register field.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_HDSKEN_ETRSTALLEN field value from a register.

#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_HDSKEN_ETRSTALLEN register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKEN_RESET   0x00100000

The reset value of the ALT_RSTMGR_HDSKEN register.

#define ALT_RSTMGR_HDSKEN_OFST   0x10

The byte offset of the ALT_RSTMGR_HDSKEN register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_HDSKEN.