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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS |
[1] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS |
[2] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS |
[3] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS |
[4] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN |
[5] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN |
[7:6] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : cfg_srf_zqcal_disable | |
Set to 1 to disable ZQ Calibration after self refresh Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_LSB 0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_MSB 0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET_MSK 0x00000001 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_CLR_MSK 0xfffffffe |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET(value) (((value) << 0) & 0x00000001) |
Field : cfg_mps_zqcal_disable | |
Set to 1 to disable ZQ Calibration after Maximum Power Saving exit Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_LSB 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_MSB 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET_MSK 0x00000002 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_CLR_MSK 0xfffffffd |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET(value) (((value) << 1) & 0x00000002) |
Field : cfg_mps_dqstrk_disable | |
Set to 1 to disable DQS Tracking after Maximum Power Saving exit Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_LSB 2 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_MSB 2 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET_MSK 0x00000004 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_CLR_MSK 0xfffffffb |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET(value) (((value) << 2) & 0x00000004) |
Field : cfg_sb_cg_disable | |
Set to 1 to disable mem_ck gating during self refresh and deep power down Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_LSB 3 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_MSB 3 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET_MSK 0x00000008 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_CLR_MSK 0xfffffff7 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET(value) (((value) << 3) & 0x00000008) |
Field : cfg_user_rfsh_en | |
Setting to 1 to enable user refresh Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_LSB 4 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_MSB 4 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010) |
Field : cfg_srf_autoexit_en | |
Setting to 1 to enable controller to exit Self Refresh when new command is detected Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020) |
Field : cfg_srf_entry_exit_block | |
Blocking arbiter from issuing cmds for the 4 cases, 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6) |
#define | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_SBCFG2_s |
Macros | |
#define | ALT_IO48_HMC_MMR_SBCFG2_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_SBCFG2_OFST 0x64 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_SBCFG2_s | ALT_IO48_HMC_MMR_SBCFG2_t |
struct ALT_IO48_HMC_MMR_SBCFG2_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_SBCFG2.
Data Fields | ||
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uint32_t | cfg_srf_zqcal_disable: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS |
uint32_t | cfg_mps_zqcal_disable: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS |
uint32_t | cfg_mps_dqstrk_disable: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS |
uint32_t | cfg_sb_cg_disable: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS |
uint32_t | cfg_user_rfsh_en: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN |
uint32_t | cfg_srf_autoexit_en: 1 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN |
uint32_t | cfg_srf_entry_exit_block: 2 | ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET_MSK 0x00000001 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET_MSK 0x00000002 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET_MSK 0x00000004 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET_MSK 0x00000008 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET | ( | value | ) | (((value) & 0x000000c0) >> 6) |
Extracts the ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET | ( | value | ) | (((value) << 6) & 0x000000c0) |
Produces a ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG2_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG2 register.
#define ALT_IO48_HMC_MMR_SBCFG2_OFST 0x64 |
The byte offset of the ALT_IO48_HMC_MMR_SBCFG2 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_SBCFG2_s ALT_IO48_HMC_MMR_SBCFG2_t |
The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG2.