Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Status Register - sr

Description

Reports FIFO transfer status, and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt.

Register Layout

Bits Access Reset Description
[0] R 0x0 SPI Busy Flag
[1] R 0x1 Transmit FIFO Not Full
[2] R 0x1 Transmit FIFO Empty
[3] R 0x0 Receive FIFO Not Empty
[4] R 0x0 Receive FIFO Full
[5] R 0x0 Transmission Error
[31:6] ??? 0x0 UNDEFINED

Field : SPI Busy Flag - busy

Reports the status of a serial transfer

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_BUSY_E_INACT 0x0 SPI Slave is inactive (idle or disabled)
ALT_SPIS_SR_BUSY_E_ACT 0x1 SPI Slave is actively transferring data

Field Access Macros:

#define ALT_SPIS_SR_BUSY_E_INACT   0x0
 
#define ALT_SPIS_SR_BUSY_E_ACT   0x1
 
#define ALT_SPIS_SR_BUSY_LSB   0
 
#define ALT_SPIS_SR_BUSY_MSB   0
 
#define ALT_SPIS_SR_BUSY_WIDTH   1
 
#define ALT_SPIS_SR_BUSY_SET_MSK   0x00000001
 
#define ALT_SPIS_SR_BUSY_CLR_MSK   0xfffffffe
 
#define ALT_SPIS_SR_BUSY_RESET   0x0
 
#define ALT_SPIS_SR_BUSY_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SPIS_SR_BUSY_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit FIFO Not Full - tfnf

Reports the status of the transmit FIFO.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_TFNF_E_FULL 0x0 Transmit FIFO is full
ALT_SPIS_SR_TFNF_E_NOTFULL 0x1 Transmit FIFO is not full

Field Access Macros:

#define ALT_SPIS_SR_TFNF_E_FULL   0x0
 
#define ALT_SPIS_SR_TFNF_E_NOTFULL   0x1
 
#define ALT_SPIS_SR_TFNF_LSB   1
 
#define ALT_SPIS_SR_TFNF_MSB   1
 
#define ALT_SPIS_SR_TFNF_WIDTH   1
 
#define ALT_SPIS_SR_TFNF_SET_MSK   0x00000002
 
#define ALT_SPIS_SR_TFNF_CLR_MSK   0xfffffffd
 
#define ALT_SPIS_SR_TFNF_RESET   0x1
 
#define ALT_SPIS_SR_TFNF_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SPIS_SR_TFNF_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Transmit FIFO Empty - tfe

Reports the status of transmit FIFO empty. This bit field does not request an interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_TFE_E_EMPTY 0x1 Transmit FIFO is empty
ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0 Transmit FIFO is not empty

Field Access Macros:

#define ALT_SPIS_SR_TFE_E_EMPTY   0x1
 
#define ALT_SPIS_SR_TFE_E_NOTEMPTY   0x0
 
#define ALT_SPIS_SR_TFE_LSB   2
 
#define ALT_SPIS_SR_TFE_MSB   2
 
#define ALT_SPIS_SR_TFE_WIDTH   1
 
#define ALT_SPIS_SR_TFE_SET_MSK   0x00000004
 
#define ALT_SPIS_SR_TFE_CLR_MSK   0xfffffffb
 
#define ALT_SPIS_SR_TFE_RESET   0x1
 
#define ALT_SPIS_SR_TFE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SPIS_SR_TFE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Receive FIFO Not Empty - rfne

Reports the status of receive FIFO empty.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_RFNE_E_EMPTY 0x0 Receive FIFO is empty
ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1 Receive FIFO is not empty

Field Access Macros:

#define ALT_SPIS_SR_RFNE_E_EMPTY   0x0
 
#define ALT_SPIS_SR_RFNE_E_NOTEMPTY   0x1
 
#define ALT_SPIS_SR_RFNE_LSB   3
 
#define ALT_SPIS_SR_RFNE_MSB   3
 
#define ALT_SPIS_SR_RFNE_WIDTH   1
 
#define ALT_SPIS_SR_RFNE_SET_MSK   0x00000008
 
#define ALT_SPIS_SR_RFNE_CLR_MSK   0xfffffff7
 
#define ALT_SPIS_SR_RFNE_RESET   0x0
 
#define ALT_SPIS_SR_RFNE_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SPIS_SR_RFNE_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Receive FIFO Full - rff

Reports the status of receive FIFO Full

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_RFF_E_NOTFULL 0x0 Receive FIFO is not full
ALT_SPIS_SR_RFF_E_FULL 0x1 Receive FIFO is full

Field Access Macros:

#define ALT_SPIS_SR_RFF_E_NOTFULL   0x0
 
#define ALT_SPIS_SR_RFF_E_FULL   0x1
 
#define ALT_SPIS_SR_RFF_LSB   4
 
#define ALT_SPIS_SR_RFF_MSB   4
 
#define ALT_SPIS_SR_RFF_WIDTH   1
 
#define ALT_SPIS_SR_RFF_SET_MSK   0x00000010
 
#define ALT_SPIS_SR_RFF_CLR_MSK   0xffffffef
 
#define ALT_SPIS_SR_RFF_RESET   0x0
 
#define ALT_SPIS_SR_RFF_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SPIS_SR_RFF_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Transmission Error - txe

Data from the previous transmission is resent on the txd line. This bit is cleared when read.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_SR_TXE_E_NOERROR 0x0 No Error
ALT_SPIS_SR_TXE_E_ERROR 0x1 Transmission Error

Field Access Macros:

#define ALT_SPIS_SR_TXE_E_NOERROR   0x0
 
#define ALT_SPIS_SR_TXE_E_ERROR   0x1
 
#define ALT_SPIS_SR_TXE_LSB   5
 
#define ALT_SPIS_SR_TXE_MSB   5
 
#define ALT_SPIS_SR_TXE_WIDTH   1
 
#define ALT_SPIS_SR_TXE_SET_MSK   0x00000020
 
#define ALT_SPIS_SR_TXE_CLR_MSK   0xffffffdf
 
#define ALT_SPIS_SR_TXE_RESET   0x0
 
#define ALT_SPIS_SR_TXE_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SPIS_SR_TXE_SET(value)   (((value) << 5) & 0x00000020)
 

Data Structures

struct  ALT_SPIS_SR_s
 

Macros

#define ALT_SPIS_SR_OFST   0x28
 
#define ALT_SPIS_SR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
 

Typedefs

typedef struct ALT_SPIS_SR_s ALT_SPIS_SR_t
 

Data Structure Documentation

struct ALT_SPIS_SR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SPIS_SR.

Data Fields
const uint32_t busy: 1 SPI Busy Flag
const uint32_t tfnf: 1 Transmit FIFO Not Full
const uint32_t tfe: 1 Transmit FIFO Empty
const uint32_t rfne: 1 Receive FIFO Not Empty
const uint32_t rff: 1 Receive FIFO Full
const uint32_t txe: 1 Transmission Error
uint32_t __pad0__: 26 UNDEFINED

Macro Definitions

#define ALT_SPIS_SR_BUSY_E_INACT   0x0

Enumerated value for register field ALT_SPIS_SR_BUSY

SPI Slave is inactive (idle or disabled)

#define ALT_SPIS_SR_BUSY_E_ACT   0x1

Enumerated value for register field ALT_SPIS_SR_BUSY

SPI Slave is actively transferring data

#define ALT_SPIS_SR_BUSY_LSB   0

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_BUSY register field.

#define ALT_SPIS_SR_BUSY_MSB   0

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_BUSY register field.

#define ALT_SPIS_SR_BUSY_WIDTH   1

The width in bits of the ALT_SPIS_SR_BUSY register field.

#define ALT_SPIS_SR_BUSY_SET_MSK   0x00000001

The mask used to set the ALT_SPIS_SR_BUSY register field value.

#define ALT_SPIS_SR_BUSY_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SPIS_SR_BUSY register field value.

#define ALT_SPIS_SR_BUSY_RESET   0x0

The reset value of the ALT_SPIS_SR_BUSY register field.

#define ALT_SPIS_SR_BUSY_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SPIS_SR_BUSY field value from a register.

#define ALT_SPIS_SR_BUSY_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SPIS_SR_BUSY register field value suitable for setting the register.

#define ALT_SPIS_SR_TFNF_E_FULL   0x0

Enumerated value for register field ALT_SPIS_SR_TFNF

Transmit FIFO is full

#define ALT_SPIS_SR_TFNF_E_NOTFULL   0x1

Enumerated value for register field ALT_SPIS_SR_TFNF

Transmit FIFO is not full

#define ALT_SPIS_SR_TFNF_LSB   1

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFNF register field.

#define ALT_SPIS_SR_TFNF_MSB   1

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFNF register field.

#define ALT_SPIS_SR_TFNF_WIDTH   1

The width in bits of the ALT_SPIS_SR_TFNF register field.

#define ALT_SPIS_SR_TFNF_SET_MSK   0x00000002

The mask used to set the ALT_SPIS_SR_TFNF register field value.

#define ALT_SPIS_SR_TFNF_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SPIS_SR_TFNF register field value.

#define ALT_SPIS_SR_TFNF_RESET   0x1

The reset value of the ALT_SPIS_SR_TFNF register field.

#define ALT_SPIS_SR_TFNF_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SPIS_SR_TFNF field value from a register.

#define ALT_SPIS_SR_TFNF_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SPIS_SR_TFNF register field value suitable for setting the register.

#define ALT_SPIS_SR_TFE_E_EMPTY   0x1

Enumerated value for register field ALT_SPIS_SR_TFE

Transmit FIFO is empty

#define ALT_SPIS_SR_TFE_E_NOTEMPTY   0x0

Enumerated value for register field ALT_SPIS_SR_TFE

Transmit FIFO is not empty

#define ALT_SPIS_SR_TFE_LSB   2

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TFE register field.

#define ALT_SPIS_SR_TFE_MSB   2

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TFE register field.

#define ALT_SPIS_SR_TFE_WIDTH   1

The width in bits of the ALT_SPIS_SR_TFE register field.

#define ALT_SPIS_SR_TFE_SET_MSK   0x00000004

The mask used to set the ALT_SPIS_SR_TFE register field value.

#define ALT_SPIS_SR_TFE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SPIS_SR_TFE register field value.

#define ALT_SPIS_SR_TFE_RESET   0x1

The reset value of the ALT_SPIS_SR_TFE register field.

#define ALT_SPIS_SR_TFE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SPIS_SR_TFE field value from a register.

#define ALT_SPIS_SR_TFE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SPIS_SR_TFE register field value suitable for setting the register.

#define ALT_SPIS_SR_RFNE_E_EMPTY   0x0

Enumerated value for register field ALT_SPIS_SR_RFNE

Receive FIFO is empty

#define ALT_SPIS_SR_RFNE_E_NOTEMPTY   0x1

Enumerated value for register field ALT_SPIS_SR_RFNE

Receive FIFO is not empty

#define ALT_SPIS_SR_RFNE_LSB   3

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFNE register field.

#define ALT_SPIS_SR_RFNE_MSB   3

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFNE register field.

#define ALT_SPIS_SR_RFNE_WIDTH   1

The width in bits of the ALT_SPIS_SR_RFNE register field.

#define ALT_SPIS_SR_RFNE_SET_MSK   0x00000008

The mask used to set the ALT_SPIS_SR_RFNE register field value.

#define ALT_SPIS_SR_RFNE_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SPIS_SR_RFNE register field value.

#define ALT_SPIS_SR_RFNE_RESET   0x0

The reset value of the ALT_SPIS_SR_RFNE register field.

#define ALT_SPIS_SR_RFNE_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SPIS_SR_RFNE field value from a register.

#define ALT_SPIS_SR_RFNE_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SPIS_SR_RFNE register field value suitable for setting the register.

#define ALT_SPIS_SR_RFF_E_NOTFULL   0x0

Enumerated value for register field ALT_SPIS_SR_RFF

Receive FIFO is not full

#define ALT_SPIS_SR_RFF_E_FULL   0x1

Enumerated value for register field ALT_SPIS_SR_RFF

Receive FIFO is full

#define ALT_SPIS_SR_RFF_LSB   4

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_RFF register field.

#define ALT_SPIS_SR_RFF_MSB   4

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_RFF register field.

#define ALT_SPIS_SR_RFF_WIDTH   1

The width in bits of the ALT_SPIS_SR_RFF register field.

#define ALT_SPIS_SR_RFF_SET_MSK   0x00000010

The mask used to set the ALT_SPIS_SR_RFF register field value.

#define ALT_SPIS_SR_RFF_CLR_MSK   0xffffffef

The mask used to clear the ALT_SPIS_SR_RFF register field value.

#define ALT_SPIS_SR_RFF_RESET   0x0

The reset value of the ALT_SPIS_SR_RFF register field.

#define ALT_SPIS_SR_RFF_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SPIS_SR_RFF field value from a register.

#define ALT_SPIS_SR_RFF_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SPIS_SR_RFF register field value suitable for setting the register.

#define ALT_SPIS_SR_TXE_E_NOERROR   0x0

Enumerated value for register field ALT_SPIS_SR_TXE

No Error

#define ALT_SPIS_SR_TXE_E_ERROR   0x1

Enumerated value for register field ALT_SPIS_SR_TXE

Transmission Error

#define ALT_SPIS_SR_TXE_LSB   5

The Least Significant Bit (LSB) position of the ALT_SPIS_SR_TXE register field.

#define ALT_SPIS_SR_TXE_MSB   5

The Most Significant Bit (MSB) position of the ALT_SPIS_SR_TXE register field.

#define ALT_SPIS_SR_TXE_WIDTH   1

The width in bits of the ALT_SPIS_SR_TXE register field.

#define ALT_SPIS_SR_TXE_SET_MSK   0x00000020

The mask used to set the ALT_SPIS_SR_TXE register field value.

#define ALT_SPIS_SR_TXE_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SPIS_SR_TXE register field value.

#define ALT_SPIS_SR_TXE_RESET   0x0

The reset value of the ALT_SPIS_SR_TXE register field.

#define ALT_SPIS_SR_TXE_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SPIS_SR_TXE field value from a register.

#define ALT_SPIS_SR_TXE_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SPIS_SR_TXE register field value suitable for setting the register.

#define ALT_SPIS_SR_OFST   0x28

The byte offset of the ALT_SPIS_SR register from the beginning of the component.

#define ALT_SPIS_SR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))

The address of the ALT_SPIS_SR register.

Typedef Documentation

typedef struct ALT_SPIS_SR_s ALT_SPIS_SR_t

The typedef declaration for register ALT_SPIS_SR.