Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ic_con

Description

This register can be written only when the I2C is disabled, which corresponds to the Bit [0] of the Enable Register being set to 0. Writes at other times have no effect.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Master Enable
[2:1] RW 0x2 Master Speed Control
[3] RW 0x1 Slave Address Size
[4] RW 0x1 Master Address Size
[5] RW 0x1 Restart Enable
[6] RW 0x1 Slave Disable
[31:7] ??? 0x0 UNDEFINED

Field : Master Enable - master_mode

This bit controls whether the i2c master is enabled.

NOTE: Software should ensure that if this bit is written with '1', then bit 6 should also be written with a '1'.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_MST_MOD_E_DIS 0x0 master disabled
ALT_I2C_CON_MST_MOD_E_EN 0x1 master enabled

Field Access Macros:

#define ALT_I2C_CON_MST_MOD_E_DIS   0x0
 
#define ALT_I2C_CON_MST_MOD_E_EN   0x1
 
#define ALT_I2C_CON_MST_MOD_LSB   0
 
#define ALT_I2C_CON_MST_MOD_MSB   0
 
#define ALT_I2C_CON_MST_MOD_WIDTH   1
 
#define ALT_I2C_CON_MST_MOD_SET_MSK   0x00000001
 
#define ALT_I2C_CON_MST_MOD_CLR_MSK   0xfffffffe
 
#define ALT_I2C_CON_MST_MOD_RESET   0x1
 
#define ALT_I2C_CON_MST_MOD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_I2C_CON_MST_MOD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Master Speed Control - speed

These bits control at which speed the I2C operates, its setting is relevant only if one is operating the I2C in master mode. Hardware protects against illegal values being programmed by software. This field should be programmed only with standard or fast speed.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_SPEED_E_STANDARD 0x1 standard mode (100 kbit/s)
ALT_I2C_CON_SPEED_E_FAST 0x2 fast mode (400 kbit/s)

Field Access Macros:

#define ALT_I2C_CON_SPEED_E_STANDARD   0x1
 
#define ALT_I2C_CON_SPEED_E_FAST   0x2
 
#define ALT_I2C_CON_SPEED_LSB   1
 
#define ALT_I2C_CON_SPEED_MSB   2
 
#define ALT_I2C_CON_SPEED_WIDTH   2
 
#define ALT_I2C_CON_SPEED_SET_MSK   0x00000006
 
#define ALT_I2C_CON_SPEED_CLR_MSK   0xfffffff9
 
#define ALT_I2C_CON_SPEED_RESET   0x2
 
#define ALT_I2C_CON_SPEED_GET(value)   (((value) & 0x00000006) >> 1)
 
#define ALT_I2C_CON_SPEED_SET(value)   (((value) << 1) & 0x00000006)
 

Field : Slave Address Size - ic_10bitaddr_slave

When acting as a slave, this bit controls whether the I2C responds to 7- or 10-bit addresses. In 7-bit addressing, only the lower 7 bits of the Slave Address Register are compared. The I2C responds will only respond to 10-bit addressing transfers that match the full 10 bits of the Slave Address register.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 7-bit addressing
ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 10-bit addressing

Field Access Macros:

#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT   0x0
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT   0x1
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB   3
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB   3
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH   1
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK   0x00000008
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK   0xfffffff7
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET   0x1
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Master Address Size - ic_10bitaddr_master

This bit controls whether the I2C starts its transfers in 7-or 10-bit addressing mode when acting as a master.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 7-bit addressing
ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 10-bit addressing

Field Access Macros:

#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT   0x0
 
#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT   0x1
 
#define ALT_I2C_CON_IC_10BITADDR_MST_LSB   4
 
#define ALT_I2C_CON_IC_10BITADDR_MST_MSB   4
 
#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH   1
 
#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK   0x00000010
 
#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK   0xffffffef
 
#define ALT_I2C_CON_IC_10BITADDR_MST_RESET   0x1
 
#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Restart Enable - ic_restart_en

Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several I2C operations. When RESTART is disabled, the master is prohibited from performing the following functions

  • Changing direction within a transfer (split),
  • Sending a START BYTE,
  • High-speed mode operation,
  • Combined format transfers in 7-bit addressing modes,
  • Read operation with a 10-bit address,
  • Sending multiple bytes per transfer,

By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple I2C transfers. If the above operations are performed, it will result in setting bit [6](tx_abort) of the Raw Interrupt Status Register.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 restart master disable
ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 restart master enable

Field Access Macros:

#define ALT_I2C_CON_IC_RESTART_EN_E_DIS   0x0
 
#define ALT_I2C_CON_IC_RESTART_EN_E_EN   0x1
 
#define ALT_I2C_CON_IC_RESTART_EN_LSB   5
 
#define ALT_I2C_CON_IC_RESTART_EN_MSB   5
 
#define ALT_I2C_CON_IC_RESTART_EN_WIDTH   1
 
#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK   0x00000020
 
#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK   0xffffffdf
 
#define ALT_I2C_CON_IC_RESTART_EN_RESET   0x1
 
#define ALT_I2C_CON_IC_RESTART_EN_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_I2C_CON_IC_RESTART_EN_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Slave Disable - ic_slave_disable

This bit controls whether I2C has its slave disabled. The slave will be disabled, after reset.

NOTE: Software should ensure that if this bit is written with 0, then bit [0] of this register should also be written with a 0.

Field Enumeration Values:

Enum Value Description
ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 slave disable
ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 slave enable

Field Access Macros:

#define ALT_I2C_CON_IC_SLV_DIS_E_DIS   0x1
 
#define ALT_I2C_CON_IC_SLV_DIS_E_EN   0x0
 
#define ALT_I2C_CON_IC_SLV_DIS_LSB   6
 
#define ALT_I2C_CON_IC_SLV_DIS_MSB   6
 
#define ALT_I2C_CON_IC_SLV_DIS_WIDTH   1
 
#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK   0x00000040
 
#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK   0xffffffbf
 
#define ALT_I2C_CON_IC_SLV_DIS_RESET   0x1
 
#define ALT_I2C_CON_IC_SLV_DIS_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_I2C_CON_IC_SLV_DIS_SET(value)   (((value) << 6) & 0x00000040)
 

Data Structures

struct  ALT_I2C_CON_s
 

Macros

#define ALT_I2C_CON_OFST   0x0
 
#define ALT_I2C_CON_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
 

Typedefs

typedef struct ALT_I2C_CON_s ALT_I2C_CON_t
 

Data Structure Documentation

struct ALT_I2C_CON_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_I2C_CON.

Data Fields
uint32_t master_mode: 1 Master Enable
uint32_t speed: 2 Master Speed Control
uint32_t ic_10bitaddr_slave: 1 Slave Address Size
uint32_t ic_10bitaddr_master: 1 Master Address Size
uint32_t ic_restart_en: 1 Restart Enable
uint32_t ic_slave_disable: 1 Slave Disable
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_I2C_CON_MST_MOD_E_DIS   0x0

Enumerated value for register field ALT_I2C_CON_MST_MOD

master disabled

#define ALT_I2C_CON_MST_MOD_E_EN   0x1

Enumerated value for register field ALT_I2C_CON_MST_MOD

master enabled

#define ALT_I2C_CON_MST_MOD_LSB   0

The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field.

#define ALT_I2C_CON_MST_MOD_MSB   0

The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field.

#define ALT_I2C_CON_MST_MOD_WIDTH   1

The width in bits of the ALT_I2C_CON_MST_MOD register field.

#define ALT_I2C_CON_MST_MOD_SET_MSK   0x00000001

The mask used to set the ALT_I2C_CON_MST_MOD register field value.

#define ALT_I2C_CON_MST_MOD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_I2C_CON_MST_MOD register field value.

#define ALT_I2C_CON_MST_MOD_RESET   0x1

The reset value of the ALT_I2C_CON_MST_MOD register field.

#define ALT_I2C_CON_MST_MOD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_I2C_CON_MST_MOD field value from a register.

#define ALT_I2C_CON_MST_MOD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register.

#define ALT_I2C_CON_SPEED_E_STANDARD   0x1

Enumerated value for register field ALT_I2C_CON_SPEED

standard mode (100 kbit/s)

#define ALT_I2C_CON_SPEED_E_FAST   0x2

Enumerated value for register field ALT_I2C_CON_SPEED

fast mode (400 kbit/s)

#define ALT_I2C_CON_SPEED_LSB   1

The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field.

#define ALT_I2C_CON_SPEED_MSB   2

The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field.

#define ALT_I2C_CON_SPEED_WIDTH   2

The width in bits of the ALT_I2C_CON_SPEED register field.

#define ALT_I2C_CON_SPEED_SET_MSK   0x00000006

The mask used to set the ALT_I2C_CON_SPEED register field value.

#define ALT_I2C_CON_SPEED_CLR_MSK   0xfffffff9

The mask used to clear the ALT_I2C_CON_SPEED register field value.

#define ALT_I2C_CON_SPEED_RESET   0x2

The reset value of the ALT_I2C_CON_SPEED register field.

#define ALT_I2C_CON_SPEED_GET (   value)    (((value) & 0x00000006) >> 1)

Extracts the ALT_I2C_CON_SPEED field value from a register.

#define ALT_I2C_CON_SPEED_SET (   value)    (((value) << 1) & 0x00000006)

Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register.

#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT   0x0

Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV

7-bit addressing

#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT   0x1

Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV

10-bit addressing

#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB   3

The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field.

#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB   3

The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field.

#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH   1

The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field.

#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK   0x00000008

The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value.

#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK   0xfffffff7

The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value.

#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET   0x1

The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field.

#define ALT_I2C_CON_IC_10BITADDR_SLV_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register.

#define ALT_I2C_CON_IC_10BITADDR_SLV_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register.

#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT   0x0

Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST

7-bit addressing

#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT   0x1

Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST

10-bit addressing

#define ALT_I2C_CON_IC_10BITADDR_MST_LSB   4

The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field.

#define ALT_I2C_CON_IC_10BITADDR_MST_MSB   4

The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field.

#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH   1

The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field.

#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK   0x00000010

The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value.

#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK   0xffffffef

The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value.

#define ALT_I2C_CON_IC_10BITADDR_MST_RESET   0x1

The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field.

#define ALT_I2C_CON_IC_10BITADDR_MST_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register.

#define ALT_I2C_CON_IC_10BITADDR_MST_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register.

#define ALT_I2C_CON_IC_RESTART_EN_E_DIS   0x0

Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN

restart master disable

#define ALT_I2C_CON_IC_RESTART_EN_E_EN   0x1

Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN

restart master enable

#define ALT_I2C_CON_IC_RESTART_EN_LSB   5

The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field.

#define ALT_I2C_CON_IC_RESTART_EN_MSB   5

The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field.

#define ALT_I2C_CON_IC_RESTART_EN_WIDTH   1

The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field.

#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK   0x00000020

The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value.

#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK   0xffffffdf

The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value.

#define ALT_I2C_CON_IC_RESTART_EN_RESET   0x1

The reset value of the ALT_I2C_CON_IC_RESTART_EN register field.

#define ALT_I2C_CON_IC_RESTART_EN_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register.

#define ALT_I2C_CON_IC_RESTART_EN_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register.

#define ALT_I2C_CON_IC_SLV_DIS_E_DIS   0x1

Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS

slave disable

#define ALT_I2C_CON_IC_SLV_DIS_E_EN   0x0

Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS

slave enable

#define ALT_I2C_CON_IC_SLV_DIS_LSB   6

The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field.

#define ALT_I2C_CON_IC_SLV_DIS_MSB   6

The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field.

#define ALT_I2C_CON_IC_SLV_DIS_WIDTH   1

The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field.

#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK   0x00000040

The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value.

#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK   0xffffffbf

The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value.

#define ALT_I2C_CON_IC_SLV_DIS_RESET   0x1

The reset value of the ALT_I2C_CON_IC_SLV_DIS register field.

#define ALT_I2C_CON_IC_SLV_DIS_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register.

#define ALT_I2C_CON_IC_SLV_DIS_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register.

#define ALT_I2C_CON_OFST   0x0

The byte offset of the ALT_I2C_CON register from the beginning of the component.

#define ALT_I2C_CON_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))

The address of the ALT_I2C_CON register.

Typedef Documentation

typedef struct ALT_I2C_CON_s ALT_I2C_CON_t

The typedef declaration for register ALT_I2C_CON.