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alt_nand.h
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32 
35 #ifndef __ALTERA_ALT_NAND_H__
36 #define __ALTERA_ALT_NAND_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
86 #define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
87 
88 #define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
89 
90 #define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
91 
92 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
93 
94 #define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
95 
96 #define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
97 
98 #define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
99 
100 #define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
101 
112 #define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
113 
114 #define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
115 
116 #define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
117 
118 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
119 
120 #define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
121 
122 #define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
123 
124 #define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
125 
126 #define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
127 
138 #define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
139 
140 #define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
141 
142 #define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
143 
144 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
145 
146 #define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
147 
148 #define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
149 
150 #define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
151 
152 #define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
153 
164 #define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
165 
166 #define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
167 
168 #define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
169 
170 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
171 
172 #define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
173 
174 #define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
175 
176 #define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
177 
178 #define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
179 
180 #ifndef __ASSEMBLY__
181 
192 {
193  uint32_t bank0 : 1;
194  uint32_t bank1 : 1;
195  uint32_t bank2 : 1;
196  uint32_t bank3 : 1;
197  uint32_t : 28;
198 };
199 
202 #endif /* __ASSEMBLY__ */
203 
205 #define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
206 
232 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
233 
234 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
235 
236 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
237 
238 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
239 
240 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
241 
242 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
243 
244 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
245 
246 #define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
247 
248 #ifndef __ASSEMBLY__
249 
260 {
261  uint32_t flag : 1;
262  uint32_t : 31;
263 };
264 
267 #endif /* __ASSEMBLY__ */
268 
270 #define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
271 
300 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
301 
302 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
303 
304 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
305 
306 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
307 
308 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
309 
310 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
311 
312 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
313 
314 #define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
315 
316 #ifndef __ASSEMBLY__
317 
328 {
329  uint32_t value : 16;
330  uint32_t : 16;
331 };
332 
335 #endif /* __ASSEMBLY__ */
336 
338 #define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
339 
369 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
370 
371 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
372 
373 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
374 
375 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
376 
377 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
378 
379 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f4
380 
381 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
382 
383 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
384 
385 #ifndef __ASSEMBLY__
386 
397 {
398  uint32_t value : 16;
399  uint32_t : 16;
400 };
401 
404 #endif /* __ASSEMBLY__ */
405 
407 #define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
408 
438 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
439 
440 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
441 
442 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
443 
444 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
445 
446 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
447 
448 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f4
449 
450 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
451 
452 #define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
453 
454 #ifndef __ASSEMBLY__
455 
466 {
467  uint32_t value : 16;
468  uint32_t : 16;
469 };
470 
473 #endif /* __ASSEMBLY__ */
474 
476 #define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
477 
502 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
503 
504 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
505 
506 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
507 
508 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
509 
510 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
511 
512 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
513 
514 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
515 
516 #define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
517 
518 #ifndef __ASSEMBLY__
519 
530 {
531  uint32_t value : 16;
532  uint32_t : 16;
533 };
534 
537 #endif /* __ASSEMBLY__ */
538 
540 #define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
541 
569 #define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
570 
571 #define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
572 
573 #define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
574 
575 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
576 
577 #define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
578 
579 #define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
580 
581 #define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
582 
583 #define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
584 
596 #define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
597 
598 #define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
599 
600 #define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
601 
602 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
603 
604 #define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
605 
606 #define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
607 
608 #define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
609 
610 #define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
611 
623 #define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
624 
625 #define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
626 
627 #define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
628 
629 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
630 
631 #define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
632 
633 #define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
634 
635 #define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
636 
637 #define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
638 
650 #define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
651 
652 #define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
653 
654 #define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
655 
656 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
657 
658 #define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
659 
660 #define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
661 
662 #define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
663 
664 #define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
665 
666 #ifndef __ASSEMBLY__
667 
678 {
679  uint32_t bank0 : 1;
680  uint32_t bank1 : 1;
681  uint32_t bank2 : 1;
682  uint32_t bank3 : 1;
683  uint32_t : 28;
684 };
685 
688 #endif /* __ASSEMBLY__ */
689 
691 #define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
692 
717 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
718 
719 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
720 
721 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
722 
723 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
724 
725 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
726 
727 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
728 
729 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
730 
731 #define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
732 
733 #ifndef __ASSEMBLY__
734 
745 {
746  uint32_t flag : 1;
747  uint32_t : 31;
748 };
749 
752 #endif /* __ASSEMBLY__ */
753 
755 #define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
756 
785 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
786 
787 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
788 
789 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
790 
791 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
792 
793 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
794 
795 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
796 
797 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
798 
799 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
800 
801 #ifndef __ASSEMBLY__
802 
813 {
814  uint32_t flag : 1;
815  uint32_t : 31;
816 };
817 
820 #endif /* __ASSEMBLY__ */
821 
823 #define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
824 
847 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
848 
849 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
850 
851 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
852 
853 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
854 
855 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
856 
857 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
858 
859 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
860 
861 #define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
862 
863 #ifndef __ASSEMBLY__
864 
875 {
876  uint32_t flag : 1;
877  uint32_t : 31;
878 };
879 
882 #endif /* __ASSEMBLY__ */
883 
885 #define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
886 
909 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
910 
911 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
912 
913 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
914 
915 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
916 
917 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
918 
919 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
920 
921 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
922 
923 #define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
924 
925 #ifndef __ASSEMBLY__
926 
937 {
938  uint32_t flag : 1;
939  uint32_t : 31;
940 };
941 
944 #endif /* __ASSEMBLY__ */
945 
947 #define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
948 
971 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
972 
973 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
974 
975 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
976 
977 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
978 
979 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
980 
981 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
982 
983 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
984 
985 #define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
986 
987 #ifndef __ASSEMBLY__
988 
999 {
1000  uint32_t flag : 1;
1001  uint32_t : 31;
1002 };
1003 
1006 #endif /* __ASSEMBLY__ */
1007 
1009 #define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1010 
1035 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1036 
1037 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1038 
1039 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1040 
1041 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1042 
1043 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1044 
1045 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1046 
1047 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1048 
1049 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1050 
1065 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1066 
1067 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1068 
1069 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1070 
1071 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1072 
1073 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1074 
1075 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1076 
1077 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1078 
1079 #define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1080 
1081 #ifndef __ASSEMBLY__
1082 
1093 {
1094  uint32_t prefetch_en : 1;
1095  uint32_t : 3;
1096  uint32_t prefetch_burst_length : 12;
1097  uint32_t : 16;
1098 };
1099 
1102 #endif /* __ASSEMBLY__ */
1103 
1105 #define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1106 
1130 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1131 
1132 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1133 
1134 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1135 
1136 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1137 
1138 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1139 
1140 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1141 
1142 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1143 
1144 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1145 
1146 #ifndef __ASSEMBLY__
1147 
1158 {
1159  uint32_t flag : 1;
1160  uint32_t : 31;
1161 };
1162 
1165 #endif /* __ASSEMBLY__ */
1166 
1168 #define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1169 
1196 #define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1197 
1198 #define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1199 
1200 #define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1201 
1202 #define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1203 
1204 #define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1205 
1206 #define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1207 
1208 #define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1209 
1210 #define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1211 
1212 #ifndef __ASSEMBLY__
1213 
1224 {
1225  uint32_t flag : 1;
1226  uint32_t : 31;
1227 };
1228 
1231 #endif /* __ASSEMBLY__ */
1232 
1234 #define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1235 
1262 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1263 
1264 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1265 
1266 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1267 
1268 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1269 
1270 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1271 
1272 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1273 
1274 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1275 
1276 #define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1277 
1287 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1288 
1289 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1290 
1291 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1292 
1293 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1294 
1295 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1296 
1297 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1298 
1299 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1300 
1301 #define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1302 
1312 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1313 
1314 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1315 
1316 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1317 
1318 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1319 
1320 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1321 
1322 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1323 
1324 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1325 
1326 #define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1327 
1328 #ifndef __ASSEMBLY__
1329 
1340 {
1341  uint32_t flag : 1;
1342  uint32_t : 3;
1343  uint32_t timeout_disable : 1;
1344  uint32_t : 3;
1345  uint32_t error_rpt_disable : 1;
1346  uint32_t : 23;
1347 };
1348 
1351 #endif /* __ASSEMBLY__ */
1352 
1354 #define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1355 
1381 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1382 
1383 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1384 
1385 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1386 
1387 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1388 
1389 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1390 
1391 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1392 
1393 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1394 
1395 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1396 
1407 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1408 
1409 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1410 
1411 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1412 
1413 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1414 
1415 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1416 
1417 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1418 
1419 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1420 
1421 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1422 
1423 #ifndef __ASSEMBLY__
1424 
1435 {
1436  uint32_t we_2_re : 6;
1437  uint32_t : 2;
1438  uint32_t twhr2 : 6;
1439  uint32_t : 18;
1440 };
1441 
1444 #endif /* __ASSEMBLY__ */
1445 
1447 #define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1448 
1474 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1475 
1476 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5
1477 
1478 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6
1479 
1480 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f
1481 
1482 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0
1483 
1484 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1485 
1486 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000003f) >> 0)
1487 
1488 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000003f)
1489 
1501 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1502 
1503 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1504 
1505 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1506 
1507 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1508 
1509 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1510 
1511 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1512 
1513 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1514 
1515 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1516 
1517 #ifndef __ASSEMBLY__
1518 
1529 {
1530  uint32_t addr_2_data : 6;
1531  uint32_t : 2;
1532  uint32_t tcwaw : 6;
1533  uint32_t : 18;
1534 };
1535 
1538 #endif /* __ASSEMBLY__ */
1539 
1541 #define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1542 
1568 #define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1569 
1570 #define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1571 
1572 #define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1573 
1574 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1575 
1576 #define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1577 
1578 #define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1579 
1580 #define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1581 
1582 #define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1583 
1584 #ifndef __ASSEMBLY__
1585 
1596 {
1597  uint32_t value : 6;
1598  uint32_t : 26;
1599 };
1600 
1603 #endif /* __ASSEMBLY__ */
1604 
1606 #define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1607 
1632 #define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1633 
1634 #define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1635 
1636 #define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1637 
1638 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1639 
1640 #define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1641 
1642 #define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1643 
1644 #define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1645 
1646 #define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1647 
1648 #ifndef __ASSEMBLY__
1649 
1660 {
1661  uint32_t value : 4;
1662  uint32_t : 28;
1663 };
1664 
1667 #endif /* __ASSEMBLY__ */
1668 
1670 #define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1671 
1699 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1700 
1701 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1702 
1703 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1704 
1705 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1706 
1707 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1708 
1709 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1710 
1711 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1712 
1713 #define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1714 
1715 #ifndef __ASSEMBLY__
1716 
1727 {
1728  uint32_t value : 3;
1729  uint32_t : 29;
1730 };
1731 
1734 #endif /* __ASSEMBLY__ */
1735 
1737 #define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1738 
1764 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1765 
1766 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1767 
1768 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1769 
1770 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1771 
1772 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1773 
1774 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1775 
1776 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1777 
1778 #define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1779 
1780 #ifndef __ASSEMBLY__
1781 
1792 {
1793  uint32_t value : 16;
1794  uint32_t : 16;
1795 };
1796 
1799 #endif /* __ASSEMBLY__ */
1800 
1802 #define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1803 
1829 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1830 
1831 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1832 
1833 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1834 
1835 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1836 
1837 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1838 
1839 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1840 
1841 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
1842 
1843 #define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
1844 
1845 #ifndef __ASSEMBLY__
1846 
1857 {
1858  uint32_t value : 2;
1859  uint32_t : 30;
1860 };
1861 
1864 #endif /* __ASSEMBLY__ */
1865 
1867 #define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
1868 
1894 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
1895 
1896 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
1897 
1898 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
1899 
1900 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1901 
1902 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1903 
1904 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
1905 
1906 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1907 
1908 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1909 
1910 #ifndef __ASSEMBLY__
1911 
1922 {
1923  uint32_t value : 16;
1924  uint32_t : 16;
1925 };
1926 
1929 #endif /* __ASSEMBLY__ */
1930 
1932 #define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
1933 
1959 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
1960 
1961 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
1962 
1963 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
1964 
1965 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
1966 
1967 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
1968 
1969 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
1970 
1971 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1972 
1973 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1974 
1975 #ifndef __ASSEMBLY__
1976 
1987 {
1988  uint32_t value : 16;
1989  uint32_t : 16;
1990 };
1991 
1994 #endif /* __ASSEMBLY__ */
1995 
1997 #define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
1998 
2023 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2024 
2025 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2026 
2027 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2028 
2029 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2030 
2031 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2032 
2033 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2034 
2035 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2036 
2037 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2038 
2039 #ifndef __ASSEMBLY__
2040 
2051 {
2052  uint32_t flag : 1;
2053  uint32_t : 31;
2054 };
2055 
2058 #endif /* __ASSEMBLY__ */
2059 
2061 #define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2062 
2088 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2089 
2090 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2091 
2092 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2093 
2094 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2095 
2096 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2097 
2098 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2099 
2100 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2101 
2102 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2103 
2104 #ifndef __ASSEMBLY__
2105 
2116 {
2117  uint32_t flag : 1;
2118  uint32_t : 31;
2119 };
2120 
2123 #endif /* __ASSEMBLY__ */
2124 
2126 #define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2127 
2152 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2153 
2154 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2155 
2156 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2157 
2158 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2159 
2160 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2161 
2162 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2163 
2164 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2165 
2166 #define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2167 
2168 #ifndef __ASSEMBLY__
2169 
2180 {
2181  uint32_t value : 8;
2182  uint32_t : 24;
2183 };
2184 
2187 #endif /* __ASSEMBLY__ */
2188 
2190 #define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2191 
2246 #define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2247 
2248 #define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2249 
2250 #define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2251 
2252 #define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2253 
2254 #define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2255 
2256 #define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2257 
2258 #define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2259 
2260 #define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2261 
2262 #ifndef __ASSEMBLY__
2263 
2274 {
2275  uint32_t value : 4;
2276  uint32_t : 28;
2277 };
2278 
2281 #endif /* __ASSEMBLY__ */
2282 
2284 #define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2285 
2326 #define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2327 
2328 #define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2329 
2330 #define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2331 
2332 #define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2333 
2334 #define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2335 
2336 #define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2337 
2338 #define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2339 
2340 #define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2341 
2342 #ifndef __ASSEMBLY__
2343 
2354 {
2355  uint32_t value : 4;
2356  uint32_t : 28;
2357 };
2358 
2361 #endif /* __ASSEMBLY__ */
2362 
2364 #define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2365 
2406 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2407 
2408 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2409 
2410 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2411 
2412 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2413 
2414 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2415 
2416 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2417 
2418 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2419 
2420 #define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2421 
2422 #ifndef __ASSEMBLY__
2423 
2434 {
2435  uint32_t value : 4;
2436  uint32_t : 28;
2437 };
2438 
2441 #endif /* __ASSEMBLY__ */
2442 
2444 #define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2445 
2473 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2474 
2475 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2476 
2477 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2478 
2479 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2480 
2481 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2482 
2483 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2484 
2485 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2486 
2487 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2488 
2489 #ifndef __ASSEMBLY__
2490 
2501 {
2502  uint32_t value : 5;
2503  uint32_t : 27;
2504 };
2505 
2508 #endif /* __ASSEMBLY__ */
2509 
2511 #define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2512 
2540 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2541 
2542 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2543 
2544 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2545 
2546 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2547 
2548 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2549 
2550 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2551 
2552 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2553 
2554 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2555 
2556 #ifndef __ASSEMBLY__
2557 
2568 {
2569  uint32_t value : 5;
2570  uint32_t : 27;
2571 };
2572 
2575 #endif /* __ASSEMBLY__ */
2576 
2578 #define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
2579 
2606 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
2607 
2608 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
2609 
2610 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
2611 
2612 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
2613 
2614 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
2615 
2616 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
2617 
2618 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2619 
2620 #define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2621 
2622 #ifndef __ASSEMBLY__
2623 
2634 {
2635  uint32_t value : 4;
2636  uint32_t : 28;
2637 };
2638 
2641 #endif /* __ASSEMBLY__ */
2642 
2644 #define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
2645 
2674 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
2675 
2676 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
2677 
2678 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
2679 
2680 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
2681 
2682 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
2683 
2684 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
2685 
2686 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2687 
2688 #define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2689 
2690 #ifndef __ASSEMBLY__
2691 
2702 {
2703  uint32_t value : 5;
2704  uint32_t : 27;
2705 };
2706 
2709 #endif /* __ASSEMBLY__ */
2710 
2712 #define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
2713 
2741 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
2742 
2743 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
2744 
2745 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
2746 
2747 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
2748 
2749 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
2750 
2751 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
2752 
2753 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
2754 
2755 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
2756 
2757 #ifndef __ASSEMBLY__
2758 
2769 {
2770  uint32_t value : 6;
2771  uint32_t : 26;
2772 };
2773 
2776 #endif /* __ASSEMBLY__ */
2777 
2779 #define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
2780 
2805 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
2806 
2807 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
2808 
2809 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
2810 
2811 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
2812 
2813 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
2814 
2815 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
2816 
2817 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2818 
2819 #define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2820 
2821 #ifndef __ASSEMBLY__
2822 
2833 {
2834  uint32_t value : 16;
2835  uint32_t : 16;
2836 };
2837 
2840 #endif /* __ASSEMBLY__ */
2841 
2843 #define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
2844 
2868 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
2869 
2870 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
2871 
2872 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
2873 
2874 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
2875 
2876 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
2877 
2878 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
2879 
2880 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
2881 
2882 #define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
2883 
2884 #ifndef __ASSEMBLY__
2885 
2896 {
2897  uint32_t value : 3;
2898  uint32_t : 29;
2899 };
2900 
2903 #endif /* __ASSEMBLY__ */
2904 
2906 #define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
2907 
2935 #define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
2936 
2937 #define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 7
2938 
2939 #define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 8
2940 
2941 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x000000ff
2942 
2943 #define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffffff00
2944 
2945 #define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
2946 
2947 #define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2948 
2949 #define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2950 
2951 #ifndef __ASSEMBLY__
2952 
2963 {
2964  uint32_t value : 8;
2965  uint32_t : 24;
2966 };
2967 
2970 #endif /* __ASSEMBLY__ */
2971 
2973 #define ALT_NAND_CFG_DIE_MSK_OFST 0x260
2974 
3001 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3002 
3003 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3004 
3005 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3006 
3007 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3008 
3009 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3010 
3011 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3012 
3013 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3014 
3015 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3016 
3017 #ifndef __ASSEMBLY__
3018 
3029 {
3030  uint32_t value : 16;
3031  uint32_t : 16;
3032 };
3033 
3036 #endif /* __ASSEMBLY__ */
3037 
3039 #define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3040 
3067 #define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3068 
3069 #define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3070 
3071 #define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3072 
3073 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3074 
3075 #define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3076 
3077 #define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3078 
3079 #define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3080 
3081 #define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3082 
3083 #ifndef __ASSEMBLY__
3084 
3095 {
3096  uint32_t flag : 1;
3097  uint32_t : 31;
3098 };
3099 
3102 #endif /* __ASSEMBLY__ */
3103 
3105 #define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3106 
3132 #define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3133 
3134 #define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3135 
3136 #define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3137 
3138 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3139 
3140 #define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3141 
3142 #define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3143 
3144 #define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3145 
3146 #define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3147 
3148 #ifndef __ASSEMBLY__
3149 
3160 {
3161  uint32_t value : 6;
3162  uint32_t : 26;
3163 };
3164 
3167 #endif /* __ASSEMBLY__ */
3168 
3170 #define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3171 
3197 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3198 
3199 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3200 
3201 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3202 
3203 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3204 
3205 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3206 
3207 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3208 
3209 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3210 
3211 #define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3212 
3213 #ifndef __ASSEMBLY__
3214 
3225 {
3226  uint32_t value : 16;
3227  uint32_t : 16;
3228 };
3229 
3232 #endif /* __ASSEMBLY__ */
3233 
3235 #define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3236 
3262 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3263 
3264 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3265 
3266 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3267 
3268 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3269 
3270 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3271 
3272 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3273 
3274 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3275 
3276 #define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3277 
3278 #ifndef __ASSEMBLY__
3279 
3290 {
3291  uint32_t value : 16;
3292  uint32_t : 16;
3293 };
3294 
3297 #endif /* __ASSEMBLY__ */
3298 
3300 #define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3301 
3302 #ifndef __ASSEMBLY__
3303 
3314 {
3316  volatile uint32_t _pad_0x4_0xf[3];
3318  volatile uint32_t _pad_0x14_0x1f[3];
3320  volatile uint32_t _pad_0x24_0x2f[3];
3322  volatile uint32_t _pad_0x34_0x3f[3];
3324  volatile uint32_t _pad_0x44_0x4f[3];
3326  volatile uint32_t _pad_0x54_0x5f[3];
3328  volatile uint32_t _pad_0x64_0x6f[3];
3330  volatile uint32_t _pad_0x74_0x7f[3];
3332  volatile uint32_t _pad_0x84_0x8f[3];
3334  volatile uint32_t _pad_0x94_0x9f[3];
3336  volatile uint32_t _pad_0xa4_0xaf[3];
3338  volatile uint32_t _pad_0xb4_0xbf[3];
3340  volatile uint32_t _pad_0xc4_0xcf[3];
3342  volatile uint32_t _pad_0xd4_0xdf[3];
3344  volatile uint32_t _pad_0xe4_0xef[3];
3346  volatile uint32_t _pad_0xf4_0xff[3];
3348  volatile uint32_t _pad_0x104_0x10f[3];
3350  volatile uint32_t _pad_0x114_0x11f[3];
3352  volatile uint32_t _pad_0x124_0x12f[3];
3354  volatile uint32_t _pad_0x134_0x13f[3];
3356  volatile uint32_t _pad_0x144_0x14f[3];
3358  volatile uint32_t _pad_0x154_0x15f[3];
3360  volatile uint32_t _pad_0x164_0x16f[3];
3362  volatile uint32_t _pad_0x174_0x17f[3];
3364  volatile uint32_t _pad_0x184_0x18f[3];
3366  volatile uint32_t _pad_0x194_0x19f[3];
3368  volatile uint32_t _pad_0x1a4_0x1af[3];
3370  volatile uint32_t _pad_0x1b4_0x1bf[3];
3372  volatile uint32_t _pad_0x1c4_0x1cf[3];
3374  volatile uint32_t _pad_0x1d4_0x1df[3];
3376  volatile uint32_t _pad_0x1e4_0x1ef[3];
3378  volatile uint32_t _pad_0x1f4_0x1ff[3];
3380  volatile uint32_t _pad_0x204_0x20f[3];
3382  volatile uint32_t _pad_0x214_0x21f[3];
3384  volatile uint32_t _pad_0x224_0x22f[3];
3386  volatile uint32_t _pad_0x234_0x23f[3];
3388  volatile uint32_t _pad_0x244_0x24f[3];
3390  volatile uint32_t _pad_0x254_0x25f[3];
3392  volatile uint32_t _pad_0x264_0x26f[3];
3394  volatile uint32_t _pad_0x274_0x27f[3];
3396  volatile uint32_t _pad_0x284_0x28f[3];
3398  volatile uint32_t _pad_0x294_0x29f[3];
3400  volatile uint32_t _pad_0x2a4_0x2af[3];
3402 };
3403 
3405 typedef volatile struct ALT_NAND_CFG_s ALT_NAND_CFG_t;
3408 {
3409  volatile uint32_t device_reset;
3410  volatile uint32_t _pad_0x4_0xf[3];
3411  volatile uint32_t transfer_spare_reg;
3412  volatile uint32_t _pad_0x14_0x1f[3];
3413  volatile uint32_t load_wait_cnt;
3414  volatile uint32_t _pad_0x24_0x2f[3];
3415  volatile uint32_t program_wait_cnt;
3416  volatile uint32_t _pad_0x34_0x3f[3];
3417  volatile uint32_t erase_wait_cnt;
3418  volatile uint32_t _pad_0x44_0x4f[3];
3419  volatile uint32_t int_mon_cyccnt;
3420  volatile uint32_t _pad_0x54_0x5f[3];
3421  volatile uint32_t rb_pin_enabled;
3422  volatile uint32_t _pad_0x64_0x6f[3];
3423  volatile uint32_t multiplane_operation;
3424  volatile uint32_t _pad_0x74_0x7f[3];
3425  volatile uint32_t multiplane_read_enable;
3426  volatile uint32_t _pad_0x84_0x8f[3];
3427  volatile uint32_t copyback_disable;
3428  volatile uint32_t _pad_0x94_0x9f[3];
3429  volatile uint32_t cache_write_enable;
3430  volatile uint32_t _pad_0xa4_0xaf[3];
3431  volatile uint32_t cache_read_enable;
3432  volatile uint32_t _pad_0xb4_0xbf[3];
3433  volatile uint32_t prefetch_mode;
3434  volatile uint32_t _pad_0xc4_0xcf[3];
3435  volatile uint32_t chip_enable_dont_care;
3436  volatile uint32_t _pad_0xd4_0xdf[3];
3437  volatile uint32_t ecc_enable;
3438  volatile uint32_t _pad_0xe4_0xef[3];
3439  volatile uint32_t global_int_enable;
3440  volatile uint32_t _pad_0xf4_0xff[3];
3441  volatile uint32_t twhr2_and_we_2_re;
3442  volatile uint32_t _pad_0x104_0x10f[3];
3443  volatile uint32_t tcwaw_and_addr_2_data;
3444  volatile uint32_t _pad_0x114_0x11f[3];
3445  volatile uint32_t re_2_we;
3446  volatile uint32_t _pad_0x124_0x12f[3];
3447  volatile uint32_t acc_clks;
3448  volatile uint32_t _pad_0x134_0x13f[3];
3449  volatile uint32_t number_of_planes;
3450  volatile uint32_t _pad_0x144_0x14f[3];
3451  volatile uint32_t pages_per_block;
3452  volatile uint32_t _pad_0x154_0x15f[3];
3453  volatile uint32_t device_width;
3454  volatile uint32_t _pad_0x164_0x16f[3];
3455  volatile uint32_t device_main_area_size;
3456  volatile uint32_t _pad_0x174_0x17f[3];
3457  volatile uint32_t device_spare_area_size;
3458  volatile uint32_t _pad_0x184_0x18f[3];
3459  volatile uint32_t two_row_addr_cycles;
3460  volatile uint32_t _pad_0x194_0x19f[3];
3461  volatile uint32_t multiplane_addr_restrict;
3462  volatile uint32_t _pad_0x1a4_0x1af[3];
3463  volatile uint32_t ecc_correction;
3464  volatile uint32_t _pad_0x1b4_0x1bf[3];
3465  volatile uint32_t read_mode;
3466  volatile uint32_t _pad_0x1c4_0x1cf[3];
3467  volatile uint32_t write_mode;
3468  volatile uint32_t _pad_0x1d4_0x1df[3];
3469  volatile uint32_t copyback_mode;
3470  volatile uint32_t _pad_0x1e4_0x1ef[3];
3471  volatile uint32_t rdwr_en_lo_cnt;
3472  volatile uint32_t _pad_0x1f4_0x1ff[3];
3473  volatile uint32_t rdwr_en_hi_cnt;
3474  volatile uint32_t _pad_0x204_0x20f[3];
3475  volatile uint32_t max_rd_delay;
3476  volatile uint32_t _pad_0x214_0x21f[3];
3477  volatile uint32_t cs_setup_cnt;
3478  volatile uint32_t _pad_0x224_0x22f[3];
3479  volatile uint32_t spare_area_skip_bytes;
3480  volatile uint32_t _pad_0x234_0x23f[3];
3481  volatile uint32_t spare_area_marker;
3482  volatile uint32_t _pad_0x244_0x24f[3];
3483  volatile uint32_t devices_connected;
3484  volatile uint32_t _pad_0x254_0x25f[3];
3485  volatile uint32_t die_mask;
3486  volatile uint32_t _pad_0x264_0x26f[3];
3487  volatile uint32_t first_block_of_next_plane;
3488  volatile uint32_t _pad_0x274_0x27f[3];
3489  volatile uint32_t write_protect;
3490  volatile uint32_t _pad_0x284_0x28f[3];
3491  volatile uint32_t re_2_re;
3492  volatile uint32_t _pad_0x294_0x29f[3];
3493  volatile uint32_t por_reset_count;
3494  volatile uint32_t _pad_0x2a4_0x2af[3];
3495  volatile uint32_t watchdog_reset_count;
3496 };
3497 
3499 typedef volatile struct ALT_NAND_CFG_raw_s ALT_NAND_CFG_raw_t;
3500 #endif /* __ASSEMBLY__ */
3501 
3531 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
3532 
3533 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
3534 
3535 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
3536 
3537 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
3538 
3539 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
3540 
3541 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
3542 
3543 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3544 
3545 #define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3546 
3547 #ifndef __ASSEMBLY__
3548 
3559 {
3560  uint32_t value : 8;
3561  uint32_t : 24;
3562 };
3563 
3566 #endif /* __ASSEMBLY__ */
3567 
3569 #define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
3570 
3591 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
3592 
3593 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
3594 
3595 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
3596 
3597 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
3598 
3599 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
3600 
3601 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
3602 
3603 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3604 
3605 #define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3606 
3607 #ifndef __ASSEMBLY__
3608 
3619 {
3620  const uint32_t value : 8;
3621  uint32_t : 24;
3622 };
3623 
3626 #endif /* __ASSEMBLY__ */
3627 
3629 #define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
3630 
3652 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
3653 
3654 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
3655 
3656 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
3657 
3658 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
3659 
3660 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
3661 
3662 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
3663 
3664 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3665 
3666 #define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3667 
3668 #ifndef __ASSEMBLY__
3669 
3680 {
3681  const uint32_t value : 8;
3682  uint32_t : 24;
3683 };
3684 
3687 #endif /* __ASSEMBLY__ */
3688 
3690 #define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
3691 
3713 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
3714 
3715 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
3716 
3717 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
3718 
3719 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
3720 
3721 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
3722 
3723 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
3724 
3725 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3726 
3727 #define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3728 
3729 #ifndef __ASSEMBLY__
3730 
3741 {
3742  const uint32_t value : 8;
3743  uint32_t : 24;
3744 };
3745 
3748 #endif /* __ASSEMBLY__ */
3749 
3751 #define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
3752 
3773 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
3774 
3775 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
3776 
3777 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
3778 
3779 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
3780 
3781 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
3782 
3783 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
3784 
3785 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
3786 
3787 #define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
3788 
3789 #ifndef __ASSEMBLY__
3790 
3801 {
3802  const uint32_t value : 8;
3803  uint32_t : 24;
3804 };
3805 
3808 #endif /* __ASSEMBLY__ */
3809 
3811 #define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
3812 
3837 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
3838 
3839 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
3840 
3841 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
3842 
3843 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
3844 
3845 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
3846 
3847 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
3848 
3849 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3850 
3851 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3852 
3853 #ifndef __ASSEMBLY__
3854 
3865 {
3866  const uint32_t value : 16;
3867  uint32_t : 16;
3868 };
3869 
3872 #endif /* __ASSEMBLY__ */
3873 
3875 #define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
3876 
3901 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
3902 
3903 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
3904 
3905 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
3906 
3907 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
3908 
3909 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
3910 
3911 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
3912 
3913 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3914 
3915 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3916 
3917 #ifndef __ASSEMBLY__
3918 
3929 {
3930  const uint32_t value : 16;
3931  uint32_t : 16;
3932 };
3933 
3936 #endif /* __ASSEMBLY__ */
3937 
3939 #define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
3940 
3963 #define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
3964 
3965 #define ALT_NAND_PARAM_REVISION_VALUE_MSB 15
3966 
3967 #define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 16
3968 
3969 #define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x0000ffff
3970 
3971 #define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffff0000
3972 
3973 #define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
3974 
3975 #define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3976 
3977 #define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3978 
3979 #ifndef __ASSEMBLY__
3980 
3991 {
3992  const uint32_t value : 16;
3993  uint32_t : 16;
3994 };
3995 
3998 #endif /* __ASSEMBLY__ */
3999 
4001 #define ALT_NAND_PARAM_REVISION_OFST 0x70
4002 
4032 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4033 
4034 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4035 
4036 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4037 
4038 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4039 
4040 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4041 
4042 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4043 
4044 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4045 
4046 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4047 
4048 #ifndef __ASSEMBLY__
4049 
4060 {
4061  const uint32_t value : 16;
4062  uint32_t : 16;
4063 };
4064 
4067 #endif /* __ASSEMBLY__ */
4068 
4070 #define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4071 
4100 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4101 
4102 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4103 
4104 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4105 
4106 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4107 
4108 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4109 
4110 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4111 
4112 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4113 
4114 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4115 
4116 #ifndef __ASSEMBLY__
4117 
4128 {
4129  const uint32_t value : 16;
4130  uint32_t : 16;
4131 };
4132 
4135 #endif /* __ASSEMBLY__ */
4136 
4138 #define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4139 
4165 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4166 
4167 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4168 
4169 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4170 
4171 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4172 
4173 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4174 
4175 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4176 
4177 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4178 
4179 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4180 
4181 #ifndef __ASSEMBLY__
4182 
4193 {
4194  const uint32_t value : 6;
4195  uint32_t : 26;
4196 };
4197 
4200 #endif /* __ASSEMBLY__ */
4201 
4203 #define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4204 
4230 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4231 
4232 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4233 
4234 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4235 
4236 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4237 
4238 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4239 
4240 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4241 
4242 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4243 
4244 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4245 
4246 #ifndef __ASSEMBLY__
4247 
4258 {
4259  const uint32_t value : 6;
4260  uint32_t : 26;
4261 };
4262 
4265 #endif /* __ASSEMBLY__ */
4266 
4268 #define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4269 
4294 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4295 
4296 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4297 
4298 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4299 
4300 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4301 
4302 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4303 
4304 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4305 
4306 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4307 
4308 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4309 
4320 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4321 
4322 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4323 
4324 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4325 
4326 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4327 
4328 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4329 
4330 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4331 
4332 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4333 
4334 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
4335 
4336 #ifndef __ASSEMBLY__
4337 
4348 {
4349  const uint32_t no_of_luns : 8;
4350  uint32_t onfi_device : 1;
4351  uint32_t : 23;
4352 };
4353 
4356 #endif /* __ASSEMBLY__ */
4357 
4359 #define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
4360 
4384 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
4385 
4386 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
4387 
4388 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
4389 
4390 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
4391 
4392 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
4393 
4394 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
4395 
4396 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4397 
4398 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4399 
4400 #ifndef __ASSEMBLY__
4401 
4412 {
4413  const uint32_t value : 16;
4414  uint32_t : 16;
4415 };
4416 
4419 #endif /* __ASSEMBLY__ */
4420 
4422 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
4423 
4447 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
4448 
4449 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
4450 
4451 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
4452 
4453 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
4454 
4455 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
4456 
4457 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
4458 
4459 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4460 
4461 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4462 
4463 #ifndef __ASSEMBLY__
4464 
4475 {
4476  const uint32_t value : 16;
4477  uint32_t : 16;
4478 };
4479 
4482 #endif /* __ASSEMBLY__ */
4483 
4485 #define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
4486 
4520 #define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
4521 
4522 #define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
4523 
4524 #define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
4525 
4526 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
4527 
4528 #define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
4529 
4530 #define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x1
4531 
4532 #define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
4533 
4534 #define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
4535 
4545 #define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
4546 
4547 #define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
4548 
4549 #define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
4550 
4551 #define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
4552 
4553 #define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
4554 
4555 #define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
4556 
4557 #define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
4558 
4559 #define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
4560 
4570 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
4571 
4572 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
4573 
4574 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
4575 
4576 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
4577 
4578 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
4579 
4580 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x0
4581 
4582 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
4583 
4584 #define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
4585 
4595 #define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
4596 
4597 #define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
4598 
4599 #define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
4600 
4601 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
4602 
4603 #define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
4604 
4605 #define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
4606 
4607 #define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
4608 
4609 #define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
4610 
4620 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
4621 
4622 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
4623 
4624 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
4625 
4626 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
4627 
4628 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
4629 
4630 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
4631 
4632 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
4633 
4634 #define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
4635 
4645 #define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
4646 
4647 #define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
4648 
4649 #define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
4650 
4651 #define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
4652 
4653 #define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
4654 
4655 #define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
4656 
4657 #define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
4658 
4659 #define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
4660 
4670 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
4671 
4672 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
4673 
4674 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
4675 
4676 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
4677 
4678 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
4679 
4680 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
4681 
4682 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
4683 
4684 #define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
4685 
4695 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
4696 
4697 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
4698 
4699 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
4700 
4701 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
4702 
4703 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
4704 
4705 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
4706 
4707 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
4708 
4709 #define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
4710 
4720 #define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
4721 
4722 #define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
4723 
4724 #define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
4725 
4726 #define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
4727 
4728 #define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
4729 
4730 #define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
4731 
4732 #define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
4733 
4734 #define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
4735 
4736 #ifndef __ASSEMBLY__
4737 
4748 {
4749  const uint32_t n_banks : 2;
4750  uint32_t : 4;
4751  const uint32_t dma : 1;
4752  const uint32_t cmd_dma : 1;
4753  const uint32_t partition : 1;
4754  const uint32_t xdma_sideband : 1;
4755  const uint32_t gpreg : 1;
4756  const uint32_t index_addr : 1;
4757  const uint32_t dfi_intf : 1;
4758  const uint32_t lba : 1;
4759  uint32_t : 18;
4760 };
4761 
4764 #endif /* __ASSEMBLY__ */
4765 
4767 #define ALT_NAND_PARAM_FEATURES_OFST 0xf0
4768 
4769 #ifndef __ASSEMBLY__
4770 
4781 {
4783  volatile uint32_t _pad_0x4_0xf[3];
4785  volatile uint32_t _pad_0x14_0x1f[3];
4787  volatile uint32_t _pad_0x24_0x2f[3];
4789  volatile uint32_t _pad_0x34_0x3f[3];
4791  volatile uint32_t _pad_0x44_0x4f[3];
4793  volatile uint32_t _pad_0x54_0x5f[3];
4795  volatile uint32_t _pad_0x64_0x6f[3];
4797  volatile uint32_t _pad_0x74_0x7f[3];
4799  volatile uint32_t _pad_0x84_0x8f[3];
4801  volatile uint32_t _pad_0x94_0x9f[3];
4803  volatile uint32_t _pad_0xa4_0xaf[3];
4805  volatile uint32_t _pad_0xb4_0xbf[3];
4807  volatile uint32_t _pad_0xc4_0xcf[3];
4809  volatile uint32_t _pad_0xd4_0xdf[3];
4811  volatile uint32_t _pad_0xe4_0xef[3];
4813 };
4814 
4816 typedef volatile struct ALT_NAND_PARAM_s ALT_NAND_PARAM_t;
4819 {
4820  volatile uint32_t manufacturer_id;
4821  volatile uint32_t _pad_0x4_0xf[3];
4822  volatile uint32_t device_id;
4823  volatile uint32_t _pad_0x14_0x1f[3];
4824  volatile uint32_t device_param_0;
4825  volatile uint32_t _pad_0x24_0x2f[3];
4826  volatile uint32_t device_param_1;
4827  volatile uint32_t _pad_0x34_0x3f[3];
4828  volatile uint32_t device_param_2;
4829  volatile uint32_t _pad_0x44_0x4f[3];
4830  volatile uint32_t logical_page_data_size;
4831  volatile uint32_t _pad_0x54_0x5f[3];
4832  volatile uint32_t logical_page_spare_size;
4833  volatile uint32_t _pad_0x64_0x6f[3];
4834  volatile uint32_t revision;
4835  volatile uint32_t _pad_0x74_0x7f[3];
4836  volatile uint32_t onfi_device_features;
4837  volatile uint32_t _pad_0x84_0x8f[3];
4838  volatile uint32_t onfi_optional_commands;
4839  volatile uint32_t _pad_0x94_0x9f[3];
4840  volatile uint32_t onfi_timing_mode;
4841  volatile uint32_t _pad_0xa4_0xaf[3];
4842  volatile uint32_t onfi_pgm_cache_timing_mode;
4843  volatile uint32_t _pad_0xb4_0xbf[3];
4844  volatile uint32_t onfi_device_no_of_luns;
4845  volatile uint32_t _pad_0xc4_0xcf[3];
4847  volatile uint32_t _pad_0xd4_0xdf[3];
4849  volatile uint32_t _pad_0xe4_0xef[3];
4850  volatile uint32_t features;
4851 };
4852 
4855 #endif /* __ASSEMBLY__ */
4856 
4892 #define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
4893 
4894 #define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
4895 
4896 #define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
4897 
4898 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
4899 
4900 #define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
4901 
4902 #define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
4903 
4904 #define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
4905 
4906 #define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
4907 
4918 #define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
4919 
4920 #define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
4921 
4922 #define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
4923 
4924 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
4925 
4926 #define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
4927 
4928 #define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
4929 
4930 #define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
4931 
4932 #define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
4933 
4944 #define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
4945 
4946 #define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
4947 
4948 #define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
4949 
4950 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
4951 
4952 #define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
4953 
4954 #define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
4955 
4956 #define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
4957 
4958 #define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
4959 
4970 #define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
4971 
4972 #define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
4973 
4974 #define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
4975 
4976 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
4977 
4978 #define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
4979 
4980 #define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
4981 
4982 #define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
4983 
4984 #define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
4985 
4986 #ifndef __ASSEMBLY__
4987 
4998 {
4999  const uint32_t value0 : 2;
5000  const uint32_t value1 : 2;
5001  const uint32_t value2 : 2;
5002  const uint32_t value3 : 2;
5003  uint32_t : 24;
5004 };
5005 
5008 #endif /* __ASSEMBLY__ */
5009 
5011 #define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5012 
5050 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5051 
5052 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5053 
5054 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5055 
5056 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5057 
5058 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5059 
5060 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5061 
5062 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5063 
5064 #define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5065 
5075 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5076 
5077 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5078 
5079 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5080 
5081 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5082 
5083 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5084 
5085 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5086 
5087 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5088 
5089 #define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5090 
5101 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5102 
5103 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5104 
5105 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5106 
5107 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5108 
5109 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5110 
5111 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5112 
5113 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5114 
5115 #define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5116 
5128 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5129 
5130 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5131 
5132 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5133 
5134 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5135 
5136 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5137 
5138 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5139 
5140 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5141 
5142 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5143 
5155 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5156 
5157 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5158 
5159 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5160 
5161 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5162 
5163 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5164 
5165 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5166 
5167 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5168 
5169 #define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5170 
5180 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5181 
5182 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5183 
5184 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5185 
5186 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5187 
5188 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5189 
5190 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5191 
5192 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5193 
5194 #define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5195 
5205 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5206 
5207 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5208 
5209 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5210 
5211 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5212 
5213 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5214 
5215 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
5216 
5217 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5218 
5219 #define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5220 
5230 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
5231 
5232 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
5233 
5234 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
5235 
5236 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
5237 
5238 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
5239 
5240 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
5241 
5242 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5243 
5244 #define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5245 
5256 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
5257 
5258 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
5259 
5260 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5261 
5262 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5263 
5264 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5265 
5266 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5267 
5268 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5269 
5270 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5271 
5282 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
5283 
5284 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
5285 
5286 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
5287 
5288 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
5289 
5290 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
5291 
5292 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
5293 
5294 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5295 
5296 #define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5297 
5308 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
5309 
5310 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
5311 
5312 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
5313 
5314 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
5315 
5316 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5317 
5318 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
5319 
5320 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5321 
5322 #define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5323 
5333 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
5334 
5335 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
5336 
5337 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
5338 
5339 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
5340 
5341 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
5342 
5343 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
5344 
5345 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5346 
5347 #define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5348 
5358 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
5359 
5360 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
5361 
5362 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
5363 
5364 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
5365 
5366 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
5367 
5368 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
5369 
5370 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5371 
5372 #define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5373 
5385 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
5386 
5387 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
5388 
5389 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
5390 
5391 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
5392 
5393 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5394 
5395 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
5396 
5397 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5398 
5399 #define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5400 
5410 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
5411 
5412 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
5413 
5414 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
5415 
5416 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
5417 
5418 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5419 
5420 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
5421 
5422 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5423 
5424 #define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5425 
5426 #ifndef __ASSEMBLY__
5427 
5438 {
5439  uint32_t ecc_uncor_err : 1;
5440  uint32_t : 1;
5441  uint32_t dma_cmd_comp : 1;
5442  uint32_t time_out : 1;
5443  uint32_t program_fail : 1;
5444  uint32_t erase_fail : 1;
5445  uint32_t load_comp : 1;
5446  uint32_t program_comp : 1;
5447  uint32_t erase_comp : 1;
5448  uint32_t pipe_cpybck_cmd_comp : 1;
5449  uint32_t locked_blk : 1;
5450  uint32_t unsup_cmd : 1;
5451  uint32_t INT_act : 1;
5452  uint32_t rst_comp : 1;
5453  uint32_t pipe_cmd_err : 1;
5454  uint32_t page_xfer_inc : 1;
5455  uint32_t : 16;
5456 };
5457 
5460 #endif /* __ASSEMBLY__ */
5461 
5463 #define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
5464 
5503 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
5504 
5505 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
5506 
5507 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
5508 
5509 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5510 
5511 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5512 
5513 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
5514 
5515 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5516 
5517 #define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5518 
5528 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
5529 
5530 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
5531 
5532 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
5533 
5534 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
5535 
5536 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5537 
5538 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
5539 
5540 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5541 
5542 #define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5543 
5554 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
5555 
5556 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
5557 
5558 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
5559 
5560 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
5561 
5562 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
5563 
5564 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
5565 
5566 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5567 
5568 #define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5569 
5581 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
5582 
5583 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
5584 
5585 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
5586 
5587 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
5588 
5589 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5590 
5591 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
5592 
5593 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5594 
5595 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5596 
5608 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
5609 
5610 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
5611 
5612 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
5613 
5614 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
5615 
5616 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
5617 
5618 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
5619 
5620 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5621 
5622 #define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5623 
5633 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
5634 
5635 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
5636 
5637 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
5638 
5639 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
5640 
5641 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
5642 
5643 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
5644 
5645 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5646 
5647 #define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5648 
5658 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
5659 
5660 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
5661 
5662 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
5663 
5664 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
5665 
5666 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5667 
5668 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
5669 
5670 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
5671 
5672 #define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
5673 
5683 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
5684 
5685 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
5686 
5687 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
5688 
5689 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
5690 
5691 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
5692 
5693 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
5694 
5695 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
5696 
5697 #define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
5698 
5709 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
5710 
5711 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
5712 
5713 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
5714 
5715 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
5716 
5717 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
5718 
5719 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
5720 
5721 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
5722 
5723 #define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
5724 
5735 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
5736 
5737 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
5738 
5739 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
5740 
5741 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
5742 
5743 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
5744 
5745 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
5746 
5747 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
5748 
5749 #define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
5750 
5761 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
5762 
5763 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
5764 
5765 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
5766 
5767 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
5768 
5769 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
5770 
5771 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
5772 
5773 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
5774 
5775 #define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
5776 
5786 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
5787 
5788 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
5789 
5790 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
5791 
5792 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
5793 
5794 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
5795 
5796 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
5797 
5798 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
5799 
5800 #define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
5801 
5811 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
5812 
5813 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
5814 
5815 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
5816 
5817 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
5818 
5819 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
5820 
5821 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
5822 
5823 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
5824 
5825 #define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
5826 
5838 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
5839 
5840 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
5841 
5842 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
5843 
5844 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
5845 
5846 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
5847 
5848 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
5849 
5850 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
5851 
5852 #define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
5853 
5863 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
5864 
5865 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
5866 
5867 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
5868 
5869 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
5870 
5871 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
5872 
5873 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
5874 
5875 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
5876 
5877 #define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
5878 
5879 #ifndef __ASSEMBLY__
5880 
5891 {
5892  uint32_t ecc_uncor_err : 1;
5893  uint32_t : 1;
5894  uint32_t dma_cmd_comp : 1;
5895  uint32_t time_out : 1;
5896  uint32_t program_fail : 1;
5897  uint32_t erase_fail : 1;
5898  uint32_t load_comp : 1;
5899  uint32_t program_comp : 1;
5900  uint32_t erase_comp : 1;
5901  uint32_t pipe_cpybck_cmd_comp : 1;
5902  uint32_t locked_blk : 1;
5903  uint32_t unsup_cmd : 1;
5904  uint32_t INT_act : 1;
5905  uint32_t rst_comp : 1;
5906  uint32_t pipe_cmd_err : 1;
5907  uint32_t page_xfer_inc : 1;
5908  uint32_t : 16;
5909 };
5910 
5913 #endif /* __ASSEMBLY__ */
5914 
5916 #define ALT_NAND_STAT_INTR_EN0_OFST 0x20
5917 
5941 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
5942 
5943 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
5944 
5945 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
5946 
5947 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
5948 
5949 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
5950 
5951 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
5952 
5953 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
5954 
5955 #define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
5956 
5957 #ifndef __ASSEMBLY__
5958 
5969 {
5970  const uint32_t value : 8;
5971  uint32_t : 24;
5972 };
5973 
5976 #endif /* __ASSEMBLY__ */
5977 
5979 #define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
5980 
6003 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6004 
6005 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6006 
6007 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6008 
6009 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6010 
6011 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6012 
6013 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6014 
6015 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6016 
6017 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6018 
6019 #ifndef __ASSEMBLY__
6020 
6031 {
6032  const uint32_t value : 16;
6033  uint32_t : 16;
6034 };
6035 
6038 #endif /* __ASSEMBLY__ */
6039 
6041 #define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6042 
6066 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6067 
6068 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6069 
6070 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6071 
6072 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6073 
6074 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6075 
6076 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6077 
6078 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6079 
6080 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6081 
6082 #ifndef __ASSEMBLY__
6083 
6094 {
6095  const uint32_t value : 16;
6096  uint32_t : 16;
6097 };
6098 
6101 #endif /* __ASSEMBLY__ */
6102 
6104 #define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
6105 
6143 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
6144 
6145 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
6146 
6147 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
6148 
6149 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6150 
6151 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6152 
6153 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
6154 
6155 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6156 
6157 #define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6158 
6168 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
6169 
6170 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
6171 
6172 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
6173 
6174 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
6175 
6176 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6177 
6178 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
6179 
6180 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6181 
6182 #define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6183 
6194 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
6195 
6196 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
6197 
6198 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
6199 
6200 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
6201 
6202 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
6203 
6204 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
6205 
6206 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6207 
6208 #define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6209 
6221 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
6222 
6223 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
6224 
6225 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
6226 
6227 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
6228 
6229 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6230 
6231 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
6232 
6233 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6234 
6235 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6236 
6248 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
6249 
6250 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
6251 
6252 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
6253 
6254 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
6255 
6256 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
6257 
6258 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
6259 
6260 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6261 
6262 #define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6263 
6273 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
6274 
6275 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
6276 
6277 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
6278 
6279 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
6280 
6281 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
6282 
6283 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
6284 
6285 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6286 
6287 #define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6288 
6298 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
6299 
6300 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
6301 
6302 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
6303 
6304 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
6305 
6306 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6307 
6308 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
6309 
6310 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6311 
6312 #define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6313 
6323 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
6324 
6325 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
6326 
6327 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
6328 
6329 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
6330 
6331 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
6332 
6333 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
6334 
6335 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6336 
6337 #define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6338 
6349 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
6350 
6351 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
6352 
6353 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6354 
6355 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6356 
6357 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6358 
6359 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6360 
6361 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6362 
6363 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6364 
6375 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
6376 
6377 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
6378 
6379 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
6380 
6381 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
6382 
6383 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
6384 
6385 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
6386 
6387 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6388 
6389 #define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6390 
6401 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
6402 
6403 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
6404 
6405 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
6406 
6407 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
6408 
6409 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6410 
6411 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
6412 
6413 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6414 
6415 #define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6416 
6426 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
6427 
6428 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
6429 
6430 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
6431 
6432 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
6433 
6434 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
6435 
6436 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
6437 
6438 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6439 
6440 #define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6441 
6452 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
6453 
6454 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
6455 
6456 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
6457 
6458 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
6459 
6460 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
6461 
6462 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
6463 
6464 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6465 
6466 #define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6467 
6479 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
6480 
6481 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
6482 
6483 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
6484 
6485 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
6486 
6487 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6488 
6489 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
6490 
6491 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6492 
6493 #define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6494 
6504 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
6505 
6506 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
6507 
6508 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
6509 
6510 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
6511 
6512 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6513 
6514 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
6515 
6516 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6517 
6518 #define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6519 
6520 #ifndef __ASSEMBLY__
6521 
6532 {
6533  uint32_t ecc_uncor_err : 1;
6534  uint32_t : 1;
6535  uint32_t dma_cmd_comp : 1;
6536  uint32_t time_out : 1;
6537  uint32_t program_fail : 1;
6538  uint32_t erase_fail : 1;
6539  uint32_t load_comp : 1;
6540  uint32_t program_comp : 1;
6541  uint32_t erase_comp : 1;
6542  uint32_t pipe_cpybck_cmd_comp : 1;
6543  uint32_t locked_blk : 1;
6544  uint32_t unsup_cmd : 1;
6545  uint32_t INT_act : 1;
6546  uint32_t rst_comp : 1;
6547  uint32_t pipe_cmd_err : 1;
6548  uint32_t page_xfer_inc : 1;
6549  uint32_t : 16;
6550 };
6551 
6554 #endif /* __ASSEMBLY__ */
6555 
6557 #define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
6558 
6597 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
6598 
6599 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
6600 
6601 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
6602 
6603 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
6604 
6605 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6606 
6607 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
6608 
6609 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6610 
6611 #define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6612 
6622 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
6623 
6624 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
6625 
6626 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
6627 
6628 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
6629 
6630 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6631 
6632 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
6633 
6634 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6635 
6636 #define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6637 
6648 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
6649 
6650 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
6651 
6652 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
6653 
6654 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
6655 
6656 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
6657 
6658 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
6659 
6660 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6661 
6662 #define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6663 
6675 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
6676 
6677 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
6678 
6679 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
6680 
6681 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
6682 
6683 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
6684 
6685 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
6686 
6687 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6688 
6689 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6690 
6702 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
6703 
6704 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
6705 
6706 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
6707 
6708 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
6709 
6710 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
6711 
6712 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
6713 
6714 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6715 
6716 #define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6717 
6727 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
6728 
6729 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
6730 
6731 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
6732 
6733 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
6734 
6735 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
6736 
6737 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
6738 
6739 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6740 
6741 #define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6742 
6752 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
6753 
6754 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
6755 
6756 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
6757 
6758 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
6759 
6760 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
6761 
6762 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
6763 
6764 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6765 
6766 #define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6767 
6777 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
6778 
6779 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
6780 
6781 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
6782 
6783 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
6784 
6785 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
6786 
6787 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
6788 
6789 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6790 
6791 #define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6792 
6803 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
6804 
6805 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
6806 
6807 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6808 
6809 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6810 
6811 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6812 
6813 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6814 
6815 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6816 
6817 #define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6818 
6829 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
6830 
6831 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
6832 
6833 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
6834 
6835 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
6836 
6837 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
6838 
6839 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
6840 
6841 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6842 
6843 #define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6844 
6855 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
6856 
6857 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
6858 
6859 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
6860 
6861 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
6862 
6863 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
6864 
6865 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
6866 
6867 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6868 
6869 #define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6870 
6880 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
6881 
6882 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
6883 
6884 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
6885 
6886 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
6887 
6888 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
6889 
6890 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
6891 
6892 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6893 
6894 #define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6895 
6905 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
6906 
6907 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
6908 
6909 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
6910 
6911 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
6912 
6913 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
6914 
6915 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
6916 
6917 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6918 
6919 #define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6920 
6932 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
6933 
6934 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
6935 
6936 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
6937 
6938 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
6939 
6940 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6941 
6942 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
6943 
6944 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6945 
6946 #define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6947 
6957 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
6958 
6959 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
6960 
6961 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
6962 
6963 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
6964 
6965 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6966 
6967 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
6968 
6969 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6970 
6971 #define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6972 
6973 #ifndef __ASSEMBLY__
6974 
6985 {
6986  uint32_t ecc_uncor_err : 1;
6987  uint32_t : 1;
6988  uint32_t dma_cmd_comp : 1;
6989  uint32_t time_out : 1;
6990  uint32_t program_fail : 1;
6991  uint32_t erase_fail : 1;
6992  uint32_t load_comp : 1;
6993  uint32_t program_comp : 1;
6994  uint32_t erase_comp : 1;
6995  uint32_t pipe_cpybck_cmd_comp : 1;
6996  uint32_t locked_blk : 1;
6997  uint32_t unsup_cmd : 1;
6998  uint32_t INT_act : 1;
6999  uint32_t rst_comp : 1;
7000  uint32_t pipe_cmd_err : 1;
7001  uint32_t page_xfer_inc : 1;
7002  uint32_t : 16;
7003 };
7004 
7007 #endif /* __ASSEMBLY__ */
7008 
7010 #define ALT_NAND_STAT_INTR_EN1_OFST 0x70
7011 
7035 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
7036 
7037 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
7038 
7039 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
7040 
7041 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
7042 
7043 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
7044 
7045 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
7046 
7047 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
7048 
7049 #define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
7050 
7051 #ifndef __ASSEMBLY__
7052 
7063 {
7064  const uint32_t value : 8;
7065  uint32_t : 24;
7066 };
7067 
7070 #endif /* __ASSEMBLY__ */
7071 
7073 #define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
7074 
7097 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
7098 
7099 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
7100 
7101 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
7102 
7103 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
7104 
7105 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
7106 
7107 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
7108 
7109 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7110 
7111 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7112 
7113 #ifndef __ASSEMBLY__
7114 
7125 {
7126  const uint32_t value : 16;
7127  uint32_t : 16;
7128 };
7129 
7132 #endif /* __ASSEMBLY__ */
7133 
7135 #define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
7136 
7160 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
7161 
7162 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
7163 
7164 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
7165 
7166 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
7167 
7168 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
7169 
7170 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
7171 
7172 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
7173 
7174 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
7175 
7176 #ifndef __ASSEMBLY__
7177 
7188 {
7189  const uint32_t value : 16;
7190  uint32_t : 16;
7191 };
7192 
7195 #endif /* __ASSEMBLY__ */
7196 
7198 #define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
7199 
7237 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
7238 
7239 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
7240 
7241 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
7242 
7243 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7244 
7245 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7246 
7247 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
7248 
7249 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7250 
7251 #define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7252 
7262 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
7263 
7264 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
7265 
7266 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
7267 
7268 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
7269 
7270 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7271 
7272 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
7273 
7274 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7275 
7276 #define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7277 
7288 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
7289 
7290 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
7291 
7292 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
7293 
7294 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
7295 
7296 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
7297 
7298 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
7299 
7300 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7301 
7302 #define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7303 
7315 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
7316 
7317 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
7318 
7319 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
7320 
7321 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
7322 
7323 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7324 
7325 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
7326 
7327 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7328 
7329 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7330 
7342 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
7343 
7344 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
7345 
7346 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
7347 
7348 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
7349 
7350 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
7351 
7352 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
7353 
7354 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7355 
7356 #define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7357 
7367 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
7368 
7369 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
7370 
7371 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
7372 
7373 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
7374 
7375 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
7376 
7377 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
7378 
7379 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7380 
7381 #define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7382 
7392 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
7393 
7394 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
7395 
7396 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
7397 
7398 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
7399 
7400 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7401 
7402 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
7403 
7404 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7405 
7406 #define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7407 
7417 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
7418 
7419 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
7420 
7421 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
7422 
7423 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
7424 
7425 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
7426 
7427 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
7428 
7429 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7430 
7431 #define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7432 
7443 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
7444 
7445 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
7446 
7447 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7448 
7449 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7450 
7451 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7452 
7453 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7454 
7455 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7456 
7457 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7458 
7469 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
7470 
7471 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
7472 
7473 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
7474 
7475 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
7476 
7477 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
7478 
7479 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
7480 
7481 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7482 
7483 #define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7484 
7495 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
7496 
7497 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
7498 
7499 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
7500 
7501 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
7502 
7503 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7504 
7505 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
7506 
7507 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7508 
7509 #define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7510 
7520 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
7521 
7522 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
7523 
7524 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
7525 
7526 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
7527 
7528 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
7529 
7530 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
7531 
7532 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7533 
7534 #define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7535 
7546 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
7547 
7548 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
7549 
7550 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
7551 
7552 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
7553 
7554 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
7555 
7556 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
7557 
7558 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7559 
7560 #define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7561 
7573 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
7574 
7575 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
7576 
7577 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
7578 
7579 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
7580 
7581 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7582 
7583 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
7584 
7585 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7586 
7587 #define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7588 
7598 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
7599 
7600 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
7601 
7602 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
7603 
7604 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
7605 
7606 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7607 
7608 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
7609 
7610 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7611 
7612 #define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7613 
7614 #ifndef __ASSEMBLY__
7615 
7626 {
7627  uint32_t ecc_uncor_err : 1;
7628  uint32_t : 1;
7629  uint32_t dma_cmd_comp : 1;
7630  uint32_t time_out : 1;
7631  uint32_t program_fail : 1;
7632  uint32_t erase_fail : 1;
7633  uint32_t load_comp : 1;
7634  uint32_t program_comp : 1;
7635  uint32_t erase_comp : 1;
7636  uint32_t pipe_cpybck_cmd_comp : 1;
7637  uint32_t locked_blk : 1;
7638  uint32_t unsup_cmd : 1;
7639  uint32_t INT_act : 1;
7640  uint32_t rst_comp : 1;
7641  uint32_t pipe_cmd_err : 1;
7642  uint32_t page_xfer_inc : 1;
7643  uint32_t : 16;
7644 };
7645 
7648 #endif /* __ASSEMBLY__ */
7649 
7651 #define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
7652 
7691 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
7692 
7693 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
7694 
7695 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
7696 
7697 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
7698 
7699 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7700 
7701 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
7702 
7703 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7704 
7705 #define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7706 
7716 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
7717 
7718 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
7719 
7720 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
7721 
7722 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
7723 
7724 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7725 
7726 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
7727 
7728 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7729 
7730 #define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7731 
7742 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
7743 
7744 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
7745 
7746 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
7747 
7748 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
7749 
7750 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
7751 
7752 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
7753 
7754 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7755 
7756 #define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7757 
7769 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
7770 
7771 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
7772 
7773 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
7774 
7775 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
7776 
7777 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
7778 
7779 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
7780 
7781 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7782 
7783 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7784 
7796 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
7797 
7798 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
7799 
7800 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
7801 
7802 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
7803 
7804 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
7805 
7806 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
7807 
7808 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7809 
7810 #define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7811 
7821 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
7822 
7823 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
7824 
7825 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
7826 
7827 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
7828 
7829 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
7830 
7831 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
7832 
7833 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7834 
7835 #define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7836 
7846 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
7847 
7848 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
7849 
7850 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
7851 
7852 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
7853 
7854 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
7855 
7856 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
7857 
7858 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7859 
7860 #define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7861 
7871 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
7872 
7873 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
7874 
7875 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
7876 
7877 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
7878 
7879 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
7880 
7881 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
7882 
7883 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7884 
7885 #define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7886 
7897 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
7898 
7899 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
7900 
7901 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7902 
7903 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7904 
7905 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7906 
7907 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7908 
7909 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7910 
7911 #define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7912 
7923 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
7924 
7925 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
7926 
7927 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
7928 
7929 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
7930 
7931 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
7932 
7933 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
7934 
7935 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7936 
7937 #define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7938 
7949 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
7950 
7951 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
7952 
7953 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
7954 
7955 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
7956 
7957 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
7958 
7959 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
7960 
7961 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7962 
7963 #define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7964 
7974 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
7975 
7976 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
7977 
7978 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
7979 
7980 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
7981 
7982 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
7983 
7984 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
7985 
7986 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7987 
7988 #define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7989 
7999 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
8000 
8001 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
8002 
8003 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
8004 
8005 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
8006 
8007 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
8008 
8009 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
8010 
8011 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8012 
8013 #define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8014 
8026 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
8027 
8028 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
8029 
8030 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
8031 
8032 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
8033 
8034 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8035 
8036 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
8037 
8038 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8039 
8040 #define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8041 
8051 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
8052 
8053 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
8054 
8055 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
8056 
8057 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
8058 
8059 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8060 
8061 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
8062 
8063 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8064 
8065 #define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8066 
8067 #ifndef __ASSEMBLY__
8068 
8079 {
8080  uint32_t ecc_uncor_err : 1;
8081  uint32_t : 1;
8082  uint32_t dma_cmd_comp : 1;
8083  uint32_t time_out : 1;
8084  uint32_t program_fail : 1;
8085  uint32_t erase_fail : 1;
8086  uint32_t load_comp : 1;
8087  uint32_t program_comp : 1;
8088  uint32_t erase_comp : 1;
8089  uint32_t pipe_cpybck_cmd_comp : 1;
8090  uint32_t locked_blk : 1;
8091  uint32_t unsup_cmd : 1;
8092  uint32_t INT_act : 1;
8093  uint32_t rst_comp : 1;
8094  uint32_t pipe_cmd_err : 1;
8095  uint32_t page_xfer_inc : 1;
8096  uint32_t : 16;
8097 };
8098 
8101 #endif /* __ASSEMBLY__ */
8102 
8104 #define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
8105 
8129 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
8130 
8131 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
8132 
8133 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
8134 
8135 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
8136 
8137 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
8138 
8139 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
8140 
8141 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8142 
8143 #define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8144 
8145 #ifndef __ASSEMBLY__
8146 
8157 {
8158  const uint32_t value : 8;
8159  uint32_t : 24;
8160 };
8161 
8164 #endif /* __ASSEMBLY__ */
8165 
8167 #define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
8168 
8191 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
8192 
8193 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
8194 
8195 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
8196 
8197 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
8198 
8199 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
8200 
8201 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
8202 
8203 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8204 
8205 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8206 
8207 #ifndef __ASSEMBLY__
8208 
8219 {
8220  const uint32_t value : 16;
8221  uint32_t : 16;
8222 };
8223 
8226 #endif /* __ASSEMBLY__ */
8227 
8229 #define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
8230 
8254 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
8255 
8256 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
8257 
8258 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
8259 
8260 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
8261 
8262 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
8263 
8264 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
8265 
8266 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8267 
8268 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8269 
8270 #ifndef __ASSEMBLY__
8271 
8282 {
8283  const uint32_t value : 16;
8284  uint32_t : 16;
8285 };
8286 
8289 #endif /* __ASSEMBLY__ */
8290 
8292 #define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
8293 
8331 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
8332 
8333 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
8334 
8335 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
8336 
8337 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8338 
8339 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8340 
8341 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
8342 
8343 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8344 
8345 #define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8346 
8356 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
8357 
8358 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
8359 
8360 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
8361 
8362 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
8363 
8364 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8365 
8366 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
8367 
8368 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8369 
8370 #define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8371 
8382 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
8383 
8384 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
8385 
8386 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
8387 
8388 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
8389 
8390 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
8391 
8392 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
8393 
8394 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8395 
8396 #define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8397 
8409 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
8410 
8411 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
8412 
8413 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
8414 
8415 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
8416 
8417 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8418 
8419 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
8420 
8421 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8422 
8423 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8424 
8436 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
8437 
8438 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
8439 
8440 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
8441 
8442 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
8443 
8444 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
8445 
8446 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
8447 
8448 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8449 
8450 #define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8451 
8461 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
8462 
8463 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
8464 
8465 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
8466 
8467 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
8468 
8469 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
8470 
8471 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
8472 
8473 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8474 
8475 #define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8476 
8486 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
8487 
8488 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
8489 
8490 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
8491 
8492 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
8493 
8494 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8495 
8496 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
8497 
8498 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8499 
8500 #define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8501 
8511 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
8512 
8513 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
8514 
8515 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
8516 
8517 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
8518 
8519 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
8520 
8521 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
8522 
8523 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8524 
8525 #define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8526 
8537 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
8538 
8539 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
8540 
8541 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8542 
8543 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8544 
8545 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8546 
8547 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8548 
8549 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8550 
8551 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8552 
8563 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
8564 
8565 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
8566 
8567 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
8568 
8569 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
8570 
8571 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
8572 
8573 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
8574 
8575 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8576 
8577 #define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8578 
8589 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
8590 
8591 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
8592 
8593 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
8594 
8595 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
8596 
8597 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
8598 
8599 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
8600 
8601 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8602 
8603 #define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8604 
8614 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
8615 
8616 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
8617 
8618 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
8619 
8620 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
8621 
8622 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
8623 
8624 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
8625 
8626 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8627 
8628 #define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8629 
8640 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
8641 
8642 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
8643 
8644 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
8645 
8646 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
8647 
8648 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
8649 
8650 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
8651 
8652 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8653 
8654 #define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8655 
8667 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
8668 
8669 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
8670 
8671 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
8672 
8673 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
8674 
8675 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8676 
8677 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
8678 
8679 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8680 
8681 #define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8682 
8692 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
8693 
8694 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
8695 
8696 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
8697 
8698 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
8699 
8700 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8701 
8702 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
8703 
8704 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8705 
8706 #define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8707 
8708 #ifndef __ASSEMBLY__
8709 
8720 {
8721  uint32_t ecc_uncor_err : 1;
8722  uint32_t : 1;
8723  uint32_t dma_cmd_comp : 1;
8724  uint32_t time_out : 1;
8725  uint32_t program_fail : 1;
8726  uint32_t erase_fail : 1;
8727  uint32_t load_comp : 1;
8728  uint32_t program_comp : 1;
8729  uint32_t erase_comp : 1;
8730  uint32_t pipe_cpybck_cmd_comp : 1;
8731  uint32_t locked_blk : 1;
8732  uint32_t unsup_cmd : 1;
8733  uint32_t INT_act : 1;
8734  uint32_t rst_comp : 1;
8735  uint32_t pipe_cmd_err : 1;
8736  uint32_t page_xfer_inc : 1;
8737  uint32_t : 16;
8738 };
8739 
8742 #endif /* __ASSEMBLY__ */
8743 
8745 #define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
8746 
8785 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
8786 
8787 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
8788 
8789 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
8790 
8791 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
8792 
8793 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8794 
8795 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
8796 
8797 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8798 
8799 #define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8800 
8810 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
8811 
8812 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
8813 
8814 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
8815 
8816 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
8817 
8818 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8819 
8820 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
8821 
8822 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8823 
8824 #define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8825 
8836 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
8837 
8838 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
8839 
8840 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
8841 
8842 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
8843 
8844 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
8845 
8846 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
8847 
8848 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8849 
8850 #define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8851 
8863 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
8864 
8865 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
8866 
8867 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
8868 
8869 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
8870 
8871 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
8872 
8873 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
8874 
8875 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8876 
8877 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8878 
8890 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
8891 
8892 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
8893 
8894 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
8895 
8896 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
8897 
8898 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
8899 
8900 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
8901 
8902 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8903 
8904 #define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8905 
8915 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
8916 
8917 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
8918 
8919 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
8920 
8921 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
8922 
8923 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
8924 
8925 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
8926 
8927 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8928 
8929 #define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8930 
8940 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
8941 
8942 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
8943 
8944 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
8945 
8946 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
8947 
8948 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
8949 
8950 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
8951 
8952 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8953 
8954 #define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8955 
8965 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
8966 
8967 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
8968 
8969 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
8970 
8971 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
8972 
8973 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
8974 
8975 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
8976 
8977 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8978 
8979 #define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8980 
8991 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
8992 
8993 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
8994 
8995 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8996 
8997 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8998 
8999 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9000 
9001 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9002 
9003 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9004 
9005 #define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9006 
9017 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
9018 
9019 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
9020 
9021 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
9022 
9023 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
9024 
9025 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
9026 
9027 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
9028 
9029 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9030 
9031 #define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9032 
9043 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
9044 
9045 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
9046 
9047 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
9048 
9049 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
9050 
9051 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9052 
9053 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
9054 
9055 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9056 
9057 #define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9058 
9068 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
9069 
9070 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
9071 
9072 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
9073 
9074 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
9075 
9076 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
9077 
9078 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
9079 
9080 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9081 
9082 #define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9083 
9093 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
9094 
9095 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
9096 
9097 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
9098 
9099 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
9100 
9101 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
9102 
9103 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
9104 
9105 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9106 
9107 #define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9108 
9120 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
9121 
9122 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
9123 
9124 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
9125 
9126 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
9127 
9128 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9129 
9130 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
9131 
9132 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9133 
9134 #define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9135 
9145 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
9146 
9147 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
9148 
9149 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
9150 
9151 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
9152 
9153 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9154 
9155 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
9156 
9157 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9158 
9159 #define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9160 
9161 #ifndef __ASSEMBLY__
9162 
9173 {
9174  uint32_t ecc_uncor_err : 1;
9175  uint32_t : 1;
9176  uint32_t dma_cmd_comp : 1;
9177  uint32_t time_out : 1;
9178  uint32_t program_fail : 1;
9179  uint32_t erase_fail : 1;
9180  uint32_t load_comp : 1;
9181  uint32_t program_comp : 1;
9182  uint32_t erase_comp : 1;
9183  uint32_t pipe_cpybck_cmd_comp : 1;
9184  uint32_t locked_blk : 1;
9185  uint32_t unsup_cmd : 1;
9186  uint32_t INT_act : 1;
9187  uint32_t rst_comp : 1;
9188  uint32_t pipe_cmd_err : 1;
9189  uint32_t page_xfer_inc : 1;
9190  uint32_t : 16;
9191 };
9192 
9195 #endif /* __ASSEMBLY__ */
9196 
9198 #define ALT_NAND_STAT_INTR_EN3_OFST 0x110
9199 
9223 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
9224 
9225 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
9226 
9227 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
9228 
9229 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
9230 
9231 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
9232 
9233 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
9234 
9235 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9236 
9237 #define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9238 
9239 #ifndef __ASSEMBLY__
9240 
9251 {
9252  const uint32_t value : 8;
9253  uint32_t : 24;
9254 };
9255 
9258 #endif /* __ASSEMBLY__ */
9259 
9261 #define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
9262 
9285 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
9286 
9287 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
9288 
9289 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
9290 
9291 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
9292 
9293 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
9294 
9295 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
9296 
9297 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9298 
9299 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9300 
9301 #ifndef __ASSEMBLY__
9302 
9313 {
9314  const uint32_t value : 16;
9315  uint32_t : 16;
9316 };
9317 
9320 #endif /* __ASSEMBLY__ */
9321 
9323 #define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
9324 
9348 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
9349 
9350 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
9351 
9352 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
9353 
9354 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
9355 
9356 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
9357 
9358 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
9359 
9360 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9361 
9362 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9363 
9364 #ifndef __ASSEMBLY__
9365 
9376 {
9377  const uint32_t value : 16;
9378  uint32_t : 16;
9379 };
9380 
9383 #endif /* __ASSEMBLY__ */
9384 
9386 #define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
9387 
9388 #ifndef __ASSEMBLY__
9389 
9400 {
9402  volatile uint32_t _pad_0x4_0xf[3];
9404  volatile uint32_t _pad_0x14_0x1f[3];
9406  volatile uint32_t _pad_0x24_0x2f[3];
9408  volatile uint32_t _pad_0x34_0x3f[3];
9410  volatile uint32_t _pad_0x44_0x4f[3];
9412  volatile uint32_t _pad_0x54_0x5f[3];
9414  volatile uint32_t _pad_0x64_0x6f[3];
9416  volatile uint32_t _pad_0x74_0x7f[3];
9418  volatile uint32_t _pad_0x84_0x8f[3];
9420  volatile uint32_t _pad_0x94_0x9f[3];
9422  volatile uint32_t _pad_0xa4_0xaf[3];
9424  volatile uint32_t _pad_0xb4_0xbf[3];
9426  volatile uint32_t _pad_0xc4_0xcf[3];
9428  volatile uint32_t _pad_0xd4_0xdf[3];
9430  volatile uint32_t _pad_0xe4_0xef[3];
9432  volatile uint32_t _pad_0xf4_0xff[3];
9434  volatile uint32_t _pad_0x104_0x10f[3];
9436  volatile uint32_t _pad_0x114_0x11f[3];
9438  volatile uint32_t _pad_0x124_0x12f[3];
9440  volatile uint32_t _pad_0x134_0x13f[3];
9442 };
9443 
9445 typedef volatile struct ALT_NAND_STAT_s ALT_NAND_STAT_t;
9448 {
9449  volatile uint32_t transfer_mode;
9450  volatile uint32_t _pad_0x4_0xf[3];
9451  volatile uint32_t intr_status0;
9452  volatile uint32_t _pad_0x14_0x1f[3];
9453  volatile uint32_t intr_en0;
9454  volatile uint32_t _pad_0x24_0x2f[3];
9455  volatile uint32_t page_cnt0;
9456  volatile uint32_t _pad_0x34_0x3f[3];
9457  volatile uint32_t err_page_addr0;
9458  volatile uint32_t _pad_0x44_0x4f[3];
9459  volatile uint32_t err_block_addr0;
9460  volatile uint32_t _pad_0x54_0x5f[3];
9461  volatile uint32_t intr_status1;
9462  volatile uint32_t _pad_0x64_0x6f[3];
9463  volatile uint32_t intr_en1;
9464  volatile uint32_t _pad_0x74_0x7f[3];
9465  volatile uint32_t page_cnt1;
9466  volatile uint32_t _pad_0x84_0x8f[3];
9467  volatile uint32_t err_page_addr1;
9468  volatile uint32_t _pad_0x94_0x9f[3];
9469  volatile uint32_t err_block_addr1;
9470  volatile uint32_t _pad_0xa4_0xaf[3];
9471  volatile uint32_t intr_status2;
9472  volatile uint32_t _pad_0xb4_0xbf[3];
9473  volatile uint32_t intr_en2;
9474  volatile uint32_t _pad_0xc4_0xcf[3];
9475  volatile uint32_t page_cnt2;
9476  volatile uint32_t _pad_0xd4_0xdf[3];
9477  volatile uint32_t err_page_addr2;
9478  volatile uint32_t _pad_0xe4_0xef[3];
9479  volatile uint32_t err_block_addr2;
9480  volatile uint32_t _pad_0xf4_0xff[3];
9481  volatile uint32_t intr_status3;
9482  volatile uint32_t _pad_0x104_0x10f[3];
9483  volatile uint32_t intr_en3;
9484  volatile uint32_t _pad_0x114_0x11f[3];
9485  volatile uint32_t page_cnt3;
9486  volatile uint32_t _pad_0x124_0x12f[3];
9487  volatile uint32_t err_page_addr3;
9488  volatile uint32_t _pad_0x134_0x13f[3];
9489  volatile uint32_t err_block_addr3;
9490 };
9491 
9494 #endif /* __ASSEMBLY__ */
9495 
9532 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
9533 
9534 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
9535 
9536 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
9537 
9538 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
9539 
9540 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
9541 
9542 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
9543 
9544 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
9545 
9546 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
9547 
9558 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
9559 
9560 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
9561 
9562 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
9563 
9564 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
9565 
9566 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
9567 
9568 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
9569 
9570 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
9571 
9572 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
9573 
9585 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
9586 
9587 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
9588 
9589 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
9590 
9591 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
9592 
9593 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
9594 
9595 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
9596 
9597 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
9598 
9599 #define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
9600 
9611 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
9612 
9613 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
9614 
9615 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
9616 
9617 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
9618 
9619 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
9620 
9621 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
9622 
9623 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
9624 
9625 #define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
9626 
9627 #ifndef __ASSEMBLY__
9628 
9639 {
9640  const uint32_t max_errors_b0 : 7;
9641  const uint32_t uncor_err_b0 : 1;
9642  const uint32_t max_errors_b1 : 7;
9643  const uint32_t uncor_err_b1 : 1;
9644  uint32_t : 16;
9645 };
9646 
9649 #endif /* __ASSEMBLY__ */
9650 
9652 #define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
9653 
9683 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
9684 
9685 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
9686 
9687 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
9688 
9689 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
9690 
9691 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
9692 
9693 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
9694 
9695 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
9696 
9697 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
9698 
9709 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
9710 
9711 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
9712 
9713 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
9714 
9715 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
9716 
9717 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
9718 
9719 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
9720 
9721 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
9722 
9723 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
9724 
9736 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
9737 
9738 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
9739 
9740 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
9741 
9742 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
9743 
9744 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
9745 
9746 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
9747 
9748 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
9749 
9750 #define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
9751 
9762 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
9763 
9764 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
9765 
9766 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
9767 
9768 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
9769 
9770 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
9771 
9772 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
9773 
9774 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
9775 
9776 #define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
9777 
9778 #ifndef __ASSEMBLY__
9779 
9790 {
9791  const uint32_t max_errors_b2 : 7;
9792  const uint32_t uncor_err_b2 : 1;
9793  const uint32_t max_errors_b3 : 7;
9794  const uint32_t uncor_err_b3 : 1;
9795  uint32_t : 16;
9796 };
9797 
9800 #endif /* __ASSEMBLY__ */
9801 
9803 #define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
9804 
9805 #ifndef __ASSEMBLY__
9806 
9817 {
9819  volatile uint32_t _pad_0x4_0xf[3];
9821 };
9822 
9824 typedef volatile struct ALT_NAND_ECC_s ALT_NAND_ECC_t;
9827 {
9828  volatile uint32_t ECCCorInfo_b01;
9829  volatile uint32_t _pad_0x4_0xf[3];
9830  volatile uint32_t ECCCorInfo_b23;
9831 };
9832 
9834 typedef volatile struct ALT_NAND_ECC_raw_s ALT_NAND_ECC_raw_t;
9835 #endif /* __ASSEMBLY__ */
9836 
9864 #define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
9865 
9866 #define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
9867 
9868 #define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
9869 
9870 #define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
9871 
9872 #define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
9873 
9874 #define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
9875 
9876 #define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
9877 
9878 #define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
9879 
9880 #ifndef __ASSEMBLY__
9881 
9892 {
9893  uint32_t flag : 1;
9894  uint32_t : 31;
9895 };
9896 
9899 #endif /* __ASSEMBLY__ */
9900 
9902 #define ALT_NAND_DMA_DMA_EN_OFST 0x0
9903 
9927 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
9928 
9929 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
9930 
9931 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
9932 
9933 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
9934 
9935 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
9936 
9937 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
9938 
9939 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
9940 
9941 #define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
9942 
9943 #ifndef __ASSEMBLY__
9944 
9955 {
9956  uint32_t target_error : 1;
9957  uint32_t : 31;
9958 };
9959 
9962 #endif /* __ASSEMBLY__ */
9963 
9965 #define ALT_NAND_DMA_DMA_INTR_OFST 0x20
9966 
9990 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
9991 
9992 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
9993 
9994 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
9995 
9996 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
9997 
9998 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
9999 
10000 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
10001 
10002 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
10003 
10004 #define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
10005 
10006 #ifndef __ASSEMBLY__
10007 
10018 {
10019  uint32_t target_error : 1;
10020  uint32_t : 31;
10021 };
10022 
10025 #endif /* __ASSEMBLY__ */
10026 
10028 #define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
10029 
10053 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
10054 
10055 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
10056 
10057 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
10058 
10059 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
10060 
10061 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
10062 
10063 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
10064 
10065 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10066 
10067 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10068 
10069 #ifndef __ASSEMBLY__
10070 
10081 {
10082  const uint32_t value : 16;
10083  uint32_t : 16;
10084 };
10085 
10088 #endif /* __ASSEMBLY__ */
10089 
10091 #define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
10092 
10116 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
10117 
10118 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
10119 
10120 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
10121 
10122 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
10123 
10124 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
10125 
10126 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
10127 
10128 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10129 
10130 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10131 
10132 #ifndef __ASSEMBLY__
10133 
10144 {
10145  const uint32_t value : 16;
10146  uint32_t : 16;
10147 };
10148 
10151 #endif /* __ASSEMBLY__ */
10152 
10154 #define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
10155 
10186 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
10187 
10188 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
10189 
10190 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
10191 
10192 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
10193 
10194 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
10195 
10196 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
10197 
10198 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
10199 
10200 #define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
10201 
10213 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
10214 
10215 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
10216 
10217 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
10218 
10219 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
10220 
10221 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
10222 
10223 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
10224 
10225 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
10226 
10227 #define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
10228 
10238 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_LSB 8
10239 
10240 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_MSB 31
10241 
10242 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_WIDTH 24
10243 
10244 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET_MSK 0xffffff00
10245 
10246 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_CLR_MSK 0x000000ff
10247 
10248 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_RESET 0x0
10249 
10250 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_GET(value) (((value) & 0xffffff00) >> 8)
10251 
10252 #define ALT_NAND_DMA_FLSH_BURST_LEN_RSVD_SET(value) (((value) << 8) & 0xffffff00)
10253 
10254 #ifndef __ASSEMBLY__
10255 
10266 {
10267  uint32_t value : 2;
10268  uint32_t : 2;
10269  uint32_t continous_burst : 1;
10270  uint32_t : 3;
10271  uint32_t reserved : 24;
10272 };
10273 
10276 #endif /* __ASSEMBLY__ */
10277 
10279 #define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
10280 
10305 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
10306 
10307 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
10308 
10309 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
10310 
10311 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
10312 
10313 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
10314 
10315 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
10316 
10317 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
10318 
10319 #define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
10320 
10336 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
10337 
10338 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
10339 
10340 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
10341 
10342 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
10343 
10344 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
10345 
10346 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
10347 
10348 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
10349 
10350 #define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
10351 
10352 #ifndef __ASSEMBLY__
10353 
10364 {
10365  uint32_t chip_interleave_enable : 1;
10366  uint32_t : 3;
10368  uint32_t : 27;
10369 };
10370 
10373 #endif /* __ASSEMBLY__ */
10374 
10376 #define ALT_NAND_DMA_INTRLV_OFST 0x80
10377 
10404 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
10405 
10406 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
10407 
10408 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
10409 
10410 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
10411 
10412 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
10413 
10414 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
10415 
10416 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
10417 
10418 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
10419 
10420 #ifndef __ASSEMBLY__
10421 
10432 {
10433  uint32_t value : 4;
10434  uint32_t : 28;
10435 };
10436 
10439 #endif /* __ASSEMBLY__ */
10440 
10442 #define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0x90
10443 
10467 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
10468 
10469 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
10470 
10471 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
10472 
10473 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
10474 
10475 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
10476 
10477 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
10478 
10479 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10480 
10481 #define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10482 
10483 #ifndef __ASSEMBLY__
10484 
10495 {
10496  uint32_t value : 16;
10497  uint32_t : 16;
10498 };
10499 
10502 #endif /* __ASSEMBLY__ */
10503 
10505 #define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xa0
10506 
10507 #ifndef __ASSEMBLY__
10508 
10519 {
10521  volatile uint32_t _pad_0x4_0x1f[7];
10523  volatile uint32_t _pad_0x24_0x2f[3];
10525  volatile uint32_t _pad_0x34_0x3f[3];
10527  volatile uint32_t _pad_0x44_0x4f[3];
10529  volatile uint32_t _pad_0x54_0x6f[7];
10531  volatile uint32_t _pad_0x74_0x7f[3];
10533  volatile uint32_t _pad_0x84_0x8f[3];
10535  volatile uint32_t _pad_0x94_0x9f[3];
10537 };
10538 
10540 typedef volatile struct ALT_NAND_DMA_s ALT_NAND_DMA_t;
10543 {
10544  volatile uint32_t dma_enable;
10545  volatile uint32_t _pad_0x4_0x1f[7];
10546  volatile uint32_t dma_intr;
10547  volatile uint32_t _pad_0x24_0x2f[3];
10548  volatile uint32_t dma_intr_en;
10549  volatile uint32_t _pad_0x34_0x3f[3];
10550  volatile uint32_t target_err_addr_lo;
10551  volatile uint32_t _pad_0x44_0x4f[3];
10552  volatile uint32_t target_err_addr_hi;
10553  volatile uint32_t _pad_0x54_0x6f[7];
10554  volatile uint32_t flash_burst_length;
10555  volatile uint32_t _pad_0x74_0x7f[3];
10557  volatile uint32_t _pad_0x84_0x8f[3];
10558  volatile uint32_t no_of_blocks_per_lun;
10559  volatile uint32_t _pad_0x94_0x9f[3];
10560  volatile uint32_t lun_status_cmd;
10561 };
10562 
10564 typedef volatile struct ALT_NAND_DMA_raw_s ALT_NAND_DMA_raw_t;
10565 #endif /* __ASSEMBLY__ */
10566 
10568 #ifndef __ASSEMBLY__
10569 
10580 {
10582  volatile uint32_t _pad_0x2b4_0x2ff[19];
10584  volatile uint32_t _pad_0x3f4_0x3ff[3];
10586  volatile uint32_t _pad_0x544_0x64f[67];
10587  volatile ALT_NAND_ECC_t ecc;
10588  volatile uint32_t _pad_0x664_0x6ff[39];
10589  volatile ALT_NAND_DMA_t dma;
10590  volatile uint32_t _pad_0x7a4_0x800[23];
10591 };
10592 
10594 typedef volatile struct ALT_NAND_s ALT_NAND_t;
10597 {
10599  volatile uint32_t _pad_0x2b4_0x2ff[19];
10601  volatile uint32_t _pad_0x3f4_0x3ff[3];
10603  volatile uint32_t _pad_0x544_0x64f[67];
10605  volatile uint32_t _pad_0x664_0x6ff[39];
10607  volatile uint32_t _pad_0x7a4_0x800[23];
10608 };
10609 
10611 typedef volatile struct ALT_NAND_raw_s ALT_NAND_raw_t;
10612 #endif /* __ASSEMBLY__ */
10613 
10615 #ifdef __cplusplus
10616 }
10617 #endif /* __cplusplus */
10618 #endif /* __ALTERA_ALT_NAND_H__ */
10619