Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : twhr2_and_we_2_re

Description

Register Layout

Bits Access Reset Description
[5:0] RW 0x32 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE
[7:6] ??? 0x0 UNDEFINED
[13:8] RW 0x14 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2
[31:14] ??? 0x0 UNDEFINED

Field : we_2_re

Signifies the number of bus interface nand_mp_clk clocks that should be introduced between write enable going high to read enable going low. The number of clocks is the function of device parameter Twhr and controller clock frequency.

Field Access Macros:

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB   0
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB   5
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH   6
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK   0x0000003f
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK   0xffffffc0
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET   0x32
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value)   (((value) & 0x0000003f) >> 0)
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value)   (((value) << 0) & 0x0000003f)
 

Field : twhr2

Signifies the number of controller clocks that should be introduced between the last command of a random data output command to the start of the data transfer.

Field Access Macros:

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB   8
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB   13
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH   6
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK   0x00003f00
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK   0xffffc0ff
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET   0x14
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value)   (((value) & 0x00003f00) >> 8)
 
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value)   (((value) << 8) & 0x00003f00)
 

Data Structures

struct  ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
 

Macros

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST   0x100
 

Typedefs

typedef struct
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s 
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t
 

Data Structure Documentation

struct ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_TWHR2_AND_WE_2_RE.

Data Fields
uint32_t we_2_re: 6 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE
uint32_t __pad0__: 2 UNDEFINED
uint32_t twhr2: 6 ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2
uint32_t __pad1__: 18 UNDEFINED

Macro Definitions

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB   5

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH   6

The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK   0x0000003f

The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK   0xffffffc0

The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET   0x32

The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET (   value)    (((value) & 0x0000003f) >> 0)

Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE field value from a register.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET (   value)    (((value) << 0) & 0x0000003f)

Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE register field value suitable for setting the register.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB   8

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB   13

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH   6

The width in bits of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK   0x00003f00

The mask used to set the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK   0xffffc0ff

The mask used to clear the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET   0x14

The reset value of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET (   value)    (((value) & 0x00003f00) >> 8)

Extracts the ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 field value from a register.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET (   value)    (((value) << 8) & 0x00003f00)

Produces a ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2 register field value suitable for setting the register.

#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST   0x100

The byte offset of the ALT_NAND_CFG_TWHR2_AND_WE_2_RE register from the beginning of the component.

Typedef Documentation