Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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alt_clock_group.h File Reference
#include "hwlib.h"
#include "socal/alt_clkmgr.h"

Go to the source code of this file.

Detailed Description

Contains the definition of an opaque data structure that contains raw configuration information for a clock group.

Data Structures

struct  ALT_CLK_GROUP_RAW_CFG_s
 
union  ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u
 
union  ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.mainpllgrp
 
union  ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.perpllgrp
 
union  ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.sdrpllgrp
 

Typedefs

typedef enum ALT_CLK_GRP_e ALT_CLK_GRP_t
 
typedef struct
ALT_CLK_GROUP_RAW_CFG_s 
ALT_CLK_GROUP_RAW_CFG_t
 

Enumerations

enum  ALT_CLK_GRP_e { ALT_MAIN_PLL_CLK_GRP, ALT_PERIPH_PLL_CLK_GRP, ALT_SDRAM_PLL_CLK_GRP }
 

Data Structure Documentation

struct ALT_CLK_GROUP_RAW_CFG_s

This type definition defines an opaque data structure for holding the configuration settings for a complete clock group.

Data Fields
uint32_t verid SoC FPGA version identifier. This field encapsulates the silicon identifier and version information associated with this clock group configuration. It is used to assert that this clock group configuration is valid for this device.
uint32_t siliid2 Reserved register - reserved for future device IDs or capability flags.
ALT_CLK_GRP_t clkgrpsel Clock group union discriminator.
union ALT_CLK_GROUP_RAW_CFG_u clkgrp
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u

This union holds the register values for configuration of the set of possible clock groups on the SoC FPGA. The clkgrpsel discriminator identifies the valid clock group union data member.

union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.mainpllgrp

Clock group configuration for Main PLL group.

Data Fields
ALT_CLKMGR_MAINPLL_t fld Field access.
ALT_CLKMGR_MAINPLL_raw_t raw Raw access.
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.perpllgrp

Clock group configuration for Peripheral PLL group.

Data Fields
ALT_CLKMGR_PERPLL_t fld Field access.
ALT_CLKMGR_PERPLL_raw_t raw Raw access.
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.sdrpllgrp

Clock group configuration for SDRAM PLL group.

Data Fields
ALT_CLKMGR_SDRPLL_t fld Field access.
ALT_CLKMGR_SDRPLL_raw_t raw Raw access.

Typedef Documentation

This type definition enumerates the clock groups

This type definition defines an opaque data structure for holding the configuration settings for a complete clock group.

Enumeration Type Documentation

This type definition enumerates the clock groups

Enumerator:
ALT_MAIN_PLL_CLK_GRP 

Main PLL clock group

ALT_PERIPH_PLL_CLK_GRP 

Peripheral PLL clock group

ALT_SDRAM_PLL_CLK_GRP 

SDRAM PLL clock group