Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 SPIM Peripherals Security - l4spim

Description

Controls security settings for L4 SPIM peripherals.

Register Layout

Bits Access Reset Description
[0] W 0x0 SPI Master 0 Security
[1] W 0x0 SPI Master 1 Security
[2] W 0x0 Scan Manager Security
[31:3] ??? 0x0 UNDEFINED

Field : SPI Master 0 Security - spim0

Controls whether secure or non-secure masters can access the SPI Master 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SPIM_SPIM0_LSB   0
 
#define ALT_L3_SEC_L4SPIM_SPIM0_MSB   0
 
#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH   1
 
#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK   0x00000001
 
#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK   0xfffffffe
 
#define ALT_L3_SEC_L4SPIM_SPIM0_RESET   0x0
 
#define ALT_L3_SEC_L4SPIM_SPIM0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L3_SEC_L4SPIM_SPIM0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : SPI Master 1 Security - spim1

Controls whether secure or non-secure masters can access the SPI Master 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SPIM_SPIM1_LSB   1
 
#define ALT_L3_SEC_L4SPIM_SPIM1_MSB   1
 
#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH   1
 
#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK   0x00000002
 
#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK   0xfffffffd
 
#define ALT_L3_SEC_L4SPIM_SPIM1_RESET   0x0
 
#define ALT_L3_SEC_L4SPIM_SPIM1_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L3_SEC_L4SPIM_SPIM1_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Scan Manager Security - scanmgr

Controls whether secure or non-secure masters can access the Scan Manager slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB   2
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB   2
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH   1
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK   0x00000004
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK   0xfffffffb
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET   0x0
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_L3_SEC_L4SPIM_SCANMGR_SET(value)   (((value) << 2) & 0x00000004)
 

Data Structures

struct  ALT_L3_SEC_L4SPIM_s
 

Macros

#define ALT_L3_SEC_L4SPIM_OFST   0x10
 

Typedefs

typedef struct ALT_L3_SEC_L4SPIM_s ALT_L3_SEC_L4SPIM_t
 

Data Structure Documentation

struct ALT_L3_SEC_L4SPIM_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L3_SEC_L4SPIM.

Data Fields
uint32_t spim0: 1 SPI Master 0 Security
uint32_t spim1: 1 SPI Master 1 Security
uint32_t scanmgr: 1 Scan Manager Security
uint32_t __pad0__: 29 UNDEFINED

Macro Definitions

#define ALT_L3_SEC_L4SPIM_SPIM0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SPIM_SPIM0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SPIM_SPIM0_LSB   0

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field.

#define ALT_L3_SEC_L4SPIM_SPIM0_MSB   0

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM0 register field.

#define ALT_L3_SEC_L4SPIM_SPIM0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SPIM_SPIM0 register field.

#define ALT_L3_SEC_L4SPIM_SPIM0_SET_MSK   0x00000001

The mask used to set the ALT_L3_SEC_L4SPIM_SPIM0 register field value.

#define ALT_L3_SEC_L4SPIM_SPIM0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM0 register field value.

#define ALT_L3_SEC_L4SPIM_SPIM0_RESET   0x0

The reset value of the ALT_L3_SEC_L4SPIM_SPIM0 register field.

#define ALT_L3_SEC_L4SPIM_SPIM0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L3_SEC_L4SPIM_SPIM0 field value from a register.

#define ALT_L3_SEC_L4SPIM_SPIM0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L3_SEC_L4SPIM_SPIM0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SPIM_SPIM1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SPIM_SPIM1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SPIM_SPIM1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SPIM_SPIM1_LSB   1

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field.

#define ALT_L3_SEC_L4SPIM_SPIM1_MSB   1

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SPIM1 register field.

#define ALT_L3_SEC_L4SPIM_SPIM1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SPIM_SPIM1 register field.

#define ALT_L3_SEC_L4SPIM_SPIM1_SET_MSK   0x00000002

The mask used to set the ALT_L3_SEC_L4SPIM_SPIM1 register field value.

#define ALT_L3_SEC_L4SPIM_SPIM1_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L3_SEC_L4SPIM_SPIM1 register field value.

#define ALT_L3_SEC_L4SPIM_SPIM1_RESET   0x0

The reset value of the ALT_L3_SEC_L4SPIM_SPIM1 register field.

#define ALT_L3_SEC_L4SPIM_SPIM1_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L3_SEC_L4SPIM_SPIM1 field value from a register.

#define ALT_L3_SEC_L4SPIM_SPIM1_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L3_SEC_L4SPIM_SPIM1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SPIM_SCANMGR_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SPIM_SCANMGR_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SPIM_SCANMGR

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SPIM_SCANMGR_LSB   2

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field.

#define ALT_L3_SEC_L4SPIM_SCANMGR_MSB   2

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SPIM_SCANMGR register field.

#define ALT_L3_SEC_L4SPIM_SCANMGR_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SPIM_SCANMGR register field.

#define ALT_L3_SEC_L4SPIM_SCANMGR_SET_MSK   0x00000004

The mask used to set the ALT_L3_SEC_L4SPIM_SCANMGR register field value.

#define ALT_L3_SEC_L4SPIM_SCANMGR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_L3_SEC_L4SPIM_SCANMGR register field value.

#define ALT_L3_SEC_L4SPIM_SCANMGR_RESET   0x0

The reset value of the ALT_L3_SEC_L4SPIM_SCANMGR register field.

#define ALT_L3_SEC_L4SPIM_SCANMGR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_L3_SEC_L4SPIM_SCANMGR field value from a register.

#define ALT_L3_SEC_L4SPIM_SCANMGR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_L3_SEC_L4SPIM_SCANMGR register field value suitable for setting the register.

#define ALT_L3_SEC_L4SPIM_OFST   0x10

The byte offset of the ALT_L3_SEC_L4SPIM register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_L3_SEC_L4SPIM.