Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : caltiming8

Description

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID
[8:4] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID
[12:9] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE
[16:13] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS
[19:17] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY
[27:20] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID
[31:28] ??? 0x0 UNDEFINED

Field : cfg_t_param_mrr_to_valid

Timing parameter for Mode Register Read to any valid command

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB   0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB   3
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK   0x0000000f
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK   0xfffffff0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : cfg_t_param_mpr_to_valid

Timing parameter for Multi Purpose Register Read to any valid command

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB   4
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB   8
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK   0x000001f0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK   0xfffffe0f
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value)   (((value) & 0x000001f0) >> 4)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value)   (((value) << 4) & 0x000001f0)
 

Field : cfg_t_param_mps_exit_cs_to_cke

Timing parameter for exit Maximum Power Saving. Timing requirement for CS assertion vs CKE de-assertion. tMPX_S

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB   9
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB   12
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK   0x00001e00
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK   0xffffe1ff
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value)   (((value) & 0x00001e00) >> 9)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value)   (((value) << 9) & 0x00001e00)
 

Field : cfg_t_param_mps_exit_cke_to_cs

Timing parameter for exit Maximum Power Saving. Timing requirement for CKE de- assertion vs CS de-assertion. tMPX_LH

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB   13
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB   16
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK   0x0001e000
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK   0xfffe1fff
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value)   (((value) & 0x0001e000) >> 13)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value)   (((value) << 13) & 0x0001e000)
 

Field : cfg_t_param_rld3_multibank_ref_delay

RLD3 Refresh to Refresh Delay for all sequences

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB   17
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB   19
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK   0x000e0000
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK   0xfff1ffff
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : cfg_t_param_mmr_cmd_to_valid

MMR cmd to valid delay

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB   20
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB   27
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH   8
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK   0x0ff00000
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK   0xf00fffff
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value)   (((value) & 0x0ff00000) >> 20)
 
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value)   (((value) << 20) & 0x0ff00000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CALTIMING8_s
 

Macros

#define ALT_IO48_HMC_MMR_CALTIMING8_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CALTIMING8_OFST   0x9c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CALTIMING8_s 
ALT_IO48_HMC_MMR_CALTIMING8_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CALTIMING8_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING8.

Data Fields
uint32_t cfg_t_param_mrr_to_valid: 4 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID
uint32_t cfg_t_param_mpr_to_valid: 5 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID
uint32_t cfg_t_param_mps_exit_cs_to_cke: 4 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE
uint32_t cfg_t_param_mps_exit_cke_to_cs: 4 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS
uint32_t cfg_t_param_rld3_multibank_ref_delay: 3 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY
uint32_t cfg_t_param_mmr_cmd_to_valid: 8 ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID
uint32_t __pad0__: 4 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB   3

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK   0x0000000f

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK   0xfffffff0

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB   4

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK   0x000001f0

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK   0xfffffe0f

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET (   value)    (((value) & 0x000001f0) >> 4)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET (   value)    (((value) << 4) & 0x000001f0)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB   12

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK   0x00001e00

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK   0xffffe1ff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET (   value)    (((value) & 0x00001e00) >> 9)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET (   value)    (((value) << 9) & 0x00001e00)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB   13

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB   16

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK   0x0001e000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK   0xfffe1fff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET (   value)    (((value) & 0x0001e000) >> 13)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET (   value)    (((value) << 13) & 0x0001e000)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB   17

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB   19

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK   0x000e0000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET   0x0
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB   20

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB   27

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH   8

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK   0x0ff00000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK   0xf00fffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET (   value)    (((value) & 0x0ff00000) >> 20)

Extracts the ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET (   value)    (((value) << 20) & 0x0ff00000)

Produces a ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING8_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CALTIMING8 register.

#define ALT_IO48_HMC_MMR_CALTIMING8_OFST   0x9c

The byte offset of the ALT_IO48_HMC_MMR_CALTIMING8 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING8.