Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Device Read Instruction Register - devrd

Description

Register Layout

Bits Access Reset Description
[7:0] RW 0x3 Read Opcode in non-XIP mode
[9:8] RW 0x0 Instruction Transfer Width
[11:10] ??? 0x0 UNDEFINED
[13:12] RW 0x0 Address Transfer Width
[15:14] ??? 0x0 UNDEFINED
[17:16] RW 0x0 Data Transfer Width
[19:18] ??? 0x0 UNDEFINED
[20] RW 0x0 Mode Bit Enable
[23:21] ??? 0x0 UNDEFINED
[28:24] RW 0x0 Dummy Read Clock Cycles
[31:29] ??? 0x0 UNDEFINED

Field : Read Opcode in non-XIP mode - rdopcode

Read Opcode to use when not in XIP mode

Field Enumeration Values:

Enum Value Description
ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 Read Opcode in Non-XIP mode
ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb Fast Read in Non-XIP mode

Field Access Macros:

#define ALT_QSPI_DEVRD_RDOPCODE_E_RD   0x3
 
#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD   0xb
 
#define ALT_QSPI_DEVRD_RDOPCODE_LSB   0
 
#define ALT_QSPI_DEVRD_RDOPCODE_MSB   7
 
#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH   8
 
#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK   0x000000ff
 
#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK   0xffffff00
 
#define ALT_QSPI_DEVRD_RDOPCODE_RESET   0x3
 
#define ALT_QSPI_DEVRD_RDOPCODE_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_QSPI_DEVRD_RDOPCODE_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : Instruction Transfer Width - instwidth

Sets instruction transfer width (1, 2, or 4 bits). Applies to all instructions sent to SPI flash device (not just read instructions).

Field Enumeration Values:

Enum Value Description
ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 Instruction transferred on DQ0. Supported by all
: SPI flash devices.
ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 Instruction transferred on DQ0 and DQ1.
: Supported by all SPI flash devices that support
: the Dual SP (DIO-SPI) Protocol.
ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 Instruction transferred on DQ0, DQ1, DQ2, and
: DQ3. Supported by all SPI flash devices that
: support the Quad SP (QIO-SPI) Protocol.

Field Access Macros:

#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE   0x0
 
#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL   0x1
 
#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD   0x2
 
#define ALT_QSPI_DEVRD_INSTWIDTH_LSB   8
 
#define ALT_QSPI_DEVRD_INSTWIDTH_MSB   9
 
#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH   2
 
#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK   0x00000300
 
#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK   0xfffffcff
 
#define ALT_QSPI_DEVRD_INSTWIDTH_RESET   0x0
 
#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value)   (((value) & 0x00000300) >> 8)
 
#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value)   (((value) << 8) & 0x00000300)
 

Field : Address Transfer Width - addrwidth

Sets read address transfer width (1, 2, or 4 bits).

Field Enumeration Values:

Enum Value Description
ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 Read address transferred on DQ0. Supported by
: all SPI flash devices
ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 Read address transferred on DQ0 and DQ1.
: Supported by some SPI flash devices that support
: the Extended SPI Protocol and by all SPI flash
: devices that support the Dual SP (DIO-SPI)
: Protocol.
ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 Read address transferred on DQ0, DQ1, DQ2, and
: DQ3. Supported by some SPI flash devices that
: support the Extended SPI Protocol and by all SPI
: flash devices that support the Quad SP (QIO-SPI)
: Protocol.

Field Access Macros:

#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE   0x0
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL   0x1
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD   0x2
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB   12
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB   13
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH   2
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK   0x00003000
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK   0xffffcfff
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET   0x0
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value)   (((value) & 0x00003000) >> 12)
 
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value)   (((value) << 12) & 0x00003000)
 

Field : Data Transfer Width - datawidth

Sets read data transfer width (1, 2, or 4 bits).

Field Enumeration Values:

Enum Value Description
ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 Read data transferred on DQ0. Supported by all
: SPI flash devices
ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 Read data transferred on DQ0 and DQ1. Supported
: by some SPI flash devices that support the
: Extended SPI Protocol and by all SPI flash
: devices that support the Dual SP (DIO-SPI)
: Protocol.
ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 Read data transferred on DQ0, DQ1, DQ2, and DQ3.
: Supported by some SPI flash devices that support
: the Extended SPI Protocol and by all SPI flash
: devices that support the Quad SP (QIO-SPI)
: Protocol.

Field Access Macros:

#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE   0x0
 
#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL   0x1
 
#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD   0x2
 
#define ALT_QSPI_DEVRD_DATAWIDTH_LSB   16
 
#define ALT_QSPI_DEVRD_DATAWIDTH_MSB   17
 
#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH   2
 
#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK   0x00030000
 
#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK   0xfffcffff
 
#define ALT_QSPI_DEVRD_DATAWIDTH_RESET   0x0
 
#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value)   (((value) & 0x00030000) >> 16)
 
#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value)   (((value) << 16) & 0x00030000)
 

Field : Mode Bit Enable - enmodebits

If this bit is set, the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 No Order
ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 Mode Bits follow address bytes

Field Access Macros:

#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER   0x0
 
#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER   0x1
 
#define ALT_QSPI_DEVRD_ENMODBITS_LSB   20
 
#define ALT_QSPI_DEVRD_ENMODBITS_MSB   20
 
#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH   1
 
#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK   0x00100000
 
#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK   0xffefffff
 
#define ALT_QSPI_DEVRD_ENMODBITS_RESET   0x0
 
#define ALT_QSPI_DEVRD_ENMODBITS_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_QSPI_DEVRD_ENMODBITS_SET(value)   (((value) << 20) & 0x00100000)
 

Field : Dummy Read Clock Cycles - dummyrdclks

Number of dummy clock cycles required by device for read instruction.

Field Access Macros:

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB   24
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB   28
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH   5
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK   0x1f000000
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK   0xe0ffffff
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET   0x0
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value)   (((value) & 0x1f000000) >> 24)
 
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value)   (((value) << 24) & 0x1f000000)
 

Data Structures

struct  ALT_QSPI_DEVRD_s
 

Macros

#define ALT_QSPI_DEVRD_OFST   0x4
 

Typedefs

typedef struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t
 

Data Structure Documentation

struct ALT_QSPI_DEVRD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_QSPI_DEVRD.

Data Fields
uint32_t rdopcode: 8 Read Opcode in non-XIP mode
uint32_t instwidth: 2 Instruction Transfer Width
uint32_t __pad0__: 2 UNDEFINED
uint32_t addrwidth: 2 Address Transfer Width
uint32_t __pad1__: 2 UNDEFINED
uint32_t datawidth: 2 Data Transfer Width
uint32_t __pad2__: 2 UNDEFINED
uint32_t enmodebits: 1 Mode Bit Enable
uint32_t __pad3__: 3 UNDEFINED
uint32_t dummyrdclks: 5 Dummy Read Clock Cycles
uint32_t __pad4__: 3 UNDEFINED

Macro Definitions

#define ALT_QSPI_DEVRD_RDOPCODE_E_RD   0x3

Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE

Read Opcode in Non-XIP mode

#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD   0xb

Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE

Fast Read in Non-XIP mode

#define ALT_QSPI_DEVRD_RDOPCODE_LSB   0

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field.

#define ALT_QSPI_DEVRD_RDOPCODE_MSB   7

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field.

#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH   8

The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field.

#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK   0x000000ff

The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value.

#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK   0xffffff00

The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value.

#define ALT_QSPI_DEVRD_RDOPCODE_RESET   0x3

The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field.

#define ALT_QSPI_DEVRD_RDOPCODE_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register.

#define ALT_QSPI_DEVRD_RDOPCODE_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE   0x0

Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH

Instruction transferred on DQ0. Supported by all SPI flash devices.

#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL   0x1

Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH

Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD   0x2

Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH

Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_INSTWIDTH_LSB   8

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field.

#define ALT_QSPI_DEVRD_INSTWIDTH_MSB   9

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field.

#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH   2

The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field.

#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK   0x00000300

The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value.

#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK   0xfffffcff

The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value.

#define ALT_QSPI_DEVRD_INSTWIDTH_RESET   0x0

The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field.

#define ALT_QSPI_DEVRD_INSTWIDTH_GET (   value)    (((value) & 0x00000300) >> 8)

Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register.

#define ALT_QSPI_DEVRD_INSTWIDTH_SET (   value)    (((value) << 8) & 0x00000300)

Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE   0x0

Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH

Read address transferred on DQ0. Supported by all SPI flash devices

#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL   0x1

Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH

Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD   0x2

Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH

Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB   12

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field.

#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB   13

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field.

#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH   2

The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field.

#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK   0x00003000

The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value.

#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK   0xffffcfff

The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value.

#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET   0x0

The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field.

#define ALT_QSPI_DEVRD_ADDRWIDTH_GET (   value)    (((value) & 0x00003000) >> 12)

Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register.

#define ALT_QSPI_DEVRD_ADDRWIDTH_SET (   value)    (((value) << 12) & 0x00003000)

Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE   0x0

Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH

Read data transferred on DQ0. Supported by all SPI flash devices

#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL   0x1

Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH

Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD   0x2

Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH

Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.

#define ALT_QSPI_DEVRD_DATAWIDTH_LSB   16

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field.

#define ALT_QSPI_DEVRD_DATAWIDTH_MSB   17

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field.

#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH   2

The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field.

#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK   0x00030000

The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value.

#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK   0xfffcffff

The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value.

#define ALT_QSPI_DEVRD_DATAWIDTH_RESET   0x0

The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field.

#define ALT_QSPI_DEVRD_DATAWIDTH_GET (   value)    (((value) & 0x00030000) >> 16)

Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register.

#define ALT_QSPI_DEVRD_DATAWIDTH_SET (   value)    (((value) << 16) & 0x00030000)

Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER   0x0

Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS

No Order

#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER   0x1

Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS

Mode Bits follow address bytes

#define ALT_QSPI_DEVRD_ENMODBITS_LSB   20

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field.

#define ALT_QSPI_DEVRD_ENMODBITS_MSB   20

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field.

#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH   1

The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field.

#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK   0x00100000

The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value.

#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK   0xffefffff

The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value.

#define ALT_QSPI_DEVRD_ENMODBITS_RESET   0x0

The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field.

#define ALT_QSPI_DEVRD_ENMODBITS_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register.

#define ALT_QSPI_DEVRD_ENMODBITS_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB   24

The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB   28

The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH   5

The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK   0x1f000000

The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK   0xe0ffffff

The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET   0x0

The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET (   value)    (((value) & 0x1f000000) >> 24)

Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register.

#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET (   value)    (((value) << 24) & 0x1f000000)

Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register.

#define ALT_QSPI_DEVRD_OFST   0x4

The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_QSPI_DEVRD.