Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECC_wdctrl

Description

Bits to Enable/Disable Watch Dog Timer

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM
[31:1] ??? 0x0 UNDEFINED

Field : WDEN_RAM

Enable watchdog timeout for OCP register access to IP RAM.

Field Access Macros:

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_LSB   0
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_MSB   0
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH   1
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK   0x00000001
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK   0xfffffffe
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_RESET   0x0
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET(value)   (((value) << 0) & 0x00000001)
 

Data Structures

struct  ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_s
 

Macros

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_RESET   0x00000000
 
#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_OFST   0x80
 

Typedefs

typedef struct
ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_s 
ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_t
 

Data Structure Documentation

struct ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL.

Data Fields
uint32_t WDEN_RAM: 1 ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM
uint32_t __pad0__: 31 UNDEFINED

Macro Definitions

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH   1

The width in bits of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK   0x00000001

The mask used to set the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field value.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field value.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_RESET   0x0

The reset value of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM field value from a register.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_WDEN_RAM register field value suitable for setting the register.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_RESET   0x00000000

The reset value of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL register.

#define ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL_OFST   0x80

The byte offset of the ALT_ECC_EMAC1_TX_ECC_ECC_WDCTL register from the beginning of the component.

Typedef Documentation