Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : read_mode

Description

The type of read sequence that the controller will follow for pipe read commands.

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_NAND_CFG_RD_MOD_VALUE
[31:4] ??? Unknown UNDEFINED

Field : value

The values in the field should be as follows[list]

[*]4'h0 - This value informs the controller that the pipe read sequence to follow is of

a normal read.

For 512 byte page devices, Normal read sequence is,

C00, Address, Data, .....

For devices with page size greater that 512 bytes, the sequence is,

C00, Address, C30, Data.....

[*]4'h1 - This value informs the controller that the pipe read sequence to follow is of

a Cache Read with the following sequence,

C00, Address, C30, C31, Data, C31, Data, ....., C3F, Data.

[*]4'h2 - This value informs the controller that the pipe read sequence to follow is of

a Cache Read with the following sequence,

C00, Address, C31, Data, Data, ....., C34.

[*]4'h3 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Read with the following sequence,

C00, Address, C00, Address, C30, Data, C06, Address, CE0, Data.....

[*]4'h4 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Read with the following sequence,

C60, Address, C60, Address, C30, C00, Address, C05, Address, CE0, Data, C00,

Address, C05, Address, CE0, Data.....

[*]4'h5 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Cache Read with the following sequence,

C60, Address, C60, Address, C30, C31, C00, Address, C05, Address, CE0, Data,

C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,

CE0, Data, C00, Address, C05, Address, CE0, Data

[*]4'h6 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Read with the following sequence,

C00, Address, C32, .., C00, Address, C30, C06, Address, CE0, Data,

C06, Address, CE0, Data,....

[*]4'h7 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Cache Read with the following sequence,

C00, Address, C32,..., C00, Address, C30, C31,C06, Address, CE0, Data,

C31, C06, Address, CE0, Data, C3F, C06, Address, CE0, Data....

[*]4'h8 - This value informs the controller that the pipe read sequence to follow is of

a 'N' Plane Cache Read with the following sequence,

C60, Address, C60, Address, C33, C31, C00, Address, C05, Address, CE0, Data,

C00, Address, C05, Address, CE0, Data, ....., C3F, C00, Address, C05, Address,

CE0, Data, C00, Address, C05, Address, CE0, Data

[*]4'h9 - 4'h15 - Reserved.

[/list]

..... indicates that the previous sequence is repeated till the last page.

Field Access Macros:

#define ALT_NAND_CFG_RD_MOD_VALUE_LSB   0
 
#define ALT_NAND_CFG_RD_MOD_VALUE_MSB   3
 
#define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH   4
 
#define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK   0x0000000f
 
#define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK   0xfffffff0
 
#define ALT_NAND_CFG_RD_MOD_VALUE_RESET   0x0
 
#define ALT_NAND_CFG_RD_MOD_VALUE_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_NAND_CFG_RD_MOD_VALUE_SET(value)   (((value) << 0) & 0x0000000f)
 

Data Structures

struct  ALT_NAND_CFG_RD_MOD_s
 

Macros

#define ALT_NAND_CFG_RD_MOD_RESET   0x00000000
 
#define ALT_NAND_CFG_RD_MOD_OFST   0x1c0
 

Typedefs

typedef struct
ALT_NAND_CFG_RD_MOD_s 
ALT_NAND_CFG_RD_MOD_t
 

Data Structure Documentation

struct ALT_NAND_CFG_RD_MOD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_RD_MOD.

Data Fields
uint32_t value: 4 ALT_NAND_CFG_RD_MOD_VALUE
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_NAND_CFG_RD_MOD_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field.

#define ALT_NAND_CFG_RD_MOD_VALUE_MSB   3

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RD_MOD_VALUE register field.

#define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH   4

The width in bits of the ALT_NAND_CFG_RD_MOD_VALUE register field.

#define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK   0x0000000f

The mask used to set the ALT_NAND_CFG_RD_MOD_VALUE register field value.

#define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK   0xfffffff0

The mask used to clear the ALT_NAND_CFG_RD_MOD_VALUE register field value.

#define ALT_NAND_CFG_RD_MOD_VALUE_RESET   0x0

The reset value of the ALT_NAND_CFG_RD_MOD_VALUE register field.

#define ALT_NAND_CFG_RD_MOD_VALUE_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_NAND_CFG_RD_MOD_VALUE field value from a register.

#define ALT_NAND_CFG_RD_MOD_VALUE_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_NAND_CFG_RD_MOD_VALUE register field value suitable for setting the register.

#define ALT_NAND_CFG_RD_MOD_RESET   0x00000000

The reset value of the ALT_NAND_CFG_RD_MOD register.

#define ALT_NAND_CFG_RD_MOD_OFST   0x1c0

The byte offset of the ALT_NAND_CFG_RD_MOD register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_CFG_RD_MOD.