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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register masks or enables all interrupts generated by the SPI Slave.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | Transmit FIFO Empty Interrupt Mask |
[1] | RW | 0x1 | Transmit FIFO Overflow Interrupt Mask |
[2] | RW | 0x1 | Receive FIFO Underflow Interrupt Mask |
[3] | RW | 0x1 | Receive FIFO Overflow Interrupt Mask |
[4] | RW | 0x1 | Receive FIFO Full Interrupt Mask |
[31:5] | ??? | 0x0 | UNDEFINED |
Field : Transmit FIFO Empty Interrupt Mask - txeim | ||||||||||
Empty mask. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SPIS_IMR_TXEIM_E_MSKED 0x0 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_E_END 0x1 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_LSB 0 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_MSB 0 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_WIDTH 1 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SPIS_IMR_TXEIM_RESET 0x1 | |||||||||
#define | ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : Transmit FIFO Overflow Interrupt Mask - txoim | ||||||||||
Overflow mask. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SPIS_IMR_TXOIM_E_MSKED 0x0 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_E_END 0x1 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_LSB 1 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_MSB 1 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_WIDTH 1 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SPIS_IMR_TXOIM_RESET 0x1 | |||||||||
#define | ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Receive FIFO Underflow Interrupt Mask - rxuim | ||||||||||
Underfow Mask Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SPIS_IMR_RXUIM_E_MSKED 0x0 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_E_END 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_LSB 2 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_MSB 2 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_WIDTH 1 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SPIS_IMR_RXUIM_RESET 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : Receive FIFO Overflow Interrupt Mask - rxoim | ||||||||||
Overflow Mask. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SPIS_IMR_RXOIM_E_MSKED 0x0 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_E_END 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_LSB 3 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_MSB 3 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_WIDTH 1 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_RESET 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Receive FIFO Full Interrupt Mask - rxfim | ||||||||||
FIFO Full Mask. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SPIS_IMR_RXFIM_E_MSKED 0x0 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_E_END 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_LSB 4 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_MSB 4 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_WIDTH 1 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SPIS_IMR_RXFIM_RESET 0x1 | |||||||||
#define | ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Data Structures | |
struct | ALT_SPIS_IMR_s |
Macros | |
#define | ALT_SPIS_IMR_OFST 0x2c |
#define | ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST)) |
Typedefs | |
typedef struct ALT_SPIS_IMR_s | ALT_SPIS_IMR_t |
struct ALT_SPIS_IMR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SPIS_IMR.
Data Fields | ||
---|---|---|
uint32_t | txeim: 1 | Transmit FIFO Empty Interrupt Mask |
uint32_t | txoim: 1 | Transmit FIFO Overflow Interrupt Mask |
uint32_t | rxuim: 1 | Receive FIFO Underflow Interrupt Mask |
uint32_t | rxoim: 1 | Receive FIFO Overflow Interrupt Mask |
uint32_t | rxfim: 1 | Receive FIFO Full Interrupt Mask |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0 |
Enumerated value for register field ALT_SPIS_IMR_TXEIM
spi_txe_intr interrupt is masked (disabled)
#define ALT_SPIS_IMR_TXEIM_E_END 0x1 |
Enumerated value for register field ALT_SPIS_IMR_TXEIM
spi_txe_intr interrupt is enabled
#define ALT_SPIS_IMR_TXEIM_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXEIM register field.
#define ALT_SPIS_IMR_TXEIM_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXEIM register field.
#define ALT_SPIS_IMR_TXEIM_WIDTH 1 |
The width in bits of the ALT_SPIS_IMR_TXEIM register field.
#define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001 |
The mask used to set the ALT_SPIS_IMR_TXEIM register field value.
#define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SPIS_IMR_TXEIM register field value.
#define ALT_SPIS_IMR_TXEIM_RESET 0x1 |
The reset value of the ALT_SPIS_IMR_TXEIM register field.
#define ALT_SPIS_IMR_TXEIM_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SPIS_IMR_TXEIM field value from a register.
#define ALT_SPIS_IMR_TXEIM_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SPIS_IMR_TXEIM register field value suitable for setting the register.
#define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0 |
Enumerated value for register field ALT_SPIS_IMR_TXOIM
spi_txo_intr interrupt is masked (disabled)
#define ALT_SPIS_IMR_TXOIM_E_END 0x1 |
Enumerated value for register field ALT_SPIS_IMR_TXOIM
spi_txo_intr interrupt is enabled
#define ALT_SPIS_IMR_TXOIM_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_TXOIM register field.
#define ALT_SPIS_IMR_TXOIM_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_TXOIM register field.
#define ALT_SPIS_IMR_TXOIM_WIDTH 1 |
The width in bits of the ALT_SPIS_IMR_TXOIM register field.
#define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002 |
The mask used to set the ALT_SPIS_IMR_TXOIM register field value.
#define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SPIS_IMR_TXOIM register field value.
#define ALT_SPIS_IMR_TXOIM_RESET 0x1 |
The reset value of the ALT_SPIS_IMR_TXOIM register field.
#define ALT_SPIS_IMR_TXOIM_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SPIS_IMR_TXOIM field value from a register.
#define ALT_SPIS_IMR_TXOIM_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SPIS_IMR_TXOIM register field value suitable for setting the register.
#define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0 |
Enumerated value for register field ALT_SPIS_IMR_RXUIM
spi_rxu_intr interrupt is masked (disabled)
#define ALT_SPIS_IMR_RXUIM_E_END 0x1 |
Enumerated value for register field ALT_SPIS_IMR_RXUIM
spi_rxu_intr interrupt is enabled
#define ALT_SPIS_IMR_RXUIM_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXUIM register field.
#define ALT_SPIS_IMR_RXUIM_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXUIM register field.
#define ALT_SPIS_IMR_RXUIM_WIDTH 1 |
The width in bits of the ALT_SPIS_IMR_RXUIM register field.
#define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004 |
The mask used to set the ALT_SPIS_IMR_RXUIM register field value.
#define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SPIS_IMR_RXUIM register field value.
#define ALT_SPIS_IMR_RXUIM_RESET 0x1 |
The reset value of the ALT_SPIS_IMR_RXUIM register field.
#define ALT_SPIS_IMR_RXUIM_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SPIS_IMR_RXUIM field value from a register.
#define ALT_SPIS_IMR_RXUIM_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SPIS_IMR_RXUIM register field value suitable for setting the register.
#define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0 |
Enumerated value for register field ALT_SPIS_IMR_RXOIM
spi_rxo_intr interrupt is masked (disabled)
#define ALT_SPIS_IMR_RXOIM_E_END 0x1 |
Enumerated value for register field ALT_SPIS_IMR_RXOIM
spi_rxo_intr interrupt is enabled
#define ALT_SPIS_IMR_RXOIM_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXOIM register field.
#define ALT_SPIS_IMR_RXOIM_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXOIM register field.
#define ALT_SPIS_IMR_RXOIM_WIDTH 1 |
The width in bits of the ALT_SPIS_IMR_RXOIM register field.
#define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008 |
The mask used to set the ALT_SPIS_IMR_RXOIM register field value.
#define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SPIS_IMR_RXOIM register field value.
#define ALT_SPIS_IMR_RXOIM_RESET 0x1 |
The reset value of the ALT_SPIS_IMR_RXOIM register field.
#define ALT_SPIS_IMR_RXOIM_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SPIS_IMR_RXOIM field value from a register.
#define ALT_SPIS_IMR_RXOIM_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SPIS_IMR_RXOIM register field value suitable for setting the register.
#define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0 |
Enumerated value for register field ALT_SPIS_IMR_RXFIM
spi_rxf_intr interrupt is masked (disabled)
#define ALT_SPIS_IMR_RXFIM_E_END 0x1 |
Enumerated value for register field ALT_SPIS_IMR_RXFIM
spi_rxf_intr interrupt is enabled
#define ALT_SPIS_IMR_RXFIM_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SPIS_IMR_RXFIM register field.
#define ALT_SPIS_IMR_RXFIM_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SPIS_IMR_RXFIM register field.
#define ALT_SPIS_IMR_RXFIM_WIDTH 1 |
The width in bits of the ALT_SPIS_IMR_RXFIM register field.
#define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010 |
The mask used to set the ALT_SPIS_IMR_RXFIM register field value.
#define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SPIS_IMR_RXFIM register field value.
#define ALT_SPIS_IMR_RXFIM_RESET 0x1 |
The reset value of the ALT_SPIS_IMR_RXFIM register field.
#define ALT_SPIS_IMR_RXFIM_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SPIS_IMR_RXFIM field value from a register.
#define ALT_SPIS_IMR_RXFIM_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SPIS_IMR_RXFIM register field value suitable for setting the register.
#define ALT_SPIS_IMR_OFST 0x2c |
The byte offset of the ALT_SPIS_IMR register from the beginning of the component.
#define ALT_SPIS_IMR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST)) |
The address of the ALT_SPIS_IMR register.
typedef struct ALT_SPIS_IMR_s ALT_SPIS_IMR_t |
The typedef declaration for register ALT_SPIS_IMR.