Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Scan Manager Control Register - ctrl

Description

Controls behaviors of Scan Manager not controlled by registers in the Scan Manager itself.

Register Layout

Bits Access Reset Description
[0] RW 0x0 FPGA JTAG Enable
[31:1] ??? 0x0 UNDEFINED

Field : FPGA JTAG Enable - fpgajtagen

Controls whether FPGA JTAG pins or Scan Manager drives JTAG signals to the FPGA.

Only reset by a cold reset (ignores warm reset).

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0 FPGA JTAG pins drive JTAG signals to FPGA
ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1 Scan Manager drives JTAG signals to FPGA

Field Access Macros:

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS   0x0
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR   0x1
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB   0
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB   0
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH   1
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK   0x00000001
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET   0x0
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value)   (((value) << 0) & 0x00000001)
 

Data Structures

struct  ALT_SYSMGR_SCANMGR_CTL_s
 

Macros

#define ALT_SYSMGR_SCANMGR_CTL_OFST   0x0
 

Typedefs

typedef struct
ALT_SYSMGR_SCANMGR_CTL_s 
ALT_SYSMGR_SCANMGR_CTL_t
 

Data Structure Documentation

struct ALT_SYSMGR_SCANMGR_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_SCANMGR_CTL.

Data Fields
uint32_t fpgajtagen: 1 FPGA JTAG Enable
uint32_t __pad0__: 31 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS   0x0

Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN

FPGA JTAG pins drive JTAG signals to FPGA

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR   0x1

Enumerated value for register field ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN

Scan Manager drives JTAG signals to FPGA

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH   1

The width in bits of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET   0x0

The reset value of the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN field value from a register.

#define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN register field value suitable for setting the register.

#define ALT_SYSMGR_SCANMGR_CTL_OFST   0x0

The byte offset of the ALT_SYSMGR_SCANMGR_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_SCANMGR_CTL.