Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : sbcfg4

Description

Register Layout

Bits Access Reset Description
[19:0] RW 0x0 ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4
[31:20] ??? 0x0 UNDEFINED

Field : cfg_sb_ddr4_mr4

This register stores the DDR4 MR4 Content

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_LSB   0
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_MSB   19
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_WIDTH   20
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK   0x000fffff
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK   0xfff00000
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_GET(value)   (((value) & 0x000fffff) >> 0)
 
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET(value)   (((value) << 0) & 0x000fffff)
 

Data Structures

struct  ALT_IO48_HMC_MMR_SBCFG4_s
 

Macros

#define ALT_IO48_HMC_MMR_SBCFG4_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_SBCFG4_OFST   0x6c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_SBCFG4_s 
ALT_IO48_HMC_MMR_SBCFG4_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_SBCFG4_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_SBCFG4.

Data Fields
uint32_t cfg_sb_ddr4_mr4: 20 ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4
uint32_t __pad0__: 12 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_MSB   19

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_WIDTH   20

The width in bits of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK   0x000fffff

The mask used to set the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK   0xfff00000

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_GET (   value)    (((value) & 0x000fffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET (   value)    (((value) << 0) & 0x000fffff)

Produces a ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4 register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG4_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_SBCFG4 register.

#define ALT_IO48_HMC_MMR_SBCFG4_OFST   0x6c

The byte offset of the ALT_IO48_HMC_MMR_SBCFG4 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG4.