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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register gives the status of the power down commands requested by the Low Power Control register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | Unknown | Deep Power Down Acknowledge |
[1] | RW | Unknown | Self-refresh Acknowledge |
[31:2] | ??? | 0x0 | UNDEFINED |
Field : Deep Power Down Acknowledge - deeppwrdnack | |
This bit is set to a one after a deep power down has been executed Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001) |
Field : Self-refresh Acknowledge - selfrfshack | |
This bit is a one to indicate that the controller is in a self-refresh state. Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002) |
Data Structures | |
struct | ALT_SDR_CTL_LOWPWRACK_s |
Macros | |
#define | ALT_SDR_CTL_LOWPWRACK_OFST 0x58 |
Typedefs | |
typedef struct ALT_SDR_CTL_LOWPWRACK_s | ALT_SDR_CTL_LOWPWRACK_t |
struct ALT_SDR_CTL_LOWPWRACK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_LOWPWRACK.
Data Fields | ||
---|---|---|
uint32_t | deeppwrdnack: 1 | Deep Power Down Acknowledge |
uint32_t | selfrfshack: 1 | Self-refresh Acknowledge |
uint32_t | __pad0__: 30 | UNDEFINED |
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001 |
The mask used to set the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK field value from a register.
#define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002 |
The mask used to set the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK field value from a register.
#define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWRACK_OFST 0x58 |
The byte offset of the ALT_SDR_CTL_LOWPWRACK register from the beginning of the component.
typedef struct ALT_SDR_CTL_LOWPWRACK_s ALT_SDR_CTL_LOWPWRACK_t |
The typedef declaration for register ALT_SDR_CTL_LOWPWRACK.