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16.0
The Altera HW Manager API Reference Manual
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alt_fpga_manager.h
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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33
/*
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* $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_fpga_manager.h#1 $
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*/
36
37
#ifndef __ALT_FPGA_MGR_H__
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#define __ALT_FPGA_MGR_H__
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#include "hwlib.h"
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#include "alt_dma.h"
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#include <stdio.h>
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44
#ifdef __cplusplus
45
extern
"C"
46
{
47
#endif
/* __cplusplus */
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67
#ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
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#define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
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#endif
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78
ALT_STATUS_CODE
alt_fpga_init
(
void
);
79
86
ALT_STATUS_CODE
alt_fpga_uninit
(
void
);
87
108
ALT_STATUS_CODE
alt_fpga_control_enable
(
void
);
109
118
ALT_STATUS_CODE
alt_fpga_control_disable
(
void
);
119
128
bool
alt_fpga_control_is_enabled
(
void
);
129
134
typedef
enum
ALT_FPGA_STATE_e
135
{
146
ALT_FPGA_STATE_POWER_UP
= 0x0,
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154
ALT_FPGA_STATE_RESET
= 0x1,
155
162
ALT_FPGA_STATE_CFG
= 0x2,
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169
ALT_FPGA_STATE_INIT
= 0x3,
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176
ALT_FPGA_STATE_USER_MODE
= 0x4,
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182
ALT_FPGA_STATE_UNKNOWN
= 0x5,
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194
ALT_FPGA_STATE_POWER_OFF
= 0xF
195
196
}
ALT_FPGA_STATE_t
;
197
203
ALT_FPGA_STATE_t
alt_fpga_state_get
(
void
);
204
209
typedef
enum
ALT_FPGA_MON_STATUS_e
210
{
215
ALT_FPGA_MON_nSTATUS
= 0x0001,
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ALT_FPGA_MON_CONF_DONE
= 0x0002,
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ALT_FPGA_MON_INIT_DONE
= 0x0004,
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233
ALT_FPGA_MON_CRC_ERROR
= 0x0008,
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239
ALT_FPGA_MON_CVP_CONF_DONE
= 0x0010,
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245
ALT_FPGA_MON_PR_READY
= 0x0020,
246
251
ALT_FPGA_MON_PR_ERROR
= 0x0040,
252
257
ALT_FPGA_MON_PR_DONE
= 0x0080,
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267
ALT_FPGA_MON_nCONFIG_PIN
= 0x0100,
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277
ALT_FPGA_MON_nSTATUS_PIN
= 0x0200,
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287
ALT_FPGA_MON_CONF_DONE_PIN
= 0x0400,
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292
ALT_FPGA_MON_FPGA_POWER_ON
= 0x0800,
293
294
}
ALT_FPGA_MON_STATUS_t
;
295
312
uint32_t
alt_fpga_mon_status_get
(
void
);
313
329
ALT_STATUS_CODE
alt_fgpa_reset_assert
(
void
);
330
345
ALT_STATUS_CODE
alt_fgpa_reset_deassert
(
void
);
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366
typedef
enum
ALT_FPGA_CFG_MODE_e
367
{
372
ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC
= 0x0,
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ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC
= 0x1,
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384
ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC
= 0x2,
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390
ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC
= 0x4,
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ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC
= 0x5,
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402
ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC
= 0x6,
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408
ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC
= 0x8,
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ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC
= 0x9,
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ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC
= 0xa,
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ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC
= 0xc,
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ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC
= 0xd,
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ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC
= 0xe,
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443
ALT_FPGA_CFG_MODE_UNKNOWN
= 0x20,
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445
}
ALT_FPGA_CFG_MODE_t
;
446
456
ALT_FPGA_CFG_MODE_t
alt_fpga_cfg_mode_get
(
void
);
457
478
ALT_STATUS_CODE
alt_fpga_cfg_mode_set
(
ALT_FPGA_CFG_MODE_t
cfg_mode);
479
523
typedef
int32_t (*
alt_fpga_istream_t
)(
void
* buf,
size_t
buf_len,
void
* user_data);
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564
ALT_STATUS_CODE
alt_fpga_configure
(
const
void
* cfg_buf,
565
size_t
cfg_buf_len);
566
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#if ALT_FPGA_ENABLE_DMA_SUPPORT
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603
ALT_STATUS_CODE alt_fpga_configure_dma(
const
void
* cfg_buf,
604
size_t
cfg_buf_len,
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ALT_DMA_CHANNEL_t
dma_channel);
606
607
#endif
608
643
ALT_STATUS_CODE
alt_fpga_istream_configure
(
alt_fpga_istream_t
cfg_stream,
644
void
* user_data);
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646
#if ALT_FPGA_ENABLE_DMA_SUPPORT
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685
ALT_STATUS_CODE alt_fpga_istream_configure_dma(
alt_fpga_istream_t
cfg_stream,
686
void
* user_data,
687
ALT_DMA_CHANNEL_t
dma_channel);
688
689
#endif
690
751
ALT_STATUS_CODE
alt_fpga_man_irq_disable
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
752
775
ALT_STATUS_CODE
alt_fpga_man_irq_enable
(
ALT_FPGA_MON_STATUS_t
mon_stat_mask);
776
797
typedef
enum
ALT_FPGA_GPI_e
798
{
800
ALT_FPGA_GPI_0
= (int32_t)(1UL << 0),
801
803
ALT_FPGA_GPI_1
= (int32_t)(1UL << 1),
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806
ALT_FPGA_GPI_2
= (int32_t)(1UL << 2),
807
809
ALT_FPGA_GPI_3
= (int32_t)(1UL << 3),
810
812
ALT_FPGA_GPI_4
= (int32_t)(1UL << 4),
813
815
ALT_FPGA_GPI_5
= (int32_t)(1UL << 5),
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818
ALT_FPGA_GPI_6
= (int32_t)(1UL << 6),
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821
ALT_FPGA_GPI_7
= (int32_t)(1UL << 7),
822
824
ALT_FPGA_GPI_8
= (int32_t)(1UL << 8),
825
827
ALT_FPGA_GPI_9
= (int32_t)(1UL << 9),
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830
ALT_FPGA_GPI_10
= (int32_t)(1UL << 10),
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ALT_FPGA_GPI_11
= (int32_t)(1UL << 11),
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836
ALT_FPGA_GPI_12
= (int32_t)(1UL << 12),
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839
ALT_FPGA_GPI_13
= (int32_t)(1UL << 13),
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842
ALT_FPGA_GPI_14
= (int32_t)(1UL << 14),
843
845
ALT_FPGA_GPI_15
= (int32_t)(1UL << 15),
846
848
ALT_FPGA_GPI_16
= (int32_t)(1UL << 16),
849
851
ALT_FPGA_GPI_17
= (int32_t)(1UL << 17),
852
854
ALT_FPGA_GPI_18
= (int32_t)(1UL << 18),
855
857
ALT_FPGA_GPI_19
= (int32_t)(1UL << 19),
858
860
ALT_FPGA_GPI_20
= (int32_t)(1UL << 20),
861
863
ALT_FPGA_GPI_21
= (int32_t)(1UL << 21),
864
866
ALT_FPGA_GPI_22
= (int32_t)(1UL << 22),
867
869
ALT_FPGA_GPI_23
= (int32_t)(1UL << 23),
870
872
ALT_FPGA_GPI_24
= (int32_t)(1UL << 24),
873
875
ALT_FPGA_GPI_25
= (int32_t)(1UL << 25),
876
878
ALT_FPGA_GPI_26
= (int32_t)(1UL << 26),
879
881
ALT_FPGA_GPI_27
= (int32_t)(1UL << 27),
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884
ALT_FPGA_GPI_28
= (int32_t)(1UL << 28),
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887
ALT_FPGA_GPI_29
= (int32_t)(1UL << 29),
888
890
ALT_FPGA_GPI_30
= (int32_t)(1UL << 30),
891
893
ALT_FPGA_GPI_31
= (int32_t)(1UL << 31)
894
895
}
ALT_FPGA_GPI_t
;
896
914
uint32_t
alt_fpga_gpi_read
(uint32_t mask);
915
920
typedef
enum
ALT_FPGA_GPO_e
921
{
923
ALT_FPGA_GPO_0
= (int32_t)(1UL << 0),
924
926
ALT_FPGA_GPO_1
= (int32_t)(1UL << 1),
927
929
ALT_FPGA_GPO_2
= (int32_t)(1UL << 2),
930
932
ALT_FPGA_GPO_3
= (int32_t)(1UL << 3),
933
935
ALT_FPGA_GPO_4
= (int32_t)(1UL << 4),
936
938
ALT_FPGA_GPO_5
= (int32_t)(1UL << 5),
939
941
ALT_FPGA_GPO_6
= (int32_t)(1UL << 6),
942
944
ALT_FPGA_GPO_7
= (int32_t)(1UL << 7),
945
947
ALT_FPGA_GPO_8
= (int32_t)(1UL << 8),
948
950
ALT_FPGA_GPO_9
= (int32_t)(1UL << 9),
951
953
ALT_FPGA_GPO_10
= (int32_t)(1UL << 10),
954
956
ALT_FPGA_GPO_11
= (int32_t)(1UL << 11),
957
959
ALT_FPGA_GPO_12
= (int32_t)(1UL << 12),
960
962
ALT_FPGA_GPO_13
= (int32_t)(1UL << 13),
963
965
ALT_FPGA_GPO_14
= (int32_t)(1UL << 14),
966
968
ALT_FPGA_GPO_15
= (int32_t)(1UL << 15),
969
971
ALT_FPGA_GPO_16
= (int32_t)(1UL << 16),
972
974
ALT_FPGA_GPO_17
= (int32_t)(1UL << 17),
975
977
ALT_FPGA_GPO_18
= (int32_t)(1UL << 18),
978
980
ALT_FPGA_GPO_19
= (int32_t)(1UL << 19),
981
983
ALT_FPGA_GPO_20
= (int32_t)(1UL << 20),
984
986
ALT_FPGA_GPO_21
= (int32_t)(1UL << 21),
987
989
ALT_FPGA_GPO_22
= (int32_t)(1UL << 22),
990
992
ALT_FPGA_GPO_23
= (int32_t)(1UL << 23),
993
995
ALT_FPGA_GPO_24
= (int32_t)(1UL << 24),
996
998
ALT_FPGA_GPO_25
= (int32_t)(1UL << 25),
999
1001
ALT_FPGA_GPO_26
= (int32_t)(1UL << 26),
1002
1004
ALT_FPGA_GPO_27
= (int32_t)(1UL << 27),
1005
1007
ALT_FPGA_GPO_28
= (int32_t)(1UL << 28),
1008
1010
ALT_FPGA_GPO_29
= (int32_t)(1UL << 29),
1011
1013
ALT_FPGA_GPO_30
= (int32_t)(1UL << 30),
1014
1016
ALT_FPGA_GPO_31
= (int32_t)(1UL << 31)
1017
1018
}
ALT_FPGA_GPO_t
;
1019
1044
ALT_STATUS_CODE
alt_fpga_gpo_write
(uint32_t mask, uint32_t value);
1045
1054
#ifdef __cplusplus
1055
}
1056
#endif
/* __cplusplus */
1057
1058
#endif
/* __ALT_FPGA_MGR_H__ */
include
soc_cv_av
alt_fpga_manager.h
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