Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : mcr

Description

Modem Control Register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_UART_MCR_DTR
[1] RW 0x0 ALT_UART_MCR_RTS
[2] RW 0x0 ALT_UART_MCR_OUT1
[3] RW 0x0 ALT_UART_MCR_OUT2
[4] RW 0x0 ALT_UART_MCR_LOOPBACK
[5] RW 0x0 ALT_UART_MCR_AFCE
[6] R 0x0 ALT_UART_MCR_SIRE
[31:7] R 0x0 ALT_UART_MCR_RSVD_MCR_31TO7

Field : dtr

Data Terminal Ready.

This is used to directly control the Data Terminal Ready (dtr_n) output. The value

written to this location is inverted and driven out on dtr_n, that is:

0 = dtr_n de-asserted (logic 1)

1 = dtr_n asserted (logic 0)

The Data Terminal Ready output is used to inform the modem or data set that the

UART is ready to establish communications. Note that in Loopback mode (MCR[4]

set to one), the dtr_n output is held inactive high while the value of this

location is internally looped back to an input.

Field Enumeration Values:

Enum Value Description
ALT_UART_MCR_DTR_E_LOGIC1 0x0 uart_dtr_n de-asserted (logic 1)
ALT_UART_MCR_DTR_E_LOGIC0 0x1 uart_dtr_n asserted (logic 0)

Field Access Macros:

#define ALT_UART_MCR_DTR_E_LOGIC1   0x0
 
#define ALT_UART_MCR_DTR_E_LOGIC0   0x1
 
#define ALT_UART_MCR_DTR_LSB   0
 
#define ALT_UART_MCR_DTR_MSB   0
 
#define ALT_UART_MCR_DTR_WIDTH   1
 
#define ALT_UART_MCR_DTR_SET_MSK   0x00000001
 
#define ALT_UART_MCR_DTR_CLR_MSK   0xfffffffe
 
#define ALT_UART_MCR_DTR_RESET   0x0
 
#define ALT_UART_MCR_DTR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_UART_MCR_DTR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : rts

Request to Send.

This is used to directly control the Request to Send (rts_n) output. The Request

To Send (rts_n) output is used to inform the modem or data set that the UART is

ready to exchange data.

When Auto RTS Flow Control is not enabled (MCR[5] set to zero), the rts_n signal

is set low by programming MCR[1] (RTS) to a high.

In Auto Flow Control, AFCE_MODE == Enabled and active (MCR[5] set to one) and

FIFO's enable (FCR[0] set to one), the rts_n output is controlled in the same way,

but is also gated with the receiver FIFO threshold trigger (rts_n is inactive high

when above the threshold).

The rts_n signal will be de-asserted when MCR[1] is set low.

Note that in Loopback mode (MCR[4] set to one), the rts_n output is held inactive

high while the value of this location is internally looped back to an input.

Field Enumeration Values:

Enum Value Description
ALT_UART_MCR_RTS_E_LOGIC1 0x0 uart_rts_n de-asserted (logic 1)
ALT_UART_MCR_RTS_E_LOGIC0 0x1 uart_rts_n asserted (logic 0)

Field Access Macros:

#define ALT_UART_MCR_RTS_E_LOGIC1   0x0
 
#define ALT_UART_MCR_RTS_E_LOGIC0   0x1
 
#define ALT_UART_MCR_RTS_LSB   1
 
#define ALT_UART_MCR_RTS_MSB   1
 
#define ALT_UART_MCR_RTS_WIDTH   1
 
#define ALT_UART_MCR_RTS_SET_MSK   0x00000002
 
#define ALT_UART_MCR_RTS_CLR_MSK   0xfffffffd
 
#define ALT_UART_MCR_RTS_RESET   0x0
 
#define ALT_UART_MCR_RTS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_UART_MCR_RTS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : out1

OUT1.

This is used to directly control the user-designated Output1 (out1_n) output. The

value written to this location is inverted and driven out on out1_n, that is:

0 = out1_n de-asserted (logic 1)

1 = out1_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out1_n output is held inactive high

while the value of this location is internally looped back to an input.

Field Enumeration Values:

Enum Value Description
ALT_UART_MCR_OUT1_E_LOGIC1 0x0 uart_out1_n de-asserted (logic 1)
ALT_UART_MCR_OUT1_E_LOGIC0 0x1 uart_out1_n asserted (logic 0)

Field Access Macros:

#define ALT_UART_MCR_OUT1_E_LOGIC1   0x0
 
#define ALT_UART_MCR_OUT1_E_LOGIC0   0x1
 
#define ALT_UART_MCR_OUT1_LSB   2
 
#define ALT_UART_MCR_OUT1_MSB   2
 
#define ALT_UART_MCR_OUT1_WIDTH   1
 
#define ALT_UART_MCR_OUT1_SET_MSK   0x00000004
 
#define ALT_UART_MCR_OUT1_CLR_MSK   0xfffffffb
 
#define ALT_UART_MCR_OUT1_RESET   0x0
 
#define ALT_UART_MCR_OUT1_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_UART_MCR_OUT1_SET(value)   (((value) << 2) & 0x00000004)
 

Field : out2

OUT2.

This is used to directly control the user-designated Output2 (out2_n) output. The

value written to this location is inverted and driven out on out2_n, that is:

0 = out2_n de-asserted (logic 1)

1 = out2_n asserted (logic 0)

Note that in Loopback mode (MCR[4] set to one), the out2_n output is held inactive

high while the value of this location is internally looped back to an input.

Field Enumeration Values:

Enum Value Description
ALT_UART_MCR_OUT2_E_LOGIC1 0x0 uart_out2_n de-asserted (logic 1)
ALT_UART_MCR_OUT2_E_LOGIC0 0x1 uart_out2_n asserted (logic 0)

Field Access Macros:

#define ALT_UART_MCR_OUT2_E_LOGIC1   0x0
 
#define ALT_UART_MCR_OUT2_E_LOGIC0   0x1
 
#define ALT_UART_MCR_OUT2_LSB   3
 
#define ALT_UART_MCR_OUT2_MSB   3
 
#define ALT_UART_MCR_OUT2_WIDTH   1
 
#define ALT_UART_MCR_OUT2_SET_MSK   0x00000008
 
#define ALT_UART_MCR_OUT2_CLR_MSK   0xfffffff7
 
#define ALT_UART_MCR_OUT2_RESET   0x0
 
#define ALT_UART_MCR_OUT2_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_UART_MCR_OUT2_SET(value)   (((value) << 3) & 0x00000008)
 

Field : loopback

LoopBack Bit.

This is used to put the UART into a dDW_iagnostic mode for test purposes.

If operating in UART mode (SIR_MODE != Enabled OR NOT active, MCR[6] set to zero),

data on the sout line is held high, while serial data output is looped back to the

sin line, internally. In this mode all the interrupts are fully functional. Also,

in loopback mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are

disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n) are looped

back to the inputs, internally.

If operating in infrared mode (SIR_MODE == Enabled AND active, MCR[6] set to one),

data on the sir_out_n line is held low, while serial data output is inverted and

looped back to the sir_in line.

Field Access Macros:

#define ALT_UART_MCR_LOOPBACK_LSB   4
 
#define ALT_UART_MCR_LOOPBACK_MSB   4
 
#define ALT_UART_MCR_LOOPBACK_WIDTH   1
 
#define ALT_UART_MCR_LOOPBACK_SET_MSK   0x00000010
 
#define ALT_UART_MCR_LOOPBACK_CLR_MSK   0xffffffef
 
#define ALT_UART_MCR_LOOPBACK_RESET   0x0
 
#define ALT_UART_MCR_LOOPBACK_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_UART_MCR_LOOPBACK_SET(value)   (((value) << 4) & 0x00000010)
 

Field : afce

Auto Flow Control Enable.

Writeable only when AFCE_MODE == Enabled, always readable. When FIFOs are enabled

and the Auto Flow Control Enable (AFCE) bit is set, Auto Flow Control features are

enabled as described in section 5.6 on page 51.

0 = Auto Flow Control Mode disabled

1 = Auto Flow Control Mode enabled

Field Enumeration Values:

Enum Value Description
ALT_UART_MCR_AFCE_E_DISD 0x0 Auto Flow Control Mode disabled
ALT_UART_MCR_AFCE_E_END 0x1 Auto Flow Control Mode enabled

Field Access Macros:

#define ALT_UART_MCR_AFCE_E_DISD   0x0
 
#define ALT_UART_MCR_AFCE_E_END   0x1
 
#define ALT_UART_MCR_AFCE_LSB   5
 
#define ALT_UART_MCR_AFCE_MSB   5
 
#define ALT_UART_MCR_AFCE_WIDTH   1
 
#define ALT_UART_MCR_AFCE_SET_MSK   0x00000020
 
#define ALT_UART_MCR_AFCE_CLR_MSK   0xffffffdf
 
#define ALT_UART_MCR_AFCE_RESET   0x0
 
#define ALT_UART_MCR_AFCE_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_UART_MCR_AFCE_SET(value)   (((value) << 5) & 0x00000020)
 

Field : sire

SIR Mode Enable.

Writeable only when SIR_MODE == Enabled, always readable. This is used to enable/

disable the IrDA SIR Mode features as described in section 5.2 on page 47.

0 = IrDA SIR Mode disabled

1 = IrDA SIR Mode enabled

Field Access Macros:

#define ALT_UART_MCR_SIRE_LSB   6
 
#define ALT_UART_MCR_SIRE_MSB   6
 
#define ALT_UART_MCR_SIRE_WIDTH   1
 
#define ALT_UART_MCR_SIRE_SET_MSK   0x00000040
 
#define ALT_UART_MCR_SIRE_CLR_MSK   0xffffffbf
 
#define ALT_UART_MCR_SIRE_RESET   0x0
 
#define ALT_UART_MCR_SIRE_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_UART_MCR_SIRE_SET(value)   (((value) << 6) & 0x00000040)
 

Field : rsvd_mcr_31to7

Reserved bits [31:7] - Read Only

Field Access Macros:

#define ALT_UART_MCR_RSVD_MCR_31TO7_LSB   7
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_MSB   31
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_WIDTH   25
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_SET_MSK   0xffffff80
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_CLR_MSK   0x0000007f
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_RESET   0x0
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_GET(value)   (((value) & 0xffffff80) >> 7)
 
#define ALT_UART_MCR_RSVD_MCR_31TO7_SET(value)   (((value) << 7) & 0xffffff80)
 

Data Structures

struct  ALT_UART_MCR_s
 

Macros

#define ALT_UART_MCR_RESET   0x00000000
 
#define ALT_UART_MCR_OFST   0x10
 
#define ALT_UART_MCR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))
 

Typedefs

typedef struct ALT_UART_MCR_s ALT_UART_MCR_t
 

Data Structure Documentation

struct ALT_UART_MCR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_MCR.

Data Fields
uint32_t dtr: 1 ALT_UART_MCR_DTR
uint32_t rts: 1 ALT_UART_MCR_RTS
uint32_t out1: 1 ALT_UART_MCR_OUT1
uint32_t out2: 1 ALT_UART_MCR_OUT2
uint32_t loopback: 1 ALT_UART_MCR_LOOPBACK
uint32_t afce: 1 ALT_UART_MCR_AFCE
const uint32_t sire: 1 ALT_UART_MCR_SIRE
const uint32_t rsvd_mcr_31to7: 25 ALT_UART_MCR_RSVD_MCR_31TO7

Macro Definitions

#define ALT_UART_MCR_DTR_E_LOGIC1   0x0

Enumerated value for register field ALT_UART_MCR_DTR

uart_dtr_n de-asserted (logic 1)

#define ALT_UART_MCR_DTR_E_LOGIC0   0x1

Enumerated value for register field ALT_UART_MCR_DTR

uart_dtr_n asserted (logic 0)

#define ALT_UART_MCR_DTR_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_MCR_DTR register field.

#define ALT_UART_MCR_DTR_MSB   0

The Most Significant Bit (MSB) position of the ALT_UART_MCR_DTR register field.

#define ALT_UART_MCR_DTR_WIDTH   1

The width in bits of the ALT_UART_MCR_DTR register field.

#define ALT_UART_MCR_DTR_SET_MSK   0x00000001

The mask used to set the ALT_UART_MCR_DTR register field value.

#define ALT_UART_MCR_DTR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_UART_MCR_DTR register field value.

#define ALT_UART_MCR_DTR_RESET   0x0

The reset value of the ALT_UART_MCR_DTR register field.

#define ALT_UART_MCR_DTR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_UART_MCR_DTR field value from a register.

#define ALT_UART_MCR_DTR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_UART_MCR_DTR register field value suitable for setting the register.

#define ALT_UART_MCR_RTS_E_LOGIC1   0x0

Enumerated value for register field ALT_UART_MCR_RTS

uart_rts_n de-asserted (logic 1)

#define ALT_UART_MCR_RTS_E_LOGIC0   0x1

Enumerated value for register field ALT_UART_MCR_RTS

uart_rts_n asserted (logic 0)

#define ALT_UART_MCR_RTS_LSB   1

The Least Significant Bit (LSB) position of the ALT_UART_MCR_RTS register field.

#define ALT_UART_MCR_RTS_MSB   1

The Most Significant Bit (MSB) position of the ALT_UART_MCR_RTS register field.

#define ALT_UART_MCR_RTS_WIDTH   1

The width in bits of the ALT_UART_MCR_RTS register field.

#define ALT_UART_MCR_RTS_SET_MSK   0x00000002

The mask used to set the ALT_UART_MCR_RTS register field value.

#define ALT_UART_MCR_RTS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_UART_MCR_RTS register field value.

#define ALT_UART_MCR_RTS_RESET   0x0

The reset value of the ALT_UART_MCR_RTS register field.

#define ALT_UART_MCR_RTS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_UART_MCR_RTS field value from a register.

#define ALT_UART_MCR_RTS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_UART_MCR_RTS register field value suitable for setting the register.

#define ALT_UART_MCR_OUT1_E_LOGIC1   0x0

Enumerated value for register field ALT_UART_MCR_OUT1

uart_out1_n de-asserted (logic 1)

#define ALT_UART_MCR_OUT1_E_LOGIC0   0x1

Enumerated value for register field ALT_UART_MCR_OUT1

uart_out1_n asserted (logic 0)

#define ALT_UART_MCR_OUT1_LSB   2

The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT1 register field.

#define ALT_UART_MCR_OUT1_MSB   2

The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT1 register field.

#define ALT_UART_MCR_OUT1_WIDTH   1

The width in bits of the ALT_UART_MCR_OUT1 register field.

#define ALT_UART_MCR_OUT1_SET_MSK   0x00000004

The mask used to set the ALT_UART_MCR_OUT1 register field value.

#define ALT_UART_MCR_OUT1_CLR_MSK   0xfffffffb

The mask used to clear the ALT_UART_MCR_OUT1 register field value.

#define ALT_UART_MCR_OUT1_RESET   0x0

The reset value of the ALT_UART_MCR_OUT1 register field.

#define ALT_UART_MCR_OUT1_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_UART_MCR_OUT1 field value from a register.

#define ALT_UART_MCR_OUT1_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_UART_MCR_OUT1 register field value suitable for setting the register.

#define ALT_UART_MCR_OUT2_E_LOGIC1   0x0

Enumerated value for register field ALT_UART_MCR_OUT2

uart_out2_n de-asserted (logic 1)

#define ALT_UART_MCR_OUT2_E_LOGIC0   0x1

Enumerated value for register field ALT_UART_MCR_OUT2

uart_out2_n asserted (logic 0)

#define ALT_UART_MCR_OUT2_LSB   3

The Least Significant Bit (LSB) position of the ALT_UART_MCR_OUT2 register field.

#define ALT_UART_MCR_OUT2_MSB   3

The Most Significant Bit (MSB) position of the ALT_UART_MCR_OUT2 register field.

#define ALT_UART_MCR_OUT2_WIDTH   1

The width in bits of the ALT_UART_MCR_OUT2 register field.

#define ALT_UART_MCR_OUT2_SET_MSK   0x00000008

The mask used to set the ALT_UART_MCR_OUT2 register field value.

#define ALT_UART_MCR_OUT2_CLR_MSK   0xfffffff7

The mask used to clear the ALT_UART_MCR_OUT2 register field value.

#define ALT_UART_MCR_OUT2_RESET   0x0

The reset value of the ALT_UART_MCR_OUT2 register field.

#define ALT_UART_MCR_OUT2_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_UART_MCR_OUT2 field value from a register.

#define ALT_UART_MCR_OUT2_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_UART_MCR_OUT2 register field value suitable for setting the register.

#define ALT_UART_MCR_LOOPBACK_LSB   4

The Least Significant Bit (LSB) position of the ALT_UART_MCR_LOOPBACK register field.

#define ALT_UART_MCR_LOOPBACK_MSB   4

The Most Significant Bit (MSB) position of the ALT_UART_MCR_LOOPBACK register field.

#define ALT_UART_MCR_LOOPBACK_WIDTH   1

The width in bits of the ALT_UART_MCR_LOOPBACK register field.

#define ALT_UART_MCR_LOOPBACK_SET_MSK   0x00000010

The mask used to set the ALT_UART_MCR_LOOPBACK register field value.

#define ALT_UART_MCR_LOOPBACK_CLR_MSK   0xffffffef

The mask used to clear the ALT_UART_MCR_LOOPBACK register field value.

#define ALT_UART_MCR_LOOPBACK_RESET   0x0

The reset value of the ALT_UART_MCR_LOOPBACK register field.

#define ALT_UART_MCR_LOOPBACK_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_UART_MCR_LOOPBACK field value from a register.

#define ALT_UART_MCR_LOOPBACK_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_UART_MCR_LOOPBACK register field value suitable for setting the register.

#define ALT_UART_MCR_AFCE_E_DISD   0x0

Enumerated value for register field ALT_UART_MCR_AFCE

Auto Flow Control Mode disabled

#define ALT_UART_MCR_AFCE_E_END   0x1

Enumerated value for register field ALT_UART_MCR_AFCE

Auto Flow Control Mode enabled

#define ALT_UART_MCR_AFCE_LSB   5

The Least Significant Bit (LSB) position of the ALT_UART_MCR_AFCE register field.

#define ALT_UART_MCR_AFCE_MSB   5

The Most Significant Bit (MSB) position of the ALT_UART_MCR_AFCE register field.

#define ALT_UART_MCR_AFCE_WIDTH   1

The width in bits of the ALT_UART_MCR_AFCE register field.

#define ALT_UART_MCR_AFCE_SET_MSK   0x00000020

The mask used to set the ALT_UART_MCR_AFCE register field value.

#define ALT_UART_MCR_AFCE_CLR_MSK   0xffffffdf

The mask used to clear the ALT_UART_MCR_AFCE register field value.

#define ALT_UART_MCR_AFCE_RESET   0x0

The reset value of the ALT_UART_MCR_AFCE register field.

#define ALT_UART_MCR_AFCE_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_UART_MCR_AFCE field value from a register.

#define ALT_UART_MCR_AFCE_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_UART_MCR_AFCE register field value suitable for setting the register.

#define ALT_UART_MCR_SIRE_LSB   6

The Least Significant Bit (LSB) position of the ALT_UART_MCR_SIRE register field.

#define ALT_UART_MCR_SIRE_MSB   6

The Most Significant Bit (MSB) position of the ALT_UART_MCR_SIRE register field.

#define ALT_UART_MCR_SIRE_WIDTH   1

The width in bits of the ALT_UART_MCR_SIRE register field.

#define ALT_UART_MCR_SIRE_SET_MSK   0x00000040

The mask used to set the ALT_UART_MCR_SIRE register field value.

#define ALT_UART_MCR_SIRE_CLR_MSK   0xffffffbf

The mask used to clear the ALT_UART_MCR_SIRE register field value.

#define ALT_UART_MCR_SIRE_RESET   0x0

The reset value of the ALT_UART_MCR_SIRE register field.

#define ALT_UART_MCR_SIRE_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_UART_MCR_SIRE field value from a register.

#define ALT_UART_MCR_SIRE_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_UART_MCR_SIRE register field value suitable for setting the register.

#define ALT_UART_MCR_RSVD_MCR_31TO7_LSB   7

The Least Significant Bit (LSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field.

#define ALT_UART_MCR_RSVD_MCR_31TO7_MSB   31

The Most Significant Bit (MSB) position of the ALT_UART_MCR_RSVD_MCR_31TO7 register field.

#define ALT_UART_MCR_RSVD_MCR_31TO7_WIDTH   25

The width in bits of the ALT_UART_MCR_RSVD_MCR_31TO7 register field.

#define ALT_UART_MCR_RSVD_MCR_31TO7_SET_MSK   0xffffff80

The mask used to set the ALT_UART_MCR_RSVD_MCR_31TO7 register field value.

#define ALT_UART_MCR_RSVD_MCR_31TO7_CLR_MSK   0x0000007f

The mask used to clear the ALT_UART_MCR_RSVD_MCR_31TO7 register field value.

#define ALT_UART_MCR_RSVD_MCR_31TO7_RESET   0x0

The reset value of the ALT_UART_MCR_RSVD_MCR_31TO7 register field.

#define ALT_UART_MCR_RSVD_MCR_31TO7_GET (   value)    (((value) & 0xffffff80) >> 7)

Extracts the ALT_UART_MCR_RSVD_MCR_31TO7 field value from a register.

#define ALT_UART_MCR_RSVD_MCR_31TO7_SET (   value)    (((value) << 7) & 0xffffff80)

Produces a ALT_UART_MCR_RSVD_MCR_31TO7 register field value suitable for setting the register.

#define ALT_UART_MCR_RESET   0x00000000

The reset value of the ALT_UART_MCR register.

#define ALT_UART_MCR_OFST   0x10

The byte offset of the ALT_UART_MCR register from the beginning of the component.

#define ALT_UART_MCR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MCR_OFST))

The address of the ALT_UART_MCR register.

Typedef Documentation

The typedef declaration for register ALT_UART_MCR.