Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
Main Page
Address Space
Data Structures
Files
File List
All
Data Structures
Variables
Typedefs
Groups
alt_ecc_hmc_ocp.h
1
/***********************************************************************************
2
* *
3
* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4
* *
5
* Redistribution and use in source and binary forms, with or without *
6
* modification, are permitted provided that the following conditions are met: *
7
* *
8
* 1. Redistributions of source code must retain the above copyright notice, *
9
* this list of conditions and the following disclaimer. *
10
* *
11
* 2. Redistributions in binary form must reproduce the above copyright notice, *
12
* this list of conditions and the following disclaimer in the documentation *
13
* and/or other materials provided with the distribution. *
14
* *
15
* 3. Neither the name of the copyright holder nor the names of its contributors *
16
* may be used to endorse or promote products derived from this software without *
17
* specific prior written permission. *
18
* *
19
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29
* POSSIBILITY OF SUCH DAMAGE. *
30
* *
31
***********************************************************************************/
32
35
#ifndef __ALT_SOCAL_ECC_HMC_OCP_H__
36
#define __ALT_SOCAL_ECC_HMC_OCP_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
43
#else
/* __cplusplus */
44
#include <stdint.h>
45
#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
47
74
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_LSB 0
75
76
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_MSB 15
77
78
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_WIDTH 16
79
80
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81
82
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83
84
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_RESET 0x0
85
86
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87
88
#define ALT_ECC_HMC_OCP_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89
90
#ifndef __ASSEMBLY__
91
101
struct
ALT_ECC_HMC_OCP_IP_REV_ID_s
102
{
103
uint32_t
SIREV
: 16;
104
uint32_t : 16;
105
};
106
108
typedef
volatile
struct
ALT_ECC_HMC_OCP_IP_REV_ID_s
ALT_ECC_HMC_OCP_IP_REV_ID_t
;
109
#endif
/* __ASSEMBLY__ */
110
112
#define ALT_ECC_HMC_OCP_IP_REV_ID_RESET 0x00000000
113
114
#define ALT_ECC_HMC_OCP_IP_REV_ID_OFST 0x0
115
146
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_LSB 0
147
148
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_MSB 1
149
150
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_WIDTH 2
151
152
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET_MSK 0x00000003
153
154
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_CLR_MSK 0xfffffffc
155
156
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_RESET 0x0
157
158
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_GET(value) (((value) & 0x00000003) >> 0)
159
160
#define ALT_ECC_HMC_OCP_DDRIOCTL_IO_SIZE_SET(value) (((value) << 0) & 0x00000003)
161
162
#ifndef __ASSEMBLY__
163
173
struct
ALT_ECC_HMC_OCP_DDRIOCTL_s
174
{
175
uint32_t
IO_SIZE
: 2;
176
uint32_t : 30;
177
};
178
180
typedef
volatile
struct
ALT_ECC_HMC_OCP_DDRIOCTL_s
ALT_ECC_HMC_OCP_DDRIOCTL_t
;
181
#endif
/* __ASSEMBLY__ */
182
184
#define ALT_ECC_HMC_OCP_DDRIOCTL_RESET 0x00000000
185
186
#define ALT_ECC_HMC_OCP_DDRIOCTL_OFST 0x8
187
216
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_LSB 0
217
218
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_MSB 0
219
220
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_WIDTH 1
221
222
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET_MSK 0x00000001
223
224
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_CLR_MSK 0xfffffffe
225
226
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_RESET 0x0
227
228
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_GET(value) (((value) & 0x00000001) >> 0)
229
230
#define ALT_ECC_HMC_OCP_DDRCALSTAT_CAL_SET(value) (((value) << 0) & 0x00000001)
231
232
#ifndef __ASSEMBLY__
233
243
struct
ALT_ECC_HMC_OCP_DDRCALSTAT_s
244
{
245
uint32_t
CAL
: 1;
246
uint32_t : 31;
247
};
248
250
typedef
volatile
struct
ALT_ECC_HMC_OCP_DDRCALSTAT_s
ALT_ECC_HMC_OCP_DDRCALSTAT_t
;
251
#endif
/* __ASSEMBLY__ */
252
254
#define ALT_ECC_HMC_OCP_DDRCALSTAT_RESET 0x00000000
255
256
#define ALT_ECC_HMC_OCP_DDRCALSTAT_OFST 0xc
257
279
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_LSB 0
280
281
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_MSB 31
282
283
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_WIDTH 32
284
285
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET_MSK 0xffffffff
286
287
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_CLR_MSK 0x00000000
288
289
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_RESET 0x0
290
291
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
292
293
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_MPR0_SET(value) (((value) << 0) & 0xffffffff)
294
295
#ifndef __ASSEMBLY__
296
306
struct
ALT_ECC_HMC_OCP_MPR_0BEAT1_s
307
{
308
uint32_t
MPR0
: 32;
309
};
310
312
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_0BEAT1_s
ALT_ECC_HMC_OCP_MPR_0BEAT1_t
;
313
#endif
/* __ASSEMBLY__ */
314
316
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_RESET 0x00000000
317
318
#define ALT_ECC_HMC_OCP_MPR_0BEAT1_OFST 0x10
319
341
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_LSB 0
342
343
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_MSB 31
344
345
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_WIDTH 32
346
347
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET_MSK 0xffffffff
348
349
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_CLR_MSK 0x00000000
350
351
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_RESET 0x0
352
353
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
354
355
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_MPR32_SET(value) (((value) << 0) & 0xffffffff)
356
357
#ifndef __ASSEMBLY__
358
368
struct
ALT_ECC_HMC_OCP_MPR_1BEAT1_s
369
{
370
uint32_t
MPR32
: 32;
371
};
372
374
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_1BEAT1_s
ALT_ECC_HMC_OCP_MPR_1BEAT1_t
;
375
#endif
/* __ASSEMBLY__ */
376
378
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_RESET 0x00000000
379
380
#define ALT_ECC_HMC_OCP_MPR_1BEAT1_OFST 0x14
381
403
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_LSB 0
404
405
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_MSB 31
406
407
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_WIDTH 32
408
409
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET_MSK 0xffffffff
410
411
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_CLR_MSK 0x00000000
412
413
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_RESET 0x0
414
415
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
416
417
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_MPR64_SET(value) (((value) << 0) & 0xffffffff)
418
419
#ifndef __ASSEMBLY__
420
430
struct
ALT_ECC_HMC_OCP_MPR_2BEAT1_s
431
{
432
uint32_t
MPR64
: 32;
433
};
434
436
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_2BEAT1_s
ALT_ECC_HMC_OCP_MPR_2BEAT1_t
;
437
#endif
/* __ASSEMBLY__ */
438
440
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_RESET 0x00000000
441
442
#define ALT_ECC_HMC_OCP_MPR_2BEAT1_OFST 0x18
443
465
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_LSB 0
466
467
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_MSB 31
468
469
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_WIDTH 32
470
471
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET_MSK 0xffffffff
472
473
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_CLR_MSK 0x00000000
474
475
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_RESET 0x0
476
477
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
478
479
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_MPR96_SET(value) (((value) << 0) & 0xffffffff)
480
481
#ifndef __ASSEMBLY__
482
492
struct
ALT_ECC_HMC_OCP_MPR_3BEAT1_s
493
{
494
uint32_t
MPR96
: 32;
495
};
496
498
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_3BEAT1_s
ALT_ECC_HMC_OCP_MPR_3BEAT1_t
;
499
#endif
/* __ASSEMBLY__ */
500
502
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_RESET 0x00000000
503
504
#define ALT_ECC_HMC_OCP_MPR_3BEAT1_OFST 0x1c
505
527
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_LSB 0
528
529
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_MSB 31
530
531
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_WIDTH 32
532
533
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET_MSK 0xffffffff
534
535
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_CLR_MSK 0x00000000
536
537
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_RESET 0x0
538
539
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
540
541
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_MPR128_SET(value) (((value) << 0) & 0xffffffff)
542
543
#ifndef __ASSEMBLY__
544
554
struct
ALT_ECC_HMC_OCP_MPR_4BEAT1_s
555
{
556
uint32_t
MPR128
: 32;
557
};
558
560
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_4BEAT1_s
ALT_ECC_HMC_OCP_MPR_4BEAT1_t
;
561
#endif
/* __ASSEMBLY__ */
562
564
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_RESET 0x00000000
565
566
#define ALT_ECC_HMC_OCP_MPR_4BEAT1_OFST 0x20
567
589
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_LSB 0
590
591
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_MSB 31
592
593
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_WIDTH 32
594
595
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET_MSK 0xffffffff
596
597
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_CLR_MSK 0x00000000
598
599
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_RESET 0x0
600
601
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
602
603
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_MPR160_SET(value) (((value) << 0) & 0xffffffff)
604
605
#ifndef __ASSEMBLY__
606
616
struct
ALT_ECC_HMC_OCP_MPR_5BEAT1_s
617
{
618
uint32_t
MPR160
: 32;
619
};
620
622
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_5BEAT1_s
ALT_ECC_HMC_OCP_MPR_5BEAT1_t
;
623
#endif
/* __ASSEMBLY__ */
624
626
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_RESET 0x00000000
627
628
#define ALT_ECC_HMC_OCP_MPR_5BEAT1_OFST 0x24
629
651
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_LSB 0
652
653
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_MSB 31
654
655
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_WIDTH 32
656
657
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET_MSK 0xffffffff
658
659
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_CLR_MSK 0x00000000
660
661
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_RESET 0x0
662
663
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
664
665
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_MPR192_SET(value) (((value) << 0) & 0xffffffff)
666
667
#ifndef __ASSEMBLY__
668
678
struct
ALT_ECC_HMC_OCP_MPR_6BEAT1_s
679
{
680
uint32_t
MPR192
: 32;
681
};
682
684
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_6BEAT1_s
ALT_ECC_HMC_OCP_MPR_6BEAT1_t
;
685
#endif
/* __ASSEMBLY__ */
686
688
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_RESET 0x00000000
689
690
#define ALT_ECC_HMC_OCP_MPR_6BEAT1_OFST 0x28
691
713
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_LSB 0
714
715
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_MSB 31
716
717
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_WIDTH 32
718
719
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET_MSK 0xffffffff
720
721
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_CLR_MSK 0x00000000
722
723
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_RESET 0x0
724
725
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
726
727
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_MPR224_SET(value) (((value) << 0) & 0xffffffff)
728
729
#ifndef __ASSEMBLY__
730
740
struct
ALT_ECC_HMC_OCP_MPR_7BEAT1_s
741
{
742
uint32_t
MPR224
: 32;
743
};
744
746
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_7BEAT1_s
ALT_ECC_HMC_OCP_MPR_7BEAT1_t
;
747
#endif
/* __ASSEMBLY__ */
748
750
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_RESET 0x00000000
751
752
#define ALT_ECC_HMC_OCP_MPR_7BEAT1_OFST 0x2c
753
775
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_LSB 0
776
777
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_MSB 31
778
779
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_WIDTH 32
780
781
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET_MSK 0xffffffff
782
783
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_CLR_MSK 0x00000000
784
785
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_RESET 0x0
786
787
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
788
789
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_MPR256_SET(value) (((value) << 0) & 0xffffffff)
790
791
#ifndef __ASSEMBLY__
792
802
struct
ALT_ECC_HMC_OCP_MPR_8BEAT1_s
803
{
804
uint32_t
MPR256
: 32;
805
};
806
808
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_8BEAT1_s
ALT_ECC_HMC_OCP_MPR_8BEAT1_t
;
809
#endif
/* __ASSEMBLY__ */
810
812
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_RESET 0x00000000
813
814
#define ALT_ECC_HMC_OCP_MPR_8BEAT1_OFST 0x30
815
837
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_LSB 0
838
839
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_MSB 31
840
841
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_WIDTH 32
842
843
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET_MSK 0xffffffff
844
845
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_CLR_MSK 0x00000000
846
847
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_RESET 0x0
848
849
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_GET(value) (((value) & 0xffffffff) >> 0)
850
851
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_MPR0_SET(value) (((value) << 0) & 0xffffffff)
852
853
#ifndef __ASSEMBLY__
854
864
struct
ALT_ECC_HMC_OCP_MPR_0BEAT2_s
865
{
866
uint32_t
MPR0
: 32;
867
};
868
870
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_0BEAT2_s
ALT_ECC_HMC_OCP_MPR_0BEAT2_t
;
871
#endif
/* __ASSEMBLY__ */
872
874
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_RESET 0x00000000
875
876
#define ALT_ECC_HMC_OCP_MPR_0BEAT2_OFST 0x34
877
899
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_LSB 0
900
901
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_MSB 31
902
903
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_WIDTH 32
904
905
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET_MSK 0xffffffff
906
907
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_CLR_MSK 0x00000000
908
909
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_RESET 0x0
910
911
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_GET(value) (((value) & 0xffffffff) >> 0)
912
913
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_MPR32_SET(value) (((value) << 0) & 0xffffffff)
914
915
#ifndef __ASSEMBLY__
916
926
struct
ALT_ECC_HMC_OCP_MPR_1BEAT2_s
927
{
928
uint32_t
MPR32
: 32;
929
};
930
932
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_1BEAT2_s
ALT_ECC_HMC_OCP_MPR_1BEAT2_t
;
933
#endif
/* __ASSEMBLY__ */
934
936
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_RESET 0x00000000
937
938
#define ALT_ECC_HMC_OCP_MPR_1BEAT2_OFST 0x38
939
961
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_LSB 0
962
963
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_MSB 31
964
965
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_WIDTH 32
966
967
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET_MSK 0xffffffff
968
969
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_CLR_MSK 0x00000000
970
971
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_RESET 0x0
972
973
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_GET(value) (((value) & 0xffffffff) >> 0)
974
975
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_MPR64_SET(value) (((value) << 0) & 0xffffffff)
976
977
#ifndef __ASSEMBLY__
978
988
struct
ALT_ECC_HMC_OCP_MPR_2BEAT2_s
989
{
990
uint32_t
MPR64
: 32;
991
};
992
994
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_2BEAT2_s
ALT_ECC_HMC_OCP_MPR_2BEAT2_t
;
995
#endif
/* __ASSEMBLY__ */
996
998
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_RESET 0x00000000
999
1000
#define ALT_ECC_HMC_OCP_MPR_2BEAT2_OFST 0x3c
1001
1023
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_LSB 0
1024
1025
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_MSB 31
1026
1027
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_WIDTH 32
1028
1029
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET_MSK 0xffffffff
1030
1031
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_CLR_MSK 0x00000000
1032
1033
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_RESET 0x0
1034
1035
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_GET(value) (((value) & 0xffffffff) >> 0)
1036
1037
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_MPR96_SET(value) (((value) << 0) & 0xffffffff)
1038
1039
#ifndef __ASSEMBLY__
1040
1050
struct
ALT_ECC_HMC_OCP_MPR_3BEAT2_s
1051
{
1052
uint32_t
MPR96
: 32;
1053
};
1054
1056
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_3BEAT2_s
ALT_ECC_HMC_OCP_MPR_3BEAT2_t
;
1057
#endif
/* __ASSEMBLY__ */
1058
1060
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_RESET 0x00000000
1061
1062
#define ALT_ECC_HMC_OCP_MPR_3BEAT2_OFST 0x40
1063
1085
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_LSB 0
1086
1087
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_MSB 31
1088
1089
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_WIDTH 32
1090
1091
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET_MSK 0xffffffff
1092
1093
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_CLR_MSK 0x00000000
1094
1095
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_RESET 0x0
1096
1097
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_GET(value) (((value) & 0xffffffff) >> 0)
1098
1099
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_MPR128_SET(value) (((value) << 0) & 0xffffffff)
1100
1101
#ifndef __ASSEMBLY__
1102
1112
struct
ALT_ECC_HMC_OCP_MPR_4BEAT2_s
1113
{
1114
uint32_t
MPR128
: 32;
1115
};
1116
1118
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_4BEAT2_s
ALT_ECC_HMC_OCP_MPR_4BEAT2_t
;
1119
#endif
/* __ASSEMBLY__ */
1120
1122
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_RESET 0x00000000
1123
1124
#define ALT_ECC_HMC_OCP_MPR_4BEAT2_OFST 0x44
1125
1147
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_LSB 0
1148
1149
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_MSB 31
1150
1151
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_WIDTH 32
1152
1153
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET_MSK 0xffffffff
1154
1155
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_CLR_MSK 0x00000000
1156
1157
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_RESET 0x0
1158
1159
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_GET(value) (((value) & 0xffffffff) >> 0)
1160
1161
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_MPR160_SET(value) (((value) << 0) & 0xffffffff)
1162
1163
#ifndef __ASSEMBLY__
1164
1174
struct
ALT_ECC_HMC_OCP_MPR_5BEAT2_s
1175
{
1176
uint32_t
MPR160
: 32;
1177
};
1178
1180
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_5BEAT2_s
ALT_ECC_HMC_OCP_MPR_5BEAT2_t
;
1181
#endif
/* __ASSEMBLY__ */
1182
1184
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_RESET 0x00000000
1185
1186
#define ALT_ECC_HMC_OCP_MPR_5BEAT2_OFST 0x48
1187
1209
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_LSB 0
1210
1211
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_MSB 31
1212
1213
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_WIDTH 32
1214
1215
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET_MSK 0xffffffff
1216
1217
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_CLR_MSK 0x00000000
1218
1219
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_RESET 0x0
1220
1221
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_GET(value) (((value) & 0xffffffff) >> 0)
1222
1223
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_MPR192_SET(value) (((value) << 0) & 0xffffffff)
1224
1225
#ifndef __ASSEMBLY__
1226
1236
struct
ALT_ECC_HMC_OCP_MPR_6BEAT2_s
1237
{
1238
uint32_t
MPR192
: 32;
1239
};
1240
1242
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_6BEAT2_s
ALT_ECC_HMC_OCP_MPR_6BEAT2_t
;
1243
#endif
/* __ASSEMBLY__ */
1244
1246
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_RESET 0x00000000
1247
1248
#define ALT_ECC_HMC_OCP_MPR_6BEAT2_OFST 0x4c
1249
1271
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_LSB 0
1272
1273
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_MSB 31
1274
1275
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_WIDTH 32
1276
1277
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET_MSK 0xffffffff
1278
1279
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_CLR_MSK 0x00000000
1280
1281
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_RESET 0x0
1282
1283
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_GET(value) (((value) & 0xffffffff) >> 0)
1284
1285
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_MPR224_SET(value) (((value) << 0) & 0xffffffff)
1286
1287
#ifndef __ASSEMBLY__
1288
1298
struct
ALT_ECC_HMC_OCP_MPR_7BEAT2_s
1299
{
1300
uint32_t
MPR224
: 32;
1301
};
1302
1304
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_7BEAT2_s
ALT_ECC_HMC_OCP_MPR_7BEAT2_t
;
1305
#endif
/* __ASSEMBLY__ */
1306
1308
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_RESET 0x00000000
1309
1310
#define ALT_ECC_HMC_OCP_MPR_7BEAT2_OFST 0x50
1311
1333
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_LSB 0
1334
1335
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_MSB 31
1336
1337
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_WIDTH 32
1338
1339
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET_MSK 0xffffffff
1340
1341
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_CLR_MSK 0x00000000
1342
1343
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_RESET 0x0
1344
1345
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_GET(value) (((value) & 0xffffffff) >> 0)
1346
1347
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_MPR256_SET(value) (((value) << 0) & 0xffffffff)
1348
1349
#ifndef __ASSEMBLY__
1350
1360
struct
ALT_ECC_HMC_OCP_MPR_8BEAT2_s
1361
{
1362
uint32_t
MPR256
: 32;
1363
};
1364
1366
typedef
volatile
struct
ALT_ECC_HMC_OCP_MPR_8BEAT2_s
ALT_ECC_HMC_OCP_MPR_8BEAT2_t
;
1367
#endif
/* __ASSEMBLY__ */
1368
1370
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_RESET 0x00000000
1371
1372
#define ALT_ECC_HMC_OCP_MPR_8BEAT2_OFST 0x54
1373
1396
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_LSB 0
1397
1398
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_MSB 0
1399
1400
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_WIDTH 1
1401
1402
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET_MSK 0x00000001
1403
1404
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_CLR_MSK 0xfffffffe
1405
1406
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_RESET 0x0
1407
1408
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_GET(value) (((value) & 0x00000001) >> 0)
1409
1410
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_CTL_SET(value) (((value) << 0) & 0x00000001)
1411
1412
#ifndef __ASSEMBLY__
1413
1423
struct
ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s
1424
{
1425
uint32_t
CTRL
: 1;
1426
uint32_t : 31;
1427
};
1428
1430
typedef
volatile
struct
ALT_ECC_HMC_OCP_AUTO_PRECHARGE_s
ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t
;
1431
#endif
/* __ASSEMBLY__ */
1432
1434
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_RESET 0x00000000
1435
1436
#define ALT_ECC_HMC_OCP_AUTO_PRECHARGE_OFST 0x60
1437
1471
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_LSB 0
1472
1473
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_MSB 0
1474
1475
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_WIDTH 1
1476
1477
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET_MSK 0x00000001
1478
1479
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_CLR_MSK 0xfffffffe
1480
1481
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_RESET 0x0
1482
1483
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
1484
1485
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
1486
1500
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_LSB 8
1501
1502
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_MSB 8
1503
1504
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_WIDTH 1
1505
1506
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET_MSK 0x00000100
1507
1508
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_CLR_MSK 0xfffffeff
1509
1510
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_RESET 0x0
1511
1512
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_GET(value) (((value) & 0x00000100) >> 8)
1513
1514
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET(value) (((value) << 8) & 0x00000100)
1515
1529
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_LSB 16
1530
1531
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_MSB 16
1532
1533
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_WIDTH 1
1534
1535
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET_MSK 0x00010000
1536
1537
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_CLR_MSK 0xfffeffff
1538
1539
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_RESET 0x0
1540
1541
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_GET(value) (((value) & 0x00010000) >> 16)
1542
1543
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET(value) (((value) << 16) & 0x00010000)
1544
1545
#ifndef __ASSEMBLY__
1546
1556
struct
ALT_ECC_HMC_OCP_ECCCTL1_s
1557
{
1558
uint32_t
ECC_EN
: 1;
1559
uint32_t : 7;
1560
uint32_t
CNT_RST
: 1;
1561
uint32_t : 7;
1562
uint32_t
AUTOWB_CNT_RST
: 1;
1563
uint32_t : 15;
1564
};
1565
1567
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECCCTL1_s
ALT_ECC_HMC_OCP_ECCCTL1_t
;
1568
#endif
/* __ASSEMBLY__ */
1569
1571
#define ALT_ECC_HMC_OCP_ECCCTL1_RESET 0x00000000
1572
1573
#define ALT_ECC_HMC_OCP_ECCCTL1_OFST 0x100
1574
1611
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_LSB 0
1612
1613
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_MSB 0
1614
1615
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_WIDTH 1
1616
1617
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET_MSK 0x00000001
1618
1619
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_CLR_MSK 0xfffffffe
1620
1621
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_RESET 0x0
1622
1623
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0)
1624
1625
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001)
1626
1644
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_LSB 8
1645
1646
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_MSB 8
1647
1648
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_WIDTH 1
1649
1650
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100
1651
1652
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_CLR_MSK 0xfffffeff
1653
1654
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_RESET 0x0
1655
1656
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8)
1657
1658
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100)
1659
1674
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_LSB 16
1675
1676
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_MSB 16
1677
1678
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_WIDTH 1
1679
1680
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000
1681
1682
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff
1683
1684
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_RESET 0x0
1685
1686
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16)
1687
1688
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000)
1689
1690
#ifndef __ASSEMBLY__
1691
1701
struct
ALT_ECC_HMC_OCP_ECCCTL2_s
1702
{
1703
uint32_t
AUTOWB_EN
: 1;
1704
uint32_t : 7;
1705
uint32_t
RMW_EN
: 1;
1706
uint32_t : 7;
1707
uint32_t
OVRW_RB_ECC_EN
: 1;
1708
uint32_t : 15;
1709
};
1710
1712
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECCCTL2_s
ALT_ECC_HMC_OCP_ECCCTL2_t
;
1713
#endif
/* __ASSEMBLY__ */
1714
1716
#define ALT_ECC_HMC_OCP_ECCCTL2_RESET 0x00000000
1717
1718
#define ALT_ECC_HMC_OCP_ECCCTL2_OFST 0x104
1719
1749
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_LSB 0
1750
1751
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_MSB 0
1752
1753
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_WIDTH 1
1754
1755
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
1756
1757
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
1758
1759
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_RESET 0x0
1760
1761
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
1762
1763
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
1764
1781
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_LSB 1
1782
1783
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_MSB 1
1784
1785
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_WIDTH 1
1786
1787
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK 0x00000002
1788
1789
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_CLR_MSK 0xfffffffd
1790
1791
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_RESET 0x0
1792
1793
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_GET(value) (((value) & 0x00000002) >> 1)
1794
1795
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET(value) (((value) << 1) & 0x00000002)
1796
1815
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_LSB 2
1816
1817
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_MSB 2
1818
1819
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_WIDTH 1
1820
1821
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET_MSK 0x00000004
1822
1823
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_CLR_MSK 0xfffffffb
1824
1825
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_RESET 0x0
1826
1827
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_GET(value) (((value) & 0x00000004) >> 2)
1828
1829
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET(value) (((value) << 2) & 0x00000004)
1830
1831
#ifndef __ASSEMBLY__
1832
1842
struct
ALT_ECC_HMC_OCP_ERRINTEN_s
1843
{
1844
uint32_t
SERRINTEN
: 1;
1845
uint32_t
DERRINTEN
: 1;
1846
uint32_t
HMI_INTREN
: 1;
1847
uint32_t : 29;
1848
};
1849
1851
typedef
volatile
struct
ALT_ECC_HMC_OCP_ERRINTEN_s
ALT_ECC_HMC_OCP_ERRINTEN_t
;
1852
#endif
/* __ASSEMBLY__ */
1853
1855
#define ALT_ECC_HMC_OCP_ERRINTEN_RESET 0x00000000
1856
1857
#define ALT_ECC_HMC_OCP_ERRINTEN_OFST 0x110
1858
1891
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_LSB 0
1892
1893
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_MSB 0
1894
1895
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_WIDTH 1
1896
1897
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET_MSK 0x00000001
1898
1899
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
1900
1901
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_RESET 0x0
1902
1903
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
1904
1905
#define ALT_ECC_HMC_OCP_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
1906
1924
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_LSB 1
1925
1926
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_MSB 1
1927
1928
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_WIDTH 1
1929
1930
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET_MSK 0x00000002
1931
1932
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_CLR_MSK 0xfffffffd
1933
1934
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_RESET 0x0
1935
1936
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_GET(value) (((value) & 0x00000002) >> 1)
1937
1938
#define ALT_ECC_HMC_OCP_ERRINTENS_DERRINTS_SET(value) (((value) << 1) & 0x00000002)
1939
1955
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_LSB 2
1956
1957
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_MSB 2
1958
1959
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_WIDTH 1
1960
1961
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET_MSK 0x00000004
1962
1963
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_CLR_MSK 0xfffffffb
1964
1965
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_RESET 0x0
1966
1967
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_GET(value) (((value) & 0x00000004) >> 2)
1968
1969
#define ALT_ECC_HMC_OCP_ERRINTENS_HMI_INTRS_SET(value) (((value) << 2) & 0x00000004)
1970
1971
#ifndef __ASSEMBLY__
1972
1982
struct
ALT_ECC_HMC_OCP_ERRINTENS_s
1983
{
1984
uint32_t
SERRINTS
: 1;
1985
uint32_t
DERRINTS
: 1;
1986
uint32_t
HMI_INTRS
: 1;
1987
uint32_t : 29;
1988
};
1989
1991
typedef
volatile
struct
ALT_ECC_HMC_OCP_ERRINTENS_s
ALT_ECC_HMC_OCP_ERRINTENS_t
;
1992
#endif
/* __ASSEMBLY__ */
1993
1995
#define ALT_ECC_HMC_OCP_ERRINTENS_RESET 0x00000000
1996
1997
#define ALT_ECC_HMC_OCP_ERRINTENS_OFST 0x114
1998
2031
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_LSB 0
2032
2033
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_MSB 0
2034
2035
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_WIDTH 1
2036
2037
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET_MSK 0x00000001
2038
2039
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
2040
2041
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_RESET 0x0
2042
2043
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
2044
2045
#define ALT_ECC_HMC_OCP_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
2046
2064
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_LSB 1
2065
2066
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_MSB 1
2067
2068
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_WIDTH 1
2069
2070
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET_MSK 0x00000002
2071
2072
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_CLR_MSK 0xfffffffd
2073
2074
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_RESET 0x0
2075
2076
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_GET(value) (((value) & 0x00000002) >> 1)
2077
2078
#define ALT_ECC_HMC_OCP_ERRINTENR_DERRINTR_SET(value) (((value) << 1) & 0x00000002)
2079
2096
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_LSB 2
2097
2098
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_MSB 2
2099
2100
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_WIDTH 1
2101
2102
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET_MSK 0x00000004
2103
2104
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_CLR_MSK 0xfffffffb
2105
2106
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_RESET 0x0
2107
2108
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_GET(value) (((value) & 0x00000004) >> 2)
2109
2110
#define ALT_ECC_HMC_OCP_ERRINTENR_HMI_INTRR_SET(value) (((value) << 2) & 0x00000004)
2111
2112
#ifndef __ASSEMBLY__
2113
2123
struct
ALT_ECC_HMC_OCP_ERRINTENR_s
2124
{
2125
uint32_t
SERRINTR
: 1;
2126
uint32_t
DERRINTR
: 1;
2127
uint32_t
HMI_INTRR
: 1;
2128
uint32_t : 29;
2129
};
2130
2132
typedef
volatile
struct
ALT_ECC_HMC_OCP_ERRINTENR_s
ALT_ECC_HMC_OCP_ERRINTENR_t
;
2133
#endif
/* __ASSEMBLY__ */
2134
2136
#define ALT_ECC_HMC_OCP_ERRINTENR_RESET 0x00000000
2137
2138
#define ALT_ECC_HMC_OCP_ERRINTENR_OFST 0x118
2139
2172
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_LSB 0
2173
2174
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_MSB 0
2175
2176
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_WIDTH 1
2177
2178
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET_MSK 0x00000001
2179
2180
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_CLR_MSK 0xfffffffe
2181
2182
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_RESET 0x0
2183
2184
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
2185
2186
#define ALT_ECC_HMC_OCP_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
2187
2204
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_LSB 8
2205
2206
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_MSB 8
2207
2208
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_WIDTH 1
2209
2210
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET_MSK 0x00000100
2211
2212
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_CLR_MSK 0xfffffeff
2213
2214
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_RESET 0x0
2215
2216
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_GET(value) (((value) & 0x00000100) >> 8)
2217
2218
#define ALT_ECC_HMC_OCP_INTMOD_EXT_ADDRPARITY_EN_SET(value) (((value) << 8) & 0x00000100)
2219
2236
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_LSB 16
2237
2238
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_MSB 16
2239
2240
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_WIDTH 1
2241
2242
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET_MSK 0x00010000
2243
2244
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
2245
2246
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_RESET 0x0
2247
2248
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
2249
2250
#define ALT_ECC_HMC_OCP_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
2251
2268
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_LSB 24
2269
2270
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_MSB 24
2271
2272
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_WIDTH 1
2273
2274
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET_MSK 0x01000000
2275
2276
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_CLR_MSK 0xfeffffff
2277
2278
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_RESET 0x0
2279
2280
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_GET(value) (((value) & 0x01000000) >> 24)
2281
2282
#define ALT_ECC_HMC_OCP_INTMOD_AFICAL_EN_SET(value) (((value) << 24) & 0x01000000)
2283
2284
#ifndef __ASSEMBLY__
2285
2295
struct
ALT_ECC_HMC_OCP_INTMOD_s
2296
{
2297
uint32_t
INTMODE
: 1;
2298
uint32_t : 7;
2299
uint32_t
EXT_ADDRPARITY_EN
: 1;
2300
uint32_t : 7;
2301
uint32_t
INTONCMP
: 1;
2302
uint32_t : 7;
2303
uint32_t
AFICAL_EN
: 1;
2304
uint32_t : 7;
2305
};
2306
2308
typedef
volatile
struct
ALT_ECC_HMC_OCP_INTMOD_s
ALT_ECC_HMC_OCP_INTMOD_t
;
2309
#endif
/* __ASSEMBLY__ */
2310
2312
#define ALT_ECC_HMC_OCP_INTMOD_RESET 0x00000000
2313
2314
#define ALT_ECC_HMC_OCP_INTMOD_OFST 0x11c
2315
2351
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_LSB 0
2352
2353
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_MSB 0
2354
2355
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_WIDTH 1
2356
2357
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001
2358
2359
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
2360
2361
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_RESET 0x0
2362
2363
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
2364
2365
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
2366
2383
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_LSB 1
2384
2385
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_MSB 1
2386
2387
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_WIDTH 1
2388
2389
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002
2390
2391
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd
2392
2393
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_RESET 0x0
2394
2395
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1)
2396
2397
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002)
2398
2415
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_LSB 2
2416
2417
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_MSB 2
2418
2419
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_WIDTH 1
2420
2421
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET_MSK 0x00000004
2422
2423
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb
2424
2425
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_RESET 0x0
2426
2427
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2)
2428
2429
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004)
2430
2452
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_LSB 16
2453
2454
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_MSB 16
2455
2456
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_WIDTH 1
2457
2458
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000
2459
2460
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff
2461
2462
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_RESET 0x0
2463
2464
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16)
2465
2466
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000)
2467
2485
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_LSB 17
2486
2487
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_MSB 17
2488
2489
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_WIDTH 1
2490
2491
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000
2492
2493
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff
2494
2495
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_RESET 0x0
2496
2497
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17)
2498
2499
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000)
2500
2519
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_LSB 18
2520
2521
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_MSB 18
2522
2523
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_WIDTH 1
2524
2525
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000
2526
2527
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff
2528
2529
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_RESET 0x0
2530
2531
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18)
2532
2533
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000)
2534
2535
#ifndef __ASSEMBLY__
2536
2546
struct
ALT_ECC_HMC_OCP_INTSTAT_s
2547
{
2548
uint32_t
SERRPENA
: 1;
2549
uint32_t
DERRPENA
: 1;
2550
uint32_t
HMI_PENA
: 1;
2551
uint32_t : 13;
2552
uint32_t
ADDRMTCFLG
: 1;
2553
uint32_t
ADDRPARFLG
: 1;
2554
uint32_t
DERRBUSFLG
: 1;
2555
uint32_t : 13;
2556
};
2557
2559
typedef
volatile
struct
ALT_ECC_HMC_OCP_INTSTAT_s
ALT_ECC_HMC_OCP_INTSTAT_t
;
2560
#endif
/* __ASSEMBLY__ */
2561
2563
#define ALT_ECC_HMC_OCP_INTSTAT_RESET 0x00000000
2564
2565
#define ALT_ECC_HMC_OCP_INTSTAT_OFST 0x120
2566
2601
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_LSB 0
2602
2603
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_MSB 0
2604
2605
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_WIDTH 1
2606
2607
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET_MSK 0x00000001
2608
2609
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_CLR_MSK 0xfffffffe
2610
2611
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_RESET 0x0
2612
2613
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
2614
2615
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
2616
2635
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_LSB 8
2636
2637
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_MSB 8
2638
2639
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_WIDTH 1
2640
2641
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET_MSK 0x00000100
2642
2643
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_CLR_MSK 0xfffffeff
2644
2645
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_RESET 0x0
2646
2647
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
2648
2649
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
2650
2670
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_LSB 16
2671
2672
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_MSB 16
2673
2674
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_WIDTH 1
2675
2676
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET_MSK 0x00010000
2677
2678
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_CLR_MSK 0xfffeffff
2679
2680
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_RESET 0x0
2681
2682
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_GET(value) (((value) & 0x00010000) >> 16)
2683
2684
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET(value) (((value) << 16) & 0x00010000)
2685
2704
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_LSB 24
2705
2706
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_MSB 24
2707
2708
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_WIDTH 1
2709
2710
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET_MSK 0x01000000
2711
2712
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_CLR_MSK 0xfeffffff
2713
2714
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_RESET 0x0
2715
2716
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_GET(value) (((value) & 0x01000000) >> 24)
2717
2718
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET(value) (((value) << 24) & 0x01000000)
2719
2720
#ifndef __ASSEMBLY__
2721
2731
struct
ALT_ECC_HMC_OCP_DIAGINTTEST_s
2732
{
2733
uint32_t
TSERRA
: 1;
2734
uint32_t : 7;
2735
uint32_t
TDERRA
: 1;
2736
uint32_t : 7;
2737
uint32_t
TADDRMTC
: 1;
2738
uint32_t : 7;
2739
uint32_t
TADDRPAR
: 1;
2740
uint32_t : 7;
2741
};
2742
2744
typedef
volatile
struct
ALT_ECC_HMC_OCP_DIAGINTTEST_s
ALT_ECC_HMC_OCP_DIAGINTTEST_t
;
2745
#endif
/* __ASSEMBLY__ */
2746
2748
#define ALT_ECC_HMC_OCP_DIAGINTTEST_RESET 0x00000000
2749
2750
#define ALT_ECC_HMC_OCP_DIAGINTTEST_OFST 0x124
2751
2789
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_LSB 0
2790
2791
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_MSB 0
2792
2793
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_WIDTH 1
2794
2795
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET_MSK 0x00000001
2796
2797
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
2798
2799
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_RESET 0x0
2800
2801
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
2802
2803
#define ALT_ECC_HMC_OCP_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
2804
2830
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_LSB 8
2831
2832
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_MSB 8
2833
2834
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_WIDTH 1
2835
2836
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET_MSK 0x00000100
2837
2838
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_CLR_MSK 0xfffffeff
2839
2840
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_RESET 0x0
2841
2842
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_GET(value) (((value) & 0x00000100) >> 8)
2843
2844
#define ALT_ECC_HMC_OCP_MODSTAT_AUTOWB_DROP_FLG_SET(value) (((value) << 8) & 0x00000100)
2845
2846
#ifndef __ASSEMBLY__
2847
2857
struct
ALT_ECC_HMC_OCP_MODSTAT_s
2858
{
2859
uint32_t
CMPFLGA
: 1;
2860
uint32_t : 7;
2861
uint32_t
AUTOWB_DROP_FLG
: 1;
2862
uint32_t : 23;
2863
};
2864
2866
typedef
volatile
struct
ALT_ECC_HMC_OCP_MODSTAT_s
ALT_ECC_HMC_OCP_MODSTAT_t
;
2867
#endif
/* __ASSEMBLY__ */
2868
2870
#define ALT_ECC_HMC_OCP_MODSTAT_RESET 0x00000000
2871
2872
#define ALT_ECC_HMC_OCP_MODSTAT_OFST 0x128
2873
2901
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_LSB 0
2902
2903
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_MSB 31
2904
2905
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_WIDTH 32
2906
2907
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET_MSK 0xffffffff
2908
2909
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_CLR_MSK 0x00000000
2910
2911
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_RESET 0x0
2912
2913
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_GET(value) (((value) & 0xffffffff) >> 0)
2914
2915
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET(value) (((value) << 0) & 0xffffffff)
2916
2917
#ifndef __ASSEMBLY__
2918
2928
struct
ALT_ECC_HMC_OCP_DERRADDRA_s
2929
{
2930
uint32_t
DADDRESS
: 32;
2931
};
2932
2934
typedef
volatile
struct
ALT_ECC_HMC_OCP_DERRADDRA_s
ALT_ECC_HMC_OCP_DERRADDRA_t
;
2935
#endif
/* __ASSEMBLY__ */
2936
2938
#define ALT_ECC_HMC_OCP_DERRADDRA_RESET 0x00000000
2939
2940
#define ALT_ECC_HMC_OCP_DERRADDRA_OFST 0x12c
2941
2967
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_LSB 0
2968
2969
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_MSB 31
2970
2971
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_WIDTH 32
2972
2973
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET_MSK 0xffffffff
2974
2975
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_CLR_MSK 0x00000000
2976
2977
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_RESET 0x0
2978
2979
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_GET(value) (((value) & 0xffffffff) >> 0)
2980
2981
#define ALT_ECC_HMC_OCP_SERRADDRA_SADDR_SET(value) (((value) << 0) & 0xffffffff)
2982
2983
#ifndef __ASSEMBLY__
2984
2994
struct
ALT_ECC_HMC_OCP_SERRADDRA_s
2995
{
2996
uint32_t
SADDRESS
: 32;
2997
};
2998
3000
typedef
volatile
struct
ALT_ECC_HMC_OCP_SERRADDRA_s
ALT_ECC_HMC_OCP_SERRADDRA_t
;
3001
#endif
/* __ASSEMBLY__ */
3002
3004
#define ALT_ECC_HMC_OCP_SERRADDRA_RESET 0x00000000
3005
3006
#define ALT_ECC_HMC_OCP_SERRADDRA_OFST 0x130
3007
3033
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_LSB 0
3034
3035
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_MSB 31
3036
3037
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_WIDTH 32
3038
3039
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET_MSK 0xffffffff
3040
3041
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_CLR_MSK 0x00000000
3042
3043
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_RESET 0x0
3044
3045
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_GET(value) (((value) & 0xffffffff) >> 0)
3046
3047
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_SWBADDR_SET(value) (((value) << 0) & 0xffffffff)
3048
3049
#ifndef __ASSEMBLY__
3050
3060
struct
ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s
3061
{
3062
uint32_t
SWBADDRESS
: 32;
3063
};
3064
3066
typedef
volatile
struct
ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_s
ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t
;
3067
#endif
/* __ASSEMBLY__ */
3068
3070
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_RESET 0x00000000
3071
3072
#define ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_OFST 0x138
3073
3107
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_LSB 0
3108
3109
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_MSB 31
3110
3111
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_WIDTH 32
3112
3113
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
3114
3115
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
3116
3117
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_RESET 0x0
3118
3119
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
3120
3121
#define ALT_ECC_HMC_OCP_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
3122
3123
#ifndef __ASSEMBLY__
3124
3134
struct
ALT_ECC_HMC_OCP_SERRCNTREG_s
3135
{
3136
uint32_t
SERRCNT
: 32;
3137
};
3138
3140
typedef
volatile
struct
ALT_ECC_HMC_OCP_SERRCNTREG_s
ALT_ECC_HMC_OCP_SERRCNTREG_t
;
3141
#endif
/* __ASSEMBLY__ */
3142
3144
#define ALT_ECC_HMC_OCP_SERRCNTREG_RESET 0x00000000
3145
3146
#define ALT_ECC_HMC_OCP_SERRCNTREG_OFST 0x13c
3147
3181
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_LSB 0
3182
3183
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_MSB 31
3184
3185
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_WIDTH 32
3186
3187
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET_MSK 0xffffffff
3188
3189
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_CLR_MSK 0x00000000
3190
3191
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_RESET 0x1
3192
3193
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_GET(value) (((value) & 0xffffffff) >> 0)
3194
3195
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_CNT_SET(value) (((value) << 0) & 0xffffffff)
3196
3197
#ifndef __ASSEMBLY__
3198
3208
struct
ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s
3209
{
3210
uint32_t
CNT
: 32;
3211
};
3212
3214
typedef
volatile
struct
ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_s
ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t
;
3215
#endif
/* __ASSEMBLY__ */
3216
3218
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_RESET 0x00000001
3219
3220
#define ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_OFST 0x140
3221
3246
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_LSB 0
3247
3248
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_MSB 7
3249
3250
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_WIDTH 8
3251
3252
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3253
3254
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3255
3256
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_RESET 0x0
3257
3258
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3259
3260
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3261
3271
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_LSB 8
3272
3273
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_MSB 15
3274
3275
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_WIDTH 8
3276
3277
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3278
3279
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3280
3281
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_RESET 0x0
3282
3283
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3284
3285
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3286
3296
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_LSB 16
3297
3298
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_MSB 23
3299
3300
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_WIDTH 8
3301
3302
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3303
3304
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3305
3306
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_RESET 0x0
3307
3308
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3309
3310
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3311
3321
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_LSB 24
3322
3323
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_MSB 31
3324
3325
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_WIDTH 8
3326
3327
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3328
3329
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3330
3331
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_RESET 0x0
3332
3333
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3334
3335
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3336
3337
#ifndef __ASSEMBLY__
3338
3348
struct
ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s
3349
{
3350
uint32_t
ECC0BUS
: 8;
3351
uint32_t
ECC1BUS
: 8;
3352
uint32_t
ECC2BUS
: 8;
3353
uint32_t
ECC3BUS
: 8;
3354
};
3355
3357
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_s
ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t
;
3358
#endif
/* __ASSEMBLY__ */
3359
3361
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_RESET 0x00000000
3362
3363
#define ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_OFST 0x144
3364
3392
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_LSB 0
3393
3394
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_MSB 7
3395
3396
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_WIDTH 8
3397
3398
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET_MSK 0x000000ff
3399
3400
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_CLR_MSK 0xffffff00
3401
3402
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_RESET 0x0
3403
3404
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3405
3406
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3407
3420
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_LSB 8
3421
3422
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_MSB 15
3423
3424
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_WIDTH 8
3425
3426
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET_MSK 0x0000ff00
3427
3428
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_CLR_MSK 0xffff00ff
3429
3430
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_RESET 0x0
3431
3432
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3433
3434
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3435
3448
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_LSB 16
3449
3450
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_MSB 23
3451
3452
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_WIDTH 8
3453
3454
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET_MSK 0x00ff0000
3455
3456
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_CLR_MSK 0xff00ffff
3457
3458
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_RESET 0x0
3459
3460
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3461
3462
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3463
3476
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_LSB 24
3477
3478
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_MSB 31
3479
3480
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_WIDTH 8
3481
3482
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET_MSK 0xff000000
3483
3484
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_CLR_MSK 0x00ffffff
3485
3486
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_RESET 0x0
3487
3488
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3489
3490
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3491
3492
#ifndef __ASSEMBLY__
3493
3503
struct
ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s
3504
{
3505
uint32_t
ECC0BUS
: 8;
3506
uint32_t
ECC1BUS
: 8;
3507
uint32_t
ECC2BUS
: 8;
3508
uint32_t
ECC3BUS
: 8;
3509
};
3510
3512
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_s
ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t
;
3513
#endif
/* __ASSEMBLY__ */
3514
3516
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_RESET 0x00000000
3517
3518
#define ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_OFST 0x148
3519
3547
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0
3548
3549
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7
3550
3551
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8
3552
3553
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff
3554
3555
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00
3556
3557
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0
3558
3559
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
3560
3561
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
3562
3576
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8
3577
3578
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15
3579
3580
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8
3581
3582
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00
3583
3584
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff
3585
3586
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0
3587
3588
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
3589
3590
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
3591
3605
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16
3606
3607
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23
3608
3609
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8
3610
3611
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000
3612
3613
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff
3614
3615
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0
3616
3617
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
3618
3619
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
3620
3634
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24
3635
3636
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31
3637
3638
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8
3639
3640
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000
3641
3642
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff
3643
3644
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0
3645
3646
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
3647
3648
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
3649
3650
#ifndef __ASSEMBLY__
3651
3661
struct
ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s
3662
{
3663
uint32_t
ECC0BUS
: 8;
3664
uint32_t
ECC1BUS
: 8;
3665
uint32_t
ECC2BUS
: 8;
3666
uint32_t
ECC3BUS
: 8;
3667
};
3668
3670
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s
ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t
;
3671
#endif
/* __ASSEMBLY__ */
3672
3674
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_RESET 0x00000000
3675
3676
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_OFST 0x14c
3677
3711
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_LSB 0
3712
3713
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_MSB 0
3714
3715
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_WIDTH 1
3716
3717
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001
3718
3719
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe
3720
3721
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_RESET 0x0
3722
3723
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0)
3724
3725
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001)
3726
3746
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_LSB 1
3747
3748
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_MSB 1
3749
3750
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_WIDTH 1
3751
3752
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002
3753
3754
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd
3755
3756
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_RESET 0x0
3757
3758
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1)
3759
3760
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002)
3761
3777
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_LSB 16
3778
3779
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_MSB 16
3780
3781
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_WIDTH 1
3782
3783
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000
3784
3785
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff
3786
3787
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_RESET 0x0
3788
3789
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16)
3790
3791
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000)
3792
3793
#ifndef __ASSEMBLY__
3794
3804
struct
ALT_ECC_HMC_OCP_ECC_DIAGON_s
3805
{
3806
uint32_t
WRDIAGON
: 1;
3807
uint32_t
RDDIAGON
: 1;
3808
uint32_t : 14;
3809
uint32_t
ECCDIAGON
: 1;
3810
uint32_t : 15;
3811
};
3812
3814
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_DIAGON_s
ALT_ECC_HMC_OCP_ECC_DIAGON_t
;
3815
#endif
/* __ASSEMBLY__ */
3816
3818
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RESET 0x00000000
3819
3820
#define ALT_ECC_HMC_OCP_ECC_DIAGON_OFST 0x150
3821
3864
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_LSB 0
3865
3866
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_MSB 0
3867
3868
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_WIDTH 1
3869
3870
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK 0x00000001
3871
3872
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK 0xfffffffe
3873
3874
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_RESET 0x0
3875
3876
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_GET(value) (((value) & 0x00000001) >> 0)
3877
3878
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET(value) (((value) << 0) & 0x00000001)
3879
3898
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_LSB 1
3899
3900
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_MSB 1
3901
3902
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_WIDTH 1
3903
3904
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK 0x00000002
3905
3906
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK 0xfffffffd
3907
3908
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_RESET 0x0
3909
3910
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_GET(value) (((value) & 0x00000002) >> 1)
3911
3912
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET(value) (((value) << 1) & 0x00000002)
3913
3932
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_LSB 2
3933
3934
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_MSB 2
3935
3936
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_WIDTH 1
3937
3938
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK 0x00000004
3939
3940
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK 0xfffffffb
3941
3942
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_RESET 0x0
3943
3944
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_GET(value) (((value) & 0x00000004) >> 2)
3945
3946
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET(value) (((value) << 2) & 0x00000004)
3947
3966
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_LSB 3
3967
3968
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_MSB 3
3969
3970
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_WIDTH 1
3971
3972
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK 0x00000008
3973
3974
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK 0xfffffff7
3975
3976
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_RESET 0x0
3977
3978
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_GET(value) (((value) & 0x00000008) >> 3)
3979
3980
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET(value) (((value) << 3) & 0x00000008)
3981
4000
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_LSB 4
4001
4002
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_MSB 4
4003
4004
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH 1
4005
4006
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK 0x00000010
4007
4008
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK 0xffffffef
4009
4010
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_RESET 0x0
4011
4012
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_GET(value) (((value) & 0x00000010) >> 4)
4013
4014
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET(value) (((value) << 4) & 0x00000010)
4015
4034
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_LSB 5
4035
4036
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_MSB 5
4037
4038
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH 1
4039
4040
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK 0x00000020
4041
4042
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK 0xffffffdf
4043
4044
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_RESET 0x0
4045
4046
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_GET(value) (((value) & 0x00000020) >> 5)
4047
4048
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET(value) (((value) << 5) & 0x00000020)
4049
4068
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_LSB 6
4069
4070
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_MSB 6
4071
4072
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH 1
4073
4074
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK 0x00000040
4075
4076
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK 0xffffffbf
4077
4078
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_RESET 0x0
4079
4080
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_GET(value) (((value) & 0x00000040) >> 6)
4081
4082
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET(value) (((value) << 6) & 0x00000040)
4083
4102
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_LSB 7
4103
4104
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_MSB 7
4105
4106
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH 1
4107
4108
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK 0x00000080
4109
4110
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK 0xffffff7f
4111
4112
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_RESET 0x0
4113
4114
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_GET(value) (((value) & 0x00000080) >> 7)
4115
4116
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET(value) (((value) << 7) & 0x00000080)
4117
4136
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_LSB 8
4137
4138
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_MSB 8
4139
4140
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_WIDTH 1
4141
4142
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK 0x00000100
4143
4144
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK 0xfffffeff
4145
4146
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_RESET 0x0
4147
4148
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_GET(value) (((value) & 0x00000100) >> 8)
4149
4150
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET(value) (((value) << 8) & 0x00000100)
4151
4170
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_LSB 9
4171
4172
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_MSB 9
4173
4174
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_WIDTH 1
4175
4176
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK 0x00000200
4177
4178
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK 0xfffffdff
4179
4180
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_RESET 0x0
4181
4182
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_GET(value) (((value) & 0x00000200) >> 9)
4183
4184
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET(value) (((value) << 9) & 0x00000200)
4185
4204
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_LSB 10
4205
4206
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_MSB 10
4207
4208
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_WIDTH 1
4209
4210
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK 0x00000400
4211
4212
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK 0xfffffbff
4213
4214
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_RESET 0x0
4215
4216
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_GET(value) (((value) & 0x00000400) >> 10)
4217
4218
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET(value) (((value) << 10) & 0x00000400)
4219
4238
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_LSB 11
4239
4240
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_MSB 11
4241
4242
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_WIDTH 1
4243
4244
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK 0x00000800
4245
4246
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK 0xfffff7ff
4247
4248
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_RESET 0x0
4249
4250
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_GET(value) (((value) & 0x00000800) >> 11)
4251
4252
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET(value) (((value) << 11) & 0x00000800)
4253
4254
#ifndef __ASSEMBLY__
4255
4265
struct
ALT_ECC_HMC_OCP_ECC_DECSTAT_s
4266
{
4267
uint32_t
DEC0SERRFLG
: 1;
4268
uint32_t
DEC1SERRFLG
: 1;
4269
uint32_t
DEC2SERRFLG
: 1;
4270
uint32_t
DEC3SERRFLG
: 1;
4271
uint32_t
DEC0ADDRFLG
: 1;
4272
uint32_t
DEC1ADDRFLG
: 1;
4273
uint32_t
DEC2ADDRFLG
: 1;
4274
uint32_t
DEC3ADDRFLG
: 1;
4275
uint32_t
DEC0DERRFLG
: 1;
4276
uint32_t
DEC1DERRFLG
: 1;
4277
uint32_t
DEC2DERRFLG
: 1;
4278
uint32_t
DEC3DERRFLG
: 1;
4279
uint32_t : 20;
4280
};
4281
4283
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_DECSTAT_s
ALT_ECC_HMC_OCP_ECC_DECSTAT_t
;
4284
#endif
/* __ASSEMBLY__ */
4285
4287
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_RESET 0x00000000
4288
4289
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_OFST 0x154
4290
4315
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_LSB 0
4316
4317
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_MSB 31
4318
4319
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_WIDTH 32
4320
4321
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET_MSK 0xffffffff
4322
4323
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_CLR_MSK 0x00000000
4324
4325
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_RESET 0x0
4326
4327
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4328
4329
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4330
4331
#ifndef __ASSEMBLY__
4332
4342
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s
4343
{
4344
uint32_t
ADDR
: 32;
4345
};
4346
4348
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t
;
4349
#endif
/* __ASSEMBLY__ */
4350
4352
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_RESET 0x00000000
4353
4354
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_OFST 0x160
4355
4380
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_LSB 0
4381
4382
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_MSB 31
4383
4384
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_WIDTH 32
4385
4386
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET_MSK 0xffffffff
4387
4388
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_CLR_MSK 0x00000000
4389
4390
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_RESET 0x0
4391
4392
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4393
4394
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4395
4396
#ifndef __ASSEMBLY__
4397
4407
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s
4408
{
4409
uint32_t
ADDR
: 32;
4410
};
4411
4413
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_s
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t
;
4414
#endif
/* __ASSEMBLY__ */
4415
4417
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_RESET 0x00000000
4418
4419
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_OFST 0x164
4420
4445
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_LSB 0
4446
4447
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_MSB 31
4448
4449
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_WIDTH 32
4450
4451
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET_MSK 0xffffffff
4452
4453
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_CLR_MSK 0x00000000
4454
4455
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_RESET 0x0
4456
4457
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4458
4459
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4460
4461
#ifndef __ASSEMBLY__
4462
4472
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s
4473
{
4474
uint32_t
ADDR
: 32;
4475
};
4476
4478
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_s
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t
;
4479
#endif
/* __ASSEMBLY__ */
4480
4482
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_RESET 0x00000000
4483
4484
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_OFST 0x168
4485
4510
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_LSB 0
4511
4512
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_MSB 31
4513
4514
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_WIDTH 32
4515
4516
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET_MSK 0xffffffff
4517
4518
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_CLR_MSK 0x00000000
4519
4520
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_RESET 0x0
4521
4522
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4523
4524
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4525
4526
#ifndef __ASSEMBLY__
4527
4537
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s
4538
{
4539
uint32_t
ADDR
: 32;
4540
};
4541
4543
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_s
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t
;
4544
#endif
/* __ASSEMBLY__ */
4545
4547
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_RESET 0x00000000
4548
4549
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_OFST 0x16c
4550
4575
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_LSB 0
4576
4577
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_MSB 7
4578
4579
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_WIDTH 8
4580
4581
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET_MSK 0x000000ff
4582
4583
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_CLR_MSK 0xffffff00
4584
4585
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_RESET 0x0
4586
4587
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4588
4589
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4590
4600
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_LSB 8
4601
4602
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_MSB 15
4603
4604
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_WIDTH 8
4605
4606
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET_MSK 0x0000ff00
4607
4608
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_CLR_MSK 0xffff00ff
4609
4610
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_RESET 0x0
4611
4612
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4613
4614
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4615
4625
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_LSB 16
4626
4627
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_MSB 23
4628
4629
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_WIDTH 8
4630
4631
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET_MSK 0x00ff0000
4632
4633
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_CLR_MSK 0xff00ffff
4634
4635
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_RESET 0x0
4636
4637
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4638
4639
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4640
4650
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_LSB 24
4651
4652
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_MSB 31
4653
4654
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_WIDTH 8
4655
4656
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET_MSK 0xff000000
4657
4658
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_CLR_MSK 0x00ffffff
4659
4660
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_RESET 0x0
4661
4662
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4663
4664
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4665
4666
#ifndef __ASSEMBLY__
4667
4677
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s
4678
{
4679
uint32_t
ECC0BUS
: 8;
4680
uint32_t
ECC1BUS
: 8;
4681
uint32_t
ECC2BUS
: 8;
4682
uint32_t
ECC3BUS
: 8;
4683
};
4684
4686
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_s
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t
;
4687
#endif
/* __ASSEMBLY__ */
4688
4690
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_RESET 0x00000000
4691
4692
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_OFST 0x170
4693
4718
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_LSB 0
4719
4720
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_MSB 7
4721
4722
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_WIDTH 8
4723
4724
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET_MSK 0x000000ff
4725
4726
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_CLR_MSK 0xffffff00
4727
4728
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_RESET 0x0
4729
4730
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4731
4732
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4733
4743
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_LSB 8
4744
4745
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_MSB 15
4746
4747
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_WIDTH 8
4748
4749
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET_MSK 0x0000ff00
4750
4751
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_CLR_MSK 0xffff00ff
4752
4753
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_RESET 0x0
4754
4755
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4756
4757
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4758
4768
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_LSB 16
4769
4770
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_MSB 23
4771
4772
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_WIDTH 8
4773
4774
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET_MSK 0x00ff0000
4775
4776
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_CLR_MSK 0xff00ffff
4777
4778
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_RESET 0x0
4779
4780
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4781
4782
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4783
4793
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_LSB 24
4794
4795
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_MSB 31
4796
4797
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_WIDTH 8
4798
4799
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET_MSK 0xff000000
4800
4801
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_CLR_MSK 0x00ffffff
4802
4803
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_RESET 0x0
4804
4805
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4806
4807
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4808
4809
#ifndef __ASSEMBLY__
4810
4820
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s
4821
{
4822
uint32_t
ECC0BUS
: 8;
4823
uint32_t
ECC1BUS
: 8;
4824
uint32_t
ECC2BUS
: 8;
4825
uint32_t
ECC3BUS
: 8;
4826
};
4827
4829
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_s
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t
;
4830
#endif
/* __ASSEMBLY__ */
4831
4833
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_RESET 0x00000000
4834
4835
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_OFST 0x174
4836
4861
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_LSB 0
4862
4863
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_MSB 7
4864
4865
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_WIDTH 8
4866
4867
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET_MSK 0x000000ff
4868
4869
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_CLR_MSK 0xffffff00
4870
4871
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_RESET 0x0
4872
4873
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
4874
4875
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
4876
4886
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_LSB 8
4887
4888
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_MSB 15
4889
4890
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_WIDTH 8
4891
4892
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET_MSK 0x0000ff00
4893
4894
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_CLR_MSK 0xffff00ff
4895
4896
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_RESET 0x0
4897
4898
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
4899
4900
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
4901
4911
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_LSB 16
4912
4913
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_MSB 23
4914
4915
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_WIDTH 8
4916
4917
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET_MSK 0x00ff0000
4918
4919
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_CLR_MSK 0xff00ffff
4920
4921
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_RESET 0x0
4922
4923
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
4924
4925
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
4926
4936
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_LSB 24
4937
4938
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_MSB 31
4939
4940
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_WIDTH 8
4941
4942
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET_MSK 0xff000000
4943
4944
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_CLR_MSK 0x00ffffff
4945
4946
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_RESET 0x0
4947
4948
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
4949
4950
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
4951
4952
#ifndef __ASSEMBLY__
4953
4963
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s
4964
{
4965
uint32_t
ECC0BUS
: 8;
4966
uint32_t
ECC1BUS
: 8;
4967
uint32_t
ECC2BUS
: 8;
4968
uint32_t
ECC3BUS
: 8;
4969
};
4970
4972
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_s
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t
;
4973
#endif
/* __ASSEMBLY__ */
4974
4976
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_RESET 0x00000000
4977
4978
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_OFST 0x178
4979
5004
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_LSB 0
5005
5006
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_MSB 7
5007
5008
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_WIDTH 8
5009
5010
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET_MSK 0x000000ff
5011
5012
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_CLR_MSK 0xffffff00
5013
5014
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_RESET 0x0
5015
5016
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0)
5017
5018
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff)
5019
5029
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_LSB 8
5030
5031
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_MSB 15
5032
5033
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_WIDTH 8
5034
5035
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET_MSK 0x0000ff00
5036
5037
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_CLR_MSK 0xffff00ff
5038
5039
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_RESET 0x0
5040
5041
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8)
5042
5043
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00)
5044
5054
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_LSB 16
5055
5056
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_MSB 23
5057
5058
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_WIDTH 8
5059
5060
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET_MSK 0x00ff0000
5061
5062
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_CLR_MSK 0xff00ffff
5063
5064
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_RESET 0x0
5065
5066
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16)
5067
5068
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000)
5069
5079
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_LSB 24
5080
5081
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_MSB 31
5082
5083
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_WIDTH 8
5084
5085
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET_MSK 0xff000000
5086
5087
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_CLR_MSK 0x00ffffff
5088
5089
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_RESET 0x0
5090
5091
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24)
5092
5093
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_ECC3BUS_SET(value) (((value) << 24) & 0xff000000)
5094
5095
#ifndef __ASSEMBLY__
5096
5106
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s
5107
{
5108
uint32_t
ECC0BUS
: 8;
5109
uint32_t
ECC1BUS
: 8;
5110
uint32_t
ECC2BUS
: 8;
5111
uint32_t
ECC3BUS
: 8;
5112
};
5113
5115
typedef
volatile
struct
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_s
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t
;
5116
#endif
/* __ASSEMBLY__ */
5117
5119
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_RESET 0x00000000
5120
5121
#define ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_OFST 0x17c
5122
5123
#ifndef __ASSEMBLY__
5124
5134
struct
ALT_ECC_HMC_OCP_s
5135
{
5136
volatile
ALT_ECC_HMC_OCP_IP_REV_ID_t
IP_REV_ID
;
5137
volatile
uint32_t
_pad_0x4_0x7
;
5138
volatile
ALT_ECC_HMC_OCP_DDRIOCTL_t
DDRIOCTRL
;
5139
volatile
ALT_ECC_HMC_OCP_DDRCALSTAT_t
DDRCALSTAT
;
5140
volatile
ALT_ECC_HMC_OCP_MPR_0BEAT1_t
MPR_0BEAT1
;
5141
volatile
ALT_ECC_HMC_OCP_MPR_1BEAT1_t
MPR_1BEAT1
;
5142
volatile
ALT_ECC_HMC_OCP_MPR_2BEAT1_t
MPR_2BEAT1
;
5143
volatile
ALT_ECC_HMC_OCP_MPR_3BEAT1_t
MPR_3BEAT1
;
5144
volatile
ALT_ECC_HMC_OCP_MPR_4BEAT1_t
MPR_4BEAT1
;
5145
volatile
ALT_ECC_HMC_OCP_MPR_5BEAT1_t
MPR_5BEAT1
;
5146
volatile
ALT_ECC_HMC_OCP_MPR_6BEAT1_t
MPR_6BEAT1
;
5147
volatile
ALT_ECC_HMC_OCP_MPR_7BEAT1_t
MPR_7BEAT1
;
5148
volatile
ALT_ECC_HMC_OCP_MPR_8BEAT1_t
MPR_8BEAT1
;
5149
volatile
ALT_ECC_HMC_OCP_MPR_0BEAT2_t
MPR_0BEAT2
;
5150
volatile
ALT_ECC_HMC_OCP_MPR_1BEAT2_t
MPR_1BEAT2
;
5151
volatile
ALT_ECC_HMC_OCP_MPR_2BEAT2_t
MPR_2BEAT2
;
5152
volatile
ALT_ECC_HMC_OCP_MPR_3BEAT2_t
MPR_3BEAT2
;
5153
volatile
ALT_ECC_HMC_OCP_MPR_4BEAT2_t
MPR_4BEAT2
;
5154
volatile
ALT_ECC_HMC_OCP_MPR_5BEAT2_t
MPR_5BEAT2
;
5155
volatile
ALT_ECC_HMC_OCP_MPR_6BEAT2_t
MPR_6BEAT2
;
5156
volatile
ALT_ECC_HMC_OCP_MPR_7BEAT2_t
MPR_7BEAT2
;
5157
volatile
ALT_ECC_HMC_OCP_MPR_8BEAT2_t
MPR_8BEAT2
;
5158
volatile
uint32_t
_pad_0x58_0x5f
[2];
5159
volatile
ALT_ECC_HMC_OCP_AUTO_PRECHARGE_t
AUTO_PRECHARGE
;
5160
volatile
uint32_t
_pad_0x64_0xff
[39];
5161
volatile
ALT_ECC_HMC_OCP_ECCCTL1_t
ECCCTRL1
;
5162
volatile
ALT_ECC_HMC_OCP_ECCCTL2_t
ECCCTRL2
;
5163
volatile
uint32_t
_pad_0x108_0x10f
[2];
5164
volatile
ALT_ECC_HMC_OCP_ERRINTEN_t
ERRINTEN
;
5165
volatile
ALT_ECC_HMC_OCP_ERRINTENS_t
ERRINTENS
;
5166
volatile
ALT_ECC_HMC_OCP_ERRINTENR_t
ERRINTENR
;
5167
volatile
ALT_ECC_HMC_OCP_INTMOD_t
INTMODE
;
5168
volatile
ALT_ECC_HMC_OCP_INTSTAT_t
INTSTAT
;
5169
volatile
ALT_ECC_HMC_OCP_DIAGINTTEST_t
DIAGINTTEST
;
5170
volatile
ALT_ECC_HMC_OCP_MODSTAT_t
MODSTAT
;
5171
volatile
ALT_ECC_HMC_OCP_DERRADDRA_t
DERRADDRA
;
5172
volatile
ALT_ECC_HMC_OCP_SERRADDRA_t
SERRADDRA
;
5173
volatile
uint32_t
_pad_0x134_0x137
;
5174
volatile
ALT_ECC_HMC_OCP_AUTOWB_CORRADDR_t
AUTOWB_CORRADDR
;
5175
volatile
ALT_ECC_HMC_OCP_SERRCNTREG_t
SERRCNTREG
;
5176
volatile
ALT_ECC_HMC_OCP_AUTOWB_DROP_CNTREG_t
AUTOWB_DROP_CNTREG
;
5177
volatile
ALT_ECC_HMC_OCP_ECC_REG2WRECCDATABUS_t
ECC_REG2WRECCDATABUS
;
5178
volatile
ALT_ECC_HMC_OCP_ECC_RDECCDATA2REGBUS_t
ECC_RDECCDATA2REGBUS
;
5179
volatile
ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t
ECC_REG2RDECCDATABUS
;
5180
volatile
ALT_ECC_HMC_OCP_ECC_DIAGON_t
ECC_DIAGON
;
5181
volatile
ALT_ECC_HMC_OCP_ECC_DECSTAT_t
ECC_DECSTAT
;
5182
volatile
uint32_t
_pad_0x158_0x15f
[2];
5183
volatile
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t
ECC_ERRGENADDR_0
;
5184
volatile
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_1_t
ECC_ERRGENADDR_1
;
5185
volatile
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_2_t
ECC_ERRGENADDR_2
;
5186
volatile
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_3_t
ECC_ERRGENADDR_3
;
5187
volatile
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT0_t
ECC_REG2RDDATABUS_BEAT0
;
5188
volatile
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT1_t
ECC_REG2RDDATABUS_BEAT1
;
5189
volatile
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT2_t
ECC_REG2RDDATABUS_BEAT2
;
5190
volatile
ALT_ECC_HMC_OCP_ECC_REG2RDDATABUS_BEAT3_t
ECC_REG2RDDATABUS_BEAT3
;
5191
volatile
uint32_t
_pad_0x180_0x500
[224];
5192
};
5193
5195
typedef
volatile
struct
ALT_ECC_HMC_OCP_s
ALT_ECC_HMC_OCP_t
;
5197
struct
ALT_ECC_HMC_OCP_raw_s
5198
{
5199
volatile
uint32_t
IP_REV_ID
;
5200
volatile
uint32_t
_pad_0x4_0x7
;
5201
volatile
uint32_t
DDRIOCTRL
;
5202
volatile
uint32_t
DDRCALSTAT
;
5203
volatile
uint32_t
MPR_0BEAT1
;
5204
volatile
uint32_t
MPR_1BEAT1
;
5205
volatile
uint32_t
MPR_2BEAT1
;
5206
volatile
uint32_t
MPR_3BEAT1
;
5207
volatile
uint32_t
MPR_4BEAT1
;
5208
volatile
uint32_t
MPR_5BEAT1
;
5209
volatile
uint32_t
MPR_6BEAT1
;
5210
volatile
uint32_t
MPR_7BEAT1
;
5211
volatile
uint32_t
MPR_8BEAT1
;
5212
volatile
uint32_t
MPR_0BEAT2
;
5213
volatile
uint32_t
MPR_1BEAT2
;
5214
volatile
uint32_t
MPR_2BEAT2
;
5215
volatile
uint32_t
MPR_3BEAT2
;
5216
volatile
uint32_t
MPR_4BEAT2
;
5217
volatile
uint32_t
MPR_5BEAT2
;
5218
volatile
uint32_t
MPR_6BEAT2
;
5219
volatile
uint32_t
MPR_7BEAT2
;
5220
volatile
uint32_t
MPR_8BEAT2
;
5221
volatile
uint32_t
_pad_0x58_0x5f
[2];
5222
volatile
uint32_t
AUTO_PRECHARGE
;
5223
volatile
uint32_t
_pad_0x64_0xff
[39];
5224
volatile
uint32_t
ECCCTRL1
;
5225
volatile
uint32_t
ECCCTRL2
;
5226
volatile
uint32_t
_pad_0x108_0x10f
[2];
5227
volatile
uint32_t
ERRINTEN
;
5228
volatile
uint32_t
ERRINTENS
;
5229
volatile
uint32_t
ERRINTENR
;
5230
volatile
uint32_t
INTMODE
;
5231
volatile
uint32_t
INTSTAT
;
5232
volatile
uint32_t
DIAGINTTEST
;
5233
volatile
uint32_t
MODSTAT
;
5234
volatile
uint32_t
DERRADDRA
;
5235
volatile
uint32_t
SERRADDRA
;
5236
volatile
uint32_t
_pad_0x134_0x137
;
5237
volatile
uint32_t
AUTOWB_CORRADDR
;
5238
volatile
uint32_t
SERRCNTREG
;
5239
volatile
uint32_t
AUTOWB_DROP_CNTREG
;
5240
volatile
uint32_t
ECC_REG2WRECCDATABUS
;
5241
volatile
uint32_t
ECC_RDECCDATA2REGBUS
;
5242
volatile
uint32_t
ECC_REG2RDECCDATABUS
;
5243
volatile
uint32_t
ECC_DIAGON
;
5244
volatile
uint32_t
ECC_DECSTAT
;
5245
volatile
uint32_t
_pad_0x158_0x15f
[2];
5246
volatile
uint32_t
ECC_ERRGENADDR_0
;
5247
volatile
uint32_t
ECC_ERRGENADDR_1
;
5248
volatile
uint32_t
ECC_ERRGENADDR_2
;
5249
volatile
uint32_t
ECC_ERRGENADDR_3
;
5250
volatile
uint32_t
ECC_REG2RDDATABUS_BEAT0
;
5251
volatile
uint32_t
ECC_REG2RDDATABUS_BEAT1
;
5252
volatile
uint32_t
ECC_REG2RDDATABUS_BEAT2
;
5253
volatile
uint32_t
ECC_REG2RDDATABUS_BEAT3
;
5254
volatile
uint32_t
_pad_0x180_0x500
[224];
5255
};
5256
5258
typedef
volatile
struct
ALT_ECC_HMC_OCP_raw_s
ALT_ECC_HMC_OCP_raw_t
;
5259
#endif
/* __ASSEMBLY__ */
5260
5262
#ifdef __cplusplus
5263
}
5264
#endif
/* __cplusplus */
5265
#endif
/* __ALT_SOCAL_ECC_HMC_OCP_H__ */
5266
include
soc_a10
socal
alt_ecc_hmc_ocp.h
Generated on Tue Sep 8 2015 13:32:55 for Altera SoCAL by
1.8.2