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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock enables for clocks derived from the Peripheral PLL
1: The clock is enabled.
0: The clock is disabled.
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | emac0_clk Enable |
[1] | RW | 0x1 | emac1_clk Enable |
[2] | RW | 0x1 | usb_mp_clk Enable |
[3] | RW | 0x1 | spi_m_clk Enable |
[4] | RW | 0x1 | can0_clk Enable |
[5] | RW | 0x1 | can1_clk Enable |
[6] | RW | 0x1 | gpio_clk Enable |
[7] | RW | 0x1 | s2f_user1_clk Enable |
[8] | RW | 0x1 | sdmmc_clk Enable |
[9] | RW | 0x1 | nand_x_clk Enable |
[10] | RW | 0x1 | nand_clk Enable |
[11] | RW | 0x1 | qspi_clk Enable |
[31:12] | ??? | 0x0 | UNDEFINED |
Field : emac0_clk Enable - emac0clk | |
Enables clock emac0_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001) |
Field : emac1_clk Enable - emac1clk | |
Enables clock emac1_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002) |
Field : usb_mp_clk Enable - usbclk | |
Enables clock usb_mp_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004) |
Field : spi_m_clk Enable - spimclk | |
Enables clock spi_m_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008) |
Field : can0_clk Enable - can0clk | |
Enables clock can0_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010) |
Field : can1_clk Enable - can1clk | |
Enables clock can1_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020) |
Field : gpio_clk Enable - gpioclk | |
Enables clock gpio_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040) |
Field : s2f_user1_clk Enable - s2fuser1clk | |
Enables clock s2f_user1_clk output. Qsys and user documenation refer to s2f_user1_clk as h2f_user1_clk. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080) |
Field : sdmmc_clk Enable - sdmmcclk | |
Enables clock sdmmc_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100) |
Field : nand_x_clk Enable - nandxclk | |
Enables clock nand_x_clk output nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and the nand_x_clk Enable should always be asserted before the nand_clk Enable is asserted. A brief delay is also required between switching the enables (8 * nand_clk period). Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200) |
Field : nand_clk Enable - nandclk | |
Enables clock nand_clk output nand_clk Enable should always be de-asserted before the nand_x_clk Enable, and the nand_x_clk Enable should always be asserted before the nand_clk Enable is asserted. A brief delay is also required between switching the enables (8 * nand_clk period). Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400) |
Field : qspi_clk Enable - qspiclk | |
Enables clock qspi_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800) |
Data Structures | |
struct | ALT_CLKMGR_PERPLL_EN_s |
Macros | |
#define | ALT_CLKMGR_PERPLL_EN_OFST 0x20 |
Typedefs | |
typedef struct ALT_CLKMGR_PERPLL_EN_s | ALT_CLKMGR_PERPLL_EN_t |
struct ALT_CLKMGR_PERPLL_EN_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_PERPLL_EN.
Data Fields | ||
---|---|---|
uint32_t | emac0clk: 1 | emac0_clk Enable |
uint32_t | emac1clk: 1 | emac1_clk Enable |
uint32_t | usbclk: 1 | usb_mp_clk Enable |
uint32_t | spimclk: 1 | spi_m_clk Enable |
uint32_t | can0clk: 1 | can0_clk Enable |
uint32_t | can1clk: 1 | can1_clk Enable |
uint32_t | gpioclk: 1 | gpio_clk Enable |
uint32_t | s2fuser1clk: 1 | s2f_user1_clk Enable |
uint32_t | sdmmcclk: 1 | sdmmc_clk Enable |
uint32_t | nandxclk: 1 | nand_x_clk Enable |
uint32_t | nandclk: 1 | nand_clk Enable |
uint32_t | qspiclk: 1 | qspi_clk Enable |
uint32_t | __pad0__: 20 | UNDEFINED |
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_PERPLL_EN_EMAC0CLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_PERPLL_EN_EMAC0CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_PERPLL_EN_EMAC1CLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_PERPLL_EN_EMAC1CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_USBCLK register field.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_USBCLK register field.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_USBCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_USBCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_USBCLK register field.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_PERPLL_EN_USBCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_PERPLL_EN_USBCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_CLKMGR_PERPLL_EN_SPIMCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_CLKMGR_PERPLL_EN_SPIMCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_CLKMGR_PERPLL_EN_CAN0CLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_CLKMGR_PERPLL_EN_CAN0CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_CLKMGR_PERPLL_EN_CAN1CLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_CLKMGR_PERPLL_EN_CAN1CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_GPIOCLK register field.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_CLKMGR_PERPLL_EN_GPIOCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_CLKMGR_PERPLL_EN_GPIOCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_CLKMGR_PERPLL_EN_SDMMCCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_CLKMGR_PERPLL_EN_SDMMCCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_NANDXCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_CLKMGR_PERPLL_EN_NANDXCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_CLKMGR_PERPLL_EN_NANDXCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_NANDCLK register field value.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_NANDCLK register field.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_CLKMGR_PERPLL_EN_NANDCLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_CLKMGR_PERPLL_EN_NANDCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800 |
The mask used to set the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_CLKMGR_PERPLL_EN_QSPICLK register field value.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_EN_QSPICLK register field.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_CLKMGR_PERPLL_EN_QSPICLK field value from a register.
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_CLKMGR_PERPLL_EN_QSPICLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EN_OFST 0x20 |
The byte offset of the ALT_CLKMGR_PERPLL_EN register from the beginning of the component.
typedef struct ALT_CLKMGR_PERPLL_EN_s ALT_CLKMGR_PERPLL_EN_t |
The typedef declaration for register ALT_CLKMGR_PERPLL_EN.