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The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_rstmgr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_RSTMGR_H__
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#define __ALT_SOCAL_RSTMGR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_LSB 0
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_MSB 0
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_WIDTH 1
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET_MSK 0x00000001
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_CLR_MSK 0xfffffffe
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_RESET 0x0
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_LSB 1
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_MSB 1
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_WIDTH 1
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET_MSK 0x00000002
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_CLR_MSK 0xfffffffd
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_RESET 0x0
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_RSTMGR_STAT_NPORPINRST_LSB 2
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#define ALT_RSTMGR_STAT_NPORPINRST_MSB 2
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#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
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#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000004
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#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffb
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#define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
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#define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 3
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#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 3
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#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
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#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000008
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#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffff7
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#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
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#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 4
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 4
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000010
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xffffffef
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_RSTMGR_STAT_SWCOLDRST_LSB 5
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#define ALT_RSTMGR_STAT_SWCOLDRST_MSB 5
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#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
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#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000020
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#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffdf
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#define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
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#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
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#define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
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#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
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#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
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#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
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#define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
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#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
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#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
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#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
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#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
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#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
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#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
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#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
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#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
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#define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
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#define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
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#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
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#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
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#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
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#define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
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#define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
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#define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_RSTMGR_STAT_MPUWD0RST_LSB 11
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#define ALT_RSTMGR_STAT_MPUWD0RST_MSB 11
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#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
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#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00000800
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#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xfffff7ff
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#define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
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#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00000800) >> 11)
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#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 11) & 0x00000800)
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#define ALT_RSTMGR_STAT_MPUWD1RST_LSB 12
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#define ALT_RSTMGR_STAT_MPUWD1RST_MSB 12
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#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
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#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00001000
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#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffefff
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#define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
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#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00001000) >> 12)
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#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 12) & 0x00001000)
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#define ALT_RSTMGR_STAT_L4WD0RST_LSB 13
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#define ALT_RSTMGR_STAT_L4WD0RST_MSB 13
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#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
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#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00002000
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#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffdfff
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#define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
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#define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00002000) >> 13)
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#define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 13) & 0x00002000)
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#define ALT_RSTMGR_STAT_L4WD1RST_LSB 14
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#define ALT_RSTMGR_STAT_L4WD1RST_MSB 14
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#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
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#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00004000
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#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffffbfff
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#define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
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#define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00004000) >> 14)
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#define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 14) & 0x00004000)
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#define ALT_RSTMGR_STAT_FPGADBGRST_LSB 16
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#define ALT_RSTMGR_STAT_FPGADBGRST_MSB 16
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#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
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#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00010000
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#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffeffff
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#define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
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#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_RSTMGR_STAT_CDBGREQRST_LSB 17
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#define ALT_RSTMGR_STAT_CDBGREQRST_MSB 17
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#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
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#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00020000
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#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfffdffff
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#define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
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#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00020000) >> 17)
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#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 17) & 0x00020000)
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#ifndef __ASSEMBLY__
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struct
ALT_RSTMGR_STAT_s
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{
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uint32_t
porhpsvoltrst
: 1;
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uint32_t
porfpgavoltrst
: 1;
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uint32_t
nporpinrst
: 1;
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uint32_t
fpgacoldrst
: 1;
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uint32_t
configiocoldrst
: 1;
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uint32_t
swcoldrst
: 1;
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uint32_t : 2;
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uint32_t
nrstpinrst
: 1;
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uint32_t
fpgawarmrst
: 1;
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uint32_t
swwarmrst
: 1;
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uint32_t
mpuwd0rst
: 1;
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uint32_t
mpuwd1rst
: 1;
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uint32_t
l4wd0rst
: 1;
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uint32_t
l4wd1rst
: 1;
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uint32_t : 1;
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uint32_t
fpgadbgrst
: 1;
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uint32_t
cdbgreqrst
: 1;
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uint32_t : 14;
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};
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typedef
volatile
struct
ALT_RSTMGR_STAT_s
ALT_RSTMGR_STAT_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_RSTMGR_STAT_RESET 0x00000000
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#define ALT_RSTMGR_STAT_OFST 0x0
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_LSB 0
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_MSB 0
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET_MSK 0x00000001
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_CLR_MSK 0xfffffffe
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_LSB 1
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_MSB 1
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET_MSK 0x00000002
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_CLR_MSK 0xfffffffd
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_LSB 2
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_MSB 2
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET_MSK 0x00000004
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_CLR_MSK 0xfffffffb
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_LSB 3
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_MSB 3
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET_MSK 0x00000008
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_CLR_MSK 0xfffffff7
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_LSB 4
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_MSB 4
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET_MSK 0x00000010
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_CLR_MSK 0xffffffef
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_LSB 5
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_MSB 5
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET_MSK 0x00000020
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_CLR_MSK 0xffffffdf
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_LSB 6
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_MSB 6
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET_MSK 0x00000040
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_CLR_MSK 0xffffffbf
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_LSB 7
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_MSB 7
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET_MSK 0x00000080
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_CLR_MSK 0xffffff7f
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_LSB 8
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_MSB 8
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET_MSK 0x00000100
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_CLR_MSK 0xfffffeff
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_LSB 9
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_MSB 9
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET_MSK 0x00000200
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_CLR_MSK 0xfffffdff
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_GET(value) (((value) & 0x00000200) >> 9)
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#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET(value) (((value) << 9) & 0x00000200)
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_LSB 10
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_MSB 10
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_WIDTH 1
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET_MSK 0x00000400
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_CLR_MSK 0xfffffbff
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_RESET 0x0
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_GET(value) (((value) & 0x00000400) >> 10)
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#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_LSB 11
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#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_MSB 11
843
844
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_WIDTH 1
845
846
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET_MSK 0x00000800
847
848
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_CLR_MSK 0xfffff7ff
849
850
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_RESET 0x0
851
852
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_GET(value) (((value) & 0x00000800) >> 11)
853
854
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET(value) (((value) << 11) & 0x00000800)
855
865
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_LSB 12
866
867
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_MSB 12
868
869
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_WIDTH 1
870
871
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET_MSK 0x00001000
872
873
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_CLR_MSK 0xffffefff
874
875
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_RESET 0x0
876
877
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_GET(value) (((value) & 0x00001000) >> 12)
878
879
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET(value) (((value) << 12) & 0x00001000)
880
890
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_LSB 13
891
892
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_MSB 13
893
894
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_WIDTH 1
895
896
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET_MSK 0x00002000
897
898
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_CLR_MSK 0xffffdfff
899
900
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_RESET 0x0
901
902
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_GET(value) (((value) & 0x00002000) >> 13)
903
904
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET(value) (((value) << 13) & 0x00002000)
905
915
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_LSB 14
916
917
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_MSB 14
918
919
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_WIDTH 1
920
921
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET_MSK 0x00004000
922
923
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_CLR_MSK 0xffffbfff
924
925
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_RESET 0x0
926
927
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_GET(value) (((value) & 0x00004000) >> 14)
928
929
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET(value) (((value) << 14) & 0x00004000)
930
940
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_LSB 15
941
942
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_MSB 15
943
944
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_WIDTH 1
945
946
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET_MSK 0x00008000
947
948
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_CLR_MSK 0xffff7fff
949
950
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_RESET 0x0
951
952
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_GET(value) (((value) & 0x00008000) >> 15)
953
954
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET(value) (((value) << 15) & 0x00008000)
955
966
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_LSB 16
967
968
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_MSB 16
969
970
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_WIDTH 1
971
972
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET_MSK 0x00010000
973
974
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_CLR_MSK 0xfffeffff
975
976
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_RESET 0x0
977
978
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_GET(value) (((value) & 0x00010000) >> 16)
979
980
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET(value) (((value) << 16) & 0x00010000)
981
991
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_LSB 17
992
993
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_MSB 17
994
995
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_WIDTH 1
996
997
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET_MSK 0x00020000
998
999
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_CLR_MSK 0xfffdffff
1000
1001
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_RESET 0x0
1002
1003
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_GET(value) (((value) & 0x00020000) >> 17)
1004
1005
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET(value) (((value) << 17) & 0x00020000)
1006
1007
#ifndef __ASSEMBLY__
1008
1018
struct
ALT_RSTMGR_RAMSTAT_s
1019
{
1020
uint32_t
onchipramclr
: 1;
1021
uint32_t
otg0ramclr
: 1;
1022
uint32_t
otg1ramclr
: 1;
1023
uint32_t
sdmmcramclr
: 1;
1024
uint32_t
dmaramclr
: 1;
1025
uint32_t
nandwramclr
: 1;
1026
uint32_t
nandrramclr
: 1;
1027
uint32_t
nanderamclr
: 1;
1028
uint32_t
emac0rxramclr
: 1;
1029
uint32_t
emac0txramclr
: 1;
1030
uint32_t
emac1rxramclr
: 1;
1031
uint32_t
emac1txramclr
: 1;
1032
uint32_t
emac2txramclr
: 1;
1033
uint32_t
emac2rxramclr
: 1;
1034
uint32_t
qspiramclr
: 1;
1035
uint32_t
mwpramclr
: 1;
1036
uint32_t
mpul1ramclr
: 1;
1037
uint32_t
mpul1timeout
: 1;
1038
uint32_t : 14;
1039
};
1040
1042
typedef
volatile
struct
ALT_RSTMGR_RAMSTAT_s
ALT_RSTMGR_RAMSTAT_t
;
1043
#endif
/* __ASSEMBLY__ */
1044
1046
#define ALT_RSTMGR_RAMSTAT_RESET 0x00000000
1047
1048
#define ALT_RSTMGR_RAMSTAT_OFST 0x4
1049
1094
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_LSB 0
1095
1096
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_MSB 0
1097
1098
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_WIDTH 1
1099
1100
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET_MSK 0x00000001
1101
1102
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_CLR_MSK 0xfffffffe
1103
1104
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_RESET 0x0
1105
1106
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_GET(value) (((value) & 0x00000001) >> 0)
1107
1108
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET(value) (((value) << 0) & 0x00000001)
1109
1121
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_LSB 1
1122
1123
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_MSB 1
1124
1125
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_WIDTH 1
1126
1127
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET_MSK 0x00000002
1128
1129
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_CLR_MSK 0xfffffffd
1130
1131
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_RESET 0x0
1132
1133
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_GET(value) (((value) & 0x00000002) >> 1)
1134
1135
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET(value) (((value) << 1) & 0x00000002)
1136
1148
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_LSB 2
1149
1150
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_MSB 2
1151
1152
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_WIDTH 1
1153
1154
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET_MSK 0x00000004
1155
1156
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_CLR_MSK 0xfffffffb
1157
1158
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_RESET 0x0
1159
1160
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_GET(value) (((value) & 0x00000004) >> 2)
1161
1162
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET(value) (((value) << 2) & 0x00000004)
1163
1175
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_LSB 3
1176
1177
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_MSB 3
1178
1179
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_WIDTH 1
1180
1181
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET_MSK 0x00000008
1182
1183
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_CLR_MSK 0xfffffff7
1184
1185
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_RESET 0x0
1186
1187
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_GET(value) (((value) & 0x00000008) >> 3)
1188
1189
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET(value) (((value) << 3) & 0x00000008)
1190
1191
#ifndef __ASSEMBLY__
1192
1202
struct
ALT_RSTMGR_MISCSTAT_s
1203
{
1204
uint32_t
sdrselfreftimeout
: 1;
1205
uint32_t
fpgamgrhstimeout
: 1;
1206
uint32_t
fpgahstimeout
: 1;
1207
uint32_t
etrstalltimeout
: 1;
1208
uint32_t : 28;
1209
};
1210
1212
typedef
volatile
struct
ALT_RSTMGR_MISCSTAT_s
ALT_RSTMGR_MISCSTAT_t
;
1213
#endif
/* __ASSEMBLY__ */
1214
1216
#define ALT_RSTMGR_MISCSTAT_RESET 0x00000000
1217
1218
#define ALT_RSTMGR_MISCSTAT_OFST 0x8
1219
1245
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
1246
1247
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
1248
1249
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
1250
1251
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
1252
1253
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
1254
1255
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
1256
1257
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
1258
1259
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
1260
1271
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
1272
1273
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
1274
1275
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
1276
1277
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
1278
1279
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
1280
1281
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
1282
1283
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
1284
1285
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
1286
1287
#ifndef __ASSEMBLY__
1288
1298
struct
ALT_RSTMGR_CTL_s
1299
{
1300
uint32_t
swcoldrstreq
: 1;
1301
uint32_t
swwarmrstreq
: 1;
1302
uint32_t : 30;
1303
};
1304
1306
typedef
volatile
struct
ALT_RSTMGR_CTL_s
ALT_RSTMGR_CTL_t
;
1307
#endif
/* __ASSEMBLY__ */
1308
1310
#define ALT_RSTMGR_CTL_RESET 0x00100000
1311
1312
#define ALT_RSTMGR_CTL_OFST 0xc
1313
1344
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_LSB 0
1345
1346
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_MSB 0
1347
1348
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_WIDTH 1
1349
1350
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK 0x00000001
1351
1352
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_CLR_MSK 0xfffffffe
1353
1354
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_RESET 0x0
1355
1356
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_GET(value) (((value) & 0x00000001) >> 0)
1357
1358
#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET(value) (((value) << 0) & 0x00000001)
1359
1379
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_LSB 1
1380
1381
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_MSB 1
1382
1383
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_WIDTH 1
1384
1385
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK 0x00000002
1386
1387
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_CLR_MSK 0xfffffffd
1388
1389
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_RESET 0x0
1390
1391
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_GET(value) (((value) & 0x00000002) >> 1)
1392
1393
#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET(value) (((value) << 1) & 0x00000002)
1394
1411
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_LSB 2
1412
1413
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_MSB 2
1414
1415
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_WIDTH 1
1416
1417
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK 0x00000004
1418
1419
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_CLR_MSK 0xfffffffb
1420
1421
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_RESET 0x0
1422
1423
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_GET(value) (((value) & 0x00000004) >> 2)
1424
1425
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET(value) (((value) << 2) & 0x00000004)
1426
1441
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_LSB 3
1442
1443
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_MSB 3
1444
1445
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_WIDTH 1
1446
1447
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK 0x00000008
1448
1449
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_CLR_MSK 0xfffffff7
1450
1451
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_RESET 0x0
1452
1453
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_GET(value) (((value) & 0x00000008) >> 3)
1454
1455
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET(value) (((value) << 3) & 0x00000008)
1456
1457
#ifndef __ASSEMBLY__
1458
1468
struct
ALT_RSTMGR_HDSKEN_s
1469
{
1470
uint32_t
sdrselfrefen
: 1;
1471
uint32_t
fpgamgrhsen
: 1;
1472
uint32_t
fpgahsen
: 1;
1473
uint32_t
etrstallen
: 1;
1474
uint32_t : 28;
1475
};
1476
1478
typedef
volatile
struct
ALT_RSTMGR_HDSKEN_s
ALT_RSTMGR_HDSKEN_t
;
1479
#endif
/* __ASSEMBLY__ */
1480
1482
#define ALT_RSTMGR_HDSKEN_RESET 0x00100000
1483
1484
#define ALT_RSTMGR_HDSKEN_OFST 0x10
1485
1524
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0
1525
1526
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0
1527
1528
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1
1529
1530
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001
1531
1532
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe
1533
1534
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0
1535
1536
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0)
1537
1538
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001)
1539
1554
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_LSB 1
1555
1556
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_MSB 1
1557
1558
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_WIDTH 1
1559
1560
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET_MSK 0x00000002
1561
1562
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_CLR_MSK 0xfffffffd
1563
1564
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_RESET 0x0
1565
1566
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_GET(value) (((value) & 0x00000002) >> 1)
1567
1568
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET(value) (((value) << 1) & 0x00000002)
1569
1583
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2
1584
1585
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2
1586
1587
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1
1588
1589
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004
1590
1591
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb
1592
1593
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0
1594
1595
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2)
1596
1597
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004)
1598
1613
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3
1614
1615
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3
1616
1617
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1
1618
1619
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008
1620
1621
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7
1622
1623
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0
1624
1625
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3)
1626
1627
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008)
1628
1629
#ifndef __ASSEMBLY__
1630
1640
struct
ALT_RSTMGR_HDSKREQ_s
1641
{
1642
uint32_t
sdrselfrefreq
: 1;
1643
uint32_t
fpgamgrhsreq
: 1;
1644
uint32_t
fpgahsreq
: 1;
1645
uint32_t
etrstallreq
: 1;
1646
uint32_t : 28;
1647
};
1648
1650
typedef
volatile
struct
ALT_RSTMGR_HDSKREQ_s
ALT_RSTMGR_HDSKREQ_t
;
1651
#endif
/* __ASSEMBLY__ */
1652
1654
#define ALT_RSTMGR_HDSKREQ_RESET 0x00100000
1655
1656
#define ALT_RSTMGR_HDSKREQ_OFST 0x14
1657
1694
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB 0
1695
1696
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB 0
1697
1698
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH 1
1699
1700
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK 0x00000001
1701
1702
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK 0xfffffffe
1703
1704
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET 0x0
1705
1706
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value) (((value) & 0x00000001) >> 0)
1707
1708
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value) (((value) << 0) & 0x00000001)
1709
1720
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_LSB 1
1721
1722
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_MSB 1
1723
1724
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_WIDTH 1
1725
1726
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET_MSK 0x00000002
1727
1728
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_CLR_MSK 0xfffffffd
1729
1730
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_RESET 0x0
1731
1732
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_GET(value) (((value) & 0x00000002) >> 1)
1733
1734
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET(value) (((value) << 1) & 0x00000002)
1735
1746
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB 2
1747
1748
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB 2
1749
1750
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH 1
1751
1752
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK 0x00000004
1753
1754
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK 0xfffffffb
1755
1756
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET 0x0
1757
1758
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value) (((value) & 0x00000004) >> 2)
1759
1760
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value) (((value) << 2) & 0x00000004)
1761
1772
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB 3
1773
1774
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB 3
1775
1776
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH 1
1777
1778
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK 0x00000008
1779
1780
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK 0xfffffff7
1781
1782
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET 0x0
1783
1784
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value) (((value) & 0x00000008) >> 3)
1785
1786
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value) (((value) << 3) & 0x00000008)
1787
1801
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_LSB 8
1802
1803
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_MSB 8
1804
1805
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_WIDTH 1
1806
1807
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET_MSK 0x00000100
1808
1809
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_CLR_MSK 0xfffffeff
1810
1811
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_RESET 0x0
1812
1813
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_GET(value) (((value) & 0x00000100) >> 8)
1814
1815
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET(value) (((value) << 8) & 0x00000100)
1816
1817
#ifndef __ASSEMBLY__
1818
1828
struct
ALT_RSTMGR_HDSKACK_s
1829
{
1830
const
uint32_t
sdrselfreqack
: 1;
1831
const
uint32_t
fpgamgrhsack
: 1;
1832
const
uint32_t
fpgahsack
: 1;
1833
const
uint32_t
etrstallack
: 1;
1834
uint32_t : 4;
1835
uint32_t
etrstallwarmrst
: 1;
1836
uint32_t : 23;
1837
};
1838
1840
typedef
volatile
struct
ALT_RSTMGR_HDSKACK_s
ALT_RSTMGR_HDSKACK_t
;
1841
#endif
/* __ASSEMBLY__ */
1842
1844
#define ALT_RSTMGR_HDSKACK_RESET 0x00100000
1845
1846
#define ALT_RSTMGR_HDSKACK_OFST 0x18
1847
1876
#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 0
1877
1878
#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 19
1879
1880
#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1881
1882
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x000fffff
1883
1884
#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xfff00000
1885
1886
#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1887
1888
#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x000fffff) >> 0)
1889
1890
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 0) & 0x000fffff)
1891
1903
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 24
1904
1905
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 31
1906
1907
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1908
1909
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0xff000000
1910
1911
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0x00ffffff
1912
1913
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1914
1915
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0xff000000) >> 24)
1916
1917
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 24) & 0xff000000)
1918
1919
#ifndef __ASSEMBLY__
1920
1930
struct
ALT_RSTMGR_COUNTS_s
1931
{
1932
uint32_t
nrstcnt
: 20;
1933
uint32_t : 4;
1934
uint32_t
warmrstcycles
: 8;
1935
};
1936
1938
typedef
volatile
struct
ALT_RSTMGR_COUNTS_s
ALT_RSTMGR_COUNTS_t
;
1939
#endif
/* __ASSEMBLY__ */
1940
1942
#define ALT_RSTMGR_COUNTS_RESET 0x80000800
1943
1944
#define ALT_RSTMGR_COUNTS_OFST 0x1c
1945
1994
#define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1995
1996
#define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1997
1998
#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1999
2000
#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
2001
2002
#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
2003
2004
#define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
2005
2006
#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
2007
2008
#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
2009
2026
#define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
2027
2028
#define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
2029
2030
#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
2031
2032
#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
2033
2034
#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
2035
2036
#define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
2037
2038
#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
2039
2040
#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
2041
2051
#define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
2052
2053
#define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
2054
2055
#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
2056
2057
#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
2058
2059
#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
2060
2061
#define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
2062
2063
#define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
2064
2065
#define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
2066
2078
#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
2079
2080
#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
2081
2082
#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
2083
2084
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
2085
2086
#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
2087
2088
#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
2089
2090
#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
2091
2092
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
2093
2094
#ifndef __ASSEMBLY__
2095
2105
struct
ALT_RSTMGR_MPUMODRST_s
2106
{
2107
uint32_t
cpu0
: 1;
2108
uint32_t
cpu1
: 1;
2109
uint32_t
wds
: 1;
2110
uint32_t
scuper
: 1;
2111
uint32_t : 28;
2112
};
2113
2115
typedef
volatile
struct
ALT_RSTMGR_MPUMODRST_s
ALT_RSTMGR_MPUMODRST_t
;
2116
#endif
/* __ASSEMBLY__ */
2117
2119
#define ALT_RSTMGR_MPUMODRST_RESET 0x00000002
2120
2121
#define ALT_RSTMGR_MPUMODRST_OFST 0x20
2122
2194
#define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0
2195
2196
#define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0
2197
2198
#define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1
2199
2200
#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001
2201
2202
#define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe
2203
2204
#define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1
2205
2206
#define ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
2207
2208
#define ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
2209
2219
#define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1
2220
2221
#define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1
2222
2223
#define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1
2224
2225
#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002
2226
2227
#define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd
2228
2229
#define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1
2230
2231
#define ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
2232
2233
#define ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
2234
2244
#define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2
2245
2246
#define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2
2247
2248
#define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1
2249
2250
#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004
2251
2252
#define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb
2253
2254
#define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1
2255
2256
#define ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
2257
2258
#define ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004)
2259
2269
#define ALT_RSTMGR_PER0MODRST_USB0_LSB 3
2270
2271
#define ALT_RSTMGR_PER0MODRST_USB0_MSB 3
2272
2273
#define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1
2274
2275
#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008
2276
2277
#define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7
2278
2279
#define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1
2280
2281
#define ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3)
2282
2283
#define ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008)
2284
2294
#define ALT_RSTMGR_PER0MODRST_USB1_LSB 4
2295
2296
#define ALT_RSTMGR_PER0MODRST_USB1_MSB 4
2297
2298
#define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1
2299
2300
#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010
2301
2302
#define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef
2303
2304
#define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1
2305
2306
#define ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4)
2307
2308
#define ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010)
2309
2319
#define ALT_RSTMGR_PER0MODRST_NAND_LSB 5
2320
2321
#define ALT_RSTMGR_PER0MODRST_NAND_MSB 5
2322
2323
#define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1
2324
2325
#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020
2326
2327
#define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf
2328
2329
#define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1
2330
2331
#define ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5)
2332
2333
#define ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020)
2334
2344
#define ALT_RSTMGR_PER0MODRST_QSPI_LSB 6
2345
2346
#define ALT_RSTMGR_PER0MODRST_QSPI_MSB 6
2347
2348
#define ALT_RSTMGR_PER0MODRST_QSPI_WIDTH 1
2349
2350
#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040
2351
2352
#define ALT_RSTMGR_PER0MODRST_QSPI_CLR_MSK 0xffffffbf
2353
2354
#define ALT_RSTMGR_PER0MODRST_QSPI_RESET 0x1
2355
2356
#define ALT_RSTMGR_PER0MODRST_QSPI_GET(value) (((value) & 0x00000040) >> 6)
2357
2358
#define ALT_RSTMGR_PER0MODRST_QSPI_SET(value) (((value) << 6) & 0x00000040)
2359
2369
#define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7
2370
2371
#define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7
2372
2373
#define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1
2374
2375
#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080
2376
2377
#define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f
2378
2379
#define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1
2380
2381
#define ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
2382
2383
#define ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080)
2384
2394
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8
2395
2396
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8
2397
2398
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1
2399
2400
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100
2401
2402
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff
2403
2404
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1
2405
2406
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
2407
2408
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
2409
2419
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9
2420
2421
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9
2422
2423
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1
2424
2425
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200
2426
2427
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff
2428
2429
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1
2430
2431
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
2432
2433
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
2434
2444
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10
2445
2446
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10
2447
2448
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1
2449
2450
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400
2451
2452
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff
2453
2454
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1
2455
2456
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
2457
2458
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
2459
2469
#define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11
2470
2471
#define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11
2472
2473
#define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1
2474
2475
#define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800
2476
2477
#define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff
2478
2479
#define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1
2480
2481
#define ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
2482
2483
#define ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
2484
2494
#define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12
2495
2496
#define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12
2497
2498
#define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1
2499
2500
#define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000
2501
2502
#define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff
2503
2504
#define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1
2505
2506
#define ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
2507
2508
#define ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
2509
2519
#define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13
2520
2521
#define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13
2522
2523
#define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1
2524
2525
#define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000
2526
2527
#define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff
2528
2529
#define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1
2530
2531
#define ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
2532
2533
#define ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
2534
2544
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_LSB 14
2545
2546
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_MSB 14
2547
2548
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_WIDTH 1
2549
2550
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET_MSK 0x00004000
2551
2552
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_CLR_MSK 0xffffbfff
2553
2554
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_RESET 0x1
2555
2556
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
2557
2558
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
2559
2569
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15
2570
2571
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15
2572
2573
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1
2574
2575
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000
2576
2577
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff
2578
2579
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1
2580
2581
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
2582
2583
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
2584
2594
#define ALT_RSTMGR_PER0MODRST_DMA_LSB 16
2595
2596
#define ALT_RSTMGR_PER0MODRST_DMA_MSB 16
2597
2598
#define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1
2599
2600
#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000
2601
2602
#define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff
2603
2604
#define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1
2605
2606
#define ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16)
2607
2608
#define ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000)
2609
2619
#define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17
2620
2621
#define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17
2622
2623
#define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1
2624
2625
#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000
2626
2627
#define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff
2628
2629
#define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1
2630
2631
#define ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
2632
2633
#define ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000)
2634
2644
#define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18
2645
2646
#define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18
2647
2648
#define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1
2649
2650
#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000
2651
2652
#define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff
2653
2654
#define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1
2655
2656
#define ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
2657
2658
#define ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000)
2659
2669
#define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19
2670
2671
#define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19
2672
2673
#define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1
2674
2675
#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000
2676
2677
#define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff
2678
2679
#define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1
2680
2681
#define ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
2682
2683
#define ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000)
2684
2694
#define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20
2695
2696
#define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20
2697
2698
#define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1
2699
2700
#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000
2701
2702
#define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff
2703
2704
#define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1
2705
2706
#define ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
2707
2708
#define ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000)
2709
2719
#define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21
2720
2721
#define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21
2722
2723
#define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1
2724
2725
#define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000
2726
2727
#define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff
2728
2729
#define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1
2730
2731
#define ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
2732
2733
#define ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
2734
2744
#define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22
2745
2746
#define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22
2747
2748
#define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1
2749
2750
#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000
2751
2752
#define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff
2753
2754
#define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1
2755
2756
#define ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
2757
2758
#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
2759
2770
#define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24
2771
2772
#define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24
2773
2774
#define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1
2775
2776
#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000
2777
2778
#define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff
2779
2780
#define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1
2781
2782
#define ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
2783
2784
#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
2785
2796
#define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25
2797
2798
#define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25
2799
2800
#define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1
2801
2802
#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000
2803
2804
#define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff
2805
2806
#define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1
2807
2808
#define ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
2809
2810
#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
2811
2822
#define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26
2823
2824
#define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26
2825
2826
#define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1
2827
2828
#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000
2829
2830
#define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff
2831
2832
#define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1
2833
2834
#define ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
2835
2836
#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
2837
2848
#define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27
2849
2850
#define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27
2851
2852
#define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1
2853
2854
#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000
2855
2856
#define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff
2857
2858
#define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1
2859
2860
#define ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
2861
2862
#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
2863
2874
#define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28
2875
2876
#define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28
2877
2878
#define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1
2879
2880
#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000
2881
2882
#define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff
2883
2884
#define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1
2885
2886
#define ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
2887
2888
#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
2889
2900
#define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29
2901
2902
#define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29
2903
2904
#define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1
2905
2906
#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000
2907
2908
#define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff
2909
2910
#define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1
2911
2912
#define ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
2913
2914
#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
2915
2926
#define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30
2927
2928
#define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30
2929
2930
#define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1
2931
2932
#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000
2933
2934
#define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff
2935
2936
#define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1
2937
2938
#define ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
2939
2940
#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
2941
2952
#define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31
2953
2954
#define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31
2955
2956
#define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1
2957
2958
#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000
2959
2960
#define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff
2961
2962
#define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1
2963
2964
#define ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
2965
2966
#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
2967
2968
#ifndef __ASSEMBLY__
2969
2979
struct
ALT_RSTMGR_PER0MODRST_s
2980
{
2981
uint32_t
emac0
: 1;
2982
uint32_t
emac1
: 1;
2983
uint32_t
emac2
: 1;
2984
uint32_t
usb0
: 1;
2985
uint32_t
usb1
: 1;
2986
uint32_t
nand
: 1;
2987
uint32_t
qspi
: 1;
2988
uint32_t
sdmmc
: 1;
2989
uint32_t
emac0ocp
: 1;
2990
uint32_t
emac1ocp
: 1;
2991
uint32_t
emac2ocp
: 1;
2992
uint32_t
usb0ocp
: 1;
2993
uint32_t
usb1ocp
: 1;
2994
uint32_t
nandocp
: 1;
2995
uint32_t
qspiocp
: 1;
2996
uint32_t
sdmmcocp
: 1;
2997
uint32_t
dma
: 1;
2998
uint32_t
spim0
: 1;
2999
uint32_t
spim1
: 1;
3000
uint32_t
spis0
: 1;
3001
uint32_t
spis1
: 1;
3002
uint32_t
dmaocp
: 1;
3003
uint32_t
emacptp
: 1;
3004
uint32_t : 1;
3005
uint32_t
dmaif0
: 1;
3006
uint32_t
dmaif1
: 1;
3007
uint32_t
dmaif2
: 1;
3008
uint32_t
dmaif3
: 1;
3009
uint32_t
dmaif4
: 1;
3010
uint32_t
dmaif5
: 1;
3011
uint32_t
dmaif6
: 1;
3012
uint32_t
dmaif7
: 1;
3013
};
3014
3016
typedef
volatile
struct
ALT_RSTMGR_PER0MODRST_s
ALT_RSTMGR_PER0MODRST_t
;
3017
#endif
/* __ASSEMBLY__ */
3018
3020
#define ALT_RSTMGR_PER0MODRST_RESET 0xff7fffff
3021
3022
#define ALT_RSTMGR_PER0MODRST_OFST 0x24
3023
3081
#define ALT_RSTMGR_PER1MODRST_WD0_LSB 0
3082
3083
#define ALT_RSTMGR_PER1MODRST_WD0_MSB 0
3084
3085
#define ALT_RSTMGR_PER1MODRST_WD0_WIDTH 1
3086
3087
#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK 0x00000001
3088
3089
#define ALT_RSTMGR_PER1MODRST_WD0_CLR_MSK 0xfffffffe
3090
3091
#define ALT_RSTMGR_PER1MODRST_WD0_RESET 0x1
3092
3093
#define ALT_RSTMGR_PER1MODRST_WD0_GET(value) (((value) & 0x00000001) >> 0)
3094
3095
#define ALT_RSTMGR_PER1MODRST_WD0_SET(value) (((value) << 0) & 0x00000001)
3096
3106
#define ALT_RSTMGR_PER1MODRST_WD1_LSB 1
3107
3108
#define ALT_RSTMGR_PER1MODRST_WD1_MSB 1
3109
3110
#define ALT_RSTMGR_PER1MODRST_WD1_WIDTH 1
3111
3112
#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK 0x00000002
3113
3114
#define ALT_RSTMGR_PER1MODRST_WD1_CLR_MSK 0xfffffffd
3115
3116
#define ALT_RSTMGR_PER1MODRST_WD1_RESET 0x1
3117
3118
#define ALT_RSTMGR_PER1MODRST_WD1_GET(value) (((value) & 0x00000002) >> 1)
3119
3120
#define ALT_RSTMGR_PER1MODRST_WD1_SET(value) (((value) << 1) & 0x00000002)
3121
3131
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_LSB 2
3132
3133
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_MSB 2
3134
3135
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_WIDTH 1
3136
3137
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK 0x00000004
3138
3139
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_CLR_MSK 0xfffffffb
3140
3141
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_RESET 0x1
3142
3143
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
3144
3145
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
3146
3156
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_LSB 3
3157
3158
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_MSB 3
3159
3160
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_WIDTH 1
3161
3162
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK 0x00000008
3163
3164
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_CLR_MSK 0xfffffff7
3165
3166
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_RESET 0x1
3167
3168
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
3169
3170
#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
3171
3181
#define ALT_RSTMGR_PER1MODRST_SPTMR0_LSB 4
3182
3183
#define ALT_RSTMGR_PER1MODRST_SPTMR0_MSB 4
3184
3185
#define ALT_RSTMGR_PER1MODRST_SPTMR0_WIDTH 1
3186
3187
#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK 0x00000010
3188
3189
#define ALT_RSTMGR_PER1MODRST_SPTMR0_CLR_MSK 0xffffffef
3190
3191
#define ALT_RSTMGR_PER1MODRST_SPTMR0_RESET 0x1
3192
3193
#define ALT_RSTMGR_PER1MODRST_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
3194
3195
#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
3196
3206
#define ALT_RSTMGR_PER1MODRST_SPTMR1_LSB 5
3207
3208
#define ALT_RSTMGR_PER1MODRST_SPTMR1_MSB 5
3209
3210
#define ALT_RSTMGR_PER1MODRST_SPTMR1_WIDTH 1
3211
3212
#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK 0x00000020
3213
3214
#define ALT_RSTMGR_PER1MODRST_SPTMR1_CLR_MSK 0xffffffdf
3215
3216
#define ALT_RSTMGR_PER1MODRST_SPTMR1_RESET 0x1
3217
3218
#define ALT_RSTMGR_PER1MODRST_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
3219
3220
#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
3221
3231
#define ALT_RSTMGR_PER1MODRST_I2C0_LSB 8
3232
3233
#define ALT_RSTMGR_PER1MODRST_I2C0_MSB 8
3234
3235
#define ALT_RSTMGR_PER1MODRST_I2C0_WIDTH 1
3236
3237
#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK 0x00000100
3238
3239
#define ALT_RSTMGR_PER1MODRST_I2C0_CLR_MSK 0xfffffeff
3240
3241
#define ALT_RSTMGR_PER1MODRST_I2C0_RESET 0x1
3242
3243
#define ALT_RSTMGR_PER1MODRST_I2C0_GET(value) (((value) & 0x00000100) >> 8)
3244
3245
#define ALT_RSTMGR_PER1MODRST_I2C0_SET(value) (((value) << 8) & 0x00000100)
3246
3256
#define ALT_RSTMGR_PER1MODRST_I2C1_LSB 9
3257
3258
#define ALT_RSTMGR_PER1MODRST_I2C1_MSB 9
3259
3260
#define ALT_RSTMGR_PER1MODRST_I2C1_WIDTH 1
3261
3262
#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK 0x00000200
3263
3264
#define ALT_RSTMGR_PER1MODRST_I2C1_CLR_MSK 0xfffffdff
3265
3266
#define ALT_RSTMGR_PER1MODRST_I2C1_RESET 0x1
3267
3268
#define ALT_RSTMGR_PER1MODRST_I2C1_GET(value) (((value) & 0x00000200) >> 9)
3269
3270
#define ALT_RSTMGR_PER1MODRST_I2C1_SET(value) (((value) << 9) & 0x00000200)
3271
3281
#define ALT_RSTMGR_PER1MODRST_I2C2_LSB 10
3282
3283
#define ALT_RSTMGR_PER1MODRST_I2C2_MSB 10
3284
3285
#define ALT_RSTMGR_PER1MODRST_I2C2_WIDTH 1
3286
3287
#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK 0x00000400
3288
3289
#define ALT_RSTMGR_PER1MODRST_I2C2_CLR_MSK 0xfffffbff
3290
3291
#define ALT_RSTMGR_PER1MODRST_I2C2_RESET 0x1
3292
3293
#define ALT_RSTMGR_PER1MODRST_I2C2_GET(value) (((value) & 0x00000400) >> 10)
3294
3295
#define ALT_RSTMGR_PER1MODRST_I2C2_SET(value) (((value) << 10) & 0x00000400)
3296
3306
#define ALT_RSTMGR_PER1MODRST_I2C3_LSB 11
3307
3308
#define ALT_RSTMGR_PER1MODRST_I2C3_MSB 11
3309
3310
#define ALT_RSTMGR_PER1MODRST_I2C3_WIDTH 1
3311
3312
#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK 0x00000800
3313
3314
#define ALT_RSTMGR_PER1MODRST_I2C3_CLR_MSK 0xfffff7ff
3315
3316
#define ALT_RSTMGR_PER1MODRST_I2C3_RESET 0x1
3317
3318
#define ALT_RSTMGR_PER1MODRST_I2C3_GET(value) (((value) & 0x00000800) >> 11)
3319
3320
#define ALT_RSTMGR_PER1MODRST_I2C3_SET(value) (((value) << 11) & 0x00000800)
3321
3331
#define ALT_RSTMGR_PER1MODRST_I2C4_LSB 12
3332
3333
#define ALT_RSTMGR_PER1MODRST_I2C4_MSB 12
3334
3335
#define ALT_RSTMGR_PER1MODRST_I2C4_WIDTH 1
3336
3337
#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK 0x00001000
3338
3339
#define ALT_RSTMGR_PER1MODRST_I2C4_CLR_MSK 0xffffefff
3340
3341
#define ALT_RSTMGR_PER1MODRST_I2C4_RESET 0x1
3342
3343
#define ALT_RSTMGR_PER1MODRST_I2C4_GET(value) (((value) & 0x00001000) >> 12)
3344
3345
#define ALT_RSTMGR_PER1MODRST_I2C4_SET(value) (((value) << 12) & 0x00001000)
3346
3356
#define ALT_RSTMGR_PER1MODRST_UART0_LSB 16
3357
3358
#define ALT_RSTMGR_PER1MODRST_UART0_MSB 16
3359
3360
#define ALT_RSTMGR_PER1MODRST_UART0_WIDTH 1
3361
3362
#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK 0x00010000
3363
3364
#define ALT_RSTMGR_PER1MODRST_UART0_CLR_MSK 0xfffeffff
3365
3366
#define ALT_RSTMGR_PER1MODRST_UART0_RESET 0x1
3367
3368
#define ALT_RSTMGR_PER1MODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
3369
3370
#define ALT_RSTMGR_PER1MODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
3371
3381
#define ALT_RSTMGR_PER1MODRST_UART1_LSB 17
3382
3383
#define ALT_RSTMGR_PER1MODRST_UART1_MSB 17
3384
3385
#define ALT_RSTMGR_PER1MODRST_UART1_WIDTH 1
3386
3387
#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK 0x00020000
3388
3389
#define ALT_RSTMGR_PER1MODRST_UART1_CLR_MSK 0xfffdffff
3390
3391
#define ALT_RSTMGR_PER1MODRST_UART1_RESET 0x1
3392
3393
#define ALT_RSTMGR_PER1MODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
3394
3395
#define ALT_RSTMGR_PER1MODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
3396
3406
#define ALT_RSTMGR_PER1MODRST_GPIO0_LSB 24
3407
3408
#define ALT_RSTMGR_PER1MODRST_GPIO0_MSB 24
3409
3410
#define ALT_RSTMGR_PER1MODRST_GPIO0_WIDTH 1
3411
3412
#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK 0x01000000
3413
3414
#define ALT_RSTMGR_PER1MODRST_GPIO0_CLR_MSK 0xfeffffff
3415
3416
#define ALT_RSTMGR_PER1MODRST_GPIO0_RESET 0x1
3417
3418
#define ALT_RSTMGR_PER1MODRST_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
3419
3420
#define ALT_RSTMGR_PER1MODRST_GPIO0_SET(value) (((value) << 24) & 0x01000000)
3421
3431
#define ALT_RSTMGR_PER1MODRST_GPIO1_LSB 25
3432
3433
#define ALT_RSTMGR_PER1MODRST_GPIO1_MSB 25
3434
3435
#define ALT_RSTMGR_PER1MODRST_GPIO1_WIDTH 1
3436
3437
#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK 0x02000000
3438
3439
#define ALT_RSTMGR_PER1MODRST_GPIO1_CLR_MSK 0xfdffffff
3440
3441
#define ALT_RSTMGR_PER1MODRST_GPIO1_RESET 0x1
3442
3443
#define ALT_RSTMGR_PER1MODRST_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
3444
3445
#define ALT_RSTMGR_PER1MODRST_GPIO1_SET(value) (((value) << 25) & 0x02000000)
3446
3456
#define ALT_RSTMGR_PER1MODRST_GPIO2_LSB 26
3457
3458
#define ALT_RSTMGR_PER1MODRST_GPIO2_MSB 26
3459
3460
#define ALT_RSTMGR_PER1MODRST_GPIO2_WIDTH 1
3461
3462
#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK 0x04000000
3463
3464
#define ALT_RSTMGR_PER1MODRST_GPIO2_CLR_MSK 0xfbffffff
3465
3466
#define ALT_RSTMGR_PER1MODRST_GPIO2_RESET 0x1
3467
3468
#define ALT_RSTMGR_PER1MODRST_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
3469
3470
#define ALT_RSTMGR_PER1MODRST_GPIO2_SET(value) (((value) << 26) & 0x04000000)
3471
3472
#ifndef __ASSEMBLY__
3473
3483
struct
ALT_RSTMGR_PER1MODRST_s
3484
{
3485
uint32_t
watchdog0
: 1;
3486
uint32_t
watchdog1
: 1;
3487
uint32_t
l4systimer0
: 1;
3488
uint32_t
l4systimer1
: 1;
3489
uint32_t
sptimer0
: 1;
3490
uint32_t
sptimer1
: 1;
3491
uint32_t : 2;
3492
uint32_t
i2c0
: 1;
3493
uint32_t
i2c1
: 1;
3494
uint32_t
i2c2
: 1;
3495
uint32_t
i2c3
: 1;
3496
uint32_t
i2c4
: 1;
3497
uint32_t : 3;
3498
uint32_t
uart0
: 1;
3499
uint32_t
uart1
: 1;
3500
uint32_t : 6;
3501
uint32_t
gpio0
: 1;
3502
uint32_t
gpio1
: 1;
3503
uint32_t
gpio2
: 1;
3504
uint32_t : 5;
3505
};
3506
3508
typedef
volatile
struct
ALT_RSTMGR_PER1MODRST_s
ALT_RSTMGR_PER1MODRST_t
;
3509
#endif
/* __ASSEMBLY__ */
3510
3512
#define ALT_RSTMGR_PER1MODRST_RESET 0x07031f3f
3513
3514
#define ALT_RSTMGR_PER1MODRST_OFST 0x28
3515
3561
#define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
3562
3563
#define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
3564
3565
#define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
3566
3567
#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
3568
3569
#define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
3570
3571
#define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
3572
3573
#define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
3574
3575
#define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
3576
3586
#define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
3587
3588
#define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
3589
3590
#define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
3591
3592
#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
3593
3594
#define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
3595
3596
#define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
3597
3598
#define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
3599
3600
#define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
3601
3611
#define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
3612
3613
#define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
3614
3615
#define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
3616
3617
#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
3618
3619
#define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
3620
3621
#define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
3622
3623
#define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
3624
3625
#define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
3626
3636
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_LSB 3
3637
3638
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_MSB 3
3639
3640
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_WIDTH 1
3641
3642
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK 0x00000008
3643
3644
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_CLR_MSK 0xfffffff7
3645
3646
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_RESET 0x1
3647
3648
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
3649
3650
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
3651
3661
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_LSB 4
3662
3663
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_MSB 4
3664
3665
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_WIDTH 1
3666
3667
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK 0x00000010
3668
3669
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_CLR_MSK 0xffffffef
3670
3671
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_RESET 0x1
3672
3673
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
3674
3675
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
3676
3686
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_LSB 5
3687
3688
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_MSB 5
3689
3690
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_WIDTH 1
3691
3692
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK 0x00000020
3693
3694
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_CLR_MSK 0xffffffdf
3695
3696
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_RESET 0x1
3697
3698
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
3699
3700
#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
3701
3711
#define ALT_RSTMGR_BRGMODRST_DDRSCH_LSB 6
3712
3713
#define ALT_RSTMGR_BRGMODRST_DDRSCH_MSB 6
3714
3715
#define ALT_RSTMGR_BRGMODRST_DDRSCH_WIDTH 1
3716
3717
#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK 0x00000040
3718
3719
#define ALT_RSTMGR_BRGMODRST_DDRSCH_CLR_MSK 0xffffffbf
3720
3721
#define ALT_RSTMGR_BRGMODRST_DDRSCH_RESET 0x1
3722
3723
#define ALT_RSTMGR_BRGMODRST_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
3724
3725
#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
3726
3727
#ifndef __ASSEMBLY__
3728
3738
struct
ALT_RSTMGR_BRGMODRST_s
3739
{
3740
uint32_t
hps2fpga
: 1;
3741
uint32_t
lwhps2fpga
: 1;
3742
uint32_t
fpga2hps
: 1;
3743
uint32_t
f2ssdram0
: 1;
3744
uint32_t
f2ssdram1
: 1;
3745
uint32_t
f2ssdram2
: 1;
3746
uint32_t
ddrsch
: 1;
3747
uint32_t : 25;
3748
};
3749
3751
typedef
volatile
struct
ALT_RSTMGR_BRGMODRST_s
ALT_RSTMGR_BRGMODRST_t
;
3752
#endif
/* __ASSEMBLY__ */
3753
3755
#define ALT_RSTMGR_BRGMODRST_RESET 0x0000007f
3756
3757
#define ALT_RSTMGR_BRGMODRST_OFST 0x2c
3758
3799
#define ALT_RSTMGR_SYSMODRST_ROM_LSB 0
3800
3801
#define ALT_RSTMGR_SYSMODRST_ROM_MSB 0
3802
3803
#define ALT_RSTMGR_SYSMODRST_ROM_WIDTH 1
3804
3805
#define ALT_RSTMGR_SYSMODRST_ROM_SET_MSK 0x00000001
3806
3807
#define ALT_RSTMGR_SYSMODRST_ROM_CLR_MSK 0xfffffffe
3808
3809
#define ALT_RSTMGR_SYSMODRST_ROM_RESET 0x0
3810
3811
#define ALT_RSTMGR_SYSMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
3812
3813
#define ALT_RSTMGR_SYSMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
3814
3824
#define ALT_RSTMGR_SYSMODRST_OCRAM_LSB 1
3825
3826
#define ALT_RSTMGR_SYSMODRST_OCRAM_MSB 1
3827
3828
#define ALT_RSTMGR_SYSMODRST_OCRAM_WIDTH 1
3829
3830
#define ALT_RSTMGR_SYSMODRST_OCRAM_SET_MSK 0x00000002
3831
3832
#define ALT_RSTMGR_SYSMODRST_OCRAM_CLR_MSK 0xfffffffd
3833
3834
#define ALT_RSTMGR_SYSMODRST_OCRAM_RESET 0x0
3835
3836
#define ALT_RSTMGR_SYSMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
3837
3838
#define ALT_RSTMGR_SYSMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
3839
3849
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_LSB 3
3850
3851
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_MSB 3
3852
3853
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_WIDTH 1
3854
3855
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET_MSK 0x00000008
3856
3857
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_CLR_MSK 0xfffffff7
3858
3859
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_RESET 0x0
3860
3861
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
3862
3863
#define ALT_RSTMGR_SYSMODRST_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
3864
3875
#define ALT_RSTMGR_SYSMODRST_S2F_LSB 4
3876
3877
#define ALT_RSTMGR_SYSMODRST_S2F_MSB 4
3878
3879
#define ALT_RSTMGR_SYSMODRST_S2F_WIDTH 1
3880
3881
#define ALT_RSTMGR_SYSMODRST_S2F_SET_MSK 0x00000010
3882
3883
#define ALT_RSTMGR_SYSMODRST_S2F_CLR_MSK 0xffffffef
3884
3885
#define ALT_RSTMGR_SYSMODRST_S2F_RESET 0x0
3886
3887
#define ALT_RSTMGR_SYSMODRST_S2F_GET(value) (((value) & 0x00000010) >> 4)
3888
3889
#define ALT_RSTMGR_SYSMODRST_S2F_SET(value) (((value) << 4) & 0x00000010)
3890
3900
#define ALT_RSTMGR_SYSMODRST_SYSDBG_LSB 5
3901
3902
#define ALT_RSTMGR_SYSMODRST_SYSDBG_MSB 5
3903
3904
#define ALT_RSTMGR_SYSMODRST_SYSDBG_WIDTH 1
3905
3906
#define ALT_RSTMGR_SYSMODRST_SYSDBG_SET_MSK 0x00000020
3907
3908
#define ALT_RSTMGR_SYSMODRST_SYSDBG_CLR_MSK 0xffffffdf
3909
3910
#define ALT_RSTMGR_SYSMODRST_SYSDBG_RESET 0x0
3911
3912
#define ALT_RSTMGR_SYSMODRST_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
3913
3914
#define ALT_RSTMGR_SYSMODRST_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
3915
3925
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_LSB 6
3926
3927
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_MSB 6
3928
3929
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_WIDTH 1
3930
3931
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET_MSK 0x00000040
3932
3933
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_CLR_MSK 0xffffffbf
3934
3935
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_RESET 0x0
3936
3937
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
3938
3939
#define ALT_RSTMGR_SYSMODRST_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
3940
3941
#ifndef __ASSEMBLY__
3942
3952
struct
ALT_RSTMGR_SYSMODRST_s
3953
{
3954
uint32_t
rom
: 1;
3955
uint32_t
ocram
: 1;
3956
uint32_t : 1;
3957
uint32_t
fpgamgr
: 1;
3958
uint32_t
s2f
: 1;
3959
uint32_t
sysdbg
: 1;
3960
uint32_t
ocramocp
: 1;
3961
uint32_t : 25;
3962
};
3963
3965
typedef
volatile
struct
ALT_RSTMGR_SYSMODRST_s
ALT_RSTMGR_SYSMODRST_t
;
3966
#endif
/* __ASSEMBLY__ */
3967
3969
#define ALT_RSTMGR_SYSMODRST_RESET 0x00000000
3970
3971
#define ALT_RSTMGR_SYSMODRST_OFST 0x30
3972
4013
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_LSB 0
4014
4015
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_MSB 0
4016
4017
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_WIDTH 1
4018
4019
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET_MSK 0x00000001
4020
4021
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_CLR_MSK 0xfffffffe
4022
4023
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_RESET 0x0
4024
4025
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000001) >> 0)
4026
4027
#define ALT_RSTMGR_COLDMODRST_CLKMGRCOLD_SET(value) (((value) << 0) & 0x00000001)
4028
4039
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_LSB 3
4040
4041
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_MSB 3
4042
4043
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_WIDTH 1
4044
4045
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET_MSK 0x00000008
4046
4047
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_CLR_MSK 0xfffffff7
4048
4049
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_RESET 0x0
4050
4051
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_GET(value) (((value) & 0x00000008) >> 3)
4052
4053
#define ALT_RSTMGR_COLDMODRST_S2FCOLD_SET(value) (((value) << 3) & 0x00000008)
4054
4064
#define ALT_RSTMGR_COLDMODRST_TSCOLD_LSB 4
4065
4066
#define ALT_RSTMGR_COLDMODRST_TSCOLD_MSB 4
4067
4068
#define ALT_RSTMGR_COLDMODRST_TSCOLD_WIDTH 1
4069
4070
#define ALT_RSTMGR_COLDMODRST_TSCOLD_SET_MSK 0x00000010
4071
4072
#define ALT_RSTMGR_COLDMODRST_TSCOLD_CLR_MSK 0xffffffef
4073
4074
#define ALT_RSTMGR_COLDMODRST_TSCOLD_RESET 0x0
4075
4076
#define ALT_RSTMGR_COLDMODRST_TSCOLD_GET(value) (((value) & 0x00000010) >> 4)
4077
4078
#define ALT_RSTMGR_COLDMODRST_TSCOLD_SET(value) (((value) << 4) & 0x00000010)
4079
4090
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_LSB 5
4091
4092
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_MSB 5
4093
4094
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_WIDTH 1
4095
4096
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET_MSK 0x00000020
4097
4098
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_CLR_MSK 0xffffffdf
4099
4100
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_RESET 0x0
4101
4102
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_GET(value) (((value) & 0x00000020) >> 5)
4103
4104
#define ALT_RSTMGR_COLDMODRST_TAPCOLD_SET(value) (((value) << 5) & 0x00000020)
4105
4115
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_LSB 6
4116
4117
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_MSB 6
4118
4119
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_WIDTH 1
4120
4121
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET_MSK 0x00000040
4122
4123
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_CLR_MSK 0xffffffbf
4124
4125
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_RESET 0x0
4126
4127
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_GET(value) (((value) & 0x00000040) >> 6)
4128
4129
#define ALT_RSTMGR_COLDMODRST_HMCCOLD_SET(value) (((value) << 6) & 0x00000040)
4130
4141
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_LSB 7
4142
4143
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_MSB 7
4144
4145
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_WIDTH 1
4146
4147
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET_MSK 0x00000080
4148
4149
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_CLR_MSK 0xffffff7f
4150
4151
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_RESET 0x0
4152
4153
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_GET(value) (((value) & 0x00000080) >> 7)
4154
4155
#define ALT_RSTMGR_COLDMODRST_IOMGRCOLD_SET(value) (((value) << 7) & 0x00000080)
4156
4157
#ifndef __ASSEMBLY__
4158
4168
struct
ALT_RSTMGR_COLDMODRST_s
4169
{
4170
uint32_t
clkmgrcold
: 1;
4171
uint32_t : 2;
4172
uint32_t
s2fcold
: 1;
4173
uint32_t
timestampcold
: 1;
4174
uint32_t
tapcold
: 1;
4175
uint32_t
hmccold
: 1;
4176
uint32_t
iomgrcold
: 1;
4177
uint32_t : 24;
4178
};
4179
4181
typedef
volatile
struct
ALT_RSTMGR_COLDMODRST_s
ALT_RSTMGR_COLDMODRST_t
;
4182
#endif
/* __ASSEMBLY__ */
4183
4185
#define ALT_RSTMGR_COLDMODRST_RESET 0x00000000
4186
4187
#define ALT_RSTMGR_COLDMODRST_OFST 0x34
4188
4223
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_LSB 0
4224
4225
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_MSB 0
4226
4227
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_WIDTH 1
4228
4229
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET_MSK 0x00000001
4230
4231
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_CLR_MSK 0xfffffffe
4232
4233
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_RESET 0x0
4234
4235
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
4236
4237
#define ALT_RSTMGR_NRSTMODRST_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
4238
4239
#ifndef __ASSEMBLY__
4240
4250
struct
ALT_RSTMGR_NRSTMODRST_s
4251
{
4252
uint32_t
nrstpinoe
: 1;
4253
uint32_t : 31;
4254
};
4255
4257
typedef
volatile
struct
ALT_RSTMGR_NRSTMODRST_s
ALT_RSTMGR_NRSTMODRST_t
;
4258
#endif
/* __ASSEMBLY__ */
4259
4261
#define ALT_RSTMGR_NRSTMODRST_RESET 0x00000000
4262
4263
#define ALT_RSTMGR_NRSTMODRST_OFST 0x38
4264
4299
#define ALT_RSTMGR_DBGMODRST_DBG_LSB 0
4300
4301
#define ALT_RSTMGR_DBGMODRST_DBG_MSB 0
4302
4303
#define ALT_RSTMGR_DBGMODRST_DBG_WIDTH 1
4304
4305
#define ALT_RSTMGR_DBGMODRST_DBG_SET_MSK 0x00000001
4306
4307
#define ALT_RSTMGR_DBGMODRST_DBG_CLR_MSK 0xfffffffe
4308
4309
#define ALT_RSTMGR_DBGMODRST_DBG_RESET 0x0
4310
4311
#define ALT_RSTMGR_DBGMODRST_DBG_GET(value) (((value) & 0x00000001) >> 0)
4312
4313
#define ALT_RSTMGR_DBGMODRST_DBG_SET(value) (((value) << 0) & 0x00000001)
4314
4315
#ifndef __ASSEMBLY__
4316
4326
struct
ALT_RSTMGR_DBGMODRST_s
4327
{
4328
uint32_t
dbg
: 1;
4329
uint32_t : 31;
4330
};
4331
4333
typedef
volatile
struct
ALT_RSTMGR_DBGMODRST_s
ALT_RSTMGR_DBGMODRST_t
;
4334
#endif
/* __ASSEMBLY__ */
4335
4337
#define ALT_RSTMGR_DBGMODRST_RESET 0x00000000
4338
4339
#define ALT_RSTMGR_DBGMODRST_OFST 0x3c
4340
4374
#define ALT_RSTMGR_MPUWARMMSK_WDS_LSB 0
4375
4376
#define ALT_RSTMGR_MPUWARMMSK_WDS_MSB 0
4377
4378
#define ALT_RSTMGR_MPUWARMMSK_WDS_WIDTH 1
4379
4380
#define ALT_RSTMGR_MPUWARMMSK_WDS_SET_MSK 0x00000001
4381
4382
#define ALT_RSTMGR_MPUWARMMSK_WDS_CLR_MSK 0xfffffffe
4383
4384
#define ALT_RSTMGR_MPUWARMMSK_WDS_RESET 0x1
4385
4386
#define ALT_RSTMGR_MPUWARMMSK_WDS_GET(value) (((value) & 0x00000001) >> 0)
4387
4388
#define ALT_RSTMGR_MPUWARMMSK_WDS_SET(value) (((value) << 0) & 0x00000001)
4389
4390
#ifndef __ASSEMBLY__
4391
4401
struct
ALT_RSTMGR_MPUWARMMSK_s
4402
{
4403
uint32_t
wds
: 1;
4404
uint32_t : 31;
4405
};
4406
4408
typedef
volatile
struct
ALT_RSTMGR_MPUWARMMSK_s
ALT_RSTMGR_MPUWARMMSK_t
;
4409
#endif
/* __ASSEMBLY__ */
4410
4412
#define ALT_RSTMGR_MPUWARMMSK_RESET 0x0000001f
4413
4414
#define ALT_RSTMGR_MPUWARMMSK_OFST 0x40
4415
4478
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_LSB 0
4479
4480
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_MSB 0
4481
4482
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_WIDTH 1
4483
4484
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET_MSK 0x00000001
4485
4486
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_CLR_MSK 0xfffffffe
4487
4488
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_RESET 0x1
4489
4490
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
4491
4492
#define ALT_RSTMGR_PER0WARMMSK_EMAC0_SET(value) (((value) << 0) & 0x00000001)
4493
4503
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_LSB 1
4504
4505
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_MSB 1
4506
4507
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_WIDTH 1
4508
4509
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET_MSK 0x00000002
4510
4511
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_CLR_MSK 0xfffffffd
4512
4513
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_RESET 0x1
4514
4515
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
4516
4517
#define ALT_RSTMGR_PER0WARMMSK_EMAC1_SET(value) (((value) << 1) & 0x00000002)
4518
4528
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_LSB 2
4529
4530
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_MSB 2
4531
4532
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_WIDTH 1
4533
4534
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET_MSK 0x00000004
4535
4536
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_CLR_MSK 0xfffffffb
4537
4538
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_RESET 0x1
4539
4540
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_GET(value) (((value) & 0x00000004) >> 2)
4541
4542
#define ALT_RSTMGR_PER0WARMMSK_EMAC2_SET(value) (((value) << 2) & 0x00000004)
4543
4553
#define ALT_RSTMGR_PER0WARMMSK_USB0_LSB 3
4554
4555
#define ALT_RSTMGR_PER0WARMMSK_USB0_MSB 3
4556
4557
#define ALT_RSTMGR_PER0WARMMSK_USB0_WIDTH 1
4558
4559
#define ALT_RSTMGR_PER0WARMMSK_USB0_SET_MSK 0x00000008
4560
4561
#define ALT_RSTMGR_PER0WARMMSK_USB0_CLR_MSK 0xfffffff7
4562
4563
#define ALT_RSTMGR_PER0WARMMSK_USB0_RESET 0x1
4564
4565
#define ALT_RSTMGR_PER0WARMMSK_USB0_GET(value) (((value) & 0x00000008) >> 3)
4566
4567
#define ALT_RSTMGR_PER0WARMMSK_USB0_SET(value) (((value) << 3) & 0x00000008)
4568
4578
#define ALT_RSTMGR_PER0WARMMSK_USB1_LSB 4
4579
4580
#define ALT_RSTMGR_PER0WARMMSK_USB1_MSB 4
4581
4582
#define ALT_RSTMGR_PER0WARMMSK_USB1_WIDTH 1
4583
4584
#define ALT_RSTMGR_PER0WARMMSK_USB1_SET_MSK 0x00000010
4585
4586
#define ALT_RSTMGR_PER0WARMMSK_USB1_CLR_MSK 0xffffffef
4587
4588
#define ALT_RSTMGR_PER0WARMMSK_USB1_RESET 0x1
4589
4590
#define ALT_RSTMGR_PER0WARMMSK_USB1_GET(value) (((value) & 0x00000010) >> 4)
4591
4592
#define ALT_RSTMGR_PER0WARMMSK_USB1_SET(value) (((value) << 4) & 0x00000010)
4593
4603
#define ALT_RSTMGR_PER0WARMMSK_NAND_LSB 5
4604
4605
#define ALT_RSTMGR_PER0WARMMSK_NAND_MSB 5
4606
4607
#define ALT_RSTMGR_PER0WARMMSK_NAND_WIDTH 1
4608
4609
#define ALT_RSTMGR_PER0WARMMSK_NAND_SET_MSK 0x00000020
4610
4611
#define ALT_RSTMGR_PER0WARMMSK_NAND_CLR_MSK 0xffffffdf
4612
4613
#define ALT_RSTMGR_PER0WARMMSK_NAND_RESET 0x1
4614
4615
#define ALT_RSTMGR_PER0WARMMSK_NAND_GET(value) (((value) & 0x00000020) >> 5)
4616
4617
#define ALT_RSTMGR_PER0WARMMSK_NAND_SET(value) (((value) << 5) & 0x00000020)
4618
4628
#define ALT_RSTMGR_PER0WARMMSK_QSPI_LSB 6
4629
4630
#define ALT_RSTMGR_PER0WARMMSK_QSPI_MSB 6
4631
4632
#define ALT_RSTMGR_PER0WARMMSK_QSPI_WIDTH 1
4633
4634
#define ALT_RSTMGR_PER0WARMMSK_QSPI_SET_MSK 0x00000040
4635
4636
#define ALT_RSTMGR_PER0WARMMSK_QSPI_CLR_MSK 0xffffffbf
4637
4638
#define ALT_RSTMGR_PER0WARMMSK_QSPI_RESET 0x1
4639
4640
#define ALT_RSTMGR_PER0WARMMSK_QSPI_GET(value) (((value) & 0x00000040) >> 6)
4641
4642
#define ALT_RSTMGR_PER0WARMMSK_QSPI_SET(value) (((value) << 6) & 0x00000040)
4643
4653
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_LSB 7
4654
4655
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_MSB 7
4656
4657
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_WIDTH 1
4658
4659
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET_MSK 0x00000080
4660
4661
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_CLR_MSK 0xffffff7f
4662
4663
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_RESET 0x1
4664
4665
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_GET(value) (((value) & 0x00000080) >> 7)
4666
4667
#define ALT_RSTMGR_PER0WARMMSK_SDMMC_SET(value) (((value) << 7) & 0x00000080)
4668
4678
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_LSB 8
4679
4680
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_MSB 8
4681
4682
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_WIDTH 1
4683
4684
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET_MSK 0x00000100
4685
4686
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_CLR_MSK 0xfffffeff
4687
4688
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_RESET 0x1
4689
4690
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8)
4691
4692
#define ALT_RSTMGR_PER0WARMMSK_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100)
4693
4703
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_LSB 9
4704
4705
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_MSB 9
4706
4707
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_WIDTH 1
4708
4709
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET_MSK 0x00000200
4710
4711
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_CLR_MSK 0xfffffdff
4712
4713
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_RESET 0x1
4714
4715
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9)
4716
4717
#define ALT_RSTMGR_PER0WARMMSK_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200)
4718
4728
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_LSB 10
4729
4730
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_MSB 10
4731
4732
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_WIDTH 1
4733
4734
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET_MSK 0x00000400
4735
4736
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_CLR_MSK 0xfffffbff
4737
4738
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_RESET 0x1
4739
4740
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10)
4741
4742
#define ALT_RSTMGR_PER0WARMMSK_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400)
4743
4753
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_LSB 11
4754
4755
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_MSB 11
4756
4757
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_WIDTH 1
4758
4759
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET_MSK 0x00000800
4760
4761
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_CLR_MSK 0xfffff7ff
4762
4763
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_RESET 0x1
4764
4765
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_GET(value) (((value) & 0x00000800) >> 11)
4766
4767
#define ALT_RSTMGR_PER0WARMMSK_USB0OCP_SET(value) (((value) << 11) & 0x00000800)
4768
4778
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_LSB 12
4779
4780
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_MSB 12
4781
4782
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_WIDTH 1
4783
4784
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET_MSK 0x00001000
4785
4786
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_CLR_MSK 0xffffefff
4787
4788
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_RESET 0x1
4789
4790
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_GET(value) (((value) & 0x00001000) >> 12)
4791
4792
#define ALT_RSTMGR_PER0WARMMSK_USB1OCP_SET(value) (((value) << 12) & 0x00001000)
4793
4803
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_LSB 13
4804
4805
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_MSB 13
4806
4807
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_WIDTH 1
4808
4809
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET_MSK 0x00002000
4810
4811
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_CLR_MSK 0xffffdfff
4812
4813
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_RESET 0x1
4814
4815
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_GET(value) (((value) & 0x00002000) >> 13)
4816
4817
#define ALT_RSTMGR_PER0WARMMSK_NANDOCP_SET(value) (((value) << 13) & 0x00002000)
4818
4828
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_LSB 14
4829
4830
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_MSB 14
4831
4832
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_WIDTH 1
4833
4834
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET_MSK 0x00004000
4835
4836
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_CLR_MSK 0xffffbfff
4837
4838
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_RESET 0x1
4839
4840
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14)
4841
4842
#define ALT_RSTMGR_PER0WARMMSK_QSPIOCP_SET(value) (((value) << 14) & 0x00004000)
4843
4853
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_LSB 15
4854
4855
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_MSB 15
4856
4857
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_WIDTH 1
4858
4859
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET_MSK 0x00008000
4860
4861
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_CLR_MSK 0xffff7fff
4862
4863
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_RESET 0x1
4864
4865
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15)
4866
4867
#define ALT_RSTMGR_PER0WARMMSK_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000)
4868
4878
#define ALT_RSTMGR_PER0WARMMSK_DMA_LSB 16
4879
4880
#define ALT_RSTMGR_PER0WARMMSK_DMA_MSB 16
4881
4882
#define ALT_RSTMGR_PER0WARMMSK_DMA_WIDTH 1
4883
4884
#define ALT_RSTMGR_PER0WARMMSK_DMA_SET_MSK 0x00010000
4885
4886
#define ALT_RSTMGR_PER0WARMMSK_DMA_CLR_MSK 0xfffeffff
4887
4888
#define ALT_RSTMGR_PER0WARMMSK_DMA_RESET 0x1
4889
4890
#define ALT_RSTMGR_PER0WARMMSK_DMA_GET(value) (((value) & 0x00010000) >> 16)
4891
4892
#define ALT_RSTMGR_PER0WARMMSK_DMA_SET(value) (((value) << 16) & 0x00010000)
4893
4903
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_LSB 17
4904
4905
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_MSB 17
4906
4907
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_WIDTH 1
4908
4909
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET_MSK 0x00020000
4910
4911
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_CLR_MSK 0xfffdffff
4912
4913
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_RESET 0x1
4914
4915
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_GET(value) (((value) & 0x00020000) >> 17)
4916
4917
#define ALT_RSTMGR_PER0WARMMSK_SPIM0_SET(value) (((value) << 17) & 0x00020000)
4918
4928
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_LSB 18
4929
4930
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_MSB 18
4931
4932
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_WIDTH 1
4933
4934
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET_MSK 0x00040000
4935
4936
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_CLR_MSK 0xfffbffff
4937
4938
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_RESET 0x1
4939
4940
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_GET(value) (((value) & 0x00040000) >> 18)
4941
4942
#define ALT_RSTMGR_PER0WARMMSK_SPIM1_SET(value) (((value) << 18) & 0x00040000)
4943
4953
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_LSB 19
4954
4955
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_MSB 19
4956
4957
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_WIDTH 1
4958
4959
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET_MSK 0x00080000
4960
4961
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_CLR_MSK 0xfff7ffff
4962
4963
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_RESET 0x1
4964
4965
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_GET(value) (((value) & 0x00080000) >> 19)
4966
4967
#define ALT_RSTMGR_PER0WARMMSK_SPIS0_SET(value) (((value) << 19) & 0x00080000)
4968
4978
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_LSB 20
4979
4980
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_MSB 20
4981
4982
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_WIDTH 1
4983
4984
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET_MSK 0x00100000
4985
4986
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_CLR_MSK 0xffefffff
4987
4988
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_RESET 0x1
4989
4990
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_GET(value) (((value) & 0x00100000) >> 20)
4991
4992
#define ALT_RSTMGR_PER0WARMMSK_SPIS1_SET(value) (((value) << 20) & 0x00100000)
4993
5004
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_LSB 21
5005
5006
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_MSB 21
5007
5008
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_WIDTH 1
5009
5010
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET_MSK 0x00200000
5011
5012
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_CLR_MSK 0xffdfffff
5013
5014
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_RESET 0x1
5015
5016
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_GET(value) (((value) & 0x00200000) >> 21)
5017
5018
#define ALT_RSTMGR_PER0WARMMSK_DMAOCP_SET(value) (((value) << 21) & 0x00200000)
5019
5029
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_LSB 22
5030
5031
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_MSB 22
5032
5033
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_WIDTH 1
5034
5035
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET_MSK 0x00400000
5036
5037
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_CLR_MSK 0xffbfffff
5038
5039
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_RESET 0x1
5040
5041
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_GET(value) (((value) & 0x00400000) >> 22)
5042
5043
#define ALT_RSTMGR_PER0WARMMSK_EMACPTP_SET(value) (((value) << 22) & 0x00400000)
5044
5055
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_LSB 24
5056
5057
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_MSB 24
5058
5059
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_WIDTH 1
5060
5061
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET_MSK 0x01000000
5062
5063
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_CLR_MSK 0xfeffffff
5064
5065
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_RESET 0x1
5066
5067
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_GET(value) (((value) & 0x01000000) >> 24)
5068
5069
#define ALT_RSTMGR_PER0WARMMSK_DMAIF0_SET(value) (((value) << 24) & 0x01000000)
5070
5081
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_LSB 25
5082
5083
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_MSB 25
5084
5085
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_WIDTH 1
5086
5087
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET_MSK 0x02000000
5088
5089
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_CLR_MSK 0xfdffffff
5090
5091
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_RESET 0x1
5092
5093
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_GET(value) (((value) & 0x02000000) >> 25)
5094
5095
#define ALT_RSTMGR_PER0WARMMSK_DMAIF1_SET(value) (((value) << 25) & 0x02000000)
5096
5107
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_LSB 26
5108
5109
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_MSB 26
5110
5111
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_WIDTH 1
5112
5113
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET_MSK 0x04000000
5114
5115
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_CLR_MSK 0xfbffffff
5116
5117
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_RESET 0x1
5118
5119
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_GET(value) (((value) & 0x04000000) >> 26)
5120
5121
#define ALT_RSTMGR_PER0WARMMSK_DMAIF2_SET(value) (((value) << 26) & 0x04000000)
5122
5133
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_LSB 27
5134
5135
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_MSB 27
5136
5137
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_WIDTH 1
5138
5139
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET_MSK 0x08000000
5140
5141
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_CLR_MSK 0xf7ffffff
5142
5143
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_RESET 0x1
5144
5145
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_GET(value) (((value) & 0x08000000) >> 27)
5146
5147
#define ALT_RSTMGR_PER0WARMMSK_DMAIF3_SET(value) (((value) << 27) & 0x08000000)
5148
5159
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_LSB 28
5160
5161
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_MSB 28
5162
5163
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_WIDTH 1
5164
5165
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET_MSK 0x10000000
5166
5167
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_CLR_MSK 0xefffffff
5168
5169
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_RESET 0x1
5170
5171
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_GET(value) (((value) & 0x10000000) >> 28)
5172
5173
#define ALT_RSTMGR_PER0WARMMSK_DMAIF4_SET(value) (((value) << 28) & 0x10000000)
5174
5185
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_LSB 29
5186
5187
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_MSB 29
5188
5189
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_WIDTH 1
5190
5191
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET_MSK 0x20000000
5192
5193
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_CLR_MSK 0xdfffffff
5194
5195
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_RESET 0x1
5196
5197
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_GET(value) (((value) & 0x20000000) >> 29)
5198
5199
#define ALT_RSTMGR_PER0WARMMSK_DMAIF5_SET(value) (((value) << 29) & 0x20000000)
5200
5211
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_LSB 30
5212
5213
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_MSB 30
5214
5215
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_WIDTH 1
5216
5217
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET_MSK 0x40000000
5218
5219
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_CLR_MSK 0xbfffffff
5220
5221
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_RESET 0x1
5222
5223
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_GET(value) (((value) & 0x40000000) >> 30)
5224
5225
#define ALT_RSTMGR_PER0WARMMSK_DMAIF6_SET(value) (((value) << 30) & 0x40000000)
5226
5237
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_LSB 31
5238
5239
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_MSB 31
5240
5241
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_WIDTH 1
5242
5243
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET_MSK 0x80000000
5244
5245
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_CLR_MSK 0x7fffffff
5246
5247
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_RESET 0x1
5248
5249
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_GET(value) (((value) & 0x80000000) >> 31)
5250
5251
#define ALT_RSTMGR_PER0WARMMSK_DMAIF7_SET(value) (((value) << 31) & 0x80000000)
5252
5253
#ifndef __ASSEMBLY__
5254
5264
struct
ALT_RSTMGR_PER0WARMMSK_s
5265
{
5266
uint32_t
emac0
: 1;
5267
uint32_t
emac1
: 1;
5268
uint32_t
emac2
: 1;
5269
uint32_t
usb0
: 1;
5270
uint32_t
usb1
: 1;
5271
uint32_t
nand
: 1;
5272
uint32_t
qspi
: 1;
5273
uint32_t
sdmmc
: 1;
5274
uint32_t
emac0ocp
: 1;
5275
uint32_t
emac1ocp
: 1;
5276
uint32_t
emac2ocp
: 1;
5277
uint32_t
usb0ocp
: 1;
5278
uint32_t
usb1ocp
: 1;
5279
uint32_t
nandocp
: 1;
5280
uint32_t
qspiocp
: 1;
5281
uint32_t
sdmmcocp
: 1;
5282
uint32_t
dma
: 1;
5283
uint32_t
spim0
: 1;
5284
uint32_t
spim1
: 1;
5285
uint32_t
spis0
: 1;
5286
uint32_t
spis1
: 1;
5287
uint32_t
dmaocp
: 1;
5288
uint32_t
emacptp
: 1;
5289
uint32_t : 1;
5290
uint32_t
dmaif0
: 1;
5291
uint32_t
dmaif1
: 1;
5292
uint32_t
dmaif2
: 1;
5293
uint32_t
dmaif3
: 1;
5294
uint32_t
dmaif4
: 1;
5295
uint32_t
dmaif5
: 1;
5296
uint32_t
dmaif6
: 1;
5297
uint32_t
dmaif7
: 1;
5298
};
5299
5301
typedef
volatile
struct
ALT_RSTMGR_PER0WARMMSK_s
ALT_RSTMGR_PER0WARMMSK_t
;
5302
#endif
/* __ASSEMBLY__ */
5303
5305
#define ALT_RSTMGR_PER0WARMMSK_RESET 0xff7fffff
5306
5307
#define ALT_RSTMGR_PER0WARMMSK_OFST 0x44
5308
5359
#define ALT_RSTMGR_PER1WARMMSK_WD0_LSB 0
5360
5361
#define ALT_RSTMGR_PER1WARMMSK_WD0_MSB 0
5362
5363
#define ALT_RSTMGR_PER1WARMMSK_WD0_WIDTH 1
5364
5365
#define ALT_RSTMGR_PER1WARMMSK_WD0_SET_MSK 0x00000001
5366
5367
#define ALT_RSTMGR_PER1WARMMSK_WD0_CLR_MSK 0xfffffffe
5368
5369
#define ALT_RSTMGR_PER1WARMMSK_WD0_RESET 0x1
5370
5371
#define ALT_RSTMGR_PER1WARMMSK_WD0_GET(value) (((value) & 0x00000001) >> 0)
5372
5373
#define ALT_RSTMGR_PER1WARMMSK_WD0_SET(value) (((value) << 0) & 0x00000001)
5374
5384
#define ALT_RSTMGR_PER1WARMMSK_WD1_LSB 1
5385
5386
#define ALT_RSTMGR_PER1WARMMSK_WD1_MSB 1
5387
5388
#define ALT_RSTMGR_PER1WARMMSK_WD1_WIDTH 1
5389
5390
#define ALT_RSTMGR_PER1WARMMSK_WD1_SET_MSK 0x00000002
5391
5392
#define ALT_RSTMGR_PER1WARMMSK_WD1_CLR_MSK 0xfffffffd
5393
5394
#define ALT_RSTMGR_PER1WARMMSK_WD1_RESET 0x1
5395
5396
#define ALT_RSTMGR_PER1WARMMSK_WD1_GET(value) (((value) & 0x00000002) >> 1)
5397
5398
#define ALT_RSTMGR_PER1WARMMSK_WD1_SET(value) (((value) << 1) & 0x00000002)
5399
5409
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_LSB 2
5410
5411
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_MSB 2
5412
5413
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_WIDTH 1
5414
5415
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET_MSK 0x00000004
5416
5417
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_CLR_MSK 0xfffffffb
5418
5419
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_RESET 0x1
5420
5421
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_GET(value) (((value) & 0x00000004) >> 2)
5422
5423
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR0_SET(value) (((value) << 2) & 0x00000004)
5424
5434
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_LSB 3
5435
5436
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_MSB 3
5437
5438
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_WIDTH 1
5439
5440
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET_MSK 0x00000008
5441
5442
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_CLR_MSK 0xfffffff7
5443
5444
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_RESET 0x1
5445
5446
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_GET(value) (((value) & 0x00000008) >> 3)
5447
5448
#define ALT_RSTMGR_PER1WARMMSK_L4SYSTMR1_SET(value) (((value) << 3) & 0x00000008)
5449
5459
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_LSB 4
5460
5461
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_MSB 4
5462
5463
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_WIDTH 1
5464
5465
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET_MSK 0x00000010
5466
5467
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_CLR_MSK 0xffffffef
5468
5469
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_RESET 0x1
5470
5471
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_GET(value) (((value) & 0x00000010) >> 4)
5472
5473
#define ALT_RSTMGR_PER1WARMMSK_SPTMR0_SET(value) (((value) << 4) & 0x00000010)
5474
5484
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_LSB 5
5485
5486
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_MSB 5
5487
5488
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_WIDTH 1
5489
5490
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET_MSK 0x00000020
5491
5492
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_CLR_MSK 0xffffffdf
5493
5494
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_RESET 0x1
5495
5496
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_GET(value) (((value) & 0x00000020) >> 5)
5497
5498
#define ALT_RSTMGR_PER1WARMMSK_SPTMR1_SET(value) (((value) << 5) & 0x00000020)
5499
5509
#define ALT_RSTMGR_PER1WARMMSK_I2C0_LSB 8
5510
5511
#define ALT_RSTMGR_PER1WARMMSK_I2C0_MSB 8
5512
5513
#define ALT_RSTMGR_PER1WARMMSK_I2C0_WIDTH 1
5514
5515
#define ALT_RSTMGR_PER1WARMMSK_I2C0_SET_MSK 0x00000100
5516
5517
#define ALT_RSTMGR_PER1WARMMSK_I2C0_CLR_MSK 0xfffffeff
5518
5519
#define ALT_RSTMGR_PER1WARMMSK_I2C0_RESET 0x1
5520
5521
#define ALT_RSTMGR_PER1WARMMSK_I2C0_GET(value) (((value) & 0x00000100) >> 8)
5522
5523
#define ALT_RSTMGR_PER1WARMMSK_I2C0_SET(value) (((value) << 8) & 0x00000100)
5524
5534
#define ALT_RSTMGR_PER1WARMMSK_I2C1_LSB 9
5535
5536
#define ALT_RSTMGR_PER1WARMMSK_I2C1_MSB 9
5537
5538
#define ALT_RSTMGR_PER1WARMMSK_I2C1_WIDTH 1
5539
5540
#define ALT_RSTMGR_PER1WARMMSK_I2C1_SET_MSK 0x00000200
5541
5542
#define ALT_RSTMGR_PER1WARMMSK_I2C1_CLR_MSK 0xfffffdff
5543
5544
#define ALT_RSTMGR_PER1WARMMSK_I2C1_RESET 0x1
5545
5546
#define ALT_RSTMGR_PER1WARMMSK_I2C1_GET(value) (((value) & 0x00000200) >> 9)
5547
5548
#define ALT_RSTMGR_PER1WARMMSK_I2C1_SET(value) (((value) << 9) & 0x00000200)
5549
5559
#define ALT_RSTMGR_PER1WARMMSK_I2C2_LSB 10
5560
5561
#define ALT_RSTMGR_PER1WARMMSK_I2C2_MSB 10
5562
5563
#define ALT_RSTMGR_PER1WARMMSK_I2C2_WIDTH 1
5564
5565
#define ALT_RSTMGR_PER1WARMMSK_I2C2_SET_MSK 0x00000400
5566
5567
#define ALT_RSTMGR_PER1WARMMSK_I2C2_CLR_MSK 0xfffffbff
5568
5569
#define ALT_RSTMGR_PER1WARMMSK_I2C2_RESET 0x1
5570
5571
#define ALT_RSTMGR_PER1WARMMSK_I2C2_GET(value) (((value) & 0x00000400) >> 10)
5572
5573
#define ALT_RSTMGR_PER1WARMMSK_I2C2_SET(value) (((value) << 10) & 0x00000400)
5574
5584
#define ALT_RSTMGR_PER1WARMMSK_I2C3_LSB 11
5585
5586
#define ALT_RSTMGR_PER1WARMMSK_I2C3_MSB 11
5587
5588
#define ALT_RSTMGR_PER1WARMMSK_I2C3_WIDTH 1
5589
5590
#define ALT_RSTMGR_PER1WARMMSK_I2C3_SET_MSK 0x00000800
5591
5592
#define ALT_RSTMGR_PER1WARMMSK_I2C3_CLR_MSK 0xfffff7ff
5593
5594
#define ALT_RSTMGR_PER1WARMMSK_I2C3_RESET 0x1
5595
5596
#define ALT_RSTMGR_PER1WARMMSK_I2C3_GET(value) (((value) & 0x00000800) >> 11)
5597
5598
#define ALT_RSTMGR_PER1WARMMSK_I2C3_SET(value) (((value) << 11) & 0x00000800)
5599
5609
#define ALT_RSTMGR_PER1WARMMSK_I2C4_LSB 12
5610
5611
#define ALT_RSTMGR_PER1WARMMSK_I2C4_MSB 12
5612
5613
#define ALT_RSTMGR_PER1WARMMSK_I2C4_WIDTH 1
5614
5615
#define ALT_RSTMGR_PER1WARMMSK_I2C4_SET_MSK 0x00001000
5616
5617
#define ALT_RSTMGR_PER1WARMMSK_I2C4_CLR_MSK 0xffffefff
5618
5619
#define ALT_RSTMGR_PER1WARMMSK_I2C4_RESET 0x1
5620
5621
#define ALT_RSTMGR_PER1WARMMSK_I2C4_GET(value) (((value) & 0x00001000) >> 12)
5622
5623
#define ALT_RSTMGR_PER1WARMMSK_I2C4_SET(value) (((value) << 12) & 0x00001000)
5624
5634
#define ALT_RSTMGR_PER1WARMMSK_UART0_LSB 16
5635
5636
#define ALT_RSTMGR_PER1WARMMSK_UART0_MSB 16
5637
5638
#define ALT_RSTMGR_PER1WARMMSK_UART0_WIDTH 1
5639
5640
#define ALT_RSTMGR_PER1WARMMSK_UART0_SET_MSK 0x00010000
5641
5642
#define ALT_RSTMGR_PER1WARMMSK_UART0_CLR_MSK 0xfffeffff
5643
5644
#define ALT_RSTMGR_PER1WARMMSK_UART0_RESET 0x1
5645
5646
#define ALT_RSTMGR_PER1WARMMSK_UART0_GET(value) (((value) & 0x00010000) >> 16)
5647
5648
#define ALT_RSTMGR_PER1WARMMSK_UART0_SET(value) (((value) << 16) & 0x00010000)
5649
5659
#define ALT_RSTMGR_PER1WARMMSK_UART1_LSB 17
5660
5661
#define ALT_RSTMGR_PER1WARMMSK_UART1_MSB 17
5662
5663
#define ALT_RSTMGR_PER1WARMMSK_UART1_WIDTH 1
5664
5665
#define ALT_RSTMGR_PER1WARMMSK_UART1_SET_MSK 0x00020000
5666
5667
#define ALT_RSTMGR_PER1WARMMSK_UART1_CLR_MSK 0xfffdffff
5668
5669
#define ALT_RSTMGR_PER1WARMMSK_UART1_RESET 0x1
5670
5671
#define ALT_RSTMGR_PER1WARMMSK_UART1_GET(value) (((value) & 0x00020000) >> 17)
5672
5673
#define ALT_RSTMGR_PER1WARMMSK_UART1_SET(value) (((value) << 17) & 0x00020000)
5674
5684
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_LSB 24
5685
5686
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_MSB 24
5687
5688
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_WIDTH 1
5689
5690
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET_MSK 0x01000000
5691
5692
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_CLR_MSK 0xfeffffff
5693
5694
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_RESET 0x1
5695
5696
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_GET(value) (((value) & 0x01000000) >> 24)
5697
5698
#define ALT_RSTMGR_PER1WARMMSK_GPIO0_SET(value) (((value) << 24) & 0x01000000)
5699
5709
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_LSB 25
5710
5711
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_MSB 25
5712
5713
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_WIDTH 1
5714
5715
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET_MSK 0x02000000
5716
5717
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_CLR_MSK 0xfdffffff
5718
5719
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_RESET 0x1
5720
5721
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_GET(value) (((value) & 0x02000000) >> 25)
5722
5723
#define ALT_RSTMGR_PER1WARMMSK_GPIO1_SET(value) (((value) << 25) & 0x02000000)
5724
5734
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_LSB 26
5735
5736
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_MSB 26
5737
5738
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_WIDTH 1
5739
5740
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET_MSK 0x04000000
5741
5742
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_CLR_MSK 0xfbffffff
5743
5744
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_RESET 0x1
5745
5746
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_GET(value) (((value) & 0x04000000) >> 26)
5747
5748
#define ALT_RSTMGR_PER1WARMMSK_GPIO2_SET(value) (((value) << 26) & 0x04000000)
5749
5750
#ifndef __ASSEMBLY__
5751
5761
struct
ALT_RSTMGR_PER1WARMMSK_s
5762
{
5763
uint32_t
watchdog0
: 1;
5764
uint32_t
watchdog1
: 1;
5765
uint32_t
l4systimer0
: 1;
5766
uint32_t
l4systimer1
: 1;
5767
uint32_t
sptimer0
: 1;
5768
uint32_t
sptimer1
: 1;
5769
uint32_t : 2;
5770
uint32_t
i2c0
: 1;
5771
uint32_t
i2c1
: 1;
5772
uint32_t
i2c2
: 1;
5773
uint32_t
i2c3
: 1;
5774
uint32_t
i2c4
: 1;
5775
uint32_t : 3;
5776
uint32_t
uart0
: 1;
5777
uint32_t
uart1
: 1;
5778
uint32_t : 6;
5779
uint32_t
gpio0
: 1;
5780
uint32_t
gpio1
: 1;
5781
uint32_t
gpio2
: 1;
5782
uint32_t : 5;
5783
};
5784
5786
typedef
volatile
struct
ALT_RSTMGR_PER1WARMMSK_s
ALT_RSTMGR_PER1WARMMSK_t
;
5787
#endif
/* __ASSEMBLY__ */
5788
5790
#define ALT_RSTMGR_PER1WARMMSK_RESET 0x07031f3f
5791
5792
#define ALT_RSTMGR_PER1WARMMSK_OFST 0x48
5793
5832
#define ALT_RSTMGR_BRGWARMMSK_H2F_LSB 0
5833
5834
#define ALT_RSTMGR_BRGWARMMSK_H2F_MSB 0
5835
5836
#define ALT_RSTMGR_BRGWARMMSK_H2F_WIDTH 1
5837
5838
#define ALT_RSTMGR_BRGWARMMSK_H2F_SET_MSK 0x00000001
5839
5840
#define ALT_RSTMGR_BRGWARMMSK_H2F_CLR_MSK 0xfffffffe
5841
5842
#define ALT_RSTMGR_BRGWARMMSK_H2F_RESET 0x1
5843
5844
#define ALT_RSTMGR_BRGWARMMSK_H2F_GET(value) (((value) & 0x00000001) >> 0)
5845
5846
#define ALT_RSTMGR_BRGWARMMSK_H2F_SET(value) (((value) << 0) & 0x00000001)
5847
5857
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_LSB 1
5858
5859
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_MSB 1
5860
5861
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_WIDTH 1
5862
5863
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET_MSK 0x00000002
5864
5865
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_CLR_MSK 0xfffffffd
5866
5867
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_RESET 0x1
5868
5869
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
5870
5871
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET(value) (((value) << 1) & 0x00000002)
5872
5882
#define ALT_RSTMGR_BRGWARMMSK_F2H_LSB 2
5883
5884
#define ALT_RSTMGR_BRGWARMMSK_F2H_MSB 2
5885
5886
#define ALT_RSTMGR_BRGWARMMSK_F2H_WIDTH 1
5887
5888
#define ALT_RSTMGR_BRGWARMMSK_F2H_SET_MSK 0x00000004
5889
5890
#define ALT_RSTMGR_BRGWARMMSK_F2H_CLR_MSK 0xfffffffb
5891
5892
#define ALT_RSTMGR_BRGWARMMSK_F2H_RESET 0x1
5893
5894
#define ALT_RSTMGR_BRGWARMMSK_F2H_GET(value) (((value) & 0x00000004) >> 2)
5895
5896
#define ALT_RSTMGR_BRGWARMMSK_F2H_SET(value) (((value) << 2) & 0x00000004)
5897
5907
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_LSB 3
5908
5909
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_MSB 3
5910
5911
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_WIDTH 1
5912
5913
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET_MSK 0x00000008
5914
5915
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_CLR_MSK 0xfffffff7
5916
5917
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_RESET 0x1
5918
5919
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3)
5920
5921
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008)
5922
5932
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_LSB 4
5933
5934
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_MSB 4
5935
5936
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_WIDTH 1
5937
5938
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET_MSK 0x00000010
5939
5940
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_CLR_MSK 0xffffffef
5941
5942
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_RESET 0x1
5943
5944
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4)
5945
5946
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010)
5947
5957
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_LSB 5
5958
5959
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_MSB 5
5960
5961
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_WIDTH 1
5962
5963
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET_MSK 0x00000020
5964
5965
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_CLR_MSK 0xffffffdf
5966
5967
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_RESET 0x1
5968
5969
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5)
5970
5971
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020)
5972
5982
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_LSB 6
5983
5984
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_MSB 6
5985
5986
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_WIDTH 1
5987
5988
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET_MSK 0x00000040
5989
5990
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_CLR_MSK 0xffffffbf
5991
5992
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_RESET 0x1
5993
5994
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6)
5995
5996
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET(value) (((value) << 6) & 0x00000040)
5997
5998
#ifndef __ASSEMBLY__
5999
6009
struct
ALT_RSTMGR_BRGWARMMSK_s
6010
{
6011
uint32_t
hps2fpga
: 1;
6012
uint32_t
lwhps2fpga
: 1;
6013
uint32_t
fpga2hps
: 1;
6014
uint32_t
f2ssdram0
: 1;
6015
uint32_t
f2ssdram1
: 1;
6016
uint32_t
f2ssdram2
: 1;
6017
uint32_t
ddrsch
: 1;
6018
uint32_t : 25;
6019
};
6020
6022
typedef
volatile
struct
ALT_RSTMGR_BRGWARMMSK_s
ALT_RSTMGR_BRGWARMMSK_t
;
6023
#endif
/* __ASSEMBLY__ */
6024
6026
#define ALT_RSTMGR_BRGWARMMSK_RESET 0x0000007f
6027
6028
#define ALT_RSTMGR_BRGWARMMSK_OFST 0x4c
6029
6071
#define ALT_RSTMGR_SYSWARMMSK_ROM_LSB 0
6072
6073
#define ALT_RSTMGR_SYSWARMMSK_ROM_MSB 0
6074
6075
#define ALT_RSTMGR_SYSWARMMSK_ROM_WIDTH 1
6076
6077
#define ALT_RSTMGR_SYSWARMMSK_ROM_SET_MSK 0x00000001
6078
6079
#define ALT_RSTMGR_SYSWARMMSK_ROM_CLR_MSK 0xfffffffe
6080
6081
#define ALT_RSTMGR_SYSWARMMSK_ROM_RESET 0x1
6082
6083
#define ALT_RSTMGR_SYSWARMMSK_ROM_GET(value) (((value) & 0x00000001) >> 0)
6084
6085
#define ALT_RSTMGR_SYSWARMMSK_ROM_SET(value) (((value) << 0) & 0x00000001)
6086
6096
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_LSB 1
6097
6098
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_MSB 1
6099
6100
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_WIDTH 1
6101
6102
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET_MSK 0x00000002
6103
6104
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_CLR_MSK 0xfffffffd
6105
6106
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_RESET 0x1
6107
6108
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6109
6110
#define ALT_RSTMGR_SYSWARMMSK_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6111
6121
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_LSB 3
6122
6123
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_MSB 3
6124
6125
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_WIDTH 1
6126
6127
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET_MSK 0x00000008
6128
6129
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_CLR_MSK 0xfffffff7
6130
6131
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_RESET 0x1
6132
6133
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_GET(value) (((value) & 0x00000008) >> 3)
6134
6135
#define ALT_RSTMGR_SYSWARMMSK_FPGAMGR_SET(value) (((value) << 3) & 0x00000008)
6136
6147
#define ALT_RSTMGR_SYSWARMMSK_S2F_LSB 4
6148
6149
#define ALT_RSTMGR_SYSWARMMSK_S2F_MSB 4
6150
6151
#define ALT_RSTMGR_SYSWARMMSK_S2F_WIDTH 1
6152
6153
#define ALT_RSTMGR_SYSWARMMSK_S2F_SET_MSK 0x00000010
6154
6155
#define ALT_RSTMGR_SYSWARMMSK_S2F_CLR_MSK 0xffffffef
6156
6157
#define ALT_RSTMGR_SYSWARMMSK_S2F_RESET 0x1
6158
6159
#define ALT_RSTMGR_SYSWARMMSK_S2F_GET(value) (((value) & 0x00000010) >> 4)
6160
6161
#define ALT_RSTMGR_SYSWARMMSK_S2F_SET(value) (((value) << 4) & 0x00000010)
6162
6173
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_LSB 5
6174
6175
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_MSB 5
6176
6177
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_WIDTH 1
6178
6179
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET_MSK 0x00000020
6180
6181
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_CLR_MSK 0xffffffdf
6182
6183
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_RESET 0x1
6184
6185
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_GET(value) (((value) & 0x00000020) >> 5)
6186
6187
#define ALT_RSTMGR_SYSWARMMSK_SYSDBG_SET(value) (((value) << 5) & 0x00000020)
6188
6198
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_LSB 6
6199
6200
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_MSB 6
6201
6202
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_WIDTH 1
6203
6204
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET_MSK 0x00000040
6205
6206
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_CLR_MSK 0xffffffbf
6207
6208
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_RESET 0x1
6209
6210
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_GET(value) (((value) & 0x00000040) >> 6)
6211
6212
#define ALT_RSTMGR_SYSWARMMSK_OCRAMOCP_SET(value) (((value) << 6) & 0x00000040)
6213
6214
#ifndef __ASSEMBLY__
6215
6225
struct
ALT_RSTMGR_SYSWARMMSK_s
6226
{
6227
uint32_t
rom
: 1;
6228
uint32_t
ocram
: 1;
6229
uint32_t : 1;
6230
uint32_t
fpgamgr
: 1;
6231
uint32_t
s2f
: 1;
6232
uint32_t
sysdbg
: 1;
6233
uint32_t
ocramocp
: 1;
6234
uint32_t : 25;
6235
};
6236
6238
typedef
volatile
struct
ALT_RSTMGR_SYSWARMMSK_s
ALT_RSTMGR_SYSWARMMSK_t
;
6239
#endif
/* __ASSEMBLY__ */
6240
6242
#define ALT_RSTMGR_SYSWARMMSK_RESET 0x000001ff
6243
6244
#define ALT_RSTMGR_SYSWARMMSK_OFST 0x50
6245
6281
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_LSB 0
6282
6283
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_MSB 0
6284
6285
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_WIDTH 1
6286
6287
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET_MSK 0x00000001
6288
6289
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_CLR_MSK 0xfffffffe
6290
6291
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_RESET 0x1
6292
6293
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0)
6294
6295
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001)
6296
6297
#ifndef __ASSEMBLY__
6298
6308
struct
ALT_RSTMGR_NRSTWARMMSK_s
6309
{
6310
uint32_t
nrstpinoe
: 1;
6311
uint32_t : 31;
6312
};
6313
6315
typedef
volatile
struct
ALT_RSTMGR_NRSTWARMMSK_s
ALT_RSTMGR_NRSTWARMMSK_t
;
6316
#endif
/* __ASSEMBLY__ */
6317
6319
#define ALT_RSTMGR_NRSTWARMMSK_RESET 0x00000001
6320
6321
#define ALT_RSTMGR_NRSTWARMMSK_OFST 0x54
6322
6359
#define ALT_RSTMGR_L3WARMMSK_L3_LSB 0
6360
6361
#define ALT_RSTMGR_L3WARMMSK_L3_MSB 0
6362
6363
#define ALT_RSTMGR_L3WARMMSK_L3_WIDTH 1
6364
6365
#define ALT_RSTMGR_L3WARMMSK_L3_SET_MSK 0x00000001
6366
6367
#define ALT_RSTMGR_L3WARMMSK_L3_CLR_MSK 0xfffffffe
6368
6369
#define ALT_RSTMGR_L3WARMMSK_L3_RESET 0x1
6370
6371
#define ALT_RSTMGR_L3WARMMSK_L3_GET(value) (((value) & 0x00000001) >> 0)
6372
6373
#define ALT_RSTMGR_L3WARMMSK_L3_SET(value) (((value) << 0) & 0x00000001)
6374
6375
#ifndef __ASSEMBLY__
6376
6386
struct
ALT_RSTMGR_L3WARMMSK_s
6387
{
6388
uint32_t
l3
: 1;
6389
uint32_t : 31;
6390
};
6391
6393
typedef
volatile
struct
ALT_RSTMGR_L3WARMMSK_s
ALT_RSTMGR_L3WARMMSK_t
;
6394
#endif
/* __ASSEMBLY__ */
6395
6397
#define ALT_RSTMGR_L3WARMMSK_RESET 0x00000001
6398
6399
#define ALT_RSTMGR_L3WARMMSK_OFST 0x58
6400
6424
#define ALT_RSTMGR_TSTSTA_WARMRSTST_LSB 0
6425
6426
#define ALT_RSTMGR_TSTSTA_WARMRSTST_MSB 3
6427
6428
#define ALT_RSTMGR_TSTSTA_WARMRSTST_WIDTH 4
6429
6430
#define ALT_RSTMGR_TSTSTA_WARMRSTST_SET_MSK 0x0000000f
6431
6432
#define ALT_RSTMGR_TSTSTA_WARMRSTST_CLR_MSK 0xfffffff0
6433
6434
#define ALT_RSTMGR_TSTSTA_WARMRSTST_RESET 0x0
6435
6436
#define ALT_RSTMGR_TSTSTA_WARMRSTST_GET(value) (((value) & 0x0000000f) >> 0)
6437
6438
#define ALT_RSTMGR_TSTSTA_WARMRSTST_SET(value) (((value) << 0) & 0x0000000f)
6439
6449
#define ALT_RSTMGR_TSTSTA_DBGRSTST_LSB 4
6450
6451
#define ALT_RSTMGR_TSTSTA_DBGRSTST_MSB 6
6452
6453
#define ALT_RSTMGR_TSTSTA_DBGRSTST_WIDTH 3
6454
6455
#define ALT_RSTMGR_TSTSTA_DBGRSTST_SET_MSK 0x00000070
6456
6457
#define ALT_RSTMGR_TSTSTA_DBGRSTST_CLR_MSK 0xffffff8f
6458
6459
#define ALT_RSTMGR_TSTSTA_DBGRSTST_RESET 0x0
6460
6461
#define ALT_RSTMGR_TSTSTA_DBGRSTST_GET(value) (((value) & 0x00000070) >> 4)
6462
6463
#define ALT_RSTMGR_TSTSTA_DBGRSTST_SET(value) (((value) << 4) & 0x00000070)
6464
6465
#ifndef __ASSEMBLY__
6466
6476
struct
ALT_RSTMGR_TSTSTA_s
6477
{
6478
const
uint32_t
warmrstst
: 4;
6479
const
uint32_t
dbgrstst
: 3;
6480
uint32_t : 25;
6481
};
6482
6484
typedef
volatile
struct
ALT_RSTMGR_TSTSTA_s
ALT_RSTMGR_TSTSTA_t
;
6485
#endif
/* __ASSEMBLY__ */
6486
6488
#define ALT_RSTMGR_TSTSTA_RESET 0x00000000
6489
6490
#define ALT_RSTMGR_TSTSTA_OFST 0x5c
6491
6513
#define ALT_RSTMGR_TSTSCRATCH_FLD0_LSB 0
6514
6515
#define ALT_RSTMGR_TSTSCRATCH_FLD0_MSB 31
6516
6517
#define ALT_RSTMGR_TSTSCRATCH_FLD0_WIDTH 32
6518
6519
#define ALT_RSTMGR_TSTSCRATCH_FLD0_SET_MSK 0xffffffff
6520
6521
#define ALT_RSTMGR_TSTSCRATCH_FLD0_CLR_MSK 0x00000000
6522
6523
#define ALT_RSTMGR_TSTSCRATCH_FLD0_RESET 0x0
6524
6525
#define ALT_RSTMGR_TSTSCRATCH_FLD0_GET(value) (((value) & 0xffffffff) >> 0)
6526
6527
#define ALT_RSTMGR_TSTSCRATCH_FLD0_SET(value) (((value) << 0) & 0xffffffff)
6528
6529
#ifndef __ASSEMBLY__
6530
6540
struct
ALT_RSTMGR_TSTSCRATCH_s
6541
{
6542
uint32_t
fld0
: 32;
6543
};
6544
6546
typedef
volatile
struct
ALT_RSTMGR_TSTSCRATCH_s
ALT_RSTMGR_TSTSCRATCH_t
;
6547
#endif
/* __ASSEMBLY__ */
6548
6550
#define ALT_RSTMGR_TSTSCRATCH_RESET 0x00000000
6551
6552
#define ALT_RSTMGR_TSTSCRATCH_OFST 0x60
6553
6580
#define ALT_RSTMGR_HDSKTMO_VAL_LSB 0
6581
6582
#define ALT_RSTMGR_HDSKTMO_VAL_MSB 24
6583
6584
#define ALT_RSTMGR_HDSKTMO_VAL_WIDTH 25
6585
6586
#define ALT_RSTMGR_HDSKTMO_VAL_SET_MSK 0x01ffffff
6587
6588
#define ALT_RSTMGR_HDSKTMO_VAL_CLR_MSK 0xfe000000
6589
6590
#define ALT_RSTMGR_HDSKTMO_VAL_RESET 0x2800
6591
6592
#define ALT_RSTMGR_HDSKTMO_VAL_GET(value) (((value) & 0x01ffffff) >> 0)
6593
6594
#define ALT_RSTMGR_HDSKTMO_VAL_SET(value) (((value) << 0) & 0x01ffffff)
6595
6596
#ifndef __ASSEMBLY__
6597
6607
struct
ALT_RSTMGR_HDSKTMO_s
6608
{
6609
uint32_t
val
: 25;
6610
uint32_t : 7;
6611
};
6612
6614
typedef
volatile
struct
ALT_RSTMGR_HDSKTMO_s
ALT_RSTMGR_HDSKTMO_t
;
6615
#endif
/* __ASSEMBLY__ */
6616
6618
#define ALT_RSTMGR_HDSKTMO_RESET 0x00002800
6619
6620
#define ALT_RSTMGR_HDSKTMO_OFST 0x64
6621
6644
#define ALT_RSTMGR_HMCINTR_INTR_LSB 0
6645
6646
#define ALT_RSTMGR_HMCINTR_INTR_MSB 0
6647
6648
#define ALT_RSTMGR_HMCINTR_INTR_WIDTH 1
6649
6650
#define ALT_RSTMGR_HMCINTR_INTR_SET_MSK 0x00000001
6651
6652
#define ALT_RSTMGR_HMCINTR_INTR_CLR_MSK 0xfffffffe
6653
6654
#define ALT_RSTMGR_HMCINTR_INTR_RESET 0x0
6655
6656
#define ALT_RSTMGR_HMCINTR_INTR_GET(value) (((value) & 0x00000001) >> 0)
6657
6658
#define ALT_RSTMGR_HMCINTR_INTR_SET(value) (((value) << 0) & 0x00000001)
6659
6660
#ifndef __ASSEMBLY__
6661
6671
struct
ALT_RSTMGR_HMCINTR_s
6672
{
6673
uint32_t
intr
: 1;
6674
uint32_t : 31;
6675
};
6676
6678
typedef
volatile
struct
ALT_RSTMGR_HMCINTR_s
ALT_RSTMGR_HMCINTR_t
;
6679
#endif
/* __ASSEMBLY__ */
6680
6682
#define ALT_RSTMGR_HMCINTR_RESET 0x00000000
6683
6684
#define ALT_RSTMGR_HMCINTR_OFST 0x68
6685
6708
#define ALT_RSTMGR_HMCINTREN_EN_LSB 0
6709
6710
#define ALT_RSTMGR_HMCINTREN_EN_MSB 0
6711
6712
#define ALT_RSTMGR_HMCINTREN_EN_WIDTH 1
6713
6714
#define ALT_RSTMGR_HMCINTREN_EN_SET_MSK 0x00000001
6715
6716
#define ALT_RSTMGR_HMCINTREN_EN_CLR_MSK 0xfffffffe
6717
6718
#define ALT_RSTMGR_HMCINTREN_EN_RESET 0x0
6719
6720
#define ALT_RSTMGR_HMCINTREN_EN_GET(value) (((value) & 0x00000001) >> 0)
6721
6722
#define ALT_RSTMGR_HMCINTREN_EN_SET(value) (((value) << 0) & 0x00000001)
6723
6724
#ifndef __ASSEMBLY__
6725
6735
struct
ALT_RSTMGR_HMCINTREN_s
6736
{
6737
uint32_t
en
: 1;
6738
uint32_t : 31;
6739
};
6740
6742
typedef
volatile
struct
ALT_RSTMGR_HMCINTREN_s
ALT_RSTMGR_HMCINTREN_t
;
6743
#endif
/* __ASSEMBLY__ */
6744
6746
#define ALT_RSTMGR_HMCINTREN_RESET 0x00000000
6747
6748
#define ALT_RSTMGR_HMCINTREN_OFST 0x6c
6749
6772
#define ALT_RSTMGR_HMCINTRENS_EN_LSB 0
6773
6774
#define ALT_RSTMGR_HMCINTRENS_EN_MSB 0
6775
6776
#define ALT_RSTMGR_HMCINTRENS_EN_WIDTH 1
6777
6778
#define ALT_RSTMGR_HMCINTRENS_EN_SET_MSK 0x00000001
6779
6780
#define ALT_RSTMGR_HMCINTRENS_EN_CLR_MSK 0xfffffffe
6781
6782
#define ALT_RSTMGR_HMCINTRENS_EN_RESET 0x0
6783
6784
#define ALT_RSTMGR_HMCINTRENS_EN_GET(value) (((value) & 0x00000001) >> 0)
6785
6786
#define ALT_RSTMGR_HMCINTRENS_EN_SET(value) (((value) << 0) & 0x00000001)
6787
6788
#ifndef __ASSEMBLY__
6789
6799
struct
ALT_RSTMGR_HMCINTRENS_s
6800
{
6801
uint32_t
en
: 1;
6802
uint32_t : 31;
6803
};
6804
6806
typedef
volatile
struct
ALT_RSTMGR_HMCINTRENS_s
ALT_RSTMGR_HMCINTRENS_t
;
6807
#endif
/* __ASSEMBLY__ */
6808
6810
#define ALT_RSTMGR_HMCINTRENS_RESET 0x00000000
6811
6812
#define ALT_RSTMGR_HMCINTRENS_OFST 0x70
6813
6836
#define ALT_RSTMGR_HMCINTRENR_EN_LSB 0
6837
6838
#define ALT_RSTMGR_HMCINTRENR_EN_MSB 0
6839
6840
#define ALT_RSTMGR_HMCINTRENR_EN_WIDTH 1
6841
6842
#define ALT_RSTMGR_HMCINTRENR_EN_SET_MSK 0x00000001
6843
6844
#define ALT_RSTMGR_HMCINTRENR_EN_CLR_MSK 0xfffffffe
6845
6846
#define ALT_RSTMGR_HMCINTRENR_EN_RESET 0x0
6847
6848
#define ALT_RSTMGR_HMCINTRENR_EN_GET(value) (((value) & 0x00000001) >> 0)
6849
6850
#define ALT_RSTMGR_HMCINTRENR_EN_SET(value) (((value) << 0) & 0x00000001)
6851
6852
#ifndef __ASSEMBLY__
6853
6863
struct
ALT_RSTMGR_HMCINTRENR_s
6864
{
6865
uint32_t
en
: 1;
6866
uint32_t : 31;
6867
};
6868
6870
typedef
volatile
struct
ALT_RSTMGR_HMCINTRENR_s
ALT_RSTMGR_HMCINTRENR_t
;
6871
#endif
/* __ASSEMBLY__ */
6872
6874
#define ALT_RSTMGR_HMCINTRENR_RESET 0x00000000
6875
6876
#define ALT_RSTMGR_HMCINTRENR_OFST 0x74
6877
6900
#define ALT_RSTMGR_HMCGPOUT_OUT_LSB 0
6901
6902
#define ALT_RSTMGR_HMCGPOUT_OUT_MSB 7
6903
6904
#define ALT_RSTMGR_HMCGPOUT_OUT_WIDTH 8
6905
6906
#define ALT_RSTMGR_HMCGPOUT_OUT_SET_MSK 0x000000ff
6907
6908
#define ALT_RSTMGR_HMCGPOUT_OUT_CLR_MSK 0xffffff00
6909
6910
#define ALT_RSTMGR_HMCGPOUT_OUT_RESET 0x0
6911
6912
#define ALT_RSTMGR_HMCGPOUT_OUT_GET(value) (((value) & 0x000000ff) >> 0)
6913
6914
#define ALT_RSTMGR_HMCGPOUT_OUT_SET(value) (((value) << 0) & 0x000000ff)
6915
6916
#ifndef __ASSEMBLY__
6917
6927
struct
ALT_RSTMGR_HMCGPOUT_s
6928
{
6929
uint32_t
out
: 8;
6930
uint32_t : 24;
6931
};
6932
6934
typedef
volatile
struct
ALT_RSTMGR_HMCGPOUT_s
ALT_RSTMGR_HMCGPOUT_t
;
6935
#endif
/* __ASSEMBLY__ */
6936
6938
#define ALT_RSTMGR_HMCGPOUT_RESET 0x00000000
6939
6940
#define ALT_RSTMGR_HMCGPOUT_OFST 0x78
6941
6964
#define ALT_RSTMGR_HMCGPIN_IN_LSB 0
6965
6966
#define ALT_RSTMGR_HMCGPIN_IN_MSB 7
6967
6968
#define ALT_RSTMGR_HMCGPIN_IN_WIDTH 8
6969
6970
#define ALT_RSTMGR_HMCGPIN_IN_SET_MSK 0x000000ff
6971
6972
#define ALT_RSTMGR_HMCGPIN_IN_CLR_MSK 0xffffff00
6973
6974
#define ALT_RSTMGR_HMCGPIN_IN_RESET 0x0
6975
6976
#define ALT_RSTMGR_HMCGPIN_IN_GET(value) (((value) & 0x000000ff) >> 0)
6977
6978
#define ALT_RSTMGR_HMCGPIN_IN_SET(value) (((value) << 0) & 0x000000ff)
6979
6980
#ifndef __ASSEMBLY__
6981
6991
struct
ALT_RSTMGR_HMCGPIN_s
6992
{
6993
const
uint32_t
in
: 8;
6994
uint32_t : 24;
6995
};
6996
6998
typedef
volatile
struct
ALT_RSTMGR_HMCGPIN_s
ALT_RSTMGR_HMCGPIN_t
;
6999
#endif
/* __ASSEMBLY__ */
7000
7002
#define ALT_RSTMGR_HMCGPIN_RESET 0x00000000
7003
7004
#define ALT_RSTMGR_HMCGPIN_OFST 0x7c
7005
7006
#ifndef __ASSEMBLY__
7007
7017
struct
ALT_RSTMGR_s
7018
{
7019
volatile
ALT_RSTMGR_STAT_t
stat
;
7020
volatile
ALT_RSTMGR_RAMSTAT_t
ramstat
;
7021
volatile
ALT_RSTMGR_MISCSTAT_t
miscstat
;
7022
volatile
ALT_RSTMGR_CTL_t
ctrl
;
7023
volatile
ALT_RSTMGR_HDSKEN_t
hdsken
;
7024
volatile
ALT_RSTMGR_HDSKREQ_t
hdskreq
;
7025
volatile
ALT_RSTMGR_HDSKACK_t
hdskack
;
7026
volatile
ALT_RSTMGR_COUNTS_t
counts
;
7027
volatile
ALT_RSTMGR_MPUMODRST_t
mpumodrst
;
7028
volatile
ALT_RSTMGR_PER0MODRST_t
per0modrst
;
7029
volatile
ALT_RSTMGR_PER1MODRST_t
per1modrst
;
7030
volatile
ALT_RSTMGR_BRGMODRST_t
brgmodrst
;
7031
volatile
ALT_RSTMGR_SYSMODRST_t
sysmodrst
;
7032
volatile
ALT_RSTMGR_COLDMODRST_t
coldmodrst
;
7033
volatile
ALT_RSTMGR_NRSTMODRST_t
nrstmodrst
;
7034
volatile
ALT_RSTMGR_DBGMODRST_t
dbgmodrst
;
7035
volatile
ALT_RSTMGR_MPUWARMMSK_t
mpuwarmmask
;
7036
volatile
ALT_RSTMGR_PER0WARMMSK_t
per0warmmask
;
7037
volatile
ALT_RSTMGR_PER1WARMMSK_t
per1warmmask
;
7038
volatile
ALT_RSTMGR_BRGWARMMSK_t
brgwarmmask
;
7039
volatile
ALT_RSTMGR_SYSWARMMSK_t
syswarmmask
;
7040
volatile
ALT_RSTMGR_NRSTWARMMSK_t
nrstwarmmask
;
7041
volatile
ALT_RSTMGR_L3WARMMSK_t
l3warmmask
;
7042
volatile
ALT_RSTMGR_TSTSTA_t
tststa
;
7043
volatile
ALT_RSTMGR_TSTSCRATCH_t
tstscratch
;
7044
volatile
ALT_RSTMGR_HDSKTMO_t
hdsktimeout
;
7045
volatile
ALT_RSTMGR_HMCINTR_t
hmcintr
;
7046
volatile
ALT_RSTMGR_HMCINTREN_t
hmcintren
;
7047
volatile
ALT_RSTMGR_HMCINTRENS_t
hmcintrens
;
7048
volatile
ALT_RSTMGR_HMCINTRENR_t
hmcintrenr
;
7049
volatile
ALT_RSTMGR_HMCGPOUT_t
hmcgpout
;
7050
volatile
ALT_RSTMGR_HMCGPIN_t
hmcgpin
;
7051
volatile
uint32_t
_pad_0x80_0x100
[32];
7052
};
7053
7055
typedef
volatile
struct
ALT_RSTMGR_s
ALT_RSTMGR_t
;
7057
struct
ALT_RSTMGR_raw_s
7058
{
7059
volatile
uint32_t
stat
;
7060
volatile
uint32_t
ramstat
;
7061
volatile
uint32_t
miscstat
;
7062
volatile
uint32_t
ctrl
;
7063
volatile
uint32_t
hdsken
;
7064
volatile
uint32_t
hdskreq
;
7065
volatile
uint32_t
hdskack
;
7066
volatile
uint32_t
counts
;
7067
volatile
uint32_t
mpumodrst
;
7068
volatile
uint32_t
per0modrst
;
7069
volatile
uint32_t
per1modrst
;
7070
volatile
uint32_t
brgmodrst
;
7071
volatile
uint32_t
sysmodrst
;
7072
volatile
uint32_t
coldmodrst
;
7073
volatile
uint32_t
nrstmodrst
;
7074
volatile
uint32_t
dbgmodrst
;
7075
volatile
uint32_t
mpuwarmmask
;
7076
volatile
uint32_t
per0warmmask
;
7077
volatile
uint32_t
per1warmmask
;
7078
volatile
uint32_t
brgwarmmask
;
7079
volatile
uint32_t
syswarmmask
;
7080
volatile
uint32_t
nrstwarmmask
;
7081
volatile
uint32_t
l3warmmask
;
7082
volatile
uint32_t
tststa
;
7083
volatile
uint32_t
tstscratch
;
7084
volatile
uint32_t
hdsktimeout
;
7085
volatile
uint32_t
hmcintr
;
7086
volatile
uint32_t
hmcintren
;
7087
volatile
uint32_t
hmcintrens
;
7088
volatile
uint32_t
hmcintrenr
;
7089
volatile
uint32_t
hmcgpout
;
7090
volatile
uint32_t
hmcgpin
;
7091
volatile
uint32_t
_pad_0x80_0x100
[32];
7092
};
7093
7095
typedef
volatile
struct
ALT_RSTMGR_raw_s
ALT_RSTMGR_raw_t
;
7096
#endif
/* __ASSEMBLY__ */
7097
7099
#ifdef __cplusplus
7100
}
7101
#endif
/* __cplusplus */
7102
#endif
/* __ALT_SOCAL_RSTMGR_H__ */
7103
include
soc_a10
socal
alt_rstmgr.h
Generated on Tue Sep 8 2015 13:33:04 for Altera SoCAL by
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