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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Chip select setup/tWB time
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[4:0] | RW | 0x3 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE |
[11:5] | ??? | Unknown | UNDEFINED |
[17:12] | RW | 0xa | ALT_NAND_CFG_CS_SETUP_CNT_TWB |
[31:18] | ??? | Unknown | UNDEFINED |
Field : value | |
Number of clk_x cycles required for meeting chip select setup time. This register refers to device timing parameter Tcs. The value in this registers reflects the extra setup cycles for chip select before read/write enable signal is set low. The default value is calculated for ONFI Timing mode 0 Tcs = 70ns and maximum clk_x period of 4ns for 1x/5x clock multiple for 20ns cycle time device. Please refer to Figure 3.3 for the relationship between the cs_setup_cnt and rdwr_en_lo_cnt values. Field Access Macros: | |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0) |
#define | ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f) |
Field : twb | |
Number of clk_x cycles required for meeting the tWB time. This register refers to device timing parameter TWB. Field Access Macros: | |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12) |
#define | ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000) |
Data Structures | |
struct | ALT_NAND_CFG_CS_SETUP_CNT_s |
Macros | |
#define | ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003 |
#define | ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220 |
Typedefs | |
typedef struct ALT_NAND_CFG_CS_SETUP_CNT_s | ALT_NAND_CFG_CS_SETUP_CNT_t |
struct ALT_NAND_CFG_CS_SETUP_CNT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_CS_SETUP_CNT.
Data Fields | ||
---|---|---|
uint32_t | value: 5 | ALT_NAND_CFG_CS_SETUP_CNT_VALUE |
uint32_t | __pad0__: 7 | UNDEFINED |
uint32_t | twb: 6 | ALT_NAND_CFG_CS_SETUP_CNT_TWB |
uint32_t | __pad1__: 14 | UNDEFINED |
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5 |
The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f |
The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0 |
The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3 |
The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET | ( | value | ) | (((value) & 0x0000001f) >> 0) |
Extracts the ALT_NAND_CFG_CS_SETUP_CNT_VALUE field value from a register.
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET | ( | value | ) | (((value) << 0) & 0x0000001f) |
Produces a ALT_NAND_CFG_CS_SETUP_CNT_VALUE register field value suitable for setting the register.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6 |
The width in bits of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000 |
The mask used to set the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff |
The mask used to clear the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa |
The reset value of the ALT_NAND_CFG_CS_SETUP_CNT_TWB register field.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET | ( | value | ) | (((value) & 0x0003f000) >> 12) |
Extracts the ALT_NAND_CFG_CS_SETUP_CNT_TWB field value from a register.
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET | ( | value | ) | (((value) << 12) & 0x0003f000) |
Produces a ALT_NAND_CFG_CS_SETUP_CNT_TWB register field value suitable for setting the register.
#define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003 |
The reset value of the ALT_NAND_CFG_CS_SETUP_CNT register.
#define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220 |
The byte offset of the ALT_NAND_CFG_CS_SETUP_CNT register from the beginning of the component.
typedef struct ALT_NAND_CFG_CS_SETUP_CNT_s ALT_NAND_CFG_CS_SETUP_CNT_t |
The typedef declaration for register ALT_NAND_CFG_CS_SETUP_CNT.