Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 14 (Interrupt Register) - Interrupt_Status

Description

The Interrupt Status register identifies the events in the MAC that can generate interrupt. All interrupt events are generated only when the corresponding optional feature is enabled.

Register Layout

Bits Access Reset Description
[0] R 0x0 RGMII or SMII Interrupt Status
[1] R 0x0 PCS Link Status Changed
[2] R 0x0 PCS Auto-Negotiation Complete
[3] ??? 0x0 UNDEFINED
[4] R 0x0 MMC Interrupt Status
[5] R 0x0 MMC Receive Interrupt Status
[6] R 0x0 MMC Transmit Interrupt Status
[7] R 0x0 MMC Receive Checksum Offload Interrupt Status
[8] ??? 0x0 UNDEFINED
[9] R 0x0 Timestamp Interrupt Status
[10] R 0x0 LPI Interrupt Status
[31:11] ??? 0x0 UNDEFINED

Field : RGMII or SMII Interrupt Status - rgsmiiis

This bit is set because of any change in value of the Link Status of RGMII or SMII interface (Bit 3 in Register 54 (SGMII/RGMII/SMII Status Register)). This bit is cleared when you perform a read operation on the SGMII/RGMII/SMII Status Register.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT 0x0 Link No Change
ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT 0x1 Link Change

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB   0
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB   0
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : PCS Link Status Changed - pcslchgis

This bit is set because of any change in Link Status in the TBI, RTBI, or SGMII PHY interface (Bit 2 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation on the AN Status register.

This bit is valid only when you select the SGMII PHY interface during operation.

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB   1
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB   1
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : PCS Auto-Negotiation Complete - pcsancis

This bit is set when the Auto-negotiation is completed in the TBI, RTBI, or SGMII PHY interface (Bit 5 in Register 49 (AN Status Register)). This bit is cleared when you perform a read operation to the AN Status register.

This bit is valid only when you select the SGMII PHY interface during operation.

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB   2
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB   2
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET(value)   (((value) << 2) & 0x00000004)
 

Field : MMC Interrupt Status - mmcis

This bit is set high when any of the Bits [7:5] is set high and cleared only when all of these bits are low.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT 0x0 MMC Interrupt Status Disabled
ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT 0x1 MMC Interrupt Status Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB   4
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB   4
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET(value)   (((value) << 4) & 0x00000010)
 

Field : MMC Receive Interrupt Status - mmcrxis

This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD 0x0 MMC Receive Interrupt Status Disabled
ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END 0x1 MMC Receive Interrupt Status Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB   5
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB   5
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET(value)   (((value) << 5) & 0x00000020)
 

Field : MMC Transmit Interrupt Status - mmctxis

This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT 0x0 MMC Transmit Interrupt Status Disabled
ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT 0x1 MMC Transmit Interrupt Status Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB   6
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB   6
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK   0x00000040
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET(value)   (((value) << 6) & 0x00000040)
 

Field : MMC Receive Checksum Offload Interrupt Status - mmcrxipis

This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all the bits in this interrupt register are cleared.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT 0x0 MMC Receive Checksum Offload Interrupt Status
: Disabled
ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT 0x1 MMC Receive Checksum Offload Interrupt Status
: Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB   7
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB   7
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Timestamp Interrupt Status - tsis

This bit is set when any of the following conditions is true:

  • The system time value equals or exceeds the value specified in the Target Time High and Low registers.
  • There is an overflow in the seconds register.
  • The Auxiliary snapshot trigger is asserted.

This bit is cleared on reading Bit 0 of the Register 458 (Timestamp Status Register).

When set, this bit indicates that the system time value is equal to or exceeds the value specified in the Target Time registers. In this mode, this bit is cleared after the completion of the read of this bit. In all other modes, this bit is reserved.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT 0x0 Timestamp Interrupt Status Disabled
ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT 0x1 Timestamp Interrupt Status Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB   9
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB   9
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET(value)   (((value) << 9) & 0x00000200)
 

Field : LPI Interrupt Status - lpiis

This bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared on reading Bit 0 of Register 12 (LPI Control and Status Register). In all other modes, this bit is reserved.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT 0x0 LPI Interrupt Status Disabled
ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT 0x1 LPI Interrupt Status Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB   10
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB   10
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET(value)   (((value) << 10) & 0x00000400)
 

Data Structures

struct  ALT_EMAC_GMAC_INT_STAT_s
 

Macros

#define ALT_EMAC_GMAC_INT_STAT_OFST   0x38
 
#define ALT_EMAC_GMAC_INT_STAT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_INT_STAT_s 
ALT_EMAC_GMAC_INT_STAT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_INT_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_INT_STAT.

Data Fields
const uint32_t rgsmiiis: 1 RGMII or SMII Interrupt Status
const uint32_t pcslchgis: 1 PCS Link Status Changed
const uint32_t pcsancis: 1 PCS Auto-Negotiation Complete
uint32_t __pad0__: 1 UNDEFINED
const uint32_t mmcis: 1 MMC Interrupt Status
const uint32_t mmcrxis: 1 MMC Receive Interrupt Status
const uint32_t mmctxis: 1 MMC Transmit Interrupt Status
const uint32_t mmcrxipis: 1 MMC Receive Checksum Offload Interrupt Status
uint32_t __pad1__: 1 UNDEFINED
const uint32_t tsis: 1 Timestamp Interrupt Status
const uint32_t lpiis: 1 LPI Interrupt Status
uint32_t __pad2__: 21 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS

Link No Change

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_RGSMIIIS

Link Change

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_INT_STAT_RGSMIIIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_RGSMIIIS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_INT_STAT_RGSMIIIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_INT_STAT_PCSLCHGIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_INT_STAT_PCSANCIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_PCSANCIS_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_INT_STAT_PCSANCIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS

MMC Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCIS

MMC Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_INT_STAT_MMCIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_MMCIS_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_INT_STAT_MMCIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS

MMC Receive Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIS

MMC Receive Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIS_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS

MMC Transmit Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCTXIS

MMC Transmit Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_GMAC_INT_STAT_MMCTXIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_MMCTXIS_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_GMAC_INT_STAT_MMCTXIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS

MMC Receive Checksum Offload Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS

MMC Receive Checksum Offload Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_INT_STAT_MMCRXIPIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS

Timestamp Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_TSIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_TSIS

Timestamp Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_TSIS_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_TSIS register field.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_TSIS register field.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_INT_STAT_TSIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_TSIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_TSIS register field.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_INT_STAT_TSIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_TSIS_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_INT_STAT_TSIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS

LPI Interrupt Status Disabled

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_STAT_LPIIS

LPI Interrupt Status Enabled

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_INT_STAT_LPIIS register field value.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_STAT_LPIIS register field.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_INT_STAT_LPIIS field value from a register.

#define ALT_EMAC_GMAC_INT_STAT_LPIIS_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_INT_STAT_LPIIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_STAT_OFST   0x38

The byte offset of the ALT_EMAC_GMAC_INT_STAT register from the beginning of the component.

#define ALT_EMAC_GMAC_INT_STAT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_STAT_OFST))

The address of the ALT_EMAC_GMAC_INT_STAT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_INT_STAT.