Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gmacgrp_mac_frame_filter

Description

Register 1 (MAC Frame Filter)

The MAC Frame Filter register contains the filter controls for receiving frames. Some of the controls from this register go to the address check block of the MAC, which performs the first level of address filtering. The second level of filtering is performed on the incoming frame, based on other controls such as Pass Bad Frames and Pass Control Frames.

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_PR
[1] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
[2] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
[3] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
[4] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_PM
[5] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
[7:6] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
[8] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
[9] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
[10] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
[15:11] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11
[16] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
[19:17] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17
[20] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
[21] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
[30:22] R 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22
[31] RW 0x0 ALT_EMAC_GMAC_MAC_FRM_FLT_RA

Field : pr

Promiscuous Mode

When this bit is set, the Address Filter module passes all incoming frames regardless of its destination or source address. The SA or DA Filter Fails status bits of the Receive Status Word are always cleared when PR is set.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB   0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB   0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : huc

Hash Unicast

When set, MAC performs destination address filtering of unicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for unicast frames, that is, it compares the DA field with the values programmed in DA registers.

If Hash Filter is not selected during core configuration, this bit is reserved (and RO).

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET(value)   (((value) << 1) & 0x00000002)
 

Field : hmc

Hash Multicast

When set, MAC performs destination address filtering of received multicast frames according to the hash table.

When reset, the MAC performs a perfect destination address filtering for multicast frames, that is, it compares the DA field with the values programmed in DA registers.

If Hash Filter is not selected during core configuration, this bit is reserved (and RO).

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB   2
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB   2
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET(value)   (((value) << 2) & 0x00000004)
 

Field : daif

DA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast frames.

When reset, normal filtering of frames is performed.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB   3
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB   3
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET(value)   (((value) << 3) & 0x00000008)
 

Field : pm

Pass All Multicast

When set, this bit indicates that all received frames with a multicast destination address (first bit in the destination address field is '1') are passed.

When reset, filtering of multicast frame depends on HMC bit.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB   4
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB   4
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET(value)   (((value) << 4) & 0x00000010)
 

Field : dbf

Disable Broadcast Frames

When this bit is set, the AFM module filters all incoming broadcast frames. In addition, it overrides all other filter settings.

When this bit is reset, the AFM module passes all received broadcast frames.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB   5
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB   5
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET(value)   (((value) << 5) & 0x00000020)
 

Field : pcf

Pass Control Frames

These bits control the forwarding of all control frames (including unicast and multicast PAUSE frames).

  • 00: MAC filters all control frames from reaching the application.
  • 01: MAC forwards all control frames except PAUSE control frames to application even if they fail the Address filter.
  • 10: MAC forwards all control frames to application even if they fail the Address Filter.
  • 11: MAC forwards control frames that pass the Address Filter.

The following conditions should be true for the PAUSE control frames processing:

  • Condition 1: The MAC is in the full-duplex mode and flow control is enabled by setting Bit 2 (RFE) of Register 6 (Flow Control Register) to 1.
  • Condition 2: The destination address (DA) of the received frame matches the special multicast address or the MAC Address 0 when Bit 3 (UP) of the Register 6 (Flow Control Register) is set.
  • Condition 3: The Type field of the received frame is 0x8808 and the OPCODE field is 0x0001.

Note:

This field should be set to 01 only when the Condition 1 is true, that is, the MAC is programmed to operate in the full-duplex mode and the RFE bit is enabled. Otherwise, the PAUSE frame filtering may be inconsistent. When Condition 1 is false, the PAUSE frames are considered as generic control frames. Therefore, to pass all control frames (including PAUSE control frames) when the full-duplex mode and flow control is not enabled, you should set the PCF field to 10 or 11 (as required by the application).

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE | 0x1 | ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL | 0x2 | ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS | 0x3 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL   0x2
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS   0x3
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB   6
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB   7
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH   2
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK   0x000000c0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK   0xffffff3f
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET(value)   (((value) & 0x000000c0) >> 6)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET(value)   (((value) << 6) & 0x000000c0)
 

Field : saif

SA Inverse Filtering

When this bit is set, the Address Check block operates in inverse filtering mode for the SA address comparison. The frames whose SA matches the SA registers are marked as failing the SA Address filter.

When this bit is reset, frames whose SA does not match the SA registers are marked as failing the SA Address filter.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB   8
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB   8
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET(value)   (((value) << 8) & 0x00000100)
 

Field : saf

Source Address Filter Enable

When this bit is set, the MAC compares the SA field of the received frames with the values programmed in the enabled SA registers. If the comparison fails, the MAC drops the frame.

When this bit is reset, the MAC forwards the received frame to the application with updated SAF bit of the Rx Status depending on the SA address comparison.

Note: According to the IEEE specification, Bit 47 of the SA is reserved and set to 0. However, in DWC_gmac, the MAC compares all 48 bits. The software driver should take this into consideration while programming the MAC address registers for SA.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB   9
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB   9
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET(value)   (((value) << 9) & 0x00000200)
 

Field : hpf

Hash or Perfect Filter

When this bit is set, it configures the address filter to pass a frame if it matches either the perfect filtering or the hash filtering as set by the HMC or HUC bits.

When this bit is low and the HUC or HMC bit is set, the frame is passed only if it matches the Hash filter. This bit is reserved (and RO) if the Hash filter is not selected during core configuration.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB   10
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB   10
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET(value)   (((value) << 10) & 0x00000400)
 

Field : reserved_15_11

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_LSB   11
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_MSB   15
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_WIDTH   5
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET_MSK   0x0000f800
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_CLR_MSK   0xffff07ff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_GET(value)   (((value) & 0x0000f800) >> 11)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET(value)   (((value) << 11) & 0x0000f800)
 

Field : vtfe

VLAN Tag Filter Enable

When set, this bit enables the MAC to drop VLAN tagged frames that do not match the VLAN Tag comparison.

When reset, the MAC forwards all frames irrespective of the match status of the VLAN Tag.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB   16
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB   16
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET(value)   (((value) << 16) & 0x00010000)
 

Field : reserved_19_17

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_LSB   17
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_MSB   19
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_WIDTH   3
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET_MSK   0x000e0000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_CLR_MSK   0xfff1ffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : ipfe

Layer 3 and Layer 4 Filter Enable

When set, this bit enables the MAC to drop frames that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching, this bit does not have any effect.

When reset, the MAC forwards all frames irrespective of the match status of the Layer 3 and Layer 4 fields.

If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value).

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB   20
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB   20
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET(value)   (((value) << 20) & 0x00100000)
 

Field : dntu

Drop non-TCP/UDP over IP Frames

When set, this bit enables the MAC to drop the non-TCP or UDP over IP frames. The MAC forward only those frames that are processed by the Layer 4 filter.

When reset, this bit enables the MAC to forward all non-TCP or UDP over IP frames.

If the Layer 3 and Layer 4 Filtering feature is not selected during core configuration, this bit is reserved (RO with default value).

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB   21
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB   21
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET(value)   (((value) << 21) & 0x00200000)
 

Field : reserved_30_22

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_LSB   22
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_MSB   30
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_WIDTH   9
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET_MSK   0x7fc00000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_CLR_MSK   0x803fffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_GET(value)   (((value) & 0x7fc00000) >> 22)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET(value)   (((value) << 22) & 0x7fc00000)
 

Field : ra

Receive All

When this bit is set, the MAC Receiver module passes all received frames, irrespective of whether they pass the address filter or not, to the Application. The result of the SA or DA filtering is updated (pass or fail) in the corresponding bits in the Receive Status Word.

When this bit is reset, the Receiver module passes only those frames to the Application that pass the SA or DA address filter.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB   31
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB   31
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK   0x80000000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK   0x7fffffff
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MAC_FRM_FLT_s
 

Macros

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RESET   0x00000000
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST   0x4
 
#define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MAC_FRM_FLT_s 
ALT_EMAC_GMAC_MAC_FRM_FLT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MAC_FRM_FLT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT.

Data Fields
uint32_t pr: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_PR
const uint32_t huc: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_HUC
const uint32_t hmc: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_HMC
uint32_t daif: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF
uint32_t pm: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_PM
uint32_t dbf: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_DBF
uint32_t pcf: 2 ALT_EMAC_GMAC_MAC_FRM_FLT_PCF
uint32_t saif: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF
uint32_t saf: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_SAF
const uint32_t hpf: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_HPF
const uint32_t reserved_15_11: 5 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11
uint32_t vtfe: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE
const uint32_t reserved_19_17: 3 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17
uint32_t ipfe: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE
uint32_t dntu: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU
const uint32_t reserved_30_22: 9 ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22
uint32_t ra: 1 ALT_EMAC_GMAC_MAC_FRM_FLT_RA

Macro Definitions

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PR

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PR field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HUC

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HUC field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HUC_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HUC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HMC

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HMC field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HMC_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HMC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DAIF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PM

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PM field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PM_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DBF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DBF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DBF_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DBF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFLTALLCFR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDXPAUSE   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDFAIL   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_E_MACFWDPASS   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_PCF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET_MSK   0x000000c0

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_CLR_MSK   0xffffff3f

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_GET (   value)    (((value) & 0x000000c0) >> 6)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_PCF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_PCF_SET (   value)    (((value) << 6) & 0x000000c0)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_PCF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAIF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_SAF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_SAF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_SAF_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_SAF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_HPF

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_HPF field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_HPF_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_HPF register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET_MSK   0x0000f800

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_CLR_MSK   0xffff07ff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_GET (   value)    (((value) & 0x0000f800) >> 11)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11_SET (   value)    (((value) << 11) & 0x0000f800)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_15_11 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_NODROP   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_E_DROP   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_VTFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_WIDTH   3

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET_MSK   0x000e0000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_19_17 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_NODROP   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_E_DROP   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_IPFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_NODROP   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_E_DROP   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_DNTU register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_MSB   30

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_WIDTH   9

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET_MSK   0x7fc00000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_CLR_MSK   0x803fffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_GET (   value)    (((value) & 0x7fc00000) >> 22)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22_SET (   value)    (((value) << 22) & 0x7fc00000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RSVD_30_22 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_FRM_FLT_RA

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_LSB   31

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET_MSK   0x80000000

The mask used to set the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_CLR_MSK   0x7fffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_EMAC_GMAC_MAC_FRM_FLT_RA field value from a register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RA_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_EMAC_GMAC_MAC_FRM_FLT_RA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_MAC_FRM_FLT register.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_OFST   0x4

The byte offset of the ALT_EMAC_GMAC_MAC_FRM_FLT register from the beginning of the component.

#define ALT_EMAC_GMAC_MAC_FRM_FLT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_FRM_FLT_OFST))

The address of the ALT_EMAC_GMAC_MAC_FRM_FLT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_MAC_FRM_FLT.