Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gmacgrp_flow_control

Description

Register 6 (Flow Control Register)

The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control module. A Write to a register with the Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
[1] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_TFE
[2] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_RFE
[3] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_UP
[5:4] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_PLT
[6] R 0x0 ALT_EMAC_GMAC_FLOW_CTL_RSVD_6
[7] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_DZPQ
[15:8] R 0x0 ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8
[31:16] RW 0x0 ALT_EMAC_GMAC_FLOW_CTL_PT

Field : fca_bpa

Flow Control Busy or Backpressure Activate

This bit initiates a Pause Control frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set.

In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared.

In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB   0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB   0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value)   (((value) << 0) & 0x00000001)
 

Field : tfe

Transmit Flow Control Enable

In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames.

In half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the back-pressure feature is disabled.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value)   (((value) << 1) & 0x00000002)
 

Field : rfe

Receive Flow Control Enable

When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : up

Unicast Pause Frame Detect

A pause frame is processed when it has the unique multicast address specified in the IEEE Std 802.3. When this bit is set, the MAC can also detect Pause frames with unicast address of the station. This unicast address should be as specified in the MAC Address0 High Register and MAC Address0 Low Register.

When this bit is reset, the MAC only detects Pause frames with unique multicast address.

Note: The MAC does not process a Pause frame if the multicast address of received frame is different from the unique multicast address.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_UP_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB   3
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB   3
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value)   (((value) << 3) & 0x00000008)
 

Field : plt

Pause Low Threshold

This field configures the threshold of the PAUSE timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame.

The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 - 28) slot times after the first PAUSE frame is transmitted.

The following list provides the threshold values for different values:

  • 00: The threshold is Pause time minus 4 slot times (PT - 4 slot times).
  • 01: The threshold is Pause time minus 28 slot times (PT - 28 slot times).
  • 10: The threshold is Pause time minus 144 slot times (PT - 144 slot times).
  • 11: The threshold is Pause time minus 256 slot times (PT - 256 slot times).

The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 | 0x1 | ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 | 0x2 | ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 | 0x3 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144   0x2
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256   0x3
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB   4
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB   5
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK   0x00000030
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK   0xffffffcf
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value)   (((value) << 4) & 0x00000030)
 

Field : reserved_6

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_LSB   6
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_MSB   6
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET_MSK   0x00000040
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET(value)   (((value) << 6) & 0x00000040)
 

Field : dzpq

Disable Zero-Quanta Pause

When this bit is set, it disables the automatic generation of the Zero-Quanta Pause Control frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i).

When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD | 0x0 | ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB   7
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB   7
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value)   (((value) << 7) & 0x00000080)
 

Field : reserved_15_8

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_LSB   8
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_MSB   15
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_WIDTH   8
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET_MSK   0x0000ff00
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_CLR_MSK   0xffff00ff
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_GET(value)   (((value) & 0x0000ff00) >> 8)
 
#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET(value)   (((value) << 8) & 0x0000ff00)
 

Field : pt

Pause Time

This field holds the value to be used in the Pause Time field in the transmit control frame. If the Pause Time bits is configured to be double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB   16
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB   31
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH   16
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK   0xffff0000
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK   0x0000ffff
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_EMAC_GMAC_FLOW_CTL_s
 

Macros

#define ALT_EMAC_GMAC_FLOW_CTL_RESET   0x00000000
 
#define ALT_EMAC_GMAC_FLOW_CTL_OFST   0x18
 
#define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_FLOW_CTL_s 
ALT_EMAC_GMAC_FLOW_CTL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_FLOW_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL.

Data Fields
uint32_t fca_bpa: 1 ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA
uint32_t tfe: 1 ALT_EMAC_GMAC_FLOW_CTL_TFE
uint32_t rfe: 1 ALT_EMAC_GMAC_FLOW_CTL_RFE
uint32_t up: 1 ALT_EMAC_GMAC_FLOW_CTL_UP
uint32_t plt: 2 ALT_EMAC_GMAC_FLOW_CTL_PLT
const uint32_t reserved_6: 1 ALT_EMAC_GMAC_FLOW_CTL_RSVD_6
uint32_t dzpq: 1 ALT_EMAC_GMAC_FLOW_CTL_DZPQ
const uint32_t reserved_15_8: 8 ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8
uint32_t pt: 16 ALT_EMAC_GMAC_FLOW_CTL_PT

Macro Definitions

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP

#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144   0x2

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256   0x3

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK   0x00000030

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK   0xffffffcf

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_6_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_GMAC_FLOW_CTL_RSVD_6 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_WIDTH   8

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET_MSK   0x0000ff00

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_CLR_MSK   0xffff00ff

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_GET (   value)    (((value) & 0x0000ff00) >> 8)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8_SET (   value)    (((value) << 8) & 0x0000ff00)

Produces a ALT_EMAC_GMAC_FLOW_CTL_RSVD_15_8 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH   16

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK   0xffff0000

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK   0x0000ffff

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_FLOW_CTL register.

#define ALT_EMAC_GMAC_FLOW_CTL_OFST   0x18

The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component.

#define ALT_EMAC_GMAC_FLOW_CTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))

The address of the ALT_EMAC_GMAC_FLOW_CTL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL.