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alt_fpgamgr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_FPGAMGR_H__
36
#define __ALT_SOCAL_FPGAMGR_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
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extern
"C"
42
{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_DCLKCNT_CNT_LSB 0
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#define ALT_FPGAMGR_DCLKCNT_CNT_MSB 31
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#define ALT_FPGAMGR_DCLKCNT_CNT_WIDTH 32
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#define ALT_FPGAMGR_DCLKCNT_CNT_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_DCLKCNT_CNT_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_DCLKCNT_CNT_RESET 0x0
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#define ALT_FPGAMGR_DCLKCNT_CNT_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_DCLKCNT_CNT_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
115
125
struct
ALT_FPGAMGR_DCLKCNT_s
126
{
127
uint32_t
cnt
: 32;
128
};
129
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typedef
volatile
struct
ALT_FPGAMGR_DCLKCNT_s
ALT_FPGAMGR_DCLKCNT_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_DCLKCNT_RESET 0x00000000
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#define ALT_FPGAMGR_DCLKCNT_OFST 0x8
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_NOTDONE 0x0
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_E_DONE 0x1
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_LSB 0
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_MSB 0
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_WIDTH 1
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET_MSK 0x00000001
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_CLR_MSK 0xfffffffe
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_RESET 0x0
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_FPGAMGR_DCLKSTAT_DCNTDONE_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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struct
ALT_FPGAMGR_DCLKSTAT_s
213
{
214
uint32_t
dcntdone
: 1;
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uint32_t : 31;
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};
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219
typedef
volatile
struct
ALT_FPGAMGR_DCLKSTAT_s
ALT_FPGAMGR_DCLKSTAT_t
;
220
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_DCLKSTAT_RESET 0x00000000
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#define ALT_FPGAMGR_DCLKSTAT_OFST 0xc
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#define ALT_FPGAMGR_GPO_VALUE_LSB 0
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#define ALT_FPGAMGR_GPO_VALUE_MSB 31
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#define ALT_FPGAMGR_GPO_VALUE_WIDTH 32
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#define ALT_FPGAMGR_GPO_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_GPO_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_GPO_VALUE_RESET 0x0
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#define ALT_FPGAMGR_GPO_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_GPO_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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277
struct
ALT_FPGAMGR_GPO_s
278
{
279
uint32_t
value
: 32;
280
};
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283
typedef
volatile
struct
ALT_FPGAMGR_GPO_s
ALT_FPGAMGR_GPO_t
;
284
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_GPO_RESET 0x00000000
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#define ALT_FPGAMGR_GPO_OFST 0x10
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#define ALT_FPGAMGR_GPI_VALUE_LSB 0
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#define ALT_FPGAMGR_GPI_VALUE_MSB 31
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#define ALT_FPGAMGR_GPI_VALUE_WIDTH 32
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#define ALT_FPGAMGR_GPI_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_GPI_VALUE_CLR_MSK 0x00000000
323
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#define ALT_FPGAMGR_GPI_VALUE_RESET 0x0
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#define ALT_FPGAMGR_GPI_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_GPI_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
331
341
struct
ALT_FPGAMGR_GPI_s
342
{
343
const
uint32_t
value
: 32;
344
};
345
347
typedef
volatile
struct
ALT_FPGAMGR_GPI_s
ALT_FPGAMGR_GPI_t
;
348
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_GPI_RESET 0x00000000
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#define ALT_FPGAMGR_GPI_OFST 0x14
354
384
#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_LSB 0
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_MSB 0
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_WIDTH 1
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET_MSK 0x00000001
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_CLR_MSK 0xfffffffe
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_RESET 0x0
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_FPGAMGR_MISCI_BOOTFPGAFAIL_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_LSB 1
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_MSB 1
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_WIDTH 1
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET_MSK 0x00000002
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_CLR_MSK 0xfffffffd
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_RESET 0x0
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426
#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_FPGAMGR_MISCI_BOOTFPGARDY_SET(value) (((value) << 1) & 0x00000002)
429
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#ifndef __ASSEMBLY__
431
441
struct
ALT_FPGAMGR_MISCI_s
442
{
443
const
uint32_t
bootFPGAfail
: 1;
444
const
uint32_t
bootFPGArdy
: 1;
445
uint32_t : 30;
446
};
447
449
typedef
volatile
struct
ALT_FPGAMGR_MISCI_s
ALT_FPGAMGR_MISCI_t
;
450
#endif
/* __ASSEMBLY__ */
451
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#define ALT_FPGAMGR_MISCI_RESET 0x00000000
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#define ALT_FPGAMGR_MISCI_OFST 0x18
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_LSB 0
479
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_MSB 31
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_WIDTH 32
483
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_RESET 0x0
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_EMR_DATA0_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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struct
ALT_FPGAMGR_EMR_DATA0_s
506
{
507
const
uint32_t
value
: 32;
508
};
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511
typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA0_s
ALT_FPGAMGR_EMR_DATA0_t
;
512
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_EMR_DATA0_RESET 0x00000000
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#define ALT_FPGAMGR_EMR_DATA0_OFST 0x30
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_LSB 0
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_MSB 31
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_WIDTH 32
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_RESET 0x0
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_EMR_DATA1_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
557
567
struct
ALT_FPGAMGR_EMR_DATA1_s
568
{
569
const
uint32_t
value
: 32;
570
};
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typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA1_s
ALT_FPGAMGR_EMR_DATA1_t
;
574
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_EMR_DATA1_RESET 0x00000000
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#define ALT_FPGAMGR_EMR_DATA1_OFST 0x34
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_LSB 0
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_MSB 31
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_WIDTH 32
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_RESET 0x0
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_EMR_DATA2_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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struct
ALT_FPGAMGR_EMR_DATA2_s
630
{
631
const
uint32_t
value
: 32;
632
};
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typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA2_s
ALT_FPGAMGR_EMR_DATA2_t
;
636
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_EMR_DATA2_RESET 0x00000000
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#define ALT_FPGAMGR_EMR_DATA2_OFST 0x38
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_LSB 0
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_MSB 31
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_WIDTH 32
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_RESET 0x0
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_EMR_DATA3_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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struct
ALT_FPGAMGR_EMR_DATA3_s
692
{
693
const
uint32_t
value
: 32;
694
};
695
697
typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA3_s
ALT_FPGAMGR_EMR_DATA3_t
;
698
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_EMR_DATA3_RESET 0x00000000
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#define ALT_FPGAMGR_EMR_DATA3_OFST 0x3c
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_LSB 0
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_MSB 31
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_WIDTH 32
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_SET_MSK 0xffffffff
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_CLR_MSK 0x00000000
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_RESET 0x0
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_FPGAMGR_EMR_DATA4_VALUE_SET(value) (((value) << 0) & 0xffffffff)
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742
#ifndef __ASSEMBLY__
743
753
struct
ALT_FPGAMGR_EMR_DATA4_s
754
{
755
const
uint32_t
value
: 32;
756
};
757
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typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA4_s
ALT_FPGAMGR_EMR_DATA4_t
;
760
#endif
/* __ASSEMBLY__ */
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#define ALT_FPGAMGR_EMR_DATA4_RESET 0x00000000
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#define ALT_FPGAMGR_EMR_DATA4_OFST 0x40
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#define ALT_FPGAMGR_EMR_DATA5_VALUE_LSB 0
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#define ALT_FPGAMGR_EMR_DATA5_VALUE_MSB 31
791
792
#define ALT_FPGAMGR_EMR_DATA5_VALUE_WIDTH 32
793
794
#define ALT_FPGAMGR_EMR_DATA5_VALUE_SET_MSK 0xffffffff
795
796
#define ALT_FPGAMGR_EMR_DATA5_VALUE_CLR_MSK 0x00000000
797
798
#define ALT_FPGAMGR_EMR_DATA5_VALUE_RESET 0x0
799
800
#define ALT_FPGAMGR_EMR_DATA5_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
801
802
#define ALT_FPGAMGR_EMR_DATA5_VALUE_SET(value) (((value) << 0) & 0xffffffff)
803
804
#ifndef __ASSEMBLY__
805
815
struct
ALT_FPGAMGR_EMR_DATA5_s
816
{
817
const
uint32_t
value
: 32;
818
};
819
821
typedef
volatile
struct
ALT_FPGAMGR_EMR_DATA5_s
ALT_FPGAMGR_EMR_DATA5_t
;
822
#endif
/* __ASSEMBLY__ */
823
825
#define ALT_FPGAMGR_EMR_DATA5_RESET 0x00000000
826
827
#define ALT_FPGAMGR_EMR_DATA5_OFST 0x44
828
847
#define ALT_FPGAMGR_EMR_VALID_VLD_LSB 0
848
849
#define ALT_FPGAMGR_EMR_VALID_VLD_MSB 0
850
851
#define ALT_FPGAMGR_EMR_VALID_VLD_WIDTH 1
852
853
#define ALT_FPGAMGR_EMR_VALID_VLD_SET_MSK 0x00000001
854
855
#define ALT_FPGAMGR_EMR_VALID_VLD_CLR_MSK 0xfffffffe
856
857
#define ALT_FPGAMGR_EMR_VALID_VLD_RESET 0x0
858
859
#define ALT_FPGAMGR_EMR_VALID_VLD_GET(value) (((value) & 0x00000001) >> 0)
860
861
#define ALT_FPGAMGR_EMR_VALID_VLD_SET(value) (((value) << 0) & 0x00000001)
862
863
#ifndef __ASSEMBLY__
864
874
struct
ALT_FPGAMGR_EMR_VALID_s
875
{
876
uint32_t
vld
: 1;
877
uint32_t : 31;
878
};
879
881
typedef
volatile
struct
ALT_FPGAMGR_EMR_VALID_s
ALT_FPGAMGR_EMR_VALID_t
;
882
#endif
/* __ASSEMBLY__ */
883
885
#define ALT_FPGAMGR_EMR_VALID_RESET 0x00000000
886
887
#define ALT_FPGAMGR_EMR_VALID_OFST 0x48
888
909
#define ALT_FPGAMGR_EMR_EN_EN_LSB 0
910
911
#define ALT_FPGAMGR_EMR_EN_EN_MSB 0
912
913
#define ALT_FPGAMGR_EMR_EN_EN_WIDTH 1
914
915
#define ALT_FPGAMGR_EMR_EN_EN_SET_MSK 0x00000001
916
917
#define ALT_FPGAMGR_EMR_EN_EN_CLR_MSK 0xfffffffe
918
919
#define ALT_FPGAMGR_EMR_EN_EN_RESET 0x0
920
921
#define ALT_FPGAMGR_EMR_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
922
923
#define ALT_FPGAMGR_EMR_EN_EN_SET(value) (((value) << 0) & 0x00000001)
924
925
#ifndef __ASSEMBLY__
926
936
struct
ALT_FPGAMGR_EMR_EN_s
937
{
938
uint32_t
en
: 1;
939
uint32_t : 31;
940
};
941
943
typedef
volatile
struct
ALT_FPGAMGR_EMR_EN_s
ALT_FPGAMGR_EMR_EN_t
;
944
#endif
/* __ASSEMBLY__ */
945
947
#define ALT_FPGAMGR_EMR_EN_RESET 0x77000000
948
949
#define ALT_FPGAMGR_EMR_EN_OFST 0x4c
950
998
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_DIS 0x0
999
1004
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_E_EN 0x1
1005
1007
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_LSB 0
1008
1009
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_MSB 0
1010
1011
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_WIDTH 1
1012
1013
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET_MSK 0x00000001
1014
1015
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_CLR_MSK 0xfffffffe
1016
1017
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_RESET 0x0
1018
1019
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_GET(value) (((value) & 0x00000001) >> 0)
1020
1021
#define ALT_FPGAMGR_JTAG_CFG_JTAGHOSTEN_SET(value) (((value) << 0) & 0x00000001)
1022
1046
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_DIS 0x0
1047
1052
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_E_EN 0x1
1053
1055
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_LSB 1
1056
1057
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_MSB 1
1058
1059
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_WIDTH 1
1060
1061
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET_MSK 0x00000002
1062
1063
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_CLR_MSK 0xfffffffd
1064
1065
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_RESET 0x0
1066
1067
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_GET(value) (((value) & 0x00000002) >> 1)
1068
1069
#define ALT_FPGAMGR_JTAG_CFG_JTAGPORTEN_SET(value) (((value) << 1) & 0x00000002)
1070
1094
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_DIS 0x0
1095
1100
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_E_EN 0x1
1101
1103
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_LSB 2
1104
1105
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_MSB 2
1106
1107
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_WIDTH 1
1108
1109
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET_MSK 0x00000004
1110
1111
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_CLR_MSK 0xfffffffb
1112
1113
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_RESET 0x0
1114
1115
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_GET(value) (((value) & 0x00000004) >> 2)
1116
1117
#define ALT_FPGAMGR_JTAG_CFG_LOOPBACKEN_SET(value) (((value) << 2) & 0x00000004)
1118
1133
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_LSB 4
1134
1135
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_MSB 4
1136
1137
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_WIDTH 1
1138
1139
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET_MSK 0x00000010
1140
1141
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_CLR_MSK 0xffffffef
1142
1143
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_RESET 0x0
1144
1145
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_GET(value) (((value) & 0x00000010) >> 4)
1146
1147
#define ALT_FPGAMGR_JTAG_CFG_TRSTEN_SET(value) (((value) << 4) & 0x00000010)
1148
1166
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_LSB 8
1167
1168
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_MSB 15
1169
1170
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_WIDTH 8
1171
1172
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET_MSK 0x0000ff00
1173
1174
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_CLR_MSK 0xffff00ff
1175
1176
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_RESET 0x14
1177
1178
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_GET(value) (((value) & 0x0000ff00) >> 8)
1179
1180
#define ALT_FPGAMGR_JTAG_CFG_TCKRATIO_SET(value) (((value) << 8) & 0x0000ff00)
1181
1211
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_LSB 16
1212
1213
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_MSB 31
1214
1215
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_WIDTH 16
1216
1217
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET_MSK 0xffff0000
1218
1219
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_CLR_MSK 0x0000ffff
1220
1221
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_RESET 0x0
1222
1223
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_GET(value) (((value) & 0xffff0000) >> 16)
1224
1225
#define ALT_FPGAMGR_JTAG_CFG_TXSIZE_SET(value) (((value) << 16) & 0xffff0000)
1226
1227
#ifndef __ASSEMBLY__
1228
1238
struct
ALT_FPGAMGR_JTAG_CFG_s
1239
{
1240
uint32_t
JtagHostEn
: 1;
1241
uint32_t
jtagPortEn
: 1;
1242
uint32_t
loopBackEn
: 1;
1243
uint32_t : 1;
1244
uint32_t
trstEn
: 1;
1245
uint32_t : 3;
1246
uint32_t
tckRatio
: 8;
1247
uint32_t
txSize
: 16;
1248
};
1249
1251
typedef
volatile
struct
ALT_FPGAMGR_JTAG_CFG_s
ALT_FPGAMGR_JTAG_CFG_t
;
1252
#endif
/* __ASSEMBLY__ */
1253
1255
#define ALT_FPGAMGR_JTAG_CFG_RESET 0x00001400
1256
1257
#define ALT_FPGAMGR_JTAG_CFG_OFST 0x50
1258
1290
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_LSB 0
1291
1292
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_MSB 3
1293
1294
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_WIDTH 4
1295
1296
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET_MSK 0x0000000f
1297
1298
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_CLR_MSK 0xfffffff0
1299
1300
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_RESET 0x0
1301
1302
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_GET(value) (((value) & 0x0000000f) >> 0)
1303
1304
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOLEVEL_SET(value) (((value) << 0) & 0x0000000f)
1305
1317
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_LSB 4
1318
1319
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_MSB 7
1320
1321
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_WIDTH 4
1322
1323
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET_MSK 0x000000f0
1324
1325
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_CLR_MSK 0xffffff0f
1326
1327
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_RESET 0x0
1328
1329
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_GET(value) (((value) & 0x000000f0) >> 4)
1330
1331
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOLEVEL_SET(value) (((value) << 4) & 0x000000f0)
1332
1346
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_LSB 8
1347
1348
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_MSB 8
1349
1350
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_WIDTH 1
1351
1352
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET_MSK 0x00000100
1353
1354
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_CLR_MSK 0xfffffeff
1355
1356
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_RESET 0x1
1357
1358
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_GET(value) (((value) & 0x00000100) >> 8)
1359
1360
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOEMPTY_SET(value) (((value) << 8) & 0x00000100)
1361
1375
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_LSB 9
1376
1377
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_MSB 9
1378
1379
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_WIDTH 1
1380
1381
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET_MSK 0x00000200
1382
1383
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_CLR_MSK 0xfffffdff
1384
1385
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_RESET 0x0
1386
1387
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_GET(value) (((value) & 0x00000200) >> 9)
1388
1389
#define ALT_FPGAMGR_JTAG_STAT_TXFIFOFULL_SET(value) (((value) << 9) & 0x00000200)
1390
1404
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_LSB 10
1405
1406
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_MSB 10
1407
1408
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_WIDTH 1
1409
1410
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET_MSK 0x00000400
1411
1412
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_CLR_MSK 0xfffffbff
1413
1414
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_RESET 0x1
1415
1416
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_GET(value) (((value) & 0x00000400) >> 10)
1417
1418
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOEMPTY_SET(value) (((value) << 10) & 0x00000400)
1419
1433
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_LSB 11
1434
1435
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_MSB 11
1436
1437
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_WIDTH 1
1438
1439
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET_MSK 0x00000800
1440
1441
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_CLR_MSK 0xfffff7ff
1442
1443
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_RESET 0x0
1444
1445
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_GET(value) (((value) & 0x00000800) >> 11)
1446
1447
#define ALT_FPGAMGR_JTAG_STAT_RXFIFOFULL_SET(value) (((value) << 11) & 0x00000800)
1448
1471
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_DIS 0x0
1472
1477
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_E_EN 0x1
1478
1480
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_LSB 15
1481
1482
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_MSB 15
1483
1484
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_WIDTH 1
1485
1486
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET_MSK 0x00008000
1487
1488
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_CLR_MSK 0xffff7fff
1489
1490
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_RESET 0x0
1491
1492
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_GET(value) (((value) & 0x00008000) >> 15)
1493
1494
#define ALT_FPGAMGR_JTAG_STAT_SESSIONSTAT_SET(value) (((value) << 15) & 0x00008000)
1495
1514
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_LSB 16
1515
1516
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_MSB 31
1517
1518
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_WIDTH 16
1519
1520
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET_MSK 0xffff0000
1521
1522
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_CLR_MSK 0x0000ffff
1523
1524
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_RESET 0x0
1525
1526
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_GET(value) (((value) & 0xffff0000) >> 16)
1527
1528
#define ALT_FPGAMGR_JTAG_STAT_TXDONESIZE_SET(value) (((value) << 16) & 0xffff0000)
1529
1530
#ifndef __ASSEMBLY__
1531
1541
struct
ALT_FPGAMGR_JTAG_STAT_s
1542
{
1543
uint32_t
txFifoLevel
: 4;
1544
uint32_t
rxFifoLevel
: 4;
1545
uint32_t
txFifoEmpty
: 1;
1546
uint32_t
txFifoFull
: 1;
1547
uint32_t
rxFifoEmpty
: 1;
1548
uint32_t
rxFifoFull
: 1;
1549
uint32_t : 3;
1550
uint32_t
SessionStatus
: 1;
1551
uint32_t
txDoneSize
: 16;
1552
};
1553
1555
typedef
volatile
struct
ALT_FPGAMGR_JTAG_STAT_s
ALT_FPGAMGR_JTAG_STAT_t
;
1556
#endif
/* __ASSEMBLY__ */
1557
1559
#define ALT_FPGAMGR_JTAG_STAT_RESET 0x00000500
1560
1561
#define ALT_FPGAMGR_JTAG_STAT_OFST 0x54
1562
1594
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_LSB 0
1595
1596
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_MSB 0
1597
1598
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_WIDTH 1
1599
1600
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET_MSK 0x00000001
1601
1602
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_CLR_MSK 0xfffffffe
1603
1604
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_RESET 0x0
1605
1606
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_GET(value) (((value) & 0x00000001) >> 0)
1607
1608
#define ALT_FPGAMGR_JTAG_KICK_STARTSESSION_SET(value) (((value) << 0) & 0x00000001)
1609
1624
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_LSB 1
1625
1626
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_MSB 1
1627
1628
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_WIDTH 1
1629
1630
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET_MSK 0x00000002
1631
1632
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_CLR_MSK 0xfffffffd
1633
1634
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_RESET 0x0
1635
1636
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_GET(value) (((value) & 0x00000002) >> 1)
1637
1638
#define ALT_FPGAMGR_JTAG_KICK_STOPSESSION_SET(value) (((value) << 1) & 0x00000002)
1639
1649
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_LSB 2
1650
1651
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_MSB 2
1652
1653
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_WIDTH 1
1654
1655
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET_MSK 0x00000004
1656
1657
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_CLR_MSK 0xfffffffb
1658
1659
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_RESET 0x0
1660
1661
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_GET(value) (((value) & 0x00000004) >> 2)
1662
1663
#define ALT_FPGAMGR_JTAG_KICK_CLRTXFIFO_SET(value) (((value) << 2) & 0x00000004)
1664
1674
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_LSB 3
1675
1676
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_MSB 3
1677
1678
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_WIDTH 1
1679
1680
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET_MSK 0x00000008
1681
1682
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_CLR_MSK 0xfffffff7
1683
1684
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_RESET 0x0
1685
1686
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_GET(value) (((value) & 0x00000008) >> 3)
1687
1688
#define ALT_FPGAMGR_JTAG_KICK_CLRRXFIFO_SET(value) (((value) << 3) & 0x00000008)
1689
1690
#ifndef __ASSEMBLY__
1691
1701
struct
ALT_FPGAMGR_JTAG_KICK_s
1702
{
1703
uint32_t
startSession
: 1;
1704
uint32_t
stopSession
: 1;
1705
uint32_t
clearTxFifo
: 1;
1706
uint32_t
clearRxFifo
: 1;
1707
uint32_t : 28;
1708
};
1709
1711
typedef
volatile
struct
ALT_FPGAMGR_JTAG_KICK_s
ALT_FPGAMGR_JTAG_KICK_t
;
1712
#endif
/* __ASSEMBLY__ */
1713
1715
#define ALT_FPGAMGR_JTAG_KICK_RESET 0x00000000
1716
1717
#define ALT_FPGAMGR_JTAG_KICK_OFST 0x58
1718
1758
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_LSB 0
1759
1760
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_MSB 15
1761
1762
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_WIDTH 16
1763
1764
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET_MSK 0x0000ffff
1765
1766
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_CLR_MSK 0xffff0000
1767
1768
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_RESET 0x0
1769
1770
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1771
1772
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1773
1783
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_LSB 16
1784
1785
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_MSB 31
1786
1787
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_WIDTH 16
1788
1789
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET_MSK 0xffff0000
1790
1791
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_CLR_MSK 0x0000ffff
1792
1793
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_RESET 0x0
1794
1795
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_GET(value) (((value) & 0xffff0000) >> 16)
1796
1797
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET(value) (((value) << 16) & 0xffff0000)
1798
1799
#ifndef __ASSEMBLY__
1800
1810
struct
ALT_FPGAMGR_JTAG_DATA_W_s
1811
{
1812
uint32_t
tdiData
: 16;
1813
uint32_t
tmsData
: 16;
1814
};
1815
1817
typedef
volatile
struct
ALT_FPGAMGR_JTAG_DATA_W_s
ALT_FPGAMGR_JTAG_DATA_W_t
;
1818
#endif
/* __ASSEMBLY__ */
1819
1821
#define ALT_FPGAMGR_JTAG_DATA_W_RESET 0x00000000
1822
1823
#define ALT_FPGAMGR_JTAG_DATA_W_OFST 0x60
1824
1862
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_LSB 0
1863
1864
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_MSB 15
1865
1866
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_WIDTH 16
1867
1868
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET_MSK 0x0000ffff
1869
1870
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_CLR_MSK 0xffff0000
1871
1872
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_RESET 0x0
1873
1874
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_GET(value) (((value) & 0x0000ffff) >> 0)
1875
1876
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET(value) (((value) << 0) & 0x0000ffff)
1877
1885
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_LSB 16
1886
1887
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_MSB 31
1888
1889
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_WIDTH 16
1890
1891
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET_MSK 0xffff0000
1892
1893
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_CLR_MSK 0x0000ffff
1894
1895
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_RESET 0x0
1896
1897
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_GET(value) (((value) & 0xffff0000) >> 16)
1898
1899
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET(value) (((value) << 16) & 0xffff0000)
1900
1901
#ifndef __ASSEMBLY__
1902
1912
struct
ALT_FPGAMGR_JTAG_DATA_R_s
1913
{
1914
uint32_t
tdiData
: 16;
1915
uint32_t
Reserved
: 16;
1916
};
1917
1919
typedef
volatile
struct
ALT_FPGAMGR_JTAG_DATA_R_s
ALT_FPGAMGR_JTAG_DATA_R_t
;
1920
#endif
/* __ASSEMBLY__ */
1921
1923
#define ALT_FPGAMGR_JTAG_DATA_R_RESET 0x00000000
1924
1925
#define ALT_FPGAMGR_JTAG_DATA_R_OFST 0x64
1926
1959
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_LSB 0
1960
1961
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_MSB 0
1962
1963
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_WIDTH 1
1964
1965
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET_MSK 0x00000001
1966
1967
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_CLR_MSK 0xfffffffe
1968
1969
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_RESET 0x1
1970
1971
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_GET(value) (((value) & 0x00000001) >> 0)
1972
1973
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NCFG_SET(value) (((value) << 0) & 0x00000001)
1974
1988
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_LSB 1
1989
1990
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_MSB 1
1991
1992
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_WIDTH 1
1993
1994
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET_MSK 0x00000002
1995
1996
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_CLR_MSK 0xfffffffd
1997
1998
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_RESET 0x1
1999
2000
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_GET(value) (((value) & 0x00000002) >> 1)
2001
2002
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_NSTAT_SET(value) (((value) << 1) & 0x00000002)
2003
2017
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_LSB 2
2018
2019
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_MSB 2
2020
2021
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_WIDTH 1
2022
2023
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET_MSK 0x00000004
2024
2025
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_CLR_MSK 0xfffffffb
2026
2027
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_RESET 0x1
2028
2029
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_GET(value) (((value) & 0x00000004) >> 2)
2030
2031
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NEN_CONDONE_SET(value) (((value) << 2) & 0x00000004)
2032
2050
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_LSB 8
2051
2052
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_MSB 8
2053
2054
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_WIDTH 1
2055
2056
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET_MSK 0x00000100
2057
2058
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_CLR_MSK 0xfffffeff
2059
2060
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_RESET 0x1
2061
2062
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_GET(value) (((value) & 0x00000100) >> 8)
2063
2064
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCFG_SET(value) (((value) << 8) & 0x00000100)
2065
2086
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_LSB 16
2087
2088
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_MSB 16
2089
2090
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_WIDTH 1
2091
2092
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET_MSK 0x00010000
2093
2094
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_CLR_MSK 0xfffeffff
2095
2096
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_RESET 0x0
2097
2098
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_GET(value) (((value) & 0x00010000) >> 16)
2099
2100
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTAT_OE_SET(value) (((value) << 16) & 0x00010000)
2101
2117
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_LSB 24
2118
2119
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_MSB 24
2120
2121
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_WIDTH 1
2122
2123
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK 0x01000000
2124
2125
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_CLR_MSK 0xfeffffff
2126
2127
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_RESET 0x0
2128
2129
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_GET(value) (((value) & 0x01000000) >> 24)
2130
2131
#define ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET(value) (((value) << 24) & 0x01000000)
2132
2133
#ifndef __ASSEMBLY__
2134
2144
struct
ALT_FPGAMGR_IMGCFG_CTL_00_s
2145
{
2146
uint32_t
s2f_nenable_nconfig
: 1;
2147
uint32_t
s2f_nenable_nstatus
: 1;
2148
uint32_t
s2f_nenable_condone
: 1;
2149
uint32_t : 5;
2150
uint32_t
s2f_nconfig
: 1;
2151
uint32_t : 7;
2152
uint32_t
s2f_nstatus_oe
: 1;
2153
uint32_t : 7;
2154
uint32_t
s2f_condone_oe
: 1;
2155
uint32_t : 7;
2156
};
2157
2159
typedef
volatile
struct
ALT_FPGAMGR_IMGCFG_CTL_00_s
ALT_FPGAMGR_IMGCFG_CTL_00_t
;
2160
#endif
/* __ASSEMBLY__ */
2161
2163
#define ALT_FPGAMGR_IMGCFG_CTL_00_RESET 0x00000107
2164
2165
#define ALT_FPGAMGR_IMGCFG_CTL_00_OFST 0x70
2166
2195
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_LSB 0
2196
2197
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_MSB 0
2198
2199
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_WIDTH 1
2200
2201
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET_MSK 0x00000001
2202
2203
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_CLR_MSK 0xfffffffe
2204
2205
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_RESET 0x1
2206
2207
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_GET(value) (((value) & 0x00000001) >> 0)
2208
2209
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NEN_CFG_SET(value) (((value) << 0) & 0x00000001)
2210
2220
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_LSB 16
2221
2222
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_MSB 16
2223
2224
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_WIDTH 1
2225
2226
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK 0x00010000
2227
2228
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_CLR_MSK 0xfffeffff
2229
2230
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_RESET 0x0
2231
2232
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_GET(value) (((value) & 0x00010000) >> 16)
2233
2234
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET(value) (((value) << 16) & 0x00010000)
2235
2245
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_LSB 24
2246
2247
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_MSB 24
2248
2249
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_WIDTH 1
2250
2251
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK 0x01000000
2252
2253
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_CLR_MSK 0xfeffffff
2254
2255
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_RESET 0x1
2256
2257
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_GET(value) (((value) & 0x01000000) >> 24)
2258
2259
#define ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET(value) (((value) << 24) & 0x01000000)
2260
2261
#ifndef __ASSEMBLY__
2262
2272
struct
ALT_FPGAMGR_IMGCFG_CTL_01_s
2273
{
2274
uint32_t
s2f_nenable_config
: 1;
2275
uint32_t : 15;
2276
uint32_t
s2f_pr_request
: 1;
2277
uint32_t : 7;
2278
uint32_t
s2f_nce
: 1;
2279
uint32_t : 7;
2280
};
2281
2283
typedef
volatile
struct
ALT_FPGAMGR_IMGCFG_CTL_01_s
ALT_FPGAMGR_IMGCFG_CTL_01_t
;
2284
#endif
/* __ASSEMBLY__ */
2285
2287
#define ALT_FPGAMGR_IMGCFG_CTL_01_RESET 0x01000001
2288
2289
#define ALT_FPGAMGR_IMGCFG_CTL_01_OFST 0x74
2290
2337
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_LSB 0
2338
2339
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_MSB 0
2340
2341
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_WIDTH 1
2342
2343
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET_MSK 0x00000001
2344
2345
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_CLR_MSK 0xfffffffe
2346
2347
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_RESET 0x0
2348
2349
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_GET(value) (((value) & 0x00000001) >> 0)
2350
2351
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET(value) (((value) << 0) & 0x00000001)
2352
2362
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_LSB 8
2363
2364
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_MSB 8
2365
2366
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_WIDTH 1
2367
2368
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100
2369
2370
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_CLR_MSK 0xfffffeff
2371
2372
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_RESET 0x0
2373
2374
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_GET(value) (((value) & 0x00000100) >> 8)
2375
2376
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET(value) (((value) << 8) & 0x00000100)
2377
2407
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 0x0
2408
2413
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 0x1
2414
2419
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 0x2
2420
2425
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 0x3
2426
2428
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16
2429
2430
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MSB 17
2431
2432
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_WIDTH 2
2433
2434
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000
2435
2436
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_CLR_MSK 0xfffcffff
2437
2438
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_RESET 0x0
2439
2440
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_GET(value) (((value) & 0x00030000) >> 16)
2441
2442
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET(value) (((value) << 16) & 0x00030000)
2443
2472
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 0x0
2473
2478
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 0x1
2479
2481
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_LSB 24
2482
2483
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_MSB 24
2484
2485
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_WIDTH 1
2486
2487
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000
2488
2489
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_CLR_MSK 0xfeffffff
2490
2491
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_RESET 0x0
2492
2493
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_GET(value) (((value) & 0x01000000) >> 24)
2494
2495
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET(value) (((value) << 24) & 0x01000000)
2496
2497
#ifndef __ASSEMBLY__
2498
2508
struct
ALT_FPGAMGR_IMGCFG_CTL_02_s
2509
{
2510
uint32_t
en_cfg_ctrl
: 1;
2511
uint32_t : 7;
2512
uint32_t
en_cfg_data
: 1;
2513
uint32_t : 7;
2514
uint32_t
cdratio
: 2;
2515
uint32_t : 6;
2516
uint32_t
cfgwidth
: 1;
2517
uint32_t : 7;
2518
};
2519
2521
typedef
volatile
struct
ALT_FPGAMGR_IMGCFG_CTL_02_s
ALT_FPGAMGR_IMGCFG_CTL_02_t
;
2522
#endif
/* __ASSEMBLY__ */
2523
2525
#define ALT_FPGAMGR_IMGCFG_CTL_02_RESET 0x00000200
2526
2527
#define ALT_FPGAMGR_IMGCFG_CTL_02_OFST 0x78
2528
2575
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_LSB 0
2576
2577
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_MSB 0
2578
2579
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_WIDTH 1
2580
2581
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
2582
2583
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
2584
2585
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_RESET 0x0
2586
2587
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
2588
2589
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
2590
2598
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_LSB 1
2599
2600
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_MSB 1
2601
2602
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_WIDTH 1
2603
2604
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
2605
2606
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
2607
2608
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_RESET 0x0
2609
2610
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
2611
2612
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
2613
2621
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_LSB 2
2622
2623
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_MSB 2
2624
2625
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_WIDTH 1
2626
2627
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET_MSK 0x00000004
2628
2629
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
2630
2631
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_RESET 0x0
2632
2633
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
2634
2635
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
2636
2644
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_LSB 3
2645
2646
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_MSB 3
2647
2648
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_WIDTH 1
2649
2650
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
2651
2652
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
2653
2654
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_RESET 0x0
2655
2656
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
2657
2658
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
2659
2667
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_LSB 4
2668
2669
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_MSB 4
2670
2671
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_WIDTH 1
2672
2673
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
2674
2675
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
2676
2677
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_RESET 0x0
2678
2679
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
2680
2681
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
2682
2690
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_LSB 5
2691
2692
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_MSB 5
2693
2694
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_WIDTH 1
2695
2696
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
2697
2698
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
2699
2700
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_RESET 0x0
2701
2702
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
2703
2704
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
2705
2713
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_LSB 6
2714
2715
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_MSB 6
2716
2717
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_WIDTH 1
2718
2719
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
2720
2721
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
2722
2723
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_RESET 0x0
2724
2725
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
2726
2727
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
2728
2736
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_LSB 7
2737
2738
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_MSB 7
2739
2740
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_WIDTH 1
2741
2742
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
2743
2744
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
2745
2746
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_RESET 0x0
2747
2748
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
2749
2750
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
2751
2759
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_LSB 8
2760
2761
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_MSB 8
2762
2763
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_WIDTH 1
2764
2765
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
2766
2767
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
2768
2769
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_RESET 0x0
2770
2771
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
2772
2773
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
2774
2782
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_LSB 9
2783
2784
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_MSB 9
2785
2786
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_WIDTH 1
2787
2788
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET_MSK 0x00000200
2789
2790
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
2791
2792
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_RESET 0x0
2793
2794
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
2795
2796
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
2797
2805
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_LSB 10
2806
2807
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_MSB 10
2808
2809
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_WIDTH 1
2810
2811
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET_MSK 0x00000400
2812
2813
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
2814
2815
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_RESET 0x0
2816
2817
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
2818
2819
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
2820
2828
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_LSB 11
2829
2830
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_MSB 11
2831
2832
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_WIDTH 1
2833
2834
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
2835
2836
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
2837
2838
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_RESET 0x0
2839
2840
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
2841
2842
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
2843
2851
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_LSB 12
2852
2853
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_MSB 12
2854
2855
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_WIDTH 1
2856
2857
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
2858
2859
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
2860
2861
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_RESET 0x0
2862
2863
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
2864
2865
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
2866
2874
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_LSB 13
2875
2876
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_MSB 13
2877
2878
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_WIDTH 1
2879
2880
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
2881
2882
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
2883
2884
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_RESET 0x0
2885
2886
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
2887
2888
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
2889
2905
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB 16
2906
2907
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_MSB 16
2908
2909
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_WIDTH 1
2910
2911
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET_MSK 0x00010000
2912
2913
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
2914
2915
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_RESET 0x0
2916
2917
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
2918
2919
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
2920
2936
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_LSB 17
2937
2938
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_MSB 17
2939
2940
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_WIDTH 1
2941
2942
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET_MSK 0x00020000
2943
2944
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
2945
2946
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_RESET 0x0
2947
2948
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
2949
2950
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
2951
2967
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_LSB 18
2968
2969
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_MSB 18
2970
2971
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_WIDTH 1
2972
2973
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET_MSK 0x00040000
2974
2975
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
2976
2977
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_RESET 0x0
2978
2979
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
2980
2981
#define ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
2982
2992
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_LSB 24
2993
2994
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_MSB 24
2995
2996
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
2997
2998
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
2999
3000
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3001
3002
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_RESET 0x1
3003
3004
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3005
3006
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3007
3017
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_LSB 25
3018
3019
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_MSB 25
3020
3021
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_WIDTH 1
3022
3023
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3024
3025
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3026
3027
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_RESET 0x0
3028
3029
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3030
3031
#define ALT_FPGAMGR_IMGCFG_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3032
3042
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_LSB 28
3043
3044
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_MSB 28
3045
3046
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_WIDTH 1
3047
3048
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET_MSK 0x10000000
3049
3050
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_CLR_MSK 0xefffffff
3051
3052
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_RESET 0x0
3053
3054
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3055
3056
#define ALT_FPGAMGR_IMGCFG_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3057
3067
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_LSB 29
3068
3069
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_MSB 29
3070
3071
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_WIDTH 1
3072
3073
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET_MSK 0x20000000
3074
3075
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_CLR_MSK 0xdfffffff
3076
3077
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_RESET 0x0
3078
3079
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3080
3081
#define ALT_FPGAMGR_IMGCFG_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3082
3083
#ifndef __ASSEMBLY__
3084
3094
struct
ALT_FPGAMGR_IMGCFG_STAT_s
3095
{
3096
const
uint32_t
f2s_crc_error
: 1;
3097
const
uint32_t
f2s_early_usermode
: 1;
3098
const
uint32_t
f2s_usermode
: 1;
3099
const
uint32_t
f2s_initdone_oe
: 1;
3100
const
uint32_t
f2s_nstatus_pin
: 1;
3101
const
uint32_t
f2s_nstatus_oe
: 1;
3102
const
uint32_t
f2s_condone_pin
: 1;
3103
const
uint32_t
f2s_condone_oe
: 1;
3104
const
uint32_t
f2s_cvp_conf_done
: 1;
3105
const
uint32_t
f2s_pr_ready
: 1;
3106
const
uint32_t
f2s_pr_done
: 1;
3107
const
uint32_t
f2s_pr_error
: 1;
3108
const
uint32_t
f2s_nconfig_pin
: 1;
3109
const
uint32_t
f2s_nceo_oe
: 1;
3110
uint32_t : 2;
3111
const
uint32_t
f2s_msel0
: 1;
3112
const
uint32_t
f2s_msel1
: 1;
3113
const
uint32_t
f2s_msel2
: 1;
3114
uint32_t : 5;
3115
const
uint32_t
imgcfg_FifoEmpty
: 1;
3116
const
uint32_t
imgcfg_FifoFull
: 1;
3117
uint32_t : 2;
3118
const
uint32_t
jtagm
: 1;
3119
const
uint32_t
emr
: 1;
3120
uint32_t : 2;
3121
};
3122
3124
typedef
volatile
struct
ALT_FPGAMGR_IMGCFG_STAT_s
ALT_FPGAMGR_IMGCFG_STAT_t
;
3125
#endif
/* __ASSEMBLY__ */
3126
3128
#define ALT_FPGAMGR_IMGCFG_STAT_RESET 0x01000000
3129
3130
#define ALT_FPGAMGR_IMGCFG_STAT_OFST 0x80
3131
3179
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_LSB 0
3180
3181
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_MSB 0
3182
3183
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_WIDTH 1
3184
3185
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET_MSK 0x00000001
3186
3187
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3188
3189
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_RESET 0x0
3190
3191
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3192
3193
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3194
3202
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_LSB 1
3203
3204
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_MSB 1
3205
3206
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_WIDTH 1
3207
3208
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3209
3210
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3211
3212
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_RESET 0x0
3213
3214
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3215
3216
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3217
3225
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_LSB 2
3226
3227
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_MSB 2
3228
3229
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_WIDTH 1
3230
3231
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET_MSK 0x00000004
3232
3233
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_CLR_MSK 0xfffffffb
3234
3235
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_RESET 0x0
3236
3237
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3238
3239
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3240
3248
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_LSB 3
3249
3250
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_MSB 3
3251
3252
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_WIDTH 1
3253
3254
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET_MSK 0x00000008
3255
3256
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3257
3258
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_RESET 0x0
3259
3260
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3261
3262
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3263
3271
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_LSB 4
3272
3273
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_MSB 4
3274
3275
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_WIDTH 1
3276
3277
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET_MSK 0x00000010
3278
3279
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3280
3281
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_RESET 0x0
3282
3283
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3284
3285
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3286
3294
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_LSB 5
3295
3296
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_MSB 5
3297
3298
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_WIDTH 1
3299
3300
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET_MSK 0x00000020
3301
3302
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3303
3304
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_RESET 0x0
3305
3306
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3307
3308
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3309
3317
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_LSB 6
3318
3319
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_MSB 6
3320
3321
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_WIDTH 1
3322
3323
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET_MSK 0x00000040
3324
3325
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3326
3327
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_RESET 0x0
3328
3329
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3330
3331
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3332
3340
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_LSB 7
3341
3342
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_MSB 7
3343
3344
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_WIDTH 1
3345
3346
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET_MSK 0x00000080
3347
3348
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3349
3350
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_RESET 0x0
3351
3352
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3353
3354
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3355
3363
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_LSB 8
3364
3365
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_MSB 8
3366
3367
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_WIDTH 1
3368
3369
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3370
3371
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3372
3373
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_RESET 0x0
3374
3375
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3376
3377
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3378
3386
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_LSB 9
3387
3388
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_MSB 9
3389
3390
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_WIDTH 1
3391
3392
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET_MSK 0x00000200
3393
3394
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_CLR_MSK 0xfffffdff
3395
3396
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_RESET 0x0
3397
3398
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3399
3400
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3401
3409
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_LSB 10
3410
3411
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_MSB 10
3412
3413
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_WIDTH 1
3414
3415
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET_MSK 0x00000400
3416
3417
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_CLR_MSK 0xfffffbff
3418
3419
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_RESET 0x0
3420
3421
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
3422
3423
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
3424
3432
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_LSB 11
3433
3434
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_MSB 11
3435
3436
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_WIDTH 1
3437
3438
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET_MSK 0x00000800
3439
3440
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
3441
3442
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_RESET 0x0
3443
3444
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
3445
3446
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
3447
3455
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_LSB 12
3456
3457
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_MSB 12
3458
3459
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_WIDTH 1
3460
3461
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET_MSK 0x00001000
3462
3463
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_CLR_MSK 0xffffefff
3464
3465
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_RESET 0x0
3466
3467
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
3468
3469
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
3470
3478
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_LSB 13
3479
3480
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_MSB 13
3481
3482
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_WIDTH 1
3483
3484
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET_MSK 0x00002000
3485
3486
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_CLR_MSK 0xffffdfff
3487
3488
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_RESET 0x0
3489
3490
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
3491
3492
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
3493
3501
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_LSB 16
3502
3503
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_MSB 16
3504
3505
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_WIDTH 1
3506
3507
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET_MSK 0x00010000
3508
3509
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_CLR_MSK 0xfffeffff
3510
3511
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_RESET 0x0
3512
3513
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
3514
3515
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
3516
3524
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_LSB 17
3525
3526
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_MSB 17
3527
3528
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_WIDTH 1
3529
3530
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET_MSK 0x00020000
3531
3532
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_CLR_MSK 0xfffdffff
3533
3534
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_RESET 0x0
3535
3536
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
3537
3538
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
3539
3547
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_LSB 18
3548
3549
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_MSB 18
3550
3551
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_WIDTH 1
3552
3553
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET_MSK 0x00040000
3554
3555
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_CLR_MSK 0xfffbffff
3556
3557
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_RESET 0x0
3558
3559
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
3560
3561
#define ALT_FPGAMGR_INTR_MSKED_STAT_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
3562
3572
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_LSB 24
3573
3574
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_MSB 24
3575
3576
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_WIDTH 1
3577
3578
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
3579
3580
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
3581
3582
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_RESET 0x0
3583
3584
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
3585
3586
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
3587
3597
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_LSB 25
3598
3599
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_MSB 25
3600
3601
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_WIDTH 1
3602
3603
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET_MSK 0x02000000
3604
3605
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
3606
3607
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_RESET 0x0
3608
3609
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
3610
3611
#define ALT_FPGAMGR_INTR_MSKED_STAT_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
3612
3622
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_LSB 28
3623
3624
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_MSB 28
3625
3626
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_WIDTH 1
3627
3628
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET_MSK 0x10000000
3629
3630
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_CLR_MSK 0xefffffff
3631
3632
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_RESET 0x0
3633
3634
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
3635
3636
#define ALT_FPGAMGR_INTR_MSKED_STAT_JTAGM_SET(value) (((value) << 28) & 0x10000000)
3637
3647
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_LSB 29
3648
3649
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_MSB 29
3650
3651
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_WIDTH 1
3652
3653
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET_MSK 0x20000000
3654
3655
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_CLR_MSK 0xdfffffff
3656
3657
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_RESET 0x0
3658
3659
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_GET(value) (((value) & 0x20000000) >> 29)
3660
3661
#define ALT_FPGAMGR_INTR_MSKED_STAT_EMR_SET(value) (((value) << 29) & 0x20000000)
3662
3663
#ifndef __ASSEMBLY__
3664
3674
struct
ALT_FPGAMGR_INTR_MSKED_STAT_s
3675
{
3676
uint32_t
f2s_crc_error
: 1;
3677
uint32_t
f2s_early_usermode
: 1;
3678
uint32_t
f2s_usermode
: 1;
3679
uint32_t
f2s_initdone_oe
: 1;
3680
uint32_t
f2s_nstatus_pin
: 1;
3681
uint32_t
f2s_nstatus_oe
: 1;
3682
uint32_t
f2s_condone_pin
: 1;
3683
uint32_t
f2s_condone_oe
: 1;
3684
uint32_t
f2s_cvp_conf_done
: 1;
3685
uint32_t
f2s_pr_ready
: 1;
3686
uint32_t
f2s_pr_done
: 1;
3687
uint32_t
f2s_pr_error
: 1;
3688
uint32_t
f2s_nconfig_pin
: 1;
3689
uint32_t
f2s_nceo_oe
: 1;
3690
uint32_t : 2;
3691
uint32_t
f2s_msel0
: 1;
3692
uint32_t
f2s_msel1
: 1;
3693
uint32_t
f2s_msel2
: 1;
3694
uint32_t : 5;
3695
uint32_t
imgcfg_FifoEmpty
: 1;
3696
uint32_t
imgcfg_FifoFull
: 1;
3697
uint32_t : 2;
3698
uint32_t
jtagm
: 1;
3699
uint32_t
emr
: 1;
3700
uint32_t : 2;
3701
};
3702
3704
typedef
volatile
struct
ALT_FPGAMGR_INTR_MSKED_STAT_s
ALT_FPGAMGR_INTR_MSKED_STAT_t
;
3705
#endif
/* __ASSEMBLY__ */
3706
3708
#define ALT_FPGAMGR_INTR_MSKED_STAT_RESET 0x00000000
3709
3710
#define ALT_FPGAMGR_INTR_MSKED_STAT_OFST 0x84
3711
3756
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_LSB 0
3757
3758
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_MSB 0
3759
3760
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_WIDTH 1
3761
3762
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET_MSK 0x00000001
3763
3764
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
3765
3766
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_RESET 0x1
3767
3768
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
3769
3770
#define ALT_FPGAMGR_INTR_MSK_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
3771
3779
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_LSB 1
3780
3781
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_MSB 1
3782
3783
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_WIDTH 1
3784
3785
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET_MSK 0x00000002
3786
3787
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
3788
3789
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_RESET 0x1
3790
3791
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
3792
3793
#define ALT_FPGAMGR_INTR_MSK_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
3794
3802
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_LSB 2
3803
3804
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_MSB 2
3805
3806
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_WIDTH 1
3807
3808
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET_MSK 0x00000004
3809
3810
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_CLR_MSK 0xfffffffb
3811
3812
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_RESET 0x1
3813
3814
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
3815
3816
#define ALT_FPGAMGR_INTR_MSK_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
3817
3825
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_LSB 3
3826
3827
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_MSB 3
3828
3829
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_WIDTH 1
3830
3831
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET_MSK 0x00000008
3832
3833
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
3834
3835
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_RESET 0x1
3836
3837
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
3838
3839
#define ALT_FPGAMGR_INTR_MSK_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
3840
3848
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_LSB 4
3849
3850
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_MSB 4
3851
3852
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_WIDTH 1
3853
3854
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET_MSK 0x00000010
3855
3856
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
3857
3858
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_RESET 0x1
3859
3860
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
3861
3862
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
3863
3871
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_LSB 5
3872
3873
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_MSB 5
3874
3875
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_WIDTH 1
3876
3877
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET_MSK 0x00000020
3878
3879
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
3880
3881
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_RESET 0x1
3882
3883
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
3884
3885
#define ALT_FPGAMGR_INTR_MSK_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
3886
3894
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_LSB 6
3895
3896
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_MSB 6
3897
3898
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_WIDTH 1
3899
3900
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET_MSK 0x00000040
3901
3902
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
3903
3904
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_RESET 0x1
3905
3906
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
3907
3908
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
3909
3917
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_LSB 7
3918
3919
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_MSB 7
3920
3921
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_WIDTH 1
3922
3923
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET_MSK 0x00000080
3924
3925
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
3926
3927
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_RESET 0x1
3928
3929
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
3930
3931
#define ALT_FPGAMGR_INTR_MSK_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
3932
3940
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_LSB 8
3941
3942
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_MSB 8
3943
3944
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_WIDTH 1
3945
3946
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
3947
3948
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
3949
3950
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_RESET 0x1
3951
3952
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
3953
3954
#define ALT_FPGAMGR_INTR_MSK_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
3955
3963
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_LSB 9
3964
3965
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_MSB 9
3966
3967
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_WIDTH 1
3968
3969
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET_MSK 0x00000200
3970
3971
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_CLR_MSK 0xfffffdff
3972
3973
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_RESET 0x1
3974
3975
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
3976
3977
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
3978
3986
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_LSB 10
3987
3988
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_MSB 10
3989
3990
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_WIDTH 1
3991
3992
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET_MSK 0x00000400
3993
3994
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_CLR_MSK 0xfffffbff
3995
3996
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_RESET 0x1
3997
3998
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
3999
4000
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4001
4009
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_LSB 11
4010
4011
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_MSB 11
4012
4013
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_WIDTH 1
4014
4015
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET_MSK 0x00000800
4016
4017
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4018
4019
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_RESET 0x1
4020
4021
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4022
4023
#define ALT_FPGAMGR_INTR_MSK_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4024
4032
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_LSB 12
4033
4034
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_MSB 12
4035
4036
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_WIDTH 1
4037
4038
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET_MSK 0x00001000
4039
4040
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4041
4042
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_RESET 0x1
4043
4044
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4045
4046
#define ALT_FPGAMGR_INTR_MSK_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4047
4055
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_LSB 13
4056
4057
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_MSB 13
4058
4059
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_WIDTH 1
4060
4061
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET_MSK 0x00002000
4062
4063
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4064
4065
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_RESET 0x1
4066
4067
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4068
4069
#define ALT_FPGAMGR_INTR_MSK_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4070
4078
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_LSB 16
4079
4080
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_MSB 16
4081
4082
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_WIDTH 1
4083
4084
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET_MSK 0x00010000
4085
4086
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_CLR_MSK 0xfffeffff
4087
4088
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_RESET 0x1
4089
4090
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4091
4092
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4093
4101
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_LSB 17
4102
4103
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_MSB 17
4104
4105
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_WIDTH 1
4106
4107
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET_MSK 0x00020000
4108
4109
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_CLR_MSK 0xfffdffff
4110
4111
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_RESET 0x1
4112
4113
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4114
4115
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4116
4124
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_LSB 18
4125
4126
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_MSB 18
4127
4128
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_WIDTH 1
4129
4130
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET_MSK 0x00040000
4131
4132
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_CLR_MSK 0xfffbffff
4133
4134
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_RESET 0x1
4135
4136
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4137
4138
#define ALT_FPGAMGR_INTR_MSK_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4139
4149
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_LSB 24
4150
4151
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_MSB 24
4152
4153
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_WIDTH 1
4154
4155
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4156
4157
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4158
4159
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_RESET 0x1
4160
4161
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4162
4163
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4164
4174
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_LSB 25
4175
4176
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_MSB 25
4177
4178
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_WIDTH 1
4179
4180
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4181
4182
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4183
4184
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_RESET 0x1
4185
4186
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4187
4188
#define ALT_FPGAMGR_INTR_MSK_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4189
4199
#define ALT_FPGAMGR_INTR_MSK_JTAGM_LSB 28
4200
4201
#define ALT_FPGAMGR_INTR_MSK_JTAGM_MSB 28
4202
4203
#define ALT_FPGAMGR_INTR_MSK_JTAGM_WIDTH 1
4204
4205
#define ALT_FPGAMGR_INTR_MSK_JTAGM_SET_MSK 0x10000000
4206
4207
#define ALT_FPGAMGR_INTR_MSK_JTAGM_CLR_MSK 0xefffffff
4208
4209
#define ALT_FPGAMGR_INTR_MSK_JTAGM_RESET 0x1
4210
4211
#define ALT_FPGAMGR_INTR_MSK_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4212
4213
#define ALT_FPGAMGR_INTR_MSK_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4214
4224
#define ALT_FPGAMGR_INTR_MSK_EMR_LSB 29
4225
4226
#define ALT_FPGAMGR_INTR_MSK_EMR_MSB 29
4227
4228
#define ALT_FPGAMGR_INTR_MSK_EMR_WIDTH 1
4229
4230
#define ALT_FPGAMGR_INTR_MSK_EMR_SET_MSK 0x20000000
4231
4232
#define ALT_FPGAMGR_INTR_MSK_EMR_CLR_MSK 0xdfffffff
4233
4234
#define ALT_FPGAMGR_INTR_MSK_EMR_RESET 0x1
4235
4236
#define ALT_FPGAMGR_INTR_MSK_EMR_GET(value) (((value) & 0x20000000) >> 29)
4237
4238
#define ALT_FPGAMGR_INTR_MSK_EMR_SET(value) (((value) << 29) & 0x20000000)
4239
4240
#ifndef __ASSEMBLY__
4241
4251
struct
ALT_FPGAMGR_INTR_MSK_s
4252
{
4253
uint32_t
f2s_crc_error
: 1;
4254
uint32_t
f2s_early_usermode
: 1;
4255
uint32_t
f2s_usermode
: 1;
4256
uint32_t
f2s_initdone_oe
: 1;
4257
uint32_t
f2s_nstatus_pin
: 1;
4258
uint32_t
f2s_nstatus_oe
: 1;
4259
uint32_t
f2s_condone_pin
: 1;
4260
uint32_t
f2s_condone_oe
: 1;
4261
uint32_t
f2s_cvp_conf_done
: 1;
4262
uint32_t
f2s_pr_ready
: 1;
4263
uint32_t
f2s_pr_done
: 1;
4264
uint32_t
f2s_pr_error
: 1;
4265
uint32_t
f2s_nconfig_pin
: 1;
4266
uint32_t
f2s_nceo_oe
: 1;
4267
uint32_t : 2;
4268
uint32_t
f2s_msel0
: 1;
4269
uint32_t
f2s_msel1
: 1;
4270
uint32_t
f2s_msel2
: 1;
4271
uint32_t : 5;
4272
uint32_t
imgcfg_FifoEmpty
: 1;
4273
uint32_t
imgcfg_FifoFull
: 1;
4274
uint32_t : 2;
4275
uint32_t
jtagm
: 1;
4276
uint32_t
emr
: 1;
4277
uint32_t : 2;
4278
};
4279
4281
typedef
volatile
struct
ALT_FPGAMGR_INTR_MSK_s
ALT_FPGAMGR_INTR_MSK_t
;
4282
#endif
/* __ASSEMBLY__ */
4283
4285
#define ALT_FPGAMGR_INTR_MSK_RESET 0x33073fff
4286
4287
#define ALT_FPGAMGR_INTR_MSK_OFST 0x88
4288
4338
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_LSB 0
4339
4340
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_MSB 0
4341
4342
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_WIDTH 1
4343
4344
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET_MSK 0x00000001
4345
4346
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_CLR_MSK 0xfffffffe
4347
4348
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_RESET 0x1
4349
4350
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_GET(value) (((value) & 0x00000001) >> 0)
4351
4352
#define ALT_FPGAMGR_INTR_POL_F2S_CRC_ERROR_SET(value) (((value) << 0) & 0x00000001)
4353
4361
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_LSB 1
4362
4363
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_MSB 1
4364
4365
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_WIDTH 1
4366
4367
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET_MSK 0x00000002
4368
4369
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_CLR_MSK 0xfffffffd
4370
4371
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_RESET 0x1
4372
4373
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_GET(value) (((value) & 0x00000002) >> 1)
4374
4375
#define ALT_FPGAMGR_INTR_POL_F2S_EARLY_USERMOD_SET(value) (((value) << 1) & 0x00000002)
4376
4384
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_LSB 2
4385
4386
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_MSB 2
4387
4388
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_WIDTH 1
4389
4390
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET_MSK 0x00000004
4391
4392
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_CLR_MSK 0xfffffffb
4393
4394
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_RESET 0x1
4395
4396
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_GET(value) (((value) & 0x00000004) >> 2)
4397
4398
#define ALT_FPGAMGR_INTR_POL_F2S_USERMOD_SET(value) (((value) << 2) & 0x00000004)
4399
4407
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_LSB 3
4408
4409
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_MSB 3
4410
4411
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_WIDTH 1
4412
4413
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET_MSK 0x00000008
4414
4415
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_CLR_MSK 0xfffffff7
4416
4417
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_RESET 0x1
4418
4419
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_GET(value) (((value) & 0x00000008) >> 3)
4420
4421
#define ALT_FPGAMGR_INTR_POL_F2S_INITDONE_OE_SET(value) (((value) << 3) & 0x00000008)
4422
4430
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_LSB 4
4431
4432
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_MSB 4
4433
4434
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_WIDTH 1
4435
4436
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET_MSK 0x00000010
4437
4438
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_CLR_MSK 0xffffffef
4439
4440
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_RESET 0x1
4441
4442
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_GET(value) (((value) & 0x00000010) >> 4)
4443
4444
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_PIN_SET(value) (((value) << 4) & 0x00000010)
4445
4453
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_LSB 5
4454
4455
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_MSB 5
4456
4457
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_WIDTH 1
4458
4459
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET_MSK 0x00000020
4460
4461
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_CLR_MSK 0xffffffdf
4462
4463
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_RESET 0x1
4464
4465
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_GET(value) (((value) & 0x00000020) >> 5)
4466
4467
#define ALT_FPGAMGR_INTR_POL_F2S_NSTAT_OE_SET(value) (((value) << 5) & 0x00000020)
4468
4476
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_LSB 6
4477
4478
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_MSB 6
4479
4480
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_WIDTH 1
4481
4482
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET_MSK 0x00000040
4483
4484
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_CLR_MSK 0xffffffbf
4485
4486
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_RESET 0x1
4487
4488
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_GET(value) (((value) & 0x00000040) >> 6)
4489
4490
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_PIN_SET(value) (((value) << 6) & 0x00000040)
4491
4499
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_LSB 7
4500
4501
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_MSB 7
4502
4503
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_WIDTH 1
4504
4505
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET_MSK 0x00000080
4506
4507
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_CLR_MSK 0xffffff7f
4508
4509
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_RESET 0x1
4510
4511
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_GET(value) (((value) & 0x00000080) >> 7)
4512
4513
#define ALT_FPGAMGR_INTR_POL_F2S_CONDONE_OE_SET(value) (((value) << 7) & 0x00000080)
4514
4522
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_LSB 8
4523
4524
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_MSB 8
4525
4526
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_WIDTH 1
4527
4528
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET_MSK 0x00000100
4529
4530
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_CLR_MSK 0xfffffeff
4531
4532
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_RESET 0x1
4533
4534
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_GET(value) (((value) & 0x00000100) >> 8)
4535
4536
#define ALT_FPGAMGR_INTR_POL_F2S_CVP_CONF_DONE_SET(value) (((value) << 8) & 0x00000100)
4537
4545
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_LSB 9
4546
4547
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_MSB 9
4548
4549
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_WIDTH 1
4550
4551
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET_MSK 0x00000200
4552
4553
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_CLR_MSK 0xfffffdff
4554
4555
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_RESET 0x1
4556
4557
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_GET(value) (((value) & 0x00000200) >> 9)
4558
4559
#define ALT_FPGAMGR_INTR_POL_F2S_PR_RDY_SET(value) (((value) << 9) & 0x00000200)
4560
4568
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_LSB 10
4569
4570
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_MSB 10
4571
4572
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_WIDTH 1
4573
4574
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET_MSK 0x00000400
4575
4576
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_CLR_MSK 0xfffffbff
4577
4578
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_RESET 0x1
4579
4580
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_GET(value) (((value) & 0x00000400) >> 10)
4581
4582
#define ALT_FPGAMGR_INTR_POL_F2S_PR_DONE_SET(value) (((value) << 10) & 0x00000400)
4583
4591
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_LSB 11
4592
4593
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_MSB 11
4594
4595
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_WIDTH 1
4596
4597
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET_MSK 0x00000800
4598
4599
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_CLR_MSK 0xfffff7ff
4600
4601
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_RESET 0x1
4602
4603
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_GET(value) (((value) & 0x00000800) >> 11)
4604
4605
#define ALT_FPGAMGR_INTR_POL_F2S_PR_ERROR_SET(value) (((value) << 11) & 0x00000800)
4606
4614
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_LSB 12
4615
4616
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_MSB 12
4617
4618
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_WIDTH 1
4619
4620
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET_MSK 0x00001000
4621
4622
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_CLR_MSK 0xffffefff
4623
4624
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_RESET 0x1
4625
4626
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_GET(value) (((value) & 0x00001000) >> 12)
4627
4628
#define ALT_FPGAMGR_INTR_POL_F2S_NCFG_PIN_SET(value) (((value) << 12) & 0x00001000)
4629
4637
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_LSB 13
4638
4639
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_MSB 13
4640
4641
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_WIDTH 1
4642
4643
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET_MSK 0x00002000
4644
4645
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_CLR_MSK 0xffffdfff
4646
4647
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_RESET 0x1
4648
4649
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_GET(value) (((value) & 0x00002000) >> 13)
4650
4651
#define ALT_FPGAMGR_INTR_POL_F2S_NCEO_OE_SET(value) (((value) << 13) & 0x00002000)
4652
4660
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_LSB 16
4661
4662
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_MSB 16
4663
4664
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_WIDTH 1
4665
4666
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET_MSK 0x00010000
4667
4668
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_CLR_MSK 0xfffeffff
4669
4670
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_RESET 0x1
4671
4672
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_GET(value) (((value) & 0x00010000) >> 16)
4673
4674
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL0_SET(value) (((value) << 16) & 0x00010000)
4675
4683
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_LSB 17
4684
4685
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_MSB 17
4686
4687
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_WIDTH 1
4688
4689
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET_MSK 0x00020000
4690
4691
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_CLR_MSK 0xfffdffff
4692
4693
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_RESET 0x1
4694
4695
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_GET(value) (((value) & 0x00020000) >> 17)
4696
4697
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL1_SET(value) (((value) << 17) & 0x00020000)
4698
4706
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_LSB 18
4707
4708
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_MSB 18
4709
4710
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_WIDTH 1
4711
4712
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET_MSK 0x00040000
4713
4714
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_CLR_MSK 0xfffbffff
4715
4716
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_RESET 0x1
4717
4718
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_GET(value) (((value) & 0x00040000) >> 18)
4719
4720
#define ALT_FPGAMGR_INTR_POL_F2S_MSEL2_SET(value) (((value) << 18) & 0x00040000)
4721
4731
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_LSB 24
4732
4733
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_MSB 24
4734
4735
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_WIDTH 1
4736
4737
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET_MSK 0x01000000
4738
4739
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_CLR_MSK 0xfeffffff
4740
4741
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_RESET 0x1
4742
4743
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_GET(value) (((value) & 0x01000000) >> 24)
4744
4745
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOEMPTY_SET(value) (((value) << 24) & 0x01000000)
4746
4756
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_LSB 25
4757
4758
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_MSB 25
4759
4760
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_WIDTH 1
4761
4762
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET_MSK 0x02000000
4763
4764
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_CLR_MSK 0xfdffffff
4765
4766
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_RESET 0x1
4767
4768
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_GET(value) (((value) & 0x02000000) >> 25)
4769
4770
#define ALT_FPGAMGR_INTR_POL_IMGCFG_FIFOFULL_SET(value) (((value) << 25) & 0x02000000)
4771
4781
#define ALT_FPGAMGR_INTR_POL_JTAGM_LSB 28
4782
4783
#define ALT_FPGAMGR_INTR_POL_JTAGM_MSB 28
4784
4785
#define ALT_FPGAMGR_INTR_POL_JTAGM_WIDTH 1
4786
4787
#define ALT_FPGAMGR_INTR_POL_JTAGM_SET_MSK 0x10000000
4788
4789
#define ALT_FPGAMGR_INTR_POL_JTAGM_CLR_MSK 0xefffffff
4790
4791
#define ALT_FPGAMGR_INTR_POL_JTAGM_RESET 0x1
4792
4793
#define ALT_FPGAMGR_INTR_POL_JTAGM_GET(value) (((value) & 0x10000000) >> 28)
4794
4795
#define ALT_FPGAMGR_INTR_POL_JTAGM_SET(value) (((value) << 28) & 0x10000000)
4796
4806
#define ALT_FPGAMGR_INTR_POL_EMR_LSB 29
4807
4808
#define ALT_FPGAMGR_INTR_POL_EMR_MSB 29
4809
4810
#define ALT_FPGAMGR_INTR_POL_EMR_WIDTH 1
4811
4812
#define ALT_FPGAMGR_INTR_POL_EMR_SET_MSK 0x20000000
4813
4814
#define ALT_FPGAMGR_INTR_POL_EMR_CLR_MSK 0xdfffffff
4815
4816
#define ALT_FPGAMGR_INTR_POL_EMR_RESET 0x1
4817
4818
#define ALT_FPGAMGR_INTR_POL_EMR_GET(value) (((value) & 0x20000000) >> 29)
4819
4820
#define ALT_FPGAMGR_INTR_POL_EMR_SET(value) (((value) << 29) & 0x20000000)
4821
4822
#ifndef __ASSEMBLY__
4823
4833
struct
ALT_FPGAMGR_INTR_POL_s
4834
{
4835
uint32_t
f2s_crc_error
: 1;
4836
uint32_t
f2s_early_usermode
: 1;
4837
uint32_t
f2s_usermode
: 1;
4838
uint32_t
f2s_initdone_oe
: 1;
4839
uint32_t
f2s_nstatus_pin
: 1;
4840
uint32_t
f2s_nstatus_oe
: 1;
4841
uint32_t
f2s_condone_pin
: 1;
4842
uint32_t
f2s_condone_oe
: 1;
4843
uint32_t
f2s_cvp_conf_done
: 1;
4844
uint32_t
f2s_pr_ready
: 1;
4845
uint32_t
f2s_pr_done
: 1;
4846
uint32_t
f2s_pr_error
: 1;
4847
uint32_t
f2s_nconfig_pin
: 1;
4848
uint32_t
f2s_nceo_oe
: 1;
4849
uint32_t : 2;
4850
uint32_t
f2s_msel0
: 1;
4851
uint32_t
f2s_msel1
: 1;
4852
uint32_t
f2s_msel2
: 1;
4853
uint32_t : 5;
4854
uint32_t
imgcfg_FifoEmpty
: 1;
4855
uint32_t
imgcfg_FifoFull
: 1;
4856
uint32_t : 2;
4857
uint32_t
jtagm
: 1;
4858
uint32_t
emr
: 1;
4859
uint32_t : 2;
4860
};
4861
4863
typedef
volatile
struct
ALT_FPGAMGR_INTR_POL_s
ALT_FPGAMGR_INTR_POL_t
;
4864
#endif
/* __ASSEMBLY__ */
4865
4867
#define ALT_FPGAMGR_INTR_POL_RESET 0x33073fff
4868
4869
#define ALT_FPGAMGR_INTR_POL_OFST 0x8c
4870
4896
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_LSB 0
4897
4898
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_MSB 7
4899
4900
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_WIDTH 8
4901
4902
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET_MSK 0x000000ff
4903
4904
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_CLR_MSK 0xffffff00
4905
4906
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_RESET 0x0
4907
4908
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_GET(value) (((value) & 0x000000ff) >> 0)
4909
4910
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET(value) (((value) << 0) & 0x000000ff)
4911
4934
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS 0x0
4935
4940
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN 0x1
4941
4943
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_LSB 8
4944
4945
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_MSB 8
4946
4947
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_WIDTH 1
4948
4949
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET_MSK 0x00000100
4950
4951
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_CLR_MSK 0xfffffeff
4952
4953
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_RESET 0x0
4954
4955
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_GET(value) (((value) & 0x00000100) >> 8)
4956
4957
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET(value) (((value) << 8) & 0x00000100)
4958
4968
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_LSB 16
4969
4970
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_MSB 16
4971
4972
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_WIDTH 1
4973
4974
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET_MSK 0x00010000
4975
4976
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_CLR_MSK 0xfffeffff
4977
4978
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_RESET 0x0
4979
4980
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_GET(value) (((value) & 0x00010000) >> 16)
4981
4982
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET(value) (((value) << 16) & 0x00010000)
4983
4984
#ifndef __ASSEMBLY__
4985
4995
struct
ALT_FPGAMGR_DMA_CFG_s
4996
{
4997
uint32_t
dmareq_level
: 8;
4998
uint32_t
dmareq_enable
: 1;
4999
uint32_t : 7;
5000
uint32_t
clearFifo
: 1;
5001
uint32_t : 15;
5002
};
5003
5005
typedef
volatile
struct
ALT_FPGAMGR_DMA_CFG_s
ALT_FPGAMGR_DMA_CFG_t
;
5006
#endif
/* __ASSEMBLY__ */
5007
5009
#define ALT_FPGAMGR_DMA_CFG_RESET 0x00000000
5010
5011
#define ALT_FPGAMGR_DMA_CFG_OFST 0x90
5012
5039
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_LSB 0
5040
5041
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_MSB 7
5042
5043
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_WIDTH 8
5044
5045
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET_MSK 0x000000ff
5046
5047
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_CLR_MSK 0xffffff00
5048
5049
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_RESET 0x0
5050
5051
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_GET(value) (((value) & 0x000000ff) >> 0)
5052
5053
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOLEVEL_SET(value) (((value) << 0) & 0x000000ff)
5054
5068
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_LSB 8
5069
5070
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_MSB 8
5071
5072
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_WIDTH 1
5073
5074
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET_MSK 0x00000100
5075
5076
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_CLR_MSK 0xfffffeff
5077
5078
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_RESET 0x0
5079
5080
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_GET(value) (((value) & 0x00000100) >> 8)
5081
5082
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOFULL_SET(value) (((value) << 8) & 0x00000100)
5083
5097
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_LSB 9
5098
5099
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_MSB 9
5100
5101
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_WIDTH 1
5102
5103
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET_MSK 0x00000200
5104
5105
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_CLR_MSK 0xfffffdff
5106
5107
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_RESET 0x1
5108
5109
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_GET(value) (((value) & 0x00000200) >> 9)
5110
5111
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_FIFOEMPTY_SET(value) (((value) << 9) & 0x00000200)
5112
5113
#ifndef __ASSEMBLY__
5114
5124
struct
ALT_FPGAMGR_IMGCFG_FIFO_STAT_s
5125
{
5126
uint32_t
FifoLevel
: 8;
5127
uint32_t
FifoFull
: 1;
5128
uint32_t
FifoEmpty
: 1;
5129
uint32_t : 22;
5130
};
5131
5133
typedef
volatile
struct
ALT_FPGAMGR_IMGCFG_FIFO_STAT_s
ALT_FPGAMGR_IMGCFG_FIFO_STAT_t
;
5134
#endif
/* __ASSEMBLY__ */
5135
5137
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_RESET 0x00000200
5138
5139
#define ALT_FPGAMGR_IMGCFG_FIFO_STAT_OFST 0x94
5140
5141
#ifndef __ASSEMBLY__
5142
5152
struct
ALT_FPGAMGR_s
5153
{
5154
volatile
uint32_t
_pad_0x0_0x7
[2];
5155
volatile
ALT_FPGAMGR_DCLKCNT_t
dclkcnt
;
5156
volatile
ALT_FPGAMGR_DCLKSTAT_t
dclkstat
;
5157
volatile
ALT_FPGAMGR_GPO_t
gpo
;
5158
volatile
ALT_FPGAMGR_GPI_t
gpi
;
5159
volatile
ALT_FPGAMGR_MISCI_t
misci
;
5160
volatile
uint32_t
_pad_0x1c_0x2f
[5];
5161
volatile
ALT_FPGAMGR_EMR_DATA0_t
emr_data0
;
5162
volatile
ALT_FPGAMGR_EMR_DATA1_t
emr_data1
;
5163
volatile
ALT_FPGAMGR_EMR_DATA2_t
emr_data2
;
5164
volatile
ALT_FPGAMGR_EMR_DATA3_t
emr_data3
;
5165
volatile
ALT_FPGAMGR_EMR_DATA4_t
emr_data4
;
5166
volatile
ALT_FPGAMGR_EMR_DATA5_t
emr_data5
;
5167
volatile
ALT_FPGAMGR_EMR_VALID_t
emr_valid
;
5168
volatile
ALT_FPGAMGR_EMR_EN_t
emr_en
;
5169
volatile
ALT_FPGAMGR_JTAG_CFG_t
jtag_config
;
5170
volatile
ALT_FPGAMGR_JTAG_STAT_t
jtag_status
;
5171
volatile
ALT_FPGAMGR_JTAG_KICK_t
jtag_kick
;
5172
volatile
uint32_t
_pad_0x5c_0x5f
;
5173
volatile
ALT_FPGAMGR_JTAG_DATA_W_t
jtag_data_w
;
5174
volatile
ALT_FPGAMGR_JTAG_DATA_R_t
jtag_data_r
;
5175
volatile
uint32_t
_pad_0x68_0x6f
[2];
5176
volatile
ALT_FPGAMGR_IMGCFG_CTL_00_t
imgcfg_ctrl_00
;
5177
volatile
ALT_FPGAMGR_IMGCFG_CTL_01_t
imgcfg_ctrl_01
;
5178
volatile
ALT_FPGAMGR_IMGCFG_CTL_02_t
imgcfg_ctrl_02
;
5179
volatile
uint32_t
_pad_0x7c_0x7f
;
5180
volatile
ALT_FPGAMGR_IMGCFG_STAT_t
imgcfg_stat
;
5181
volatile
ALT_FPGAMGR_INTR_MSKED_STAT_t
intr_masked_status
;
5182
volatile
ALT_FPGAMGR_INTR_MSK_t
intr_mask
;
5183
volatile
ALT_FPGAMGR_INTR_POL_t
intr_polarity
;
5184
volatile
ALT_FPGAMGR_DMA_CFG_t
dma_config
;
5185
volatile
ALT_FPGAMGR_IMGCFG_FIFO_STAT_t
imgcfg_fifo_status
;
5186
volatile
uint32_t
_pad_0x98_0x1000
[986];
5187
};
5188
5190
typedef
volatile
struct
ALT_FPGAMGR_s
ALT_FPGAMGR_t
;
5192
struct
ALT_FPGAMGR_raw_s
5193
{
5194
volatile
uint32_t
_pad_0x0_0x7
[2];
5195
volatile
uint32_t
dclkcnt
;
5196
volatile
uint32_t
dclkstat
;
5197
volatile
uint32_t
gpo
;
5198
volatile
uint32_t
gpi
;
5199
volatile
uint32_t
misci
;
5200
volatile
uint32_t
_pad_0x1c_0x2f
[5];
5201
volatile
uint32_t
emr_data0
;
5202
volatile
uint32_t
emr_data1
;
5203
volatile
uint32_t
emr_data2
;
5204
volatile
uint32_t
emr_data3
;
5205
volatile
uint32_t
emr_data4
;
5206
volatile
uint32_t
emr_data5
;
5207
volatile
uint32_t
emr_valid
;
5208
volatile
uint32_t
emr_en
;
5209
volatile
uint32_t
jtag_config
;
5210
volatile
uint32_t
jtag_status
;
5211
volatile
uint32_t
jtag_kick
;
5212
volatile
uint32_t
_pad_0x5c_0x5f
;
5213
volatile
uint32_t
jtag_data_w
;
5214
volatile
uint32_t
jtag_data_r
;
5215
volatile
uint32_t
_pad_0x68_0x6f
[2];
5216
volatile
uint32_t
imgcfg_ctrl_00
;
5217
volatile
uint32_t
imgcfg_ctrl_01
;
5218
volatile
uint32_t
imgcfg_ctrl_02
;
5219
volatile
uint32_t
_pad_0x7c_0x7f
;
5220
volatile
uint32_t
imgcfg_stat
;
5221
volatile
uint32_t
intr_masked_status
;
5222
volatile
uint32_t
intr_mask
;
5223
volatile
uint32_t
intr_polarity
;
5224
volatile
uint32_t
dma_config
;
5225
volatile
uint32_t
imgcfg_fifo_status
;
5226
volatile
uint32_t
_pad_0x98_0x1000
[986];
5227
};
5228
5230
typedef
volatile
struct
ALT_FPGAMGR_raw_s
ALT_FPGAMGR_raw_t
;
5231
#endif
/* __ASSEMBLY__ */
5232
5234
#ifdef __cplusplus
5235
}
5236
#endif
/* __cplusplus */
5237
#endif
/* __ALT_SOCAL_FPGAMGR_H__ */
5238
include
soc_a10
socal
alt_fpgamgr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
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