Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 65 (MMC Receive Interrupt Register) - MMC_Receive_Interrupt

Description

The MMC Receive Interrupt register maintains the interrupts that are generated when the following happens:

When the Counter Stop Rollover is set, then interrupts are set but the counter remains at all-ones. The MMC Receive Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.

Register Layout

Bits Access Reset Description
[0] R 0x0 MMC Receive Good Bad Frame Counter Interrupt Status
[1] R 0x0 MMC Receive Good Bad Octet Counter Interrupt Status
[2] R 0x0 MMC Receive Good Octet Counter Interrupt Status.
[3] R 0x0 MMC Receive Broadcast Good Frame Counter Interrupt Status.
[4] R 0x0 MMC Receive Multicast Good Frame Counter Interrupt Status
[5] R 0x0 MMC Receive CRC Error Frame Counter Interrupt Status
[6] R 0x0 MMC Receive Alignment Error Frame Counter Interrupt Status
[7] R 0x0 MMC Receive Runt Frame Counter Interrupt Status
[8] R 0x0 MMC Receive Jabber Error Frame Counter Interrupt Status
[9] R 0x0 MMC Receive Undersize Good Frame Counter Interrupt Status
[10] R 0x0 MMC Receive Oversize Good Frame Counter Interrupt Status
[11] R 0x0 MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
[12] R 0x0 MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
[13] R 0x0 MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
[14] R 0x0 MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
[15] R 0x0 MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
[16] R 0x0 MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
[17] R 0x0 MMC Receive Unicast Good Frame Counter Interrupt Status
[18] R 0x0 MMC Receive Length Error Frame Counter Interrupt Status
[19] R 0x0 MMC Receive Out Of Range Error Frame Counter Interrupt Status
[20] R 0x0 MMC Receive Pause Frame Counter Interrupt Status
[21] R 0x0 MMC Receive FIFO Overflow Frame Counter Interrupt Status
[22] R 0x0 MMC Receive VLAN Good Bad Frame Counter Interrupt Status
[23] R 0x0 MMC Receive Watchdog Error Frame Counter Interrupt Status
[24] R 0x0 MMC Receive Error Frame Counter Interrupt Status
[25] R 0x0 MMC Receive Control Frame Counter Interrupt Status
[31:26] ??? 0x0 UNDEFINED

Field : MMC Receive Good Bad Frame Counter Interrupt Status - rxgbfrmis

This bit is set when the rxframecount_bg counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF 0x0 Preset All Counters to almost-half
ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL 0x1 Present All Counters almost-full

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB   0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB   0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : MMC Receive Good Bad Octet Counter Interrupt Status - rxgboctis

This bit is set when the rxoctetcount_bg counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT 0x0 Rxoctetcount_bg < half max
ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT 0x1 Rxoctetcount_bg >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : MMC Receive Good Octet Counter Interrupt Status. - rxgoctis

This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT 0x0 Rxoctetcount_g < half max
ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT 0x1 Rxoctetcount_g >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB   2
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB   2
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET(value)   (((value) << 2) & 0x00000004)
 

Field : MMC Receive Broadcast Good Frame Counter Interrupt Status. - rxbcgfis

This bit is set when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value.

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB   3
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB   3
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET(value)   (((value) << 3) & 0x00000008)
 

Field : MMC Receive Multicast Good Frame Counter Interrupt Status - rxmcgfis

This bit is set when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT 0x0 rxbroadcastframes_g < half max
ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT 0x1 rxbroadcastframes_g >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB   4
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB   4
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET(value)   (((value) << 4) & 0x00000010)
 

Field : MMC Receive CRC Error Frame Counter Interrupt Status - rxcrcerfis

This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT 0x0 rxcrcerror < half max
ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT 0x1 rxcrcerror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB   5
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB   5
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET(value)   (((value) << 5) & 0x00000020)
 

Field : MMC Receive Alignment Error Frame Counter Interrupt Status - rxalgnerfis

This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT 0x0 rxalignmenterror < half max
ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT 0x1 rxalignmenterror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB   6
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB   6
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK   0x00000040
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET(value)   (((value) << 6) & 0x00000040)
 

Field : MMC Receive Runt Frame Counter Interrupt Status - rxruntfis

This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT 0x0 rxrunterror < half max
ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT 0x1 rxrunterror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB   7
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB   7
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : MMC Receive Jabber Error Frame Counter Interrupt Status - rxjaberfis

This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT 0x0 rxjabbererror < half max
ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT 0x1 rxjabbererror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB   8
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB   8
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET(value)   (((value) << 8) & 0x00000100)
 

Field : MMC Receive Undersize Good Frame Counter Interrupt Status - rxusizegfis

This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT 0x0 rxundersize_g < half max
ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT 0x1 rxundersize_g >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB   9
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB   9
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET(value)   (((value) << 9) & 0x00000200)
 

Field : MMC Receive Oversize Good Frame Counter Interrupt Status - rxosizegfis

This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT 0x0 rxoversize_g < half max
ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT 0x1 rxoversize_g >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB   10
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB   10
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status - rx64octgbfis

This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT 0x0 rx64octets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT 0x1 rx64octets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB   11
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB   11
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET(value)   (((value) << 11) & 0x00000800)
 

Field : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status - rx65t127octgbfis

This is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT 0x0 rx65to127octets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT 0x1 rx65to127octets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB   12
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB   12
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET(value)   (((value) << 12) & 0x00001000)
 

Field : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status - rx128t255octgbfis

This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT 0x0 rx128to255octets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT 0x1 rx128to255octets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB   13
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB   13
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET(value)   (((value) << 13) & 0x00002000)
 

Field : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status - rx256t511octgbfis

This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT 0x0 rx256to511octets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT 0x1 rx256to511octets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB   14
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB   14
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK   0x00004000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET(value)   (((value) << 14) & 0x00004000)
 

Field : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status - rx512t1023octgbfis

This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT 0x0 rx512to1023octets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT 0x1 rx512to1023octets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB   15
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB   15
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK   0x00008000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET(value)   (((value) << 15) & 0x00008000)
 

Field : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status - rx1024tmaxoctgbfis

This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT 0x0 rx1024tomaxoctets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT 0x1 rx1024tomaxoctets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB   16
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB   16
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET(value)   (((value) << 16) & 0x00010000)
 

Field : MMC Receive Unicast Good Frame Counter Interrupt Status - rxucgfis

This bit is set when the rxunicastframes_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT 0x0 rx1024tomaxoctets_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT 0x1 rx1024tomaxoctets_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB   17
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB   17
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK   0x00020000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK   0xfffdffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET(value)   (((value) << 17) & 0x00020000)
 

Field : MMC Receive Length Error Frame Counter Interrupt Status - rxlenerfis

This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT 0x0 rxlengtherror < half max
ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT 0x1 rxlengtherror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB   18
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB   18
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET(value)   (((value) << 18) & 0x00040000)
 

Field : MMC Receive Out Of Range Error Frame Counter Interrupt Status - rxorangefis

This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT 0x0 rxoutofrangetype < half max
ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT 0x1 rxoutofrangetype >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB   19
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB   19
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET(value)   (((value) << 19) & 0x00080000)
 

Field : MMC Receive Pause Frame Counter Interrupt Status - rxpausfis

This bit is set when the rxpauseframe counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT 0x0 rxpauseframe < half max
ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT 0x1 rxpauseframe >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB   20
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB   20
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET(value)   (((value) << 20) & 0x00100000)
 

Field : MMC Receive FIFO Overflow Frame Counter Interrupt Status - rxfovfis

This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT 0x0 rxfifooverflow < half max
ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT 0x1 rxfifooverflow >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB   21
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB   21
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET(value)   (((value) << 21) & 0x00200000)
 

Field : MMC Receive VLAN Good Bad Frame Counter Interrupt Status - rxvlangbfis

This bit is set when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT 0x0 rxvlanframes_gb < half max
ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT 0x1 rxvlanframes_gb >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB   22
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB   22
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK   0x00400000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET(value)   (((value) << 22) & 0x00400000)
 

Field : MMC Receive Watchdog Error Frame Counter Interrupt Status - rxwdogfis

This bit is set when the rxwatchdogerror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT 0x0 rxwatchdogerror < half max
ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT 0x1 rxwatchdogerror >= half max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT   0x1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB   23
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB   23
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK   0x00800000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET(value)   (((value) << 23) & 0x00800000)
 

Field : MMC Receive Error Frame Counter Interrupt Status - rxrcverrfis

This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value.

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB   24
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB   24
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET(value)   (((value) << 24) & 0x01000000)
 

Field : MMC Receive Control Frame Counter Interrupt Status - rxctrlfis

This bit is set when the rxctrlframes_g counter reaches half of the maximum value or the maximum value.

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB   25
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB   25
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET(value)   (((value) << 25) & 0x02000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MMC_RX_INT_s
 

Macros

#define ALT_EMAC_GMAC_MMC_RX_INT_OFST   0x104
 
#define ALT_EMAC_GMAC_MMC_RX_INT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MMC_RX_INT_s 
ALT_EMAC_GMAC_MMC_RX_INT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MMC_RX_INT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT.

Data Fields
const uint32_t rxgbfrmis: 1 MMC Receive Good Bad Frame Counter Interrupt Status
const uint32_t rxgboctis: 1 MMC Receive Good Bad Octet Counter Interrupt Status
const uint32_t rxgoctis: 1 MMC Receive Good Octet Counter Interrupt Status.
const uint32_t rxbcgfis: 1 MMC Receive Broadcast Good Frame Counter Interrupt Status.
const uint32_t rxmcgfis: 1 MMC Receive Multicast Good Frame Counter Interrupt Status
const uint32_t rxcrcerfis: 1 MMC Receive CRC Error Frame Counter Interrupt Status
const uint32_t rxalgnerfis: 1 MMC Receive Alignment Error Frame Counter Interrupt Status
const uint32_t rxruntfis: 1 MMC Receive Runt Frame Counter Interrupt Status
const uint32_t rxjaberfis: 1 MMC Receive Jabber Error Frame Counter Interrupt Status
const uint32_t rxusizegfis: 1 MMC Receive Undersize Good Frame Counter Interrupt Status
const uint32_t rxosizegfis: 1 MMC Receive Oversize Good Frame Counter Interrupt Status
const uint32_t rx64octgbfis: 1 MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
const uint32_t rx65t127octgbfis: 1 MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
const uint32_t rx128t255octgbfis: 1 MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
const uint32_t rx256t511octgbfis: 1 MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
const uint32_t rx512t1023octgbfis: 1 MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
const uint32_t rx1024tmaxoctgbfis: 1 MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
const uint32_t rxucgfis: 1 MMC Receive Unicast Good Frame Counter Interrupt Status
const uint32_t rxlenerfis: 1 MMC Receive Length Error Frame Counter Interrupt Status
const uint32_t rxorangefis: 1 MMC Receive Out Of Range Error Frame Counter Interrupt Status
const uint32_t rxpausfis: 1 MMC Receive Pause Frame Counter Interrupt Status
const uint32_t rxfovfis: 1 MMC Receive FIFO Overflow Frame Counter Interrupt Status
const uint32_t rxvlangbfis: 1 MMC Receive VLAN Good Bad Frame Counter Interrupt Status
const uint32_t rxwdogfis: 1 MMC Receive Watchdog Error Frame Counter Interrupt Status
const uint32_t rxrcverrfis: 1 MMC Receive Error Frame Counter Interrupt Status
const uint32_t rxctrlfis: 1 MMC Receive Control Frame Counter Interrupt Status
uint32_t __pad0__: 6 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTHALF   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS

Preset All Counters to almost-half

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_E_ALMOSTFULL   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS

Present All Counters almost-full

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBFRMIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS

Rxoctetcount_bg < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS

Rxoctetcount_bg >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_GBOCTIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS

Rxoctetcount_g < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS

Rxoctetcount_g >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_GOCTIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_BCGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS

rxbroadcastframes_g < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS

rxbroadcastframes_g >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_MCGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS

rxcrcerror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS

rxcrcerror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_CRCERFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS

rxalignmenterror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS

rxalignmenterror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_ALGNERFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS

rxrunterror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS

rxrunterror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_RUNTFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS

rxjabbererror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS

rxjabbererror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_JABERFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS

rxundersize_g < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS

rxundersize_g >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_USIZEGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS

rxoversize_g < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS

rxoversize_g >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_OSIZEGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS

rx64octets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS

rx64octets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_64OCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS

rx65to127octets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS

rx65to127octets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_65T127OCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS

rx128to255octets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS

rx128to255octets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_128T255OCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS

rx256to511octets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS

rx256to511octets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_256T511OCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS

rx512to1023octets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS

rx512to1023octets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_512T1023OCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS

rx1024tomaxoctets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS

rx1024tomaxoctets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS

rx1024tomaxoctets_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS

rx1024tomaxoctets_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET_MSK   0x00020000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_CLR_MSK   0xfffdffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_UCGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS

rxlengtherror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS

rxlengtherror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_LENERFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS

rxoutofrangetype < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS

rxoutofrangetype >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_ORANGEFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS

rxpauseframe < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS

rxpauseframe >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_PAUSFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS

rxfifooverflow < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS

rxfifooverflow >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_FOVFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS

rxvlanframes_gb < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS

rxvlanframes_gb >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_VLANGBFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS

rxwatchdogerror < half max

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS

rxwatchdogerror >= half max

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_WDOGFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_RCVERRFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS field value from a register.

#define ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_MMC_RX_INT_CTLFIS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_RX_INT_OFST   0x104

The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT register from the beginning of the component.

#define ALT_EMAC_GMAC_MMC_RX_INT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_OFST))

The address of the ALT_EMAC_GMAC_MMC_RX_INT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT.