Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - emac2

Description

Registers used by the EMAC. All fields are reset by a cold or warm reset.

Register Layout

Bits Access Reset Description
[1:0] RW 0x3 ALT_SYSMGR_EMAC2_PHY_INTF_SEL
[7:2] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_SYSMGR_EMAC2_PTP_REF_SEL
[11:9] ??? 0x0 UNDEFINED
[12] RW 0x0 ALT_SYSMGR_EMAC2_APP_CLK_SEL
[15:13] ??? 0x0 UNDEFINED
[19:16] RW 0x0 ALT_SYSMGR_EMAC2_ARCACHE
[23:20] RW 0x0 ALT_SYSMGR_EMAC2_AWCACHE
[25:24] RW 0x2 ALT_SYSMGR_EMAC2_ARPROT
[26] ??? 0x0 UNDEFINED
[28:27] RW 0x2 ALT_SYSMGR_EMAC2_AWPROT
[29] ??? 0x0 UNDEFINED
[30] RW 0x0 ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS
[31] RW 0x0 ALT_SYSMGR_EMAC2_AXI_DIS

Field : phy_intf_sel

PHY Interface Select

Field to select "Out of Reset", GMII (or MII), RGMII or RMII as the PHY interface. Note, the MAC speed is an output of Synopsys IP. So the System Manager PHY Select combined with MAC speed from the IP determine the clock/PHY configuration. "Out of Reset" mode implies that the MAC RX and TX internal clocks use the Clock Manager reference rather than depending on the PHY to have active clocks.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII | 0x0 | ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII | 0x1 | ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII | 0x2 | ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST | 0x3 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII   0x0
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII   0x1
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII   0x2
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST   0x3
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_LSB   0
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_MSB   1
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_WIDTH   2
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK   0x00000003
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_CLR_MSK   0xfffffffc
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_RESET   0x3
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET(value)   (((value) << 0) & 0x00000003)
 

Field : ptp_ref_sel

This field selects if the Timestamp reference is internally or externally generated. EMAC0 may be the master to generate the timestamp for EMAC1 and EMAC2. EMAC0 must be set to Internal Timestamp. EMAC1/2 may be set to either Internal or External.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL | 0x0 | ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL | 0x1 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL   0x0
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL   0x1
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_LSB   8
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_MSB   8
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_WIDTH   1
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET_MSK   0x00000100
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_CLR_MSK   0xfffffeff
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET(value)   (((value) << 8) & 0x00000100)
 

Field : app_clk_sel

Selects the source of the Application clock for the datapath to either l4_mp_clk for normal Baum operation or to f2s_ap_clk if the switch interface is enabled to the FPGA fabric.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK | 0x0 | ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK | 0x1 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK   0x0
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK   0x1
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_LSB   12
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_MSB   12
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_WIDTH   1
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET_MSK   0x00001000
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_CLR_MSK   0xffffefff
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET(value)   (((value) << 12) & 0x00001000)
 

Field : arcache

Specifies the values of the 2 EMAC ARCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF | 0x0 | ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF | 0x1 | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC | 0x2 | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC | 0x3 | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1 | 0x4 | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2 | 0x5 | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3 | 0x8 | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4 | 0x9 | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC | 0xb | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5 | 0xc | ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6 | 0xd | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC | 0xe | ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC | 0xf |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC2_ARCACHE_LSB   16
 
#define ALT_SYSMGR_EMAC2_ARCACHE_MSB   19
 
#define ALT_SYSMGR_EMAC2_ARCACHE_WIDTH   4
 
#define ALT_SYSMGR_EMAC2_ARCACHE_SET_MSK   0x000f0000
 
#define ALT_SYSMGR_EMAC2_ARCACHE_CLR_MSK   0xfff0ffff
 
#define ALT_SYSMGR_EMAC2_ARCACHE_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_ARCACHE_GET(value)   (((value) & 0x000f0000) >> 16)
 
#define ALT_SYSMGR_EMAC2_ARCACHE_SET(value)   (((value) << 16) & 0x000f0000)
 

Field : awcache

Specifies the values of the 2 EMAC AWCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF | 0x0 | ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF | 0x1 | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC | 0x2 | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC | 0x3 | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1 | 0x4 | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2 | 0x5 | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC | 0x6 | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC | 0x7 | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3 | 0x8 | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4 | 0x9 | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC | 0xa | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC | 0xb | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5 | 0xc | ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6 | 0xd | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC | 0xe | ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC | 0xf |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC2_AWCACHE_LSB   20
 
#define ALT_SYSMGR_EMAC2_AWCACHE_MSB   23
 
#define ALT_SYSMGR_EMAC2_AWCACHE_WIDTH   4
 
#define ALT_SYSMGR_EMAC2_AWCACHE_SET_MSK   0x00f00000
 
#define ALT_SYSMGR_EMAC2_AWCACHE_CLR_MSK   0xff0fffff
 
#define ALT_SYSMGR_EMAC2_AWCACHE_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_AWCACHE_GET(value)   (((value) & 0x00f00000) >> 20)
 
#define ALT_SYSMGR_EMAC2_AWCACHE_SET(value)   (((value) << 20) & 0x00f00000)
 

Field : arprot

Specifies the values of the ARPROT signals.


AxPROT[1]

LOW: Secure Access

HIGH: NonSecure Access


AxPROT[0]

LOW: Normal Access

HIGH: Privileged Access


Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL | 0x0 | ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED | 0x1 | ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL | 0x2 | ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED | 0x3 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL   0x0
 
#define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED   0x1
 
#define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL   0x2
 
#define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED   0x3
 
#define ALT_SYSMGR_EMAC2_ARPROT_LSB   24
 
#define ALT_SYSMGR_EMAC2_ARPROT_MSB   25
 
#define ALT_SYSMGR_EMAC2_ARPROT_WIDTH   2
 
#define ALT_SYSMGR_EMAC2_ARPROT_SET_MSK   0x03000000
 
#define ALT_SYSMGR_EMAC2_ARPROT_CLR_MSK   0xfcffffff
 
#define ALT_SYSMGR_EMAC2_ARPROT_RESET   0x2
 
#define ALT_SYSMGR_EMAC2_ARPROT_GET(value)   (((value) & 0x03000000) >> 24)
 
#define ALT_SYSMGR_EMAC2_ARPROT_SET(value)   (((value) << 24) & 0x03000000)
 

Field : awprot

Specifies the values of the 2 EMAC AWCACHE signals.


AxPROT[1]

LOW: Secure Access

HIGH: NonSecure Access


AxPROT[0]

LOW: Normal Access

HIGH: Privileged Access


Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL | 0x0 | ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED | 0x1 | ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL | 0x2 | ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED | 0x3 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL   0x0
 
#define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED   0x1
 
#define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL   0x2
 
#define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED   0x3
 
#define ALT_SYSMGR_EMAC2_AWPROT_LSB   27
 
#define ALT_SYSMGR_EMAC2_AWPROT_MSB   28
 
#define ALT_SYSMGR_EMAC2_AWPROT_WIDTH   2
 
#define ALT_SYSMGR_EMAC2_AWPROT_SET_MSK   0x18000000
 
#define ALT_SYSMGR_EMAC2_AWPROT_CLR_MSK   0xe7ffffff
 
#define ALT_SYSMGR_EMAC2_AWPROT_RESET   0x2
 
#define ALT_SYSMGR_EMAC2_AWPROT_GET(value)   (((value) & 0x18000000) >> 27)
 
#define ALT_SYSMGR_EMAC2_AWPROT_SET(value)   (((value) << 27) & 0x18000000)
 

Field : sbd_data_endianness

Specifies the endianness of the EMAC DMA transfers.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN | 0x0 | ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN | 0x1 |

Field Access Macros:

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN   0x0
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN   0x1
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_LSB   30
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_MSB   30
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_WIDTH   1
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK   0x40000000
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK   0xbfffffff
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET(value)   (((value) << 30) & 0x40000000)
 

Field : axi_disable

AXI Disable

Field Access Macros:

#define ALT_SYSMGR_EMAC2_AXI_DIS_LSB   31
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_MSB   31
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_WIDTH   1
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_SET_MSK   0x80000000
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_CLR_MSK   0x7fffffff
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_RESET   0x0
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_SYSMGR_EMAC2_AXI_DIS_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_SYSMGR_EMAC2_s
 

Macros

#define ALT_SYSMGR_EMAC2_RESET   0x12000003
 
#define ALT_SYSMGR_EMAC2_OFST   0x4c
 

Typedefs

typedef struct ALT_SYSMGR_EMAC2_s ALT_SYSMGR_EMAC2_t
 

Data Structure Documentation

struct ALT_SYSMGR_EMAC2_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_EMAC2.

Data Fields
uint32_t phy_intf_sel: 2 ALT_SYSMGR_EMAC2_PHY_INTF_SEL
uint32_t __pad0__: 6 UNDEFINED
uint32_t ptp_ref_sel: 1 ALT_SYSMGR_EMAC2_PTP_REF_SEL
uint32_t __pad1__: 3 UNDEFINED
uint32_t app_clk_sel: 1 ALT_SYSMGR_EMAC2_APP_CLK_SEL
uint32_t __pad2__: 3 UNDEFINED
uint32_t arcache: 4 ALT_SYSMGR_EMAC2_ARCACHE
uint32_t awcache: 4 ALT_SYSMGR_EMAC2_AWCACHE
uint32_t arprot: 2 ALT_SYSMGR_EMAC2_ARPROT
uint32_t __pad3__: 1 UNDEFINED
uint32_t awprot: 2 ALT_SYSMGR_EMAC2_AWPROT
uint32_t __pad4__: 1 UNDEFINED
uint32_t sbd_data_endianness: 1 ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS
uint32_t axi_disable: 1 ALT_SYSMGR_EMAC2_AXI_DIS

Macro Definitions

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII   0x2

Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST   0x3

Enumerated value for register field ALT_SYSMGR_EMAC2_PHY_INTF_SEL

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_WIDTH   2

The width in bits of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK   0x00000003

The mask used to set the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_CLR_MSK   0xfffffffc

The mask used to clear the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_RESET   0x3

The reset value of the ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_SYSMGR_EMAC2_PHY_INTF_SEL field value from a register.

#define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_SYSMGR_EMAC2_PHY_INTF_SEL register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_PTP_REF_SEL

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_PTP_REF_SEL

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_MSB   8

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_WIDTH   1

The width in bits of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET_MSK   0x00000100

The mask used to set the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_PTP_REF_SEL register field.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SYSMGR_EMAC2_PTP_REF_SEL field value from a register.

#define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SYSMGR_EMAC2_PTP_REF_SEL register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_APP_CLK_SEL

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_APP_CLK_SEL

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_LSB   12

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_MSB   12

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_WIDTH   1

The width in bits of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET_MSK   0x00001000

The mask used to set the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_CLR_MSK   0xffffefff

The mask used to clear the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_APP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_SYSMGR_EMAC2_APP_CLK_SEL field value from a register.

#define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_SYSMGR_EMAC2_APP_CLK_SEL register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC2_ARCACHE

#define ALT_SYSMGR_EMAC2_ARCACHE_LSB   16

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_ARCACHE register field.

#define ALT_SYSMGR_EMAC2_ARCACHE_MSB   19

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_ARCACHE register field.

#define ALT_SYSMGR_EMAC2_ARCACHE_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC2_ARCACHE register field.

#define ALT_SYSMGR_EMAC2_ARCACHE_SET_MSK   0x000f0000

The mask used to set the ALT_SYSMGR_EMAC2_ARCACHE register field value.

#define ALT_SYSMGR_EMAC2_ARCACHE_CLR_MSK   0xfff0ffff

The mask used to clear the ALT_SYSMGR_EMAC2_ARCACHE register field value.

#define ALT_SYSMGR_EMAC2_ARCACHE_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_ARCACHE register field.

#define ALT_SYSMGR_EMAC2_ARCACHE_GET (   value)    (((value) & 0x000f0000) >> 16)

Extracts the ALT_SYSMGR_EMAC2_ARCACHE field value from a register.

#define ALT_SYSMGR_EMAC2_ARCACHE_SET (   value)    (((value) << 16) & 0x000f0000)

Produces a ALT_SYSMGR_EMAC2_ARCACHE register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC2_AWCACHE

#define ALT_SYSMGR_EMAC2_AWCACHE_LSB   20

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AWCACHE register field.

#define ALT_SYSMGR_EMAC2_AWCACHE_MSB   23

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AWCACHE register field.

#define ALT_SYSMGR_EMAC2_AWCACHE_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC2_AWCACHE register field.

#define ALT_SYSMGR_EMAC2_AWCACHE_SET_MSK   0x00f00000

The mask used to set the ALT_SYSMGR_EMAC2_AWCACHE register field value.

#define ALT_SYSMGR_EMAC2_AWCACHE_CLR_MSK   0xff0fffff

The mask used to clear the ALT_SYSMGR_EMAC2_AWCACHE register field value.

#define ALT_SYSMGR_EMAC2_AWCACHE_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_AWCACHE register field.

#define ALT_SYSMGR_EMAC2_AWCACHE_GET (   value)    (((value) & 0x00f00000) >> 20)

Extracts the ALT_SYSMGR_EMAC2_AWCACHE field value from a register.

#define ALT_SYSMGR_EMAC2_AWCACHE_SET (   value)    (((value) << 20) & 0x00f00000)

Produces a ALT_SYSMGR_EMAC2_AWCACHE register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT

Secure Normal(non-privileged) access

#define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT

Secure Privileged access

#define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL   0x2

Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT

Non-Secure Normal(non-privileged) access

#define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED   0x3

Enumerated value for register field ALT_SYSMGR_EMAC2_ARPROT

Non-Secure Privileged access

#define ALT_SYSMGR_EMAC2_ARPROT_LSB   24

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_ARPROT register field.

#define ALT_SYSMGR_EMAC2_ARPROT_MSB   25

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_ARPROT register field.

#define ALT_SYSMGR_EMAC2_ARPROT_WIDTH   2

The width in bits of the ALT_SYSMGR_EMAC2_ARPROT register field.

#define ALT_SYSMGR_EMAC2_ARPROT_SET_MSK   0x03000000

The mask used to set the ALT_SYSMGR_EMAC2_ARPROT register field value.

#define ALT_SYSMGR_EMAC2_ARPROT_CLR_MSK   0xfcffffff

The mask used to clear the ALT_SYSMGR_EMAC2_ARPROT register field value.

#define ALT_SYSMGR_EMAC2_ARPROT_RESET   0x2

The reset value of the ALT_SYSMGR_EMAC2_ARPROT register field.

#define ALT_SYSMGR_EMAC2_ARPROT_GET (   value)    (((value) & 0x03000000) >> 24)

Extracts the ALT_SYSMGR_EMAC2_ARPROT field value from a register.

#define ALT_SYSMGR_EMAC2_ARPROT_SET (   value)    (((value) << 24) & 0x03000000)

Produces a ALT_SYSMGR_EMAC2_ARPROT register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT

Secure Normal(non-privileged) access

#define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT

Secure Privileged access

#define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL   0x2

Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT

Non-Secure Normal(non-privileged) access

#define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED   0x3

Enumerated value for register field ALT_SYSMGR_EMAC2_AWPROT

Non-Secure Privileged access

#define ALT_SYSMGR_EMAC2_AWPROT_LSB   27

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AWPROT register field.

#define ALT_SYSMGR_EMAC2_AWPROT_MSB   28

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AWPROT register field.

#define ALT_SYSMGR_EMAC2_AWPROT_WIDTH   2

The width in bits of the ALT_SYSMGR_EMAC2_AWPROT register field.

#define ALT_SYSMGR_EMAC2_AWPROT_SET_MSK   0x18000000

The mask used to set the ALT_SYSMGR_EMAC2_AWPROT register field value.

#define ALT_SYSMGR_EMAC2_AWPROT_CLR_MSK   0xe7ffffff

The mask used to clear the ALT_SYSMGR_EMAC2_AWPROT register field value.

#define ALT_SYSMGR_EMAC2_AWPROT_RESET   0x2

The reset value of the ALT_SYSMGR_EMAC2_AWPROT register field.

#define ALT_SYSMGR_EMAC2_AWPROT_GET (   value)    (((value) & 0x18000000) >> 27)

Extracts the ALT_SYSMGR_EMAC2_AWPROT field value from a register.

#define ALT_SYSMGR_EMAC2_AWPROT_SET (   value)    (((value) << 27) & 0x18000000)

Produces a ALT_SYSMGR_EMAC2_AWPROT register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN   0x0

Enumerated value for register field ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN   0x1

Enumerated value for register field ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_LSB   30

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_MSB   30

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_WIDTH   1

The width in bits of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK   0x40000000

The mask used to set the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK   0xbfffffff

The mask used to clear the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS field value from a register.

#define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_AXI_DIS_LSB   31

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC2_AXI_DIS register field.

#define ALT_SYSMGR_EMAC2_AXI_DIS_MSB   31

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC2_AXI_DIS register field.

#define ALT_SYSMGR_EMAC2_AXI_DIS_WIDTH   1

The width in bits of the ALT_SYSMGR_EMAC2_AXI_DIS register field.

#define ALT_SYSMGR_EMAC2_AXI_DIS_SET_MSK   0x80000000

The mask used to set the ALT_SYSMGR_EMAC2_AXI_DIS register field value.

#define ALT_SYSMGR_EMAC2_AXI_DIS_CLR_MSK   0x7fffffff

The mask used to clear the ALT_SYSMGR_EMAC2_AXI_DIS register field value.

#define ALT_SYSMGR_EMAC2_AXI_DIS_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC2_AXI_DIS register field.

#define ALT_SYSMGR_EMAC2_AXI_DIS_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_SYSMGR_EMAC2_AXI_DIS field value from a register.

#define ALT_SYSMGR_EMAC2_AXI_DIS_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_SYSMGR_EMAC2_AXI_DIS register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC2_RESET   0x12000003

The reset value of the ALT_SYSMGR_EMAC2 register.

#define ALT_SYSMGR_EMAC2_OFST   0x4c

The byte offset of the ALT_SYSMGR_EMAC2 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_EMAC2.