![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Name: DMA Control Register
Size: 2 bits
Address Offset: 0x88
Read/Write Access: Read/Write
This register is only valid when DW_apb_i2c is configured
with a set of DMA Controller interface signals (IC_HAS_DMA = 1).
When DW_apb_i2c is not configured for DMA operation, this register
does not exist and writing to the register’s address has no
effect and reading from this register address will return zero.
The register is used to enable the DMA Controller interface operation.
There is a separate bit for transmit and receive. This can be programmed
regardless of the state of IC_ENABLE.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_I2C_DMA_CR_RDMAE |
[1] | RW | 0x0 | ALT_I2C_DMA_CR_TDMAE |
[31:2] | R | 0x0 | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 |
Field : rdmae | ||||||||||
Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. 0 = Receive DMA disabled 1 = Receive DMA enabled Reset value: 0x0 Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_LSB 0 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_MSB 0 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_WIDTH 1 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_RESET 0x0 | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : tdmae | ||||||||||
Transmit DMA Enable. //This bit enables/disables the transmit FIFO DMA channel. 0 = Transmit DMA disabled 1 = Transmit DMA enabled Reset value: 0x0 Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_LSB 1 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_MSB 1 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_WIDTH 1 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_RESET 0x0 | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : rsvd_ic_dma_cr_31to2 | |
Reserved bits [31:1] - Read Only Field Access Macros: | |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_LSB 2 |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_MSB 31 |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_WIDTH 30 |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET_MSK 0xfffffffc |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_CLR_MSK 0x00000003 |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_RESET 0x0 |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_GET(value) (((value) & 0xfffffffc) >> 2) |
#define | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET(value) (((value) << 2) & 0xfffffffc) |
Data Structures | |
struct | ALT_I2C_DMA_CR_s |
Macros | |
#define | ALT_I2C_DMA_CR_RESET 0x00000000 |
#define | ALT_I2C_DMA_CR_OFST 0x88 |
#define | ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) |
Typedefs | |
typedef struct ALT_I2C_DMA_CR_s | ALT_I2C_DMA_CR_t |
struct ALT_I2C_DMA_CR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_DMA_CR.
Data Fields | ||
---|---|---|
uint32_t | rdmae: 1 | ALT_I2C_DMA_CR_RDMAE |
uint32_t | tdmae: 1 | ALT_I2C_DMA_CR_TDMAE |
const uint32_t | rsvd_ic_dma_cr_31to2: 30 | ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 |
#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0 |
Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
Receive DMA disable
#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1 |
Enumerated value for register field ALT_I2C_DMA_CR_RDMAE
Receive DMA enabled
#define ALT_I2C_DMA_CR_RDMAE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RDMAE register field.
#define ALT_I2C_DMA_CR_RDMAE_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RDMAE register field.
#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1 |
The width in bits of the ALT_I2C_DMA_CR_RDMAE register field.
#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001 |
The mask used to set the ALT_I2C_DMA_CR_RDMAE register field value.
#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_I2C_DMA_CR_RDMAE register field value.
#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0 |
The reset value of the ALT_I2C_DMA_CR_RDMAE register field.
#define ALT_I2C_DMA_CR_RDMAE_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_I2C_DMA_CR_RDMAE field value from a register.
#define ALT_I2C_DMA_CR_RDMAE_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_I2C_DMA_CR_RDMAE register field value suitable for setting the register.
#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0 |
Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
Transmit DMA disable
#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1 |
Enumerated value for register field ALT_I2C_DMA_CR_TDMAE
Transmit DMA enabled
#define ALT_I2C_DMA_CR_TDMAE_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_TDMAE register field.
#define ALT_I2C_DMA_CR_TDMAE_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_TDMAE register field.
#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1 |
The width in bits of the ALT_I2C_DMA_CR_TDMAE register field.
#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002 |
The mask used to set the ALT_I2C_DMA_CR_TDMAE register field value.
#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_I2C_DMA_CR_TDMAE register field value.
#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0 |
The reset value of the ALT_I2C_DMA_CR_TDMAE register field.
#define ALT_I2C_DMA_CR_TDMAE_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_I2C_DMA_CR_TDMAE field value from a register.
#define ALT_I2C_DMA_CR_TDMAE_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_I2C_DMA_CR_TDMAE register field value suitable for setting the register.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_WIDTH 30 |
The width in bits of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET_MSK 0xfffffffc |
The mask used to set the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_CLR_MSK 0x00000003 |
The mask used to clear the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_RESET 0x0 |
The reset value of the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_GET | ( | value | ) | (((value) & 0xfffffffc) >> 2) |
Extracts the ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 field value from a register.
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET | ( | value | ) | (((value) << 2) & 0xfffffffc) |
Produces a ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2 register field value suitable for setting the register.
#define ALT_I2C_DMA_CR_RESET 0x00000000 |
The reset value of the ALT_I2C_DMA_CR register.
#define ALT_I2C_DMA_CR_OFST 0x88 |
The byte offset of the ALT_I2C_DMA_CR register from the beginning of the component.
#define ALT_I2C_DMA_CR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST)) |
The address of the ALT_I2C_DMA_CR register.
typedef struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t |
The typedef declaration for register ALT_I2C_DMA_CR.