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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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ECC control 2.
This bit is used to set the initialize the memory and ecc to a known value
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN |
[7:1] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN |
[15:9] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN |
[31:17] | ??? | 0x0 | UNDEFINED |
Field : AUTOWB_EN | |
Enable auto write back correction feature. When serr is detected on outgoing reads, HMC adaptor schedules the corrected data and ECC to the written to the DDR memory. This bit enables auto correction of DDR memory. 1'b0: disable auto WB drop correction. Default value after reset. 1'b1: enable auto WB drop correction. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_LSB 0 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_MSB 0 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET_MSK 0x00000001 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_CLR_MSK 0xfffffffe |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : RMW_EN | |
Enable read modify write logic. When ECC is enabled and sub word accesses require correct ECC to be calculated, this bit should be enabled. RMW_EN bit should be disabled when ECC_EN is disabled. 1'b0: disable RMW logic. Default value after reset. 1'b1: enable RMW logic. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_LSB 8 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_MSB 8 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_CLR_MSK 0xfffffeff |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET(value) (((value) << 8) & 0x00000100) |
Field : OVRW_RB_ECC_EN | |
Overwrite the read-back ecc code during RMW process if DBE is detected. 1'b0: write the read-back ECC from RMW process if derr is detected. Default value after reset. 1'b1: write of 1 will overwrite the ECC overwrite feature. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_LSB 16 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_MSB 16 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET(value) (((value) << 16) & 0x00010000) |
Data Structures | |
struct | ALT_ECC_HMC_OCP_ECCCTL2_s |
Macros | |
#define | ALT_ECC_HMC_OCP_ECCCTL2_RESET 0x00000000 |
#define | ALT_ECC_HMC_OCP_ECCCTL2_OFST 0x104 |
Typedefs | |
typedef struct ALT_ECC_HMC_OCP_ECCCTL2_s | ALT_ECC_HMC_OCP_ECCCTL2_t |
struct ALT_ECC_HMC_OCP_ECCCTL2_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_HMC_OCP_ECCCTL2.
Data Fields | ||
---|---|---|
uint32_t | AUTOWB_EN: 1 | ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN |
uint32_t | __pad0__: 7 | UNDEFINED |
uint32_t | RMW_EN: 1 | ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN |
uint32_t | __pad1__: 7 | UNDEFINED |
uint32_t | OVRW_RB_ECC_EN: 1 | ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN |
uint32_t | __pad2__: 15 | UNDEFINED |
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN field value from a register.
#define ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_ECC_HMC_OCP_ECCCTL2_AUTOWB_EN register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET_MSK 0x00000100 |
The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN field value from a register.
#define ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_ECC_HMC_OCP_ECCCTL2_RMW_EN register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET_MSK 0x00010000 |
The mask used to set the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN field value from a register.
#define ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_ECC_HMC_OCP_ECCCTL2_OVRW_RB_ECC_EN register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECCCTL2_RESET 0x00000000 |
The reset value of the ALT_ECC_HMC_OCP_ECCCTL2 register.
#define ALT_ECC_HMC_OCP_ECCCTL2_OFST 0x104 |
The byte offset of the ALT_ECC_HMC_OCP_ECCCTL2 register from the beginning of the component.
typedef struct ALT_ECC_HMC_OCP_ECCCTL2_s ALT_ECC_HMC_OCP_ECCCTL2_t |
The typedef declaration for register ALT_ECC_HMC_OCP_ECCCTL2.