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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Control Register 1
This register exists only when the DW_apb_ssi is configured as a
master device. When the DW_apb_ssi is configured as a serial slave,
writing to this location has no effect; reading from this location
returns 0. Control register 1 controls the end of serial transfers
when in receive-only mode. It is impossible to write to this
register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled
and disabled by writing to the SSIENR register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[15:0] | RW | 0x0 | ALT_SPIM_CTLR1_NDF |
[31:16] | ??? | 0x0 | UNDEFINED |
Field : ndf | |
Number of Data Frames. When TMOD = 10 or TMOD = 11, this register field sets the number of data frames to be continuously received by the DW_apb_ssi. The DW_apb_ssi continues to receive serial data until the number of data frames received is equal to this register value plus 1, which enables you to receive up to 64 KB of data in a continuous transfer. When the DW_apb_ssi is configured as a serial slave, the transfer continues for as long as the slave is selected. Therefore, this register serves no purpose and is not present when the DW_apb_ssi is configured as a serial slave. Field Access Macros: | |
#define | ALT_SPIM_CTLR1_NDF_LSB 0 |
#define | ALT_SPIM_CTLR1_NDF_MSB 15 |
#define | ALT_SPIM_CTLR1_NDF_WIDTH 16 |
#define | ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff |
#define | ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000 |
#define | ALT_SPIM_CTLR1_NDF_RESET 0x0 |
#define | ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0) |
#define | ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff) |
Data Structures | |
struct | ALT_SPIM_CTLR1_s |
Macros | |
#define | ALT_SPIM_CTLR1_RESET 0x00000000 |
#define | ALT_SPIM_CTLR1_OFST 0x4 |
#define | ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST)) |
Typedefs | |
typedef struct ALT_SPIM_CTLR1_s | ALT_SPIM_CTLR1_t |
struct ALT_SPIM_CTLR1_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SPIM_CTLR1.
Data Fields | ||
---|---|---|
uint32_t | ndf: 16 | ALT_SPIM_CTLR1_NDF |
uint32_t | __pad0__: 16 | UNDEFINED |
#define ALT_SPIM_CTLR1_NDF_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SPIM_CTLR1_NDF register field.
#define ALT_SPIM_CTLR1_NDF_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_SPIM_CTLR1_NDF register field.
#define ALT_SPIM_CTLR1_NDF_WIDTH 16 |
The width in bits of the ALT_SPIM_CTLR1_NDF register field.
#define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff |
The mask used to set the ALT_SPIM_CTLR1_NDF register field value.
#define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000 |
The mask used to clear the ALT_SPIM_CTLR1_NDF register field value.
#define ALT_SPIM_CTLR1_NDF_RESET 0x0 |
The reset value of the ALT_SPIM_CTLR1_NDF register field.
#define ALT_SPIM_CTLR1_NDF_GET | ( | value | ) | (((value) & 0x0000ffff) >> 0) |
Extracts the ALT_SPIM_CTLR1_NDF field value from a register.
#define ALT_SPIM_CTLR1_NDF_SET | ( | value | ) | (((value) << 0) & 0x0000ffff) |
Produces a ALT_SPIM_CTLR1_NDF register field value suitable for setting the register.
#define ALT_SPIM_CTLR1_RESET 0x00000000 |
The reset value of the ALT_SPIM_CTLR1 register.
#define ALT_SPIM_CTLR1_OFST 0x4 |
The byte offset of the ALT_SPIM_CTLR1 register from the beginning of the component.
#define ALT_SPIM_CTLR1_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST)) |
The address of the ALT_SPIM_CTLR1 register.
typedef struct ALT_SPIM_CTLR1_s ALT_SPIM_CTLR1_t |
The typedef declaration for register ALT_SPIM_CTLR1.