Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ctrl

Description

Allows HPS to control FPGA configuration.

The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA Control Block that are logically ORed into their respective pins. These signals are always driven independent of the value of EN. The polarity of the NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their associated pins.

The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used to set the appropriate clock to data ratio, and CFGWDTH should always be set to 16-bit Passive Parallel.

AXICFGEN is used to enable transfer of configuration data by enabling or disabling DCLK during data transfers.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Enable
[1] RW 0x0 nCE
[2] RW 0x0 nCONFIG Pull-Down
[3] RW 0x0 nSTATUS Pull-Down
[4] RW 0x0 CONF_DONE Pull-Down
[5] RW 0x0 Partial Reconfiguration
[7:6] RW 0x0 CD Ratio
[8] RW 0x0 AXI Configuration Enable
[9] RW 0x1 Configuration Data Width
[31:10] ??? 0x0 UNDEFINED

Field : Enable - en

Controls whether the FPGA configuration pins or HPS FPGA Manager drive configuration inputs to the CB.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG 0x0 FPGA configuration pins drive configuration
: inputs to the CB. Used when FPGA is configured
: by means other than the HPS.
ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG 0x1 FPGA Manager drives configuration inputs to the
: CB. Used when HPS configures the FPGA.

Field Access Macros:

#define ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG   0x0
 
#define ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG   0x1
 
#define ALT_FPGAMGR_CTL_EN_LSB   0
 
#define ALT_FPGAMGR_CTL_EN_MSB   0
 
#define ALT_FPGAMGR_CTL_EN_WIDTH   1
 
#define ALT_FPGAMGR_CTL_EN_SET_MSK   0x00000001
 
#define ALT_FPGAMGR_CTL_EN_CLR_MSK   0xfffffffe
 
#define ALT_FPGAMGR_CTL_EN_RESET   0x0
 
#define ALT_FPGAMGR_CTL_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_FPGAMGR_CTL_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : nCE - nce

This field drives the active-low Chip Enable (nCE) signal to the CB. It should be set to 0 (configuration enabled) before CTRL.EN is set.

This field only effects the FPGA if CTRL.EN is 1.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_NCE_E_CFG_END 0x0 Configuration is enabled. The nCE to the CB is
: driven to 0.
ALT_FPGAMGR_CTL_NCE_E_CFG_DISD 0x1 Configuration is disabled. The nCE to the CB is
: driven to 1.

Field Access Macros:

#define ALT_FPGAMGR_CTL_NCE_E_CFG_END   0x0
 
#define ALT_FPGAMGR_CTL_NCE_E_CFG_DISD   0x1
 
#define ALT_FPGAMGR_CTL_NCE_LSB   1
 
#define ALT_FPGAMGR_CTL_NCE_MSB   1
 
#define ALT_FPGAMGR_CTL_NCE_WIDTH   1
 
#define ALT_FPGAMGR_CTL_NCE_SET_MSK   0x00000002
 
#define ALT_FPGAMGR_CTL_NCE_CLR_MSK   0xfffffffd
 
#define ALT_FPGAMGR_CTL_NCE_RESET   0x0
 
#define ALT_FPGAMGR_CTL_NCE_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_FPGAMGR_CTL_NCE_SET(value)   (((value) << 1) & 0x00000002)
 

Field : nCONFIG Pull-Down - nconfigpull

The nCONFIG input is used to put the FPGA into its reset phase. If the FPGA was configured, its operation stops and it will have to be configured again to start operation.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN 0x0 Don't pull-down nCONFIG input to the CB.
ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN 0x1 Pull-down nCONFIG input to the CB. This puts the
: FPGA in reset phase and restarts configuration.

Field Access Macros:

#define ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN   0x0
 
#define ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN   0x1
 
#define ALT_FPGAMGR_CTL_NCFGPULL_LSB   2
 
#define ALT_FPGAMGR_CTL_NCFGPULL_MSB   2
 
#define ALT_FPGAMGR_CTL_NCFGPULL_WIDTH   1
 
#define ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK   0x00000004
 
#define ALT_FPGAMGR_CTL_NCFGPULL_CLR_MSK   0xfffffffb
 
#define ALT_FPGAMGR_CTL_NCFGPULL_RESET   0x0
 
#define ALT_FPGAMGR_CTL_NCFGPULL_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_FPGAMGR_CTL_NCFGPULL_SET(value)   (((value) << 2) & 0x00000004)
 

Field : nSTATUS Pull-Down - nstatuspull

Pulls down nSTATUS input to the CB

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN 0x0 Don't pull-down nSTATUS input to the CB.
ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN 0x1 Pull-down nSTATUS input to the CB.

Field Access Macros:

#define ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN   0x0
 
#define ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN   0x1
 
#define ALT_FPGAMGR_CTL_NSTATPULL_LSB   3
 
#define ALT_FPGAMGR_CTL_NSTATPULL_MSB   3
 
#define ALT_FPGAMGR_CTL_NSTATPULL_WIDTH   1
 
#define ALT_FPGAMGR_CTL_NSTATPULL_SET_MSK   0x00000008
 
#define ALT_FPGAMGR_CTL_NSTATPULL_CLR_MSK   0xfffffff7
 
#define ALT_FPGAMGR_CTL_NSTATPULL_RESET   0x0
 
#define ALT_FPGAMGR_CTL_NSTATPULL_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_FPGAMGR_CTL_NSTATPULL_SET(value)   (((value) << 3) & 0x00000008)
 

Field : CONF_DONE Pull-Down - confdonepull

Pulls down CONF_DONE input to the CB

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN 0x0 Don't pull-down CONF_DONE input to the CB.
ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN 0x1 Pull-down CONF_DONE input to the CB.

Field Access Macros:

#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN   0x0
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN   0x1
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_LSB   4
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_MSB   4
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_WIDTH   1
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET_MSK   0x00000010
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_CLR_MSK   0xffffffef
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_RESET   0x0
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Partial Reconfiguration - prreq

This field is used to assert PR_REQUEST to request partial reconfiguration while the FPGA is in User Mode. This field only affects the FPGA if CTRL.EN is 1.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT 0x0 De-assert PR_REQUEST (driven to 0).
ALT_FPGAMGR_CTL_PRREQ_E_ASSERT 0x1 Assert PR_REQUEST (driven to 1).

Field Access Macros:

#define ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT   0x0
 
#define ALT_FPGAMGR_CTL_PRREQ_E_ASSERT   0x1
 
#define ALT_FPGAMGR_CTL_PRREQ_LSB   5
 
#define ALT_FPGAMGR_CTL_PRREQ_MSB   5
 
#define ALT_FPGAMGR_CTL_PRREQ_WIDTH   1
 
#define ALT_FPGAMGR_CTL_PRREQ_SET_MSK   0x00000020
 
#define ALT_FPGAMGR_CTL_PRREQ_CLR_MSK   0xffffffdf
 
#define ALT_FPGAMGR_CTL_PRREQ_RESET   0x0
 
#define ALT_FPGAMGR_CTL_PRREQ_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_FPGAMGR_CTL_PRREQ_SET(value)   (((value) << 5) & 0x00000020)
 

Field : CD Ratio - cdratio

This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration and Partial Reconfiguration data transfer from the AXI Slave to the FPGA.

For Normal Configuration, the value in this field must be set to be consistent to the implied CD ratio of the MSEL setting.

For Partial Reconfiguration, the value in this field must be set to the same clock to data ratio in the options bits in the Normal Configuration file.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_CDRATIO_E_X1 0x0 CDRATIO of 1
ALT_FPGAMGR_CTL_CDRATIO_E_X2 0x1 CDRATIO of 2
ALT_FPGAMGR_CTL_CDRATIO_E_X4 0x2 CDRATIO of 4
ALT_FPGAMGR_CTL_CDRATIO_E_X8 0x3 CDRATIO of 8

Field Access Macros:

#define ALT_FPGAMGR_CTL_CDRATIO_E_X1   0x0
 
#define ALT_FPGAMGR_CTL_CDRATIO_E_X2   0x1
 
#define ALT_FPGAMGR_CTL_CDRATIO_E_X4   0x2
 
#define ALT_FPGAMGR_CTL_CDRATIO_E_X8   0x3
 
#define ALT_FPGAMGR_CTL_CDRATIO_LSB   6
 
#define ALT_FPGAMGR_CTL_CDRATIO_MSB   7
 
#define ALT_FPGAMGR_CTL_CDRATIO_WIDTH   2
 
#define ALT_FPGAMGR_CTL_CDRATIO_SET_MSK   0x000000c0
 
#define ALT_FPGAMGR_CTL_CDRATIO_CLR_MSK   0xffffff3f
 
#define ALT_FPGAMGR_CTL_CDRATIO_RESET   0x0
 
#define ALT_FPGAMGR_CTL_CDRATIO_GET(value)   (((value) & 0x000000c0) >> 6)
 
#define ALT_FPGAMGR_CTL_CDRATIO_SET(value)   (((value) << 6) & 0x000000c0)
 

Field : AXI Configuration Enable - axicfgen

There are strict SW initialization steps for configuration, partial configuration and error cases. When SW is sending configuration files, this bit must be set before the file is transferred on the AXI bus. This bit enables the DCLK during the AXI configuration data transfers.

Note, the AXI and configuration datapaths remain active irregardless of the state of this bit. Simply, if the AXI slave is enabled, the DCLK to the CB will be active. If disabled, the DCLK to the CB will not be active. So AXI transfers destined to the FPGA Manager when AXIEN is 0, will complete normally from the HPS perspective.

This field only affects the FPGA if CTRL.EN is 1.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_AXICFGEN_E_DISD 0x0 Incoming AXI data transfers will be ignored.
: DCLK will not toggle during data transfer.
ALT_FPGAMGR_CTL_AXICFGEN_E_END 0x1 AXI data transfer to CB is active. DCLK will
: toggle during data transfer.

Field Access Macros:

#define ALT_FPGAMGR_CTL_AXICFGEN_E_DISD   0x0
 
#define ALT_FPGAMGR_CTL_AXICFGEN_E_END   0x1
 
#define ALT_FPGAMGR_CTL_AXICFGEN_LSB   8
 
#define ALT_FPGAMGR_CTL_AXICFGEN_MSB   8
 
#define ALT_FPGAMGR_CTL_AXICFGEN_WIDTH   1
 
#define ALT_FPGAMGR_CTL_AXICFGEN_SET_MSK   0x00000100
 
#define ALT_FPGAMGR_CTL_AXICFGEN_CLR_MSK   0xfffffeff
 
#define ALT_FPGAMGR_CTL_AXICFGEN_RESET   0x0
 
#define ALT_FPGAMGR_CTL_AXICFGEN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_FPGAMGR_CTL_AXICFGEN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Configuration Data Width - cfgwdth

This field determines the Configuration Passive Parallel data bus width when HPS configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel are supported.

When HPS does Normal Configuration, configuration should use 32-bit Passive Parallel Mode. The external pins MSEL must be set appropriately for the configuration selected.

For Partial Reconfiguration, 16-bit Passive Parallel must be used.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16 0x0 16-bit Passive Parallel
ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32 0x1 32-bit Passive Parallel

Field Access Macros:

#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16   0x0
 
#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32   0x1
 
#define ALT_FPGAMGR_CTL_CFGWDTH_LSB   9
 
#define ALT_FPGAMGR_CTL_CFGWDTH_MSB   9
 
#define ALT_FPGAMGR_CTL_CFGWDTH_WIDTH   1
 
#define ALT_FPGAMGR_CTL_CFGWDTH_SET_MSK   0x00000200
 
#define ALT_FPGAMGR_CTL_CFGWDTH_CLR_MSK   0xfffffdff
 
#define ALT_FPGAMGR_CTL_CFGWDTH_RESET   0x1
 
#define ALT_FPGAMGR_CTL_CFGWDTH_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_FPGAMGR_CTL_CFGWDTH_SET(value)   (((value) << 9) & 0x00000200)
 

Data Structures

struct  ALT_FPGAMGR_CTL_s
 

Macros

#define ALT_FPGAMGR_CTL_OFST   0x4
 

Typedefs

typedef struct ALT_FPGAMGR_CTL_s ALT_FPGAMGR_CTL_t
 

Data Structure Documentation

struct ALT_FPGAMGR_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_FPGAMGR_CTL.

Data Fields
uint32_t en: 1 Enable
uint32_t nce: 1 nCE
uint32_t nconfigpull: 1 nCONFIG Pull-Down
uint32_t nstatuspull: 1 nSTATUS Pull-Down
uint32_t confdonepull: 1 CONF_DONE Pull-Down
uint32_t prreq: 1 Partial Reconfiguration
uint32_t cdratio: 2 CD Ratio
uint32_t axicfgen: 1 AXI Configuration Enable
uint32_t cfgwdth: 1 Configuration Data Width
uint32_t __pad0__: 22 UNDEFINED

Macro Definitions

#define ALT_FPGAMGR_CTL_EN_E_FPGA_PINS_CTL_CFG   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_EN

FPGA configuration pins drive configuration inputs to the CB. Used when FPGA is configured by means other than the HPS.

#define ALT_FPGAMGR_CTL_EN_E_FPGAMGR_CTLS_CFG   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_EN

FPGA Manager drives configuration inputs to the CB. Used when HPS configures the FPGA.

#define ALT_FPGAMGR_CTL_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_EN register field.

#define ALT_FPGAMGR_CTL_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_EN register field.

#define ALT_FPGAMGR_CTL_EN_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_EN register field.

#define ALT_FPGAMGR_CTL_EN_SET_MSK   0x00000001

The mask used to set the ALT_FPGAMGR_CTL_EN register field value.

#define ALT_FPGAMGR_CTL_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_FPGAMGR_CTL_EN register field value.

#define ALT_FPGAMGR_CTL_EN_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_EN register field.

#define ALT_FPGAMGR_CTL_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_FPGAMGR_CTL_EN field value from a register.

#define ALT_FPGAMGR_CTL_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_FPGAMGR_CTL_EN register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_NCE_E_CFG_END   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_NCE

Configuration is enabled. The nCE to the CB is driven to 0.

#define ALT_FPGAMGR_CTL_NCE_E_CFG_DISD   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_NCE

Configuration is disabled. The nCE to the CB is driven to 1.

#define ALT_FPGAMGR_CTL_NCE_LSB   1

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCE register field.

#define ALT_FPGAMGR_CTL_NCE_MSB   1

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCE register field.

#define ALT_FPGAMGR_CTL_NCE_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_NCE register field.

#define ALT_FPGAMGR_CTL_NCE_SET_MSK   0x00000002

The mask used to set the ALT_FPGAMGR_CTL_NCE register field value.

#define ALT_FPGAMGR_CTL_NCE_CLR_MSK   0xfffffffd

The mask used to clear the ALT_FPGAMGR_CTL_NCE register field value.

#define ALT_FPGAMGR_CTL_NCE_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_NCE register field.

#define ALT_FPGAMGR_CTL_NCE_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_FPGAMGR_CTL_NCE field value from a register.

#define ALT_FPGAMGR_CTL_NCE_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_FPGAMGR_CTL_NCE register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_NCFGPULL_E_DONT_PULLDOWN   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL

Don't pull-down nCONFIG input to the CB.

#define ALT_FPGAMGR_CTL_NCFGPULL_E_PULLDOWN   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_NCFGPULL

Pull-down nCONFIG input to the CB. This puts the FPGA in reset phase and restarts configuration.

#define ALT_FPGAMGR_CTL_NCFGPULL_LSB   2

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field.

#define ALT_FPGAMGR_CTL_NCFGPULL_MSB   2

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NCFGPULL register field.

#define ALT_FPGAMGR_CTL_NCFGPULL_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_NCFGPULL register field.

#define ALT_FPGAMGR_CTL_NCFGPULL_SET_MSK   0x00000004

The mask used to set the ALT_FPGAMGR_CTL_NCFGPULL register field value.

#define ALT_FPGAMGR_CTL_NCFGPULL_CLR_MSK   0xfffffffb

The mask used to clear the ALT_FPGAMGR_CTL_NCFGPULL register field value.

#define ALT_FPGAMGR_CTL_NCFGPULL_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_NCFGPULL register field.

#define ALT_FPGAMGR_CTL_NCFGPULL_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_FPGAMGR_CTL_NCFGPULL field value from a register.

#define ALT_FPGAMGR_CTL_NCFGPULL_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_FPGAMGR_CTL_NCFGPULL register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_NSTATPULL_E_DONT_PULLDOWN   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL

Don't pull-down nSTATUS input to the CB.

#define ALT_FPGAMGR_CTL_NSTATPULL_E_PULLDOWN   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_NSTATPULL

Pull-down nSTATUS input to the CB.

#define ALT_FPGAMGR_CTL_NSTATPULL_LSB   3

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field.

#define ALT_FPGAMGR_CTL_NSTATPULL_MSB   3

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_NSTATPULL register field.

#define ALT_FPGAMGR_CTL_NSTATPULL_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_NSTATPULL register field.

#define ALT_FPGAMGR_CTL_NSTATPULL_SET_MSK   0x00000008

The mask used to set the ALT_FPGAMGR_CTL_NSTATPULL register field value.

#define ALT_FPGAMGR_CTL_NSTATPULL_CLR_MSK   0xfffffff7

The mask used to clear the ALT_FPGAMGR_CTL_NSTATPULL register field value.

#define ALT_FPGAMGR_CTL_NSTATPULL_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_NSTATPULL register field.

#define ALT_FPGAMGR_CTL_NSTATPULL_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_FPGAMGR_CTL_NSTATPULL field value from a register.

#define ALT_FPGAMGR_CTL_NSTATPULL_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_FPGAMGR_CTL_NSTATPULL register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_DONT_PULLDOWN   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL

Don't pull-down CONF_DONE input to the CB.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_E_PULLDOWN   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_CONFDONEPULL

Pull-down CONF_DONE input to the CB.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_LSB   4

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_MSB   4

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CONFDONEPULL register field.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_CONFDONEPULL register field.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET_MSK   0x00000010

The mask used to set the ALT_FPGAMGR_CTL_CONFDONEPULL register field value.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_CLR_MSK   0xffffffef

The mask used to clear the ALT_FPGAMGR_CTL_CONFDONEPULL register field value.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_CONFDONEPULL register field.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_FPGAMGR_CTL_CONFDONEPULL field value from a register.

#define ALT_FPGAMGR_CTL_CONFDONEPULL_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_FPGAMGR_CTL_CONFDONEPULL register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_PRREQ_E_DEASSERT   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ

De-assert PR_REQUEST (driven to 0).

#define ALT_FPGAMGR_CTL_PRREQ_E_ASSERT   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_PRREQ

Assert PR_REQUEST (driven to 1).

#define ALT_FPGAMGR_CTL_PRREQ_LSB   5

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_PRREQ register field.

#define ALT_FPGAMGR_CTL_PRREQ_MSB   5

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_PRREQ register field.

#define ALT_FPGAMGR_CTL_PRREQ_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_PRREQ register field.

#define ALT_FPGAMGR_CTL_PRREQ_SET_MSK   0x00000020

The mask used to set the ALT_FPGAMGR_CTL_PRREQ register field value.

#define ALT_FPGAMGR_CTL_PRREQ_CLR_MSK   0xffffffdf

The mask used to clear the ALT_FPGAMGR_CTL_PRREQ register field value.

#define ALT_FPGAMGR_CTL_PRREQ_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_PRREQ register field.

#define ALT_FPGAMGR_CTL_PRREQ_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_FPGAMGR_CTL_PRREQ field value from a register.

#define ALT_FPGAMGR_CTL_PRREQ_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_FPGAMGR_CTL_PRREQ register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_CDRATIO_E_X1   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO

CDRATIO of 1

#define ALT_FPGAMGR_CTL_CDRATIO_E_X2   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO

CDRATIO of 2

#define ALT_FPGAMGR_CTL_CDRATIO_E_X4   0x2

Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO

CDRATIO of 4

#define ALT_FPGAMGR_CTL_CDRATIO_E_X8   0x3

Enumerated value for register field ALT_FPGAMGR_CTL_CDRATIO

CDRATIO of 8

#define ALT_FPGAMGR_CTL_CDRATIO_LSB   6

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field.

#define ALT_FPGAMGR_CTL_CDRATIO_MSB   7

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CDRATIO register field.

#define ALT_FPGAMGR_CTL_CDRATIO_WIDTH   2

The width in bits of the ALT_FPGAMGR_CTL_CDRATIO register field.

#define ALT_FPGAMGR_CTL_CDRATIO_SET_MSK   0x000000c0

The mask used to set the ALT_FPGAMGR_CTL_CDRATIO register field value.

#define ALT_FPGAMGR_CTL_CDRATIO_CLR_MSK   0xffffff3f

The mask used to clear the ALT_FPGAMGR_CTL_CDRATIO register field value.

#define ALT_FPGAMGR_CTL_CDRATIO_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_CDRATIO register field.

#define ALT_FPGAMGR_CTL_CDRATIO_GET (   value)    (((value) & 0x000000c0) >> 6)

Extracts the ALT_FPGAMGR_CTL_CDRATIO field value from a register.

#define ALT_FPGAMGR_CTL_CDRATIO_SET (   value)    (((value) << 6) & 0x000000c0)

Produces a ALT_FPGAMGR_CTL_CDRATIO register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_AXICFGEN_E_DISD   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN

Incoming AXI data transfers will be ignored. DCLK will not toggle during data transfer.

#define ALT_FPGAMGR_CTL_AXICFGEN_E_END   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_AXICFGEN

AXI data transfer to CB is active. DCLK will toggle during data transfer.

#define ALT_FPGAMGR_CTL_AXICFGEN_LSB   8

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field.

#define ALT_FPGAMGR_CTL_AXICFGEN_MSB   8

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_AXICFGEN register field.

#define ALT_FPGAMGR_CTL_AXICFGEN_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_AXICFGEN register field.

#define ALT_FPGAMGR_CTL_AXICFGEN_SET_MSK   0x00000100

The mask used to set the ALT_FPGAMGR_CTL_AXICFGEN register field value.

#define ALT_FPGAMGR_CTL_AXICFGEN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_FPGAMGR_CTL_AXICFGEN register field value.

#define ALT_FPGAMGR_CTL_AXICFGEN_RESET   0x0

The reset value of the ALT_FPGAMGR_CTL_AXICFGEN register field.

#define ALT_FPGAMGR_CTL_AXICFGEN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_FPGAMGR_CTL_AXICFGEN field value from a register.

#define ALT_FPGAMGR_CTL_AXICFGEN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_FPGAMGR_CTL_AXICFGEN register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX16   0x0

Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH

16-bit Passive Parallel

#define ALT_FPGAMGR_CTL_CFGWDTH_E_PPX32   0x1

Enumerated value for register field ALT_FPGAMGR_CTL_CFGWDTH

32-bit Passive Parallel

#define ALT_FPGAMGR_CTL_CFGWDTH_LSB   9

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field.

#define ALT_FPGAMGR_CTL_CFGWDTH_MSB   9

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_CTL_CFGWDTH register field.

#define ALT_FPGAMGR_CTL_CFGWDTH_WIDTH   1

The width in bits of the ALT_FPGAMGR_CTL_CFGWDTH register field.

#define ALT_FPGAMGR_CTL_CFGWDTH_SET_MSK   0x00000200

The mask used to set the ALT_FPGAMGR_CTL_CFGWDTH register field value.

#define ALT_FPGAMGR_CTL_CFGWDTH_CLR_MSK   0xfffffdff

The mask used to clear the ALT_FPGAMGR_CTL_CFGWDTH register field value.

#define ALT_FPGAMGR_CTL_CFGWDTH_RESET   0x1

The reset value of the ALT_FPGAMGR_CTL_CFGWDTH register field.

#define ALT_FPGAMGR_CTL_CFGWDTH_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_FPGAMGR_CTL_CFGWDTH field value from a register.

#define ALT_FPGAMGR_CTL_CFGWDTH_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_FPGAMGR_CTL_CFGWDTH register field value suitable for setting the register.

#define ALT_FPGAMGR_CTL_OFST   0x4

The byte offset of the ALT_FPGAMGR_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_FPGAMGR_CTL.