Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Debug clock Control Register - dbctrl

Description

Contains fields that control the debug clocks.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Debug Clocks Stay on EOSC1_CLK
[1] RW 0x1 Debug Clocks Enable Safe Mode
[31:2] ??? 0x0 UNDEFINED

Field : Debug Clocks Stay on EOSC1_CLK - stayosc1

When this bit is set the debug root clock (Main PLL C2 output) will always be bypassed to the EOSC1_clk independent of any other clock manager settings. When clear the debug source will be a function of register settings in the clock manager. Clocks affected by this bit are dbg_at_clk, dbg_clk, dbg_trace_clk, and dbg_timer_clk.

The reset value for this bit is applied on a cold reset. Warm reset has no affect on this bit.

Field Access Macros:

#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB   0
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB   0
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH   1
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK   0x00000001
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET   0x1
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Debug Clocks Enable Safe Mode - ensfmdwr

When this bit is set the debug clocks will be affected by the assertion of Safe Mode on a warm reset if Stay OSC1 is not set.

When this bit is clear the debug clocks will not be affected by the assertion of Safe Mode on a warm reset.

If Debug Clocks are in Safe Mode they are taken out of Safe Mode when the Safe Mode bit is cleared independent of this bit.The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit.

Field Access Macros:

#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB   1
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB   1
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH   1
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK   0x00000002
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK   0xfffffffd
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET   0x1
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value)   (((value) << 1) & 0x00000002)
 

Data Structures

struct  ALT_CLKMGR_DBCTL_s
 

Macros

#define ALT_CLKMGR_DBCTL_OFST   0x10
 

Typedefs

typedef struct ALT_CLKMGR_DBCTL_s ALT_CLKMGR_DBCTL_t
 

Data Structure Documentation

struct ALT_CLKMGR_DBCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_DBCTL.

Data Fields
uint32_t stayosc1: 1 Debug Clocks Stay on EOSC1_CLK
uint32_t ensfmdwr: 1 Debug Clocks Enable Safe Mode
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field.

#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_STAYOSC1 register field.

#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH   1

The width in bits of the ALT_CLKMGR_DBCTL_STAYOSC1 register field.

#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_DBCTL_STAYOSC1 register field value.

#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_DBCTL_STAYOSC1 register field value.

#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET   0x1

The reset value of the ALT_CLKMGR_DBCTL_STAYOSC1 register field.

#define ALT_CLKMGR_DBCTL_STAYOSC1_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_DBCTL_STAYOSC1 field value from a register.

#define ALT_CLKMGR_DBCTL_STAYOSC1_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_DBCTL_STAYOSC1 register field value suitable for setting the register.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB   1

The Least Significant Bit (LSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB   1

The Most Significant Bit (MSB) position of the ALT_CLKMGR_DBCTL_ENSFMDWR register field.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH   1

The width in bits of the ALT_CLKMGR_DBCTL_ENSFMDWR register field.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK   0x00000002

The mask used to set the ALT_CLKMGR_DBCTL_ENSFMDWR register field value.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK   0xfffffffd

The mask used to clear the ALT_CLKMGR_DBCTL_ENSFMDWR register field value.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET   0x1

The reset value of the ALT_CLKMGR_DBCTL_ENSFMDWR register field.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_CLKMGR_DBCTL_ENSFMDWR field value from a register.

#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_CLKMGR_DBCTL_ENSFMDWR register field value suitable for setting the register.

#define ALT_CLKMGR_DBCTL_OFST   0x10

The byte offset of the ALT_CLKMGR_DBCTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_DBCTL.