Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Interrupt Enable and Divisor Latch High - ier_dlh

Description

This is a multi-function register. This register enables/disables receive and transmit interrupts and also controls the most-significant 8-bits of the baud rate divisor.

Divisor Latch High Register:

This register is accessed when the DLAB bit [7] of the LCR Register is set to 1.Bits[7:0] contain the high order 8-bits of the baud rate divisor.The output baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen times the value of the baud rate divisor, as follows:

baud rate = (serial clock freq) / (16 * divisor):

Note that with the Divisor Latch Registers (DLLand DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 l4_sp_clk clock cycles should be allowed to pass before transmitting or receiving data.

Interrupt Enable Register:

This register may only be accessed when the DLAB bit [7] of the LCR Register is set to 0.Allows control of the Interrupt Enables for transmit and receive functions.

Register Layout

Bits Access Reset Description
[0] RW 0x0 DLH[0] and Receive Data Interrupt Enable
[1] RW 0x0 DLH[1] and Transmit Data Interrupt Control
[2] RW 0x0 DLH[2] and Enable Receiver Line Status
[3] RW 0x0 DLH[3] and Enable Modem Status Interrupt
[4] RW 0x0 DLH[4]
[5] RW 0x0 DLH[5]
[6] RW 0x0 DLH[6]
[7] RW 0x0 DLH[7] and PTIME THRE Interrupt Mode Enable
[31:8] ??? 0x0 UNDEFINED

Field : DLH[0] and Receive Data Interrupt Enable - erbfi_dlh0

Divisor Latch High Register:

Bit 0 of DLH value.

Interrupt Enable Register:

Used to enable/disable the generation of the Receive Data Available Interrupt and the Character Timeout Interrupt(if FIFO's enabled). These are the second highest priority interrupts.

Field Enumeration Values:

Enum Value Description
ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD 0x0 Interrupt Disable
ALT_UART_IER_DLH_ERBFI_DLH0_E_END 0x1 Interrupt Enable

Field Access Macros:

#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD   0x0
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END   0x1
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB   0
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB   0
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH   1
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK   0x00000001
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK   0xfffffffe
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET   0x0
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_UART_IER_DLH_ERBFI_DLH0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : DLH[1] and Transmit Data Interrupt Control - etbei_dlhl

Divisor Latch High Register:

Bit 1 of DLH value.

Interrupt Enable Register:

Enable Transmit Holding Register Empty Interrupt. This is used to enable/disable the generation of Transmitter Holding Register Empty Interrupt. This is the third highest priority interrupt.

Field Enumeration Values:

Enum Value Description
ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD 0x0 Tx disable
ALT_UART_IER_DLH_ETBEI_DLHL_E_END 0x1 Tx enable

Field Access Macros:

#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD   0x0
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END   0x1
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB   1
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB   1
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH   1
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK   0x00000002
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK   0xfffffffd
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET   0x0
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_UART_IER_DLH_ETBEI_DLHL_SET(value)   (((value) << 1) & 0x00000002)
 

Field : DLH[2] and Enable Receiver Line Status - elsi_dhl2

Divisor Latch High Register:

Bit 2 of DLH value.

Interrupt Enable Register:

This is used to enable/disable the generation of Receiver Line Status Interrupt. This is the highest priority interrupt.

Field Enumeration Values:

Enum Value Description
ALT_UART_IER_DLH_ELSI_DHL2_E_DISD 0x0 Disable interrupt line stat
ALT_UART_IER_DLH_ELSI_DHL2_E_END 0x1 Enable interrupt line stat

Field Access Macros:

#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD   0x0
 
#define ALT_UART_IER_DLH_ELSI_DHL2_E_END   0x1
 
#define ALT_UART_IER_DLH_ELSI_DHL2_LSB   2
 
#define ALT_UART_IER_DLH_ELSI_DHL2_MSB   2
 
#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH   1
 
#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK   0x00000004
 
#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK   0xfffffffb
 
#define ALT_UART_IER_DLH_ELSI_DHL2_RESET   0x0
 
#define ALT_UART_IER_DLH_ELSI_DHL2_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_UART_IER_DLH_ELSI_DHL2_SET(value)   (((value) << 2) & 0x00000004)
 

Field : DLH[3] and Enable Modem Status Interrupt - edssi_dhl3

Divisor Latch High Register:

Bit 3 of DLH value.

Interrupt Enable Register:

This is used to enable/disable the generation of Modem Status Interrupts. This is the fourth highest priority interrupt.

Field Enumeration Values:

Enum Value Description
ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD 0x0 disable modem status interrupt
ALT_UART_IER_DLH_EDSSI_DHL3_E_END 0x1 enable modem status interrupt

Field Access Macros:

#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD   0x0
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END   0x1
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB   3
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB   3
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH   1
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK   0x00000008
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK   0xfffffff7
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET   0x0
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_UART_IER_DLH_EDSSI_DHL3_SET(value)   (((value) << 3) & 0x00000008)
 

Field : DLH[4] - dlh4

Bit 4 of DLH value.

Field Access Macros:

#define ALT_UART_IER_DLH_DLH4_LSB   4
 
#define ALT_UART_IER_DLH_DLH4_MSB   4
 
#define ALT_UART_IER_DLH_DLH4_WIDTH   1
 
#define ALT_UART_IER_DLH_DLH4_SET_MSK   0x00000010
 
#define ALT_UART_IER_DLH_DLH4_CLR_MSK   0xffffffef
 
#define ALT_UART_IER_DLH_DLH4_RESET   0x0
 
#define ALT_UART_IER_DLH_DLH4_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_UART_IER_DLH_DLH4_SET(value)   (((value) << 4) & 0x00000010)
 

Field : DLH[5] - dlh5

Bit 5 of DLH value.

Field Access Macros:

#define ALT_UART_IER_DLH_DLH5_LSB   5
 
#define ALT_UART_IER_DLH_DLH5_MSB   5
 
#define ALT_UART_IER_DLH_DLH5_WIDTH   1
 
#define ALT_UART_IER_DLH_DLH5_SET_MSK   0x00000020
 
#define ALT_UART_IER_DLH_DLH5_CLR_MSK   0xffffffdf
 
#define ALT_UART_IER_DLH_DLH5_RESET   0x0
 
#define ALT_UART_IER_DLH_DLH5_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_UART_IER_DLH_DLH5_SET(value)   (((value) << 5) & 0x00000020)
 

Field : DLH[6] - dlh6

Bit 6 of DLH value.

Field Access Macros:

#define ALT_UART_IER_DLH_DLH6_LSB   6
 
#define ALT_UART_IER_DLH_DLH6_MSB   6
 
#define ALT_UART_IER_DLH_DLH6_WIDTH   1
 
#define ALT_UART_IER_DLH_DLH6_SET_MSK   0x00000040
 
#define ALT_UART_IER_DLH_DLH6_CLR_MSK   0xffffffbf
 
#define ALT_UART_IER_DLH_DLH6_RESET   0x0
 
#define ALT_UART_IER_DLH_DLH6_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_UART_IER_DLH_DLH6_SET(value)   (((value) << 6) & 0x00000040)
 

Field : DLH[7] and PTIME THRE Interrupt Mode Enable - ptime_dlh7

Divisor Latch High Register:

Bit 7 of DLH value.

Interrupt Enable Register:

This is used to enable/disable the generation of THRE Interrupt.

Field Enumeration Values:

Enum Value Description
ALT_UART_IER_DLH_PTIME_DLH7_E_DISD 0x0 disable tx-hold-reg-empty interrupt
ALT_UART_IER_DLH_PTIME_DLH7_E_END 0x1 enable tx-hold-reg-empty interrupt

Field Access Macros:

#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD   0x0
 
#define ALT_UART_IER_DLH_PTIME_DLH7_E_END   0x1
 
#define ALT_UART_IER_DLH_PTIME_DLH7_LSB   7
 
#define ALT_UART_IER_DLH_PTIME_DLH7_MSB   7
 
#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH   1
 
#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK   0x00000080
 
#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK   0xffffff7f
 
#define ALT_UART_IER_DLH_PTIME_DLH7_RESET   0x0
 
#define ALT_UART_IER_DLH_PTIME_DLH7_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_UART_IER_DLH_PTIME_DLH7_SET(value)   (((value) << 7) & 0x00000080)
 

Data Structures

struct  ALT_UART_IER_DLH_s
 

Macros

#define ALT_UART_IER_DLH_OFST   0x4
 
#define ALT_UART_IER_DLH_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))
 

Typedefs

typedef struct ALT_UART_IER_DLH_s ALT_UART_IER_DLH_t
 

Data Structure Documentation

struct ALT_UART_IER_DLH_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_IER_DLH.

Data Fields
uint32_t erbfi_dlh0: 1 DLH[0] and Receive Data Interrupt Enable
uint32_t etbei_dlhl: 1 DLH[1] and Transmit Data Interrupt Control
uint32_t elsi_dhl2: 1 DLH[2] and Enable Receiver Line Status
uint32_t edssi_dhl3: 1 DLH[3] and Enable Modem Status Interrupt
uint32_t dlh4: 1 DLH[4]
uint32_t dlh5: 1 DLH[5]
uint32_t dlh6: 1 DLH[6]
uint32_t ptime_dlh7: 1 DLH[7] and PTIME THRE Interrupt Mode Enable
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_UART_IER_DLH_ERBFI_DLH0_E_DISD   0x0

Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0

Interrupt Disable

#define ALT_UART_IER_DLH_ERBFI_DLH0_E_END   0x1

Enumerated value for register field ALT_UART_IER_DLH_ERBFI_DLH0

Interrupt Enable

#define ALT_UART_IER_DLH_ERBFI_DLH0_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field.

#define ALT_UART_IER_DLH_ERBFI_DLH0_MSB   0

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ERBFI_DLH0 register field.

#define ALT_UART_IER_DLH_ERBFI_DLH0_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_ERBFI_DLH0 register field.

#define ALT_UART_IER_DLH_ERBFI_DLH0_SET_MSK   0x00000001

The mask used to set the ALT_UART_IER_DLH_ERBFI_DLH0 register field value.

#define ALT_UART_IER_DLH_ERBFI_DLH0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_UART_IER_DLH_ERBFI_DLH0 register field value.

#define ALT_UART_IER_DLH_ERBFI_DLH0_RESET   0x0

The reset value of the ALT_UART_IER_DLH_ERBFI_DLH0 register field.

#define ALT_UART_IER_DLH_ERBFI_DLH0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_UART_IER_DLH_ERBFI_DLH0 field value from a register.

#define ALT_UART_IER_DLH_ERBFI_DLH0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_UART_IER_DLH_ERBFI_DLH0 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_ETBEI_DLHL_E_DISD   0x0

Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL

Tx disable

#define ALT_UART_IER_DLH_ETBEI_DLHL_E_END   0x1

Enumerated value for register field ALT_UART_IER_DLH_ETBEI_DLHL

Tx enable

#define ALT_UART_IER_DLH_ETBEI_DLHL_LSB   1

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field.

#define ALT_UART_IER_DLH_ETBEI_DLHL_MSB   1

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ETBEI_DLHL register field.

#define ALT_UART_IER_DLH_ETBEI_DLHL_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_ETBEI_DLHL register field.

#define ALT_UART_IER_DLH_ETBEI_DLHL_SET_MSK   0x00000002

The mask used to set the ALT_UART_IER_DLH_ETBEI_DLHL register field value.

#define ALT_UART_IER_DLH_ETBEI_DLHL_CLR_MSK   0xfffffffd

The mask used to clear the ALT_UART_IER_DLH_ETBEI_DLHL register field value.

#define ALT_UART_IER_DLH_ETBEI_DLHL_RESET   0x0

The reset value of the ALT_UART_IER_DLH_ETBEI_DLHL register field.

#define ALT_UART_IER_DLH_ETBEI_DLHL_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_UART_IER_DLH_ETBEI_DLHL field value from a register.

#define ALT_UART_IER_DLH_ETBEI_DLHL_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_UART_IER_DLH_ETBEI_DLHL register field value suitable for setting the register.

#define ALT_UART_IER_DLH_ELSI_DHL2_E_DISD   0x0

Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2

Disable interrupt line stat

#define ALT_UART_IER_DLH_ELSI_DHL2_E_END   0x1

Enumerated value for register field ALT_UART_IER_DLH_ELSI_DHL2

Enable interrupt line stat

#define ALT_UART_IER_DLH_ELSI_DHL2_LSB   2

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field.

#define ALT_UART_IER_DLH_ELSI_DHL2_MSB   2

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_ELSI_DHL2 register field.

#define ALT_UART_IER_DLH_ELSI_DHL2_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_ELSI_DHL2 register field.

#define ALT_UART_IER_DLH_ELSI_DHL2_SET_MSK   0x00000004

The mask used to set the ALT_UART_IER_DLH_ELSI_DHL2 register field value.

#define ALT_UART_IER_DLH_ELSI_DHL2_CLR_MSK   0xfffffffb

The mask used to clear the ALT_UART_IER_DLH_ELSI_DHL2 register field value.

#define ALT_UART_IER_DLH_ELSI_DHL2_RESET   0x0

The reset value of the ALT_UART_IER_DLH_ELSI_DHL2 register field.

#define ALT_UART_IER_DLH_ELSI_DHL2_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_UART_IER_DLH_ELSI_DHL2 field value from a register.

#define ALT_UART_IER_DLH_ELSI_DHL2_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_UART_IER_DLH_ELSI_DHL2 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_EDSSI_DHL3_E_DISD   0x0

Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3

disable modem status interrupt

#define ALT_UART_IER_DLH_EDSSI_DHL3_E_END   0x1

Enumerated value for register field ALT_UART_IER_DLH_EDSSI_DHL3

enable modem status interrupt

#define ALT_UART_IER_DLH_EDSSI_DHL3_LSB   3

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field.

#define ALT_UART_IER_DLH_EDSSI_DHL3_MSB   3

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_EDSSI_DHL3 register field.

#define ALT_UART_IER_DLH_EDSSI_DHL3_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_EDSSI_DHL3 register field.

#define ALT_UART_IER_DLH_EDSSI_DHL3_SET_MSK   0x00000008

The mask used to set the ALT_UART_IER_DLH_EDSSI_DHL3 register field value.

#define ALT_UART_IER_DLH_EDSSI_DHL3_CLR_MSK   0xfffffff7

The mask used to clear the ALT_UART_IER_DLH_EDSSI_DHL3 register field value.

#define ALT_UART_IER_DLH_EDSSI_DHL3_RESET   0x0

The reset value of the ALT_UART_IER_DLH_EDSSI_DHL3 register field.

#define ALT_UART_IER_DLH_EDSSI_DHL3_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_UART_IER_DLH_EDSSI_DHL3 field value from a register.

#define ALT_UART_IER_DLH_EDSSI_DHL3_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_UART_IER_DLH_EDSSI_DHL3 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_DLH4_LSB   4

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH4 register field.

#define ALT_UART_IER_DLH_DLH4_MSB   4

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH4 register field.

#define ALT_UART_IER_DLH_DLH4_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_DLH4 register field.

#define ALT_UART_IER_DLH_DLH4_SET_MSK   0x00000010

The mask used to set the ALT_UART_IER_DLH_DLH4 register field value.

#define ALT_UART_IER_DLH_DLH4_CLR_MSK   0xffffffef

The mask used to clear the ALT_UART_IER_DLH_DLH4 register field value.

#define ALT_UART_IER_DLH_DLH4_RESET   0x0

The reset value of the ALT_UART_IER_DLH_DLH4 register field.

#define ALT_UART_IER_DLH_DLH4_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_UART_IER_DLH_DLH4 field value from a register.

#define ALT_UART_IER_DLH_DLH4_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_UART_IER_DLH_DLH4 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_DLH5_LSB   5

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH5 register field.

#define ALT_UART_IER_DLH_DLH5_MSB   5

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH5 register field.

#define ALT_UART_IER_DLH_DLH5_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_DLH5 register field.

#define ALT_UART_IER_DLH_DLH5_SET_MSK   0x00000020

The mask used to set the ALT_UART_IER_DLH_DLH5 register field value.

#define ALT_UART_IER_DLH_DLH5_CLR_MSK   0xffffffdf

The mask used to clear the ALT_UART_IER_DLH_DLH5 register field value.

#define ALT_UART_IER_DLH_DLH5_RESET   0x0

The reset value of the ALT_UART_IER_DLH_DLH5 register field.

#define ALT_UART_IER_DLH_DLH5_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_UART_IER_DLH_DLH5 field value from a register.

#define ALT_UART_IER_DLH_DLH5_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_UART_IER_DLH_DLH5 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_DLH6_LSB   6

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_DLH6 register field.

#define ALT_UART_IER_DLH_DLH6_MSB   6

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_DLH6 register field.

#define ALT_UART_IER_DLH_DLH6_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_DLH6 register field.

#define ALT_UART_IER_DLH_DLH6_SET_MSK   0x00000040

The mask used to set the ALT_UART_IER_DLH_DLH6 register field value.

#define ALT_UART_IER_DLH_DLH6_CLR_MSK   0xffffffbf

The mask used to clear the ALT_UART_IER_DLH_DLH6 register field value.

#define ALT_UART_IER_DLH_DLH6_RESET   0x0

The reset value of the ALT_UART_IER_DLH_DLH6 register field.

#define ALT_UART_IER_DLH_DLH6_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_UART_IER_DLH_DLH6 field value from a register.

#define ALT_UART_IER_DLH_DLH6_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_UART_IER_DLH_DLH6 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_PTIME_DLH7_E_DISD   0x0

Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7

disable tx-hold-reg-empty interrupt

#define ALT_UART_IER_DLH_PTIME_DLH7_E_END   0x1

Enumerated value for register field ALT_UART_IER_DLH_PTIME_DLH7

enable tx-hold-reg-empty interrupt

#define ALT_UART_IER_DLH_PTIME_DLH7_LSB   7

The Least Significant Bit (LSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field.

#define ALT_UART_IER_DLH_PTIME_DLH7_MSB   7

The Most Significant Bit (MSB) position of the ALT_UART_IER_DLH_PTIME_DLH7 register field.

#define ALT_UART_IER_DLH_PTIME_DLH7_WIDTH   1

The width in bits of the ALT_UART_IER_DLH_PTIME_DLH7 register field.

#define ALT_UART_IER_DLH_PTIME_DLH7_SET_MSK   0x00000080

The mask used to set the ALT_UART_IER_DLH_PTIME_DLH7 register field value.

#define ALT_UART_IER_DLH_PTIME_DLH7_CLR_MSK   0xffffff7f

The mask used to clear the ALT_UART_IER_DLH_PTIME_DLH7 register field value.

#define ALT_UART_IER_DLH_PTIME_DLH7_RESET   0x0

The reset value of the ALT_UART_IER_DLH_PTIME_DLH7 register field.

#define ALT_UART_IER_DLH_PTIME_DLH7_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_UART_IER_DLH_PTIME_DLH7 field value from a register.

#define ALT_UART_IER_DLH_PTIME_DLH7_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_UART_IER_DLH_PTIME_DLH7 register field value suitable for setting the register.

#define ALT_UART_IER_DLH_OFST   0x4

The byte offset of the ALT_UART_IER_DLH register from the beginning of the component.

#define ALT_UART_IER_DLH_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_IER_DLH_OFST))

The address of the ALT_UART_IER_DLH register.

Typedef Documentation

The typedef declaration for register ALT_UART_IER_DLH.