Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : uhs_reg_ext

Description

UHS Register Extention

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG
[22:16] RW 0x0 ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL
[29:23] RW 0x0 ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL
[31:30] RW 0x0 ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL

Field : mmc_volt_reg

Support for 1.2V. MMC_VOLT_REG bits; must be read in combination

with UHS_VOLT_REG to decode output selected voltage.

The biu_volt_reg_1_2[NUM_CARD_BUS-1:0] signal decodes the voltage combination selected for the I/O voltage logic.

Host controllers that support only SD standard or standard versions before eMMC4.41 do not program MMC_VOLT_REG.

Only host controllers that support all three versions3.3,1.8,1.2 Vcan program MMC_VOLT_REG and connect biu_volt_reg_1_2.

Field Access Macros:

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_LSB   0
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_MSB   15
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_WIDTH   16
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET_MSK   0x0000ffff
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_CLR_MSK   0xffff0000
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : clk_smpl_phase_ctrl

Control for amount of phase shift on cclk_in_sample clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively, use only LSBs.

Field Access Macros:

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_LSB   16
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_MSB   22
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_WIDTH   7
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET_MSK   0x007f0000
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_CLR_MSK   0xff80ffff
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_GET(value)   (((value) & 0x007f0000) >> 16)
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET(value)   (((value) << 16) & 0x007f0000)
 

Field : clk_drv_phase_ctrl

Control for amount of phase shift on cclk_in_drv clock. Can choose three MSBs to control delay lines and four LSBs to control phase shift; alternatively, use only LSBs.

Field Access Macros:

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_LSB   23
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_MSB   29
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_WIDTH   7
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET_MSK   0x3f800000
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_CLR_MSK   0xc07fffff
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_GET(value)   (((value) & 0x3f800000) >> 23)
 
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET(value)   (((value) << 23) & 0x3f800000)
 

Field : ext_clk_mux_ctrl

Input clock control for cclk_in. The MUX controlled by these bits exists outside DWC_mobile_storage IP.

Field Access Macros:

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_LSB   30
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_MSB   31
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_WIDTH   2
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET_MSK   0xc0000000
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_CLR_MSK   0x3fffffff
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_GET(value)   (((value) & 0xc0000000) >> 30)
 
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET(value)   (((value) << 30) & 0xc0000000)
 

Data Structures

struct  ALT_SDMMC_UHS_REG_EXT_s
 

Macros

#define ALT_SDMMC_UHS_REG_EXT_RESET   0x00000000
 
#define ALT_SDMMC_UHS_REG_EXT_OFST   0x108
 

Typedefs

typedef struct
ALT_SDMMC_UHS_REG_EXT_s 
ALT_SDMMC_UHS_REG_EXT_t
 

Data Structure Documentation

struct ALT_SDMMC_UHS_REG_EXT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_UHS_REG_EXT.

Data Fields
uint32_t mmc_volt_reg: 16 ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG
uint32_t clk_smpl_phase_ctrl: 7 ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL
uint32_t clk_drv_phase_ctrl: 7 ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL
uint32_t ext_clk_mux_ctrl: 2 ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL

Macro Definitions

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_WIDTH   16

The width in bits of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET_MSK   0x0000ffff

The mask used to set the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_CLR_MSK   0xffff0000

The mask used to clear the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG field value from a register.

#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_MSB   22

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_WIDTH   7

The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET_MSK   0x007f0000

The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_CLR_MSK   0xff80ffff

The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_GET (   value)    (((value) & 0x007f0000) >> 16)

Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL field value from a register.

#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET (   value)    (((value) << 16) & 0x007f0000)

Produces a ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_LSB   23

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_MSB   29

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_WIDTH   7

The width in bits of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET_MSK   0x3f800000

The mask used to set the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_CLR_MSK   0xc07fffff

The mask used to clear the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_GET (   value)    (((value) & 0x3f800000) >> 23)

Extracts the ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL field value from a register.

#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET (   value)    (((value) << 23) & 0x3f800000)

Produces a ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_LSB   30

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_MSB   31

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_WIDTH   2

The width in bits of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET_MSK   0xc0000000

The mask used to set the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_CLR_MSK   0x3fffffff

The mask used to clear the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_GET (   value)    (((value) & 0xc0000000) >> 30)

Extracts the ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL field value from a register.

#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET (   value)    (((value) << 30) & 0xc0000000)

Produces a ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_EXT_RESET   0x00000000

The reset value of the ALT_SDMMC_UHS_REG_EXT register.

#define ALT_SDMMC_UHS_REG_EXT_OFST   0x108

The byte offset of the ALT_SDMMC_UHS_REG_EXT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_UHS_REG_EXT.