Altera SoCAL  16.0
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alt_rstmgr.h
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32 
35 #ifndef __ALTERA_ALT_RSTMGR_H__
36 #define __ALTERA_ALT_RSTMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
111 #define ALT_RSTMGR_STAT_PORVOLTRST_LSB 0
112 
113 #define ALT_RSTMGR_STAT_PORVOLTRST_MSB 0
114 
115 #define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH 1
116 
117 #define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK 0x00000001
118 
119 #define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK 0xfffffffe
120 
121 #define ALT_RSTMGR_STAT_PORVOLTRST_RESET 0x0
122 
123 #define ALT_RSTMGR_STAT_PORVOLTRST_GET(value) (((value) & 0x00000001) >> 0)
124 
125 #define ALT_RSTMGR_STAT_PORVOLTRST_SET(value) (((value) << 0) & 0x00000001)
126 
136 #define ALT_RSTMGR_STAT_NPORPINRST_LSB 1
137 
138 #define ALT_RSTMGR_STAT_NPORPINRST_MSB 1
139 
140 #define ALT_RSTMGR_STAT_NPORPINRST_WIDTH 1
141 
142 #define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK 0x00000002
143 
144 #define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK 0xfffffffd
145 
146 #define ALT_RSTMGR_STAT_NPORPINRST_RESET 0x0
147 
148 #define ALT_RSTMGR_STAT_NPORPINRST_GET(value) (((value) & 0x00000002) >> 1)
149 
150 #define ALT_RSTMGR_STAT_NPORPINRST_SET(value) (((value) << 1) & 0x00000002)
151 
161 #define ALT_RSTMGR_STAT_FPGACOLDRST_LSB 2
162 
163 #define ALT_RSTMGR_STAT_FPGACOLDRST_MSB 2
164 
165 #define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH 1
166 
167 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK 0x00000004
168 
169 #define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK 0xfffffffb
170 
171 #define ALT_RSTMGR_STAT_FPGACOLDRST_RESET 0x0
172 
173 #define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value) (((value) & 0x00000004) >> 2)
174 
175 #define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value) (((value) << 2) & 0x00000004)
176 
186 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB 3
187 
188 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB 3
189 
190 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH 1
191 
192 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK 0x00000008
193 
194 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK 0xfffffff7
195 
196 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET 0x0
197 
198 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value) (((value) & 0x00000008) >> 3)
199 
200 #define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value) (((value) << 3) & 0x00000008)
201 
211 #define ALT_RSTMGR_STAT_SWCOLDRST_LSB 4
212 
213 #define ALT_RSTMGR_STAT_SWCOLDRST_MSB 4
214 
215 #define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH 1
216 
217 #define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK 0x00000010
218 
219 #define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK 0xffffffef
220 
221 #define ALT_RSTMGR_STAT_SWCOLDRST_RESET 0x0
222 
223 #define ALT_RSTMGR_STAT_SWCOLDRST_GET(value) (((value) & 0x00000010) >> 4)
224 
225 #define ALT_RSTMGR_STAT_SWCOLDRST_SET(value) (((value) << 4) & 0x00000010)
226 
236 #define ALT_RSTMGR_STAT_NRSTPINRST_LSB 8
237 
238 #define ALT_RSTMGR_STAT_NRSTPINRST_MSB 8
239 
240 #define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH 1
241 
242 #define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK 0x00000100
243 
244 #define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK 0xfffffeff
245 
246 #define ALT_RSTMGR_STAT_NRSTPINRST_RESET 0x0
247 
248 #define ALT_RSTMGR_STAT_NRSTPINRST_GET(value) (((value) & 0x00000100) >> 8)
249 
250 #define ALT_RSTMGR_STAT_NRSTPINRST_SET(value) (((value) << 8) & 0x00000100)
251 
261 #define ALT_RSTMGR_STAT_FPGAWARMRST_LSB 9
262 
263 #define ALT_RSTMGR_STAT_FPGAWARMRST_MSB 9
264 
265 #define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH 1
266 
267 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK 0x00000200
268 
269 #define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK 0xfffffdff
270 
271 #define ALT_RSTMGR_STAT_FPGAWARMRST_RESET 0x0
272 
273 #define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value) (((value) & 0x00000200) >> 9)
274 
275 #define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value) (((value) << 9) & 0x00000200)
276 
287 #define ALT_RSTMGR_STAT_SWWARMRST_LSB 10
288 
289 #define ALT_RSTMGR_STAT_SWWARMRST_MSB 10
290 
291 #define ALT_RSTMGR_STAT_SWWARMRST_WIDTH 1
292 
293 #define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK 0x00000400
294 
295 #define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK 0xfffffbff
296 
297 #define ALT_RSTMGR_STAT_SWWARMRST_RESET 0x0
298 
299 #define ALT_RSTMGR_STAT_SWWARMRST_GET(value) (((value) & 0x00000400) >> 10)
300 
301 #define ALT_RSTMGR_STAT_SWWARMRST_SET(value) (((value) << 10) & 0x00000400)
302 
312 #define ALT_RSTMGR_STAT_MPUWD0RST_LSB 12
313 
314 #define ALT_RSTMGR_STAT_MPUWD0RST_MSB 12
315 
316 #define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH 1
317 
318 #define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK 0x00001000
319 
320 #define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK 0xffffefff
321 
322 #define ALT_RSTMGR_STAT_MPUWD0RST_RESET 0x0
323 
324 #define ALT_RSTMGR_STAT_MPUWD0RST_GET(value) (((value) & 0x00001000) >> 12)
325 
326 #define ALT_RSTMGR_STAT_MPUWD0RST_SET(value) (((value) << 12) & 0x00001000)
327 
337 #define ALT_RSTMGR_STAT_MPUWD1RST_LSB 13
338 
339 #define ALT_RSTMGR_STAT_MPUWD1RST_MSB 13
340 
341 #define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH 1
342 
343 #define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK 0x00002000
344 
345 #define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK 0xffffdfff
346 
347 #define ALT_RSTMGR_STAT_MPUWD1RST_RESET 0x0
348 
349 #define ALT_RSTMGR_STAT_MPUWD1RST_GET(value) (((value) & 0x00002000) >> 13)
350 
351 #define ALT_RSTMGR_STAT_MPUWD1RST_SET(value) (((value) << 13) & 0x00002000)
352 
362 #define ALT_RSTMGR_STAT_L4WD0RST_LSB 14
363 
364 #define ALT_RSTMGR_STAT_L4WD0RST_MSB 14
365 
366 #define ALT_RSTMGR_STAT_L4WD0RST_WIDTH 1
367 
368 #define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK 0x00004000
369 
370 #define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK 0xffffbfff
371 
372 #define ALT_RSTMGR_STAT_L4WD0RST_RESET 0x0
373 
374 #define ALT_RSTMGR_STAT_L4WD0RST_GET(value) (((value) & 0x00004000) >> 14)
375 
376 #define ALT_RSTMGR_STAT_L4WD0RST_SET(value) (((value) << 14) & 0x00004000)
377 
387 #define ALT_RSTMGR_STAT_L4WD1RST_LSB 15
388 
389 #define ALT_RSTMGR_STAT_L4WD1RST_MSB 15
390 
391 #define ALT_RSTMGR_STAT_L4WD1RST_WIDTH 1
392 
393 #define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK 0x00008000
394 
395 #define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK 0xffff7fff
396 
397 #define ALT_RSTMGR_STAT_L4WD1RST_RESET 0x0
398 
399 #define ALT_RSTMGR_STAT_L4WD1RST_GET(value) (((value) & 0x00008000) >> 15)
400 
401 #define ALT_RSTMGR_STAT_L4WD1RST_SET(value) (((value) << 15) & 0x00008000)
402 
412 #define ALT_RSTMGR_STAT_FPGADBGRST_LSB 18
413 
414 #define ALT_RSTMGR_STAT_FPGADBGRST_MSB 18
415 
416 #define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH 1
417 
418 #define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK 0x00040000
419 
420 #define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK 0xfffbffff
421 
422 #define ALT_RSTMGR_STAT_FPGADBGRST_RESET 0x0
423 
424 #define ALT_RSTMGR_STAT_FPGADBGRST_GET(value) (((value) & 0x00040000) >> 18)
425 
426 #define ALT_RSTMGR_STAT_FPGADBGRST_SET(value) (((value) << 18) & 0x00040000)
427 
437 #define ALT_RSTMGR_STAT_CDBGREQRST_LSB 19
438 
439 #define ALT_RSTMGR_STAT_CDBGREQRST_MSB 19
440 
441 #define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH 1
442 
443 #define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK 0x00080000
444 
445 #define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK 0xfff7ffff
446 
447 #define ALT_RSTMGR_STAT_CDBGREQRST_RESET 0x0
448 
449 #define ALT_RSTMGR_STAT_CDBGREQRST_GET(value) (((value) & 0x00080000) >> 19)
450 
451 #define ALT_RSTMGR_STAT_CDBGREQRST_SET(value) (((value) << 19) & 0x00080000)
452 
465 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB 24
466 
467 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB 24
468 
469 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH 1
470 
471 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK 0x01000000
472 
473 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK 0xfeffffff
474 
475 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET 0x0
476 
477 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value) (((value) & 0x01000000) >> 24)
478 
479 #define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value) (((value) << 24) & 0x01000000)
480 
492 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB 25
493 
494 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB 25
495 
496 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH 1
497 
498 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK 0x02000000
499 
500 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK 0xfdffffff
501 
502 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET 0x0
503 
504 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value) (((value) & 0x02000000) >> 25)
505 
506 #define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value) (((value) << 25) & 0x02000000)
507 
519 #define ALT_RSTMGR_STAT_SCANHSTMO_LSB 26
520 
521 #define ALT_RSTMGR_STAT_SCANHSTMO_MSB 26
522 
523 #define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH 1
524 
525 #define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK 0x04000000
526 
527 #define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK 0xfbffffff
528 
529 #define ALT_RSTMGR_STAT_SCANHSTMO_RESET 0x0
530 
531 #define ALT_RSTMGR_STAT_SCANHSTMO_GET(value) (((value) & 0x04000000) >> 26)
532 
533 #define ALT_RSTMGR_STAT_SCANHSTMO_SET(value) (((value) << 26) & 0x04000000)
534 
546 #define ALT_RSTMGR_STAT_FPGAHSTMO_LSB 27
547 
548 #define ALT_RSTMGR_STAT_FPGAHSTMO_MSB 27
549 
550 #define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH 1
551 
552 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK 0x08000000
553 
554 #define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK 0xf7ffffff
555 
556 #define ALT_RSTMGR_STAT_FPGAHSTMO_RESET 0x0
557 
558 #define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value) (((value) & 0x08000000) >> 27)
559 
560 #define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value) (((value) << 27) & 0x08000000)
561 
573 #define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB 28
574 
575 #define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB 28
576 
577 #define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH 1
578 
579 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK 0x10000000
580 
581 #define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK 0xefffffff
582 
583 #define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET 0x0
584 
585 #define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value) (((value) & 0x10000000) >> 28)
586 
587 #define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value) (((value) << 28) & 0x10000000)
588 
589 #ifndef __ASSEMBLY__
590 
601 {
602  uint32_t porvoltrst : 1;
603  uint32_t nporpinrst : 1;
604  uint32_t fpgacoldrst : 1;
605  uint32_t configiocoldrst : 1;
606  uint32_t swcoldrst : 1;
607  uint32_t : 3;
608  uint32_t nrstpinrst : 1;
609  uint32_t fpgawarmrst : 1;
610  uint32_t swwarmrst : 1;
611  uint32_t : 1;
612  uint32_t mpuwd0rst : 1;
613  uint32_t mpuwd1rst : 1;
614  uint32_t l4wd0rst : 1;
615  uint32_t l4wd1rst : 1;
616  uint32_t : 2;
617  uint32_t fpgadbgrst : 1;
618  uint32_t cdbgreqrst : 1;
619  uint32_t : 4;
620  uint32_t sdrselfreftimeout : 1;
621  uint32_t fpgamgrhstimeout : 1;
622  uint32_t scanhstimeout : 1;
623  uint32_t fpgahstimeout : 1;
624  uint32_t etrstalltimeout : 1;
625  uint32_t : 3;
626 };
627 
629 typedef volatile struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t;
630 #endif /* __ASSEMBLY__ */
631 
633 #define ALT_RSTMGR_STAT_OFST 0x0
634 
687 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB 0
688 
689 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB 0
690 
691 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH 1
692 
693 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK 0x00000001
694 
695 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK 0xfffffffe
696 
697 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET 0x0
698 
699 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value) (((value) & 0x00000001) >> 0)
700 
701 #define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value) (((value) << 0) & 0x00000001)
702 
713 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB 1
714 
715 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB 1
716 
717 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH 1
718 
719 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK 0x00000002
720 
721 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK 0xfffffffd
722 
723 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET 0x0
724 
725 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value) (((value) & 0x00000002) >> 1)
726 
727 #define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value) (((value) << 1) & 0x00000002)
728 
742 #define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB 4
743 
744 #define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB 4
745 
746 #define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH 1
747 
748 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK 0x00000010
749 
750 #define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK 0xffffffef
751 
752 #define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET 0x0
753 
754 #define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value) (((value) & 0x00000010) >> 4)
755 
756 #define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value) (((value) << 4) & 0x00000010)
757 
773 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB 5
774 
775 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB 5
776 
777 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH 1
778 
779 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK 0x00000020
780 
781 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK 0xffffffdf
782 
783 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET 0x0
784 
785 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value) (((value) & 0x00000020) >> 5)
786 
787 #define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value) (((value) << 5) & 0x00000020)
788 
800 #define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB 6
801 
802 #define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB 6
803 
804 #define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH 1
805 
806 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK 0x00000040
807 
808 #define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK 0xffffffbf
809 
810 #define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET 0x0
811 
812 #define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value) (((value) & 0x00000040) >> 6)
813 
814 #define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value) (((value) << 6) & 0x00000040)
815 
835 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB 8
836 
837 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB 8
838 
839 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH 1
840 
841 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK 0x00000100
842 
843 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK 0xfffffeff
844 
845 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET 0x0
846 
847 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value) (((value) & 0x00000100) >> 8)
848 
849 #define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value) (((value) << 8) & 0x00000100)
850 
865 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB 9
866 
867 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB 9
868 
869 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH 1
870 
871 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK 0x00000200
872 
873 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK 0xfffffdff
874 
875 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET 0x0
876 
877 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value) (((value) & 0x00000200) >> 9)
878 
879 #define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value) (((value) << 9) & 0x00000200)
880 
891 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB 10
892 
893 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB 10
894 
895 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH 1
896 
897 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK 0x00000400
898 
899 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK 0xfffffbff
900 
901 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET 0x0
902 
903 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value) (((value) & 0x00000400) >> 10)
904 
905 #define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value) (((value) << 10) & 0x00000400)
906 
926 #define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB 12
927 
928 #define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB 12
929 
930 #define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH 1
931 
932 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK 0x00001000
933 
934 #define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK 0xffffefff
935 
936 #define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET 0x0
937 
938 #define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value) (((value) & 0x00001000) >> 12)
939 
940 #define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value) (((value) << 12) & 0x00001000)
941 
956 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB 13
957 
958 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB 13
959 
960 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH 1
961 
962 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK 0x00002000
963 
964 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK 0xffffdfff
965 
966 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET 0x0
967 
968 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value) (((value) & 0x00002000) >> 13)
969 
970 #define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value) (((value) << 13) & 0x00002000)
971 
982 #define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB 14
983 
984 #define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB 14
985 
986 #define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH 1
987 
988 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK 0x00004000
989 
990 #define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK 0xffffbfff
991 
992 #define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET 0x0
993 
994 #define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value) (((value) & 0x00004000) >> 14)
995 
996 #define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value) (((value) << 14) & 0x00004000)
997 
1014 #define ALT_RSTMGR_CTL_FPGAHSEN_LSB 16
1015 
1016 #define ALT_RSTMGR_CTL_FPGAHSEN_MSB 16
1017 
1018 #define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH 1
1019 
1020 #define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK 0x00010000
1021 
1022 #define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK 0xfffeffff
1023 
1024 #define ALT_RSTMGR_CTL_FPGAHSEN_RESET 0x0
1025 
1026 #define ALT_RSTMGR_CTL_FPGAHSEN_GET(value) (((value) & 0x00010000) >> 16)
1027 
1028 #define ALT_RSTMGR_CTL_FPGAHSEN_SET(value) (((value) << 16) & 0x00010000)
1029 
1043 #define ALT_RSTMGR_CTL_FPGAHSREQ_LSB 17
1044 
1045 #define ALT_RSTMGR_CTL_FPGAHSREQ_MSB 17
1046 
1047 #define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH 1
1048 
1049 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK 0x00020000
1050 
1051 #define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK 0xfffdffff
1052 
1053 #define ALT_RSTMGR_CTL_FPGAHSREQ_RESET 0x0
1054 
1055 #define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value) (((value) & 0x00020000) >> 17)
1056 
1057 #define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value) (((value) << 17) & 0x00020000)
1058 
1069 #define ALT_RSTMGR_CTL_FPGAHSACK_LSB 18
1070 
1071 #define ALT_RSTMGR_CTL_FPGAHSACK_MSB 18
1072 
1073 #define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH 1
1074 
1075 #define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK 0x00040000
1076 
1077 #define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK 0xfffbffff
1078 
1079 #define ALT_RSTMGR_CTL_FPGAHSACK_RESET 0x0
1080 
1081 #define ALT_RSTMGR_CTL_FPGAHSACK_GET(value) (((value) & 0x00040000) >> 18)
1082 
1083 #define ALT_RSTMGR_CTL_FPGAHSACK_SET(value) (((value) << 18) & 0x00040000)
1084 
1102 #define ALT_RSTMGR_CTL_ETRSTALLEN_LSB 20
1103 
1104 #define ALT_RSTMGR_CTL_ETRSTALLEN_MSB 20
1105 
1106 #define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH 1
1107 
1108 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK 0x00100000
1109 
1110 #define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK 0xffefffff
1111 
1112 #define ALT_RSTMGR_CTL_ETRSTALLEN_RESET 0x1
1113 
1114 #define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value) (((value) & 0x00100000) >> 20)
1115 
1116 #define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value) (((value) << 20) & 0x00100000)
1117 
1132 #define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB 21
1133 
1134 #define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB 21
1135 
1136 #define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH 1
1137 
1138 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK 0x00200000
1139 
1140 #define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK 0xffdfffff
1141 
1142 #define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET 0x0
1143 
1144 #define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value) (((value) & 0x00200000) >> 21)
1145 
1146 #define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value) (((value) << 21) & 0x00200000)
1147 
1158 #define ALT_RSTMGR_CTL_ETRSTALLACK_LSB 22
1159 
1160 #define ALT_RSTMGR_CTL_ETRSTALLACK_MSB 22
1161 
1162 #define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH 1
1163 
1164 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK 0x00400000
1165 
1166 #define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK 0xffbfffff
1167 
1168 #define ALT_RSTMGR_CTL_ETRSTALLACK_RESET 0x0
1169 
1170 #define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value) (((value) & 0x00400000) >> 22)
1171 
1172 #define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value) (((value) << 22) & 0x00400000)
1173 
1187 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB 23
1188 
1189 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB 23
1190 
1191 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH 1
1192 
1193 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK 0x00800000
1194 
1195 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK 0xff7fffff
1196 
1197 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET 0x0
1198 
1199 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value) (((value) & 0x00800000) >> 23)
1200 
1201 #define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value) (((value) << 23) & 0x00800000)
1202 
1203 #ifndef __ASSEMBLY__
1204 
1215 {
1216  uint32_t swcoldrstreq : 1;
1217  uint32_t swwarmrstreq : 1;
1218  uint32_t : 2;
1219  uint32_t sdrselfrefen : 1;
1220  uint32_t sdrselfrefreq : 1;
1221  const uint32_t sdrselfreqack : 1;
1222  uint32_t : 1;
1223  uint32_t fpgamgrhsen : 1;
1224  uint32_t fpgamgrhsreq : 1;
1225  const uint32_t fpgamgrhsack : 1;
1226  uint32_t : 1;
1227  uint32_t scanmgrhsen : 1;
1228  uint32_t scanmgrhsreq : 1;
1229  const uint32_t scanmgrhsack : 1;
1230  uint32_t : 1;
1231  uint32_t fpgahsen : 1;
1232  uint32_t fpgahsreq : 1;
1233  const uint32_t fpgahsack : 1;
1234  uint32_t : 1;
1235  uint32_t etrstallen : 1;
1236  uint32_t etrstallreq : 1;
1237  const uint32_t etrstallack : 1;
1238  uint32_t etrstallwarmrst : 1;
1239  uint32_t : 8;
1240 };
1241 
1243 typedef volatile struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t;
1244 #endif /* __ASSEMBLY__ */
1245 
1247 #define ALT_RSTMGR_CTL_OFST 0x4
1248 
1277 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0
1278 
1279 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7
1280 
1281 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8
1282 
1283 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff
1284 
1285 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00
1286 
1287 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80
1288 
1289 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0)
1290 
1291 #define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff)
1292 
1304 #define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8
1305 
1306 #define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27
1307 
1308 #define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20
1309 
1310 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00
1311 
1312 #define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff
1313 
1314 #define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800
1315 
1316 #define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8)
1317 
1318 #define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00)
1319 
1320 #ifndef __ASSEMBLY__
1321 
1332 {
1333  uint32_t warmrstcycles : 8;
1334  uint32_t nrstcnt : 20;
1335  uint32_t : 4;
1336 };
1337 
1340 #endif /* __ASSEMBLY__ */
1341 
1343 #define ALT_RSTMGR_COUNTS_OFST 0x8
1344 
1394 #define ALT_RSTMGR_MPUMODRST_CPU0_LSB 0
1395 
1396 #define ALT_RSTMGR_MPUMODRST_CPU0_MSB 0
1397 
1398 #define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH 1
1399 
1400 #define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK 0x00000001
1401 
1402 #define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK 0xfffffffe
1403 
1404 #define ALT_RSTMGR_MPUMODRST_CPU0_RESET 0x0
1405 
1406 #define ALT_RSTMGR_MPUMODRST_CPU0_GET(value) (((value) & 0x00000001) >> 0)
1407 
1408 #define ALT_RSTMGR_MPUMODRST_CPU0_SET(value) (((value) << 0) & 0x00000001)
1409 
1426 #define ALT_RSTMGR_MPUMODRST_CPU1_LSB 1
1427 
1428 #define ALT_RSTMGR_MPUMODRST_CPU1_MSB 1
1429 
1430 #define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH 1
1431 
1432 #define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK 0x00000002
1433 
1434 #define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK 0xfffffffd
1435 
1436 #define ALT_RSTMGR_MPUMODRST_CPU1_RESET 0x1
1437 
1438 #define ALT_RSTMGR_MPUMODRST_CPU1_GET(value) (((value) & 0x00000002) >> 1)
1439 
1440 #define ALT_RSTMGR_MPUMODRST_CPU1_SET(value) (((value) << 1) & 0x00000002)
1441 
1451 #define ALT_RSTMGR_MPUMODRST_WDS_LSB 2
1452 
1453 #define ALT_RSTMGR_MPUMODRST_WDS_MSB 2
1454 
1455 #define ALT_RSTMGR_MPUMODRST_WDS_WIDTH 1
1456 
1457 #define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK 0x00000004
1458 
1459 #define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK 0xfffffffb
1460 
1461 #define ALT_RSTMGR_MPUMODRST_WDS_RESET 0x0
1462 
1463 #define ALT_RSTMGR_MPUMODRST_WDS_GET(value) (((value) & 0x00000004) >> 2)
1464 
1465 #define ALT_RSTMGR_MPUMODRST_WDS_SET(value) (((value) << 2) & 0x00000004)
1466 
1478 #define ALT_RSTMGR_MPUMODRST_SCUPER_LSB 3
1479 
1480 #define ALT_RSTMGR_MPUMODRST_SCUPER_MSB 3
1481 
1482 #define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH 1
1483 
1484 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK 0x00000008
1485 
1486 #define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK 0xfffffff7
1487 
1488 #define ALT_RSTMGR_MPUMODRST_SCUPER_RESET 0x0
1489 
1490 #define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value) (((value) & 0x00000008) >> 3)
1491 
1492 #define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value) (((value) << 3) & 0x00000008)
1493 
1503 #define ALT_RSTMGR_MPUMODRST_L2_LSB 4
1504 
1505 #define ALT_RSTMGR_MPUMODRST_L2_MSB 4
1506 
1507 #define ALT_RSTMGR_MPUMODRST_L2_WIDTH 1
1508 
1509 #define ALT_RSTMGR_MPUMODRST_L2_SET_MSK 0x00000010
1510 
1511 #define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK 0xffffffef
1512 
1513 #define ALT_RSTMGR_MPUMODRST_L2_RESET 0x0
1514 
1515 #define ALT_RSTMGR_MPUMODRST_L2_GET(value) (((value) & 0x00000010) >> 4)
1516 
1517 #define ALT_RSTMGR_MPUMODRST_L2_SET(value) (((value) << 4) & 0x00000010)
1518 
1519 #ifndef __ASSEMBLY__
1520 
1531 {
1532  uint32_t cpu0 : 1;
1533  uint32_t cpu1 : 1;
1534  uint32_t wds : 1;
1535  uint32_t scuper : 1;
1536  uint32_t l2 : 1;
1537  uint32_t : 27;
1538 };
1539 
1542 #endif /* __ASSEMBLY__ */
1543 
1545 #define ALT_RSTMGR_MPUMODRST_OFST 0x10
1546 
1615 #define ALT_RSTMGR_PERMODRST_EMAC0_LSB 0
1616 
1617 #define ALT_RSTMGR_PERMODRST_EMAC0_MSB 0
1618 
1619 #define ALT_RSTMGR_PERMODRST_EMAC0_WIDTH 1
1620 
1621 #define ALT_RSTMGR_PERMODRST_EMAC0_SET_MSK 0x00000001
1622 
1623 #define ALT_RSTMGR_PERMODRST_EMAC0_CLR_MSK 0xfffffffe
1624 
1625 #define ALT_RSTMGR_PERMODRST_EMAC0_RESET 0x1
1626 
1627 #define ALT_RSTMGR_PERMODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0)
1628 
1629 #define ALT_RSTMGR_PERMODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001)
1630 
1640 #define ALT_RSTMGR_PERMODRST_EMAC1_LSB 1
1641 
1642 #define ALT_RSTMGR_PERMODRST_EMAC1_MSB 1
1643 
1644 #define ALT_RSTMGR_PERMODRST_EMAC1_WIDTH 1
1645 
1646 #define ALT_RSTMGR_PERMODRST_EMAC1_SET_MSK 0x00000002
1647 
1648 #define ALT_RSTMGR_PERMODRST_EMAC1_CLR_MSK 0xfffffffd
1649 
1650 #define ALT_RSTMGR_PERMODRST_EMAC1_RESET 0x1
1651 
1652 #define ALT_RSTMGR_PERMODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1)
1653 
1654 #define ALT_RSTMGR_PERMODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002)
1655 
1665 #define ALT_RSTMGR_PERMODRST_USB0_LSB 2
1666 
1667 #define ALT_RSTMGR_PERMODRST_USB0_MSB 2
1668 
1669 #define ALT_RSTMGR_PERMODRST_USB0_WIDTH 1
1670 
1671 #define ALT_RSTMGR_PERMODRST_USB0_SET_MSK 0x00000004
1672 
1673 #define ALT_RSTMGR_PERMODRST_USB0_CLR_MSK 0xfffffffb
1674 
1675 #define ALT_RSTMGR_PERMODRST_USB0_RESET 0x1
1676 
1677 #define ALT_RSTMGR_PERMODRST_USB0_GET(value) (((value) & 0x00000004) >> 2)
1678 
1679 #define ALT_RSTMGR_PERMODRST_USB0_SET(value) (((value) << 2) & 0x00000004)
1680 
1690 #define ALT_RSTMGR_PERMODRST_USB1_LSB 3
1691 
1692 #define ALT_RSTMGR_PERMODRST_USB1_MSB 3
1693 
1694 #define ALT_RSTMGR_PERMODRST_USB1_WIDTH 1
1695 
1696 #define ALT_RSTMGR_PERMODRST_USB1_SET_MSK 0x00000008
1697 
1698 #define ALT_RSTMGR_PERMODRST_USB1_CLR_MSK 0xfffffff7
1699 
1700 #define ALT_RSTMGR_PERMODRST_USB1_RESET 0x1
1701 
1702 #define ALT_RSTMGR_PERMODRST_USB1_GET(value) (((value) & 0x00000008) >> 3)
1703 
1704 #define ALT_RSTMGR_PERMODRST_USB1_SET(value) (((value) << 3) & 0x00000008)
1705 
1715 #define ALT_RSTMGR_PERMODRST_NAND_LSB 4
1716 
1717 #define ALT_RSTMGR_PERMODRST_NAND_MSB 4
1718 
1719 #define ALT_RSTMGR_PERMODRST_NAND_WIDTH 1
1720 
1721 #define ALT_RSTMGR_PERMODRST_NAND_SET_MSK 0x00000010
1722 
1723 #define ALT_RSTMGR_PERMODRST_NAND_CLR_MSK 0xffffffef
1724 
1725 #define ALT_RSTMGR_PERMODRST_NAND_RESET 0x1
1726 
1727 #define ALT_RSTMGR_PERMODRST_NAND_GET(value) (((value) & 0x00000010) >> 4)
1728 
1729 #define ALT_RSTMGR_PERMODRST_NAND_SET(value) (((value) << 4) & 0x00000010)
1730 
1740 #define ALT_RSTMGR_PERMODRST_QSPI_LSB 5
1741 
1742 #define ALT_RSTMGR_PERMODRST_QSPI_MSB 5
1743 
1744 #define ALT_RSTMGR_PERMODRST_QSPI_WIDTH 1
1745 
1746 #define ALT_RSTMGR_PERMODRST_QSPI_SET_MSK 0x00000020
1747 
1748 #define ALT_RSTMGR_PERMODRST_QSPI_CLR_MSK 0xffffffdf
1749 
1750 #define ALT_RSTMGR_PERMODRST_QSPI_RESET 0x1
1751 
1752 #define ALT_RSTMGR_PERMODRST_QSPI_GET(value) (((value) & 0x00000020) >> 5)
1753 
1754 #define ALT_RSTMGR_PERMODRST_QSPI_SET(value) (((value) << 5) & 0x00000020)
1755 
1765 #define ALT_RSTMGR_PERMODRST_L4WD0_LSB 6
1766 
1767 #define ALT_RSTMGR_PERMODRST_L4WD0_MSB 6
1768 
1769 #define ALT_RSTMGR_PERMODRST_L4WD0_WIDTH 1
1770 
1771 #define ALT_RSTMGR_PERMODRST_L4WD0_SET_MSK 0x00000040
1772 
1773 #define ALT_RSTMGR_PERMODRST_L4WD0_CLR_MSK 0xffffffbf
1774 
1775 #define ALT_RSTMGR_PERMODRST_L4WD0_RESET 0x1
1776 
1777 #define ALT_RSTMGR_PERMODRST_L4WD0_GET(value) (((value) & 0x00000040) >> 6)
1778 
1779 #define ALT_RSTMGR_PERMODRST_L4WD0_SET(value) (((value) << 6) & 0x00000040)
1780 
1790 #define ALT_RSTMGR_PERMODRST_L4WD1_LSB 7
1791 
1792 #define ALT_RSTMGR_PERMODRST_L4WD1_MSB 7
1793 
1794 #define ALT_RSTMGR_PERMODRST_L4WD1_WIDTH 1
1795 
1796 #define ALT_RSTMGR_PERMODRST_L4WD1_SET_MSK 0x00000080
1797 
1798 #define ALT_RSTMGR_PERMODRST_L4WD1_CLR_MSK 0xffffff7f
1799 
1800 #define ALT_RSTMGR_PERMODRST_L4WD1_RESET 0x1
1801 
1802 #define ALT_RSTMGR_PERMODRST_L4WD1_GET(value) (((value) & 0x00000080) >> 7)
1803 
1804 #define ALT_RSTMGR_PERMODRST_L4WD1_SET(value) (((value) << 7) & 0x00000080)
1805 
1815 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_LSB 8
1816 
1817 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_MSB 8
1818 
1819 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_WIDTH 1
1820 
1821 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET_MSK 0x00000100
1822 
1823 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_CLR_MSK 0xfffffeff
1824 
1825 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_RESET 0x1
1826 
1827 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_GET(value) (((value) & 0x00000100) >> 8)
1828 
1829 #define ALT_RSTMGR_PERMODRST_OSC1TMR0_SET(value) (((value) << 8) & 0x00000100)
1830 
1840 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_LSB 9
1841 
1842 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_MSB 9
1843 
1844 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_WIDTH 1
1845 
1846 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET_MSK 0x00000200
1847 
1848 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_CLR_MSK 0xfffffdff
1849 
1850 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_RESET 0x1
1851 
1852 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_GET(value) (((value) & 0x00000200) >> 9)
1853 
1854 #define ALT_RSTMGR_PERMODRST_OSC1TMR1_SET(value) (((value) << 9) & 0x00000200)
1855 
1865 #define ALT_RSTMGR_PERMODRST_SPTMR0_LSB 10
1866 
1867 #define ALT_RSTMGR_PERMODRST_SPTMR0_MSB 10
1868 
1869 #define ALT_RSTMGR_PERMODRST_SPTMR0_WIDTH 1
1870 
1871 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET_MSK 0x00000400
1872 
1873 #define ALT_RSTMGR_PERMODRST_SPTMR0_CLR_MSK 0xfffffbff
1874 
1875 #define ALT_RSTMGR_PERMODRST_SPTMR0_RESET 0x1
1876 
1877 #define ALT_RSTMGR_PERMODRST_SPTMR0_GET(value) (((value) & 0x00000400) >> 10)
1878 
1879 #define ALT_RSTMGR_PERMODRST_SPTMR0_SET(value) (((value) << 10) & 0x00000400)
1880 
1890 #define ALT_RSTMGR_PERMODRST_SPTMR1_LSB 11
1891 
1892 #define ALT_RSTMGR_PERMODRST_SPTMR1_MSB 11
1893 
1894 #define ALT_RSTMGR_PERMODRST_SPTMR1_WIDTH 1
1895 
1896 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET_MSK 0x00000800
1897 
1898 #define ALT_RSTMGR_PERMODRST_SPTMR1_CLR_MSK 0xfffff7ff
1899 
1900 #define ALT_RSTMGR_PERMODRST_SPTMR1_RESET 0x1
1901 
1902 #define ALT_RSTMGR_PERMODRST_SPTMR1_GET(value) (((value) & 0x00000800) >> 11)
1903 
1904 #define ALT_RSTMGR_PERMODRST_SPTMR1_SET(value) (((value) << 11) & 0x00000800)
1905 
1915 #define ALT_RSTMGR_PERMODRST_I2C0_LSB 12
1916 
1917 #define ALT_RSTMGR_PERMODRST_I2C0_MSB 12
1918 
1919 #define ALT_RSTMGR_PERMODRST_I2C0_WIDTH 1
1920 
1921 #define ALT_RSTMGR_PERMODRST_I2C0_SET_MSK 0x00001000
1922 
1923 #define ALT_RSTMGR_PERMODRST_I2C0_CLR_MSK 0xffffefff
1924 
1925 #define ALT_RSTMGR_PERMODRST_I2C0_RESET 0x1
1926 
1927 #define ALT_RSTMGR_PERMODRST_I2C0_GET(value) (((value) & 0x00001000) >> 12)
1928 
1929 #define ALT_RSTMGR_PERMODRST_I2C0_SET(value) (((value) << 12) & 0x00001000)
1930 
1940 #define ALT_RSTMGR_PERMODRST_I2C1_LSB 13
1941 
1942 #define ALT_RSTMGR_PERMODRST_I2C1_MSB 13
1943 
1944 #define ALT_RSTMGR_PERMODRST_I2C1_WIDTH 1
1945 
1946 #define ALT_RSTMGR_PERMODRST_I2C1_SET_MSK 0x00002000
1947 
1948 #define ALT_RSTMGR_PERMODRST_I2C1_CLR_MSK 0xffffdfff
1949 
1950 #define ALT_RSTMGR_PERMODRST_I2C1_RESET 0x1
1951 
1952 #define ALT_RSTMGR_PERMODRST_I2C1_GET(value) (((value) & 0x00002000) >> 13)
1953 
1954 #define ALT_RSTMGR_PERMODRST_I2C1_SET(value) (((value) << 13) & 0x00002000)
1955 
1965 #define ALT_RSTMGR_PERMODRST_I2C2_LSB 14
1966 
1967 #define ALT_RSTMGR_PERMODRST_I2C2_MSB 14
1968 
1969 #define ALT_RSTMGR_PERMODRST_I2C2_WIDTH 1
1970 
1971 #define ALT_RSTMGR_PERMODRST_I2C2_SET_MSK 0x00004000
1972 
1973 #define ALT_RSTMGR_PERMODRST_I2C2_CLR_MSK 0xffffbfff
1974 
1975 #define ALT_RSTMGR_PERMODRST_I2C2_RESET 0x1
1976 
1977 #define ALT_RSTMGR_PERMODRST_I2C2_GET(value) (((value) & 0x00004000) >> 14)
1978 
1979 #define ALT_RSTMGR_PERMODRST_I2C2_SET(value) (((value) << 14) & 0x00004000)
1980 
1990 #define ALT_RSTMGR_PERMODRST_I2C3_LSB 15
1991 
1992 #define ALT_RSTMGR_PERMODRST_I2C3_MSB 15
1993 
1994 #define ALT_RSTMGR_PERMODRST_I2C3_WIDTH 1
1995 
1996 #define ALT_RSTMGR_PERMODRST_I2C3_SET_MSK 0x00008000
1997 
1998 #define ALT_RSTMGR_PERMODRST_I2C3_CLR_MSK 0xffff7fff
1999 
2000 #define ALT_RSTMGR_PERMODRST_I2C3_RESET 0x1
2001 
2002 #define ALT_RSTMGR_PERMODRST_I2C3_GET(value) (((value) & 0x00008000) >> 15)
2003 
2004 #define ALT_RSTMGR_PERMODRST_I2C3_SET(value) (((value) << 15) & 0x00008000)
2005 
2015 #define ALT_RSTMGR_PERMODRST_UART0_LSB 16
2016 
2017 #define ALT_RSTMGR_PERMODRST_UART0_MSB 16
2018 
2019 #define ALT_RSTMGR_PERMODRST_UART0_WIDTH 1
2020 
2021 #define ALT_RSTMGR_PERMODRST_UART0_SET_MSK 0x00010000
2022 
2023 #define ALT_RSTMGR_PERMODRST_UART0_CLR_MSK 0xfffeffff
2024 
2025 #define ALT_RSTMGR_PERMODRST_UART0_RESET 0x1
2026 
2027 #define ALT_RSTMGR_PERMODRST_UART0_GET(value) (((value) & 0x00010000) >> 16)
2028 
2029 #define ALT_RSTMGR_PERMODRST_UART0_SET(value) (((value) << 16) & 0x00010000)
2030 
2040 #define ALT_RSTMGR_PERMODRST_UART1_LSB 17
2041 
2042 #define ALT_RSTMGR_PERMODRST_UART1_MSB 17
2043 
2044 #define ALT_RSTMGR_PERMODRST_UART1_WIDTH 1
2045 
2046 #define ALT_RSTMGR_PERMODRST_UART1_SET_MSK 0x00020000
2047 
2048 #define ALT_RSTMGR_PERMODRST_UART1_CLR_MSK 0xfffdffff
2049 
2050 #define ALT_RSTMGR_PERMODRST_UART1_RESET 0x1
2051 
2052 #define ALT_RSTMGR_PERMODRST_UART1_GET(value) (((value) & 0x00020000) >> 17)
2053 
2054 #define ALT_RSTMGR_PERMODRST_UART1_SET(value) (((value) << 17) & 0x00020000)
2055 
2065 #define ALT_RSTMGR_PERMODRST_SPIM0_LSB 18
2066 
2067 #define ALT_RSTMGR_PERMODRST_SPIM0_MSB 18
2068 
2069 #define ALT_RSTMGR_PERMODRST_SPIM0_WIDTH 1
2070 
2071 #define ALT_RSTMGR_PERMODRST_SPIM0_SET_MSK 0x00040000
2072 
2073 #define ALT_RSTMGR_PERMODRST_SPIM0_CLR_MSK 0xfffbffff
2074 
2075 #define ALT_RSTMGR_PERMODRST_SPIM0_RESET 0x1
2076 
2077 #define ALT_RSTMGR_PERMODRST_SPIM0_GET(value) (((value) & 0x00040000) >> 18)
2078 
2079 #define ALT_RSTMGR_PERMODRST_SPIM0_SET(value) (((value) << 18) & 0x00040000)
2080 
2090 #define ALT_RSTMGR_PERMODRST_SPIM1_LSB 19
2091 
2092 #define ALT_RSTMGR_PERMODRST_SPIM1_MSB 19
2093 
2094 #define ALT_RSTMGR_PERMODRST_SPIM1_WIDTH 1
2095 
2096 #define ALT_RSTMGR_PERMODRST_SPIM1_SET_MSK 0x00080000
2097 
2098 #define ALT_RSTMGR_PERMODRST_SPIM1_CLR_MSK 0xfff7ffff
2099 
2100 #define ALT_RSTMGR_PERMODRST_SPIM1_RESET 0x1
2101 
2102 #define ALT_RSTMGR_PERMODRST_SPIM1_GET(value) (((value) & 0x00080000) >> 19)
2103 
2104 #define ALT_RSTMGR_PERMODRST_SPIM1_SET(value) (((value) << 19) & 0x00080000)
2105 
2115 #define ALT_RSTMGR_PERMODRST_SPIS0_LSB 20
2116 
2117 #define ALT_RSTMGR_PERMODRST_SPIS0_MSB 20
2118 
2119 #define ALT_RSTMGR_PERMODRST_SPIS0_WIDTH 1
2120 
2121 #define ALT_RSTMGR_PERMODRST_SPIS0_SET_MSK 0x00100000
2122 
2123 #define ALT_RSTMGR_PERMODRST_SPIS0_CLR_MSK 0xffefffff
2124 
2125 #define ALT_RSTMGR_PERMODRST_SPIS0_RESET 0x1
2126 
2127 #define ALT_RSTMGR_PERMODRST_SPIS0_GET(value) (((value) & 0x00100000) >> 20)
2128 
2129 #define ALT_RSTMGR_PERMODRST_SPIS0_SET(value) (((value) << 20) & 0x00100000)
2130 
2140 #define ALT_RSTMGR_PERMODRST_SPIS1_LSB 21
2141 
2142 #define ALT_RSTMGR_PERMODRST_SPIS1_MSB 21
2143 
2144 #define ALT_RSTMGR_PERMODRST_SPIS1_WIDTH 1
2145 
2146 #define ALT_RSTMGR_PERMODRST_SPIS1_SET_MSK 0x00200000
2147 
2148 #define ALT_RSTMGR_PERMODRST_SPIS1_CLR_MSK 0xffdfffff
2149 
2150 #define ALT_RSTMGR_PERMODRST_SPIS1_RESET 0x1
2151 
2152 #define ALT_RSTMGR_PERMODRST_SPIS1_GET(value) (((value) & 0x00200000) >> 21)
2153 
2154 #define ALT_RSTMGR_PERMODRST_SPIS1_SET(value) (((value) << 21) & 0x00200000)
2155 
2165 #define ALT_RSTMGR_PERMODRST_SDMMC_LSB 22
2166 
2167 #define ALT_RSTMGR_PERMODRST_SDMMC_MSB 22
2168 
2169 #define ALT_RSTMGR_PERMODRST_SDMMC_WIDTH 1
2170 
2171 #define ALT_RSTMGR_PERMODRST_SDMMC_SET_MSK 0x00400000
2172 
2173 #define ALT_RSTMGR_PERMODRST_SDMMC_CLR_MSK 0xffbfffff
2174 
2175 #define ALT_RSTMGR_PERMODRST_SDMMC_RESET 0x1
2176 
2177 #define ALT_RSTMGR_PERMODRST_SDMMC_GET(value) (((value) & 0x00400000) >> 22)
2178 
2179 #define ALT_RSTMGR_PERMODRST_SDMMC_SET(value) (((value) << 22) & 0x00400000)
2180 
2192 #define ALT_RSTMGR_PERMODRST_CAN0_LSB 23
2193 
2194 #define ALT_RSTMGR_PERMODRST_CAN0_MSB 23
2195 
2196 #define ALT_RSTMGR_PERMODRST_CAN0_WIDTH 1
2197 
2198 #define ALT_RSTMGR_PERMODRST_CAN0_SET_MSK 0x00800000
2199 
2200 #define ALT_RSTMGR_PERMODRST_CAN0_CLR_MSK 0xff7fffff
2201 
2202 #define ALT_RSTMGR_PERMODRST_CAN0_RESET 0x1
2203 
2204 #define ALT_RSTMGR_PERMODRST_CAN0_GET(value) (((value) & 0x00800000) >> 23)
2205 
2206 #define ALT_RSTMGR_PERMODRST_CAN0_SET(value) (((value) << 23) & 0x00800000)
2207 
2219 #define ALT_RSTMGR_PERMODRST_CAN1_LSB 24
2220 
2221 #define ALT_RSTMGR_PERMODRST_CAN1_MSB 24
2222 
2223 #define ALT_RSTMGR_PERMODRST_CAN1_WIDTH 1
2224 
2225 #define ALT_RSTMGR_PERMODRST_CAN1_SET_MSK 0x01000000
2226 
2227 #define ALT_RSTMGR_PERMODRST_CAN1_CLR_MSK 0xfeffffff
2228 
2229 #define ALT_RSTMGR_PERMODRST_CAN1_RESET 0x1
2230 
2231 #define ALT_RSTMGR_PERMODRST_CAN1_GET(value) (((value) & 0x01000000) >> 24)
2232 
2233 #define ALT_RSTMGR_PERMODRST_CAN1_SET(value) (((value) << 24) & 0x01000000)
2234 
2244 #define ALT_RSTMGR_PERMODRST_GPIO0_LSB 25
2245 
2246 #define ALT_RSTMGR_PERMODRST_GPIO0_MSB 25
2247 
2248 #define ALT_RSTMGR_PERMODRST_GPIO0_WIDTH 1
2249 
2250 #define ALT_RSTMGR_PERMODRST_GPIO0_SET_MSK 0x02000000
2251 
2252 #define ALT_RSTMGR_PERMODRST_GPIO0_CLR_MSK 0xfdffffff
2253 
2254 #define ALT_RSTMGR_PERMODRST_GPIO0_RESET 0x1
2255 
2256 #define ALT_RSTMGR_PERMODRST_GPIO0_GET(value) (((value) & 0x02000000) >> 25)
2257 
2258 #define ALT_RSTMGR_PERMODRST_GPIO0_SET(value) (((value) << 25) & 0x02000000)
2259 
2269 #define ALT_RSTMGR_PERMODRST_GPIO1_LSB 26
2270 
2271 #define ALT_RSTMGR_PERMODRST_GPIO1_MSB 26
2272 
2273 #define ALT_RSTMGR_PERMODRST_GPIO1_WIDTH 1
2274 
2275 #define ALT_RSTMGR_PERMODRST_GPIO1_SET_MSK 0x04000000
2276 
2277 #define ALT_RSTMGR_PERMODRST_GPIO1_CLR_MSK 0xfbffffff
2278 
2279 #define ALT_RSTMGR_PERMODRST_GPIO1_RESET 0x1
2280 
2281 #define ALT_RSTMGR_PERMODRST_GPIO1_GET(value) (((value) & 0x04000000) >> 26)
2282 
2283 #define ALT_RSTMGR_PERMODRST_GPIO1_SET(value) (((value) << 26) & 0x04000000)
2284 
2294 #define ALT_RSTMGR_PERMODRST_GPIO2_LSB 27
2295 
2296 #define ALT_RSTMGR_PERMODRST_GPIO2_MSB 27
2297 
2298 #define ALT_RSTMGR_PERMODRST_GPIO2_WIDTH 1
2299 
2300 #define ALT_RSTMGR_PERMODRST_GPIO2_SET_MSK 0x08000000
2301 
2302 #define ALT_RSTMGR_PERMODRST_GPIO2_CLR_MSK 0xf7ffffff
2303 
2304 #define ALT_RSTMGR_PERMODRST_GPIO2_RESET 0x1
2305 
2306 #define ALT_RSTMGR_PERMODRST_GPIO2_GET(value) (((value) & 0x08000000) >> 27)
2307 
2308 #define ALT_RSTMGR_PERMODRST_GPIO2_SET(value) (((value) << 27) & 0x08000000)
2309 
2319 #define ALT_RSTMGR_PERMODRST_DMA_LSB 28
2320 
2321 #define ALT_RSTMGR_PERMODRST_DMA_MSB 28
2322 
2323 #define ALT_RSTMGR_PERMODRST_DMA_WIDTH 1
2324 
2325 #define ALT_RSTMGR_PERMODRST_DMA_SET_MSK 0x10000000
2326 
2327 #define ALT_RSTMGR_PERMODRST_DMA_CLR_MSK 0xefffffff
2328 
2329 #define ALT_RSTMGR_PERMODRST_DMA_RESET 0x1
2330 
2331 #define ALT_RSTMGR_PERMODRST_DMA_GET(value) (((value) & 0x10000000) >> 28)
2332 
2333 #define ALT_RSTMGR_PERMODRST_DMA_SET(value) (((value) << 28) & 0x10000000)
2334 
2344 #define ALT_RSTMGR_PERMODRST_SDR_LSB 29
2345 
2346 #define ALT_RSTMGR_PERMODRST_SDR_MSB 29
2347 
2348 #define ALT_RSTMGR_PERMODRST_SDR_WIDTH 1
2349 
2350 #define ALT_RSTMGR_PERMODRST_SDR_SET_MSK 0x20000000
2351 
2352 #define ALT_RSTMGR_PERMODRST_SDR_CLR_MSK 0xdfffffff
2353 
2354 #define ALT_RSTMGR_PERMODRST_SDR_RESET 0x1
2355 
2356 #define ALT_RSTMGR_PERMODRST_SDR_GET(value) (((value) & 0x20000000) >> 29)
2357 
2358 #define ALT_RSTMGR_PERMODRST_SDR_SET(value) (((value) << 29) & 0x20000000)
2359 
2360 #ifndef __ASSEMBLY__
2361 
2372 {
2373  uint32_t emac0 : 1;
2374  uint32_t emac1 : 1;
2375  uint32_t usb0 : 1;
2376  uint32_t usb1 : 1;
2377  uint32_t nand : 1;
2378  uint32_t qspi : 1;
2379  uint32_t l4wd0 : 1;
2380  uint32_t l4wd1 : 1;
2381  uint32_t osc1timer0 : 1;
2382  uint32_t osc1timer1 : 1;
2383  uint32_t sptimer0 : 1;
2384  uint32_t sptimer1 : 1;
2385  uint32_t i2c0 : 1;
2386  uint32_t i2c1 : 1;
2387  uint32_t i2c2 : 1;
2388  uint32_t i2c3 : 1;
2389  uint32_t uart0 : 1;
2390  uint32_t uart1 : 1;
2391  uint32_t spim0 : 1;
2392  uint32_t spim1 : 1;
2393  uint32_t spis0 : 1;
2394  uint32_t spis1 : 1;
2395  uint32_t sdmmc : 1;
2396  uint32_t can0 : 1;
2397  uint32_t can1 : 1;
2398  uint32_t gpio0 : 1;
2399  uint32_t gpio1 : 1;
2400  uint32_t gpio2 : 1;
2401  uint32_t dma : 1;
2402  uint32_t sdr : 1;
2403  uint32_t : 2;
2404 };
2405 
2408 #endif /* __ASSEMBLY__ */
2409 
2411 #define ALT_RSTMGR_PERMODRST_OFST 0x14
2412 
2460 #define ALT_RSTMGR_PER2MODRST_DMAIF0_LSB 0
2461 
2462 #define ALT_RSTMGR_PER2MODRST_DMAIF0_MSB 0
2463 
2464 #define ALT_RSTMGR_PER2MODRST_DMAIF0_WIDTH 1
2465 
2466 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET_MSK 0x00000001
2467 
2468 #define ALT_RSTMGR_PER2MODRST_DMAIF0_CLR_MSK 0xfffffffe
2469 
2470 #define ALT_RSTMGR_PER2MODRST_DMAIF0_RESET 0x1
2471 
2472 #define ALT_RSTMGR_PER2MODRST_DMAIF0_GET(value) (((value) & 0x00000001) >> 0)
2473 
2474 #define ALT_RSTMGR_PER2MODRST_DMAIF0_SET(value) (((value) << 0) & 0x00000001)
2475 
2486 #define ALT_RSTMGR_PER2MODRST_DMAIF1_LSB 1
2487 
2488 #define ALT_RSTMGR_PER2MODRST_DMAIF1_MSB 1
2489 
2490 #define ALT_RSTMGR_PER2MODRST_DMAIF1_WIDTH 1
2491 
2492 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET_MSK 0x00000002
2493 
2494 #define ALT_RSTMGR_PER2MODRST_DMAIF1_CLR_MSK 0xfffffffd
2495 
2496 #define ALT_RSTMGR_PER2MODRST_DMAIF1_RESET 0x1
2497 
2498 #define ALT_RSTMGR_PER2MODRST_DMAIF1_GET(value) (((value) & 0x00000002) >> 1)
2499 
2500 #define ALT_RSTMGR_PER2MODRST_DMAIF1_SET(value) (((value) << 1) & 0x00000002)
2501 
2512 #define ALT_RSTMGR_PER2MODRST_DMAIF2_LSB 2
2513 
2514 #define ALT_RSTMGR_PER2MODRST_DMAIF2_MSB 2
2515 
2516 #define ALT_RSTMGR_PER2MODRST_DMAIF2_WIDTH 1
2517 
2518 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET_MSK 0x00000004
2519 
2520 #define ALT_RSTMGR_PER2MODRST_DMAIF2_CLR_MSK 0xfffffffb
2521 
2522 #define ALT_RSTMGR_PER2MODRST_DMAIF2_RESET 0x1
2523 
2524 #define ALT_RSTMGR_PER2MODRST_DMAIF2_GET(value) (((value) & 0x00000004) >> 2)
2525 
2526 #define ALT_RSTMGR_PER2MODRST_DMAIF2_SET(value) (((value) << 2) & 0x00000004)
2527 
2538 #define ALT_RSTMGR_PER2MODRST_DMAIF3_LSB 3
2539 
2540 #define ALT_RSTMGR_PER2MODRST_DMAIF3_MSB 3
2541 
2542 #define ALT_RSTMGR_PER2MODRST_DMAIF3_WIDTH 1
2543 
2544 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET_MSK 0x00000008
2545 
2546 #define ALT_RSTMGR_PER2MODRST_DMAIF3_CLR_MSK 0xfffffff7
2547 
2548 #define ALT_RSTMGR_PER2MODRST_DMAIF3_RESET 0x1
2549 
2550 #define ALT_RSTMGR_PER2MODRST_DMAIF3_GET(value) (((value) & 0x00000008) >> 3)
2551 
2552 #define ALT_RSTMGR_PER2MODRST_DMAIF3_SET(value) (((value) << 3) & 0x00000008)
2553 
2564 #define ALT_RSTMGR_PER2MODRST_DMAIF4_LSB 4
2565 
2566 #define ALT_RSTMGR_PER2MODRST_DMAIF4_MSB 4
2567 
2568 #define ALT_RSTMGR_PER2MODRST_DMAIF4_WIDTH 1
2569 
2570 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET_MSK 0x00000010
2571 
2572 #define ALT_RSTMGR_PER2MODRST_DMAIF4_CLR_MSK 0xffffffef
2573 
2574 #define ALT_RSTMGR_PER2MODRST_DMAIF4_RESET 0x1
2575 
2576 #define ALT_RSTMGR_PER2MODRST_DMAIF4_GET(value) (((value) & 0x00000010) >> 4)
2577 
2578 #define ALT_RSTMGR_PER2MODRST_DMAIF4_SET(value) (((value) << 4) & 0x00000010)
2579 
2590 #define ALT_RSTMGR_PER2MODRST_DMAIF5_LSB 5
2591 
2592 #define ALT_RSTMGR_PER2MODRST_DMAIF5_MSB 5
2593 
2594 #define ALT_RSTMGR_PER2MODRST_DMAIF5_WIDTH 1
2595 
2596 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET_MSK 0x00000020
2597 
2598 #define ALT_RSTMGR_PER2MODRST_DMAIF5_CLR_MSK 0xffffffdf
2599 
2600 #define ALT_RSTMGR_PER2MODRST_DMAIF5_RESET 0x1
2601 
2602 #define ALT_RSTMGR_PER2MODRST_DMAIF5_GET(value) (((value) & 0x00000020) >> 5)
2603 
2604 #define ALT_RSTMGR_PER2MODRST_DMAIF5_SET(value) (((value) << 5) & 0x00000020)
2605 
2616 #define ALT_RSTMGR_PER2MODRST_DMAIF6_LSB 6
2617 
2618 #define ALT_RSTMGR_PER2MODRST_DMAIF6_MSB 6
2619 
2620 #define ALT_RSTMGR_PER2MODRST_DMAIF6_WIDTH 1
2621 
2622 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET_MSK 0x00000040
2623 
2624 #define ALT_RSTMGR_PER2MODRST_DMAIF6_CLR_MSK 0xffffffbf
2625 
2626 #define ALT_RSTMGR_PER2MODRST_DMAIF6_RESET 0x1
2627 
2628 #define ALT_RSTMGR_PER2MODRST_DMAIF6_GET(value) (((value) & 0x00000040) >> 6)
2629 
2630 #define ALT_RSTMGR_PER2MODRST_DMAIF6_SET(value) (((value) << 6) & 0x00000040)
2631 
2642 #define ALT_RSTMGR_PER2MODRST_DMAIF7_LSB 7
2643 
2644 #define ALT_RSTMGR_PER2MODRST_DMAIF7_MSB 7
2645 
2646 #define ALT_RSTMGR_PER2MODRST_DMAIF7_WIDTH 1
2647 
2648 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET_MSK 0x00000080
2649 
2650 #define ALT_RSTMGR_PER2MODRST_DMAIF7_CLR_MSK 0xffffff7f
2651 
2652 #define ALT_RSTMGR_PER2MODRST_DMAIF7_RESET 0x1
2653 
2654 #define ALT_RSTMGR_PER2MODRST_DMAIF7_GET(value) (((value) & 0x00000080) >> 7)
2655 
2656 #define ALT_RSTMGR_PER2MODRST_DMAIF7_SET(value) (((value) << 7) & 0x00000080)
2657 
2658 #ifndef __ASSEMBLY__
2659 
2670 {
2671  uint32_t dmaif0 : 1;
2672  uint32_t dmaif1 : 1;
2673  uint32_t dmaif2 : 1;
2674  uint32_t dmaif3 : 1;
2675  uint32_t dmaif4 : 1;
2676  uint32_t dmaif5 : 1;
2677  uint32_t dmaif6 : 1;
2678  uint32_t dmaif7 : 1;
2679  uint32_t : 24;
2680 };
2681 
2684 #endif /* __ASSEMBLY__ */
2685 
2687 #define ALT_RSTMGR_PER2MODRST_OFST 0x18
2688 
2730 #define ALT_RSTMGR_BRGMODRST_H2F_LSB 0
2731 
2732 #define ALT_RSTMGR_BRGMODRST_H2F_MSB 0
2733 
2734 #define ALT_RSTMGR_BRGMODRST_H2F_WIDTH 1
2735 
2736 #define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK 0x00000001
2737 
2738 #define ALT_RSTMGR_BRGMODRST_H2F_CLR_MSK 0xfffffffe
2739 
2740 #define ALT_RSTMGR_BRGMODRST_H2F_RESET 0x1
2741 
2742 #define ALT_RSTMGR_BRGMODRST_H2F_GET(value) (((value) & 0x00000001) >> 0)
2743 
2744 #define ALT_RSTMGR_BRGMODRST_H2F_SET(value) (((value) << 0) & 0x00000001)
2745 
2755 #define ALT_RSTMGR_BRGMODRST_LWH2F_LSB 1
2756 
2757 #define ALT_RSTMGR_BRGMODRST_LWH2F_MSB 1
2758 
2759 #define ALT_RSTMGR_BRGMODRST_LWH2F_WIDTH 1
2760 
2761 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK 0x00000002
2762 
2763 #define ALT_RSTMGR_BRGMODRST_LWH2F_CLR_MSK 0xfffffffd
2764 
2765 #define ALT_RSTMGR_BRGMODRST_LWH2F_RESET 0x1
2766 
2767 #define ALT_RSTMGR_BRGMODRST_LWH2F_GET(value) (((value) & 0x00000002) >> 1)
2768 
2769 #define ALT_RSTMGR_BRGMODRST_LWH2F_SET(value) (((value) << 1) & 0x00000002)
2770 
2780 #define ALT_RSTMGR_BRGMODRST_F2H_LSB 2
2781 
2782 #define ALT_RSTMGR_BRGMODRST_F2H_MSB 2
2783 
2784 #define ALT_RSTMGR_BRGMODRST_F2H_WIDTH 1
2785 
2786 #define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK 0x00000004
2787 
2788 #define ALT_RSTMGR_BRGMODRST_F2H_CLR_MSK 0xfffffffb
2789 
2790 #define ALT_RSTMGR_BRGMODRST_F2H_RESET 0x1
2791 
2792 #define ALT_RSTMGR_BRGMODRST_F2H_GET(value) (((value) & 0x00000004) >> 2)
2793 
2794 #define ALT_RSTMGR_BRGMODRST_F2H_SET(value) (((value) << 2) & 0x00000004)
2795 
2796 #ifndef __ASSEMBLY__
2797 
2808 {
2809  uint32_t hps2fpga : 1;
2810  uint32_t lwhps2fpga : 1;
2811  uint32_t fpga2hps : 1;
2812  uint32_t : 29;
2813 };
2814 
2817 #endif /* __ASSEMBLY__ */
2818 
2820 #define ALT_RSTMGR_BRGMODRST_OFST 0x1c
2821 
2872 #define ALT_RSTMGR_MISCMODRST_ROM_LSB 0
2873 
2874 #define ALT_RSTMGR_MISCMODRST_ROM_MSB 0
2875 
2876 #define ALT_RSTMGR_MISCMODRST_ROM_WIDTH 1
2877 
2878 #define ALT_RSTMGR_MISCMODRST_ROM_SET_MSK 0x00000001
2879 
2880 #define ALT_RSTMGR_MISCMODRST_ROM_CLR_MSK 0xfffffffe
2881 
2882 #define ALT_RSTMGR_MISCMODRST_ROM_RESET 0x0
2883 
2884 #define ALT_RSTMGR_MISCMODRST_ROM_GET(value) (((value) & 0x00000001) >> 0)
2885 
2886 #define ALT_RSTMGR_MISCMODRST_ROM_SET(value) (((value) << 0) & 0x00000001)
2887 
2897 #define ALT_RSTMGR_MISCMODRST_OCRAM_LSB 1
2898 
2899 #define ALT_RSTMGR_MISCMODRST_OCRAM_MSB 1
2900 
2901 #define ALT_RSTMGR_MISCMODRST_OCRAM_WIDTH 1
2902 
2903 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET_MSK 0x00000002
2904 
2905 #define ALT_RSTMGR_MISCMODRST_OCRAM_CLR_MSK 0xfffffffd
2906 
2907 #define ALT_RSTMGR_MISCMODRST_OCRAM_RESET 0x0
2908 
2909 #define ALT_RSTMGR_MISCMODRST_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
2910 
2911 #define ALT_RSTMGR_MISCMODRST_OCRAM_SET(value) (((value) << 1) & 0x00000002)
2912 
2923 #define ALT_RSTMGR_MISCMODRST_SYSMGR_LSB 2
2924 
2925 #define ALT_RSTMGR_MISCMODRST_SYSMGR_MSB 2
2926 
2927 #define ALT_RSTMGR_MISCMODRST_SYSMGR_WIDTH 1
2928 
2929 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET_MSK 0x00000004
2930 
2931 #define ALT_RSTMGR_MISCMODRST_SYSMGR_CLR_MSK 0xfffffffb
2932 
2933 #define ALT_RSTMGR_MISCMODRST_SYSMGR_RESET 0x0
2934 
2935 #define ALT_RSTMGR_MISCMODRST_SYSMGR_GET(value) (((value) & 0x00000004) >> 2)
2936 
2937 #define ALT_RSTMGR_MISCMODRST_SYSMGR_SET(value) (((value) << 2) & 0x00000004)
2938 
2949 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_LSB 3
2950 
2951 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_MSB 3
2952 
2953 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_WIDTH 1
2954 
2955 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET_MSK 0x00000008
2956 
2957 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_CLR_MSK 0xfffffff7
2958 
2959 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_RESET 0x0
2960 
2961 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_GET(value) (((value) & 0x00000008) >> 3)
2962 
2963 #define ALT_RSTMGR_MISCMODRST_SYSMGRCOLD_SET(value) (((value) << 3) & 0x00000008)
2964 
2974 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_LSB 4
2975 
2976 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_MSB 4
2977 
2978 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_WIDTH 1
2979 
2980 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET_MSK 0x00000010
2981 
2982 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_CLR_MSK 0xffffffef
2983 
2984 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_RESET 0x0
2985 
2986 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_GET(value) (((value) & 0x00000010) >> 4)
2987 
2988 #define ALT_RSTMGR_MISCMODRST_FPGAMGR_SET(value) (((value) << 4) & 0x00000010)
2989 
2999 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_LSB 5
3000 
3001 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_MSB 5
3002 
3003 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_WIDTH 1
3004 
3005 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET_MSK 0x00000020
3006 
3007 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_CLR_MSK 0xffffffdf
3008 
3009 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_RESET 0x0
3010 
3011 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_GET(value) (((value) & 0x00000020) >> 5)
3012 
3013 #define ALT_RSTMGR_MISCMODRST_ACPIDMAP_SET(value) (((value) << 5) & 0x00000020)
3014 
3025 #define ALT_RSTMGR_MISCMODRST_S2F_LSB 6
3026 
3027 #define ALT_RSTMGR_MISCMODRST_S2F_MSB 6
3028 
3029 #define ALT_RSTMGR_MISCMODRST_S2F_WIDTH 1
3030 
3031 #define ALT_RSTMGR_MISCMODRST_S2F_SET_MSK 0x00000040
3032 
3033 #define ALT_RSTMGR_MISCMODRST_S2F_CLR_MSK 0xffffffbf
3034 
3035 #define ALT_RSTMGR_MISCMODRST_S2F_RESET 0x0
3036 
3037 #define ALT_RSTMGR_MISCMODRST_S2F_GET(value) (((value) & 0x00000040) >> 6)
3038 
3039 #define ALT_RSTMGR_MISCMODRST_S2F_SET(value) (((value) << 6) & 0x00000040)
3040 
3051 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_LSB 7
3052 
3053 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_MSB 7
3054 
3055 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_WIDTH 1
3056 
3057 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET_MSK 0x00000080
3058 
3059 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_CLR_MSK 0xffffff7f
3060 
3061 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_RESET 0x0
3062 
3063 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_GET(value) (((value) & 0x00000080) >> 7)
3064 
3065 #define ALT_RSTMGR_MISCMODRST_S2FCOLD_SET(value) (((value) << 7) & 0x00000080)
3066 
3076 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_LSB 8
3077 
3078 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_MSB 8
3079 
3080 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_WIDTH 1
3081 
3082 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET_MSK 0x00000100
3083 
3084 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_CLR_MSK 0xfffffeff
3085 
3086 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_RESET 0x0
3087 
3088 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_GET(value) (((value) & 0x00000100) >> 8)
3089 
3090 #define ALT_RSTMGR_MISCMODRST_NRSTPIN_SET(value) (((value) << 8) & 0x00000100)
3091 
3101 #define ALT_RSTMGR_MISCMODRST_TSCOLD_LSB 9
3102 
3103 #define ALT_RSTMGR_MISCMODRST_TSCOLD_MSB 9
3104 
3105 #define ALT_RSTMGR_MISCMODRST_TSCOLD_WIDTH 1
3106 
3107 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET_MSK 0x00000200
3108 
3109 #define ALT_RSTMGR_MISCMODRST_TSCOLD_CLR_MSK 0xfffffdff
3110 
3111 #define ALT_RSTMGR_MISCMODRST_TSCOLD_RESET 0x0
3112 
3113 #define ALT_RSTMGR_MISCMODRST_TSCOLD_GET(value) (((value) & 0x00000200) >> 9)
3114 
3115 #define ALT_RSTMGR_MISCMODRST_TSCOLD_SET(value) (((value) << 9) & 0x00000200)
3116 
3126 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_LSB 10
3127 
3128 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_MSB 10
3129 
3130 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_WIDTH 1
3131 
3132 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET_MSK 0x00000400
3133 
3134 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_CLR_MSK 0xfffffbff
3135 
3136 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_RESET 0x0
3137 
3138 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_GET(value) (((value) & 0x00000400) >> 10)
3139 
3140 #define ALT_RSTMGR_MISCMODRST_CLKMGRCOLD_SET(value) (((value) << 10) & 0x00000400)
3141 
3151 #define ALT_RSTMGR_MISCMODRST_SCANMGR_LSB 11
3152 
3153 #define ALT_RSTMGR_MISCMODRST_SCANMGR_MSB 11
3154 
3155 #define ALT_RSTMGR_MISCMODRST_SCANMGR_WIDTH 1
3156 
3157 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET_MSK 0x00000800
3158 
3159 #define ALT_RSTMGR_MISCMODRST_SCANMGR_CLR_MSK 0xfffff7ff
3160 
3161 #define ALT_RSTMGR_MISCMODRST_SCANMGR_RESET 0x0
3162 
3163 #define ALT_RSTMGR_MISCMODRST_SCANMGR_GET(value) (((value) & 0x00000800) >> 11)
3164 
3165 #define ALT_RSTMGR_MISCMODRST_SCANMGR_SET(value) (((value) << 11) & 0x00000800)
3166 
3176 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_LSB 12
3177 
3178 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_MSB 12
3179 
3180 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_WIDTH 1
3181 
3182 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET_MSK 0x00001000
3183 
3184 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_CLR_MSK 0xffffefff
3185 
3186 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_RESET 0x0
3187 
3188 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_GET(value) (((value) & 0x00001000) >> 12)
3189 
3190 #define ALT_RSTMGR_MISCMODRST_FRZCTLCOLD_SET(value) (((value) << 12) & 0x00001000)
3191 
3201 #define ALT_RSTMGR_MISCMODRST_SYSDBG_LSB 13
3202 
3203 #define ALT_RSTMGR_MISCMODRST_SYSDBG_MSB 13
3204 
3205 #define ALT_RSTMGR_MISCMODRST_SYSDBG_WIDTH 1
3206 
3207 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET_MSK 0x00002000
3208 
3209 #define ALT_RSTMGR_MISCMODRST_SYSDBG_CLR_MSK 0xffffdfff
3210 
3211 #define ALT_RSTMGR_MISCMODRST_SYSDBG_RESET 0x0
3212 
3213 #define ALT_RSTMGR_MISCMODRST_SYSDBG_GET(value) (((value) & 0x00002000) >> 13)
3214 
3215 #define ALT_RSTMGR_MISCMODRST_SYSDBG_SET(value) (((value) << 13) & 0x00002000)
3216 
3226 #define ALT_RSTMGR_MISCMODRST_DBG_LSB 14
3227 
3228 #define ALT_RSTMGR_MISCMODRST_DBG_MSB 14
3229 
3230 #define ALT_RSTMGR_MISCMODRST_DBG_WIDTH 1
3231 
3232 #define ALT_RSTMGR_MISCMODRST_DBG_SET_MSK 0x00004000
3233 
3234 #define ALT_RSTMGR_MISCMODRST_DBG_CLR_MSK 0xffffbfff
3235 
3236 #define ALT_RSTMGR_MISCMODRST_DBG_RESET 0x0
3237 
3238 #define ALT_RSTMGR_MISCMODRST_DBG_GET(value) (((value) & 0x00004000) >> 14)
3239 
3240 #define ALT_RSTMGR_MISCMODRST_DBG_SET(value) (((value) << 14) & 0x00004000)
3241 
3252 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_LSB 15
3253 
3254 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_MSB 15
3255 
3256 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_WIDTH 1
3257 
3258 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET_MSK 0x00008000
3259 
3260 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_CLR_MSK 0xffff7fff
3261 
3262 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_RESET 0x0
3263 
3264 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_GET(value) (((value) & 0x00008000) >> 15)
3265 
3266 #define ALT_RSTMGR_MISCMODRST_TAPCOLD_SET(value) (((value) << 15) & 0x00008000)
3267 
3277 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_LSB 16
3278 
3279 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_MSB 16
3280 
3281 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_WIDTH 1
3282 
3283 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET_MSK 0x00010000
3284 
3285 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_CLR_MSK 0xfffeffff
3286 
3287 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_RESET 0x0
3288 
3289 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_GET(value) (((value) & 0x00010000) >> 16)
3290 
3291 #define ALT_RSTMGR_MISCMODRST_SDRCOLD_SET(value) (((value) << 16) & 0x00010000)
3292 
3293 #ifndef __ASSEMBLY__
3294 
3305 {
3306  uint32_t rom : 1;
3307  uint32_t ocram : 1;
3308  uint32_t sysmgr : 1;
3309  uint32_t sysmgrcold : 1;
3310  uint32_t fpgamgr : 1;
3311  uint32_t acpidmap : 1;
3312  uint32_t s2f : 1;
3313  uint32_t s2fcold : 1;
3314  uint32_t nrstpin : 1;
3315  uint32_t timestampcold : 1;
3316  uint32_t clkmgrcold : 1;
3317  uint32_t scanmgr : 1;
3318  uint32_t frzctrlcold : 1;
3319  uint32_t sysdbg : 1;
3320  uint32_t dbg : 1;
3321  uint32_t tapcold : 1;
3322  uint32_t sdrcold : 1;
3323  uint32_t : 15;
3324 };
3325 
3328 #endif /* __ASSEMBLY__ */
3329 
3331 #define ALT_RSTMGR_MISCMODRST_OFST 0x20
3332 
3333 #ifndef __ASSEMBLY__
3334 
3345 {
3349  volatile uint32_t _pad_0xc_0xf;
3355  volatile uint32_t _pad_0x24_0x100[55];
3356 };
3357 
3359 typedef volatile struct ALT_RSTMGR_s ALT_RSTMGR_t;
3362 {
3363  volatile uint32_t stat;
3364  volatile uint32_t ctrl;
3365  volatile uint32_t counts;
3366  volatile uint32_t _pad_0xc_0xf;
3367  volatile uint32_t mpumodrst;
3368  volatile uint32_t permodrst;
3369  volatile uint32_t per2modrst;
3370  volatile uint32_t brgmodrst;
3371  volatile uint32_t miscmodrst;
3372  volatile uint32_t _pad_0x24_0x100[55];
3373 };
3374 
3376 typedef volatile struct ALT_RSTMGR_raw_s ALT_RSTMGR_raw_t;
3377 #endif /* __ASSEMBLY__ */
3378 
3380 #ifdef __cplusplus
3381 }
3382 #endif /* __cplusplus */
3383 #endif /* __ALTERA_ALT_RSTMGR_H__ */
3384