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16.0
The Altera HW Manager API Reference Manual
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alt_l2_p310.h
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/******************************************************************************
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*
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* Copyright 2013 Altera Corporation. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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/*
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* $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/alt_l2_p310.h#1 $
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*/
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#ifndef __ALT_L2_P310_H__
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#define __ALT_L2_P310_H__
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#include <stdbool.h>
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#include "socal/hps.h"
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#ifdef __cplusplus
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extern
"C"
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{
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#endif
/* __cplusplus */
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/******************************************************************************/
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// ARM Level 2 Cache Controller L2C-310 Register Interface
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// These definitions should match the values given in DDI0246H_l2c310_r3p3_trm.pdf
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// provided by ARM
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// Cache ID Register
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// The Cache ID Registers is a read only register
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:24] | Implementer | ID of IP provider. Should be 0x41 (ARM)
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// [23:16] | Reserved | SBZ/RAZ
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// [15:10] | Cache ID |
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// [9:6] | Part Number |
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// [5:0] | RTL release |
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// Cache ID Register Address
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#define ALT_L2_CACHE_ID_OFST 0x000
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#define ALT_L2_CACHE_ID_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
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// Cache ID Register - Implementer Mask
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#define ALT_L2_CACHE_ID_IMPLEMENTER_MASK 0xFF000000
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// Cache ID Register - Cache ID Mask
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#define ALT_L2_CACHE_ID_CACHE_ID_MASK 0x0000FC00
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// Cache ID Register - Part Number Mask
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#define ALT_L2_CACHE_ID_PART_NUMBER_MASK 0x000003C0
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// Cache ID Register - RTL Relase Mask
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#define ALT_L2_CACHE_ID_RTL_RELEASE_MASK 0x0000003F
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#define ALT_L2_CACHE_TYPE_OFST 0x004
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#define ALT_L2_CACHE_TYPE_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
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// The Cache Control Register is a read and write register
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:1] | Reservered | SBZ/RAZ
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// [0] | L2 Cache Enable |
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// Cache Control Register Address
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#define ALT_L2_CACHE_REG1_CNTRL_OFST 0x100
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#define ALT_L2_CACHE_REG1_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_CNTRL_OFST)
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// Cache Control Register - Enable
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#define ALT_L2_CACHE_REG1_CNTRL_DISABLE 0x0
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#define ALT_L2_CACHE_REG1_CNTRL_ENABLE 0x1
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#define ALT_L2_CACHE_REG1_CNTRL_ENABLE_MASK 0x1
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// Aux Cache Control Register
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// The Aux Cache Control Register is a read and write register
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31] | Reservered | SBZ/RAZ
102
// [30] | Early BRESP Enabled |
103
// [29] | Inst Prefetch Enable |
104
// [28] | Data Prefetch Enable |
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// [27] | N/S Int Access Cntrl |
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// [26] | N/S Lockdown Enable |
107
// [25] | Cache Replacement Policy |
108
// [24:23] | Force Write Allocate |
109
// [22] | Shared Attr Override En |
110
// [21] | Parity Enable |
111
// [20] | Event Monitor Bus Enable |
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// [19:17] | Way Size |
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// [16] | Associativity |
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// [15:14] | Reserved |
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// [13] | Shared Attribute Inv En |
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// [12] | Exclusive Cache Config |
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// [11] | Store Buffer Dev Limit En |
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// [10] | High Priority for SO En |
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// [9:1] | Reserved |
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// [0] | Full Line of Zero En |
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// Aux Cache Control Register Address
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_OFST 0x104
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_AUX_CNTRL_OFST)
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_EN_MASK 0x40000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_ENABLE 0x40000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_EN_MASK 0x20000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_ENABLE 0x20000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_EN_MASK 0x10000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_ENABLE 0x10000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_MASK 0x08000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_ENABLE 0x08000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_EN_MASK 0x04000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_ENABLE 0x04000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_MASK 0x02000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RANDOM 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RR 0x02000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_MASK 0x01800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_AWCACHE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA0 0x00800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA1 0x01000000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_00 0x01800000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_EN_MASK 0x00400000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_ENABLE 0x00400000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_EN_MASK 0x00200000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_ENABLE 0x00200000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_EN_MASK 0x00100000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_ENABLE 0x00100000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_MASK 0x000E0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_16KB 0x00020000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_32KB 0x00040000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_64KB 0x00060000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_128KB 0x00080000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_256B 0x000A0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_512KB 0x000C0000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_MASK 0x00010000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_8WAY 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_16WAY 0x00010000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_EN_MASK 0x00002000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_ENABLE 0x00002000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_MASK 0x00001000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_ENABLE 0x00001000
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_EN_MASK 0x00000800
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_ENABLE 0x00000800
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_EN_MASK 0x00000400
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_ENABLE 0x00000400
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_DISABLE 0
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_EN_MASK 0x1
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_ENABLE 0x1
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#define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_DISABLE 0
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// Tag and Data RAM Latency Control Register
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// The Tag and Data RAM Latency Control Register is a read and write register
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// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:11] | Reservered | SBZ/RAZ
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// [10:8] | RAM Write Access Latency |
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// [7] | Reserved |
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// [10:8] | RAM Read Access Latency |
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// [3] | Reserved |
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// [2:0] | RAM Setup Latency |
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST 0x108
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST)
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_MASK 0x00000700
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_2 0x00000100
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_3 0x00000200
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_4 0x00000300
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_5 0x00000400
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_6 0x00000500
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_7 0x00000600
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_8 0x00000700
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_MASK 0x00000070
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_2 0x00000010
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_3 0x00000020
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_4 0x00000030
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_5 0x00000040
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_6 0x00000050
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_7 0x00000060
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_8 0x00000070
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_MASK 0x00000007
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_2 0x00000001
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_3 0x00000002
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_4 0x00000003
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_5 0x00000004
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_6 0x00000005
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_7 0x00000006
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_8 0x00000007
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_LSB 8
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_LSB 4
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_LSB 0
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_1 0x00000000
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_2 0x00000001
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_3 0x00000002
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_4 0x00000003
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_5 0x00000004
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_6 0x00000005
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_7 0x00000006
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#define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_8 0x00000007
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#define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST 0x10C
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#define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST)
240
241
// Event Counter Control Register
242
// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
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// [31:3] | Reservered | SBZ/RAZ
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// [2:1] | Counter Reset |
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// [0] | Event Counter Enable |
247
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_OFST 0x200
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT_CNTRL_OFST)
250
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_MASK 0x00000006
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_0 0x00000002
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_1 0x00000004
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_EN_MASK 1
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// Enable Counter
256
#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ENABLE 1
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#define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_DISABLE 0
258
259
260
// Event Counter Configuration Registers
261
// Bits Field Description
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// :-------|:--------------------------|:-----------------------------------------
263
// [31:6] | Reservered | SBZ/RAZ
264
// [5:2] | Counter Event Source |
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// [1:0] | Event Counter Interupt En |
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// Event Counter Configuration Register Addresses
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#define ALT_L2_CACHE_REG2_EV_CNT1_CFG_OFST 0x204
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#define ALT_L2_CACHE_REG2_EV_CNT1_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT1_CFG_OFST)
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#define ALT_L2_CACHE_REG2_EV_CNT0_CFG_OFST 0x208
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#define ALT_L2_CACHE_REG2_EV_CNT0_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT0_CFG_OFST)
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273
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_MASK 0x0000003C
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DISABLE 0x00000000
275
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_CO 0x00000004
276
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRHIT 0x00000008
277
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRREQ 0x0000000C
278
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWHIT 0x00000010
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWREQ 0x00000014
280
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWTREQ 0x00000018
281
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRHIT 0x0000001C
282
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRREQ 0x00000020
283
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_WA 0x00000024
284
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IPFALLOC 0x00000028
285
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFHIT 0x0000002C
286
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFALLOC 0x00000030
287
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRRCVD 0x00000034
288
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRCONF 0x00000038
289
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFRCVD 0x0000003C
290
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_MASK 0x3
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#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_DISABLED 0
292
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_INC 0x00000001
293
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_OF 0x00000002
294
#define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_GEN_DIS 0x00000003
295
296
297
// Event Counter Registers
298
#define ALT_L2_CACHE_REG2_EV_CNT1_OFST 0x20C
299
#define ALT_L2_CACHE_REG2_EV_CNT1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT1_OFST)
300
#define ALT_L2_CACHE_REG2_EV_CNT0_OFST 0x210
301
#define ALT_L2_CACHE_REG2_EV_CNT0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT0_OFST)
302
303
// Interrupt Registers. The following defines are used for the next several registers
304
// Bits Field Description
305
// :-------|:--------------------------|:-----------------------------------------
306
// [31:9] | Reservered | SBZ/RAZ
307
// [8] | DECERR |
308
// [7] | SLVERR |
309
// [6] | ERRRD |
310
// [5] | ERRRT |
311
// [4] | ERRWD |
312
// [3] | ERRWT |
313
// [2] | PARRD |
314
// [1] | PARRT |
315
// [0] | ECNTR |
316
317
#define ALT_L2_CACHE_REG2_INT_DECERR 0x100
318
#define ALT_L2_CACHE_REG2_INT_SLVERR 0x080
319
#define ALT_L2_CACHE_REG2_INT_ERRRD 0x040
320
#define ALT_L2_CACHE_REG2_INT_ERRRT 0x020
321
#define ALT_L2_CACHE_REG2_INT_ERRWD 0x010
322
#define ALT_L2_CACHE_REG2_INT_ERRWT 0x008
323
#define ALT_L2_CACHE_REG2_INT_PARRD 0x004
324
#define ALT_L2_CACHE_REG2_INT_PARRT 0x002
325
#define ALT_L2_CACHE_REG2_INT_ECNTR 0x001
326
327
// Interrupt Enable Mask Register
328
// See "Interrupt Registers" above
329
#define ALT_L2_CACHE_REG2_INT_MASK_OFST 0x214
330
#define ALT_L2_CACHE_REG2_INT_MASK_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_OFST)
331
332
// Interrupt Status Register (Should be RAW_STATUS & INT_MASK
333
// See "Interrupt Registers" above
334
#define ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST 0x218
335
#define ALT_L2_CACHE_REG2_INT_MASK_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST)
336
337
// Interrupt Raw Status Register (Excludes Masks)
338
// See "Interrupt Registers" above
339
#define ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST 0x21C
340
#define ALT_L2_CACHE_REG2_INT_RAW_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST)
341
342
// Interrupt Clear Status Register
343
// See "Interrupt Registers" above
344
#define ALT_L2_CACHE_REG2_INT_CLEAR_OFST 0x220
345
#define ALT_L2_CACHE_REG2_INT_CLEAR_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_CLEAR_OFST)
346
347
// PA Format
348
// Bits Field Description
349
// :-------|:--------------------------|:-----------------------------------------
350
// [31:12] | Tag |
351
// [11:5] | Index |
352
// [4:1] | Reserved |
353
// [0] | Complete |
354
355
// Index or Way Format
356
// Bits Field Description
357
// :-------|:--------------------------|:-----------------------------------------
358
// [31:28] | Way |
359
// [27:12] | Reserved |
360
// [11:5] | Index |
361
// [4:1] | Reserved |
362
// [0] | Complete |
363
364
// Way Format
365
// Bits Field Description
366
// :-------|:--------------------------|:-----------------------------------------
367
// [31:16] | Reserved |
368
// [15:0] | Way Bits |
369
370
// Cache Sync Register
371
// Bits Field Description
372
// :-------|:--------------------------|:-----------------------------------------
373
// [31:1] | Reserved |
374
// [0] | Complete |
375
#define ALT_L2_CACHE_REG7_CACHE_SYNC_OFST 0x730
376
#define ALT_L2_CACHE_REG7_CACHE_SYNC_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CACHE_SYNC_OFST)
377
378
// Invalidate Line by Physical Address
379
// See the "PA Format" above for description of the fields of this register
380
#define ALT_L2_CACHE_REG7_INV_PA_OFST 0x770
381
#define ALT_L2_CACHE_REG7_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_PA_OFST)
382
383
// Invalidate Line by Way
384
// See the "Way Format" above for description of the fields of this register
385
#define ALT_L2_CACHE_REG7_INV_WAY_OFST 0x77C
386
#define ALT_L2_CACHE_REG7_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_WAY_OFST)
387
388
// Clean Line by Physical Address
389
// See the "PA Format" above for description of the fields of this register
390
#define ALT_L2_CACHE_REG7_CLEAN_PA_OFST 0x7B0
391
#define ALT_L2_CACHE_REG7_CLEAN_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_PA_OFST)
392
393
// Clean Line by Set/Way
394
// See the "Index or Way Format" above for a description of the fields of this register
395
#define ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST 0x7B8
396
#define ALT_L2_CACHE_REG7_CLEAN_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST)
397
398
// Invalidate Line by Way
399
// See the "Way Format" above for description of the fields of this register
400
#define ALT_L2_CACHE_REG7_CLEAN_WAY_OFST 0x7BC
401
#define ALT_L2_CACHE_REG7_CLEAN_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_WAY_OFST)
402
403
// Clean and Invalidate Line by Physical Address
404
// See the "PA Format" above for description of the fields of this register
405
#define ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST 0x7F0
406
#define ALT_L2_CACHE_REG7_CLEAN_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST)
407
408
// Clean and Invalidate Line by Set/Way
409
// See the "Index or Way Format" above for a description of the fields of this register
410
#define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST 0x7F8
411
#define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST)
412
413
// Invalidate Line by Way
414
// See the "Way Format" above for description of the fields of this register
415
#define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST 0x7FC
416
#define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST)
417
418
// Lockdown Registers
419
// The format for each of these lockdown registers is the same
420
// Bits Field Description
421
// :-------|:--------------------------|:-----------------------------------------
422
// [31:16] | Reserved |
423
// [15:0] | Way Bits |
424
425
426
#define ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X) (0x900 + (X)*0x10)
427
#define ALT_L2_CACHE_REG9_D_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X))
428
429
#define ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X) (0x904 + (X)*0x10)
430
#define ALT_L2_CACHE_REG9_I_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X))
431
432
#define ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST 0x900
433
#define ALT_L2_CACHE_REG9_D_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST)
434
435
#define ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST 0x904
436
#define ALT_L2_CACHE_REG9_I_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST)
437
438
#define ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST 0x908
439
#define ALT_L2_CACHE_REG9_D_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST)
440
441
#define ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST 0x90C
442
#define ALT_L2_CACHE_REG9_I_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST)
443
444
#define ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST 0x910
445
#define ALT_L2_CACHE_REG9_D_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST)
446
447
#define ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST 0x914
448
#define ALT_L2_CACHE_REG9_I_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST)
449
450
#define ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST 0x918
451
#define ALT_L2_CACHE_REG9_D_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST)
452
453
#define ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST 0x91C
454
#define ALT_L2_CACHE_REG9_I_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST)
455
456
#define ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST 0x920
457
#define ALT_L2_CACHE_REG9_D_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST)
458
459
#define ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST 0x924
460
#define ALT_L2_CACHE_REG9_I_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST)
461
462
#define ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST 0x928
463
#define ALT_L2_CACHE_REG9_D_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST)
464
465
#define ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST 0x92C
466
#define ALT_L2_CACHE_REG9_I_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST)
467
468
#define ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST 0x930
469
#define ALT_L2_CACHE_REG9_D_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST)
470
471
#define ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST 0x934
472
#define ALT_L2_CACHE_REG9_I_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST)
473
474
#define ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST 0x938
475
#define ALT_L2_CACHE_REG9_D_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST)
476
477
#define ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST 0x93C
478
#define ALT_L2_CACHE_REG9_I_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST)
479
480
// Lockdown by Line Enable
481
// Bits Field Description
482
// :-------|:--------------------------|:-----------------------------------------
483
// [31:1] | Reserved |
484
// [0] | Enable |
485
486
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST 0x950
487
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST)
488
#define ALT_L2_CACHE_REG9_LOCK_LINE_EN_MASK 0x00000001
489
#define ALT_L2_CACHE_REG9_LOCK_LINE_ENABLE 0x00000001
490
#define ALT_L2_CACHE_REG9_LOCK_LINE_DISABLE 0
491
492
#define ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST 0x954
493
#define ALT_L2_CACHE_REG9_UNLOCK_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST)
494
495
// Address Filtering Start Register
496
// The Address Filtering Start Register is a read and write register.
497
// Bits Field Description
498
// :-------|:--------------------------|:-----------------------------------------
499
// [31:20] | address_filtering_start | Address filtering start address for
500
// | | bits [31:20] of the filtering address.
501
// [19:1] | Reserved | SBZ/RAZ
502
// [0] | address_filtering_enable | 0 - address filtering disabled
503
// | | 1 - address filtering enabled.
504
505
// Address Filtering Start Register Address
506
#define ALT_L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
507
#define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ADDR_FILTERING_START_OFST)
508
// Address Filtering Start Register - Start Value Mask
509
#define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
510
// Address Filtering Start Register - Reset Start Address Value (1 MB)
511
#define ALT_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
512
// Address Filtering Start Register - Enable Flag Mask
513
#define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
514
// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
515
#define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
516
517
// Address Filtering End Register
518
// The Address Filtering End Register is a read and write register.
519
// Bits Field Description
520
// :-------|:--------------------------|:-----------------------------------------
521
// [31:20] | address_filtering_end | Address filtering end address for bits
522
// | | [31:20] of the filtering address.
523
// [19:0] | Reserved | SBZ/RAZ
524
525
// Address Filtering End Register Address
526
#define ALT_L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
527
#define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ADDR_FILTERING_END_OFST)
528
// Address Filtering End Register - End Value Mask
529
#define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
530
// Address Filtering End Register - Reset End Address Value (3 GiB)
531
#define ALT_L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
532
533
#ifdef __cplusplus
534
}
535
#endif
/* __cplusplus */
536
#endif
/* __ALT_L2_P310_H__ */
include
alt_l2_p310.h
Generated on Tue Sep 8 2015 13:35:04 for Altera HWLIB by
1.8.2