![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Name: I2C Enable Status Register
Size: 3 bits
Address Offset: 0x9C
Read/Write Access: Read
The register is used to report the DW_apb_i2c hardware
status when the IC_ENABLE[0] register is set from 1 to 0;
that is, when DW_apb_i2c is disabled.
If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
and bit 0 is forced to 1.
If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid
as soon as bit 0 is read as '0'.
Note
When IC_ENABLE[0] has been written with '0'a delay occurs for
bit 0 to be read as '0' because disabling the DW_apb_i2c
depends on I2C bus activities.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | ALT_I2C_EN_STAT_IC_EN |
[1] | R | 0x0 | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY |
[2] | R | 0x0 | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST |
[31:3] | ??? | 0x0 | UNDEFINED |
Field : ic_en | |
ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, DW_apb_i2c is deemed to be in an enabled state. When read as 0, DW_apb_i2c is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1). Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_EN_STAT_IC_EN_LSB 0 |
#define | ALT_I2C_EN_STAT_IC_EN_MSB 0 |
#define | ALT_I2C_EN_STAT_IC_EN_WIDTH 1 |
#define | ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 |
#define | ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe |
#define | ALT_I2C_EN_STAT_IC_EN_RESET 0x0 |
#define | ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : slv_disabled_while_busy | |
Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master; OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002) |
Field : slv_rx_data_lost | |
Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1. When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004) |
Data Structures | |
struct | ALT_I2C_EN_STAT_s |
Macros | |
#define | ALT_I2C_EN_STAT_RESET 0x00000000 |
#define | ALT_I2C_EN_STAT_OFST 0x9c |
#define | ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) |
Typedefs | |
typedef struct ALT_I2C_EN_STAT_s | ALT_I2C_EN_STAT_t |
struct ALT_I2C_EN_STAT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_EN_STAT.
Data Fields | ||
---|---|---|
const uint32_t | ic_en: 1 | ALT_I2C_EN_STAT_IC_EN |
const uint32_t | slv_disabled_while_busy: 1 | ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY |
const uint32_t | slv_rx_data_lost: 1 | ALT_I2C_EN_STAT_SLV_RX_DATA_LOST |
uint32_t | __pad0__: 29 | UNDEFINED |
#define ALT_I2C_EN_STAT_IC_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_IC_EN register field.
#define ALT_I2C_EN_STAT_IC_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_IC_EN register field.
#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1 |
The width in bits of the ALT_I2C_EN_STAT_IC_EN register field.
#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_I2C_EN_STAT_IC_EN register field value.
#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_I2C_EN_STAT_IC_EN register field value.
#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0 |
The reset value of the ALT_I2C_EN_STAT_IC_EN register field.
#define ALT_I2C_EN_STAT_IC_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_I2C_EN_STAT_IC_EN field value from a register.
#define ALT_I2C_EN_STAT_IC_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_I2C_EN_STAT_IC_EN register field value suitable for setting the register.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1 |
The width in bits of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002 |
The mask used to set the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0 |
The reset value of the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY field value from a register.
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY register field value suitable for setting the register.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1 |
The width in bits of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004 |
The mask used to set the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0 |
The reset value of the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_I2C_EN_STAT_SLV_RX_DATA_LOST field value from a register.
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_I2C_EN_STAT_SLV_RX_DATA_LOST register field value suitable for setting the register.
#define ALT_I2C_EN_STAT_RESET 0x00000000 |
The reset value of the ALT_I2C_EN_STAT register.
#define ALT_I2C_EN_STAT_OFST 0x9c |
The byte offset of the ALT_I2C_EN_STAT register from the beginning of the component.
#define ALT_I2C_EN_STAT_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST)) |
The address of the ALT_I2C_EN_STAT register.
typedef struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t |
The typedef declaration for register ALT_I2C_EN_STAT.