Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECC_RDataecc0bus

Description

The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.

Register Layout

Bits Access Reset Description
[6:0] RW 0x0 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS
[7] ??? 0x0 UNDEFINED
[14:8] RW 0x0 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS
[15] ??? 0x0 UNDEFINED
[22:16] RW 0x0 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS
[23] ??? 0x0 UNDEFINED
[30:24] RW 0x0 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS
[31] ??? 0x0 UNDEFINED

Field : ECC_RDataecc0BUS

Eccdata will be read to this register field.

Field Access Macros:

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB   0
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB   6
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH   7
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK   0x0000007f
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK   0xffffff80
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET   0x0
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value)   (((value) & 0x0000007f) >> 0)
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value)   (((value) << 0) & 0x0000007f)
 

Field : ECC_RDataecc1BUS

Eccdata will be read to this register field.

Field Access Macros:

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB   8
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB   14
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH   7
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK   0x00007f00
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK   0xffff80ff
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET   0x0
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value)   (((value) & 0x00007f00) >> 8)
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value)   (((value) << 8) & 0x00007f00)
 

Field : ECC_RDataecc2BUS

Eccdata will be read to this register field.

Field Access Macros:

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB   16
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB   22
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH   7
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK   0x007f0000
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK   0xff80ffff
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET   0x0
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value)   (((value) & 0x007f0000) >> 16)
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value)   (((value) << 16) & 0x007f0000)
 

Field : ECC_RDataecc3BUS

Eccdata will be read to this register field.

Field Access Macros:

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB   24
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB   30
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH   7
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK   0x7f000000
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK   0x80ffffff
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET   0x0
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value)   (((value) & 0x7f000000) >> 24)
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value)   (((value) << 24) & 0x7f000000)
 

Data Structures

struct  ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_s
 

Macros

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_RESET   0x00000000
 
#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_OFST   0x64
 

Typedefs

typedef struct
ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_s 
ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_t
 

Data Structure Documentation

struct ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS.

Data Fields
uint32_t ECC_RDataecc0BUS: 7 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS
uint32_t __pad0__: 1 UNDEFINED
uint32_t ECC_RDataecc1BUS: 7 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS
uint32_t __pad1__: 1 UNDEFINED
uint32_t ECC_RDataecc2BUS: 7 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS
uint32_t __pad2__: 1 UNDEFINED
uint32_t ECC_RDataecc3BUS: 7 ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS
uint32_t __pad3__: 1 UNDEFINED

Macro Definitions

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB   6

The Most Significant Bit (MSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH   7

The width in bits of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK   0x0000007f

The mask used to set the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK   0xffffff80

The mask used to clear the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET   0x0

The reset value of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET (   value)    (((value) & 0x0000007f) >> 0)

Extracts the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS field value from a register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET (   value)    (((value) << 0) & 0x0000007f)

Produces a ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS register field value suitable for setting the register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB   14

The Most Significant Bit (MSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH   7

The width in bits of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK   0x00007f00

The mask used to set the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK   0xffff80ff

The mask used to clear the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET   0x0

The reset value of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET (   value)    (((value) & 0x00007f00) >> 8)

Extracts the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS field value from a register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET (   value)    (((value) << 8) & 0x00007f00)

Produces a ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS register field value suitable for setting the register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB   16

The Least Significant Bit (LSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB   22

The Most Significant Bit (MSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH   7

The width in bits of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK   0x007f0000

The mask used to set the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK   0xff80ffff

The mask used to clear the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET   0x0

The reset value of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET (   value)    (((value) & 0x007f0000) >> 16)

Extracts the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS field value from a register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET (   value)    (((value) << 16) & 0x007f0000)

Produces a ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS register field value suitable for setting the register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB   24

The Least Significant Bit (LSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB   30

The Most Significant Bit (MSB) position of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH   7

The width in bits of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK   0x7f000000

The mask used to set the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK   0x80ffffff

The mask used to clear the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET   0x0

The reset value of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET (   value)    (((value) & 0x7f000000) >> 24)

Extracts the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS field value from a register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET (   value)    (((value) << 24) & 0x7f000000)

Produces a ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS register field value suitable for setting the register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_RESET   0x00000000

The reset value of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS register.

#define ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS_OFST   0x64

The byte offset of the ALT_ECC_OTG1_ECC_ECC_RDATAECC0BUS register from the beginning of the component.

Typedef Documentation