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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Write One to Clear corresponding fields in Bypass Register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | MPU Bypass |
[1] | RW | 0x1 | NOC Bypass |
[2] | RW | 0x1 | S2F User0 Bypass |
[3] | RW | 0x1 | HMC PLL Reference Bypass |
[4] | RW | 0x1 | PLL RFEN Clock Bypass |
[5] | RW | 0x1 | PLL FBEN Clock Bypass |
[31:6] | ??? | 0x0 | UNDEFINED |
Field : MPU Bypass - mpu | |
If set, the MPU clock group will be bypassed to the input clock reference of the Main PLL. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_LSB 0 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_MSB 0 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET(value) (((value) << 0) & 0x00000001) |
Field : NOC Bypass - noc | |
If set, the NOC clock group will be bypassed to the input clock reference of the Main PLL. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_LSB 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_MSB 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET(value) (((value) << 1) & 0x00000002) |
Field : S2F User0 Bypass - s2fuser0 | |
If set, the s2f_user0_clk will be bypassed to the input clock reference of the Main PLL. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_LSB 2 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_MSB 2 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET(value) (((value) << 2) & 0x00000004) |
Field : HMC PLL Reference Bypass - hmcpllref | |
If set, the hmc_pll_ref_clk will be bypassed to the boot_clk. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_LSB 3 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_MSB 3 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET_MSK 0x00000008 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_CLR_MSK 0xfffffff7 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008) |
Field : PLL RFEN Clock Bypass - rfen | |
If set, the pll_main_rfen_clk will be bypassed to the boot_clk. The pll_main_rfen_clk is used to synchronously update the Denominator to the Main PLL. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_LSB 4 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_MSB 4 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET_MSK 0x00000010 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_CLR_MSK 0xffffffef |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET(value) (((value) << 4) & 0x00000010) |
Field : PLL FBEN Clock Bypass - fben | |
If set, the pll_main_fben_clk will be bypassed to the boot_clk. The pll_main_fben_clk is used to synchronously update the Numerator to the Main PLL. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_LSB 5 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_MSB 5 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET_MSK 0x00000020 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_CLR_MSK 0xffffffdf |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET(value) (((value) << 5) & 0x00000020) |
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_BYPASSR_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_RESET 0x0000003f |
#define | ALT_CLKMGR_MAINPLL_BYPASSR_OFST 0x1c |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_BYPASSR_s | ALT_CLKMGR_MAINPLL_BYPASSR_t |
struct ALT_CLKMGR_MAINPLL_BYPASSR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_BYPASSR.
Data Fields | ||
---|---|---|
uint32_t | mpu: 1 | MPU Bypass |
uint32_t | noc: 1 | NOC Bypass |
uint32_t | s2fuser0: 1 | S2F User0 Bypass |
uint32_t | hmcpllref: 1 | HMC PLL Reference Bypass |
uint32_t | rfen: 1 | PLL RFEN Clock Bypass |
uint32_t | fben: 1 | PLL FBEN Clock Bypass |
uint32_t | __pad0__: 26 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_MPU field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_MPU register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_NOC field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_NOC register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0 register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET_MSK 0x00000008 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET_MSK 0x00000010 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_RFEN field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_RFEN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET_MSK 0x00000020 |
The mask used to set the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_CLKMGR_MAINPLL_BYPASSR_FBEN field value from a register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_CLKMGR_MAINPLL_BYPASSR_FBEN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_RESET 0x0000003f |
The reset value of the ALT_CLKMGR_MAINPLL_BYPASSR register.
#define ALT_CLKMGR_MAINPLL_BYPASSR_OFST 0x1c |
The byte offset of the ALT_CLKMGR_MAINPLL_BYPASSR register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_BYPASSR_s ALT_CLKMGR_MAINPLL_BYPASSR_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_BYPASSR.