Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Register 5 (Status Register) - Status

Description

The Status register contains all status bits that the DMA reports to the host. The software driver reads this register during an interrupt service routine or polling. Most of the fields in this register cause the host to be interrupted. The bits of this register are not cleared when read. Writing 1'b1 to (unreserved) Bits[16:0] of this register clears these bits and writing 1'b0 has no effect. Each field (Bits[16:0]) can be masked by masking the appropriate bit in Register 7 (Interrupt Enable Register).

Register Layout

Bits Access Reset Description
[0] RW 0x0 Transmit Interrupt
[1] RW 0x0 Transmit Process Stopped
[2] RW 0x0 Transmit Buffer Unavailable
[3] RW 0x0 Transmit Jabber Timeout
[4] RW 0x0 Receive Overflow
[5] RW 0x0 Transmit Underflow
[6] RW 0x0 Receive Interrupt
[7] RW 0x0 Receive Buffer Unavailable
[8] RW 0x0 Receive Process Stopped
[9] RW 0x0 Receive Watchdog Timeout
[10] RW 0x0 Early Transmit Interrupt
[12:11] ??? 0x0 UNDEFINED
[13] RW 0x0 Fatal Bus Error Interrupt
[14] RW 0x0 Early Receive Interrupt
[15] RW 0x0 Abnormal Interrupt Summary
[16] RW 0x0 Normal Interrupt Summary
[19:17] R 0x0 Received Process State
[22:20] R 0x0 Transmit Process State
[25:23] R 0x0 Error Bits
[26] R 0x0 GMAC Line Interface Interrupt
[27] R 0x0 GMAC MMC Interrupt
[28] ??? 0x0 UNDEFINED
[29] R 0x0 Timestamp Trigger Interrupt
[30] R 0x0 GMAC LPI Interrupt (for Channel 0)
[31] ??? 0x0 UNDEFINED

Field : Transmit Interrupt - ti

This bit indicates that the frame transmission is complete. When transmission is complete, the Bit 31 (Interrupt on Completion) of TDES1 is reset in the first descriptor, and the specific frame status information is updated in the descriptor.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TI_LSB   0
 
#define ALT_EMAC_DMA_STAT_TI_MSB   0
 
#define ALT_EMAC_DMA_STAT_TI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_TI_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_STAT_TI_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_STAT_TI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TI_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_STAT_TI_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit Process Stopped - tps

This bit is set when the transmission is stopped.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TPS_LSB   1
 
#define ALT_EMAC_DMA_STAT_TPS_MSB   1
 
#define ALT_EMAC_DMA_STAT_TPS_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_TPS_SET_MSK   0x00000002
 
#define ALT_EMAC_DMA_STAT_TPS_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_DMA_STAT_TPS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TPS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_DMA_STAT_TPS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Transmit Buffer Unavailable - tu

This bit indicates that the host owns the Next Descriptor in the Transmit List and the DMA cannot acquire it. Transmission is suspended. Bits[22:20] explain the Transmit Process state transitions.

To resume processing Transmit descriptors, the host should change the ownership of the descriptor by setting TDES0[31] and then issue a Transmit Poll Demand command.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TU_LSB   2
 
#define ALT_EMAC_DMA_STAT_TU_MSB   2
 
#define ALT_EMAC_DMA_STAT_TU_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_TU_SET_MSK   0x00000004
 
#define ALT_EMAC_DMA_STAT_TU_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_DMA_STAT_TU_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TU_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_DMA_STAT_TU_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Transmit Jabber Timeout - tjt

This bit indicates that the Transmit Jabber Timer expired, which happens when the frame size exceeds 2,048 (10,240 bytes when the Jumbo frame is enabled). When the Jabber Timeout occurs, the transmission process is aborted and placed in the Stopped state. This causes the Transmit Jabber Timeout TDES0[14] flag to assert.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TJT_LSB   3
 
#define ALT_EMAC_DMA_STAT_TJT_MSB   3
 
#define ALT_EMAC_DMA_STAT_TJT_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_TJT_SET_MSK   0x00000008
 
#define ALT_EMAC_DMA_STAT_TJT_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_DMA_STAT_TJT_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TJT_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_DMA_STAT_TJT_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Receive Overflow - ovf

This bit indicates that the Receive Buffer had an Overflow during frame reception. If the partial frame is transferred to the application, the overflow status is set in RDES0[11].

Field Access Macros:

#define ALT_EMAC_DMA_STAT_OVF_LSB   4
 
#define ALT_EMAC_DMA_STAT_OVF_MSB   4
 
#define ALT_EMAC_DMA_STAT_OVF_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_OVF_SET_MSK   0x00000010
 
#define ALT_EMAC_DMA_STAT_OVF_CLR_MSK   0xffffffef
 
#define ALT_EMAC_DMA_STAT_OVF_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_OVF_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_DMA_STAT_OVF_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Transmit Underflow - unf

This bit indicates that the Transmit Buffer had an Underflow during frame transmission. Transmission is suspended and an Underflow Error TDES0[1] is set.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_UNF_LSB   5
 
#define ALT_EMAC_DMA_STAT_UNF_MSB   5
 
#define ALT_EMAC_DMA_STAT_UNF_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_UNF_SET_MSK   0x00000020
 
#define ALT_EMAC_DMA_STAT_UNF_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_DMA_STAT_UNF_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_UNF_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_DMA_STAT_UNF_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Receive Interrupt - ri

This bit indicates that the frame reception is complete. When reception is complete, the Bit 31 of RDES1 (Disable Interrupt on Completion) is reset in the last Descriptor, and the specific frame status information is updated in the descriptor.

The reception remains in the Running state.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_RI_LSB   6
 
#define ALT_EMAC_DMA_STAT_RI_MSB   6
 
#define ALT_EMAC_DMA_STAT_RI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_RI_SET_MSK   0x00000040
 
#define ALT_EMAC_DMA_STAT_RI_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_DMA_STAT_RI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_RI_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_DMA_STAT_RI_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Receive Buffer Unavailable - ru

This bit indicates that the host owns the Next Descriptor in the Receive List and the DMA cannot acquire it. The Receive Process is suspended. To resume processing Receive descriptors, the host should change the ownership of the descriptor and issue a Receive Poll Demand command. If no Receive Poll Demand is issued, the Receive Process resumes when the next recognized incoming frame is received. This bit is set only when the previous Receive Descriptor is owned by the DMA.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_RU_LSB   7
 
#define ALT_EMAC_DMA_STAT_RU_MSB   7
 
#define ALT_EMAC_DMA_STAT_RU_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_RU_SET_MSK   0x00000080
 
#define ALT_EMAC_DMA_STAT_RU_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_DMA_STAT_RU_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_RU_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_DMA_STAT_RU_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Receive Process Stopped - rps

This bit is asserted when the Receive Process enters the Stopped state.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_RPS_LSB   8
 
#define ALT_EMAC_DMA_STAT_RPS_MSB   8
 
#define ALT_EMAC_DMA_STAT_RPS_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_RPS_SET_MSK   0x00000100
 
#define ALT_EMAC_DMA_STAT_RPS_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_DMA_STAT_RPS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_RPS_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_DMA_STAT_RPS_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Receive Watchdog Timeout - rwt

This bit is asserted when a frame with length greater than 2,048 bytes is received (10, 240 when Jumbo Frame mode is enabled).

Field Access Macros:

#define ALT_EMAC_DMA_STAT_RWT_LSB   9
 
#define ALT_EMAC_DMA_STAT_RWT_MSB   9
 
#define ALT_EMAC_DMA_STAT_RWT_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_RWT_SET_MSK   0x00000200
 
#define ALT_EMAC_DMA_STAT_RWT_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_DMA_STAT_RWT_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_RWT_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_DMA_STAT_RWT_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Early Transmit Interrupt - eti

This bit indicates that the frame to be transmitted is fully transferred to the MTL Transmit FIFO.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_ETI_LSB   10
 
#define ALT_EMAC_DMA_STAT_ETI_MSB   10
 
#define ALT_EMAC_DMA_STAT_ETI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_ETI_SET_MSK   0x00000400
 
#define ALT_EMAC_DMA_STAT_ETI_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_DMA_STAT_ETI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_ETI_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_DMA_STAT_ETI_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Fatal Bus Error Interrupt - fbi

This bit indicates that a bus error occurred, as described in Bits[25:23]. When this bit is set, the corresponding DMA engine disables all of its bus accesses.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_FBI_LSB   13
 
#define ALT_EMAC_DMA_STAT_FBI_MSB   13
 
#define ALT_EMAC_DMA_STAT_FBI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_FBI_SET_MSK   0x00002000
 
#define ALT_EMAC_DMA_STAT_FBI_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_DMA_STAT_FBI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_FBI_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_DMA_STAT_FBI_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Early Receive Interrupt - eri

This bit indicates that the DMA had filled the first data buffer of the packet. Bit 6 (RI) of this register automatically clears this bit.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_ERI_LSB   14
 
#define ALT_EMAC_DMA_STAT_ERI_MSB   14
 
#define ALT_EMAC_DMA_STAT_ERI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_ERI_SET_MSK   0x00004000
 
#define ALT_EMAC_DMA_STAT_ERI_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_DMA_STAT_ERI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_ERI_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_DMA_STAT_ERI_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Abnormal Interrupt Summary - ais

Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):

  • Register 5[1]: Transmit Process Stopped
  • Register 5[3]: Transmit Jabber Timeout
  • Register 5[4]: Receive FIFO Overflow
  • Register 5[5]: Transmit Underflow
  • Register 5[7]: Receive Buffer Unavailable
  • Register 5[8]: Receive Process Stopped
  • Register 5[9]: Receive Watchdog Timeout
  • Register 5[10]: Early Transmit Interrupt
  • Register 5[13]: Fatal Bus Error

Only unmasked bits affect the Abnormal Interrupt Summary bit.

This is a sticky bit and must be cleared each time a corresponding bit, which causes AIS to be set, is cleared.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_AIS_LSB   15
 
#define ALT_EMAC_DMA_STAT_AIS_MSB   15
 
#define ALT_EMAC_DMA_STAT_AIS_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_AIS_SET_MSK   0x00008000
 
#define ALT_EMAC_DMA_STAT_AIS_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_DMA_STAT_AIS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_AIS_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_DMA_STAT_AIS_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Normal Interrupt Summary - nis

Normal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in Register 7 (Interrupt Enable Register):

  • Register 5[0]: Transmit Interrupt
  • Register 5[2]: Transmit Buffer Unavailable
  • Register 5[6]: Receive Interrupt
  • Register 5[14]: Early Receive Interrupt

Only unmasked bits (interrupts for which interrupt enable is set in Register 7) affect the Normal Interrupt Summary bit.

This is a sticky bit and must be cleared (by writing 1 to this bit) each time a corresponding bit, which causes NIS to be set, is cleared.

Field Access Macros:

#define ALT_EMAC_DMA_STAT_NIS_LSB   16
 
#define ALT_EMAC_DMA_STAT_NIS_MSB   16
 
#define ALT_EMAC_DMA_STAT_NIS_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_NIS_SET_MSK   0x00010000
 
#define ALT_EMAC_DMA_STAT_NIS_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_DMA_STAT_NIS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_NIS_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_DMA_STAT_NIS_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Received Process State - rs

This field indicates the Receive DMA FSM state. This field does not generate an interrupt.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_RS_E_STOPPED 0x0 Stopped Reset or Stop Receive Command issued
ALT_EMAC_DMA_STAT_RS_E_RUNFETCH 0x1 Running: Fetching Receive Transfer Descriptor
ALT_EMAC_DMA_STAT_RS_E_RESERVE 0x2 Reserved for future use
ALT_EMAC_DMA_STAT_RS_E_RUNWAIT 0x3 Running: Waiting for receive packet
ALT_EMAC_DMA_STAT_RS_E_SUSPEND 0x4 Suspended: Receive Descriptor Unavailable
ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE 0x5 Running: Closing Receive Descriptor
ALT_EMAC_DMA_STAT_RS_E_TIMESTMP 0x6 TIME_STAMP write state
ALT_EMAC_DMA_STAT_RS_E_RUNTRANS 0x7 Transferring rcv packet data from receive buffer
: to host memory

Field Access Macros:

#define ALT_EMAC_DMA_STAT_RS_E_STOPPED   0x0
 
#define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH   0x1
 
#define ALT_EMAC_DMA_STAT_RS_E_RESERVE   0x2
 
#define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT   0x3
 
#define ALT_EMAC_DMA_STAT_RS_E_SUSPEND   0x4
 
#define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE   0x5
 
#define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP   0x6
 
#define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS   0x7
 
#define ALT_EMAC_DMA_STAT_RS_LSB   17
 
#define ALT_EMAC_DMA_STAT_RS_MSB   19
 
#define ALT_EMAC_DMA_STAT_RS_WIDTH   3
 
#define ALT_EMAC_DMA_STAT_RS_SET_MSK   0x000e0000
 
#define ALT_EMAC_DMA_STAT_RS_CLR_MSK   0xfff1ffff
 
#define ALT_EMAC_DMA_STAT_RS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_RS_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_EMAC_DMA_STAT_RS_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : Transmit Process State - ts

This field indicates the Transmit DMA FSM state. This field does not generate an interrupt.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_TS_E_STOPPED 0x0 Stopped Reset or Stop Transmit Command
ALT_EMAC_DMA_STAT_TS_E_RUNFETCH 0x1 Running: Fetching Tranmit Transfer Descriptor
ALT_EMAC_DMA_STAT_TS_E_RUNWAIT 0x2 Running; Waiting for status
ALT_EMAC_DMA_STAT_TS_E_RUNRD 0x3 Running; Reading Data host memory buffer and
: queuing it to transmit buffer (Tx FIFO)
ALT_EMAC_DMA_STAT_TS_E_TIMESTMP 0x4 TIME_STAMP write state
ALT_EMAC_DMA_STAT_TS_E_RESERVE 0x5 Reserved for future use
ALT_EMAC_DMA_STAT_TS_E_SUSPTX 0x6 Suspended; Transmit Descriptor Unavailable or
: Transmit Buffer Underflow
ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE 0x7 Running; Closing Transmit Descriptor

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TS_E_STOPPED   0x0
 
#define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH   0x1
 
#define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT   0x2
 
#define ALT_EMAC_DMA_STAT_TS_E_RUNRD   0x3
 
#define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP   0x4
 
#define ALT_EMAC_DMA_STAT_TS_E_RESERVE   0x5
 
#define ALT_EMAC_DMA_STAT_TS_E_SUSPTX   0x6
 
#define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE   0x7
 
#define ALT_EMAC_DMA_STAT_TS_LSB   20
 
#define ALT_EMAC_DMA_STAT_TS_MSB   22
 
#define ALT_EMAC_DMA_STAT_TS_WIDTH   3
 
#define ALT_EMAC_DMA_STAT_TS_SET_MSK   0x00700000
 
#define ALT_EMAC_DMA_STAT_TS_CLR_MSK   0xff8fffff
 
#define ALT_EMAC_DMA_STAT_TS_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TS_GET(value)   (((value) & 0x00700000) >> 20)
 
#define ALT_EMAC_DMA_STAT_TS_SET(value)   (((value) << 20) & 0x00700000)
 

Field : Error Bits - eb

This field indicates the type of error that caused a Bus Error, for example, error response on the AHB or AXI interface. This field is valid only when Bit 13 (FBI) is set. This field does not generate an interrupt.

  • Bit 23

    • 1'b1: Error during data transfer by the Tx DMA
    • 1'b0: Error during data transfer by the Rx DMA
  • Bit 24

    • 1'b1: Error during read transfer
    • 1'b0: Error during write transfer
  • Bit 25

    • 1'b1: Error during descriptor access
    • 1'b0: Error during data buffer access

Field Access Macros:

#define ALT_EMAC_DMA_STAT_EB_LSB   23
 
#define ALT_EMAC_DMA_STAT_EB_MSB   25
 
#define ALT_EMAC_DMA_STAT_EB_WIDTH   3
 
#define ALT_EMAC_DMA_STAT_EB_SET_MSK   0x03800000
 
#define ALT_EMAC_DMA_STAT_EB_CLR_MSK   0xfc7fffff
 
#define ALT_EMAC_DMA_STAT_EB_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_EB_GET(value)   (((value) & 0x03800000) >> 23)
 
#define ALT_EMAC_DMA_STAT_EB_SET(value)   (((value) << 23) & 0x03800000)
 

Field : GMAC Line Interface Interrupt - gli

This bit reflects an interrupt event in the PCS (link change and AN complete), SMII (link change), or RGMII (link change) interface block of the EMAC. The software must read the corresponding registers (Register 49 for PCS or Register 54 for SMII or RGMII) in the EMAC to get the exact cause of the interrupt and clear the source of interrupt to make this bit as 1'b0. The interrupt signal from the EMAC subsystem (sbd_intr_o) is high when this bit is high.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP 0x0 No Interrupt
ALT_EMAC_DMA_STAT_GLI_E_INTERRUP 0x1 GMAC Line Interrupt

Field Access Macros:

#define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP   0x0
 
#define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP   0x1
 
#define ALT_EMAC_DMA_STAT_GLI_LSB   26
 
#define ALT_EMAC_DMA_STAT_GLI_MSB   26
 
#define ALT_EMAC_DMA_STAT_GLI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_GLI_SET_MSK   0x04000000
 
#define ALT_EMAC_DMA_STAT_GLI_CLR_MSK   0xfbffffff
 
#define ALT_EMAC_DMA_STAT_GLI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_GLI_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_EMAC_DMA_STAT_GLI_SET(value)   (((value) << 26) & 0x04000000)
 

Field : GMAC MMC Interrupt - gmi

This bit reflects an interrupt event in the MMC block of the EMAC. The software must read the corresponding registers in the EMAC to get the exact cause of interrupt and clear the source of interrupt to make this bit as 1'b0. The interrupt signal from the EMAC subsystem (sbd_intr_o) is high when this bit is high.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP 0x0 No Interrupt
ALT_EMAC_DMA_STAT_GMI_E_INTERRUP 0x1 GMAC MMC Interrupt

Field Access Macros:

#define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP   0x0
 
#define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP   0x1
 
#define ALT_EMAC_DMA_STAT_GMI_LSB   27
 
#define ALT_EMAC_DMA_STAT_GMI_MSB   27
 
#define ALT_EMAC_DMA_STAT_GMI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_GMI_SET_MSK   0x08000000
 
#define ALT_EMAC_DMA_STAT_GMI_CLR_MSK   0xf7ffffff
 
#define ALT_EMAC_DMA_STAT_GMI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_GMI_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_EMAC_DMA_STAT_GMI_SET(value)   (((value) << 27) & 0x08000000)
 

Field : Timestamp Trigger Interrupt - tti

This bit indicates an interrupt event in the Timestamp Generator block of EMAC. The software must read the corresponding registers in the EMAC to get the exact cause of interrupt and clear its source to reset this bit to 1'b0. When this bit is high, the interrupt signal from the EMAC subsystem (sbd_intr_o) is high.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP 0x0 No Interrupt
ALT_EMAC_DMA_STAT_TTI_E_INTERRUP 0x1 Timestamp Trigger Interrupt

Field Access Macros:

#define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP   0x0
 
#define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP   0x1
 
#define ALT_EMAC_DMA_STAT_TTI_LSB   29
 
#define ALT_EMAC_DMA_STAT_TTI_MSB   29
 
#define ALT_EMAC_DMA_STAT_TTI_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_TTI_SET_MSK   0x20000000
 
#define ALT_EMAC_DMA_STAT_TTI_CLR_MSK   0xdfffffff
 
#define ALT_EMAC_DMA_STAT_TTI_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_TTI_GET(value)   (((value) & 0x20000000) >> 29)
 
#define ALT_EMAC_DMA_STAT_TTI_SET(value)   (((value) << 29) & 0x20000000)
 

Field : GMAC LPI Interrupt (for Channel 0) - glpii

This bit indicates an interrupt event in the LPI logic of the EMAC. To reset this bit to 1'b0, the software must read the corresponding registers in the EMAC to get the exact cause of the interrupt and clear its source.

When this bit is high, the interrupt signal from the MAC (sbd_intr_o) is high.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP 0x0 No Interrupt
ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP 0x1 GMAC LPI Interrupt

Field Access Macros:

#define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP   0x0
 
#define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP   0x1
 
#define ALT_EMAC_DMA_STAT_GLPII_LSB   30
 
#define ALT_EMAC_DMA_STAT_GLPII_MSB   30
 
#define ALT_EMAC_DMA_STAT_GLPII_WIDTH   1
 
#define ALT_EMAC_DMA_STAT_GLPII_SET_MSK   0x40000000
 
#define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK   0xbfffffff
 
#define ALT_EMAC_DMA_STAT_GLPII_RESET   0x0
 
#define ALT_EMAC_DMA_STAT_GLPII_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_EMAC_DMA_STAT_GLPII_SET(value)   (((value) << 30) & 0x40000000)
 

Data Structures

struct  ALT_EMAC_DMA_STAT_s
 

Macros

#define ALT_EMAC_DMA_STAT_OFST   0x14
 
#define ALT_EMAC_DMA_STAT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST))
 

Typedefs

typedef struct ALT_EMAC_DMA_STAT_s ALT_EMAC_DMA_STAT_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_STAT.

Data Fields
uint32_t ti: 1 Transmit Interrupt
uint32_t tps: 1 Transmit Process Stopped
uint32_t tu: 1 Transmit Buffer Unavailable
uint32_t tjt: 1 Transmit Jabber Timeout
uint32_t ovf: 1 Receive Overflow
uint32_t unf: 1 Transmit Underflow
uint32_t ri: 1 Receive Interrupt
uint32_t ru: 1 Receive Buffer Unavailable
uint32_t rps: 1 Receive Process Stopped
uint32_t rwt: 1 Receive Watchdog Timeout
uint32_t eti: 1 Early Transmit Interrupt
uint32_t __pad0__: 2 UNDEFINED
uint32_t fbi: 1 Fatal Bus Error Interrupt
uint32_t eri: 1 Early Receive Interrupt
uint32_t ais: 1 Abnormal Interrupt Summary
uint32_t nis: 1 Normal Interrupt Summary
const uint32_t rs: 3 Received Process State
const uint32_t ts: 3 Transmit Process State
const uint32_t eb: 3 Error Bits
const uint32_t gli: 1 GMAC Line Interface Interrupt
const uint32_t gmi: 1 GMAC MMC Interrupt
uint32_t __pad1__: 1 UNDEFINED
const uint32_t tti: 1 Timestamp Trigger Interrupt
const uint32_t glpii: 1 GMAC LPI Interrupt (for Channel 0)
uint32_t __pad2__: 1 UNDEFINED

Macro Definitions

#define ALT_EMAC_DMA_STAT_TI_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TI register field.

#define ALT_EMAC_DMA_STAT_TI_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TI register field.

#define ALT_EMAC_DMA_STAT_TI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_TI register field.

#define ALT_EMAC_DMA_STAT_TI_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_STAT_TI register field value.

#define ALT_EMAC_DMA_STAT_TI_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_STAT_TI register field value.

#define ALT_EMAC_DMA_STAT_TI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TI register field.

#define ALT_EMAC_DMA_STAT_TI_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_STAT_TI field value from a register.

#define ALT_EMAC_DMA_STAT_TI_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_STAT_TI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_TPS_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TPS register field.

#define ALT_EMAC_DMA_STAT_TPS_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TPS register field.

#define ALT_EMAC_DMA_STAT_TPS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_TPS register field.

#define ALT_EMAC_DMA_STAT_TPS_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_DMA_STAT_TPS register field value.

#define ALT_EMAC_DMA_STAT_TPS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_DMA_STAT_TPS register field value.

#define ALT_EMAC_DMA_STAT_TPS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TPS register field.

#define ALT_EMAC_DMA_STAT_TPS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_DMA_STAT_TPS field value from a register.

#define ALT_EMAC_DMA_STAT_TPS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_DMA_STAT_TPS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_TU_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TU register field.

#define ALT_EMAC_DMA_STAT_TU_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TU register field.

#define ALT_EMAC_DMA_STAT_TU_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_TU register field.

#define ALT_EMAC_DMA_STAT_TU_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_DMA_STAT_TU register field value.

#define ALT_EMAC_DMA_STAT_TU_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_DMA_STAT_TU register field value.

#define ALT_EMAC_DMA_STAT_TU_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TU register field.

#define ALT_EMAC_DMA_STAT_TU_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_DMA_STAT_TU field value from a register.

#define ALT_EMAC_DMA_STAT_TU_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_DMA_STAT_TU register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_TJT_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TJT register field.

#define ALT_EMAC_DMA_STAT_TJT_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TJT register field.

#define ALT_EMAC_DMA_STAT_TJT_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_TJT register field.

#define ALT_EMAC_DMA_STAT_TJT_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_DMA_STAT_TJT register field value.

#define ALT_EMAC_DMA_STAT_TJT_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_DMA_STAT_TJT register field value.

#define ALT_EMAC_DMA_STAT_TJT_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TJT register field.

#define ALT_EMAC_DMA_STAT_TJT_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_DMA_STAT_TJT field value from a register.

#define ALT_EMAC_DMA_STAT_TJT_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_DMA_STAT_TJT register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_OVF_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_OVF register field.

#define ALT_EMAC_DMA_STAT_OVF_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_OVF register field.

#define ALT_EMAC_DMA_STAT_OVF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_OVF register field.

#define ALT_EMAC_DMA_STAT_OVF_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_DMA_STAT_OVF register field value.

#define ALT_EMAC_DMA_STAT_OVF_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_DMA_STAT_OVF register field value.

#define ALT_EMAC_DMA_STAT_OVF_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_OVF register field.

#define ALT_EMAC_DMA_STAT_OVF_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_DMA_STAT_OVF field value from a register.

#define ALT_EMAC_DMA_STAT_OVF_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_DMA_STAT_OVF register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_UNF_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_UNF register field.

#define ALT_EMAC_DMA_STAT_UNF_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_UNF register field.

#define ALT_EMAC_DMA_STAT_UNF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_UNF register field.

#define ALT_EMAC_DMA_STAT_UNF_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_DMA_STAT_UNF register field value.

#define ALT_EMAC_DMA_STAT_UNF_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_DMA_STAT_UNF register field value.

#define ALT_EMAC_DMA_STAT_UNF_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_UNF register field.

#define ALT_EMAC_DMA_STAT_UNF_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_DMA_STAT_UNF field value from a register.

#define ALT_EMAC_DMA_STAT_UNF_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_DMA_STAT_UNF register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_RI_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RI register field.

#define ALT_EMAC_DMA_STAT_RI_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RI register field.

#define ALT_EMAC_DMA_STAT_RI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_RI register field.

#define ALT_EMAC_DMA_STAT_RI_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_DMA_STAT_RI register field value.

#define ALT_EMAC_DMA_STAT_RI_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_DMA_STAT_RI register field value.

#define ALT_EMAC_DMA_STAT_RI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_RI register field.

#define ALT_EMAC_DMA_STAT_RI_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_DMA_STAT_RI field value from a register.

#define ALT_EMAC_DMA_STAT_RI_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_DMA_STAT_RI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_RU_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RU register field.

#define ALT_EMAC_DMA_STAT_RU_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RU register field.

#define ALT_EMAC_DMA_STAT_RU_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_RU register field.

#define ALT_EMAC_DMA_STAT_RU_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_DMA_STAT_RU register field value.

#define ALT_EMAC_DMA_STAT_RU_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_DMA_STAT_RU register field value.

#define ALT_EMAC_DMA_STAT_RU_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_RU register field.

#define ALT_EMAC_DMA_STAT_RU_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_DMA_STAT_RU field value from a register.

#define ALT_EMAC_DMA_STAT_RU_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_DMA_STAT_RU register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_RPS_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RPS register field.

#define ALT_EMAC_DMA_STAT_RPS_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RPS register field.

#define ALT_EMAC_DMA_STAT_RPS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_RPS register field.

#define ALT_EMAC_DMA_STAT_RPS_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_DMA_STAT_RPS register field value.

#define ALT_EMAC_DMA_STAT_RPS_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_DMA_STAT_RPS register field value.

#define ALT_EMAC_DMA_STAT_RPS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_RPS register field.

#define ALT_EMAC_DMA_STAT_RPS_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_DMA_STAT_RPS field value from a register.

#define ALT_EMAC_DMA_STAT_RPS_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_DMA_STAT_RPS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_RWT_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RWT register field.

#define ALT_EMAC_DMA_STAT_RWT_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RWT register field.

#define ALT_EMAC_DMA_STAT_RWT_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_RWT register field.

#define ALT_EMAC_DMA_STAT_RWT_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_DMA_STAT_RWT register field value.

#define ALT_EMAC_DMA_STAT_RWT_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_DMA_STAT_RWT register field value.

#define ALT_EMAC_DMA_STAT_RWT_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_RWT register field.

#define ALT_EMAC_DMA_STAT_RWT_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_DMA_STAT_RWT field value from a register.

#define ALT_EMAC_DMA_STAT_RWT_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_DMA_STAT_RWT register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_ETI_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ETI register field.

#define ALT_EMAC_DMA_STAT_ETI_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ETI register field.

#define ALT_EMAC_DMA_STAT_ETI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_ETI register field.

#define ALT_EMAC_DMA_STAT_ETI_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_DMA_STAT_ETI register field value.

#define ALT_EMAC_DMA_STAT_ETI_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_DMA_STAT_ETI register field value.

#define ALT_EMAC_DMA_STAT_ETI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_ETI register field.

#define ALT_EMAC_DMA_STAT_ETI_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_DMA_STAT_ETI field value from a register.

#define ALT_EMAC_DMA_STAT_ETI_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_DMA_STAT_ETI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_FBI_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_FBI register field.

#define ALT_EMAC_DMA_STAT_FBI_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_FBI register field.

#define ALT_EMAC_DMA_STAT_FBI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_FBI register field.

#define ALT_EMAC_DMA_STAT_FBI_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_DMA_STAT_FBI register field value.

#define ALT_EMAC_DMA_STAT_FBI_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_DMA_STAT_FBI register field value.

#define ALT_EMAC_DMA_STAT_FBI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_FBI register field.

#define ALT_EMAC_DMA_STAT_FBI_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_DMA_STAT_FBI field value from a register.

#define ALT_EMAC_DMA_STAT_FBI_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_DMA_STAT_FBI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_ERI_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_ERI register field.

#define ALT_EMAC_DMA_STAT_ERI_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_ERI register field.

#define ALT_EMAC_DMA_STAT_ERI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_ERI register field.

#define ALT_EMAC_DMA_STAT_ERI_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_DMA_STAT_ERI register field value.

#define ALT_EMAC_DMA_STAT_ERI_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_DMA_STAT_ERI register field value.

#define ALT_EMAC_DMA_STAT_ERI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_ERI register field.

#define ALT_EMAC_DMA_STAT_ERI_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_DMA_STAT_ERI field value from a register.

#define ALT_EMAC_DMA_STAT_ERI_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_DMA_STAT_ERI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_AIS_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_AIS register field.

#define ALT_EMAC_DMA_STAT_AIS_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_AIS register field.

#define ALT_EMAC_DMA_STAT_AIS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_AIS register field.

#define ALT_EMAC_DMA_STAT_AIS_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_DMA_STAT_AIS register field value.

#define ALT_EMAC_DMA_STAT_AIS_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_DMA_STAT_AIS register field value.

#define ALT_EMAC_DMA_STAT_AIS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_AIS register field.

#define ALT_EMAC_DMA_STAT_AIS_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_DMA_STAT_AIS field value from a register.

#define ALT_EMAC_DMA_STAT_AIS_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_DMA_STAT_AIS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_NIS_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_NIS register field.

#define ALT_EMAC_DMA_STAT_NIS_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_NIS register field.

#define ALT_EMAC_DMA_STAT_NIS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_NIS register field.

#define ALT_EMAC_DMA_STAT_NIS_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_DMA_STAT_NIS register field value.

#define ALT_EMAC_DMA_STAT_NIS_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_DMA_STAT_NIS register field value.

#define ALT_EMAC_DMA_STAT_NIS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_NIS register field.

#define ALT_EMAC_DMA_STAT_NIS_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_DMA_STAT_NIS field value from a register.

#define ALT_EMAC_DMA_STAT_NIS_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_DMA_STAT_NIS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_RS_E_STOPPED   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Stopped Reset or Stop Receive Command issued

#define ALT_EMAC_DMA_STAT_RS_E_RUNFETCH   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Running: Fetching Receive Transfer Descriptor

#define ALT_EMAC_DMA_STAT_RS_E_RESERVE   0x2

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Reserved for future use

#define ALT_EMAC_DMA_STAT_RS_E_RUNWAIT   0x3

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Running: Waiting for receive packet

#define ALT_EMAC_DMA_STAT_RS_E_SUSPEND   0x4

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Suspended: Receive Descriptor Unavailable

#define ALT_EMAC_DMA_STAT_RS_E_RUNCLOSE   0x5

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Running: Closing Receive Descriptor

#define ALT_EMAC_DMA_STAT_RS_E_TIMESTMP   0x6

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

TIME_STAMP write state

#define ALT_EMAC_DMA_STAT_RS_E_RUNTRANS   0x7

Enumerated value for register field ALT_EMAC_DMA_STAT_RS

Transferring rcv packet data from receive buffer to host memory

#define ALT_EMAC_DMA_STAT_RS_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_RS register field.

#define ALT_EMAC_DMA_STAT_RS_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_RS register field.

#define ALT_EMAC_DMA_STAT_RS_WIDTH   3

The width in bits of the ALT_EMAC_DMA_STAT_RS register field.

#define ALT_EMAC_DMA_STAT_RS_SET_MSK   0x000e0000

The mask used to set the ALT_EMAC_DMA_STAT_RS register field value.

#define ALT_EMAC_DMA_STAT_RS_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_EMAC_DMA_STAT_RS register field value.

#define ALT_EMAC_DMA_STAT_RS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_RS register field.

#define ALT_EMAC_DMA_STAT_RS_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_EMAC_DMA_STAT_RS field value from a register.

#define ALT_EMAC_DMA_STAT_RS_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_EMAC_DMA_STAT_RS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_TS_E_STOPPED   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Stopped Reset or Stop Transmit Command

#define ALT_EMAC_DMA_STAT_TS_E_RUNFETCH   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Running: Fetching Tranmit Transfer Descriptor

#define ALT_EMAC_DMA_STAT_TS_E_RUNWAIT   0x2

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Running; Waiting for status

#define ALT_EMAC_DMA_STAT_TS_E_RUNRD   0x3

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Running; Reading Data host memory buffer and queuing it to transmit buffer (Tx FIFO)

#define ALT_EMAC_DMA_STAT_TS_E_TIMESTMP   0x4

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

TIME_STAMP write state

#define ALT_EMAC_DMA_STAT_TS_E_RESERVE   0x5

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Reserved for future use

#define ALT_EMAC_DMA_STAT_TS_E_SUSPTX   0x6

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Suspended; Transmit Descriptor Unavailable or Transmit Buffer Underflow

#define ALT_EMAC_DMA_STAT_TS_E_RUNCLOSE   0x7

Enumerated value for register field ALT_EMAC_DMA_STAT_TS

Running; Closing Transmit Descriptor

#define ALT_EMAC_DMA_STAT_TS_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TS register field.

#define ALT_EMAC_DMA_STAT_TS_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TS register field.

#define ALT_EMAC_DMA_STAT_TS_WIDTH   3

The width in bits of the ALT_EMAC_DMA_STAT_TS register field.

#define ALT_EMAC_DMA_STAT_TS_SET_MSK   0x00700000

The mask used to set the ALT_EMAC_DMA_STAT_TS register field value.

#define ALT_EMAC_DMA_STAT_TS_CLR_MSK   0xff8fffff

The mask used to clear the ALT_EMAC_DMA_STAT_TS register field value.

#define ALT_EMAC_DMA_STAT_TS_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TS register field.

#define ALT_EMAC_DMA_STAT_TS_GET (   value)    (((value) & 0x00700000) >> 20)

Extracts the ALT_EMAC_DMA_STAT_TS field value from a register.

#define ALT_EMAC_DMA_STAT_TS_SET (   value)    (((value) << 20) & 0x00700000)

Produces a ALT_EMAC_DMA_STAT_TS register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_EB_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_EB register field.

#define ALT_EMAC_DMA_STAT_EB_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_EB register field.

#define ALT_EMAC_DMA_STAT_EB_WIDTH   3

The width in bits of the ALT_EMAC_DMA_STAT_EB register field.

#define ALT_EMAC_DMA_STAT_EB_SET_MSK   0x03800000

The mask used to set the ALT_EMAC_DMA_STAT_EB register field value.

#define ALT_EMAC_DMA_STAT_EB_CLR_MSK   0xfc7fffff

The mask used to clear the ALT_EMAC_DMA_STAT_EB register field value.

#define ALT_EMAC_DMA_STAT_EB_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_EB register field.

#define ALT_EMAC_DMA_STAT_EB_GET (   value)    (((value) & 0x03800000) >> 23)

Extracts the ALT_EMAC_DMA_STAT_EB field value from a register.

#define ALT_EMAC_DMA_STAT_EB_SET (   value)    (((value) << 23) & 0x03800000)

Produces a ALT_EMAC_DMA_STAT_EB register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_GLI_E_NOINTERRUP   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_GLI

No Interrupt

#define ALT_EMAC_DMA_STAT_GLI_E_INTERRUP   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_GLI

GMAC Line Interrupt

#define ALT_EMAC_DMA_STAT_GLI_LSB   26

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLI register field.

#define ALT_EMAC_DMA_STAT_GLI_MSB   26

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLI register field.

#define ALT_EMAC_DMA_STAT_GLI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_GLI register field.

#define ALT_EMAC_DMA_STAT_GLI_SET_MSK   0x04000000

The mask used to set the ALT_EMAC_DMA_STAT_GLI register field value.

#define ALT_EMAC_DMA_STAT_GLI_CLR_MSK   0xfbffffff

The mask used to clear the ALT_EMAC_DMA_STAT_GLI register field value.

#define ALT_EMAC_DMA_STAT_GLI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_GLI register field.

#define ALT_EMAC_DMA_STAT_GLI_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_EMAC_DMA_STAT_GLI field value from a register.

#define ALT_EMAC_DMA_STAT_GLI_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_EMAC_DMA_STAT_GLI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_GMI_E_NOINTERRUP   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_GMI

No Interrupt

#define ALT_EMAC_DMA_STAT_GMI_E_INTERRUP   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_GMI

GMAC MMC Interrupt

#define ALT_EMAC_DMA_STAT_GMI_LSB   27

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GMI register field.

#define ALT_EMAC_DMA_STAT_GMI_MSB   27

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GMI register field.

#define ALT_EMAC_DMA_STAT_GMI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_GMI register field.

#define ALT_EMAC_DMA_STAT_GMI_SET_MSK   0x08000000

The mask used to set the ALT_EMAC_DMA_STAT_GMI register field value.

#define ALT_EMAC_DMA_STAT_GMI_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_EMAC_DMA_STAT_GMI register field value.

#define ALT_EMAC_DMA_STAT_GMI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_GMI register field.

#define ALT_EMAC_DMA_STAT_GMI_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_EMAC_DMA_STAT_GMI field value from a register.

#define ALT_EMAC_DMA_STAT_GMI_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_EMAC_DMA_STAT_GMI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_TTI_E_NOINTERRUP   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_TTI

No Interrupt

#define ALT_EMAC_DMA_STAT_TTI_E_INTERRUP   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_TTI

Timestamp Trigger Interrupt

#define ALT_EMAC_DMA_STAT_TTI_LSB   29

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_TTI register field.

#define ALT_EMAC_DMA_STAT_TTI_MSB   29

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_TTI register field.

#define ALT_EMAC_DMA_STAT_TTI_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_TTI register field.

#define ALT_EMAC_DMA_STAT_TTI_SET_MSK   0x20000000

The mask used to set the ALT_EMAC_DMA_STAT_TTI register field value.

#define ALT_EMAC_DMA_STAT_TTI_CLR_MSK   0xdfffffff

The mask used to clear the ALT_EMAC_DMA_STAT_TTI register field value.

#define ALT_EMAC_DMA_STAT_TTI_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_TTI register field.

#define ALT_EMAC_DMA_STAT_TTI_GET (   value)    (((value) & 0x20000000) >> 29)

Extracts the ALT_EMAC_DMA_STAT_TTI field value from a register.

#define ALT_EMAC_DMA_STAT_TTI_SET (   value)    (((value) << 29) & 0x20000000)

Produces a ALT_EMAC_DMA_STAT_TTI register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_GLPII_E_NOINTERRUP   0x0

Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII

No Interrupt

#define ALT_EMAC_DMA_STAT_GLPII_E_INTERRUP   0x1

Enumerated value for register field ALT_EMAC_DMA_STAT_GLPII

GMAC LPI Interrupt

#define ALT_EMAC_DMA_STAT_GLPII_LSB   30

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_STAT_GLPII register field.

#define ALT_EMAC_DMA_STAT_GLPII_MSB   30

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_STAT_GLPII register field.

#define ALT_EMAC_DMA_STAT_GLPII_WIDTH   1

The width in bits of the ALT_EMAC_DMA_STAT_GLPII register field.

#define ALT_EMAC_DMA_STAT_GLPII_SET_MSK   0x40000000

The mask used to set the ALT_EMAC_DMA_STAT_GLPII register field value.

#define ALT_EMAC_DMA_STAT_GLPII_CLR_MSK   0xbfffffff

The mask used to clear the ALT_EMAC_DMA_STAT_GLPII register field value.

#define ALT_EMAC_DMA_STAT_GLPII_RESET   0x0

The reset value of the ALT_EMAC_DMA_STAT_GLPII register field.

#define ALT_EMAC_DMA_STAT_GLPII_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_EMAC_DMA_STAT_GLPII field value from a register.

#define ALT_EMAC_DMA_STAT_GLPII_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_EMAC_DMA_STAT_GLPII register field value suitable for setting the register.

#define ALT_EMAC_DMA_STAT_OFST   0x14

The byte offset of the ALT_EMAC_DMA_STAT register from the beginning of the component.

#define ALT_EMAC_DMA_STAT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_STAT_OFST))

The address of the ALT_EMAC_DMA_STAT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_STAT.