Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Status Register - stat

Description

Provides status fields for software for the FPGA Manager.

The Mode field tells software what configuration phase the FPGA currently is in. For regular configuration through the PINs or through the HPS, these states map directly to customer configuration documentation.

For Configuration Via PCI Express (CVP), the IOCSR configuration is done through the PINS or through HPS. Then the complete configuration is done through the PCI Express Bus. When CVP is being done, InitPhase indicates only IOCSR configuration has completed. CVP_CONF_DONE is available in the CB Monitor for observation by software.

The MSEL field provides a read only register for software to read the MSEL value driven from the external pins.

Register Layout

Bits Access Reset Description
[2:0] RW 0x5 Mode
[7:3] R 0x8 MSEL
[31:8] ??? 0x0 UNDEFINED

Field : Mode - mode

Reports FPGA state

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_STAT_MOD_E_FPGAOFF 0x0 FPGA Powered Off
ALT_FPGAMGR_STAT_MOD_E_RSTPHASE 0x1 FPGA in Reset Phase
ALT_FPGAMGR_STAT_MOD_E_CFGPHASE 0x2 FPGA in Configuration Phase
ALT_FPGAMGR_STAT_MOD_E_INITPHASE 0x3 FPGA in Initialization Phase. In CVP
: configuration, this state indicates IO
: configuration has completed.
ALT_FPGAMGR_STAT_MOD_E_USERMOD 0x4 FPGA in User Mode
ALT_FPGAMGR_STAT_MOD_E_UNKNOWN 0x5 FPGA state has not yet been determined. This
: only occurs briefly after reset.

Field Access Macros:

#define ALT_FPGAMGR_STAT_MOD_E_FPGAOFF   0x0
 
#define ALT_FPGAMGR_STAT_MOD_E_RSTPHASE   0x1
 
#define ALT_FPGAMGR_STAT_MOD_E_CFGPHASE   0x2
 
#define ALT_FPGAMGR_STAT_MOD_E_INITPHASE   0x3
 
#define ALT_FPGAMGR_STAT_MOD_E_USERMOD   0x4
 
#define ALT_FPGAMGR_STAT_MOD_E_UNKNOWN   0x5
 
#define ALT_FPGAMGR_STAT_MOD_LSB   0
 
#define ALT_FPGAMGR_STAT_MOD_MSB   2
 
#define ALT_FPGAMGR_STAT_MOD_WIDTH   3
 
#define ALT_FPGAMGR_STAT_MOD_SET_MSK   0x00000007
 
#define ALT_FPGAMGR_STAT_MOD_CLR_MSK   0xfffffff8
 
#define ALT_FPGAMGR_STAT_MOD_RESET   0x5
 
#define ALT_FPGAMGR_STAT_MOD_GET(value)   (((value) & 0x00000007) >> 0)
 
#define ALT_FPGAMGR_STAT_MOD_SET(value)   (((value) << 0) & 0x00000007)
 

Field : MSEL - msel

This read-only field allows software to observe the MSEL inputs from the device pins. The MSEL pins define the FPGA configuration mode.

Field Enumeration Values:

Enum Value Description
ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC 0x0 16-bit Passive Parallel with Fast Power on Reset
: Delay; No AES Encryption; No Data Compression.
: CDRATIO must be programmed to x1
ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC 0x1 16-bit Passive Parallel with Fast Power on Reset
: Delay; With AES Encryption; No Data Compression.
: CDRATIO must be programmed to x4
ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC 0x2 16-bit Passive Parallel with Fast Power on Reset
: Delay; AES Optional; With Data Compression.
: CDRATIO must be programmed to x8
ALT_FPGAMGR_STAT_MSEL_E_RSVD3 0x3 Reserved
ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC 0x4 16-bit Passive Parallel with Slow Power on Reset
: Delay; No AES Encryption; No Data Compression.
: CDRATIO must be programmed to x1
ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC 0x5 16-bit Passive Parallel with Slow Power on Reset
: Delay; With AES Encryption; No Data Compression.
: CDRATIO must be programmed to x4
ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC 0x6 16-bit Passive Parallel with Slow Power on Reset
: Delay; AES Optional; With Data Compression.
: CDRATIO must be programmed to x8
ALT_FPGAMGR_STAT_MSEL_E_RSVD7 0x7 Reserved
ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC 0x8 32-bit Passive Parallel with Fast Power on Reset
: Delay; No AES Encryption; No Data Compression.
: CDRATIO must be programmed to x1
ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC 0x9 32-bit Passive Parallel with Fast Power on Reset
: Delay; With AES Encryption; No Data Compression.
: CDRATIO must be programmed to x4
ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC 0xa 32-bit Passive Parallel with Fast Power on Reset
: Delay; AES Optional; With Data Compression.
: CDRATIO must be programmed to x8
ALT_FPGAMGR_STAT_MSEL_E_RSVD11 0xb Reserved
ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC 0xc 32-bit Passive Parallel with Slow Power on Reset
: Delay; No AES Encryption; No Data Compression.
: CDRATIO must be programmed to x1
ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC 0xd 32-bit Passive Parallel with Slow Power on Reset
: Delay; With AES Encryption; No Data Compression.
: CDRATIO must be programmed to x4
ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC 0xe 32-bit Passive Parallel with Slow Power on Reset
: Delay; AES Optional; With Data Compression.
: CDRATIO must be programmed to x8
ALT_FPGAMGR_STAT_MSEL_E_RSVD15 0xf Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD16 0x10 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD17 0x11 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD18 0x12 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD19 0x13 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD20 0x14 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD21 0x15 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD22 0x16 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD23 0x17 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD24 0x18 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD25 0x19 Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD26 0x1a Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD27 0x1b Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD28 0x1c Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD29 0x1d Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD30 0x1e Reserved
ALT_FPGAMGR_STAT_MSEL_E_RSVD31 0x1f Reserved

Field Access Macros:

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC   0x0
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC   0x1
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC   0x2
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD3   0x3
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC   0x4
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC   0x5
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC   0x6
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD7   0x7
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC   0x8
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC   0x9
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC   0xa
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD11   0xb
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC   0xc
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC   0xd
 
#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC   0xe
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD15   0xf
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD16   0x10
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD17   0x11
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD18   0x12
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD19   0x13
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD20   0x14
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD21   0x15
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD22   0x16
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD23   0x17
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD24   0x18
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD25   0x19
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD26   0x1a
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD27   0x1b
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD28   0x1c
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD29   0x1d
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD30   0x1e
 
#define ALT_FPGAMGR_STAT_MSEL_E_RSVD31   0x1f
 
#define ALT_FPGAMGR_STAT_MSEL_LSB   3
 
#define ALT_FPGAMGR_STAT_MSEL_MSB   7
 
#define ALT_FPGAMGR_STAT_MSEL_WIDTH   5
 
#define ALT_FPGAMGR_STAT_MSEL_SET_MSK   0x000000f8
 
#define ALT_FPGAMGR_STAT_MSEL_CLR_MSK   0xffffff07
 
#define ALT_FPGAMGR_STAT_MSEL_RESET   0x8
 
#define ALT_FPGAMGR_STAT_MSEL_GET(value)   (((value) & 0x000000f8) >> 3)
 
#define ALT_FPGAMGR_STAT_MSEL_SET(value)   (((value) << 3) & 0x000000f8)
 

Data Structures

struct  ALT_FPGAMGR_STAT_s
 

Macros

#define ALT_FPGAMGR_STAT_OFST   0x0
 

Typedefs

typedef struct ALT_FPGAMGR_STAT_s ALT_FPGAMGR_STAT_t
 

Data Structure Documentation

struct ALT_FPGAMGR_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_FPGAMGR_STAT.

Data Fields
uint32_t mode: 3 Mode
const uint32_t msel: 5 MSEL
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_FPGAMGR_STAT_MOD_E_FPGAOFF   0x0

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA Powered Off

#define ALT_FPGAMGR_STAT_MOD_E_RSTPHASE   0x1

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA in Reset Phase

#define ALT_FPGAMGR_STAT_MOD_E_CFGPHASE   0x2

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA in Configuration Phase

#define ALT_FPGAMGR_STAT_MOD_E_INITPHASE   0x3

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA in Initialization Phase. In CVP configuration, this state indicates IO configuration has completed.

#define ALT_FPGAMGR_STAT_MOD_E_USERMOD   0x4

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA in User Mode

#define ALT_FPGAMGR_STAT_MOD_E_UNKNOWN   0x5

Enumerated value for register field ALT_FPGAMGR_STAT_MOD

FPGA state has not yet been determined. This only occurs briefly after reset.

#define ALT_FPGAMGR_STAT_MOD_LSB   0

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MOD register field.

#define ALT_FPGAMGR_STAT_MOD_MSB   2

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MOD register field.

#define ALT_FPGAMGR_STAT_MOD_WIDTH   3

The width in bits of the ALT_FPGAMGR_STAT_MOD register field.

#define ALT_FPGAMGR_STAT_MOD_SET_MSK   0x00000007

The mask used to set the ALT_FPGAMGR_STAT_MOD register field value.

#define ALT_FPGAMGR_STAT_MOD_CLR_MSK   0xfffffff8

The mask used to clear the ALT_FPGAMGR_STAT_MOD register field value.

#define ALT_FPGAMGR_STAT_MOD_RESET   0x5

The reset value of the ALT_FPGAMGR_STAT_MOD register field.

#define ALT_FPGAMGR_STAT_MOD_GET (   value)    (((value) & 0x00000007) >> 0)

Extracts the ALT_FPGAMGR_STAT_MOD field value from a register.

#define ALT_FPGAMGR_STAT_MOD_SET (   value)    (((value) << 0) & 0x00000007)

Produces a ALT_FPGAMGR_STAT_MOD register field value suitable for setting the register.

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_NOAES_NODC   0x0

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression.

CDRATIO must be programmed to x1

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AES_NODC   0x1

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression.

CDRATIO must be programmed to x4

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_FAST_AESOPT_DC   0x2

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression.

CDRATIO must be programmed to x8

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD3   0x3

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_NOAES_NODC   0x4

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression.

CDRATIO must be programmed to x1

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AES_NODC   0x5

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression.

CDRATIO must be programmed to x4

#define ALT_FPGAMGR_STAT_MSEL_E_PP16_SLOW_AESOPT_DC   0x6

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression.

CDRATIO must be programmed to x8

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD7   0x7

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_NOAES_NODC   0x8

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression.

CDRATIO must be programmed to x1

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AES_NODC   0x9

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression.

CDRATIO must be programmed to x4

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_FAST_AESOPT_DC   0xa

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression.

CDRATIO must be programmed to x8

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD11   0xb

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_NOAES_NODC   0xc

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression.

CDRATIO must be programmed to x1

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AES_NODC   0xd

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression.

CDRATIO must be programmed to x4

#define ALT_FPGAMGR_STAT_MSEL_E_PP32_SLOW_AESOPT_DC   0xe

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression.

CDRATIO must be programmed to x8

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD15   0xf

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD16   0x10

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD17   0x11

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD18   0x12

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD19   0x13

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD20   0x14

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD21   0x15

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD22   0x16

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD23   0x17

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD24   0x18

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD25   0x19

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD26   0x1a

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD27   0x1b

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD28   0x1c

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD29   0x1d

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD30   0x1e

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_E_RSVD31   0x1f

Enumerated value for register field ALT_FPGAMGR_STAT_MSEL

Reserved

#define ALT_FPGAMGR_STAT_MSEL_LSB   3

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_STAT_MSEL register field.

#define ALT_FPGAMGR_STAT_MSEL_MSB   7

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_STAT_MSEL register field.

#define ALT_FPGAMGR_STAT_MSEL_WIDTH   5

The width in bits of the ALT_FPGAMGR_STAT_MSEL register field.

#define ALT_FPGAMGR_STAT_MSEL_SET_MSK   0x000000f8

The mask used to set the ALT_FPGAMGR_STAT_MSEL register field value.

#define ALT_FPGAMGR_STAT_MSEL_CLR_MSK   0xffffff07

The mask used to clear the ALT_FPGAMGR_STAT_MSEL register field value.

#define ALT_FPGAMGR_STAT_MSEL_RESET   0x8

The reset value of the ALT_FPGAMGR_STAT_MSEL register field.

#define ALT_FPGAMGR_STAT_MSEL_GET (   value)    (((value) & 0x000000f8) >> 3)

Extracts the ALT_FPGAMGR_STAT_MSEL field value from a register.

#define ALT_FPGAMGR_STAT_MSEL_SET (   value)    (((value) << 3) & 0x000000f8)

Produces a ALT_FPGAMGR_STAT_MSEL register field value suitable for setting the register.

#define ALT_FPGAMGR_STAT_OFST   0x0

The byte offset of the ALT_FPGAMGR_STAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_FPGAMGR_STAT.