![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
The COUNTS register is used by software to control reset behavior.It includes fields for software to control the behavior of the warm reset and nRST pin.
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x80 | Warm reset release delay count |
[27:8] | RW | 0x800 | nRST Pin Count |
[31:28] | ??? | 0x0 | UNDEFINED |
Field : Warm reset release delay count - warmrstcycles | |
On a warm reset, the Reset Manager releases the reset to the Clock Manager, and then waits for the number of cycles specified in this register before releasing the rest of the hardware controlled resets. Value must be greater than 16. Field Access Macros: | |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value) (((value) << 0) & 0x000000ff) |
Field : nRST Pin Count - nrstcnt | |
The Reset Manager pulls down the nRST pin on a warm reset for the number of cycles specified in this register. A value of 0x0 prevents the Reset Manager from pulling down the nRST pin. Field Access Macros: | |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_GET(value) (((value) & 0x0fffff00) >> 8) |
#define | ALT_RSTMGR_COUNTS_NRSTCNT_SET(value) (((value) << 8) & 0x0fffff00) |
Data Structures | |
struct | ALT_RSTMGR_COUNTS_s |
Macros | |
#define | ALT_RSTMGR_COUNTS_OFST 0x8 |
Typedefs | |
typedef struct ALT_RSTMGR_COUNTS_s | ALT_RSTMGR_COUNTS_t |
struct ALT_RSTMGR_COUNTS_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_RSTMGR_COUNTS.
Data Fields | ||
---|---|---|
uint32_t | warmrstcycles: 8 | Warm reset release delay count |
uint32_t | nrstcnt: 20 | nRST Pin Count |
uint32_t | __pad0__: 4 | UNDEFINED |
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH 8 |
The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK 0x000000ff |
The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET 0x80 |
The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register.
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register.
#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field.
#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field.
#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH 20 |
The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field.
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK 0x0fffff00 |
The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value.
#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK 0xf00000ff |
The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value.
#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET 0x800 |
The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field.
#define ALT_RSTMGR_COUNTS_NRSTCNT_GET | ( | value | ) | (((value) & 0x0fffff00) >> 8) |
Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register.
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET | ( | value | ) | (((value) << 8) & 0x0fffff00) |
Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register.
#define ALT_RSTMGR_COUNTS_OFST 0x8 |
The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component.
typedef struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t |
The typedef declaration for register ALT_RSTMGR_COUNTS.