Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : DERRADDRA

Description

Double-bit error address

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 ALT_ECC_HMC_OCP_DERRADDRA_DADDR

Field : DADDRESS

Recent DBE address.

This register shows the address of the current double-bit error. RAM size will determine the maximum number of address bits.

This address is logged when a new derr_req or bus error is generated to the system. This is gated by the ecc_en enable bit and derrinten bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_LSB   0
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_MSB   31
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_WIDTH   32
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET_MSK   0xffffffff
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_CLR_MSK   0x00000000
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_RESET   0x0
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_ECC_HMC_OCP_DERRADDRA_s
 

Macros

#define ALT_ECC_HMC_OCP_DERRADDRA_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_DERRADDRA_OFST   0x12c
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_DERRADDRA_s 
ALT_ECC_HMC_OCP_DERRADDRA_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_DERRADDRA_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_DERRADDRA.

Data Fields
uint32_t DADDRESS: 32 ALT_ECC_HMC_OCP_DERRADDRA_DADDR

Macro Definitions

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_MSB   31

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_WIDTH   32

The width in bits of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET_MSK   0xffffffff

The mask used to set the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_CLR_MSK   0x00000000

The mask used to clear the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_ECC_HMC_OCP_DERRADDRA_DADDR field value from a register.

#define ALT_ECC_HMC_OCP_DERRADDRA_DADDR_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_ECC_HMC_OCP_DERRADDRA_DADDR register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_DERRADDRA_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_DERRADDRA register.

#define ALT_ECC_HMC_OCP_DERRADDRA_OFST   0x12c

The byte offset of the ALT_ECC_HMC_OCP_DERRADDRA register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_ECC_HMC_OCP_DERRADDRA.