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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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ECC from register associated to RD data which will be written to hmc ecc
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS |
[15:8] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS |
[23:16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS |
[31:24] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS |
Field : ECC0BUS | |
ECC from register associated to RD data [63:0] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET(value) (((value) << 0) & 0x000000ff) |
Field : ECC1BUS | |
ECC from register associated to RD data [127:64] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_GET(value) (((value) & 0x0000ff00) >> 8) |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET(value) (((value) << 8) & 0x0000ff00) |
Field : ECC2BUS | |
ECC from register associated to RD data [191:128] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_GET(value) (((value) & 0x00ff0000) >> 16) |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET(value) (((value) << 16) & 0x00ff0000) |
Field : ECC3BUS | |
ECC from register associated to RD data [255:192] which will be written to hmc ecc. Based on the DDR IO width, unimplemented bytes of this register will read as zero. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_GET(value) (((value) & 0xff000000) >> 24) |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET(value) (((value) << 24) & 0xff000000) |
Data Structures | |
struct | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s |
Macros | |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_RESET 0x00000000 |
#define | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_OFST 0x14c |
Typedefs | |
typedef struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_t |
struct ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS.
Data Fields | ||
---|---|---|
uint32_t | ECC0BUS: 8 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS |
uint32_t | ECC1BUS: 8 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS |
uint32_t | ECC2BUS: 8 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS |
uint32_t | ECC3BUS: 8 | ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS |
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_WIDTH 8 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET_MSK 0x000000ff |
The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS field value from a register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC0BUS register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_WIDTH 8 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET_MSK 0x0000ff00 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_CLR_MSK 0xffff00ff |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_GET | ( | value | ) | (((value) & 0x0000ff00) >> 8) |
Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS field value from a register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS_SET | ( | value | ) | (((value) << 8) & 0x0000ff00) |
Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC1BUS register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_WIDTH 8 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET_MSK 0x00ff0000 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_CLR_MSK 0xff00ffff |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_GET | ( | value | ) | (((value) & 0x00ff0000) >> 16) |
Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS field value from a register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS_SET | ( | value | ) | (((value) << 16) & 0x00ff0000) |
Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC2BUS register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_WIDTH 8 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET_MSK 0xff000000 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_CLR_MSK 0x00ffffff |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_GET | ( | value | ) | (((value) & 0xff000000) >> 24) |
Extracts the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS field value from a register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS_SET | ( | value | ) | (((value) << 24) & 0xff000000) |
Produces a ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_ECC3BUS register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_RESET 0x00000000 |
The reset value of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS register.
#define ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS_OFST 0x14c |
The byte offset of the ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS register from the beginning of the component.
The typedef declaration for register ALT_ECC_HMC_OCP_ECC_REG2RDECCDATABUS.