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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The Bridge_WARM_MASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).
All fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | HPS2FPGA Bridge |
[1] | RW | 0x1 | LWHPS2FPGA Bridge |
[2] | RW | 0x1 | FPGA2HPS Bridge |
[3] | RW | 0x1 | F2S SDRAM0 Bridge |
[4] | RW | 0x1 | F2S SDRAM1 Bridge |
[5] | RW | 0x1 | F2S SDRAM2 Bridge |
[6] | RW | 0x1 | DDR Scheduler |
[31:7] | ??? | 0x0 | UNDEFINED |
Field : HPS2FPGA Bridge - hps2fpga | |
Masks hardware sequenced warm reset for HPS2FPGA Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_LSB 0 |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_MSB 0 |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_SET_MSK 0x00000001 |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_CLR_MSK 0xfffffffe |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_RSTMGR_BRGWARMMSK_H2F_SET(value) (((value) << 0) & 0x00000001) |
Field : LWHPS2FPGA Bridge - lwhps2fpga | |
Masks hardware sequenced warm reset for LWHPS2FPGA Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_LSB 1 |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_MSB 1 |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_SET_MSK 0x00000002 |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_CLR_MSK 0xfffffffd |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_RSTMGR_BRGWARMMSK_LWH2F_SET(value) (((value) << 1) & 0x00000002) |
Field : FPGA2HPS Bridge - fpga2hps | |
Masks hardware sequenced warm reset for FPGA2HPS Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_LSB 2 |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_MSB 2 |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_SET_MSK 0x00000004 |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_CLR_MSK 0xfffffffb |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_RSTMGR_BRGWARMMSK_F2H_SET(value) (((value) << 2) & 0x00000004) |
Field : F2S SDRAM0 Bridge - f2ssdram0 | |
Masks hardware sequenced warm reset for F2S_SDRAM0 Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_LSB 3 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_MSB 3 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET_MSK 0x00000008 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_CLR_MSK 0xfffffff7 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET(value) (((value) << 3) & 0x00000008) |
Field : F2S SDRAM1 Bridge - f2ssdram1 | |
Masks hardware sequenced warm reset for F2S_SDRAM1 Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_LSB 4 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_MSB 4 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET_MSK 0x00000010 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_CLR_MSK 0xffffffef |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET(value) (((value) << 4) & 0x00000010) |
Field : F2S SDRAM2 Bridge - f2ssdram2 | |
Masks hardware sequenced warm reset for F2S_SDRAM2 Bridge Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_LSB 5 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_MSB 5 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET_MSK 0x00000020 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_CLR_MSK 0xffffffdf |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET(value) (((value) << 5) & 0x00000020) |
Field : DDR Scheduler - ddrsch | |
Masks hardware sequenced warm reset for the DDR Scheduler in the NOC. Field Access Macros: | |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_LSB 6 |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_MSB 6 |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_WIDTH 1 |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET_MSK 0x00000040 |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_CLR_MSK 0xffffffbf |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_RESET 0x1 |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET(value) (((value) << 6) & 0x00000040) |
Data Structures | |
struct | ALT_RSTMGR_BRGWARMMSK_s |
Macros | |
#define | ALT_RSTMGR_BRGWARMMSK_RESET 0x0000007f |
#define | ALT_RSTMGR_BRGWARMMSK_OFST 0x4c |
Typedefs | |
typedef struct ALT_RSTMGR_BRGWARMMSK_s | ALT_RSTMGR_BRGWARMMSK_t |
struct ALT_RSTMGR_BRGWARMMSK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_RSTMGR_BRGWARMMSK.
Data Fields | ||
---|---|---|
uint32_t | hps2fpga: 1 | HPS2FPGA Bridge |
uint32_t | lwhps2fpga: 1 | LWHPS2FPGA Bridge |
uint32_t | fpga2hps: 1 | FPGA2HPS Bridge |
uint32_t | f2ssdram0: 1 | F2S SDRAM0 Bridge |
uint32_t | f2ssdram1: 1 | F2S SDRAM1 Bridge |
uint32_t | f2ssdram2: 1 | F2S SDRAM2 Bridge |
uint32_t | ddrsch: 1 | DDR Scheduler |
uint32_t | __pad0__: 25 | UNDEFINED |
#define ALT_RSTMGR_BRGWARMMSK_H2F_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_H2F register field.
#define ALT_RSTMGR_BRGWARMMSK_H2F_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_H2F register field.
#define ALT_RSTMGR_BRGWARMMSK_H2F_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_H2F register field.
#define ALT_RSTMGR_BRGWARMMSK_H2F_SET_MSK 0x00000001 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_H2F register field value.
#define ALT_RSTMGR_BRGWARMMSK_H2F_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_H2F register field value.
#define ALT_RSTMGR_BRGWARMMSK_H2F_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_H2F register field.
#define ALT_RSTMGR_BRGWARMMSK_H2F_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_RSTMGR_BRGWARMMSK_H2F field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_H2F_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_RSTMGR_BRGWARMMSK_H2F register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET_MSK 0x00000002 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_LWH2F register field value.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_LWH2F register field value.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_LWH2F register field.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_RSTMGR_BRGWARMMSK_LWH2F field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_LWH2F_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_RSTMGR_BRGWARMMSK_LWH2F register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_F2H_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2H register field.
#define ALT_RSTMGR_BRGWARMMSK_F2H_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2H register field.
#define ALT_RSTMGR_BRGWARMMSK_F2H_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2H register field.
#define ALT_RSTMGR_BRGWARMMSK_F2H_SET_MSK 0x00000004 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2H register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2H_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2H register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2H_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_F2H register field.
#define ALT_RSTMGR_BRGWARMMSK_F2H_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_RSTMGR_BRGWARMMSK_F2H field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_F2H_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_RSTMGR_BRGWARMMSK_F2H register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET_MSK 0x00000008 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM0 register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET_MSK 0x00000010 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_CLR_MSK 0xffffffef |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM1 register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET_MSK 0x00000020 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_RSTMGR_BRGWARMMSK_F2SSDRAM2 register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_WIDTH 1 |
The width in bits of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET_MSK 0x00000040 |
The mask used to set the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_RESET 0x1 |
The reset value of the ALT_RSTMGR_BRGWARMMSK_DDRSCH register field.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_RSTMGR_BRGWARMMSK_DDRSCH field value from a register.
#define ALT_RSTMGR_BRGWARMMSK_DDRSCH_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_RSTMGR_BRGWARMMSK_DDRSCH register field value suitable for setting the register.
#define ALT_RSTMGR_BRGWARMMSK_RESET 0x0000007f |
The reset value of the ALT_RSTMGR_BRGWARMMSK register.
#define ALT_RSTMGR_BRGWARMMSK_OFST 0x4c |
The byte offset of the ALT_RSTMGR_BRGWARMMSK register from the beginning of the component.
typedef struct ALT_RSTMGR_BRGWARMMSK_s ALT_RSTMGR_BRGWARMMSK_t |
The typedef declaration for register ALT_RSTMGR_BRGWARMMSK.