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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock enables for clocks derived from the Main PLL.
1: The clock is enabled.
0: The clock is disabled.
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | l4_main_clk Enable |
[1] | RW | 0x1 | l3_mp_clk Enable |
[2] | RW | 0x1 | l4_mp_clk Enable |
[3] | RW | 0x1 | l4_sp_clk Enable |
[4] | RW | 0x1 | dbg_at_clk Enable |
[5] | RW | 0x1 | dbg_clk Enable |
[6] | RW | 0x1 | dbg_trace_clk Enable |
[7] | RW | 0x1 | dbg_timer_clk Enable |
[8] | RW | 0x1 | cfg_clk Enable |
[9] | RW | 0x1 | s2f_user0_clk Enable |
[31:10] | ??? | 0x0 | UNDEFINED |
Field : l4_main_clk Enable - l4mainclk | |
Enables clock l4_main_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001) |
Field : l3_mp_clk Enable - l3mpclk | |
Enables clock l3_mp_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002) |
Field : l4_mp_clk Enable - l4mpclk | |
Enables clock l4_mp_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004) |
Field : l4_sp_clk Enable - l4spclk | |
Enables clock l4_sp_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008) |
Field : dbg_at_clk Enable - dbgatclk | |
Enables clock dbg_at_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010) |
Field : dbg_clk Enable - dbgclk | |
Enables clock dbg_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020) |
Field : dbg_trace_clk Enable - dbgtraceclk | |
Enables clock dbg_trace_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040) |
Field : dbg_timer_clk Enable - dbgtimerclk | |
Enables clock dbg_timer_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080) |
Field : cfg_clk Enable - cfgclk | |
Enables clock cfg_clk output Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100) |
Field : s2f_user0_clk Enable - s2fuser0clk | |
Enables clock s2f_user0_clk output. Qsys and user documenation refer to s2f_user0_clk as h2f_user0_clk. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200) |
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_EN_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_EN_OFST 0x20 |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_EN_s | ALT_CLKMGR_MAINPLL_EN_t |
struct ALT_CLKMGR_MAINPLL_EN_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_EN.
Data Fields | ||
---|---|---|
uint32_t | l4mainclk: 1 | l4_main_clk Enable |
uint32_t | l3mpclk: 1 | l3_mp_clk Enable |
uint32_t | l4mpclk: 1 | l4_mp_clk Enable |
uint32_t | l4spclk: 1 | l4_sp_clk Enable |
uint32_t | dbgatclk: 1 | dbg_at_clk Enable |
uint32_t | dbgclk: 1 | dbg_clk Enable |
uint32_t | dbgtraceclk: 1 | dbg_trace_clk Enable |
uint32_t | dbgtimerclk: 1 | dbg_timer_clk Enable |
uint32_t | cfgclk: 1 | cfg_clk Enable |
uint32_t | s2fuser0clk: 1 | s2f_user0_clk Enable |
uint32_t | __pad0__: 22 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_EN_L4MAINCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_MAINPLL_EN_L4MAINCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_MAINPLL_EN_L3MPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_MAINPLL_EN_L3MPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_MAINPLL_EN_L4MPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_MAINPLL_EN_L4MPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_CLKMGR_MAINPLL_EN_L4SPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_CLKMGR_MAINPLL_EN_L4SPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_CLKMGR_MAINPLL_EN_DBGATCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_CLKMGR_MAINPLL_EN_DBGATCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_CLKMGR_MAINPLL_EN_DBGCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_CLKMGR_MAINPLL_EN_DBGCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_CFGCLK register field.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_CLKMGR_MAINPLL_EN_CFGCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_CLKMGR_MAINPLL_EN_CFGCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200 |
The mask used to set the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK field value from a register.
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20 |
The byte offset of the ALT_CLKMGR_MAINPLL_EN register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_EN_s ALT_CLKMGR_MAINPLL_EN_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_EN.