Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ddr_scheduler_register

Description

Per-Master Security bit for ddr_scheduler_register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0
[15:1] ??? Unknown UNDEFINED
[16] RW 0x0 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H
[23:17] ??? Unknown UNDEFINED
[24] RW 0x0 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP
[31:25] ??? Unknown UNDEFINED

Field : mpu_m0

Security bit configuration for transactions from mpu_m0 to ddr_scheduler_register. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

Field Access Macros:

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_LSB   0
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_MSB   0
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_WIDTH   1
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET_MSK   0x00000001
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_CLR_MSK   0xfffffffe
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_RESET   0x0
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : fpga2soc

Security bit configuration for transactions from fpga2soc to ddr_scheduler_register. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

Field Access Macros:

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_LSB   16
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_MSB   16
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_WIDTH   1
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET_MSK   0x00010000
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_CLR_MSK   0xfffeffff
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_RESET   0x0
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET(value)   (((value) << 16) & 0x00010000)
 

Field : ahb_ap

Security bit configuration for transactions from ahb_ap to ddr_schedule_register. When cleared (0), only Secure transactions are allowed. When set (1), both Secure and Non-Secure transactions are allowed.

Field Access Macros:

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_LSB   24
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_MSB   24
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_WIDTH   1
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET_MSK   0x01000000
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_CLR_MSK   0xfeffffff
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_RESET   0x0
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET(value)   (((value) << 24) & 0x01000000)
 

Data Structures

struct  ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s
 

Macros

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_RESET   0x00000000
 
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_OFST   0x88
 

Typedefs

typedef struct
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s 
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t
 

Data Structure Documentation

struct ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG.

Data Fields
uint32_t mpu_m0: 1 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0
uint32_t __pad0__: 15 UNDEFINED
uint32_t fpga2soc: 1 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H
uint32_t __pad1__: 7 UNDEFINED
uint32_t ahb_ap: 1 ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP
uint32_t __pad2__: 7 UNDEFINED

Macro Definitions

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_MSB   0

The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_WIDTH   1

The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET_MSK   0x00000001

The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_RESET   0x0

The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 field value from a register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0 register field value suitable for setting the register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_LSB   16

The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_MSB   16

The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_WIDTH   1

The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET_MSK   0x00010000

The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_CLR_MSK   0xfffeffff

The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_RESET   0x0

The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H field value from a register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H register field value suitable for setting the register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_LSB   24

The Least Significant Bit (LSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_MSB   24

The Most Significant Bit (MSB) position of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_WIDTH   1

The width in bits of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET_MSK   0x01000000

The mask used to set the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_CLR_MSK   0xfeffffff

The mask used to clear the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_RESET   0x0

The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP field value from a register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP register field value suitable for setting the register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_RESET   0x00000000

The reset value of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG register.

#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_OFST   0x88

The byte offset of the ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG register from the beginning of the component.

Typedef Documentation