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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 0 (Bus Mode Register)
The Bus Mode register establishes the bus operating modes for the DMA.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_SWR |
[1] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_DA |
[6:2] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_DSL |
[7] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_ATDS |
[13:8] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_PBL |
[15:14] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_PR |
[16] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_FB |
[22:17] | RW | 0x1 | ALT_EMAC_DMA_BUS_MOD_RPBL |
[23] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_USP |
[24] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL |
[25] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_AAL |
[26] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_MB |
[27] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_TXPR |
[29:28] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_PRWG |
[30] | R | 0x0 | ALT_EMAC_DMA_BUS_MOD_RSVD_30 |
[31] | RW | 0x0 | ALT_EMAC_DMA_BUS_MOD_RIB |
Field : swr | |
Software Reset When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation has completed in all of the DWC_gmac clock domains. Before reprogramming any register of the DWC_gmac, you should read a zero (0) value in this bit . Note:
Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST | 0x0 | ALT_EMAC_DMA_BUS_MOD_SWR_E_RST | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_LSB 0 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_MSB 0 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK 0x00000001 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_RESET 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_DMA_BUS_MOD_SWR_SET(value) (((value) << 0) & 0x00000001) |
Field : da | |
DMA Arbitration Scheme This bit specifies the arbitration scheme between the transmit and receive paths of Channel 0.
The priority between the paths is according to the priority specified in bits 15:14 (PR) and priority weights specified in Bit 27 (TXPR).
The transmit path has priority over receive path when Bit 27 (TXPR) is set. Otherwise, receive path has priority over the transmit path. In the GMAC-AXI configuration, these bits are reserved and read-only (RO). Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_DA_LSB 1 |
#define | ALT_EMAC_DMA_BUS_MOD_DA_MSB 1 |
#define | ALT_EMAC_DMA_BUS_MOD_DA_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_DA_SET_MSK 0x00000002 |
#define | ALT_EMAC_DMA_BUS_MOD_DA_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_DMA_BUS_MOD_DA_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_DA_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_DMA_BUS_MOD_DA_SET(value) (((value) << 1) & 0x00000002) |
Field : dsl | |
Descriptor Skip Length This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, the descriptor table is taken as contiguous by the DMA in Ring mode. Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_LSB 2 |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_MSB 6 |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH 5 |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK 0x0000007c |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK 0xffffff83 |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_GET(value) (((value) & 0x0000007c) >> 2) |
#define | ALT_EMAC_DMA_BUS_MOD_DSL_SET(value) (((value) << 2) & 0x0000007c) |
Field : atds | |
Alternate Descriptor Size When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2) features are not enabled. In such cases, you can use the 16 bytes descriptor to save 4 bytes of memory. This bit is present only when you select the Alternate Descriptor feature and any one of the following features during core configuration:
Otherwise, this bit is reserved and read-only. When reset, the descriptor size reverts back to 4 DWORDs (16 bytes). This bit preserves the backward compatibility for the descriptor size. In versions prior to 3.50a, the descriptor size is 16 bytes for both normal and enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST | 0x0 | ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_LSB 7 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_MSB 7 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK 0x00000080 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK 0xffffff7f |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value) (((value) << 7) & 0x00000080) |
Field : pbl | |
Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions. If the number of beats to be transferred is more than 32, then perform the following steps:
For example, if the maximum number of beats to be transferred is 64, then first set PBLx8 to 1 and then set PBL to 8. The PBL values have the following limitation: The maximum number of possible beats (PBL) is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified. For different data bus widths and FIFO sizes, the valid PBL range (including x8 mode) is provided in the following list. If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx FIFO depths must be considered. Note: In the half-duplex mode, the valid PBL range specified in the following list is applicable only for Tx FIFO.
Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_LSB 8 |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_MSB 13 |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH 6 |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK 0x00003f00 |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK 0xffffc0ff |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_RESET 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_GET(value) (((value) & 0x00003f00) >> 8) |
#define | ALT_EMAC_DMA_BUS_MOD_PBL_SET(value) (((value) << 8) & 0x00003f00) |
Field : pr | |
Priority Ratio These bits control the priority ratio in the weighted round-robin arbitration between the Rx DMA and Tx DMA. These bits are valid only when Bit 1 (DA) is reset. The priority ratio is Rx:Tx or Tx:Rx depending on whether Bit 27 (TXPR) is reset or set.
In the GMAC-AXI configuration, these bits are reserved and read-only (RO). Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_PR_LSB 14 |
#define | ALT_EMAC_DMA_BUS_MOD_PR_MSB 15 |
#define | ALT_EMAC_DMA_BUS_MOD_PR_WIDTH 2 |
#define | ALT_EMAC_DMA_BUS_MOD_PR_SET_MSK 0x0000c000 |
#define | ALT_EMAC_DMA_BUS_MOD_PR_CLR_MSK 0xffff3fff |
#define | ALT_EMAC_DMA_BUS_MOD_PR_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_PR_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_EMAC_DMA_BUS_MOD_PR_SET(value) (((value) << 14) & 0x0000c000) |
Field : fb | |
Fixed Burst This bit controls whether the AHB or AXI Master interface performs fixed burst transfers or not. When set, the AHB interface uses only SINGLE, INCR4, INCR8, or INCR16 during start of the normal burst transfers. When reset, the AHB or AXI interface uses SINGLE and INCR burst transfer operations. For more information, see Bit 0 (UNDEF) of the AXI Bus Mode register in the GMAC-AXI configuration. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB | 0x0 | ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_LSB 16 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_MSB 16 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK 0x00010000 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_DMA_BUS_MOD_FB_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_FB_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_DMA_BUS_MOD_FB_SET(value) (((value) << 16) & 0x00010000) |
Field : rpbl | |
Rx DMA PBL This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write. The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. This field is valid and applicable only when USP is set high. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 | 0x1 | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 | 0x2 | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 | 0x4 | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 | 0x8 | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 | 0x10 | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 | 0x20 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_LSB 17 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_MSB 22 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH 6 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK 0x007e0000 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK 0xff81ffff |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_RESET 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value) (((value) & 0x007e0000) >> 17) |
#define | ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value) (((value) << 17) & 0x007e0000) |
Field : usp | |
Use Seperate PBL When set high, this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations. When reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_USP_E_DISD | 0x0 | ALT_EMAC_DMA_BUS_MOD_USP_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_LSB 23 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_MSB 23 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK 0x00800000 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK 0xff7fffff |
#define | ALT_EMAC_DMA_BUS_MOD_USP_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_USP_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_EMAC_DMA_BUS_MOD_USP_SET(value) (((value) << 23) & 0x00800000) |
Field : eightxpbl | |
PBLx8 Mode When set high, this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value. Note: This bit function is not backward compatible. Before release 3.50a, this bit was 4xPBL. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD | 0x0 | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB 24 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB 24 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK 0x01000000 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK 0xfeffffff |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value) (((value) << 24) & 0x01000000) |
Field : aal | |
Address Aligned Beats When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address. This bit is valid only in the GMAC-AHB and GMAC-AXI configuration and is reserved (RO with default value 0) in all other configurations. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD | 0x0 | ALT_EMAC_DMA_BUS_MOD_AAL_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_LSB 25 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_MSB 25 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK 0x02000000 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK 0xfdffffff |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_EMAC_DMA_BUS_MOD_AAL_SET(value) (((value) << 25) & 0x02000000) |
Field : mb | |
Mixed Burst When this bit is set high and the FB bit is low, the AHB Master interface starts all bursts of length more than 16 with INCR (undefined burst) whereas it reverts to fixed burst transfers (INCRx and SINGLE) for burst length of 16 and less. This bit is valid only in the GMAC-AHB configuration and reserved in all other configuration. Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_MB_LSB 26 |
#define | ALT_EMAC_DMA_BUS_MOD_MB_MSB 26 |
#define | ALT_EMAC_DMA_BUS_MOD_MB_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_MB_SET_MSK 0x04000000 |
#define | ALT_EMAC_DMA_BUS_MOD_MB_CLR_MSK 0xfbffffff |
#define | ALT_EMAC_DMA_BUS_MOD_MB_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_MB_GET(value) (((value) & 0x04000000) >> 26) |
#define | ALT_EMAC_DMA_BUS_MOD_MB_SET(value) (((value) << 26) & 0x04000000) |
Field : txpr | |
Transmit Priority When set, this bit indicates that the transmit DMA has higher priority than the receive DMA during arbitration for the system-side bus. In the GMAC-AXI configuration, this bit is reserved and read-only (RO). Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_LSB 27 |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_MSB 27 |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_SET_MSK 0x08000000 |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_CLR_MSK 0xf7ffffff |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_GET(value) (((value) & 0x08000000) >> 27) |
#define | ALT_EMAC_DMA_BUS_MOD_TXPR_SET(value) (((value) << 27) & 0x08000000) |
Field : prwg | |
Channel Priority Weights This field sets the priority weights for Channel 0 during the round-robin arbitration between the DMA channels for the system bus.
This field is present in all DWC_gmac configurations except GMAC-AXI when you select the AV feature. Otherwise, this field is reserved and read-only (RO). Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_LSB 28 |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_MSB 29 |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_WIDTH 2 |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_SET_MSK 0x30000000 |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_CLR_MSK 0xcfffffff |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_GET(value) (((value) & 0x30000000) >> 28) |
#define | ALT_EMAC_DMA_BUS_MOD_PRWG_SET(value) (((value) << 28) & 0x30000000) |
Field : reserved_30 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_LSB 30 |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_MSB 30 |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET_MSK 0x40000000 |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_CLR_MSK 0xbfffffff |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_GET(value) (((value) & 0x40000000) >> 30) |
#define | ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET(value) (((value) << 30) & 0x40000000) |
Field : rib | |
Rebuild INCRx Burst When this bit is set high and the AHB master gets an EBT (Retry, Split, or Losing bus grant), the AHB master interface rebuilds the pending beats of any burst transfer initiated with INCRx. The AHB master interface rebuilds the beats with a combination of specified bursts with INCRx and SINGLE. By default, the AHB master interface rebuilds pending beats of an EBT with an unspecified (INCR) burst. This bit is valid only in the GMAC-AHB configuration. It is reserved in all other configuration. Field Access Macros: | |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_LSB 31 |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_MSB 31 |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_WIDTH 1 |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_SET_MSK 0x80000000 |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_CLR_MSK 0x7fffffff |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_RESET 0x0 |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_EMAC_DMA_BUS_MOD_RIB_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_EMAC_DMA_BUS_MOD_s |
Macros | |
#define | ALT_EMAC_DMA_BUS_MOD_RESET 0x00020101 |
#define | ALT_EMAC_DMA_BUS_MOD_OFST 0x1000 |
#define | ALT_EMAC_DMA_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_DMA_BUS_MOD_s | ALT_EMAC_DMA_BUS_MOD_t |
struct ALT_EMAC_DMA_BUS_MOD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_DMA_BUS_MOD.
Data Fields | ||
---|---|---|
uint32_t | swr: 1 | ALT_EMAC_DMA_BUS_MOD_SWR |
uint32_t | da: 1 | ALT_EMAC_DMA_BUS_MOD_DA |
uint32_t | dsl: 5 | ALT_EMAC_DMA_BUS_MOD_DSL |
uint32_t | atds: 1 | ALT_EMAC_DMA_BUS_MOD_ATDS |
uint32_t | pbl: 6 | ALT_EMAC_DMA_BUS_MOD_PBL |
uint32_t | pr: 2 | ALT_EMAC_DMA_BUS_MOD_PR |
uint32_t | fb: 1 | ALT_EMAC_DMA_BUS_MOD_FB |
uint32_t | rpbl: 6 | ALT_EMAC_DMA_BUS_MOD_RPBL |
uint32_t | usp: 1 | ALT_EMAC_DMA_BUS_MOD_USP |
uint32_t | eightxpbl: 1 | ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL |
uint32_t | aal: 1 | ALT_EMAC_DMA_BUS_MOD_AAL |
uint32_t | mb: 1 | ALT_EMAC_DMA_BUS_MOD_MB |
uint32_t | txpr: 1 | ALT_EMAC_DMA_BUS_MOD_TXPR |
uint32_t | prwg: 2 | ALT_EMAC_DMA_BUS_MOD_PRWG |
const uint32_t | reserved_30: 1 | ALT_EMAC_DMA_BUS_MOD_RSVD_30 |
uint32_t | rib: 1 | ALT_EMAC_DMA_BUS_MOD_RIB |
#define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
#define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR
#define ALT_EMAC_DMA_BUS_MOD_SWR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field.
#define ALT_EMAC_DMA_BUS_MOD_SWR_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field.
#define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field.
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value.
#define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value.
#define ALT_EMAC_DMA_BUS_MOD_SWR_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field.
#define ALT_EMAC_DMA_BUS_MOD_SWR_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_DA_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DA register field.
#define ALT_EMAC_DMA_BUS_MOD_DA_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DA register field.
#define ALT_EMAC_DMA_BUS_MOD_DA_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_DA register field.
#define ALT_EMAC_DMA_BUS_MOD_DA_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_DA register field value.
#define ALT_EMAC_DMA_BUS_MOD_DA_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DA register field value.
#define ALT_EMAC_DMA_BUS_MOD_DA_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_DA register field.
#define ALT_EMAC_DMA_BUS_MOD_DA_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_DMA_BUS_MOD_DA field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_DA_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_DMA_BUS_MOD_DA register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_DSL_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field.
#define ALT_EMAC_DMA_BUS_MOD_DSL_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field.
#define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH 5 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field.
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK 0x0000007c |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value.
#define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK 0xffffff83 |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value.
#define ALT_EMAC_DMA_BUS_MOD_DSL_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field.
#define ALT_EMAC_DMA_BUS_MOD_DSL_GET | ( | value | ) | (((value) & 0x0000007c) >> 2) |
Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET | ( | value | ) | (((value) << 2) & 0x0000007c) |
Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS
#define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_PBL_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field.
#define ALT_EMAC_DMA_BUS_MOD_PBL_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field.
#define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH 6 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field.
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK 0x00003f00 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK 0xffffc0ff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_PBL_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field.
#define ALT_EMAC_DMA_BUS_MOD_PBL_GET | ( | value | ) | (((value) & 0x00003f00) >> 8) |
Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET | ( | value | ) | (((value) << 8) & 0x00003f00) |
Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_PR_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PR register field.
#define ALT_EMAC_DMA_BUS_MOD_PR_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PR register field.
#define ALT_EMAC_DMA_BUS_MOD_PR_WIDTH 2 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_PR register field.
#define ALT_EMAC_DMA_BUS_MOD_PR_SET_MSK 0x0000c000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_PR register field value.
#define ALT_EMAC_DMA_BUS_MOD_PR_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PR register field value.
#define ALT_EMAC_DMA_BUS_MOD_PR_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_PR register field.
#define ALT_EMAC_DMA_BUS_MOD_PR_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_EMAC_DMA_BUS_MOD_PR field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_PR_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_EMAC_DMA_BUS_MOD_PR register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
#define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB
#define ALT_EMAC_DMA_BUS_MOD_FB_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field.
#define ALT_EMAC_DMA_BUS_MOD_FB_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field.
#define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field.
#define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value.
#define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value.
#define ALT_EMAC_DMA_BUS_MOD_FB_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field.
#define ALT_EMAC_DMA_BUS_MOD_FB_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_FB_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL
#define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH 6 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK 0x007e0000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK 0xff81ffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_GET | ( | value | ) | (((value) & 0x007e0000) >> 17) |
Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET | ( | value | ) | (((value) << 17) & 0x007e0000) |
Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
#define ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP
#define ALT_EMAC_DMA_BUS_MOD_USP_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field.
#define ALT_EMAC_DMA_BUS_MOD_USP_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field.
#define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field.
#define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK 0x00800000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value.
#define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value.
#define ALT_EMAC_DMA_BUS_MOD_USP_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field.
#define ALT_EMAC_DMA_BUS_MOD_USP_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_USP_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
#define ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL
#define ALT_EMAC_DMA_BUS_MOD_AAL_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field.
#define ALT_EMAC_DMA_BUS_MOD_AAL_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field.
#define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field.
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value.
#define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value.
#define ALT_EMAC_DMA_BUS_MOD_AAL_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field.
#define ALT_EMAC_DMA_BUS_MOD_AAL_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_MB_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_MB register field.
#define ALT_EMAC_DMA_BUS_MOD_MB_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_MB register field.
#define ALT_EMAC_DMA_BUS_MOD_MB_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_MB register field.
#define ALT_EMAC_DMA_BUS_MOD_MB_SET_MSK 0x04000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_MB register field value.
#define ALT_EMAC_DMA_BUS_MOD_MB_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_MB register field value.
#define ALT_EMAC_DMA_BUS_MOD_MB_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_MB register field.
#define ALT_EMAC_DMA_BUS_MOD_MB_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_EMAC_DMA_BUS_MOD_MB field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_MB_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_MB register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_TXPR register field.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_TXPR register field.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_TXPR register field.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_SET_MSK 0x08000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_TXPR register field value.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_TXPR register field value.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_TXPR register field.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_EMAC_DMA_BUS_MOD_TXPR field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_TXPR_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_TXPR register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PRWG register field.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PRWG register field.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_WIDTH 2 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_PRWG register field.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_SET_MSK 0x30000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_PRWG register field value.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_CLR_MSK 0xcfffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PRWG register field value.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_PRWG register field.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_GET | ( | value | ) | (((value) & 0x30000000) >> 28) |
Extracts the ALT_EMAC_DMA_BUS_MOD_PRWG field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_PRWG_SET | ( | value | ) | (((value) << 28) & 0x30000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_PRWG register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_LSB 30 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET_MSK 0x40000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_CLR_MSK 0xbfffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_GET | ( | value | ) | (((value) & 0x40000000) >> 30) |
Extracts the ALT_EMAC_DMA_BUS_MOD_RSVD_30 field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_RSVD_30_SET | ( | value | ) | (((value) << 30) & 0x40000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_RSVD_30 register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_RIB_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RIB register field.
#define ALT_EMAC_DMA_BUS_MOD_RIB_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RIB register field.
#define ALT_EMAC_DMA_BUS_MOD_RIB_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_BUS_MOD_RIB register field.
#define ALT_EMAC_DMA_BUS_MOD_RIB_SET_MSK 0x80000000 |
The mask used to set the ALT_EMAC_DMA_BUS_MOD_RIB register field value.
#define ALT_EMAC_DMA_BUS_MOD_RIB_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RIB register field value.
#define ALT_EMAC_DMA_BUS_MOD_RIB_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_BUS_MOD_RIB register field.
#define ALT_EMAC_DMA_BUS_MOD_RIB_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_EMAC_DMA_BUS_MOD_RIB field value from a register.
#define ALT_EMAC_DMA_BUS_MOD_RIB_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_EMAC_DMA_BUS_MOD_RIB register field value suitable for setting the register.
#define ALT_EMAC_DMA_BUS_MOD_RESET 0x00020101 |
The reset value of the ALT_EMAC_DMA_BUS_MOD register.
#define ALT_EMAC_DMA_BUS_MOD_OFST 0x1000 |
The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component.
#define ALT_EMAC_DMA_BUS_MOD_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST)) |
The address of the ALT_EMAC_DMA_BUS_MOD register.
typedef struct ALT_EMAC_DMA_BUS_MOD_s ALT_EMAC_DMA_BUS_MOD_t |
The typedef declaration for register ALT_EMAC_DMA_BUS_MOD.