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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Activate freeze or thaw operations on VIO channel 1 (HPS IO bank 2 and bank 3) and monitor for completeness and the current state.
These fields interact with the hardware state machine in the Freeze Controller. These fields can be accessed independent of the value of SRC1.VIO1 although they only have an effect on the VIO channel 1 freeze signals when SRC1.VIO1 is setup to have the hardware state machine be the freeze signal source.
All fields are only reset by a cold reset (ignore warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | VIO channel 1 Freeze/Thaw request |
[2:1] | R | 0x2 | VIO channel 1 State |
[31:3] | ??? | 0x0 | UNDEFINED |
Field : VIO channel 1 Freeze/Thaw request - vio1req | ||||||||||
Requests hardware state machine to generate freeze signal sequence to transition between frozen and thawed states. If this field is read by software, it contains the value previously written by software (i.e. this field is not written by hardware). Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : VIO channel 1 State - vio1state | |||||||||||||||||||||||||||||||
Software reads this field to determine the current frozen/thawed state of the VIO channel 1 or to determine when a freeze/thaw request is made by writing the corresponding *REQ field in this register has completed. Reset by a cold reset (ignores warm reset). Field Enumeration Values:
Field Access Macros: | |||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1) | ||||||||||||||||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006) | ||||||||||||||||||||||||||||||
Data Structures | |
struct | ALT_SYSMGR_FRZCTL_HWCTL_s |
Macros | |
#define | ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 |
Typedefs | |
typedef struct ALT_SYSMGR_FRZCTL_HWCTL_s | ALT_SYSMGR_FRZCTL_HWCTL_t |
struct ALT_SYSMGR_FRZCTL_HWCTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_FRZCTL_HWCTL.
Data Fields | ||
---|---|---|
uint32_t | vio1req: 1 | VIO channel 1 Freeze/Thaw request |
const uint32_t | vio1state: 2 | VIO channel 1 State |
uint32_t | __pad0__: 29 | UNDEFINED |
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
Requests a thaw (unfreeze) operation.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ
Requests a freeze operation.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1 |
The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ field value from a register.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
Transitioning from thawed state to frozen state.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
Thawed state. I/Os behave as configured. I/Os must be configured by the Scan Manager before entering this state.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
Frozen state. I/O configuration is ignored. Instead, I/Os are in tri-state mode with a weak pull-up. Scan Manager can be used to configure the I/Os while they are frozen.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE
Transitioning from frozen state to thawed state.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2 |
The width in bits of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006 |
The mask used to set the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9 |
The mask used to clear the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2 |
The reset value of the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET | ( | value | ) | (((value) & 0x00000006) >> 1) |
Extracts the ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE field value from a register.
#define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET | ( | value | ) | (((value) << 1) & 0x00000006) |
Produces a ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18 |
The byte offset of the ALT_SYSMGR_FRZCTL_HWCTL register from the beginning of the component.
typedef struct ALT_SYSMGR_FRZCTL_HWCTL_s ALT_SYSMGR_FRZCTL_HWCTL_t |
The typedef declaration for register ALT_SYSMGR_FRZCTL_HWCTL.