Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Peripheral PLL C0 Control Register for Clock emac0_clk - emac0clk

Description

Contains settings that control clock emac0_clk generated from the C0 output of the Peripheral PLL.

Only reset by a cold reset.

Register Layout

Bits Access Reset Description
[8:0] RW 0x1 Counter
[31:9] ??? 0x0 UNDEFINED

Field : Counter - cnt

Divides the VCO frequency by the value+1 in this field.

Field Access Macros:

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB   0
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB   8
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH   9
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK   0x000001ff
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK   0xfffffe00
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET   0x1
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value)   (((value) & 0x000001ff) >> 0)
 
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value)   (((value) << 0) & 0x000001ff)
 

Data Structures

struct  ALT_CLKMGR_PERPLL_EMAC0CLK_s
 

Macros

#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST   0x8
 

Typedefs

typedef struct
ALT_CLKMGR_PERPLL_EMAC0CLK_s 
ALT_CLKMGR_PERPLL_EMAC0CLK_t
 

Data Structure Documentation

struct ALT_CLKMGR_PERPLL_EMAC0CLK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK.

Data Fields
uint32_t cnt: 9 Counter
uint32_t __pad0__: 23 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB   8

The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH   9

The width in bits of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK   0x000001ff

The mask used to set the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK   0xfffffe00

The mask used to clear the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET   0x1

The reset value of the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET (   value)    (((value) & 0x000001ff) >> 0)

Extracts the ALT_CLKMGR_PERPLL_EMAC0CLK_CNT field value from a register.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET (   value)    (((value) << 0) & 0x000001ff)

Produces a ALT_CLKMGR_PERPLL_EMAC0CLK_CNT register field value suitable for setting the register.

#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST   0x8

The byte offset of the ALT_CLKMGR_PERPLL_EMAC0CLK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_PERPLL_EMAC0CLK.