Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Component : ALT_PINMUX_DCTD_IO_GRP

Description

Members

 Register : Dedicated IO 1 OSC_CLK - pinmux_dedicated_io_1
 
 Register : Dedicated IO 2 nPOR - pinmux_dedicated_io_2
 
 Register : Dedicated IO 3 nRST - pinmux_dedicated_io_3
 
 Register : Dedicated IO 4 Mux Selection Register - pinmux_dedicated_io_4
 
 Register : Dedicated IO 5 Mux Selection Register - pinmux_dedicated_io_5
 
 Register : Dedicated IO 6 Mux Selection Register - pinmux_dedicated_io_6
 
 Register : Dedicated IO 7 Mux Selection Register - pinmux_dedicated_io_7
 
 Register : Dedicated IO 8 Mux Selection Register - pinmux_dedicated_io_8
 
 Register : Dedicated IO 9 Mux Selection Register - pinmux_dedicated_io_9
 
 Register : Dedicated IO 10 Mux Selection Register - pinmux_dedicated_io_10
 
 Register : Dedicated IO 11 Mux Selection Register - pinmux_dedicated_io_11
 
 Register : Dedicated IO 12 Mux Selection Register - pinmux_dedicated_io_12
 
 Register : Dedicated IO 13 Mux Selection Register - pinmux_dedicated_io_13
 
 Register : Dedicated IO 14 Mux Selection Register - pinmux_dedicated_io_14
 
 Register : Dedicated IO 15 Mux Selection Register - pinmux_dedicated_io_15
 
 Register : Dedicated IO 16 Mux Selection Register - pinmux_dedicated_io_16
 
 Register : Dedicated IO 17 Mux Selection Register - pinmux_dedicated_io_17
 
 Register : Voltage Level Configuration Register - configuration_dedicated_io_bank
 
 Register : Dedicated IO 1 Configuration Register - configuration_dedicated_io_1
 
 Register : Dedicated IO 2 Configuration Register - configuration_dedicated_io_2
 
 Register : Dedicated IO 3 Configuration Register - configuration_dedicated_io_3
 
 Register : Dedicated IO 4 Configuration Register - configuration_dedicated_io_4
 
 Register : Dedicated IO 5 Configuration Register - configuration_dedicated_io_5
 
 Register : Dedicated IO 6 Configuration Register - configuration_dedicated_io_6
 
 Register : Dedicated IO 7 Configuration Register - configuration_dedicated_io_7
 
 Register : Dedicated IO 8 Configuration Register - configuration_dedicated_io_8
 
 Register : Dedicated IO 9 Configuration Register - configuration_dedicated_io_9
 
 Register : Dedicated IO 10 Configuration Register - configuration_dedicated_io_10
 
 Register : Dedicated IO 11 Configuration Register - configuration_dedicated_io_11
 
 Register : Dedicated IO 12 Configuration Register - configuration_dedicated_io_12
 
 Register : Dedicated IO 13 Configuration Register - configuration_dedicated_io_13
 
 Register : Dedicated IO 14 Configuration Register - configuration_dedicated_io_14
 
 Register : Dedicated IO 15 Configuration Register - configuration_dedicated_io_15
 
 Register : Dedicated IO 16 Configuration Register - configuration_dedicated_io_16
 
 Register : Dedicated IO 17 Configuration Register - configuration_dedicated_io_17
 

Data Structures

struct  ALT_PINMUX_DCTD_IO_GRP_s
 
struct  ALT_PINMUX_DCTD_IO_GRP_raw_s
 

Typedefs

typedef struct
ALT_PINMUX_DCTD_IO_GRP_s 
ALT_PINMUX_DCTD_IO_GRP_t
 
typedef struct
ALT_PINMUX_DCTD_IO_GRP_raw_s 
ALT_PINMUX_DCTD_IO_GRP_raw_t
 

Data Structure Documentation

struct ALT_PINMUX_DCTD_IO_GRP_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register group ALT_PINMUX_DCTD_IO_GRP.

Data Fields
volatile ALT_PINMUX_DCTD_IO_1_t pinmux_dedicated_io_1 ALT_PINMUX_DCTD_IO_1
volatile ALT_PINMUX_DCTD_IO_2_t pinmux_dedicated_io_2 ALT_PINMUX_DCTD_IO_2
volatile ALT_PINMUX_DCTD_IO_3_t pinmux_dedicated_io_3 ALT_PINMUX_DCTD_IO_3
volatile ALT_PINMUX_DCTD_IO_4_t pinmux_dedicated_io_4 ALT_PINMUX_DCTD_IO_4
volatile ALT_PINMUX_DCTD_IO_5_t pinmux_dedicated_io_5 ALT_PINMUX_DCTD_IO_5
volatile ALT_PINMUX_DCTD_IO_6_t pinmux_dedicated_io_6 ALT_PINMUX_DCTD_IO_6
volatile ALT_PINMUX_DCTD_IO_7_t pinmux_dedicated_io_7 ALT_PINMUX_DCTD_IO_7
volatile ALT_PINMUX_DCTD_IO_8_t pinmux_dedicated_io_8 ALT_PINMUX_DCTD_IO_8
volatile ALT_PINMUX_DCTD_IO_9_t pinmux_dedicated_io_9 ALT_PINMUX_DCTD_IO_9
volatile ALT_PINMUX_DCTD_IO_10_t pinmux_dedicated_io_10 ALT_PINMUX_DCTD_IO_10
volatile ALT_PINMUX_DCTD_IO_11_t pinmux_dedicated_io_11 ALT_PINMUX_DCTD_IO_11
volatile ALT_PINMUX_DCTD_IO_12_t pinmux_dedicated_io_12 ALT_PINMUX_DCTD_IO_12
volatile ALT_PINMUX_DCTD_IO_13_t pinmux_dedicated_io_13 ALT_PINMUX_DCTD_IO_13
volatile ALT_PINMUX_DCTD_IO_14_t pinmux_dedicated_io_14 ALT_PINMUX_DCTD_IO_14
volatile ALT_PINMUX_DCTD_IO_15_t pinmux_dedicated_io_15 ALT_PINMUX_DCTD_IO_15
volatile ALT_PINMUX_DCTD_IO_16_t pinmux_dedicated_io_16 ALT_PINMUX_DCTD_IO_16
volatile ALT_PINMUX_DCTD_IO_17_t pinmux_dedicated_io_17 ALT_PINMUX_DCTD_IO_17
volatile uint32_t _pad_0x44_0xff UNDEFINED
volatile
ALT_PINMUX_DCTD_IO_CFG_BANK_t
configuration_dedicated_io_bank ALT_PINMUX_DCTD_IO_CFG_BANK
volatile ALT_PINMUX_DCTD_IO_CFG_1_t configuration_dedicated_io_1 ALT_PINMUX_DCTD_IO_CFG_1
volatile ALT_PINMUX_DCTD_IO_CFG_2_t configuration_dedicated_io_2 ALT_PINMUX_DCTD_IO_CFG_2
volatile ALT_PINMUX_DCTD_IO_CFG_3_t configuration_dedicated_io_3 ALT_PINMUX_DCTD_IO_CFG_3
volatile ALT_PINMUX_DCTD_IO_CFG_4_t configuration_dedicated_io_4 ALT_PINMUX_DCTD_IO_CFG_4
volatile ALT_PINMUX_DCTD_IO_CFG_5_t configuration_dedicated_io_5 ALT_PINMUX_DCTD_IO_CFG_5
volatile ALT_PINMUX_DCTD_IO_CFG_6_t configuration_dedicated_io_6 ALT_PINMUX_DCTD_IO_CFG_6
volatile ALT_PINMUX_DCTD_IO_CFG_7_t configuration_dedicated_io_7 ALT_PINMUX_DCTD_IO_CFG_7
volatile ALT_PINMUX_DCTD_IO_CFG_8_t configuration_dedicated_io_8 ALT_PINMUX_DCTD_IO_CFG_8
volatile ALT_PINMUX_DCTD_IO_CFG_9_t configuration_dedicated_io_9 ALT_PINMUX_DCTD_IO_CFG_9
volatile
ALT_PINMUX_DCTD_IO_CFG_10_t
configuration_dedicated_io_10 ALT_PINMUX_DCTD_IO_CFG_10
volatile
ALT_PINMUX_DCTD_IO_CFG_11_t
configuration_dedicated_io_11 ALT_PINMUX_DCTD_IO_CFG_11
volatile
ALT_PINMUX_DCTD_IO_CFG_12_t
configuration_dedicated_io_12 ALT_PINMUX_DCTD_IO_CFG_12
volatile
ALT_PINMUX_DCTD_IO_CFG_13_t
configuration_dedicated_io_13 ALT_PINMUX_DCTD_IO_CFG_13
volatile
ALT_PINMUX_DCTD_IO_CFG_14_t
configuration_dedicated_io_14 ALT_PINMUX_DCTD_IO_CFG_14
volatile
ALT_PINMUX_DCTD_IO_CFG_15_t
configuration_dedicated_io_15 ALT_PINMUX_DCTD_IO_CFG_15
volatile
ALT_PINMUX_DCTD_IO_CFG_16_t
configuration_dedicated_io_16 ALT_PINMUX_DCTD_IO_CFG_16
volatile
ALT_PINMUX_DCTD_IO_CFG_17_t
configuration_dedicated_io_17 ALT_PINMUX_DCTD_IO_CFG_17
volatile uint32_t _pad_0x148_0x200 UNDEFINED
struct ALT_PINMUX_DCTD_IO_GRP_raw_s

The struct declaration for the raw register contents of register group ALT_PINMUX_DCTD_IO_GRP.

Data Fields
volatile uint32_t pinmux_dedicated_io_1 ALT_PINMUX_DCTD_IO_1
volatile uint32_t pinmux_dedicated_io_2 ALT_PINMUX_DCTD_IO_2
volatile uint32_t pinmux_dedicated_io_3 ALT_PINMUX_DCTD_IO_3
volatile uint32_t pinmux_dedicated_io_4 ALT_PINMUX_DCTD_IO_4
volatile uint32_t pinmux_dedicated_io_5 ALT_PINMUX_DCTD_IO_5
volatile uint32_t pinmux_dedicated_io_6 ALT_PINMUX_DCTD_IO_6
volatile uint32_t pinmux_dedicated_io_7 ALT_PINMUX_DCTD_IO_7
volatile uint32_t pinmux_dedicated_io_8 ALT_PINMUX_DCTD_IO_8
volatile uint32_t pinmux_dedicated_io_9 ALT_PINMUX_DCTD_IO_9
volatile uint32_t pinmux_dedicated_io_10 ALT_PINMUX_DCTD_IO_10
volatile uint32_t pinmux_dedicated_io_11 ALT_PINMUX_DCTD_IO_11
volatile uint32_t pinmux_dedicated_io_12 ALT_PINMUX_DCTD_IO_12
volatile uint32_t pinmux_dedicated_io_13 ALT_PINMUX_DCTD_IO_13
volatile uint32_t pinmux_dedicated_io_14 ALT_PINMUX_DCTD_IO_14
volatile uint32_t pinmux_dedicated_io_15 ALT_PINMUX_DCTD_IO_15
volatile uint32_t pinmux_dedicated_io_16 ALT_PINMUX_DCTD_IO_16
volatile uint32_t pinmux_dedicated_io_17 ALT_PINMUX_DCTD_IO_17
volatile uint32_t _pad_0x44_0xff UNDEFINED
volatile uint32_t configuration_dedicated_io_bank ALT_PINMUX_DCTD_IO_CFG_BANK
volatile uint32_t configuration_dedicated_io_1 ALT_PINMUX_DCTD_IO_CFG_1
volatile uint32_t configuration_dedicated_io_2 ALT_PINMUX_DCTD_IO_CFG_2
volatile uint32_t configuration_dedicated_io_3 ALT_PINMUX_DCTD_IO_CFG_3
volatile uint32_t configuration_dedicated_io_4 ALT_PINMUX_DCTD_IO_CFG_4
volatile uint32_t configuration_dedicated_io_5 ALT_PINMUX_DCTD_IO_CFG_5
volatile uint32_t configuration_dedicated_io_6 ALT_PINMUX_DCTD_IO_CFG_6
volatile uint32_t configuration_dedicated_io_7 ALT_PINMUX_DCTD_IO_CFG_7
volatile uint32_t configuration_dedicated_io_8 ALT_PINMUX_DCTD_IO_CFG_8
volatile uint32_t configuration_dedicated_io_9 ALT_PINMUX_DCTD_IO_CFG_9
volatile uint32_t configuration_dedicated_io_10 ALT_PINMUX_DCTD_IO_CFG_10
volatile uint32_t configuration_dedicated_io_11 ALT_PINMUX_DCTD_IO_CFG_11
volatile uint32_t configuration_dedicated_io_12 ALT_PINMUX_DCTD_IO_CFG_12
volatile uint32_t configuration_dedicated_io_13 ALT_PINMUX_DCTD_IO_CFG_13
volatile uint32_t configuration_dedicated_io_14 ALT_PINMUX_DCTD_IO_CFG_14
volatile uint32_t configuration_dedicated_io_15 ALT_PINMUX_DCTD_IO_CFG_15
volatile uint32_t configuration_dedicated_io_16 ALT_PINMUX_DCTD_IO_CFG_16
volatile uint32_t configuration_dedicated_io_17 ALT_PINMUX_DCTD_IO_CFG_17
volatile uint32_t _pad_0x148_0x200 UNDEFINED

Typedef Documentation

The typedef declaration for register group ALT_PINMUX_DCTD_IO_GRP.

The typedef declaration for the raw register contents of register group ALT_PINMUX_DCTD_IO_GRP.