Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Enable Reset Register - enr

Description

Write One to Clear corresponding fields in Enable Register.

Register Layout

Bits Access Reset Description
[0] RW 0x1 MPU Clock Group Enable
[1] RW 0x1 l4_main_clk Enable
[2] RW 0x1 l4_mp_clk Enable
[3] RW 0x1 l4_sp_clk Enable
[4] RW 0x1 Debug Group Enable
[5] RW 0x1 Debug Timer Enable
[6] RW 0x1 s2f_user0_clk Enable
[7] RW 0x1 hmc_pll_ref_clk Enable
[31:8] ??? 0x0 UNDEFINED

Field : MPU Clock Group Enable - mpuclken

Enable for MPU Clock Group (mpu_clk, mpu_l2ram_clk and mpu_periph_clk).

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_LSB   0
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_MSB   0
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET_MSK   0x00000001
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : l4_main_clk Enable - l4mainclken

Enables clock l4_main_clk output

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_LSB   1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_MSB   1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET_MSK   0x00000002
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_CLR_MSK   0xfffffffd
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET(value)   (((value) << 1) & 0x00000002)
 

Field : l4_mp_clk Enable - l4mpclken

Enables clock l4_mp_clk output

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_LSB   2
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_MSB   2
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET_MSK   0x00000004
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_CLR_MSK   0xfffffffb
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET(value)   (((value) << 2) & 0x00000004)
 

Field : l4_sp_clk Enable - l4spclken

Enables clock l4_sp_clk output

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_LSB   3
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_MSB   3
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET_MSK   0x00000008
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_CLR_MSK   0xfffffff7
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Debug Group Enable - csclken

Enables Debug Clock outputs (cs_at_clk, cs_pdbg_clk and cs_trace_clk)

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_LSB   4
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_MSB   4
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET_MSK   0x00000010
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_CLR_MSK   0xffffffef
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Debug Timer Enable - cstimerclken

Enables Debug Timer Clock output (cs_timer_clk)

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_LSB   5
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_MSB   5
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET_MSK   0x00000020
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_CLR_MSK   0xffffffdf
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET(value)   (((value) << 5) & 0x00000020)
 

Field : s2f_user0_clk Enable - s2fuser0clken

Enables clock s2f_user0_clk output

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_LSB   6
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_MSB   6
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET_MSK   0x00000040
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_CLR_MSK   0xffffffbf
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET(value)   (((value) << 6) & 0x00000040)
 

Field : hmc_pll_ref_clk Enable - hmcpllrefclken

Enables clock hmc_pll_ref_clk output

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_LSB   7
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_MSB   7
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET_MSK   0x00000080
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_CLR_MSK   0xffffff7f
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_RESET   0x1
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET(value)   (((value) << 7) & 0x00000080)
 

Data Structures

struct  ALT_CLKMGR_MAINPLL_ENR_s
 

Macros

#define ALT_CLKMGR_MAINPLL_ENR_RESET   0x000000ff
 
#define ALT_CLKMGR_MAINPLL_ENR_OFST   0x10
 

Typedefs

typedef struct
ALT_CLKMGR_MAINPLL_ENR_s 
ALT_CLKMGR_MAINPLL_ENR_t
 

Data Structure Documentation

struct ALT_CLKMGR_MAINPLL_ENR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_MAINPLL_ENR.

Data Fields
uint32_t mpuclken: 1 MPU Clock Group Enable
uint32_t l4mainclken: 1 l4_main_clk Enable
uint32_t l4mpclken: 1 l4_mp_clk Enable
uint32_t l4spclken: 1 l4_sp_clk Enable
uint32_t csclken: 1 Debug Group Enable
uint32_t cstimerclken: 1 Debug Timer Enable
uint32_t s2fuser0clken: 1 s2f_user0_clk Enable
uint32_t hmcpllrefclken: 1 hmc_pll_ref_clk Enable
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_LSB   1

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_MSB   1

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET_MSK   0x00000002

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_CLR_MSK   0xfffffffd

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_LSB   2

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_MSB   2

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET_MSK   0x00000004

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_CLR_MSK   0xfffffffb

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_LSB   3

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_MSB   3

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET_MSK   0x00000008

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_CLR_MSK   0xfffffff7

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_LSB   4

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_MSB   4

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET_MSK   0x00000010

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_CLR_MSK   0xffffffef

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_CLKMGR_MAINPLL_ENR_CSCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_CLKMGR_MAINPLL_ENR_CSCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_LSB   5

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_MSB   5

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET_MSK   0x00000020

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_CLR_MSK   0xffffffdf

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_LSB   6

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_MSB   6

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET_MSK   0x00000040

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_CLR_MSK   0xffffffbf

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_LSB   7

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_MSB   7

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET_MSK   0x00000080

The mask used to set the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_CLR_MSK   0xffffff7f

The mask used to clear the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_RESET   0x1

The reset value of the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN field value from a register.

#define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_ENR_RESET   0x000000ff

The reset value of the ALT_CLKMGR_MAINPLL_ENR register.

#define ALT_CLKMGR_MAINPLL_ENR_OFST   0x10

The byte offset of the ALT_CLKMGR_MAINPLL_ENR register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_MAINPLL_ENR.