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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register maintains the interrupts generated when receive IPC statistic counters reach half their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and when they cross their maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all- ones. The MMC Receive Checksum Offload Interrupt register is 32-bits wide. When the MMC IPC counter that caused the interrupt is read, its corresponding interrupt bit is cleared. The counter's least-significant byte lane (bits[7:0]) must be read to clear the interrupt bit.
Register Layout
Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Status - rxipv4herfis | ||||||||||
This bit is set when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK 0x00000002 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Status - rxipv4nopayfis | ||||||||||
This bit is set when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB 2 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB 2 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK 0x00000004 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status - rxipv4fragfis | ||||||||||
This bit is set when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB 3 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB 3 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK 0x00000008 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status - rxipv4udsblfis | ||||||||||
This bit is set when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB 4 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB 4 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK 0x00000010 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK 0xffffffef | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : MMC Receive IPV6 Good Frame Counter Interrupt Status - rxipv6gfis | ||||||||||
This bit is set when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB 5 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB 5 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK 0x00000020 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Status - rxipv6herfis | ||||||||||
This bit is set when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB 6 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB 6 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK 0x00000040 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Status - rxipv6nopayfis | ||||||||||
This bit is set when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB 7 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB 7 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK 0x00000080 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : MMC Receive UDP Good Frame Counter Interrupt Status - rxudpgfis | ||||||||||
This bit is set when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB 8 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB 8 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK 0x00000100 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : MMC Receive UDP Error Frame Counter Interrupt Status - rxudperfis | ||||||||||
This bit is set when the rxudp_err_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB 9 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB 9 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK 0x00000200 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK 0xfffffdff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET(value) (((value) & 0x00000200) >> 9) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET(value) (((value) << 9) & 0x00000200) | |||||||||
Field : MMC Receive TCP Good Frame Counter Interrupt Status - rxtcpgfis | ||||||||||
This bit is set when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB 10 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB 10 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK 0x00000400 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK 0xfffffbff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET(value) (((value) & 0x00000400) >> 10) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET(value) (((value) << 10) & 0x00000400) | |||||||||
Field : MMC Receive TCP Error Frame Counter Interrupt Status - rxtcperfis | ||||||||||
This bit is set when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB 11 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB 11 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK 0x00000800 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK 0xfffff7ff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET(value) (((value) & 0x00000800) >> 11) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET(value) (((value) << 11) & 0x00000800) | |||||||||
Field : MMC Receive ICMP Good Frame Counter Interrupt Status - rxicmpgfis | ||||||||||
This bit is set when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB 12 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB 12 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK 0x00001000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK 0xffffefff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET(value) (((value) & 0x00001000) >> 12) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET(value) (((value) << 12) & 0x00001000) | |||||||||
Field : MMC Receive ICMP Error Frame Counter Interrupt Status - rxicmperfis | ||||||||||
This bit is set when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB 13 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB 13 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK 0x00002000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK 0xffffdfff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET(value) (((value) & 0x00002000) >> 13) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET(value) (((value) << 13) & 0x00002000) | |||||||||
Field : MMC Receive IPV4 Good Octet Counter Interrupt Status - rxipv4gois | ||||||||||
This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB 16 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB 16 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK 0x00010000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK 0xfffeffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET(value) (((value) & 0x00010000) >> 16) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET(value) (((value) << 16) & 0x00010000) | |||||||||
Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Status - rxipv4herois | ||||||||||
This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB 17 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB 17 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK 0x00020000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK 0xfffdffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET(value) (((value) & 0x00020000) >> 17) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET(value) (((value) << 17) & 0x00020000) | |||||||||
Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Status - rxipv4nopayois | ||||||||||
This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB 18 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB 18 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK 0x00040000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK 0xfffbffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET(value) (((value) & 0x00040000) >> 18) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET(value) (((value) << 18) & 0x00040000) | |||||||||
Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status - rxipv4fragois | ||||||||||
This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB 19 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB 19 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK 0x00080000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK 0xfff7ffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET(value) (((value) & 0x00080000) >> 19) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET(value) (((value) << 19) & 0x00080000) | |||||||||
Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status - rxipv4udsblois | ||||||||||
This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB 20 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB 20 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK 0x00100000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK 0xffefffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET(value) (((value) & 0x00100000) >> 20) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET(value) (((value) << 20) & 0x00100000) | |||||||||
Field : MMC Receive IPV6 Good Octet Counter Interrupt Status - rxipv6gois | ||||||||||
This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB 21 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB 21 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK 0x00200000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK 0xffdfffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET(value) (((value) & 0x00200000) >> 21) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET(value) (((value) << 21) & 0x00200000) | |||||||||
Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Status - rxipv6herois | ||||||||||
This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB 22 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB 22 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK 0x00400000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK 0xffbfffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET(value) (((value) & 0x00400000) >> 22) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET(value) (((value) << 22) & 0x00400000) | |||||||||
Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Status - rxipv6nopayois | ||||||||||
This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB 23 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB 23 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK 0x00800000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK 0xff7fffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET(value) (((value) & 0x00800000) >> 23) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET(value) (((value) << 23) & 0x00800000) | |||||||||
Field : MMC Receive UDP Good Octet Counter Interrupt Status - rxudpgois | ||||||||||
This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB 24 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB 24 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK 0x01000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK 0xfeffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET(value) (((value) & 0x01000000) >> 24) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET(value) (((value) << 24) & 0x01000000) | |||||||||
Field : MMC Receive UDP Error Octet Counter Interrupt Status - rxudperois | ||||||||||
This bit is set when the rxudp_err_octets counter reaches half the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB 25 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB 25 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK 0x02000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK 0xfdffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET(value) (((value) & 0x02000000) >> 25) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET(value) (((value) << 25) & 0x02000000) | |||||||||
Field : MMC Receive TCP Good Octet Counter Interrupt Status - rxtcpgois | ||||||||||
This bit is set when the rxtcp_gd_octets counter reaches half the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB 26 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB 26 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK 0x04000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK 0xfbffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET(value) (((value) & 0x04000000) >> 26) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET(value) (((value) << 26) & 0x04000000) | |||||||||
Field : MMC Receive TCP Error Octet Counter Interrupt Status - rxtcperois | ||||||||||
This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB 27 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB 27 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK 0x08000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK 0xf7ffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET(value) (((value) & 0x08000000) >> 27) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET(value) (((value) << 27) & 0x08000000) | |||||||||
Field : MMC Receive ICMP Good Octet Counter Interrupt Status - rxicmpgois | ||||||||||
This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB 28 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB 28 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK 0x10000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK 0xefffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET(value) (((value) & 0x10000000) >> 28) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET(value) (((value) << 28) & 0x10000000) | |||||||||
Field : MMC Receive ICMP Error Octet Counter Interrupt Status - rxicmperois | ||||||||||
This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB 29 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB 29 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK 0x20000000 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK 0xdfffffff | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET(value) (((value) & 0x20000000) >> 29) | |||||||||
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET(value) (((value) << 29) & 0x20000000) | |||||||||
Data Structures | |
struct | ALT_EMAC_GMAC_MMC_IPC_RX_INT_s |
Macros | |
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST 0x208 |
#define | ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s | ALT_EMAC_GMAC_MMC_IPC_RX_INT_t |
struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT.
Data Fields | ||
---|---|---|
const uint32_t | rxipv4gfis: 1 | MMC Receive IPV4 Good Frame Counter Interrupt Status |
const uint32_t | rxipv4herfis: 1 | MMC Receive IPV4 Header Error Frame Counter Interrupt Status |
const uint32_t | rxipv4nopayfis: 1 | MMC Receive IPV4 No Payload Frame Counter Interrupt Status |
const uint32_t | rxipv4fragfis: 1 | MMC Receive IPV4 Fragmented Frame Counter Interrupt Status |
const uint32_t | rxipv4udsblfis: 1 | MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status |
const uint32_t | rxipv6gfis: 1 | MMC Receive IPV6 Good Frame Counter Interrupt Status |
const uint32_t | rxipv6herfis: 1 | MMC Receive IPV6 Header Error Frame Counter Interrupt Status |
const uint32_t | rxipv6nopayfis: 1 | MMC Receive IPV6 No Payload Frame Counter Interrupt Status |
const uint32_t | rxudpgfis: 1 | MMC Receive UDP Good Frame Counter Interrupt Status |
const uint32_t | rxudperfis: 1 | MMC Receive UDP Error Frame Counter Interrupt Status |
const uint32_t | rxtcpgfis: 1 | MMC Receive TCP Good Frame Counter Interrupt Status |
const uint32_t | rxtcperfis: 1 | MMC Receive TCP Error Frame Counter Interrupt Status |
const uint32_t | rxicmpgfis: 1 | MMC Receive ICMP Good Frame Counter Interrupt Status |
const uint32_t | rxicmperfis: 1 | MMC Receive ICMP Error Frame Counter Interrupt Status |
uint32_t | __pad0__: 2 | UNDEFINED |
const uint32_t | rxipv4gois: 1 | MMC Receive IPV4 Good Octet Counter Interrupt Status |
const uint32_t | rxipv4herois: 1 | MMC Receive IPV4 Header Error Octet Counter Interrupt Status |
const uint32_t | rxipv4nopayois: 1 | MMC Receive IPV4 No Payload Octet Counter Interrupt Status |
const uint32_t | rxipv4fragois: 1 | MMC Receive IPV4 Fragmented Octet Counter Interrupt Status |
const uint32_t | rxipv4udsblois: 1 | MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status |
const uint32_t | rxipv6gois: 1 | MMC Receive IPV6 Good Octet Counter Interrupt Status |
const uint32_t | rxipv6herois: 1 | MMC Receive IPV6 Header Error Octet Counter Interrupt Status |
const uint32_t | rxipv6nopayois: 1 | MMC Receive IPV6 No Payload Octet Counter Interrupt Status |
const uint32_t | rxudpgois: 1 | MMC Receive UDP Good Octet Counter Interrupt Status |
const uint32_t | rxudperois: 1 | MMC Receive UDP Error Octet Counter Interrupt Status |
const uint32_t | rxtcpgois: 1 | MMC Receive TCP Good Octet Counter Interrupt Status |
const uint32_t | rxtcperois: 1 | MMC Receive TCP Error Octet Counter Interrupt Status |
const uint32_t | rxicmpgois: 1 | MMC Receive ICMP Good Octet Counter Interrupt Status |
const uint32_t | rxicmperois: 1 | MMC Receive ICMP Error Octet Counter Interrupt Status |
uint32_t | __pad1__: 2 | UNDEFINED |
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET_MSK 0x00000040 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET_MSK 0x00000200 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET_MSK 0x00000400 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET_MSK 0x00000800 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET_MSK 0x00001000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_CLR_MSK 0xffffefff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4GOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET_MSK 0x00020000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4HEROIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4NOPAYOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4FRAGOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET_MSK 0x00100000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_CLR_MSK 0xffefffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV4UDSBLOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET_MSK 0x00200000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6GOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET_MSK 0x00400000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6HEROIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET_MSK 0x00800000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_IPV6NOPAYOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPGOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_UDPEROIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET_MSK 0x04000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPGOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET_MSK 0x08000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_TCPEROIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET_MSK 0x10000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_CLR_MSK 0xefffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPGOIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_NOINT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
counter < half max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_E_INTERR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS
counter >= half max or max
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET_MSK 0x20000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_CLR_MSK 0xdfffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_GET | ( | value | ) | (((value) & 0x20000000) >> 29) |
Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS field value from a register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS_SET | ( | value | ) | (((value) << 29) & 0x20000000) |
Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_ICMPEROIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST 0x208 |
The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register from the beginning of the component.
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_OFST)) |
The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT register.
typedef struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_s ALT_EMAC_GMAC_MMC_IPC_RX_INT_t |
The typedef declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT.