Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ecc_correction

Description

Correction capability required and the Erase threshold value.

Register Layout

Bits Access Reset Description
[7:0] RW 0x8 ALT_NAND_CFG_ECC_CORRECTION_VALUE
[15:8] ??? Unknown UNDEFINED
[31:16] RW 0x0 ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD

Field : value

The required correction capability. A smaller correction capability will

lead to lesser number of ECC check-bits being written per ECC sector.

The supported ECC correction levels are -

[list]

[*] 16,8,4 over 512 bytes.

[*] 24 over 1024 bytes.

[*] All other values will cause the correction value in the controller

to fall back to the previously selected value.

[/list]

Field Access Macros:

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB   0
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB   7
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH   8
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK   0x000000ff
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK   0xffffff00
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET   0x8
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : erase_threshold

This value informs the ECC logic of the number of 0's to count

in a page before considering it as Erased. If the number of 0's in

the page being read is less than the value in this register,

an erased page is inferred and no un-correctable error will be flagged

for that page. If ECC is disabled, the erased_page interrupt shall be

set as explained above. If ECC is enabled, in addition to the above

condition, only when the ECC logic detects an un-correctable error for

that page will the erased_page interrupt be flagged. If the ECC logic

detects a no-error or correctable error page, this erased page interrupt

will not be set. A value of ZERO in this register will disabled checking for

erased pages. Erased page detection logic will be activated only in MAIN or

MAIN+SPARE or META-DATA(if available) modes of operation.

Field Access Macros:

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB   16
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB   31
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH   16
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK   0xffff0000
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK   0x0000ffff
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET   0x0
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_NAND_CFG_ECC_CORRECTION_s
 

Macros

#define ALT_NAND_CFG_ECC_CORRECTION_RESET   0x00000008
 
#define ALT_NAND_CFG_ECC_CORRECTION_OFST   0x1b0
 

Typedefs

typedef struct
ALT_NAND_CFG_ECC_CORRECTION_s 
ALT_NAND_CFG_ECC_CORRECTION_t
 

Data Structure Documentation

struct ALT_NAND_CFG_ECC_CORRECTION_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_ECC_CORRECTION.

Data Fields
uint32_t value: 8 ALT_NAND_CFG_ECC_CORRECTION_VALUE
uint32_t __pad0__: 8 UNDEFINED
uint32_t erase_threshold: 16 ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD

Macro Definitions

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB   7

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH   8

The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK   0x000000ff

The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK   0xffffff00

The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET   0x8

The reset value of the ALT_NAND_CFG_ECC_CORRECTION_VALUE register field.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_NAND_CFG_ECC_CORRECTION_VALUE field value from a register.

#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_NAND_CFG_ECC_CORRECTION_VALUE register field value suitable for setting the register.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB   16

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB   31

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH   16

The width in bits of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK   0xffff0000

The mask used to set the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK   0x0000ffff

The mask used to clear the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET   0x0

The reset value of the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD field value from a register.

#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD register field value suitable for setting the register.

#define ALT_NAND_CFG_ECC_CORRECTION_RESET   0x00000008

The reset value of the ALT_NAND_CFG_ECC_CORRECTION register.

#define ALT_NAND_CFG_ECC_CORRECTION_OFST   0x1b0

The byte offset of the ALT_NAND_CFG_ECC_CORRECTION register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_CFG_ECC_CORRECTION.