Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ctrl

Description

Contains fields that control the entire Clock Manager.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Safe Mode
[1] ??? 0x0 UNDEFINED
[2] RW 0x1 Enable SafeMode on Warm Reset
[31:3] ??? 0x0 UNDEFINED

Field : Safe Mode - safemode

When set the Clock Manager is in Safe Mode.

In Safe Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to a Safe Mode state.In Safe Mode all clocks with the optional exception of debug clocks, are directly generated from the EOSC1 clock input, all PLLs are bypassed, all programmable dividers are set to 1 and all clocks are enabled.

This bit should only be cleared when clocks have been correctly configured

This field is set on a cold reset and optionally on a warm reset and may not be set by SW.

Field Access Macros:

#define ALT_CLKMGR_CTL_SAFEMOD_LSB   0
 
#define ALT_CLKMGR_CTL_SAFEMOD_MSB   0
 
#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH   1
 
#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK   0x00000001
 
#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_CTL_SAFEMOD_RESET   0x1
 
#define ALT_CLKMGR_CTL_SAFEMOD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_CTL_SAFEMOD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Enable SafeMode on Warm Reset - ensfmdwr

When set the Clock Manager will respond to a Safe Mode request from the Reset Manager on a warm reset by setting the Safe Mode bit. When clear the clock manager will not set the the Safe Mode bit on a warm reset This bit is cleared on a cold reset. Warm reset has no affect on this bit.

Field Access Macros:

#define ALT_CLKMGR_CTL_ENSFMDWR_LSB   2
 
#define ALT_CLKMGR_CTL_ENSFMDWR_MSB   2
 
#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH   1
 
#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK   0x00000004
 
#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK   0xfffffffb
 
#define ALT_CLKMGR_CTL_ENSFMDWR_RESET   0x1
 
#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value)   (((value) << 2) & 0x00000004)
 

Data Structures

struct  ALT_CLKMGR_CTL_s
 

Macros

#define ALT_CLKMGR_CTL_OFST   0x0
 

Typedefs

typedef struct ALT_CLKMGR_CTL_s ALT_CLKMGR_CTL_t
 

Data Structure Documentation

struct ALT_CLKMGR_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_CTL.

Data Fields
uint32_t safemode: 1 Safe Mode
uint32_t __pad0__: 1 UNDEFINED
uint32_t ensfmdwr: 1 Enable SafeMode on Warm Reset
uint32_t __pad1__: 29 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_CTL_SAFEMOD_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field.

#define ALT_CLKMGR_CTL_SAFEMOD_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_SAFEMOD register field.

#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH   1

The width in bits of the ALT_CLKMGR_CTL_SAFEMOD register field.

#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_CTL_SAFEMOD register field value.

#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_CTL_SAFEMOD register field value.

#define ALT_CLKMGR_CTL_SAFEMOD_RESET   0x1

The reset value of the ALT_CLKMGR_CTL_SAFEMOD register field.

#define ALT_CLKMGR_CTL_SAFEMOD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_CTL_SAFEMOD field value from a register.

#define ALT_CLKMGR_CTL_SAFEMOD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_CTL_SAFEMOD register field value suitable for setting the register.

#define ALT_CLKMGR_CTL_ENSFMDWR_LSB   2

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field.

#define ALT_CLKMGR_CTL_ENSFMDWR_MSB   2

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CTL_ENSFMDWR register field.

#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH   1

The width in bits of the ALT_CLKMGR_CTL_ENSFMDWR register field.

#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK   0x00000004

The mask used to set the ALT_CLKMGR_CTL_ENSFMDWR register field value.

#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_CLKMGR_CTL_ENSFMDWR register field value.

#define ALT_CLKMGR_CTL_ENSFMDWR_RESET   0x1

The reset value of the ALT_CLKMGR_CTL_ENSFMDWR register field.

#define ALT_CLKMGR_CTL_ENSFMDWR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_CLKMGR_CTL_ENSFMDWR field value from a register.

#define ALT_CLKMGR_CTL_ENSFMDWR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_CLKMGR_CTL_ENSFMDWR register field value suitable for setting the register.

#define ALT_CLKMGR_CTL_OFST   0x0

The byte offset of the ALT_CLKMGR_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_CTL.