Altera SoCAL  16.0
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alt_noc_mpu_prb.h
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32 
35 #ifndef __ALT_SOCAL_NOC_MPU_PRB_H__
36 #define __ALT_SOCAL_NOC_MPU_PRB_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
72 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_LSB 0
73 
74 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_MSB 7
75 
76 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_WIDTH 8
77 
78 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
79 
80 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
81 
82 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_RESET 0x6
83 
84 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
85 
86 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
87 
97 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_LSB 8
98 
99 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_MSB 31
100 
101 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_WIDTH 24
102 
103 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
104 
105 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
106 
107 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_RESET 0x567d6
108 
109 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
110 
111 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
112 
113 #ifndef __ASSEMBLY__
114 
125 {
126  const uint32_t CORETYPEID : 8;
127  const uint32_t CORECHECKSUM : 24;
128 };
129 
132 #endif /* __ASSEMBLY__ */
133 
135 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_RESET 0x0567d606
136 
137 #define ALT_NOC_MPU_PRB_H2F_MAIN_COREID_OFST 0x0
138 
159 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_LSB 0
160 
161 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_MSB 7
162 
163 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_WIDTH 8
164 
165 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_SET_MSK 0x000000ff
166 
167 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_CLR_MSK 0xffffff00
168 
169 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_RESET 0x0
170 
171 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
172 
173 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
174 
185 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_LSB 8
186 
187 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_MSB 31
188 
189 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_WIDTH 24
190 
191 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
192 
193 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
194 
195 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_RESET 0x129ff
196 
197 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
198 
199 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
200 
201 #ifndef __ASSEMBLY__
202 
213 {
214  const uint32_t USERID : 8;
215  const uint32_t FLEXNOCID : 24;
216 };
217 
220 #endif /* __ASSEMBLY__ */
221 
223 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_RESET 0x0129ff00
224 
225 #define ALT_NOC_MPU_PRB_H2F_MAIN_REVID_OFST 0x4
226 
259 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_LSB 0
260 
261 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_MSB 0
262 
263 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_WIDTH 1
264 
265 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
266 
267 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
268 
269 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_RESET 0x0
270 
271 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
272 
273 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
274 
285 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_LSB 1
286 
287 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_MSB 1
288 
289 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_WIDTH 1
290 
291 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
292 
293 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
294 
295 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_RESET 0x0
296 
297 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
298 
299 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
300 
311 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_LSB 2
312 
313 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_MSB 2
314 
315 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_WIDTH 1
316 
317 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
318 
319 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
320 
321 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_RESET 0x0
322 
323 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
324 
325 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
326 
339 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_LSB 3
340 
341 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_MSB 3
342 
343 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_WIDTH 1
344 
345 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
346 
347 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
348 
349 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_RESET 0x0
350 
351 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
352 
353 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
354 
366 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_LSB 4
367 
368 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_MSB 4
369 
370 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_WIDTH 1
371 
372 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
373 
374 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
375 
376 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_RESET 0x0
377 
378 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
379 
380 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
381 
395 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_LSB 5
396 
397 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_MSB 5
398 
399 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
400 
401 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
402 
403 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
404 
405 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
406 
407 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
408 
409 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
410 
422 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
423 
424 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
425 
426 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
427 
428 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
429 
430 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
431 
432 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
433 
434 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
435 
436 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
437 
451 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
452 
453 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
454 
455 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
456 
457 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
458 
459 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
460 
461 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
462 
463 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
464 
465 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
466 
467 #ifndef __ASSEMBLY__
468 
479 {
480  uint32_t ERREN : 1;
481  uint32_t TRACEEN : 1;
482  uint32_t PAYLOADEN : 1;
483  uint32_t STATEN : 1;
484  uint32_t ALARMEN : 1;
485  uint32_t STATCONDDUMP : 1;
486  const uint32_t INTRUSIVEMODE : 1;
488  uint32_t : 24;
489 };
490 
493 #endif /* __ASSEMBLY__ */
494 
496 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_RESET 0x00000000
497 
498 #define ALT_NOC_MPU_PRB_H2F_MAIN_MAINCTL_OFST 0x8
499 
520 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_LSB 0
521 
522 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_MSB 0
523 
524 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_WIDTH 1
525 
526 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
527 
528 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
529 
530 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_RESET 0x0
531 
532 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
533 
534 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
535 
544 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_LSB 1
545 
546 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_MSB 1
547 
548 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_WIDTH 1
549 
550 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
551 
552 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
553 
554 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_RESET 0x0
555 
556 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
557 
558 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
559 
560 #ifndef __ASSEMBLY__
561 
572 {
573  uint32_t GLOBALEN : 1;
574  const uint32_t ACTIVE : 1;
575  uint32_t : 30;
576 };
577 
580 #endif /* __ASSEMBLY__ */
581 
583 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_RESET 0x00000000
584 
585 #define ALT_NOC_MPU_PRB_H2F_MAIN_CFGCTL_OFST 0xc
586 
611 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_LSB 0
612 
613 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_MSB 0
614 
615 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_WIDTH 1
616 
617 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET_MSK 0x00000001
618 
619 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_CLR_MSK 0xfffffffe
620 
621 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_RESET 0x0
622 
623 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_GET(value) (((value) & 0x00000001) >> 0)
624 
625 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET(value) (((value) << 0) & 0x00000001)
626 
627 #ifndef __ASSEMBLY__
628 
639 {
640  uint32_t TRACEPORTSEL : 1;
641  uint32_t : 31;
642 };
643 
646 #endif /* __ASSEMBLY__ */
647 
649 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_RESET 0x00000000
650 
651 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEPORTSEL_OFST 0x10
652 
678 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_LSB 0
679 
680 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_MSB 3
681 
682 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_WIDTH 4
683 
684 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_SET_MSK 0x0000000f
685 
686 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffff0
687 
688 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_RESET 0x0
689 
690 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000000f) >> 0)
691 
692 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000000f)
693 
694 #ifndef __ASSEMBLY__
695 
706 {
707  uint32_t FILTERLUT : 4;
708  uint32_t : 28;
709 };
710 
713 #endif /* __ASSEMBLY__ */
714 
716 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_RESET 0x00000000
717 
718 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTLUT_OFST 0x14
719 
746 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
747 
748 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 2
749 
750 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 3
751 
752 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000007
753 
754 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffff8
755 
756 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
757 
758 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000007) >> 0)
759 
760 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000007)
761 
762 #ifndef __ASSEMBLY__
763 
774 {
775  uint32_t TRACEALARMEN : 3;
776  uint32_t : 29;
777 };
778 
781 #endif /* __ASSEMBLY__ */
782 
784 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_RESET 0x00000000
785 
786 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMEN_OFST 0x18
787 
813 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
814 
815 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 2
816 
817 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 3
818 
819 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000007
820 
821 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffff8
822 
823 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
824 
825 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000007) >> 0)
826 
827 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000007)
828 
829 #ifndef __ASSEMBLY__
830 
841 {
842  const uint32_t TRACEALARMSTATUS : 3;
843  uint32_t : 29;
844 };
845 
848 #endif /* __ASSEMBLY__ */
849 
851 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_RESET 0x00000000
852 
853 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMSTAT_OFST 0x1c
854 
879 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
880 
881 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 2
882 
883 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 3
884 
885 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000007
886 
887 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffff8
888 
889 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
890 
891 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000007) >> 0)
892 
893 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000007)
894 
895 #ifndef __ASSEMBLY__
896 
907 {
908  uint32_t TRACEALARMCLR : 3;
909  uint32_t : 29;
910 };
911 
914 #endif /* __ASSEMBLY__ */
915 
917 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_RESET 0x00000000
918 
919 #define ALT_NOC_MPU_PRB_H2F_MAIN_TRACEALARMCLR_OFST 0x20
920 
949 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_LSB 0
950 
951 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_MSB 4
952 
953 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
954 
955 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
956 
957 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
958 
959 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
960 
961 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
962 
963 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
964 
965 #ifndef __ASSEMBLY__
966 
977 {
978  uint32_t STATPERIOD : 5;
979  uint32_t : 27;
980 };
981 
984 #endif /* __ASSEMBLY__ */
985 
987 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_RESET 0x00000000
988 
989 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATPERIOD_OFST 0x24
990 
1015 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_LSB 0
1016 
1017 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_MSB 0
1018 
1019 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_WIDTH 1
1020 
1021 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_SET_MSK 0x00000001
1022 
1023 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
1024 
1025 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_RESET 0x0
1026 
1027 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
1028 
1029 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
1030 
1031 #ifndef __ASSEMBLY__
1032 
1043 {
1044  uint32_t STATGO : 1;
1045  uint32_t : 31;
1046 };
1047 
1050 #endif /* __ASSEMBLY__ */
1051 
1053 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_RESET 0x00000000
1054 
1055 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATGO_OFST 0x28
1056 
1080 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
1081 
1082 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
1083 
1084 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
1085 
1086 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1087 
1088 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1089 
1090 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
1091 
1092 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1093 
1094 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1095 
1096 #ifndef __ASSEMBLY__
1097 
1108 {
1109  uint32_t STATALARMMIN : 32;
1110 };
1111 
1114 #endif /* __ASSEMBLY__ */
1115 
1117 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_RESET 0x00000000
1118 
1119 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMIN_OFST 0x2c
1120 
1144 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
1145 
1146 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
1147 
1148 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
1149 
1150 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1151 
1152 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1153 
1154 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
1155 
1156 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1157 
1158 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1159 
1160 #ifndef __ASSEMBLY__
1161 
1172 {
1173  uint32_t STATALARMMAX : 32;
1174 };
1175 
1178 #endif /* __ASSEMBLY__ */
1179 
1181 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_RESET 0x00000000
1182 
1183 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMMAX_OFST 0x30
1184 
1210 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
1211 
1212 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
1213 
1214 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
1215 
1216 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
1217 
1218 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
1219 
1220 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
1221 
1222 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
1223 
1224 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
1225 
1226 #ifndef __ASSEMBLY__
1227 
1238 {
1239  const uint32_t STATALARMSTATUS : 1;
1240  uint32_t : 31;
1241 };
1242 
1245 #endif /* __ASSEMBLY__ */
1246 
1248 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_RESET 0x00000000
1249 
1250 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMSTAT_OFST 0x34
1251 
1276 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
1277 
1278 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
1279 
1280 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
1281 
1282 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1283 
1284 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1285 
1286 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
1287 
1288 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1289 
1290 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1291 
1292 #ifndef __ASSEMBLY__
1293 
1304 {
1305  uint32_t STATALARMCLR : 1;
1306  uint32_t : 31;
1307 };
1308 
1311 #endif /* __ASSEMBLY__ */
1312 
1314 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_RESET 0x00000000
1315 
1316 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMCLR_OFST 0x38
1317 
1340 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_LSB 0
1341 
1342 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_MSB 0
1343 
1344 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
1345 
1346 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1347 
1348 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1349 
1350 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
1351 
1352 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1353 
1354 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1355 
1356 #ifndef __ASSEMBLY__
1357 
1368 {
1369  uint32_t STATALARMEN : 1;
1370  uint32_t : 31;
1371 };
1372 
1375 #endif /* __ASSEMBLY__ */
1376 
1378 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_RESET 0x00000001
1379 
1380 #define ALT_NOC_MPU_PRB_H2F_MAIN_STATALARMEN_OFST 0x3c
1381 
1404 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
1405 
1406 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
1407 
1408 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
1409 
1410 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
1411 
1412 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
1413 
1414 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
1415 
1416 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
1417 
1418 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
1419 
1420 #ifndef __ASSEMBLY__
1421 
1432 {
1433  uint32_t FILTERS_0_ROUTEIDBASE : 19;
1434  uint32_t : 13;
1435 };
1436 
1439 #endif /* __ASSEMBLY__ */
1440 
1442 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
1443 
1444 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
1445 
1469 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
1470 
1471 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
1472 
1473 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
1474 
1475 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
1476 
1477 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
1478 
1479 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
1480 
1481 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
1482 
1483 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
1484 
1485 #ifndef __ASSEMBLY__
1486 
1497 {
1498  uint32_t FILTERS_0_ROUTEIDMASK : 19;
1499  uint32_t : 13;
1500 };
1501 
1504 #endif /* __ASSEMBLY__ */
1505 
1507 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
1508 
1509 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
1510 
1531 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
1532 
1533 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
1534 
1535 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
1536 
1537 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1538 
1539 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1540 
1541 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
1542 
1543 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1544 
1545 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1546 
1547 #ifndef __ASSEMBLY__
1548 
1559 {
1560  uint32_t FILTERS_0_ADDRBASE_LOW : 32;
1561 };
1562 
1565 #endif /* __ASSEMBLY__ */
1566 
1568 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
1569 
1570 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
1571 
1597 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
1598 
1599 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
1600 
1601 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
1602 
1603 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
1604 
1605 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1606 
1607 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
1608 
1609 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1610 
1611 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1612 
1613 #ifndef __ASSEMBLY__
1614 
1625 {
1626  uint32_t FILTERS_0_WINDOWSIZE : 6;
1627  uint32_t : 26;
1628 };
1629 
1632 #endif /* __ASSEMBLY__ */
1633 
1635 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
1636 
1637 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
1638 
1660 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
1661 
1662 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
1663 
1664 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
1665 
1666 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
1667 
1668 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
1669 
1670 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
1671 
1672 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1673 
1674 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1675 
1676 #ifndef __ASSEMBLY__
1677 
1688 {
1689  uint32_t FILTERS_0_SECURITYBASE : 3;
1690  uint32_t : 29;
1691 };
1692 
1695 #endif /* __ASSEMBLY__ */
1696 
1698 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
1699 
1700 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
1701 
1725 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
1726 
1727 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
1728 
1729 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
1730 
1731 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
1732 
1733 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
1734 
1735 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
1736 
1737 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1738 
1739 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1740 
1741 #ifndef __ASSEMBLY__
1742 
1753 {
1754  uint32_t FILTERS_0_SECURITYMASK : 3;
1755  uint32_t : 29;
1756 };
1757 
1760 #endif /* __ASSEMBLY__ */
1761 
1763 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
1764 
1765 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
1766 
1793 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
1794 
1795 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
1796 
1797 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
1798 
1799 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
1800 
1801 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1802 
1803 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
1804 
1805 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1806 
1807 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1808 
1818 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_LSB 1
1819 
1820 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_MSB 1
1821 
1822 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
1823 
1824 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
1825 
1826 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1827 
1828 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
1829 
1830 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1831 
1832 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1833 
1843 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
1844 
1845 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
1846 
1847 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
1848 
1849 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1850 
1851 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1852 
1853 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
1854 
1855 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1856 
1857 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1858 
1868 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
1869 
1870 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
1871 
1872 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
1873 
1874 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
1875 
1876 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1877 
1878 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
1879 
1880 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1881 
1882 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1883 
1884 #ifndef __ASSEMBLY__
1885 
1896 {
1897  uint32_t RDEN : 1;
1898  uint32_t WREN : 1;
1899  uint32_t LOCKEN : 1;
1900  uint32_t URGEN : 1;
1901  uint32_t : 28;
1902 };
1903 
1906 #endif /* __ASSEMBLY__ */
1907 
1909 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_RESET 0x00000000
1910 
1911 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_OPCODE_OFST 0x60
1912 
1937 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_LSB 0
1938 
1939 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_MSB 0
1940 
1941 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
1942 
1943 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
1944 
1945 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
1946 
1947 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
1948 
1949 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1950 
1951 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
1952 
1962 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_LSB 1
1963 
1964 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_MSB 1
1965 
1966 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
1967 
1968 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
1969 
1970 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
1971 
1972 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
1973 
1974 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1975 
1976 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1977 
1978 #ifndef __ASSEMBLY__
1979 
1990 {
1991  uint32_t REQEN : 1;
1992  uint32_t RSPEN : 1;
1993  uint32_t : 30;
1994 };
1995 
1998 #endif /* __ASSEMBLY__ */
1999 
2001 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_RESET 0x00000000
2002 
2003 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_STAT_OFST 0x64
2004 
2027 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
2028 
2029 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
2030 
2031 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
2032 
2033 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
2034 
2035 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
2036 
2037 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
2038 
2039 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2040 
2041 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
2042 
2043 #ifndef __ASSEMBLY__
2044 
2055 {
2056  uint32_t FILTERS_0_LENGTH : 4;
2057  uint32_t : 28;
2058 };
2059 
2062 #endif /* __ASSEMBLY__ */
2063 
2065 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_RESET 0x00000000
2066 
2067 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_LEN_OFST 0x68
2068 
2092 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
2093 
2094 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
2095 
2096 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
2097 
2098 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
2099 
2100 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
2101 
2102 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
2103 
2104 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2105 
2106 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2107 
2108 #ifndef __ASSEMBLY__
2109 
2120 {
2121  uint32_t FILTERS_0_URGENCY : 2;
2122  uint32_t : 30;
2123 };
2124 
2127 #endif /* __ASSEMBLY__ */
2128 
2130 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_RESET 0x00000000
2131 
2132 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_0_URGENCY_OFST 0x6c
2133 
2156 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
2157 
2158 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
2159 
2160 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
2161 
2162 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
2163 
2164 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
2165 
2166 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
2167 
2168 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2169 
2170 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2171 
2172 #ifndef __ASSEMBLY__
2173 
2184 {
2185  uint32_t FILTERS_1_ROUTEIDBASE : 19;
2186  uint32_t : 13;
2187 };
2188 
2191 #endif /* __ASSEMBLY__ */
2192 
2194 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_RESET 0x00000000
2195 
2196 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDBASE_OFST 0x80
2197 
2221 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
2222 
2223 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
2224 
2225 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
2226 
2227 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
2228 
2229 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
2230 
2231 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
2232 
2233 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2234 
2235 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2236 
2237 #ifndef __ASSEMBLY__
2238 
2249 {
2250  uint32_t FILTERS_1_ROUTEIDMASK : 19;
2251  uint32_t : 13;
2252 };
2253 
2256 #endif /* __ASSEMBLY__ */
2257 
2259 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_RESET 0x00000000
2260 
2261 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ROUTEIDMSK_OFST 0x84
2262 
2283 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
2284 
2285 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
2286 
2287 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
2288 
2289 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2290 
2291 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2292 
2293 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
2294 
2295 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2296 
2297 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2298 
2299 #ifndef __ASSEMBLY__
2300 
2311 {
2312  uint32_t FILTERS_1_ADDRBASE_LOW : 32;
2313 };
2314 
2317 #endif /* __ASSEMBLY__ */
2318 
2320 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
2321 
2322 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_ADDRBASE_LOW_OFST 0x88
2323 
2349 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
2350 
2351 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
2352 
2353 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
2354 
2355 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
2356 
2357 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2358 
2359 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
2360 
2361 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2362 
2363 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2364 
2365 #ifndef __ASSEMBLY__
2366 
2377 {
2378  uint32_t FILTERS_1_WINDOWSIZE : 6;
2379  uint32_t : 26;
2380 };
2381 
2384 #endif /* __ASSEMBLY__ */
2385 
2387 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_RESET 0x00000000
2388 
2389 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_WINDOWSIZE_OFST 0x90
2390 
2412 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
2413 
2414 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
2415 
2416 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
2417 
2418 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
2419 
2420 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
2421 
2422 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
2423 
2424 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
2425 
2426 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
2427 
2428 #ifndef __ASSEMBLY__
2429 
2440 {
2441  uint32_t FILTERS_1_SECURITYBASE : 3;
2442  uint32_t : 29;
2443 };
2444 
2447 #endif /* __ASSEMBLY__ */
2448 
2450 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_RESET 0x00000000
2451 
2452 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYBASE_OFST 0x94
2453 
2477 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
2478 
2479 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
2480 
2481 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
2482 
2483 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
2484 
2485 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
2486 
2487 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
2488 
2489 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
2490 
2491 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
2492 
2493 #ifndef __ASSEMBLY__
2494 
2505 {
2506  uint32_t FILTERS_1_SECURITYMASK : 3;
2507  uint32_t : 29;
2508 };
2509 
2512 #endif /* __ASSEMBLY__ */
2513 
2515 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_RESET 0x00000000
2516 
2517 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_SECURITYMSK_OFST 0x98
2518 
2545 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_LSB 0
2546 
2547 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_MSB 0
2548 
2549 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_WIDTH 1
2550 
2551 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
2552 
2553 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2554 
2555 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_RESET 0x0
2556 
2557 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2558 
2559 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2560 
2570 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_LSB 1
2571 
2572 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_MSB 1
2573 
2574 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_WIDTH 1
2575 
2576 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
2577 
2578 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2579 
2580 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_RESET 0x0
2581 
2582 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2583 
2584 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2585 
2595 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_LSB 2
2596 
2597 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_MSB 2
2598 
2599 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH 1
2600 
2601 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2602 
2603 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2604 
2605 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_RESET 0x0
2606 
2607 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2608 
2609 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2610 
2620 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_LSB 3
2621 
2622 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_MSB 3
2623 
2624 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_WIDTH 1
2625 
2626 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
2627 
2628 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2629 
2630 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_RESET 0x0
2631 
2632 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2633 
2634 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2635 
2636 #ifndef __ASSEMBLY__
2637 
2648 {
2649  uint32_t RDEN : 1;
2650  uint32_t WREN : 1;
2651  uint32_t LOCKEN : 1;
2652  uint32_t URGEN : 1;
2653  uint32_t : 28;
2654 };
2655 
2658 #endif /* __ASSEMBLY__ */
2659 
2661 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RESET 0x00000000
2662 
2663 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_OFST 0x9c
2664 
2689 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_LSB 0
2690 
2691 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_MSB 0
2692 
2693 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_WIDTH 1
2694 
2695 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
2696 
2697 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
2698 
2699 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_RESET 0x0
2700 
2701 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2702 
2703 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
2704 
2714 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_LSB 1
2715 
2716 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_MSB 1
2717 
2718 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_WIDTH 1
2719 
2720 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
2721 
2722 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
2723 
2724 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_RESET 0x0
2725 
2726 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2727 
2728 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2729 
2730 #ifndef __ASSEMBLY__
2731 
2742 {
2743  uint32_t REQEN : 1;
2744  uint32_t RSPEN : 1;
2745  uint32_t : 30;
2746 };
2747 
2750 #endif /* __ASSEMBLY__ */
2751 
2753 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_RESET 0x00000000
2754 
2755 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_STAT_OFST 0xa0
2756 
2779 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_LSB 0
2780 
2781 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_MSB 3
2782 
2783 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
2784 
2785 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
2786 
2787 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
2788 
2789 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
2790 
2791 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2792 
2793 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
2794 
2795 #ifndef __ASSEMBLY__
2796 
2807 {
2808  uint32_t FILTERS_1_LENGTH : 4;
2809  uint32_t : 28;
2810 };
2811 
2814 #endif /* __ASSEMBLY__ */
2815 
2817 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_RESET 0x00000000
2818 
2819 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_LEN_OFST 0xa4
2820 
2844 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
2845 
2846 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
2847 
2848 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
2849 
2850 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
2851 
2852 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
2853 
2854 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
2855 
2856 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2857 
2858 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2859 
2860 #ifndef __ASSEMBLY__
2861 
2872 {
2873  uint32_t FILTERS_1_URGENCY : 2;
2874  uint32_t : 30;
2875 };
2876 
2879 #endif /* __ASSEMBLY__ */
2880 
2882 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_RESET 0x00000000
2883 
2884 #define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_URGENCY_OFST 0xa8
2885 
2909 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_LSB 0
2910 
2911 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_MSB 0
2912 
2913 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_WIDTH 1
2914 
2915 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET_MSK 0x00000001
2916 
2917 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_CLR_MSK 0xfffffffe
2918 
2919 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_RESET 0x0
2920 
2921 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
2922 
2923 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
2924 
2925 #ifndef __ASSEMBLY__
2926 
2937 {
2938  uint32_t COUNTERS_0_PORTSEL : 1;
2939  uint32_t : 31;
2940 };
2941 
2944 #endif /* __ASSEMBLY__ */
2945 
2947 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_RESET 0x00000000
2948 
2949 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_PORTSEL_OFST 0x134
2950 
2975 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
2976 
2977 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
2978 
2979 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
2980 
2981 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
2982 
2983 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
2984 
2985 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
2986 
2987 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
2988 
2989 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
2990 
2991 #ifndef __ASSEMBLY__
2992 
3003 {
3004  uint32_t INTEVENT : 5;
3005  uint32_t : 27;
3006 };
3007 
3010 #endif /* __ASSEMBLY__ */
3011 
3013 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_RESET 0x00000000
3014 
3015 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_SRC_OFST 0x138
3016 
3040 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
3041 
3042 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
3043 
3044 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
3045 
3046 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
3047 
3048 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
3049 
3050 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
3051 
3052 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3053 
3054 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3055 
3056 #ifndef __ASSEMBLY__
3057 
3068 {
3069  uint32_t COUNTERS_0_ALARMMODE : 2;
3070  uint32_t : 30;
3071 };
3072 
3075 #endif /* __ASSEMBLY__ */
3076 
3078 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
3079 
3080 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
3081 
3105 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
3106 
3107 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
3108 
3109 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
3110 
3111 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
3112 
3113 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
3114 
3115 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
3116 
3117 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3118 
3119 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3120 
3121 #ifndef __ASSEMBLY__
3122 
3133 {
3134  const uint32_t COUNTERS_0_VAL : 16;
3135  uint32_t : 16;
3136 };
3137 
3140 #endif /* __ASSEMBLY__ */
3141 
3143 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_RESET 0x00000000
3144 
3145 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_0_VAL_OFST 0x140
3146 
3170 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_LSB 0
3171 
3172 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_MSB 0
3173 
3174 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_WIDTH 1
3175 
3176 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET_MSK 0x00000001
3177 
3178 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_CLR_MSK 0xfffffffe
3179 
3180 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_RESET 0x0
3181 
3182 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3183 
3184 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3185 
3186 #ifndef __ASSEMBLY__
3187 
3198 {
3199  uint32_t COUNTERS_1_PORTSEL : 1;
3200  uint32_t : 31;
3201 };
3202 
3205 #endif /* __ASSEMBLY__ */
3206 
3208 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_RESET 0x00000000
3209 
3210 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_PORTSEL_OFST 0x148
3211 
3236 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
3237 
3238 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
3239 
3240 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
3241 
3242 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
3243 
3244 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
3245 
3246 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
3247 
3248 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3249 
3250 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3251 
3252 #ifndef __ASSEMBLY__
3253 
3264 {
3265  uint32_t INTEVENT : 5;
3266  uint32_t : 27;
3267 };
3268 
3271 #endif /* __ASSEMBLY__ */
3272 
3274 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_RESET 0x00000000
3275 
3276 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_SRC_OFST 0x14c
3277 
3301 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
3302 
3303 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
3304 
3305 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
3306 
3307 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
3308 
3309 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
3310 
3311 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
3312 
3313 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3314 
3315 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3316 
3317 #ifndef __ASSEMBLY__
3318 
3329 {
3330  uint32_t COUNTERS_1_ALARMMODE : 2;
3331  uint32_t : 30;
3332 };
3333 
3336 #endif /* __ASSEMBLY__ */
3337 
3339 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
3340 
3341 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
3342 
3366 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
3367 
3368 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
3369 
3370 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
3371 
3372 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
3373 
3374 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
3375 
3376 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
3377 
3378 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3379 
3380 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3381 
3382 #ifndef __ASSEMBLY__
3383 
3394 {
3395  const uint32_t COUNTERS_1_VAL : 16;
3396  uint32_t : 16;
3397 };
3398 
3401 #endif /* __ASSEMBLY__ */
3402 
3404 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_RESET 0x00000000
3405 
3406 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_1_VAL_OFST 0x154
3407 
3431 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_LSB 0
3432 
3433 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_MSB 0
3434 
3435 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_WIDTH 1
3436 
3437 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET_MSK 0x00000001
3438 
3439 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_CLR_MSK 0xfffffffe
3440 
3441 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_RESET 0x0
3442 
3443 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3444 
3445 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3446 
3447 #ifndef __ASSEMBLY__
3448 
3459 {
3460  uint32_t COUNTERS_2_PORTSEL : 1;
3461  uint32_t : 31;
3462 };
3463 
3466 #endif /* __ASSEMBLY__ */
3467 
3469 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_RESET 0x00000000
3470 
3471 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_PORTSEL_OFST 0x15c
3472 
3497 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
3498 
3499 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
3500 
3501 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
3502 
3503 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
3504 
3505 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
3506 
3507 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
3508 
3509 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3510 
3511 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3512 
3513 #ifndef __ASSEMBLY__
3514 
3525 {
3526  uint32_t INTEVENT : 5;
3527  uint32_t : 27;
3528 };
3529 
3532 #endif /* __ASSEMBLY__ */
3533 
3535 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_RESET 0x00000000
3536 
3537 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_SRC_OFST 0x160
3538 
3562 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
3563 
3564 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
3565 
3566 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
3567 
3568 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
3569 
3570 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
3571 
3572 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
3573 
3574 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3575 
3576 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3577 
3578 #ifndef __ASSEMBLY__
3579 
3590 {
3591  uint32_t COUNTERS_2_ALARMMODE : 2;
3592  uint32_t : 30;
3593 };
3594 
3597 #endif /* __ASSEMBLY__ */
3598 
3600 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
3601 
3602 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
3603 
3627 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
3628 
3629 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
3630 
3631 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
3632 
3633 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
3634 
3635 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
3636 
3637 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
3638 
3639 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3640 
3641 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3642 
3643 #ifndef __ASSEMBLY__
3644 
3655 {
3656  const uint32_t COUNTERS_2_VAL : 16;
3657  uint32_t : 16;
3658 };
3659 
3662 #endif /* __ASSEMBLY__ */
3663 
3665 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_RESET 0x00000000
3666 
3667 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_2_VAL_OFST 0x168
3668 
3692 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_LSB 0
3693 
3694 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_MSB 0
3695 
3696 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_WIDTH 1
3697 
3698 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET_MSK 0x00000001
3699 
3700 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_CLR_MSK 0xfffffffe
3701 
3702 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_RESET 0x0
3703 
3704 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
3705 
3706 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
3707 
3708 #ifndef __ASSEMBLY__
3709 
3720 {
3721  uint32_t COUNTERS_3_PORTSEL : 1;
3722  uint32_t : 31;
3723 };
3724 
3727 #endif /* __ASSEMBLY__ */
3728 
3730 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_RESET 0x00000000
3731 
3732 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_PORTSEL_OFST 0x170
3733 
3758 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
3759 
3760 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
3761 
3762 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
3763 
3764 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
3765 
3766 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
3767 
3768 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
3769 
3770 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
3771 
3772 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
3773 
3774 #ifndef __ASSEMBLY__
3775 
3786 {
3787  uint32_t INTEVENT : 5;
3788  uint32_t : 27;
3789 };
3790 
3793 #endif /* __ASSEMBLY__ */
3794 
3796 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_RESET 0x00000000
3797 
3798 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_SRC_OFST 0x174
3799 
3823 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
3824 
3825 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
3826 
3827 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
3828 
3829 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
3830 
3831 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
3832 
3833 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
3834 
3835 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
3836 
3837 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
3838 
3839 #ifndef __ASSEMBLY__
3840 
3851 {
3852  uint32_t COUNTERS_3_ALARMMODE : 2;
3853  uint32_t : 30;
3854 };
3855 
3858 #endif /* __ASSEMBLY__ */
3859 
3861 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
3862 
3863 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
3864 
3888 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
3889 
3890 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
3891 
3892 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
3893 
3894 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
3895 
3896 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
3897 
3898 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
3899 
3900 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
3901 
3902 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
3903 
3904 #ifndef __ASSEMBLY__
3905 
3916 {
3917  const uint32_t COUNTERS_3_VAL : 16;
3918  uint32_t : 16;
3919 };
3920 
3923 #endif /* __ASSEMBLY__ */
3924 
3926 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_RESET 0x00000000
3927 
3928 #define ALT_NOC_MPU_PRB_H2F_MAIN_CNTRS_3_VAL_OFST 0x17c
3929 
3930 #ifndef __ASSEMBLY__
3931 
3942 {
3959  volatile uint32_t _pad_0x40_0x43;
3963  volatile uint32_t _pad_0x50_0x53;
3971  volatile uint32_t _pad_0x70_0x7f[4];
3975  volatile uint32_t _pad_0x8c_0x8f;
3983  volatile uint32_t _pad_0xac_0x133[34];
3988  volatile uint32_t _pad_0x144_0x147;
3993  volatile uint32_t _pad_0x158_0x15b;
3998  volatile uint32_t _pad_0x16c_0x16f;
4003  volatile uint32_t _pad_0x180_0x400[160];
4004 };
4005 
4010 {
4027  volatile uint32_t _pad_0x40_0x43;
4031  volatile uint32_t _pad_0x50_0x53;
4039  volatile uint32_t _pad_0x70_0x7f[4];
4043  volatile uint32_t _pad_0x8c_0x8f;
4051  volatile uint32_t _pad_0xac_0x133[34];
4056  volatile uint32_t _pad_0x144_0x147;
4061  volatile uint32_t _pad_0x158_0x15b;
4066  volatile uint32_t _pad_0x16c_0x16f;
4071  volatile uint32_t _pad_0x180_0x400[160];
4072 };
4073 
4076 #endif /* __ASSEMBLY__ */
4077 
4103 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_LSB 0
4104 
4105 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_MSB 7
4106 
4107 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_WIDTH 8
4108 
4109 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
4110 
4111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
4112 
4113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_RESET 0x6
4114 
4115 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
4116 
4117 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
4118 
4128 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_LSB 8
4129 
4130 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_MSB 31
4131 
4132 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_WIDTH 24
4133 
4134 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
4135 
4136 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
4137 
4138 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_RESET 0xf46f63
4139 
4140 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
4141 
4142 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
4143 
4144 #ifndef __ASSEMBLY__
4145 
4156 {
4157  const uint32_t CORETYPEID : 8;
4158  const uint32_t CORECHECKSUM : 24;
4159 };
4160 
4163 #endif /* __ASSEMBLY__ */
4164 
4166 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_RESET 0xf46f6306
4167 
4168 #define ALT_NOC_MPU_PRB_EMACS_MAIN_COREID_OFST 0x0
4169 
4190 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_LSB 0
4191 
4192 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_MSB 7
4193 
4194 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_WIDTH 8
4195 
4196 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_SET_MSK 0x000000ff
4197 
4198 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_CLR_MSK 0xffffff00
4199 
4200 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_RESET 0x0
4201 
4202 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
4203 
4204 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
4205 
4216 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_LSB 8
4217 
4218 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_MSB 31
4219 
4220 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_WIDTH 24
4221 
4222 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
4223 
4224 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
4225 
4226 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_RESET 0x129ff
4227 
4228 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
4229 
4230 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
4231 
4232 #ifndef __ASSEMBLY__
4233 
4244 {
4245  const uint32_t USERID : 8;
4246  const uint32_t FLEXNOCID : 24;
4247 };
4248 
4251 #endif /* __ASSEMBLY__ */
4252 
4254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_RESET 0x0129ff00
4255 
4256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_REVID_OFST 0x4
4257 
4290 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_LSB 0
4291 
4292 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_MSB 0
4293 
4294 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_WIDTH 1
4295 
4296 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
4297 
4298 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
4299 
4300 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_RESET 0x0
4301 
4302 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
4303 
4304 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
4305 
4316 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_LSB 1
4317 
4318 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_MSB 1
4319 
4320 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_WIDTH 1
4321 
4322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
4323 
4324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
4325 
4326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_RESET 0x0
4327 
4328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
4329 
4330 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
4331 
4342 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_LSB 2
4343 
4344 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_MSB 2
4345 
4346 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_WIDTH 1
4347 
4348 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
4349 
4350 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
4351 
4352 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_RESET 0x0
4353 
4354 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
4355 
4356 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
4357 
4370 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_LSB 3
4371 
4372 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_MSB 3
4373 
4374 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_WIDTH 1
4375 
4376 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
4377 
4378 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
4379 
4380 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_RESET 0x0
4381 
4382 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
4383 
4384 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
4385 
4397 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_LSB 4
4398 
4399 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_MSB 4
4400 
4401 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_WIDTH 1
4402 
4403 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
4404 
4405 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
4406 
4407 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_RESET 0x0
4408 
4409 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
4410 
4411 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
4412 
4426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_LSB 5
4427 
4428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_MSB 5
4429 
4430 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
4431 
4432 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
4433 
4434 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
4435 
4436 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
4437 
4438 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
4439 
4440 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
4441 
4453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
4454 
4455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
4456 
4457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
4458 
4459 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
4460 
4461 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
4462 
4463 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
4464 
4465 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
4466 
4467 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
4468 
4482 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
4483 
4484 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
4485 
4486 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
4487 
4488 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
4489 
4490 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
4491 
4492 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
4493 
4494 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
4495 
4496 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
4497 
4498 #ifndef __ASSEMBLY__
4499 
4510 {
4511  uint32_t ERREN : 1;
4512  uint32_t TRACEEN : 1;
4513  uint32_t PAYLOADEN : 1;
4514  uint32_t STATEN : 1;
4515  uint32_t ALARMEN : 1;
4516  uint32_t STATCONDDUMP : 1;
4517  const uint32_t INTRUSIVEMODE : 1;
4519  uint32_t : 24;
4520 };
4521 
4524 #endif /* __ASSEMBLY__ */
4525 
4527 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_RESET 0x00000000
4528 
4529 #define ALT_NOC_MPU_PRB_EMACS_MAIN_MAINCTL_OFST 0x8
4530 
4551 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_LSB 0
4552 
4553 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_MSB 0
4554 
4555 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_WIDTH 1
4556 
4557 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
4558 
4559 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
4560 
4561 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_RESET 0x0
4562 
4563 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
4564 
4565 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
4566 
4575 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_LSB 1
4576 
4577 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_MSB 1
4578 
4579 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_WIDTH 1
4580 
4581 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
4582 
4583 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
4584 
4585 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_RESET 0x0
4586 
4587 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
4588 
4589 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
4590 
4591 #ifndef __ASSEMBLY__
4592 
4603 {
4604  uint32_t GLOBALEN : 1;
4605  const uint32_t ACTIVE : 1;
4606  uint32_t : 30;
4607 };
4608 
4611 #endif /* __ASSEMBLY__ */
4612 
4614 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_RESET 0x00000000
4615 
4616 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CFGCTL_OFST 0xc
4617 
4642 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_LSB 0
4643 
4644 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_MSB 0
4645 
4646 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_WIDTH 1
4647 
4648 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET_MSK 0x00000001
4649 
4650 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_CLR_MSK 0xfffffffe
4651 
4652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_RESET 0x0
4653 
4654 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_GET(value) (((value) & 0x00000001) >> 0)
4655 
4656 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_TRACEPORTSEL_SET(value) (((value) << 0) & 0x00000001)
4657 
4658 #ifndef __ASSEMBLY__
4659 
4670 {
4671  uint32_t TRACEPORTSEL : 1;
4672  uint32_t : 31;
4673 };
4674 
4677 #endif /* __ASSEMBLY__ */
4678 
4680 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_RESET 0x00000000
4681 
4682 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEPORTSEL_OFST 0x10
4683 
4709 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_LSB 0
4710 
4711 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_MSB 3
4712 
4713 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_WIDTH 4
4714 
4715 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_SET_MSK 0x0000000f
4716 
4717 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffff0
4718 
4719 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_RESET 0x0
4720 
4721 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000000f) >> 0)
4722 
4723 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000000f)
4724 
4725 #ifndef __ASSEMBLY__
4726 
4737 {
4738  uint32_t FILTERLUT : 4;
4739  uint32_t : 28;
4740 };
4741 
4744 #endif /* __ASSEMBLY__ */
4745 
4747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_RESET 0x00000000
4748 
4749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTLUT_OFST 0x14
4750 
4777 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
4778 
4779 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 2
4780 
4781 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 3
4782 
4783 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000007
4784 
4785 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffff8
4786 
4787 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
4788 
4789 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000007) >> 0)
4790 
4791 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000007)
4792 
4793 #ifndef __ASSEMBLY__
4794 
4805 {
4806  uint32_t TRACEALARMEN : 3;
4807  uint32_t : 29;
4808 };
4809 
4812 #endif /* __ASSEMBLY__ */
4813 
4815 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_RESET 0x00000000
4816 
4817 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMEN_OFST 0x18
4818 
4844 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
4845 
4846 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 2
4847 
4848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 3
4849 
4850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000007
4851 
4852 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffff8
4853 
4854 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
4855 
4856 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000007) >> 0)
4857 
4858 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000007)
4859 
4860 #ifndef __ASSEMBLY__
4861 
4872 {
4873  const uint32_t TRACEALARMSTATUS : 3;
4874  uint32_t : 29;
4875 };
4876 
4879 #endif /* __ASSEMBLY__ */
4880 
4882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_RESET 0x00000000
4883 
4884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMSTAT_OFST 0x1c
4885 
4910 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
4911 
4912 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 2
4913 
4914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 3
4915 
4916 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000007
4917 
4918 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffff8
4919 
4920 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
4921 
4922 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000007) >> 0)
4923 
4924 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000007)
4925 
4926 #ifndef __ASSEMBLY__
4927 
4938 {
4939  uint32_t TRACEALARMCLR : 3;
4940  uint32_t : 29;
4941 };
4942 
4945 #endif /* __ASSEMBLY__ */
4946 
4948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_RESET 0x00000000
4949 
4950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_TRACEALARMCLR_OFST 0x20
4951 
4980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_LSB 0
4981 
4982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_MSB 4
4983 
4984 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
4985 
4986 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
4987 
4988 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
4989 
4990 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
4991 
4992 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
4993 
4994 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
4995 
4996 #ifndef __ASSEMBLY__
4997 
5008 {
5009  uint32_t STATPERIOD : 5;
5010  uint32_t : 27;
5011 };
5012 
5015 #endif /* __ASSEMBLY__ */
5016 
5018 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_RESET 0x00000000
5019 
5020 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATPERIOD_OFST 0x24
5021 
5046 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_LSB 0
5047 
5048 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_MSB 0
5049 
5050 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_WIDTH 1
5051 
5052 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_SET_MSK 0x00000001
5053 
5054 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
5055 
5056 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_RESET 0x0
5057 
5058 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
5059 
5060 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
5061 
5062 #ifndef __ASSEMBLY__
5063 
5074 {
5075  uint32_t STATGO : 1;
5076  uint32_t : 31;
5077 };
5078 
5081 #endif /* __ASSEMBLY__ */
5082 
5084 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_RESET 0x00000000
5085 
5086 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATGO_OFST 0x28
5087 
5111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
5112 
5113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
5114 
5115 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
5116 
5117 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
5118 
5119 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
5120 
5121 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
5122 
5123 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
5124 
5125 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
5126 
5127 #ifndef __ASSEMBLY__
5128 
5139 {
5140  uint32_t STATALARMMIN : 32;
5141 };
5142 
5145 #endif /* __ASSEMBLY__ */
5146 
5148 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_RESET 0x00000000
5149 
5150 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMIN_OFST 0x2c
5151 
5175 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
5176 
5177 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
5178 
5179 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
5180 
5181 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
5182 
5183 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
5184 
5185 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
5186 
5187 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
5188 
5189 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
5190 
5191 #ifndef __ASSEMBLY__
5192 
5203 {
5204  uint32_t STATALARMMAX : 32;
5205 };
5206 
5209 #endif /* __ASSEMBLY__ */
5210 
5212 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_RESET 0x00000000
5213 
5214 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMMAX_OFST 0x30
5215 
5241 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
5242 
5243 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
5244 
5245 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
5246 
5247 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
5248 
5249 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
5250 
5251 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
5252 
5253 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
5254 
5255 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
5256 
5257 #ifndef __ASSEMBLY__
5258 
5269 {
5270  const uint32_t STATALARMSTATUS : 1;
5271  uint32_t : 31;
5272 };
5273 
5276 #endif /* __ASSEMBLY__ */
5277 
5279 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_RESET 0x00000000
5280 
5281 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMSTAT_OFST 0x34
5282 
5307 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
5308 
5309 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
5310 
5311 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
5312 
5313 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
5314 
5315 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
5316 
5317 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
5318 
5319 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
5320 
5321 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
5322 
5323 #ifndef __ASSEMBLY__
5324 
5335 {
5336  uint32_t STATALARMCLR : 1;
5337  uint32_t : 31;
5338 };
5339 
5342 #endif /* __ASSEMBLY__ */
5343 
5345 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_RESET 0x00000000
5346 
5347 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMCLR_OFST 0x38
5348 
5371 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_LSB 0
5372 
5373 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_MSB 0
5374 
5375 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
5376 
5377 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
5378 
5379 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
5380 
5381 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
5382 
5383 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
5384 
5385 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
5386 
5387 #ifndef __ASSEMBLY__
5388 
5399 {
5400  uint32_t STATALARMEN : 1;
5401  uint32_t : 31;
5402 };
5403 
5406 #endif /* __ASSEMBLY__ */
5407 
5409 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_RESET 0x00000001
5410 
5411 #define ALT_NOC_MPU_PRB_EMACS_MAIN_STATALARMEN_OFST 0x3c
5412 
5435 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
5436 
5437 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
5438 
5439 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
5440 
5441 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
5442 
5443 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
5444 
5445 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
5446 
5447 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
5448 
5449 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
5450 
5451 #ifndef __ASSEMBLY__
5452 
5463 {
5464  uint32_t FILTERS_0_ROUTEIDBASE : 19;
5465  uint32_t : 13;
5466 };
5467 
5470 #endif /* __ASSEMBLY__ */
5471 
5473 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
5474 
5475 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
5476 
5500 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
5501 
5502 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
5503 
5504 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
5505 
5506 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
5507 
5508 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
5509 
5510 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
5511 
5512 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
5513 
5514 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
5515 
5516 #ifndef __ASSEMBLY__
5517 
5528 {
5529  uint32_t FILTERS_0_ROUTEIDMASK : 19;
5530  uint32_t : 13;
5531 };
5532 
5535 #endif /* __ASSEMBLY__ */
5536 
5538 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
5539 
5540 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
5541 
5562 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
5563 
5564 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
5565 
5566 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
5567 
5568 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
5569 
5570 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
5571 
5572 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
5573 
5574 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
5575 
5576 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
5577 
5578 #ifndef __ASSEMBLY__
5579 
5590 {
5591  uint32_t FILTERS_0_ADDRBASE_LOW : 32;
5592 };
5593 
5596 #endif /* __ASSEMBLY__ */
5597 
5599 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
5600 
5601 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
5602 
5628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
5629 
5630 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
5631 
5632 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
5633 
5634 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
5635 
5636 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
5637 
5638 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
5639 
5640 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
5641 
5642 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
5643 
5644 #ifndef __ASSEMBLY__
5645 
5656 {
5657  uint32_t FILTERS_0_WINDOWSIZE : 6;
5658  uint32_t : 26;
5659 };
5660 
5663 #endif /* __ASSEMBLY__ */
5664 
5666 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
5667 
5668 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
5669 
5691 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
5692 
5693 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
5694 
5695 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
5696 
5697 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
5698 
5699 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
5700 
5701 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
5702 
5703 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
5704 
5705 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
5706 
5707 #ifndef __ASSEMBLY__
5708 
5719 {
5720  uint32_t FILTERS_0_SECURITYBASE : 3;
5721  uint32_t : 29;
5722 };
5723 
5726 #endif /* __ASSEMBLY__ */
5727 
5729 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
5730 
5731 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
5732 
5756 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
5757 
5758 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
5759 
5760 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
5761 
5762 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
5763 
5764 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
5765 
5766 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
5767 
5768 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
5769 
5770 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
5771 
5772 #ifndef __ASSEMBLY__
5773 
5784 {
5785  uint32_t FILTERS_0_SECURITYMASK : 3;
5786  uint32_t : 29;
5787 };
5788 
5791 #endif /* __ASSEMBLY__ */
5792 
5794 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
5795 
5796 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
5797 
5824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
5825 
5826 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
5827 
5828 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
5829 
5830 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
5831 
5832 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
5833 
5834 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
5835 
5836 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
5837 
5838 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
5839 
5849 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_LSB 1
5850 
5851 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_MSB 1
5852 
5853 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
5854 
5855 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
5856 
5857 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
5858 
5859 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
5860 
5861 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
5862 
5863 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
5864 
5874 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
5875 
5876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
5877 
5878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
5879 
5880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
5881 
5882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
5883 
5884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
5885 
5886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
5887 
5888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
5889 
5899 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
5900 
5901 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
5902 
5903 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
5904 
5905 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
5906 
5907 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
5908 
5909 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
5910 
5911 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
5912 
5913 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
5914 
5915 #ifndef __ASSEMBLY__
5916 
5927 {
5928  uint32_t RDEN : 1;
5929  uint32_t WREN : 1;
5930  uint32_t LOCKEN : 1;
5931  uint32_t URGEN : 1;
5932  uint32_t : 28;
5933 };
5934 
5937 #endif /* __ASSEMBLY__ */
5938 
5940 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_RESET 0x00000000
5941 
5942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_OPCODE_OFST 0x60
5943 
5968 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_LSB 0
5969 
5970 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_MSB 0
5971 
5972 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
5973 
5974 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
5975 
5976 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
5977 
5978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
5979 
5980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
5981 
5982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
5983 
5993 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_LSB 1
5994 
5995 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_MSB 1
5996 
5997 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
5998 
5999 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
6000 
6001 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
6002 
6003 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
6004 
6005 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
6006 
6007 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
6008 
6009 #ifndef __ASSEMBLY__
6010 
6021 {
6022  uint32_t REQEN : 1;
6023  uint32_t RSPEN : 1;
6024  uint32_t : 30;
6025 };
6026 
6029 #endif /* __ASSEMBLY__ */
6030 
6032 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_RESET 0x00000000
6033 
6034 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_STAT_OFST 0x64
6035 
6058 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
6059 
6060 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
6061 
6062 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
6063 
6064 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
6065 
6066 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
6067 
6068 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
6069 
6070 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
6071 
6072 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
6073 
6074 #ifndef __ASSEMBLY__
6075 
6086 {
6087  uint32_t FILTERS_0_LENGTH : 4;
6088  uint32_t : 28;
6089 };
6090 
6093 #endif /* __ASSEMBLY__ */
6094 
6096 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_RESET 0x00000000
6097 
6098 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_LEN_OFST 0x68
6099 
6123 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
6124 
6125 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
6126 
6127 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
6128 
6129 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
6130 
6131 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
6132 
6133 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
6134 
6135 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
6136 
6137 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
6138 
6139 #ifndef __ASSEMBLY__
6140 
6151 {
6152  uint32_t FILTERS_0_URGENCY : 2;
6153  uint32_t : 30;
6154 };
6155 
6158 #endif /* __ASSEMBLY__ */
6159 
6161 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_RESET 0x00000000
6162 
6163 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_0_URGENCY_OFST 0x6c
6164 
6187 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
6188 
6189 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
6190 
6191 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
6192 
6193 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
6194 
6195 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
6196 
6197 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
6198 
6199 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
6200 
6201 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
6202 
6203 #ifndef __ASSEMBLY__
6204 
6215 {
6216  uint32_t FILTERS_1_ROUTEIDBASE : 19;
6217  uint32_t : 13;
6218 };
6219 
6222 #endif /* __ASSEMBLY__ */
6223 
6225 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_RESET 0x00000000
6226 
6227 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDBASE_OFST 0x80
6228 
6252 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
6253 
6254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
6255 
6256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
6257 
6258 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
6259 
6260 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
6261 
6262 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
6263 
6264 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
6265 
6266 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
6267 
6268 #ifndef __ASSEMBLY__
6269 
6280 {
6281  uint32_t FILTERS_1_ROUTEIDMASK : 19;
6282  uint32_t : 13;
6283 };
6284 
6287 #endif /* __ASSEMBLY__ */
6288 
6290 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_RESET 0x00000000
6291 
6292 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ROUTEIDMSK_OFST 0x84
6293 
6314 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
6315 
6316 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
6317 
6318 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
6319 
6320 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
6321 
6322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
6323 
6324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
6325 
6326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
6327 
6328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
6329 
6330 #ifndef __ASSEMBLY__
6331 
6342 {
6343  uint32_t FILTERS_1_ADDRBASE_LOW : 32;
6344 };
6345 
6348 #endif /* __ASSEMBLY__ */
6349 
6351 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
6352 
6353 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_ADDRBASE_LOW_OFST 0x88
6354 
6380 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
6381 
6382 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
6383 
6384 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
6385 
6386 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
6387 
6388 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
6389 
6390 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
6391 
6392 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
6393 
6394 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
6395 
6396 #ifndef __ASSEMBLY__
6397 
6408 {
6409  uint32_t FILTERS_1_WINDOWSIZE : 6;
6410  uint32_t : 26;
6411 };
6412 
6415 #endif /* __ASSEMBLY__ */
6416 
6418 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_RESET 0x00000000
6419 
6420 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_WINDOWSIZE_OFST 0x90
6421 
6443 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
6444 
6445 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
6446 
6447 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
6448 
6449 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
6450 
6451 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
6452 
6453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
6454 
6455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
6456 
6457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
6458 
6459 #ifndef __ASSEMBLY__
6460 
6471 {
6472  uint32_t FILTERS_1_SECURITYBASE : 3;
6473  uint32_t : 29;
6474 };
6475 
6478 #endif /* __ASSEMBLY__ */
6479 
6481 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_RESET 0x00000000
6482 
6483 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYBASE_OFST 0x94
6484 
6508 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
6509 
6510 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
6511 
6512 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
6513 
6514 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
6515 
6516 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
6517 
6518 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
6519 
6520 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
6521 
6522 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
6523 
6524 #ifndef __ASSEMBLY__
6525 
6536 {
6537  uint32_t FILTERS_1_SECURITYMASK : 3;
6538  uint32_t : 29;
6539 };
6540 
6543 #endif /* __ASSEMBLY__ */
6544 
6546 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_RESET 0x00000000
6547 
6548 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_SECURITYMSK_OFST 0x98
6549 
6576 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_LSB 0
6577 
6578 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_MSB 0
6579 
6580 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_WIDTH 1
6581 
6582 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
6583 
6584 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
6585 
6586 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_RESET 0x0
6587 
6588 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
6589 
6590 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
6591 
6601 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_LSB 1
6602 
6603 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_MSB 1
6604 
6605 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_WIDTH 1
6606 
6607 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
6608 
6609 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
6610 
6611 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_RESET 0x0
6612 
6613 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
6614 
6615 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
6616 
6626 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_LSB 2
6627 
6628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_MSB 2
6629 
6630 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH 1
6631 
6632 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
6633 
6634 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
6635 
6636 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_RESET 0x0
6637 
6638 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
6639 
6640 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
6641 
6651 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_LSB 3
6652 
6653 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_MSB 3
6654 
6655 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_WIDTH 1
6656 
6657 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
6658 
6659 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
6660 
6661 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_RESET 0x0
6662 
6663 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
6664 
6665 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
6666 
6667 #ifndef __ASSEMBLY__
6668 
6679 {
6680  uint32_t RDEN : 1;
6681  uint32_t WREN : 1;
6682  uint32_t LOCKEN : 1;
6683  uint32_t URGEN : 1;
6684  uint32_t : 28;
6685 };
6686 
6689 #endif /* __ASSEMBLY__ */
6690 
6692 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_RESET 0x00000000
6693 
6694 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_OPCODE_OFST 0x9c
6695 
6720 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_LSB 0
6721 
6722 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_MSB 0
6723 
6724 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_WIDTH 1
6725 
6726 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
6727 
6728 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
6729 
6730 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_RESET 0x0
6731 
6732 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
6733 
6734 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
6735 
6745 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_LSB 1
6746 
6747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_MSB 1
6748 
6749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_WIDTH 1
6750 
6751 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
6752 
6753 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
6754 
6755 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_RESET 0x0
6756 
6757 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
6758 
6759 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
6760 
6761 #ifndef __ASSEMBLY__
6762 
6773 {
6774  uint32_t REQEN : 1;
6775  uint32_t RSPEN : 1;
6776  uint32_t : 30;
6777 };
6778 
6781 #endif /* __ASSEMBLY__ */
6782 
6784 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_RESET 0x00000000
6785 
6786 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_STAT_OFST 0xa0
6787 
6810 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_LSB 0
6811 
6812 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_MSB 3
6813 
6814 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
6815 
6816 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
6817 
6818 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
6819 
6820 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
6821 
6822 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
6823 
6824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
6825 
6826 #ifndef __ASSEMBLY__
6827 
6838 {
6839  uint32_t FILTERS_1_LENGTH : 4;
6840  uint32_t : 28;
6841 };
6842 
6845 #endif /* __ASSEMBLY__ */
6846 
6848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_RESET 0x00000000
6849 
6850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_LEN_OFST 0xa4
6851 
6875 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
6876 
6877 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
6878 
6879 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
6880 
6881 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
6882 
6883 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
6884 
6885 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
6886 
6887 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
6888 
6889 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
6890 
6891 #ifndef __ASSEMBLY__
6892 
6903 {
6904  uint32_t FILTERS_1_URGENCY : 2;
6905  uint32_t : 30;
6906 };
6907 
6910 #endif /* __ASSEMBLY__ */
6911 
6913 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_RESET 0x00000000
6914 
6915 #define ALT_NOC_MPU_PRB_EMACS_MAIN_FLTS_1_URGENCY_OFST 0xa8
6916 
6940 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_LSB 0
6941 
6942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_MSB 0
6943 
6944 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_WIDTH 1
6945 
6946 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET_MSK 0x00000001
6947 
6948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_CLR_MSK 0xfffffffe
6949 
6950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_RESET 0x0
6951 
6952 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
6953 
6954 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_CNTRS_0_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
6955 
6956 #ifndef __ASSEMBLY__
6957 
6968 {
6969  uint32_t COUNTERS_0_PORTSEL : 1;
6970  uint32_t : 31;
6971 };
6972 
6975 #endif /* __ASSEMBLY__ */
6976 
6978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_RESET 0x00000000
6979 
6980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_PORTSEL_OFST 0x134
6981 
7007 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
7008 
7009 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
7010 
7011 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
7012 
7013 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
7014 
7015 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
7016 
7017 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
7018 
7019 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7020 
7021 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7022 
7033 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_LSB 5
7034 
7035 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_MSB 5
7036 
7037 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_WIDTH 1
7038 
7039 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_SET_MSK 0x00000020
7040 
7041 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7042 
7043 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_RESET 0x0
7044 
7045 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7046 
7047 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7048 
7049 #ifndef __ASSEMBLY__
7050 
7061 {
7062  uint32_t INTEVENT : 5;
7063  uint32_t EXTEVENT : 1;
7064  uint32_t : 26;
7065 };
7066 
7069 #endif /* __ASSEMBLY__ */
7070 
7072 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_RESET 0x00000000
7073 
7074 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_SRC_OFST 0x138
7075 
7099 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
7100 
7101 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
7102 
7103 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
7104 
7105 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
7106 
7107 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
7108 
7109 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
7110 
7111 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7112 
7113 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7114 
7115 #ifndef __ASSEMBLY__
7116 
7127 {
7128  uint32_t COUNTERS_0_ALARMMODE : 2;
7129  uint32_t : 30;
7130 };
7131 
7134 #endif /* __ASSEMBLY__ */
7135 
7137 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
7138 
7139 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
7140 
7164 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
7165 
7166 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
7167 
7168 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
7169 
7170 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
7171 
7172 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
7173 
7174 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
7175 
7176 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7177 
7178 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7179 
7180 #ifndef __ASSEMBLY__
7181 
7192 {
7193  const uint32_t COUNTERS_0_VAL : 16;
7194  uint32_t : 16;
7195 };
7196 
7199 #endif /* __ASSEMBLY__ */
7200 
7202 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_RESET 0x00000000
7203 
7204 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_OFST 0x140
7205 
7229 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_LSB 0
7230 
7231 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_MSB 0
7232 
7233 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_WIDTH 1
7234 
7235 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET_MSK 0x00000001
7236 
7237 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_CLR_MSK 0xfffffffe
7238 
7239 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_RESET 0x0
7240 
7241 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7242 
7243 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_CNTRS_1_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7244 
7245 #ifndef __ASSEMBLY__
7246 
7257 {
7258  uint32_t COUNTERS_1_PORTSEL : 1;
7259  uint32_t : 31;
7260 };
7261 
7264 #endif /* __ASSEMBLY__ */
7265 
7267 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_RESET 0x00000000
7268 
7269 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_PORTSEL_OFST 0x148
7270 
7296 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
7297 
7298 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
7299 
7300 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
7301 
7302 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
7303 
7304 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
7305 
7306 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
7307 
7308 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7309 
7310 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7311 
7322 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_LSB 5
7323 
7324 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_MSB 5
7325 
7326 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_WIDTH 1
7327 
7328 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_SET_MSK 0x00000020
7329 
7330 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7331 
7332 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_RESET 0x0
7333 
7334 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7335 
7336 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7337 
7338 #ifndef __ASSEMBLY__
7339 
7350 {
7351  uint32_t INTEVENT : 5;
7352  uint32_t EXTEVENT : 1;
7353  uint32_t : 26;
7354 };
7355 
7358 #endif /* __ASSEMBLY__ */
7359 
7361 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_RESET 0x00000000
7362 
7363 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_SRC_OFST 0x14c
7364 
7388 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
7389 
7390 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
7391 
7392 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
7393 
7394 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
7395 
7396 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
7397 
7398 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
7399 
7400 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7401 
7402 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7403 
7404 #ifndef __ASSEMBLY__
7405 
7416 {
7417  uint32_t COUNTERS_1_ALARMMODE : 2;
7418  uint32_t : 30;
7419 };
7420 
7423 #endif /* __ASSEMBLY__ */
7424 
7426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
7427 
7428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
7429 
7453 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
7454 
7455 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
7456 
7457 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
7458 
7459 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
7460 
7461 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
7462 
7463 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
7464 
7465 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7466 
7467 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7468 
7469 #ifndef __ASSEMBLY__
7470 
7481 {
7482  const uint32_t COUNTERS_1_VAL : 16;
7483  uint32_t : 16;
7484 };
7485 
7488 #endif /* __ASSEMBLY__ */
7489 
7491 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_RESET 0x00000000
7492 
7493 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_1_VAL_OFST 0x154
7494 
7518 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_LSB 0
7519 
7520 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_MSB 0
7521 
7522 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_WIDTH 1
7523 
7524 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET_MSK 0x00000001
7525 
7526 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_CLR_MSK 0xfffffffe
7527 
7528 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_RESET 0x0
7529 
7530 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7531 
7532 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_CNTRS_2_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7533 
7534 #ifndef __ASSEMBLY__
7535 
7546 {
7547  uint32_t COUNTERS_2_PORTSEL : 1;
7548  uint32_t : 31;
7549 };
7550 
7553 #endif /* __ASSEMBLY__ */
7554 
7556 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_RESET 0x00000000
7557 
7558 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_PORTSEL_OFST 0x15c
7559 
7585 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
7586 
7587 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
7588 
7589 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
7590 
7591 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
7592 
7593 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
7594 
7595 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
7596 
7597 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7598 
7599 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7600 
7611 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_LSB 5
7612 
7613 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_MSB 5
7614 
7615 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_WIDTH 1
7616 
7617 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_SET_MSK 0x00000020
7618 
7619 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7620 
7621 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_RESET 0x0
7622 
7623 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7624 
7625 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7626 
7627 #ifndef __ASSEMBLY__
7628 
7639 {
7640  uint32_t INTEVENT : 5;
7641  uint32_t EXTEVENT : 1;
7642  uint32_t : 26;
7643 };
7644 
7647 #endif /* __ASSEMBLY__ */
7648 
7650 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_RESET 0x00000000
7651 
7652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_SRC_OFST 0x160
7653 
7677 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
7678 
7679 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
7680 
7681 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
7682 
7683 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
7684 
7685 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
7686 
7687 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
7688 
7689 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7690 
7691 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7692 
7693 #ifndef __ASSEMBLY__
7694 
7705 {
7706  uint32_t COUNTERS_2_ALARMMODE : 2;
7707  uint32_t : 30;
7708 };
7709 
7712 #endif /* __ASSEMBLY__ */
7713 
7715 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
7716 
7717 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
7718 
7742 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
7743 
7744 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
7745 
7746 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
7747 
7748 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
7749 
7750 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
7751 
7752 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
7753 
7754 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
7755 
7756 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
7757 
7758 #ifndef __ASSEMBLY__
7759 
7770 {
7771  const uint32_t COUNTERS_2_VAL : 16;
7772  uint32_t : 16;
7773 };
7774 
7777 #endif /* __ASSEMBLY__ */
7778 
7780 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_RESET 0x00000000
7781 
7782 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_2_VAL_OFST 0x168
7783 
7807 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_LSB 0
7808 
7809 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_MSB 0
7810 
7811 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_WIDTH 1
7812 
7813 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET_MSK 0x00000001
7814 
7815 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_CLR_MSK 0xfffffffe
7816 
7817 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_RESET 0x0
7818 
7819 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_GET(value) (((value) & 0x00000001) >> 0)
7820 
7821 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_CNTRS_3_PORTSEL_SET(value) (((value) << 0) & 0x00000001)
7822 
7823 #ifndef __ASSEMBLY__
7824 
7835 {
7836  uint32_t COUNTERS_3_PORTSEL : 1;
7837  uint32_t : 31;
7838 };
7839 
7842 #endif /* __ASSEMBLY__ */
7843 
7845 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_RESET 0x00000000
7846 
7847 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_PORTSEL_OFST 0x170
7848 
7874 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
7875 
7876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
7877 
7878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
7879 
7880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
7881 
7882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
7883 
7884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
7885 
7886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
7887 
7888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
7889 
7900 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_LSB 5
7901 
7902 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_MSB 5
7903 
7904 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_WIDTH 1
7905 
7906 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_SET_MSK 0x00000020
7907 
7908 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_CLR_MSK 0xffffffdf
7909 
7910 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_RESET 0x0
7911 
7912 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_GET(value) (((value) & 0x00000020) >> 5)
7913 
7914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_EXTEVENT_SET(value) (((value) << 5) & 0x00000020)
7915 
7916 #ifndef __ASSEMBLY__
7917 
7928 {
7929  uint32_t INTEVENT : 5;
7930  uint32_t EXTEVENT : 1;
7931  uint32_t : 26;
7932 };
7933 
7936 #endif /* __ASSEMBLY__ */
7937 
7939 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_RESET 0x00000000
7940 
7941 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_SRC_OFST 0x174
7942 
7966 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
7967 
7968 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
7969 
7970 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
7971 
7972 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
7973 
7974 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
7975 
7976 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
7977 
7978 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
7979 
7980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
7981 
7982 #ifndef __ASSEMBLY__
7983 
7994 {
7995  uint32_t COUNTERS_3_ALARMMODE : 2;
7996  uint32_t : 30;
7997 };
7998 
8001 #endif /* __ASSEMBLY__ */
8002 
8004 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
8005 
8006 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
8007 
8031 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
8032 
8033 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
8034 
8035 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
8036 
8037 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
8038 
8039 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
8040 
8041 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
8042 
8043 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
8044 
8045 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
8046 
8047 #ifndef __ASSEMBLY__
8048 
8059 {
8060  const uint32_t COUNTERS_3_VAL : 16;
8061  uint32_t : 16;
8062 };
8063 
8066 #endif /* __ASSEMBLY__ */
8067 
8069 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_RESET 0x00000000
8070 
8071 #define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_3_VAL_OFST 0x17c
8072 
8073 #ifndef __ASSEMBLY__
8074 
8085 {
8102  volatile uint32_t _pad_0x40_0x43;
8106  volatile uint32_t _pad_0x50_0x53;
8114  volatile uint32_t _pad_0x70_0x7f[4];
8118  volatile uint32_t _pad_0x8c_0x8f;
8126  volatile uint32_t _pad_0xac_0x133[34];
8131  volatile uint32_t _pad_0x144_0x147;
8136  volatile uint32_t _pad_0x158_0x15b;
8141  volatile uint32_t _pad_0x16c_0x16f;
8146  volatile uint32_t _pad_0x180_0x400[160];
8147 };
8148 
8153 {
8157  volatile uint32_t Probe_emacs_main_Probe_CfgCtl;
8164  volatile uint32_t Probe_emacs_main_Probe_StatGo;
8170  volatile uint32_t _pad_0x40_0x43;
8174  volatile uint32_t _pad_0x50_0x53;
8182  volatile uint32_t _pad_0x70_0x7f[4];
8186  volatile uint32_t _pad_0x8c_0x8f;
8194  volatile uint32_t _pad_0xac_0x133[34];
8199  volatile uint32_t _pad_0x144_0x147;
8204  volatile uint32_t _pad_0x158_0x15b;
8209  volatile uint32_t _pad_0x16c_0x16f;
8214  volatile uint32_t _pad_0x180_0x400[160];
8215 };
8216 
8219 #endif /* __ASSEMBLY__ */
8220 
8246 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_LSB 0
8247 
8248 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_MSB 7
8249 
8250 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_WIDTH 8
8251 
8252 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_SET_MSK 0x000000ff
8253 
8254 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_CLR_MSK 0xffffff00
8255 
8256 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_RESET 0xa
8257 
8258 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
8259 
8260 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
8261 
8271 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_LSB 8
8272 
8273 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_MSB 31
8274 
8275 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_WIDTH 24
8276 
8277 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_SET_MSK 0xffffff00
8278 
8279 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_CLR_MSK 0x000000ff
8280 
8281 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_RESET 0xa6b796
8282 
8283 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
8284 
8285 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
8286 
8287 #ifndef __ASSEMBLY__
8288 
8299 {
8300  const uint32_t CORETYPEID : 8;
8301  const uint32_t CORECHECKSUM : 24;
8302 };
8303 
8306 #endif /* __ASSEMBLY__ */
8307 
8309 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_RESET 0xa6b7960a
8310 
8311 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_COREID_OFST 0x0
8312 
8333 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_LSB 0
8334 
8335 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_MSB 7
8336 
8337 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_WIDTH 8
8338 
8339 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_SET_MSK 0x000000ff
8340 
8341 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_CLR_MSK 0xffffff00
8342 
8343 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_RESET 0x0
8344 
8345 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
8346 
8347 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
8348 
8359 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_LSB 8
8360 
8361 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_MSB 31
8362 
8363 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_WIDTH 24
8364 
8365 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_SET_MSK 0xffffff00
8366 
8367 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_CLR_MSK 0x000000ff
8368 
8369 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_RESET 0x129ff
8370 
8371 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
8372 
8373 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
8374 
8375 #ifndef __ASSEMBLY__
8376 
8387 {
8388  const uint32_t USERID : 8;
8389  const uint32_t FLEXNOCID : 24;
8390 };
8391 
8394 #endif /* __ASSEMBLY__ */
8395 
8397 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_RESET 0x0129ff00
8398 
8399 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_REVID_OFST 0x4
8400 
8422 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_LSB 0
8423 
8424 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_MSB 0
8425 
8426 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_WIDTH 1
8427 
8428 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_SET_MSK 0x00000001
8429 
8430 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_CLR_MSK 0xfffffffe
8431 
8432 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_RESET 0x0
8433 
8434 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
8435 
8436 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_EN_SET(value) (((value) << 0) & 0x00000001)
8437 
8438 #ifndef __ASSEMBLY__
8439 
8450 {
8451  uint32_t EN : 1;
8452  uint32_t : 31;
8453 };
8454 
8457 #endif /* __ASSEMBLY__ */
8458 
8460 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_RESET 0x00000000
8461 
8462 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_EN_OFST 0x8
8463 
8486 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_LSB 0
8487 
8488 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_MSB 0
8489 
8490 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_WIDTH 1
8491 
8492 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_SET_MSK 0x00000001
8493 
8494 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_CLR_MSK 0xfffffffe
8495 
8496 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_RESET 0x0
8497 
8498 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_GET(value) (((value) & 0x00000001) >> 0)
8499 
8500 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_MOD_SET(value) (((value) << 0) & 0x00000001)
8501 
8502 #ifndef __ASSEMBLY__
8503 
8514 {
8515  uint32_t MODE : 1;
8516  uint32_t : 31;
8517 };
8518 
8521 #endif /* __ASSEMBLY__ */
8522 
8524 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_RESET 0x00000000
8525 
8526 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_MOD_OFST 0xc
8527 
8550 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_LSB 0
8551 
8552 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_MSB 1
8553 
8554 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_WIDTH 2
8555 
8556 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SET_MSK 0x00000003
8557 
8558 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_CLR_MSK 0xfffffffc
8559 
8560 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_RESET 0x0
8561 
8562 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_GET(value) (((value) & 0x00000003) >> 0)
8563 
8564 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_THRESHOLDS_0_0_SET(value) (((value) << 0) & 0x00000003)
8565 
8566 #ifndef __ASSEMBLY__
8567 
8578 {
8579  uint32_t THRESHOLDS_0_0 : 2;
8580  uint32_t : 30;
8581 };
8582 
8585 #endif /* __ASSEMBLY__ */
8586 
8588 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_RESET 0x00000000
8589 
8590 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_0_OFST 0x2c
8591 
8614 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_LSB 0
8615 
8616 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_MSB 1
8617 
8618 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_WIDTH 2
8619 
8620 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SET_MSK 0x00000003
8621 
8622 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_CLR_MSK 0xfffffffc
8623 
8624 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_RESET 0x0
8625 
8626 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_GET(value) (((value) & 0x00000003) >> 0)
8627 
8628 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_THRESHOLDS_0_1_SET(value) (((value) << 0) & 0x00000003)
8629 
8630 #ifndef __ASSEMBLY__
8631 
8642 {
8643  uint32_t THRESHOLDS_0_1 : 2;
8644  uint32_t : 30;
8645 };
8646 
8649 #endif /* __ASSEMBLY__ */
8650 
8652 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_RESET 0x00000000
8653 
8654 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_1_OFST 0x30
8655 
8678 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_LSB 0
8679 
8680 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_MSB 1
8681 
8682 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_WIDTH 2
8683 
8684 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SET_MSK 0x00000003
8685 
8686 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_CLR_MSK 0xfffffffc
8687 
8688 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_RESET 0x0
8689 
8690 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_GET(value) (((value) & 0x00000003) >> 0)
8691 
8692 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_THRESHOLDS_0_2_SET(value) (((value) << 0) & 0x00000003)
8693 
8694 #ifndef __ASSEMBLY__
8695 
8706 {
8707  uint32_t THRESHOLDS_0_2 : 2;
8708  uint32_t : 30;
8709 };
8710 
8713 #endif /* __ASSEMBLY__ */
8714 
8716 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_RESET 0x00000000
8717 
8718 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_THRESHOLDS_0_2_OFST 0x34
8719 
8745 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_LSB 0
8746 
8747 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_MSB 0
8748 
8749 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_WIDTH 1
8750 
8751 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_SET_MSK 0x00000001
8752 
8753 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_CLR_MSK 0xfffffffe
8754 
8755 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_RESET 0x0
8756 
8757 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_GET(value) (((value) & 0x00000001) >> 0)
8758 
8759 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OVFSTAT_SET(value) (((value) << 0) & 0x00000001)
8760 
8761 #ifndef __ASSEMBLY__
8762 
8773 {
8774  const uint32_t OVERFLOWSTATUS : 1;
8775  uint32_t : 31;
8776 };
8777 
8780 #endif /* __ASSEMBLY__ */
8781 
8783 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_RESET 0x00000000
8784 
8785 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFSTAT_OFST 0x6c
8786 
8810 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_LSB 0
8811 
8812 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_MSB 0
8813 
8814 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_WIDTH 1
8815 
8816 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_SET_MSK 0x00000001
8817 
8818 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_CLR_MSK 0xfffffffe
8819 
8820 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_RESET 0x0
8821 
8822 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_GET(value) (((value) & 0x00000001) >> 0)
8823 
8824 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OVFRST_SET(value) (((value) << 0) & 0x00000001)
8825 
8826 #ifndef __ASSEMBLY__
8827 
8838 {
8839  uint32_t OVERFLOWRESET : 1;
8840  uint32_t : 31;
8841 };
8842 
8845 #endif /* __ASSEMBLY__ */
8846 
8848 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_RESET 0x00000000
8849 
8850 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_OVFRST_OFST 0x70
8851 
8876 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_LSB 0
8877 
8878 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_MSB 0
8879 
8880 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_WIDTH 1
8881 
8882 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_SET_MSK 0x00000001
8883 
8884 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_CLR_MSK 0xfffffffe
8885 
8886 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_RESET 0x0
8887 
8888 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_GET(value) (((value) & 0x00000001) >> 0)
8889 
8890 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_PENDINGEVENTMOD_SET(value) (((value) << 0) & 0x00000001)
8891 
8892 #ifndef __ASSEMBLY__
8893 
8904 {
8905  uint32_t PENDINGEVENTMODE : 1;
8906  uint32_t : 31;
8907 };
8908 
8911 #endif /* __ASSEMBLY__ */
8912 
8914 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_RESET 0x00000000
8915 
8916 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PENDINGEVENTMOD_OFST 0x74
8917 
8942 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_LSB 0
8943 
8944 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_MSB 7
8945 
8946 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_WIDTH 8
8947 
8948 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_SET_MSK 0x000000ff
8949 
8950 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_CLR_MSK 0xffffff00
8951 
8952 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_RESET 0x0
8953 
8954 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_GET(value) (((value) & 0x000000ff) >> 0)
8955 
8956 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_PRESCALER_SET(value) (((value) << 0) & 0x000000ff)
8957 
8958 #ifndef __ASSEMBLY__
8959 
8970 {
8971  uint32_t PRESCALER : 8;
8972  uint32_t : 24;
8973 };
8974 
8977 #endif /* __ASSEMBLY__ */
8978 
8980 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_RESET 0x00000000
8981 
8982 #define ALT_NOC_MPU_PRB_EMACS_MAIN_XACTSTATPROFILER_PRESCALER_OFST 0x78
8983 
8984 #ifndef __ASSEMBLY__
8985 
8996 {
9001  volatile uint32_t _pad_0x10_0x2b[7];
9005  volatile uint32_t _pad_0x38_0x6b[13];
9010  volatile uint32_t _pad_0x7c_0x80;
9011 };
9012 
9017 {
9022  volatile uint32_t _pad_0x10_0x2b[7];
9026  volatile uint32_t _pad_0x38_0x6b[13];
9031  volatile uint32_t _pad_0x7c_0x80;
9032 };
9033 
9036 #endif /* __ASSEMBLY__ */
9037 
9063 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_LSB 0
9064 
9065 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_MSB 7
9066 
9067 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_WIDTH 8
9068 
9069 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_SET_MSK 0x000000ff
9070 
9071 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_CLR_MSK 0xffffff00
9072 
9073 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_RESET 0x6
9074 
9075 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
9076 
9077 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
9078 
9088 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_LSB 8
9089 
9090 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_MSB 31
9091 
9092 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_WIDTH 24
9093 
9094 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_SET_MSK 0xffffff00
9095 
9096 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_CLR_MSK 0x000000ff
9097 
9098 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_RESET 0xc7360b
9099 
9100 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
9101 
9102 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
9103 
9104 #ifndef __ASSEMBLY__
9105 
9116 {
9117  const uint32_t CORETYPEID : 8;
9118  const uint32_t CORECHECKSUM : 24;
9119 };
9120 
9123 #endif /* __ASSEMBLY__ */
9124 
9126 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_RESET 0xc7360b06
9127 
9128 #define ALT_NOC_MPU_PRB_MPU_MAIN_COREID_OFST 0x0
9129 
9150 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_LSB 0
9151 
9152 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_MSB 7
9153 
9154 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_WIDTH 8
9155 
9156 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_SET_MSK 0x000000ff
9157 
9158 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_CLR_MSK 0xffffff00
9159 
9160 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_RESET 0x0
9161 
9162 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
9163 
9164 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
9165 
9176 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_LSB 8
9177 
9178 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_MSB 31
9179 
9180 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_WIDTH 24
9181 
9182 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_SET_MSK 0xffffff00
9183 
9184 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_CLR_MSK 0x000000ff
9185 
9186 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_RESET 0x129ff
9187 
9188 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
9189 
9190 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
9191 
9192 #ifndef __ASSEMBLY__
9193 
9204 {
9205  const uint32_t USERID : 8;
9206  const uint32_t FLEXNOCID : 24;
9207 };
9208 
9211 #endif /* __ASSEMBLY__ */
9212 
9214 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_RESET 0x0129ff00
9215 
9216 #define ALT_NOC_MPU_PRB_MPU_MAIN_REVID_OFST 0x4
9217 
9250 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_LSB 0
9251 
9252 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_MSB 0
9253 
9254 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_WIDTH 1
9255 
9256 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_SET_MSK 0x00000001
9257 
9258 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_CLR_MSK 0xfffffffe
9259 
9260 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_RESET 0x0
9261 
9262 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
9263 
9264 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
9265 
9276 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_LSB 1
9277 
9278 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_MSB 1
9279 
9280 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_WIDTH 1
9281 
9282 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_SET_MSK 0x00000002
9283 
9284 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
9285 
9286 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_RESET 0x0
9287 
9288 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
9289 
9290 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
9291 
9302 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_LSB 2
9303 
9304 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_MSB 2
9305 
9306 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_WIDTH 1
9307 
9308 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_SET_MSK 0x00000004
9309 
9310 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
9311 
9312 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_RESET 0x0
9313 
9314 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
9315 
9316 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
9317 
9330 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_LSB 3
9331 
9332 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_MSB 3
9333 
9334 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_WIDTH 1
9335 
9336 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_SET_MSK 0x00000008
9337 
9338 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_CLR_MSK 0xfffffff7
9339 
9340 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_RESET 0x0
9341 
9342 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
9343 
9344 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
9345 
9357 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_LSB 4
9358 
9359 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_MSB 4
9360 
9361 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_WIDTH 1
9362 
9363 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_SET_MSK 0x00000010
9364 
9365 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
9366 
9367 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_RESET 0x0
9368 
9369 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
9370 
9371 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
9372 
9386 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_LSB 5
9387 
9388 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_MSB 5
9389 
9390 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_WIDTH 1
9391 
9392 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
9393 
9394 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
9395 
9396 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_RESET 0x0
9397 
9398 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
9399 
9400 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
9401 
9413 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_LSB 6
9414 
9415 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_MSB 6
9416 
9417 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_WIDTH 1
9418 
9419 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
9420 
9421 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
9422 
9423 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_RESET 0x0
9424 
9425 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
9426 
9427 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
9428 
9442 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
9443 
9444 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
9445 
9446 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
9447 
9448 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
9449 
9450 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
9451 
9452 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
9453 
9454 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
9455 
9456 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
9457 
9458 #ifndef __ASSEMBLY__
9459 
9470 {
9471  uint32_t ERREN : 1;
9472  uint32_t TRACEEN : 1;
9473  uint32_t PAYLOADEN : 1;
9474  uint32_t STATEN : 1;
9475  uint32_t ALARMEN : 1;
9476  uint32_t STATCONDDUMP : 1;
9477  const uint32_t INTRUSIVEMODE : 1;
9479  uint32_t : 24;
9480 };
9481 
9484 #endif /* __ASSEMBLY__ */
9485 
9487 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_RESET 0x00000000
9488 
9489 #define ALT_NOC_MPU_PRB_MPU_MAIN_MAINCTL_OFST 0x8
9490 
9511 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_LSB 0
9512 
9513 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_MSB 0
9514 
9515 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_WIDTH 1
9516 
9517 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_SET_MSK 0x00000001
9518 
9519 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
9520 
9521 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_RESET 0x0
9522 
9523 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
9524 
9525 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
9526 
9535 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_LSB 1
9536 
9537 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_MSB 1
9538 
9539 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_WIDTH 1
9540 
9541 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_SET_MSK 0x00000002
9542 
9543 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_CLR_MSK 0xfffffffd
9544 
9545 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_RESET 0x0
9546 
9547 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
9548 
9549 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
9550 
9551 #ifndef __ASSEMBLY__
9552 
9563 {
9564  uint32_t GLOBALEN : 1;
9565  const uint32_t ACTIVE : 1;
9566  uint32_t : 30;
9567 };
9568 
9571 #endif /* __ASSEMBLY__ */
9572 
9574 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_RESET 0x00000000
9575 
9576 #define ALT_NOC_MPU_PRB_MPU_MAIN_CFGCTL_OFST 0xc
9577 
9603 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_LSB 0
9604 
9605 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_MSB 1
9606 
9607 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_WIDTH 2
9608 
9609 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_SET_MSK 0x00000003
9610 
9611 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_CLR_MSK 0xfffffffc
9612 
9613 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_RESET 0x0
9614 
9615 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_GET(value) (((value) & 0x00000003) >> 0)
9616 
9617 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x00000003)
9618 
9619 #ifndef __ASSEMBLY__
9620 
9631 {
9632  uint32_t FILTERLUT : 2;
9633  uint32_t : 30;
9634 };
9635 
9638 #endif /* __ASSEMBLY__ */
9639 
9641 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_RESET 0x00000000
9642 
9643 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTLUT_OFST 0x14
9644 
9671 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_LSB 0
9672 
9673 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_MSB 1
9674 
9675 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_WIDTH 2
9676 
9677 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x00000003
9678 
9679 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xfffffffc
9680 
9681 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_RESET 0x0
9682 
9683 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x00000003) >> 0)
9684 
9685 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x00000003)
9686 
9687 #ifndef __ASSEMBLY__
9688 
9699 {
9700  uint32_t TRACEALARMEN : 2;
9701  uint32_t : 30;
9702 };
9703 
9706 #endif /* __ASSEMBLY__ */
9707 
9709 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_RESET 0x00000000
9710 
9711 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMEN_OFST 0x18
9712 
9738 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
9739 
9740 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_MSB 1
9741 
9742 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 2
9743 
9744 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x00000003
9745 
9746 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xfffffffc
9747 
9748 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
9749 
9750 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x00000003) >> 0)
9751 
9752 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x00000003)
9753 
9754 #ifndef __ASSEMBLY__
9755 
9766 {
9767  const uint32_t TRACEALARMSTATUS : 2;
9768  uint32_t : 30;
9769 };
9770 
9773 #endif /* __ASSEMBLY__ */
9774 
9776 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_RESET 0x00000000
9777 
9778 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMSTAT_OFST 0x1c
9779 
9804 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_LSB 0
9805 
9806 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_MSB 1
9807 
9808 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_WIDTH 2
9809 
9810 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x00000003
9811 
9812 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xfffffffc
9813 
9814 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
9815 
9816 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x00000003) >> 0)
9817 
9818 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x00000003)
9819 
9820 #ifndef __ASSEMBLY__
9821 
9832 {
9833  uint32_t TRACEALARMCLR : 2;
9834  uint32_t : 30;
9835 };
9836 
9839 #endif /* __ASSEMBLY__ */
9840 
9842 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_RESET 0x00000000
9843 
9844 #define ALT_NOC_MPU_PRB_MPU_MAIN_TRACEALARMCLR_OFST 0x20
9845 
9874 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_LSB 0
9875 
9876 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_MSB 4
9877 
9878 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_WIDTH 5
9879 
9880 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
9881 
9882 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
9883 
9884 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_RESET 0x0
9885 
9886 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
9887 
9888 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
9889 
9890 #ifndef __ASSEMBLY__
9891 
9902 {
9903  uint32_t STATPERIOD : 5;
9904  uint32_t : 27;
9905 };
9906 
9909 #endif /* __ASSEMBLY__ */
9910 
9912 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_RESET 0x00000000
9913 
9914 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATPERIOD_OFST 0x24
9915 
9940 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_LSB 0
9941 
9942 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_MSB 0
9943 
9944 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_WIDTH 1
9945 
9946 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_SET_MSK 0x00000001
9947 
9948 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_CLR_MSK 0xfffffffe
9949 
9950 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_RESET 0x0
9951 
9952 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
9953 
9954 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
9955 
9956 #ifndef __ASSEMBLY__
9957 
9968 {
9969  uint32_t STATGO : 1;
9970  uint32_t : 31;
9971 };
9972 
9975 #endif /* __ASSEMBLY__ */
9976 
9978 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_RESET 0x00000000
9979 
9980 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATGO_OFST 0x28
9981 
10005 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_LSB 0
10006 
10007 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_MSB 31
10008 
10009 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_WIDTH 32
10010 
10011 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
10012 
10013 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
10014 
10015 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_RESET 0x0
10016 
10017 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
10018 
10019 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
10020 
10021 #ifndef __ASSEMBLY__
10022 
10033 {
10034  uint32_t STATALARMMIN : 32;
10035 };
10036 
10039 #endif /* __ASSEMBLY__ */
10040 
10042 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_RESET 0x00000000
10043 
10044 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMIN_OFST 0x2c
10045 
10069 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_LSB 0
10070 
10071 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_MSB 31
10072 
10073 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_WIDTH 32
10074 
10075 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
10076 
10077 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
10078 
10079 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_RESET 0x0
10080 
10081 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
10082 
10083 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
10084 
10085 #ifndef __ASSEMBLY__
10086 
10097 {
10098  uint32_t STATALARMMAX : 32;
10099 };
10100 
10103 #endif /* __ASSEMBLY__ */
10104 
10106 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_RESET 0x00000000
10107 
10108 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMMAX_OFST 0x30
10109 
10135 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_LSB 0
10136 
10137 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_MSB 0
10138 
10139 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_WIDTH 1
10140 
10141 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
10142 
10143 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
10144 
10145 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_RESET 0x0
10146 
10147 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
10148 
10149 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
10150 
10151 #ifndef __ASSEMBLY__
10152 
10163 {
10164  const uint32_t STATALARMSTATUS : 1;
10165  uint32_t : 31;
10166 };
10167 
10170 #endif /* __ASSEMBLY__ */
10171 
10173 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_RESET 0x00000000
10174 
10175 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMSTAT_OFST 0x34
10176 
10201 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_LSB 0
10202 
10203 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_MSB 0
10204 
10205 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_WIDTH 1
10206 
10207 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
10208 
10209 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
10210 
10211 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_RESET 0x0
10212 
10213 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
10214 
10215 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
10216 
10217 #ifndef __ASSEMBLY__
10218 
10229 {
10230  uint32_t STATALARMCLR : 1;
10231  uint32_t : 31;
10232 };
10233 
10236 #endif /* __ASSEMBLY__ */
10237 
10239 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_RESET 0x00000000
10240 
10241 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMCLR_OFST 0x38
10242 
10265 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_LSB 0
10266 
10267 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_MSB 0
10268 
10269 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_WIDTH 1
10270 
10271 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
10272 
10273 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
10274 
10275 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_RESET 0x1
10276 
10277 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
10278 
10279 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
10280 
10281 #ifndef __ASSEMBLY__
10282 
10293 {
10294  uint32_t STATALARMEN : 1;
10295  uint32_t : 31;
10296 };
10297 
10300 #endif /* __ASSEMBLY__ */
10301 
10303 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_RESET 0x00000001
10304 
10305 #define ALT_NOC_MPU_PRB_MPU_MAIN_STATALARMEN_OFST 0x3c
10306 
10329 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
10330 
10331 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
10332 
10333 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
10334 
10335 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
10336 
10337 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
10338 
10339 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
10340 
10341 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
10342 
10343 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
10344 
10345 #ifndef __ASSEMBLY__
10346 
10357 {
10358  uint32_t FILTERS_0_ROUTEIDBASE : 19;
10359  uint32_t : 13;
10360 };
10361 
10364 #endif /* __ASSEMBLY__ */
10365 
10367 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_RESET 0x00000000
10368 
10369 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDBASE_OFST 0x44
10370 
10394 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
10395 
10396 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
10397 
10398 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
10399 
10400 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
10401 
10402 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
10403 
10404 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
10405 
10406 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
10407 
10408 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
10409 
10410 #ifndef __ASSEMBLY__
10411 
10422 {
10423  uint32_t FILTERS_0_ROUTEIDMASK : 19;
10424  uint32_t : 13;
10425 };
10426 
10429 #endif /* __ASSEMBLY__ */
10430 
10432 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_RESET 0x00000000
10433 
10434 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ROUTEIDMSK_OFST 0x48
10435 
10456 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
10457 
10458 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
10459 
10460 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
10461 
10462 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
10463 
10464 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
10465 
10466 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
10467 
10468 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
10469 
10470 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
10471 
10472 #ifndef __ASSEMBLY__
10473 
10484 {
10485  uint32_t FILTERS_0_ADDRBASE_LOW : 32;
10486 };
10487 
10490 #endif /* __ASSEMBLY__ */
10491 
10493 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
10494 
10495 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_ADDRBASE_LOW_OFST 0x4c
10496 
10522 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
10523 
10524 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
10525 
10526 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
10527 
10528 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
10529 
10530 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
10531 
10532 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
10533 
10534 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
10535 
10536 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
10537 
10538 #ifndef __ASSEMBLY__
10539 
10550 {
10551  uint32_t FILTERS_0_WINDOWSIZE : 6;
10552  uint32_t : 26;
10553 };
10554 
10557 #endif /* __ASSEMBLY__ */
10558 
10560 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_RESET 0x00000000
10561 
10562 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_WINDOWSIZE_OFST 0x54
10563 
10585 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
10586 
10587 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
10588 
10589 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
10590 
10591 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
10592 
10593 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
10594 
10595 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
10596 
10597 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
10598 
10599 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
10600 
10601 #ifndef __ASSEMBLY__
10602 
10613 {
10614  uint32_t FILTERS_0_SECURITYBASE : 3;
10615  uint32_t : 29;
10616 };
10617 
10620 #endif /* __ASSEMBLY__ */
10621 
10623 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_RESET 0x00000000
10624 
10625 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYBASE_OFST 0x58
10626 
10650 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
10651 
10652 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
10653 
10654 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
10655 
10656 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
10657 
10658 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
10659 
10660 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
10661 
10662 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
10663 
10664 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
10665 
10666 #ifndef __ASSEMBLY__
10667 
10678 {
10679  uint32_t FILTERS_0_SECURITYMASK : 3;
10680  uint32_t : 29;
10681 };
10682 
10685 #endif /* __ASSEMBLY__ */
10686 
10688 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_RESET 0x00000000
10689 
10690 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_SECURITYMSK_OFST 0x5c
10691 
10718 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_LSB 0
10719 
10720 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_MSB 0
10721 
10722 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_WIDTH 1
10723 
10724 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
10725 
10726 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
10727 
10728 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_RESET 0x0
10729 
10730 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
10731 
10732 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
10733 
10743 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_LSB 1
10744 
10745 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_MSB 1
10746 
10747 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_WIDTH 1
10748 
10749 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
10750 
10751 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
10752 
10753 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_RESET 0x0
10754 
10755 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
10756 
10757 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
10758 
10768 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_LSB 2
10769 
10770 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_MSB 2
10771 
10772 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_WIDTH 1
10773 
10774 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
10775 
10776 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
10777 
10778 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_RESET 0x0
10779 
10780 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
10781 
10782 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
10783 
10793 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_LSB 3
10794 
10795 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_MSB 3
10796 
10797 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_WIDTH 1
10798 
10799 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
10800 
10801 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
10802 
10803 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_RESET 0x0
10804 
10805 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
10806 
10807 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
10808 
10809 #ifndef __ASSEMBLY__
10810 
10821 {
10822  uint32_t RDEN : 1;
10823  uint32_t WREN : 1;
10824  uint32_t LOCKEN : 1;
10825  uint32_t URGEN : 1;
10826  uint32_t : 28;
10827 };
10828 
10831 #endif /* __ASSEMBLY__ */
10832 
10834 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_RESET 0x00000000
10835 
10836 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_OPCODE_OFST 0x60
10837 
10862 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_LSB 0
10863 
10864 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_MSB 0
10865 
10866 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_WIDTH 1
10867 
10868 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
10869 
10870 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
10871 
10872 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_RESET 0x0
10873 
10874 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
10875 
10876 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
10877 
10887 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_LSB 1
10888 
10889 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_MSB 1
10890 
10891 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_WIDTH 1
10892 
10893 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
10894 
10895 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
10896 
10897 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_RESET 0x0
10898 
10899 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
10900 
10901 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
10902 
10903 #ifndef __ASSEMBLY__
10904 
10915 {
10916  uint32_t REQEN : 1;
10917  uint32_t RSPEN : 1;
10918  uint32_t : 30;
10919 };
10920 
10923 #endif /* __ASSEMBLY__ */
10924 
10926 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_RESET 0x00000000
10927 
10928 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_STAT_OFST 0x64
10929 
10952 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_LSB 0
10953 
10954 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_MSB 3
10955 
10956 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
10957 
10958 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
10959 
10960 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
10961 
10962 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
10963 
10964 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
10965 
10966 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
10967 
10968 #ifndef __ASSEMBLY__
10969 
10980 {
10981  uint32_t FILTERS_0_LENGTH : 4;
10982  uint32_t : 28;
10983 };
10984 
10987 #endif /* __ASSEMBLY__ */
10988 
10990 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_RESET 0x00000000
10991 
10992 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_LEN_OFST 0x68
10993 
11017 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
11018 
11019 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
11020 
11021 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
11022 
11023 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
11024 
11025 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
11026 
11027 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
11028 
11029 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
11030 
11031 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
11032 
11033 #ifndef __ASSEMBLY__
11034 
11045 {
11046  uint32_t FILTERS_0_URGENCY : 2;
11047  uint32_t : 30;
11048 };
11049 
11052 #endif /* __ASSEMBLY__ */
11053 
11055 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_RESET 0x00000000
11056 
11057 #define ALT_NOC_MPU_PRB_MPU_MAIN_FLTS_0_URGENCY_OFST 0x6c
11058 
11083 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_LSB 0
11084 
11085 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_MSB 4
11086 
11087 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_WIDTH 5
11088 
11089 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
11090 
11091 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
11092 
11093 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_RESET 0x0
11094 
11095 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11096 
11097 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11098 
11099 #ifndef __ASSEMBLY__
11100 
11111 {
11112  uint32_t INTEVENT : 5;
11113  uint32_t : 27;
11114 };
11115 
11118 #endif /* __ASSEMBLY__ */
11119 
11121 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_RESET 0x00000000
11122 
11123 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_SRC_OFST 0x138
11124 
11148 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
11149 
11150 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
11151 
11152 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
11153 
11154 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
11155 
11156 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
11157 
11158 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
11159 
11160 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11161 
11162 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11163 
11164 #ifndef __ASSEMBLY__
11165 
11176 {
11177  uint32_t COUNTERS_0_ALARMMODE : 2;
11178  uint32_t : 30;
11179 };
11180 
11183 #endif /* __ASSEMBLY__ */
11184 
11186 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_RESET 0x00000000
11187 
11188 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_ALARMMOD_OFST 0x13c
11189 
11213 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
11214 
11215 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
11216 
11217 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
11218 
11219 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
11220 
11221 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
11222 
11223 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
11224 
11225 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11226 
11227 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11228 
11229 #ifndef __ASSEMBLY__
11230 
11241 {
11242  const uint32_t COUNTERS_0_VAL : 16;
11243  uint32_t : 16;
11244 };
11245 
11248 #endif /* __ASSEMBLY__ */
11249 
11251 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_RESET 0x00000000
11252 
11253 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_0_VAL_OFST 0x140
11254 
11279 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_LSB 0
11280 
11281 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_MSB 4
11282 
11283 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_WIDTH 5
11284 
11285 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
11286 
11287 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
11288 
11289 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_RESET 0x0
11290 
11291 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11292 
11293 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11294 
11295 #ifndef __ASSEMBLY__
11296 
11307 {
11308  uint32_t INTEVENT : 5;
11309  uint32_t : 27;
11310 };
11311 
11314 #endif /* __ASSEMBLY__ */
11315 
11317 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_RESET 0x00000000
11318 
11319 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_SRC_OFST 0x14c
11320 
11344 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
11345 
11346 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
11347 
11348 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
11349 
11350 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
11351 
11352 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
11353 
11354 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
11355 
11356 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11357 
11358 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11359 
11360 #ifndef __ASSEMBLY__
11361 
11372 {
11373  uint32_t COUNTERS_1_ALARMMODE : 2;
11374  uint32_t : 30;
11375 };
11376 
11379 #endif /* __ASSEMBLY__ */
11380 
11382 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_RESET 0x00000000
11383 
11384 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_ALARMMOD_OFST 0x150
11385 
11409 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
11410 
11411 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
11412 
11413 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
11414 
11415 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
11416 
11417 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
11418 
11419 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
11420 
11421 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11422 
11423 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11424 
11425 #ifndef __ASSEMBLY__
11426 
11437 {
11438  const uint32_t COUNTERS_1_VAL : 16;
11439  uint32_t : 16;
11440 };
11441 
11444 #endif /* __ASSEMBLY__ */
11445 
11447 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_RESET 0x00000000
11448 
11449 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_1_VAL_OFST 0x154
11450 
11475 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_LSB 0
11476 
11477 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_MSB 4
11478 
11479 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_WIDTH 5
11480 
11481 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_SET_MSK 0x0000001f
11482 
11483 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_CLR_MSK 0xffffffe0
11484 
11485 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_RESET 0x0
11486 
11487 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11488 
11489 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11490 
11491 #ifndef __ASSEMBLY__
11492 
11503 {
11504  uint32_t INTEVENT : 5;
11505  uint32_t : 27;
11506 };
11507 
11510 #endif /* __ASSEMBLY__ */
11511 
11513 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_RESET 0x00000000
11514 
11515 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_SRC_OFST 0x160
11516 
11540 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_LSB 0
11541 
11542 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_MSB 1
11543 
11544 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_WIDTH 2
11545 
11546 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET_MSK 0x00000003
11547 
11548 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_CLR_MSK 0xfffffffc
11549 
11550 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_RESET 0x0
11551 
11552 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11553 
11554 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_CNTRS_2_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11555 
11556 #ifndef __ASSEMBLY__
11557 
11568 {
11569  uint32_t COUNTERS_2_ALARMMODE : 2;
11570  uint32_t : 30;
11571 };
11572 
11575 #endif /* __ASSEMBLY__ */
11576 
11578 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_RESET 0x00000000
11579 
11580 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_ALARMMOD_OFST 0x164
11581 
11605 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_LSB 0
11606 
11607 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_MSB 15
11608 
11609 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_WIDTH 16
11610 
11611 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET_MSK 0x0000ffff
11612 
11613 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_CLR_MSK 0xffff0000
11614 
11615 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_RESET 0x0
11616 
11617 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11618 
11619 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_CNTRS_2_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11620 
11621 #ifndef __ASSEMBLY__
11622 
11633 {
11634  const uint32_t COUNTERS_2_VAL : 16;
11635  uint32_t : 16;
11636 };
11637 
11640 #endif /* __ASSEMBLY__ */
11641 
11643 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_RESET 0x00000000
11644 
11645 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_2_VAL_OFST 0x168
11646 
11671 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_LSB 0
11672 
11673 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_MSB 4
11674 
11675 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_WIDTH 5
11676 
11677 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_SET_MSK 0x0000001f
11678 
11679 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_CLR_MSK 0xffffffe0
11680 
11681 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_RESET 0x0
11682 
11683 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
11684 
11685 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
11686 
11687 #ifndef __ASSEMBLY__
11688 
11699 {
11700  uint32_t INTEVENT : 5;
11701  uint32_t : 27;
11702 };
11703 
11706 #endif /* __ASSEMBLY__ */
11707 
11709 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_RESET 0x00000000
11710 
11711 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_SRC_OFST 0x174
11712 
11736 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_LSB 0
11737 
11738 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_MSB 1
11739 
11740 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_WIDTH 2
11741 
11742 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET_MSK 0x00000003
11743 
11744 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_CLR_MSK 0xfffffffc
11745 
11746 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_RESET 0x0
11747 
11748 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
11749 
11750 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_CNTRS_3_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
11751 
11752 #ifndef __ASSEMBLY__
11753 
11764 {
11765  uint32_t COUNTERS_3_ALARMMODE : 2;
11766  uint32_t : 30;
11767 };
11768 
11771 #endif /* __ASSEMBLY__ */
11772 
11774 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_RESET 0x00000000
11775 
11776 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_ALARMMOD_OFST 0x178
11777 
11801 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_LSB 0
11802 
11803 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_MSB 15
11804 
11805 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_WIDTH 16
11806 
11807 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET_MSK 0x0000ffff
11808 
11809 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_CLR_MSK 0xffff0000
11810 
11811 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_RESET 0x0
11812 
11813 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
11814 
11815 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_CNTRS_3_VAL_SET(value) (((value) << 0) & 0x0000ffff)
11816 
11817 #ifndef __ASSEMBLY__
11818 
11829 {
11830  const uint32_t COUNTERS_3_VAL : 16;
11831  uint32_t : 16;
11832 };
11833 
11836 #endif /* __ASSEMBLY__ */
11837 
11839 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_RESET 0x00000000
11840 
11841 #define ALT_NOC_MPU_PRB_MPU_MAIN_CNTRS_3_VAL_OFST 0x17c
11842 
11843 #ifndef __ASSEMBLY__
11844 
11855 {
11860  volatile uint32_t _pad_0x10_0x13;
11872  volatile uint32_t _pad_0x40_0x43;
11876  volatile uint32_t _pad_0x50_0x53;
11884  volatile uint32_t _pad_0x70_0x137[50];
11888  volatile uint32_t _pad_0x144_0x14b[2];
11892  volatile uint32_t _pad_0x158_0x15f[2];
11896  volatile uint32_t _pad_0x16c_0x173[2];
11900  volatile uint32_t _pad_0x180_0x400[160];
11901 };
11902 
11907 {
11910  volatile uint32_t Probe_MPU_main_Probe_MainCtl;
11911  volatile uint32_t Probe_MPU_main_Probe_CfgCtl;
11912  volatile uint32_t _pad_0x10_0x13;
11918  volatile uint32_t Probe_MPU_main_Probe_StatGo;
11924  volatile uint32_t _pad_0x40_0x43;
11928  volatile uint32_t _pad_0x50_0x53;
11936  volatile uint32_t _pad_0x70_0x137[50];
11940  volatile uint32_t _pad_0x144_0x14b[2];
11944  volatile uint32_t _pad_0x158_0x15f[2];
11948  volatile uint32_t _pad_0x16c_0x173[2];
11952  volatile uint32_t _pad_0x180_0x400[160];
11953 };
11954 
11957 #endif /* __ASSEMBLY__ */
11958 
11960 #ifdef __cplusplus
11961 }
11962 #endif /* __cplusplus */
11963 #endif /* __ALT_SOCAL_NOC_MPU_PRB_H__ */
11964