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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Bits indicating CMD-DMA channel receiving an error condition. To get more information on the error, s/w needs to read the status field of the descriptor.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 |
[1] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 |
[2] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 |
[3] | RW | 0x0 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 |
[31:4] | ??? | Unknown | UNDEFINED |
Field : channel0 | |
CMD-DMA channel 0 received an error. Field Access Macros: | |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001) |
Field : channel1 | |
CMD-DMA channel 1 received an error. Field Access Macros: | |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002) |
Field : channel2 | |
CMD-DMA channel 2 received an error. Field Access Macros: | |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004) |
Field : channel3 | |
CMD-DMA channel 3 received an error. Field Access Macros: | |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008) |
Data Structures | |
struct | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s |
Macros | |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000 |
#define | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0 |
Typedefs | |
typedef struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t |
struct ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR.
Data Fields | ||
---|---|---|
uint32_t | channel0: 1 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 |
uint32_t | channel1: 1 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 |
uint32_t | channel2: 1 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 |
uint32_t | channel3: 1 | ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 |
uint32_t | __pad0__: 28 | UNDEFINED |
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001 |
The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0 |
The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 field value from a register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0 register field value suitable for setting the register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002 |
The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0 |
The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 field value from a register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1 register field value suitable for setting the register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004 |
The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0 |
The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 field value from a register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2 register field value suitable for setting the register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008 |
The mask used to set the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0 |
The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 field value from a register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3 register field value suitable for setting the register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000 |
The reset value of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register.
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0 |
The byte offset of the ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR register from the beginning of the component.
The typedef declaration for register ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR.