Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Control Register - ctrl

Description

Registers used by the SDMMC Controller. All fields are reset by a cold or warm reset.

Register Layout

Bits Access Reset Description
[2:0] RW 0x0 Drive Clock Phase Shift Select
[5:3] RW 0x0 Sample Clock Phase Shift Select
[6] RW 0x0 Feedback Clock Select
[31:7] ??? 0x0 UNDEFINED

Field : Drive Clock Phase Shift Select - drvsel

Select which phase shift of the clock for cclk_in_drv.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0 0 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1 45 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2 90 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3 135 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4 180 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5 225 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6 270 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7 315 degrees phase shifted clock is selected

Field Access Macros:

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0   0x0
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45   0x1
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90   0x2
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135   0x3
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180   0x4
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225   0x5
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270   0x6
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315   0x7
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB   0
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB   2
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH   3
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK   0x00000007
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK   0xfffffff8
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET   0x0
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value)   (((value) & 0x00000007) >> 0)
 
#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value)   (((value) << 0) & 0x00000007)
 

Field : Sample Clock Phase Shift Select - smplsel

Select which phase shift of the clock for cclk_in_sample.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0 0 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1 45 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2 90 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3 135 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4 180 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5 225 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6 270 degrees phase shifted clock is selected
ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7 315 degrees phase shifted clock is selected

Field Access Macros:

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0   0x0
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45   0x1
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90   0x2
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135   0x3
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180   0x4
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225   0x5
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270   0x6
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315   0x7
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB   3
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB   5
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH   3
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK   0x00000038
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK   0xffffffc7
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET   0x0
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value)   (((value) & 0x00000038) >> 3)
 
#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value)   (((value) << 3) & 0x00000038)
 

Field : Feedback Clock Select - fbclksel

Select which fb_clk to be used as cclk_in_sample.

If 0, cclk_in_sample is driven by internal phase shifted cclk_in.

If 1, cclk_in_sample is driven by fb_clk_in. No phase shifting is provided internally on cclk_in_sample.

Note: Using the feedback clock (setting this bit to 1) is not a supported use model.

Field Access Macros:

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB   6
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB   6
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH   1
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK   0x00000040
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK   0xffffffbf
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET   0x0
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value)   (((value) << 6) & 0x00000040)
 

Data Structures

struct  ALT_SYSMGR_SDMMC_CTL_s
 

Macros

#define ALT_SYSMGR_SDMMC_CTL_OFST   0x0
 

Typedefs

typedef struct
ALT_SYSMGR_SDMMC_CTL_s 
ALT_SYSMGR_SDMMC_CTL_t
 

Data Structure Documentation

struct ALT_SYSMGR_SDMMC_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_SDMMC_CTL.

Data Fields
uint32_t drvsel: 3 Drive Clock Phase Shift Select
uint32_t smplsel: 3 Sample Clock Phase Shift Select
uint32_t fbclksel: 1 Feedback Clock Select
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0   0x0

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

0 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45   0x1

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

45 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90   0x2

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

90 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135   0x3

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

135 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180   0x4

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

180 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225   0x5

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

225 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270   0x6

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

270 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315   0x7

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_DRVSEL

315 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB   2

The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK   0x00000007

The mask used to set the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK   0xfffffff8

The mask used to clear the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET   0x0

The reset value of the ALT_SYSMGR_SDMMC_CTL_DRVSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET (   value)    (((value) & 0x00000007) >> 0)

Extracts the ALT_SYSMGR_SDMMC_CTL_DRVSEL field value from a register.

#define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET (   value)    (((value) << 0) & 0x00000007)

Produces a ALT_SYSMGR_SDMMC_CTL_DRVSEL register field value suitable for setting the register.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0   0x0

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

0 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45   0x1

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

45 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90   0x2

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

90 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135   0x3

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

135 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180   0x4

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

180 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225   0x5

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

225 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270   0x6

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

270 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315   0x7

Enumerated value for register field ALT_SYSMGR_SDMMC_CTL_SMPLSEL

315 degrees phase shifted clock is selected

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB   3

The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB   5

The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK   0x00000038

The mask used to set the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK   0xffffffc7

The mask used to clear the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET   0x0

The reset value of the ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET (   value)    (((value) & 0x00000038) >> 3)

Extracts the ALT_SYSMGR_SDMMC_CTL_SMPLSEL field value from a register.

#define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET (   value)    (((value) << 3) & 0x00000038)

Produces a ALT_SYSMGR_SDMMC_CTL_SMPLSEL register field value suitable for setting the register.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB   6

The Least Significant Bit (LSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB   6

The Most Significant Bit (MSB) position of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH   1

The width in bits of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK   0x00000040

The mask used to set the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET   0x0

The reset value of the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SYSMGR_SDMMC_CTL_FBCLKSEL field value from a register.

#define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SYSMGR_SDMMC_CTL_FBCLKSEL register field value suitable for setting the register.

#define ALT_SYSMGR_SDMMC_CTL_OFST   0x0

The byte offset of the ALT_SYSMGR_SDMMC_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_SDMMC_CTL.