Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_sysmgr.h
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32 
35 #ifndef __ALTERA_ALT_SYSMGR_H__
36 #define __ALTERA_ALT_SYSMGR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
82 #define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x1
83 
85 #define ALT_SYSMGR_SILICONID1_REV_LSB 0
86 
87 #define ALT_SYSMGR_SILICONID1_REV_MSB 15
88 
89 #define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
90 
91 #define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
92 
93 #define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
94 
95 #define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
96 
97 #define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
98 
99 #define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
100 
120 #define ALT_SYSMGR_SILICONID1_ID_E_CYCLONEV_ARRIAV 0x0
121 
123 #define ALT_SYSMGR_SILICONID1_ID_LSB 16
124 
125 #define ALT_SYSMGR_SILICONID1_ID_MSB 31
126 
127 #define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
128 
129 #define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
130 
131 #define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
132 
133 #define ALT_SYSMGR_SILICONID1_ID_RESET 0x0
134 
135 #define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
136 
137 #define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
138 
139 #ifndef __ASSEMBLY__
140 
151 {
152  const uint32_t rev : 16;
153  const uint32_t id : 16;
154 };
155 
158 #endif /* __ASSEMBLY__ */
159 
161 #define ALT_SYSMGR_SILICONID1_OFST 0x0
162 
184 #define ALT_SYSMGR_SILICONID2_RSV_LSB 0
185 
186 #define ALT_SYSMGR_SILICONID2_RSV_MSB 31
187 
188 #define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
189 
190 #define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
191 
192 #define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
193 
194 #define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
195 
196 #define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
197 
198 #define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
199 
200 #ifndef __ASSEMBLY__
201 
212 {
213  const uint32_t rsv : 32;
214 };
215 
218 #endif /* __ASSEMBLY__ */
219 
221 #define ALT_SYSMGR_SILICONID2_OFST 0x4
222 
267 #define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
268 
273 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
274 
279 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
280 
285 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
286 
288 #define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
289 
290 #define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
291 
292 #define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
293 
294 #define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
295 
296 #define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
297 
298 #define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
299 
300 #define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
301 
302 #define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
303 
331 #define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
332 
337 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
338 
343 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
344 
349 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
350 
352 #define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
353 
354 #define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
355 
356 #define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
357 
358 #define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
359 
360 #define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
361 
362 #define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
363 
364 #define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
365 
366 #define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
367 
368 #ifndef __ASSEMBLY__
369 
380 {
381  uint32_t mode_0 : 2;
382  uint32_t mode_1 : 2;
383  uint32_t : 28;
384 };
385 
387 typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
388 #endif /* __ASSEMBLY__ */
389 
391 #define ALT_SYSMGR_WDDBG_OFST 0x10
392 
438 #define ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0
439 
444 #define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
445 
450 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
451 
456 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
457 
462 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
463 
468 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
469 
474 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
475 
480 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
481 
483 #define ALT_SYSMGR_BOOT_BSEL_LSB 0
484 
485 #define ALT_SYSMGR_BOOT_BSEL_MSB 2
486 
487 #define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
488 
489 #define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00000007
490 
491 #define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xfffffff8
492 
493 #define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
494 
495 #define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00000007) >> 0)
496 
497 #define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 0) & 0x00000007)
498 
542 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0
543 
549 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1
550 
556 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2
557 
563 #define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3
564 
566 #define ALT_SYSMGR_BOOT_CSEL_LSB 3
567 
568 #define ALT_SYSMGR_BOOT_CSEL_MSB 4
569 
570 #define ALT_SYSMGR_BOOT_CSEL_WIDTH 2
571 
572 #define ALT_SYSMGR_BOOT_CSEL_SET_MSK 0x00000018
573 
574 #define ALT_SYSMGR_BOOT_CSEL_CLR_MSK 0xffffffe7
575 
576 #define ALT_SYSMGR_BOOT_CSEL_RESET 0x0
577 
578 #define ALT_SYSMGR_BOOT_CSEL_GET(value) (((value) & 0x00000018) >> 3)
579 
580 #define ALT_SYSMGR_BOOT_CSEL_SET(value) (((value) << 3) & 0x00000018)
581 
592 #define ALT_SYSMGR_BOOT_PINBSEL_LSB 5
593 
594 #define ALT_SYSMGR_BOOT_PINBSEL_MSB 7
595 
596 #define ALT_SYSMGR_BOOT_PINBSEL_WIDTH 3
597 
598 #define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK 0x000000e0
599 
600 #define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK 0xffffff1f
601 
602 #define ALT_SYSMGR_BOOT_PINBSEL_RESET 0x0
603 
604 #define ALT_SYSMGR_BOOT_PINBSEL_GET(value) (((value) & 0x000000e0) >> 5)
605 
606 #define ALT_SYSMGR_BOOT_PINBSEL_SET(value) (((value) << 5) & 0x000000e0)
607 
618 #define ALT_SYSMGR_BOOT_PINCSEL_LSB 8
619 
620 #define ALT_SYSMGR_BOOT_PINCSEL_MSB 9
621 
622 #define ALT_SYSMGR_BOOT_PINCSEL_WIDTH 2
623 
624 #define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK 0x00000300
625 
626 #define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK 0xfffffcff
627 
628 #define ALT_SYSMGR_BOOT_PINCSEL_RESET 0x0
629 
630 #define ALT_SYSMGR_BOOT_PINCSEL_GET(value) (((value) & 0x00000300) >> 8)
631 
632 #define ALT_SYSMGR_BOOT_PINCSEL_SET(value) (((value) << 8) & 0x00000300)
633 
634 #ifndef __ASSEMBLY__
635 
646 {
647  const uint32_t bsel : 3;
648  const uint32_t csel : 2;
649  const uint32_t pinbsel : 3;
650  const uint32_t pincsel : 2;
651  uint32_t : 22;
652 };
653 
655 typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
656 #endif /* __ASSEMBLY__ */
657 
659 #define ALT_SYSMGR_BOOT_OFST 0x14
660 
695 #define ALT_SYSMGR_HPSINFO_DUALCORE_E_SINGLECORE 0x0
696 
701 #define ALT_SYSMGR_HPSINFO_DUALCORE_E_DUALCORE 0x1
702 
704 #define ALT_SYSMGR_HPSINFO_DUALCORE_LSB 0
705 
706 #define ALT_SYSMGR_HPSINFO_DUALCORE_MSB 0
707 
708 #define ALT_SYSMGR_HPSINFO_DUALCORE_WIDTH 1
709 
710 #define ALT_SYSMGR_HPSINFO_DUALCORE_SET_MSK 0x00000001
711 
712 #define ALT_SYSMGR_HPSINFO_DUALCORE_CLR_MSK 0xfffffffe
713 
714 #define ALT_SYSMGR_HPSINFO_DUALCORE_RESET 0x0
715 
716 #define ALT_SYSMGR_HPSINFO_DUALCORE_GET(value) (((value) & 0x00000001) >> 0)
717 
718 #define ALT_SYSMGR_HPSINFO_DUALCORE_SET(value) (((value) << 0) & 0x00000001)
719 
740 #define ALT_SYSMGR_HPSINFO_CAN_E_CAN_UNAVAILABLE 0x0
741 
746 #define ALT_SYSMGR_HPSINFO_CAN_E_CAN_AVAILABLE 0x1
747 
749 #define ALT_SYSMGR_HPSINFO_CAN_LSB 1
750 
751 #define ALT_SYSMGR_HPSINFO_CAN_MSB 1
752 
753 #define ALT_SYSMGR_HPSINFO_CAN_WIDTH 1
754 
755 #define ALT_SYSMGR_HPSINFO_CAN_SET_MSK 0x00000002
756 
757 #define ALT_SYSMGR_HPSINFO_CAN_CLR_MSK 0xfffffffd
758 
759 #define ALT_SYSMGR_HPSINFO_CAN_RESET 0x0
760 
761 #define ALT_SYSMGR_HPSINFO_CAN_GET(value) (((value) & 0x00000002) >> 1)
762 
763 #define ALT_SYSMGR_HPSINFO_CAN_SET(value) (((value) << 1) & 0x00000002)
764 
765 #ifndef __ASSEMBLY__
766 
777 {
778  const uint32_t dualcore : 1;
779  const uint32_t can : 1;
780  uint32_t : 30;
781 };
782 
785 #endif /* __ASSEMBLY__ */
786 
788 #define ALT_SYSMGR_HPSINFO_OFST 0x18
789 
832 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_LSB 0
833 
834 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_MSB 0
835 
836 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_WIDTH 1
837 
838 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET_MSK 0x00000001
839 
840 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_CLR_MSK 0xfffffffe
841 
842 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_RESET 0x0
843 
844 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_GET(value) (((value) & 0x00000001) >> 0)
845 
846 #define ALT_SYSMGR_PARITYINJ_DCDATA_0_SET(value) (((value) << 0) & 0x00000001)
847 
858 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_LSB 1
859 
860 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_MSB 1
861 
862 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_WIDTH 1
863 
864 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET_MSK 0x00000002
865 
866 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_CLR_MSK 0xfffffffd
867 
868 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_RESET 0x0
869 
870 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_GET(value) (((value) & 0x00000002) >> 1)
871 
872 #define ALT_SYSMGR_PARITYINJ_DCDATA_1_SET(value) (((value) << 1) & 0x00000002)
873 
884 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_LSB 2
885 
886 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_MSB 2
887 
888 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_WIDTH 1
889 
890 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET_MSK 0x00000004
891 
892 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_CLR_MSK 0xfffffffb
893 
894 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_RESET 0x0
895 
896 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_GET(value) (((value) & 0x00000004) >> 2)
897 
898 #define ALT_SYSMGR_PARITYINJ_DCTAG_0_SET(value) (((value) << 2) & 0x00000004)
899 
910 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_LSB 3
911 
912 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_MSB 3
913 
914 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_WIDTH 1
915 
916 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET_MSK 0x00000008
917 
918 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_CLR_MSK 0xfffffff7
919 
920 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_RESET 0x0
921 
922 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_GET(value) (((value) & 0x00000008) >> 3)
923 
924 #define ALT_SYSMGR_PARITYINJ_DCTAG_1_SET(value) (((value) << 3) & 0x00000008)
925 
936 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_LSB 4
937 
938 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_MSB 4
939 
940 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_WIDTH 1
941 
942 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET_MSK 0x00000010
943 
944 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_CLR_MSK 0xffffffef
945 
946 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_RESET 0x0
947 
948 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_GET(value) (((value) & 0x00000010) >> 4)
949 
950 #define ALT_SYSMGR_PARITYINJ_DCOUTER_0_SET(value) (((value) << 4) & 0x00000010)
951 
962 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_LSB 5
963 
964 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_MSB 5
965 
966 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_WIDTH 1
967 
968 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET_MSK 0x00000020
969 
970 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_CLR_MSK 0xffffffdf
971 
972 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_RESET 0x0
973 
974 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_GET(value) (((value) & 0x00000020) >> 5)
975 
976 #define ALT_SYSMGR_PARITYINJ_DCOUTER_1_SET(value) (((value) << 5) & 0x00000020)
977 
988 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_LSB 6
989 
990 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_MSB 6
991 
992 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_WIDTH 1
993 
994 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET_MSK 0x00000040
995 
996 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_CLR_MSK 0xffffffbf
997 
998 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_RESET 0x0
999 
1000 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_GET(value) (((value) & 0x00000040) >> 6)
1001 
1002 #define ALT_SYSMGR_PARITYINJ_MAINTLB_0_SET(value) (((value) << 6) & 0x00000040)
1003 
1014 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_LSB 7
1015 
1016 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_MSB 7
1017 
1018 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_WIDTH 1
1019 
1020 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET_MSK 0x00000080
1021 
1022 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_CLR_MSK 0xffffff7f
1023 
1024 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_RESET 0x0
1025 
1026 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_GET(value) (((value) & 0x00000080) >> 7)
1027 
1028 #define ALT_SYSMGR_PARITYINJ_MAINTLB_1_SET(value) (((value) << 7) & 0x00000080)
1029 
1040 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_LSB 8
1041 
1042 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_MSB 8
1043 
1044 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_WIDTH 1
1045 
1046 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET_MSK 0x00000100
1047 
1048 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_CLR_MSK 0xfffffeff
1049 
1050 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_RESET 0x0
1051 
1052 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_GET(value) (((value) & 0x00000100) >> 8)
1053 
1054 #define ALT_SYSMGR_PARITYINJ_ICDATA_0_SET(value) (((value) << 8) & 0x00000100)
1055 
1066 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_LSB 9
1067 
1068 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_MSB 9
1069 
1070 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_WIDTH 1
1071 
1072 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET_MSK 0x00000200
1073 
1074 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_CLR_MSK 0xfffffdff
1075 
1076 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_RESET 0x0
1077 
1078 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_GET(value) (((value) & 0x00000200) >> 9)
1079 
1080 #define ALT_SYSMGR_PARITYINJ_ICDATA_1_SET(value) (((value) << 9) & 0x00000200)
1081 
1092 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_LSB 10
1093 
1094 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_MSB 10
1095 
1096 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_WIDTH 1
1097 
1098 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET_MSK 0x00000400
1099 
1100 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_CLR_MSK 0xfffffbff
1101 
1102 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_RESET 0x0
1103 
1104 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_GET(value) (((value) & 0x00000400) >> 10)
1105 
1106 #define ALT_SYSMGR_PARITYINJ_ICTAG_0_SET(value) (((value) << 10) & 0x00000400)
1107 
1118 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_LSB 11
1119 
1120 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_MSB 11
1121 
1122 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_WIDTH 1
1123 
1124 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET_MSK 0x00000800
1125 
1126 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_CLR_MSK 0xfffff7ff
1127 
1128 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_RESET 0x0
1129 
1130 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_GET(value) (((value) & 0x00000800) >> 11)
1131 
1132 #define ALT_SYSMGR_PARITYINJ_ICTAG_1_SET(value) (((value) << 11) & 0x00000800)
1133 
1144 #define ALT_SYSMGR_PARITYINJ_GHB_0_LSB 12
1145 
1146 #define ALT_SYSMGR_PARITYINJ_GHB_0_MSB 12
1147 
1148 #define ALT_SYSMGR_PARITYINJ_GHB_0_WIDTH 1
1149 
1150 #define ALT_SYSMGR_PARITYINJ_GHB_0_SET_MSK 0x00001000
1151 
1152 #define ALT_SYSMGR_PARITYINJ_GHB_0_CLR_MSK 0xffffefff
1153 
1154 #define ALT_SYSMGR_PARITYINJ_GHB_0_RESET 0x0
1155 
1156 #define ALT_SYSMGR_PARITYINJ_GHB_0_GET(value) (((value) & 0x00001000) >> 12)
1157 
1158 #define ALT_SYSMGR_PARITYINJ_GHB_0_SET(value) (((value) << 12) & 0x00001000)
1159 
1170 #define ALT_SYSMGR_PARITYINJ_GHB_1_LSB 13
1171 
1172 #define ALT_SYSMGR_PARITYINJ_GHB_1_MSB 13
1173 
1174 #define ALT_SYSMGR_PARITYINJ_GHB_1_WIDTH 1
1175 
1176 #define ALT_SYSMGR_PARITYINJ_GHB_1_SET_MSK 0x00002000
1177 
1178 #define ALT_SYSMGR_PARITYINJ_GHB_1_CLR_MSK 0xffffdfff
1179 
1180 #define ALT_SYSMGR_PARITYINJ_GHB_1_RESET 0x0
1181 
1182 #define ALT_SYSMGR_PARITYINJ_GHB_1_GET(value) (((value) & 0x00002000) >> 13)
1183 
1184 #define ALT_SYSMGR_PARITYINJ_GHB_1_SET(value) (((value) << 13) & 0x00002000)
1185 
1196 #define ALT_SYSMGR_PARITYINJ_BTAC_0_LSB 14
1197 
1198 #define ALT_SYSMGR_PARITYINJ_BTAC_0_MSB 14
1199 
1200 #define ALT_SYSMGR_PARITYINJ_BTAC_0_WIDTH 1
1201 
1202 #define ALT_SYSMGR_PARITYINJ_BTAC_0_SET_MSK 0x00004000
1203 
1204 #define ALT_SYSMGR_PARITYINJ_BTAC_0_CLR_MSK 0xffffbfff
1205 
1206 #define ALT_SYSMGR_PARITYINJ_BTAC_0_RESET 0x0
1207 
1208 #define ALT_SYSMGR_PARITYINJ_BTAC_0_GET(value) (((value) & 0x00004000) >> 14)
1209 
1210 #define ALT_SYSMGR_PARITYINJ_BTAC_0_SET(value) (((value) << 14) & 0x00004000)
1211 
1222 #define ALT_SYSMGR_PARITYINJ_BTAC_1_LSB 15
1223 
1224 #define ALT_SYSMGR_PARITYINJ_BTAC_1_MSB 15
1225 
1226 #define ALT_SYSMGR_PARITYINJ_BTAC_1_WIDTH 1
1227 
1228 #define ALT_SYSMGR_PARITYINJ_BTAC_1_SET_MSK 0x00008000
1229 
1230 #define ALT_SYSMGR_PARITYINJ_BTAC_1_CLR_MSK 0xffff7fff
1231 
1232 #define ALT_SYSMGR_PARITYINJ_BTAC_1_RESET 0x0
1233 
1234 #define ALT_SYSMGR_PARITYINJ_BTAC_1_GET(value) (((value) & 0x00008000) >> 15)
1235 
1236 #define ALT_SYSMGR_PARITYINJ_BTAC_1_SET(value) (((value) << 15) & 0x00008000)
1237 
1238 #ifndef __ASSEMBLY__
1239 
1250 {
1251  uint32_t dcdata_0 : 1;
1252  uint32_t dcdata_1 : 1;
1253  uint32_t dctag_0 : 1;
1254  uint32_t dctag_1 : 1;
1255  uint32_t dcouter_0 : 1;
1256  uint32_t dcouter_1 : 1;
1257  uint32_t maintlb_0 : 1;
1258  uint32_t maintlb_1 : 1;
1259  uint32_t icdata_0 : 1;
1260  uint32_t icdata_1 : 1;
1261  uint32_t ictag_0 : 1;
1262  uint32_t ictag_1 : 1;
1263  uint32_t ghb_0 : 1;
1264  uint32_t ghb_1 : 1;
1265  uint32_t btac_0 : 1;
1266  uint32_t btac_1 : 1;
1267  uint32_t : 16;
1268 };
1269 
1272 #endif /* __ASSEMBLY__ */
1273 
1275 #define ALT_SYSMGR_PARITYINJ_OFST 0x1c
1276 
1331 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0
1332 
1341 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1
1342 
1344 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB 0
1345 
1346 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB 0
1347 
1348 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH 1
1349 
1350 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK 0x00000001
1351 
1352 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK 0xfffffffe
1353 
1354 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET 0x1
1355 
1356 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value) (((value) & 0x00000001) >> 0)
1357 
1358 #define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value) (((value) << 0) & 0x00000001)
1359 
1360 #ifndef __ASSEMBLY__
1361 
1372 {
1373  uint32_t intf : 1;
1374  uint32_t : 31;
1375 };
1376 
1379 #endif /* __ASSEMBLY__ */
1380 
1382 #define ALT_SYSMGR_FPGAINTF_GBL_OFST 0x0
1383 
1431 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0
1432 
1437 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1
1438 
1440 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB 0
1441 
1442 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB 0
1443 
1444 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH 1
1445 
1446 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK 0x00000001
1447 
1448 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK 0xfffffffe
1449 
1450 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET 0x1
1451 
1452 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value) (((value) & 0x00000001) >> 0)
1453 
1454 #define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value) (((value) << 0) & 0x00000001)
1455 
1480 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0
1481 
1487 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1
1488 
1490 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB 1
1491 
1492 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB 1
1493 
1494 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH 1
1495 
1496 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK 0x00000002
1497 
1498 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK 0xfffffffd
1499 
1500 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET 0x1
1501 
1502 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value) (((value) & 0x00000002) >> 1)
1503 
1504 #define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value) (((value) << 1) & 0x00000002)
1505 
1536 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0
1537 
1543 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1
1544 
1546 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB 2
1547 
1548 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB 2
1549 
1550 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH 1
1551 
1552 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK 0x00000004
1553 
1554 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK 0xfffffffb
1555 
1556 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET 0x1
1557 
1558 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value) (((value) & 0x00000004) >> 2)
1559 
1560 #define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value) (((value) << 2) & 0x00000004)
1561 
1591 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0
1592 
1598 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1
1599 
1601 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB 3
1602 
1603 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB 3
1604 
1605 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH 1
1606 
1607 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK 0x00000008
1608 
1609 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK 0xfffffff7
1610 
1611 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET 0x1
1612 
1613 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value) (((value) & 0x00000008) >> 3)
1614 
1615 #define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value) (((value) << 3) & 0x00000008)
1616 
1642 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0
1643 
1649 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1
1650 
1652 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB 4
1653 
1654 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB 4
1655 
1656 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH 1
1657 
1658 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK 0x00000010
1659 
1660 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK 0xffffffef
1661 
1662 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET 0x1
1663 
1664 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value) (((value) & 0x00000010) >> 4)
1665 
1666 #define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value) (((value) << 4) & 0x00000010)
1667 
1692 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0
1693 
1699 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1
1700 
1702 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB 6
1703 
1704 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB 6
1705 
1706 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH 1
1707 
1708 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK 0x00000040
1709 
1710 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK 0xffffffbf
1711 
1712 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET 0x1
1713 
1714 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value) (((value) & 0x00000040) >> 6)
1715 
1716 #define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value) (((value) << 6) & 0x00000040)
1717 
1740 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0
1741 
1746 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1
1747 
1749 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB 7
1750 
1751 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB 7
1752 
1753 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH 1
1754 
1755 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK 0x00000080
1756 
1757 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK 0xffffff7f
1758 
1759 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET 0x1
1760 
1761 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value) (((value) & 0x00000080) >> 7)
1762 
1763 #define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value) (((value) << 7) & 0x00000080)
1764 
1765 #ifndef __ASSEMBLY__
1766 
1777 {
1778  uint32_t rstreqintf : 1;
1779  uint32_t jtagenintf : 1;
1780  uint32_t configiointf : 1;
1781  uint32_t bscanintf : 1;
1782  uint32_t traceintf : 1;
1783  uint32_t : 1;
1784  uint32_t stmeventintf : 1;
1785  uint32_t crosstrigintf : 1;
1786  uint32_t : 24;
1787 };
1788 
1791 #endif /* __ASSEMBLY__ */
1792 
1794 #define ALT_SYSMGR_FPGAINTF_INDIV_OFST 0x4
1795 
1836 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_DIS 0x0
1837 
1842 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_E_EN 0x1
1843 
1845 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_LSB 2
1846 
1847 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_MSB 2
1848 
1849 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_WIDTH 1
1850 
1851 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET_MSK 0x00000004
1852 
1853 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_CLR_MSK 0xfffffffb
1854 
1855 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_RESET 0x0
1856 
1857 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_GET(value) (((value) & 0x00000004) >> 2)
1858 
1859 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_0_SET(value) (((value) << 2) & 0x00000004)
1860 
1886 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_DIS 0x0
1887 
1892 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_E_EN 0x1
1893 
1895 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_LSB 3
1896 
1897 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_MSB 3
1898 
1899 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_WIDTH 1
1900 
1901 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET_MSK 0x00000008
1902 
1903 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_CLR_MSK 0xfffffff7
1904 
1905 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_RESET 0x0
1906 
1907 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_GET(value) (((value) & 0x00000008) >> 3)
1908 
1909 #define ALT_SYSMGR_FPGAINTF_MODULE_EMAC_1_SET(value) (((value) << 3) & 0x00000008)
1910 
1911 #ifndef __ASSEMBLY__
1912 
1923 {
1924  uint32_t : 2;
1925  uint32_t emac_0 : 1;
1926  uint32_t emac_1 : 1;
1927  uint32_t : 28;
1928 };
1929 
1932 #endif /* __ASSEMBLY__ */
1933 
1935 #define ALT_SYSMGR_FPGAINTF_MODULE_OFST 0x8
1936 
1937 #ifndef __ASSEMBLY__
1938 
1949 {
1953  volatile uint32_t _pad_0xc_0x10;
1954 };
1955 
1960 {
1961  volatile uint32_t gbl;
1962  volatile uint32_t indiv;
1963  volatile uint32_t module;
1964  volatile uint32_t _pad_0xc_0x10;
1965 };
1966 
1969 #endif /* __ASSEMBLY__ */
1970 
2016 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_FPGAPINS 0x0
2017 
2022 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_E_SCANMGR 0x1
2023 
2025 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_LSB 0
2026 
2027 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_MSB 0
2028 
2029 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_WIDTH 1
2030 
2031 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET_MSK 0x00000001
2032 
2033 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_CLR_MSK 0xfffffffe
2034 
2035 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_RESET 0x0
2036 
2037 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_GET(value) (((value) & 0x00000001) >> 0)
2038 
2039 #define ALT_SYSMGR_SCANMGR_CTL_FPGAJTAGEN_SET(value) (((value) << 0) & 0x00000001)
2040 
2041 #ifndef __ASSEMBLY__
2042 
2053 {
2054  uint32_t fpgajtagen : 1;
2055  uint32_t : 31;
2056 };
2057 
2060 #endif /* __ASSEMBLY__ */
2061 
2063 #define ALT_SYSMGR_SCANMGR_CTL_OFST 0x0
2064 
2065 #ifndef __ASSEMBLY__
2066 
2077 {
2079 };
2080 
2085 {
2086  volatile uint32_t ctrl;
2087 };
2088 
2091 #endif /* __ASSEMBLY__ */
2092 
2159 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0
2160 
2166 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1
2167 
2169 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0
2170 
2171 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0
2172 
2173 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1
2174 
2175 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001
2176 
2177 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe
2178 
2179 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0
2180 
2181 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2182 
2183 #define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2184 
2205 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0
2206 
2211 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1
2212 
2214 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1
2215 
2216 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1
2217 
2218 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1
2219 
2220 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002
2221 
2222 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2223 
2224 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0
2225 
2226 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2227 
2228 #define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2229 
2250 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0
2251 
2256 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1
2257 
2259 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2
2260 
2261 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2
2262 
2263 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1
2264 
2265 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004
2266 
2267 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2268 
2269 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0
2270 
2271 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2272 
2273 #define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2274 
2296 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0
2297 
2302 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1
2303 
2305 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3
2306 
2307 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3
2308 
2309 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1
2310 
2311 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008
2312 
2313 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2314 
2315 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0
2316 
2317 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2318 
2319 #define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2320 
2341 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0
2342 
2347 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1
2348 
2350 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4
2351 
2352 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4
2353 
2354 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1
2355 
2356 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010
2357 
2358 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef
2359 
2360 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0
2361 
2362 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2363 
2364 #define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2365 
2366 #ifndef __ASSEMBLY__
2367 
2378 {
2379  uint32_t cfg : 1;
2380  uint32_t bushold : 1;
2381  uint32_t tristate : 1;
2382  uint32_t wkpullup : 1;
2383  uint32_t slew : 1;
2384  uint32_t : 27;
2385 };
2386 
2389 #endif /* __ASSEMBLY__ */
2390 
2392 #define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0
2393 
2445 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0
2446 
2452 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1
2453 
2455 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0
2456 
2457 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0
2458 
2459 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1
2460 
2461 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001
2462 
2463 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe
2464 
2465 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0
2466 
2467 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0)
2468 
2469 #define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001)
2470 
2491 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0
2492 
2497 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1
2498 
2500 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1
2501 
2502 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1
2503 
2504 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1
2505 
2506 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002
2507 
2508 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd
2509 
2510 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0
2511 
2512 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1)
2513 
2514 #define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002)
2515 
2536 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0
2537 
2542 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1
2543 
2545 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2
2546 
2547 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2
2548 
2549 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1
2550 
2551 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004
2552 
2553 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb
2554 
2555 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0
2556 
2557 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2)
2558 
2559 #define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004)
2560 
2582 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0
2583 
2588 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1
2589 
2591 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3
2592 
2593 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3
2594 
2595 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1
2596 
2597 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008
2598 
2599 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7
2600 
2601 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0
2602 
2603 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3)
2604 
2605 #define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008)
2606 
2627 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0
2628 
2633 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1
2634 
2636 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4
2637 
2638 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4
2639 
2640 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1
2641 
2642 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010
2643 
2644 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef
2645 
2646 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0
2647 
2648 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4)
2649 
2650 #define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010)
2651 
2673 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0
2674 
2679 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1
2680 
2682 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5
2683 
2684 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5
2685 
2686 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1
2687 
2688 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020
2689 
2690 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf
2691 
2692 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1
2693 
2694 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5)
2695 
2696 #define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020)
2697 
2718 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0
2719 
2724 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1
2725 
2727 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6
2728 
2729 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6
2730 
2731 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1
2732 
2733 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040
2734 
2735 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf
2736 
2737 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1
2738 
2739 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6)
2740 
2741 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040)
2742 
2763 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0
2764 
2769 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1
2770 
2772 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7
2773 
2774 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7
2775 
2776 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1
2777 
2778 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080
2779 
2780 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f
2781 
2782 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1
2783 
2784 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7)
2785 
2786 #define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080)
2787 
2810 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0
2811 
2817 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1
2818 
2820 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8
2821 
2822 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8
2823 
2824 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1
2825 
2826 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100
2827 
2828 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff
2829 
2830 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0
2831 
2832 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8)
2833 
2834 #define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100)
2835 
2836 #ifndef __ASSEMBLY__
2837 
2848 {
2849  uint32_t cfg : 1;
2850  uint32_t bushold : 1;
2851  uint32_t tristate : 1;
2852  uint32_t wkpullup : 1;
2853  uint32_t slew : 1;
2854  uint32_t dllrst : 1;
2855  uint32_t octrst : 1;
2856  uint32_t regrst : 1;
2857  uint32_t oct_cfgen_calstart : 1;
2858  uint32_t : 23;
2859 };
2860 
2863 #endif /* __ASSEMBLY__ */
2864 
2866 #define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10
2867 
2913 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0
2914 
2921 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1
2922 
2924 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB 0
2925 
2926 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB 0
2927 
2928 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH 1
2929 
2930 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK 0x00000001
2931 
2932 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK 0xfffffffe
2933 
2934 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET 0x0
2935 
2936 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value) (((value) & 0x00000001) >> 0)
2937 
2938 #define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value) (((value) << 0) & 0x00000001)
2939 
2940 #ifndef __ASSEMBLY__
2941 
2952 {
2953  uint32_t vio1 : 1;
2954  uint32_t : 31;
2955 };
2956 
2959 #endif /* __ASSEMBLY__ */
2960 
2962 #define ALT_SYSMGR_FRZCTL_SRC_OFST 0x14
2963 
3010 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQTHAW 0x0
3011 
3016 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_E_REQFRZ 0x1
3017 
3019 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_LSB 0
3020 
3021 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_MSB 0
3022 
3023 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_WIDTH 1
3024 
3025 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET_MSK 0x00000001
3026 
3027 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_CLR_MSK 0xfffffffe
3028 
3029 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_RESET 0x1
3030 
3031 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_GET(value) (((value) & 0x00000001) >> 0)
3032 
3033 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1REQ_SET(value) (((value) << 0) & 0x00000001)
3034 
3066 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED2FROZEN 0x0
3067 
3073 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_THAWED 0x1
3074 
3081 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN 0x2
3082 
3087 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_E_FROZEN2THAWED 0x3
3088 
3090 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_LSB 1
3091 
3092 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_MSB 2
3093 
3094 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_WIDTH 2
3095 
3096 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET_MSK 0x00000006
3097 
3098 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_CLR_MSK 0xfffffff9
3099 
3100 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_RESET 0x2
3101 
3102 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_GET(value) (((value) & 0x00000006) >> 1)
3103 
3104 #define ALT_SYSMGR_FRZCTL_HWCTL_VIO1STATE_SET(value) (((value) << 1) & 0x00000006)
3105 
3106 #ifndef __ASSEMBLY__
3107 
3118 {
3119  uint32_t vio1req : 1;
3120  const uint32_t vio1state : 2;
3121  uint32_t : 29;
3122 };
3123 
3126 #endif /* __ASSEMBLY__ */
3127 
3129 #define ALT_SYSMGR_FRZCTL_HWCTL_OFST 0x18
3130 
3131 #ifndef __ASSEMBLY__
3132 
3143 {
3145  volatile uint32_t _pad_0xc_0xf;
3149  volatile uint32_t _pad_0x1c_0x20;
3150 };
3151 
3156 {
3157  volatile uint32_t vioctrl[3];
3158  volatile uint32_t _pad_0xc_0xf;
3159  volatile uint32_t hioctrl;
3160  volatile uint32_t src;
3161  volatile uint32_t hwctrl;
3162  volatile uint32_t _pad_0x1c_0x20;
3163 };
3164 
3167 #endif /* __ASSEMBLY__ */
3168 
3216 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0
3217 
3222 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1
3223 
3228 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2
3229 
3231 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0
3232 
3233 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1
3234 
3235 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2
3236 
3237 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003
3238 
3239 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc
3240 
3241 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2
3242 
3243 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0)
3244 
3245 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003)
3246 
3270 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0
3271 
3276 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1
3277 
3282 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2
3283 
3285 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2
3286 
3287 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3
3288 
3289 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2
3290 
3291 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c
3292 
3293 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3
3294 
3295 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2
3296 
3297 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2)
3298 
3299 #define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c)
3300 
3323 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0
3324 
3329 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1
3330 
3332 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4
3333 
3334 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4
3335 
3336 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1
3337 
3338 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010
3339 
3340 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef
3341 
3342 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0
3343 
3344 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4)
3345 
3346 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010)
3347 
3370 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0
3371 
3376 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1
3377 
3379 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5
3380 
3381 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5
3382 
3383 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1
3384 
3385 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020
3386 
3387 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf
3388 
3389 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0
3390 
3391 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5)
3392 
3393 #define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020)
3394 
3395 #ifndef __ASSEMBLY__
3396 
3407 {
3408  uint32_t physel_0 : 2;
3409  uint32_t physel_1 : 2;
3410  uint32_t ptpclksel_0 : 1;
3411  uint32_t ptpclksel_1 : 1;
3412  uint32_t : 26;
3413 };
3414 
3417 #endif /* __ASSEMBLY__ */
3418 
3420 #define ALT_SYSMGR_EMAC_CTL_OFST 0x0
3421 
3483 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
3484 
3489 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1
3490 
3495 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
3496 
3501 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3502 
3507 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4
3508 
3513 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5
3514 
3519 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3520 
3525 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3526 
3531 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8
3532 
3537 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9
3538 
3543 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3544 
3549 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3550 
3555 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc
3556 
3561 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd
3562 
3567 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3568 
3573 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3574 
3576 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB 0
3577 
3578 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB 3
3579 
3580 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH 4
3581 
3582 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK 0x0000000f
3583 
3584 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
3585 
3586 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET 0x0
3587 
3588 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
3589 
3590 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
3591 
3631 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0
3632 
3637 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1
3638 
3643 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2
3644 
3649 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3650 
3655 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4
3656 
3661 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5
3662 
3667 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3668 
3673 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3674 
3679 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8
3680 
3685 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9
3686 
3691 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3692 
3697 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3698 
3703 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc
3704 
3709 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd
3710 
3715 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
3716 
3721 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
3722 
3724 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB 4
3725 
3726 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB 7
3727 
3728 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH 4
3729 
3730 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK 0x000000f0
3731 
3732 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK 0xffffff0f
3733 
3734 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET 0x0
3735 
3736 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value) (((value) & 0x000000f0) >> 4)
3737 
3738 #define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value) (((value) << 4) & 0x000000f0)
3739 
3779 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
3780 
3785 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1
3786 
3791 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
3792 
3797 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
3798 
3803 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4
3804 
3809 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5
3810 
3815 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
3816 
3821 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
3822 
3827 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8
3828 
3833 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9
3834 
3839 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
3840 
3845 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
3846 
3851 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc
3852 
3857 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd
3858 
3863 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
3864 
3869 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
3870 
3872 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB 8
3873 
3874 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB 11
3875 
3876 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH 4
3877 
3878 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK 0x00000f00
3879 
3880 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK 0xfffff0ff
3881 
3882 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET 0x0
3883 
3884 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value) (((value) & 0x00000f00) >> 8)
3885 
3886 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value) (((value) << 8) & 0x00000f00)
3887 
3927 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0
3928 
3933 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1
3934 
3939 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2
3940 
3945 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3
3946 
3951 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4
3952 
3957 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5
3958 
3963 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6
3964 
3969 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7
3970 
3975 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8
3976 
3981 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9
3982 
3987 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa
3988 
3993 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb
3994 
3999 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc
4000 
4005 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd
4006 
4011 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe
4012 
4017 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf
4018 
4020 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB 12
4021 
4022 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB 15
4023 
4024 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH 4
4025 
4026 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK 0x0000f000
4027 
4028 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK 0xffff0fff
4029 
4030 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET 0x0
4031 
4032 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value) (((value) & 0x0000f000) >> 12)
4033 
4034 #define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value) (((value) << 12) & 0x0000f000)
4035 
4036 #ifndef __ASSEMBLY__
4037 
4048 {
4049  uint32_t arcache_0 : 4;
4050  uint32_t arcache_1 : 4;
4051  uint32_t awcache_0 : 4;
4052  uint32_t awcache_1 : 4;
4053  uint32_t : 16;
4054 };
4055 
4058 #endif /* __ASSEMBLY__ */
4059 
4061 #define ALT_SYSMGR_EMAC_L3MST_OFST 0x4
4062 
4063 #ifndef __ASSEMBLY__
4064 
4075 {
4078  volatile uint32_t _pad_0x8_0x10[2];
4079 };
4080 
4082 typedef volatile struct ALT_SYSMGR_EMAC_s ALT_SYSMGR_EMAC_t;
4085 {
4086  volatile uint32_t ctrl;
4087  volatile uint32_t l3master;
4088  volatile uint32_t _pad_0x8_0x10[2];
4089 };
4090 
4093 #endif /* __ASSEMBLY__ */
4094 
4149 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0
4150 
4155 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1
4156 
4158 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0
4159 
4160 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0
4161 
4162 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1
4163 
4164 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001
4165 
4166 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe
4167 
4168 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0
4169 
4170 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
4171 
4172 #define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
4173 
4196 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0
4197 
4202 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1
4203 
4205 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1
4206 
4207 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1
4208 
4209 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1
4210 
4211 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002
4212 
4213 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd
4214 
4215 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0
4216 
4217 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1)
4218 
4219 #define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002)
4220 
4243 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0
4244 
4249 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1
4250 
4252 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2
4253 
4254 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2
4255 
4256 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1
4257 
4258 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004
4259 
4260 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb
4261 
4262 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0
4263 
4264 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2)
4265 
4266 #define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004)
4267 
4290 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0
4291 
4296 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1
4297 
4299 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3
4300 
4301 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3
4302 
4303 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1
4304 
4305 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008
4306 
4307 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7
4308 
4309 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0
4310 
4311 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3)
4312 
4313 #define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008)
4314 
4330 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4
4331 
4332 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4
4333 
4334 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1
4335 
4336 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010
4337 
4338 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef
4339 
4340 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0
4341 
4342 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4)
4343 
4344 #define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010)
4345 
4360 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5
4361 
4362 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12
4363 
4364 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8
4365 
4366 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0
4367 
4368 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f
4369 
4370 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0
4371 
4372 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5)
4373 
4374 #define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0)
4375 
4376 #ifndef __ASSEMBLY__
4377 
4388 {
4389  uint32_t chansel_0 : 1;
4390  uint32_t chansel_1 : 1;
4391  uint32_t chansel_2 : 1;
4392  uint32_t chansel_3 : 1;
4393  uint32_t mgrnonsecure : 1;
4394  uint32_t irqnonsecure : 8;
4395  uint32_t : 19;
4396 };
4397 
4400 #endif /* __ASSEMBLY__ */
4401 
4403 #define ALT_SYSMGR_DMA_CTL_OFST 0x0
4404 
4437 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_LSB 0
4438 
4439 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_MSB 31
4440 
4441 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_WIDTH 32
4442 
4443 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET_MSK 0xffffffff
4444 
4445 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_CLR_MSK 0x00000000
4446 
4447 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_RESET 0x0
4448 
4449 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_GET(value) (((value) & 0xffffffff) >> 0)
4450 
4451 #define ALT_SYSMGR_DMA_PERSECURITY_NONSECURE_SET(value) (((value) << 0) & 0xffffffff)
4452 
4453 #ifndef __ASSEMBLY__
4454 
4465 {
4466  uint32_t nonsecure : 32;
4467 };
4468 
4471 #endif /* __ASSEMBLY__ */
4472 
4474 #define ALT_SYSMGR_DMA_PERSECURITY_OFST 0x4
4475 
4476 #ifndef __ASSEMBLY__
4477 
4488 {
4491 };
4492 
4494 typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
4497 {
4498  volatile uint32_t ctrl;
4499  volatile uint32_t persecurity;
4500 };
4501 
4504 #endif /* __ASSEMBLY__ */
4505 
4539 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_LSB 0
4540 
4541 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_MSB 31
4542 
4543 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_WIDTH 32
4544 
4545 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET_MSK 0xffffffff
4546 
4547 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_CLR_MSK 0x00000000
4548 
4549 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_RESET 0x0
4550 
4551 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4552 
4553 #define ALT_SYSMGR_ISW_HANDOFF_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4554 
4555 #ifndef __ASSEMBLY__
4556 
4567 {
4568  uint32_t value : 32;
4569 };
4570 
4573 #endif /* __ASSEMBLY__ */
4574 
4576 #define ALT_SYSMGR_ISW_HANDOFF_OFST 0x0
4577 
4578 #ifndef __ASSEMBLY__
4579 
4590 {
4592 };
4593 
4595 typedef volatile struct ALT_SYSMGR_ISW_s ALT_SYSMGR_ISW_t;
4598 {
4599  volatile uint32_t handoff[8];
4600 };
4601 
4604 #endif /* __ASSEMBLY__ */
4605 
4655 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
4656 
4661 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
4662 
4664 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
4665 
4666 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
4667 
4668 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
4669 
4670 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
4671 
4672 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
4673 
4674 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
4675 
4676 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
4677 
4678 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
4679 
4706 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
4707 
4712 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
4713 
4715 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
4716 
4717 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
4718 
4719 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
4720 
4721 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
4722 
4723 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
4724 
4725 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
4726 
4727 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
4728 
4729 #define ALT_SYSMGR_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
4730 
4731 #ifndef __ASSEMBLY__
4732 
4743 {
4744  uint32_t warmrstcfgpinmux : 1;
4745  uint32_t warmrstcfgio : 1;
4746  uint32_t : 30;
4747 };
4748 
4751 #endif /* __ASSEMBLY__ */
4752 
4754 #define ALT_SYSMGR_ROMCODE_CTL_OFST 0x0
4755 
4780 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB 0
4781 
4782 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB 31
4783 
4784 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH 32
4785 
4786 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK 0xffffffff
4787 
4788 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK 0x00000000
4789 
4790 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET 0x0
4791 
4792 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4793 
4794 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4795 
4796 #ifndef __ASSEMBLY__
4797 
4808 {
4809  uint32_t value : 32;
4810 };
4811 
4814 #endif /* __ASSEMBLY__ */
4815 
4817 #define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST 0x4
4818 
4851 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
4852 
4856 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
4857 
4859 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_LSB 0
4860 
4861 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_MSB 31
4862 
4863 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
4864 
4865 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
4866 
4867 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
4868 
4869 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
4870 
4871 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4872 
4873 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4874 
4875 #ifndef __ASSEMBLY__
4876 
4887 {
4888  uint32_t value : 32;
4889 };
4890 
4893 #endif /* __ASSEMBLY__ */
4894 
4896 #define ALT_SYSMGR_ROMCODE_INITSWSTATE_OFST 0x8
4897 
4921 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_LSB 0
4922 
4923 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_MSB 1
4924 
4925 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
4926 
4927 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
4928 
4929 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
4930 
4931 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
4932 
4933 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
4934 
4935 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
4936 
4937 #ifndef __ASSEMBLY__
4938 
4949 {
4950  uint32_t index : 2;
4951  uint32_t : 30;
4952 };
4953 
4956 #endif /* __ASSEMBLY__ */
4957 
4959 #define ALT_SYSMGR_ROMCODE_INITSWLASTLD_OFST 0xc
4960 
4983 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
4984 
4985 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
4986 
4987 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
4988 
4989 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
4990 
4991 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
4992 
4993 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
4994 
4995 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4996 
4997 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4998 
4999 #ifndef __ASSEMBLY__
5000 
5011 {
5012  uint32_t value : 32;
5013 };
5014 
5017 #endif /* __ASSEMBLY__ */
5018 
5020 #define ALT_SYSMGR_ROMCODE_BOOTROMSWSTATE_OFST 0x10
5021 
5069 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_DISD 0x0
5070 
5075 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_E_END 0xae9efebc
5076 
5078 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_LSB 0
5079 
5080 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_MSB 31
5081 
5082 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_WIDTH 32
5083 
5084 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
5085 
5086 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
5087 
5088 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_RESET 0x0
5089 
5090 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
5091 
5092 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
5093 
5094 #ifndef __ASSEMBLY__
5095 
5106 {
5107  uint32_t magic : 32;
5108 };
5109 
5112 #endif /* __ASSEMBLY__ */
5113 
5115 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST 0x0
5116 
5117 #define ALT_SYSMGR_ROMCODE_WARMRAM_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EN_OFST))
5118 
5144 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_LSB 0
5145 
5146 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_MSB 15
5147 
5148 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_WIDTH 16
5149 
5150 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET_MSK 0x0000ffff
5151 
5152 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_CLR_MSK 0xffff0000
5153 
5154 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_RESET 0x0
5155 
5156 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5157 
5158 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5159 
5160 #ifndef __ASSEMBLY__
5161 
5172 {
5173  uint32_t offset : 16;
5174  uint32_t : 16;
5175 };
5176 
5179 #endif /* __ASSEMBLY__ */
5180 
5182 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST 0x4
5183 
5184 #define ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_DATASTART_OFST))
5185 
5219 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_LSB 0
5220 
5221 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_MSB 15
5222 
5223 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_WIDTH 16
5224 
5225 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET_MSK 0x0000ffff
5226 
5227 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_CLR_MSK 0xffff0000
5228 
5229 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_RESET 0x0
5230 
5231 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
5232 
5233 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
5234 
5235 #ifndef __ASSEMBLY__
5236 
5247 {
5248  uint32_t size : 16;
5249  uint32_t : 16;
5250 };
5251 
5254 #endif /* __ASSEMBLY__ */
5255 
5257 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST 0x8
5258 
5259 #define ALT_SYSMGR_ROMCODE_WARMRAM_LEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_LEN_OFST))
5260 
5286 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_LSB 0
5287 
5288 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_MSB 15
5289 
5290 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_WIDTH 16
5291 
5292 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET_MSK 0x0000ffff
5293 
5294 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0xffff0000
5295 
5296 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_RESET 0x0
5297 
5298 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0x0000ffff) >> 0)
5299 
5300 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0x0000ffff)
5301 
5302 #ifndef __ASSEMBLY__
5303 
5314 {
5315  uint32_t offset : 16;
5316  uint32_t : 16;
5317 };
5318 
5321 #endif /* __ASSEMBLY__ */
5322 
5324 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST 0xc
5325 
5326 #define ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_EXECUTION_OFST))
5327 
5364 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_LSB 0
5365 
5366 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_MSB 31
5367 
5368 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_WIDTH 32
5369 
5370 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
5371 
5372 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
5373 
5374 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_RESET 0xe763552a
5375 
5376 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
5377 
5378 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
5379 
5380 #ifndef __ASSEMBLY__
5381 
5392 {
5393  uint32_t expected : 32;
5394 };
5395 
5398 #endif /* __ASSEMBLY__ */
5399 
5401 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST 0x10
5402 
5403 #define ALT_SYSMGR_ROMCODE_WARMRAM_CRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SYSMGR_ROMCODE_WARMRAM_CRC_OFST))
5404 
5405 #ifndef __ASSEMBLY__
5406 
5417 {
5423  volatile uint32_t _pad_0x14_0x20[3];
5424 };
5425 
5430 {
5431  volatile uint32_t enable;
5432  volatile uint32_t datastart;
5433  volatile uint32_t length;
5434  volatile uint32_t execution;
5435  volatile uint32_t crc;
5436  volatile uint32_t _pad_0x14_0x20[3];
5437 };
5438 
5441 #endif /* __ASSEMBLY__ */
5442 
5444 #ifndef __ASSEMBLY__
5445 
5456 {
5462  volatile uint32_t _pad_0x14_0x1f[3];
5464 };
5465 
5470 {
5471  volatile uint32_t ctrl;
5472  volatile uint32_t cpu1startaddr;
5473  volatile uint32_t initswstate;
5474  volatile uint32_t initswlastld;
5475  volatile uint32_t bootromswstate;
5476  volatile uint32_t _pad_0x14_0x1f[3];
5478 };
5479 
5482 #endif /* __ASSEMBLY__ */
5483 
5533 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0
5534 
5539 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1
5540 
5542 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0
5543 
5544 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0
5545 
5546 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1
5547 
5548 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
5549 
5550 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
5551 
5552 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0
5553 
5554 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
5555 
5556 #define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
5557 
5585 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0
5586 
5594 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1
5595 
5597 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1
5598 
5599 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1
5600 
5601 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1
5602 
5603 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002
5604 
5605 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd
5606 
5607 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1
5608 
5609 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1)
5610 
5611 #define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002)
5612 
5613 #ifndef __ASSEMBLY__
5614 
5625 {
5626  uint32_t waitstate : 1;
5627  uint32_t ensfmdwru : 1;
5628  uint32_t : 30;
5629 };
5630 
5633 #endif /* __ASSEMBLY__ */
5634 
5636 #define ALT_SYSMGR_ROMHW_CTL_OFST 0x0
5637 
5638 #ifndef __ASSEMBLY__
5639 
5650 {
5652 };
5653 
5655 typedef volatile struct ALT_SYSMGR_ROMHW_s ALT_SYSMGR_ROMHW_t;
5658 {
5659  volatile uint32_t ctrl;
5660 };
5661 
5664 #endif /* __ASSEMBLY__ */
5665 
5717 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES0 0x0
5718 
5723 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES45 0x1
5724 
5729 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES90 0x2
5730 
5735 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES135 0x3
5736 
5741 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES180 0x4
5742 
5747 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES225 0x5
5748 
5753 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES270 0x6
5754 
5759 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_E_DEGREES315 0x7
5760 
5762 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_LSB 0
5763 
5764 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_MSB 2
5765 
5766 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_WIDTH 3
5767 
5768 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET_MSK 0x00000007
5769 
5770 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_CLR_MSK 0xfffffff8
5771 
5772 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_RESET 0x0
5773 
5774 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
5775 
5776 #define ALT_SYSMGR_SDMMC_CTL_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
5777 
5804 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES0 0x0
5805 
5810 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES45 0x1
5811 
5816 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES90 0x2
5817 
5822 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES135 0x3
5823 
5828 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES180 0x4
5829 
5834 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES225 0x5
5835 
5840 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES270 0x6
5841 
5846 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_E_DEGREES315 0x7
5847 
5849 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_LSB 3
5850 
5851 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_MSB 5
5852 
5853 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_WIDTH 3
5854 
5855 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET_MSK 0x00000038
5856 
5857 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_CLR_MSK 0xffffffc7
5858 
5859 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_RESET 0x0
5860 
5861 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_GET(value) (((value) & 0x00000038) >> 3)
5862 
5863 #define ALT_SYSMGR_SDMMC_CTL_SMPLSEL_SET(value) (((value) << 3) & 0x00000038)
5864 
5882 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_LSB 6
5883 
5884 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_MSB 6
5885 
5886 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_WIDTH 1
5887 
5888 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET_MSK 0x00000040
5889 
5890 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_CLR_MSK 0xffffffbf
5891 
5892 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_RESET 0x0
5893 
5894 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_GET(value) (((value) & 0x00000040) >> 6)
5895 
5896 #define ALT_SYSMGR_SDMMC_CTL_FBCLKSEL_SET(value) (((value) << 6) & 0x00000040)
5897 
5898 #ifndef __ASSEMBLY__
5899 
5910 {
5911  uint32_t drvsel : 3;
5912  uint32_t smplsel : 3;
5913  uint32_t fbclksel : 1;
5914  uint32_t : 25;
5915 };
5916 
5919 #endif /* __ASSEMBLY__ */
5920 
5922 #define ALT_SYSMGR_SDMMC_CTL_OFST 0x0
5923 
5966 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_OPCODE 0x0
5967 
5972 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_E_DATA 0x1
5973 
5975 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_LSB 0
5976 
5977 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_MSB 0
5978 
5979 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_WIDTH 1
5980 
5981 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET_MSK 0x00000001
5982 
5983 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
5984 
5985 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_RESET 0x1
5986 
5987 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
5988 
5989 #define ALT_SYSMGR_SDMMC_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
5990 
6000 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_LSB 1
6001 
6002 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_MSB 1
6003 
6004 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_WIDTH 1
6005 
6006 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET_MSK 0x00000002
6007 
6008 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffd
6009 
6010 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_RESET 0x1
6011 
6012 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000002) >> 1)
6013 
6014 #define ALT_SYSMGR_SDMMC_L3MST_HPROTPRIV_0_SET(value) (((value) << 1) & 0x00000002)
6015 
6025 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_LSB 2
6026 
6027 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_MSB 2
6028 
6029 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_WIDTH 1
6030 
6031 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET_MSK 0x00000004
6032 
6033 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_CLR_MSK 0xfffffffb
6034 
6035 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_RESET 0x0
6036 
6037 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000004) >> 2)
6038 
6039 #define ALT_SYSMGR_SDMMC_L3MST_HPROTBUFF_0_SET(value) (((value) << 2) & 0x00000004)
6040 
6050 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_LSB 3
6051 
6052 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_MSB 3
6053 
6054 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_WIDTH 1
6055 
6056 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET_MSK 0x00000008
6057 
6058 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_CLR_MSK 0xfffffff7
6059 
6060 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_RESET 0x0
6061 
6062 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000008) >> 3)
6063 
6064 #define ALT_SYSMGR_SDMMC_L3MST_HPROTCACHE_0_SET(value) (((value) << 3) & 0x00000008)
6065 
6066 #ifndef __ASSEMBLY__
6067 
6078 {
6079  uint32_t hprotdata_0 : 1;
6080  uint32_t hprotpriv_0 : 1;
6081  uint32_t hprotbuff_0 : 1;
6082  uint32_t hprotcache_0 : 1;
6083  uint32_t : 28;
6084 };
6085 
6088 #endif /* __ASSEMBLY__ */
6089 
6091 #define ALT_SYSMGR_SDMMC_L3MST_OFST 0x4
6092 
6093 #ifndef __ASSEMBLY__
6094 
6105 {
6108 };
6109 
6111 typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
6114 {
6115  volatile uint32_t ctrl;
6116  volatile uint32_t l3master;
6117 };
6118 
6121 #endif /* __ASSEMBLY__ */
6122 
6161 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
6162 
6163 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
6164 
6165 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
6166 
6167 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
6168 
6169 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
6170 
6171 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
6172 
6173 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
6174 
6175 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
6176 
6186 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 1
6187 
6188 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 1
6189 
6190 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
6191 
6192 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x00000002
6193 
6194 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfffffffd
6195 
6196 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
6197 
6198 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x00000002) >> 1)
6199 
6200 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 1) & 0x00000002)
6201 
6212 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 2
6213 
6214 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 2
6215 
6216 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
6217 
6218 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000004
6219 
6220 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffffb
6221 
6222 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
6223 
6224 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000004) >> 2)
6225 
6226 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 2) & 0x00000004)
6227 
6238 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 3
6239 
6240 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 3
6241 
6242 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
6243 
6244 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00000008
6245 
6246 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffffff7
6247 
6248 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
6249 
6250 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00000008) >> 3)
6251 
6252 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 3) & 0x00000008)
6253 
6254 #ifndef __ASSEMBLY__
6255 
6266 {
6267  uint32_t noinit : 1;
6268  uint32_t page512 : 1;
6269  uint32_t noloadb0p0 : 1;
6270  uint32_t tworowaddr : 1;
6271  uint32_t : 28;
6272 };
6273 
6276 #endif /* __ASSEMBLY__ */
6277 
6279 #define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x0
6280 
6338 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
6339 
6344 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
6345 
6350 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
6351 
6356 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6357 
6362 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
6363 
6368 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
6369 
6374 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6375 
6380 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6381 
6386 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
6387 
6392 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
6393 
6398 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6399 
6404 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6405 
6410 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
6411 
6416 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
6417 
6422 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6423 
6428 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6429 
6431 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
6432 
6433 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
6434 
6435 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
6436 
6437 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
6438 
6439 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
6440 
6441 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
6442 
6443 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
6444 
6445 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
6446 
6484 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
6485 
6490 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
6491 
6496 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
6497 
6502 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
6503 
6508 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
6509 
6514 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
6515 
6520 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
6521 
6526 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
6527 
6532 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
6533 
6538 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
6539 
6544 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
6545 
6550 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
6551 
6556 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
6557 
6562 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
6563 
6568 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
6569 
6574 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
6575 
6577 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
6578 
6579 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
6580 
6581 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
6582 
6583 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
6584 
6585 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
6586 
6587 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
6588 
6589 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
6590 
6591 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
6592 
6593 #ifndef __ASSEMBLY__
6594 
6605 {
6606  uint32_t arcache_0 : 4;
6607  uint32_t awcache_0 : 4;
6608  uint32_t : 24;
6609 };
6610 
6613 #endif /* __ASSEMBLY__ */
6614 
6616 #define ALT_SYSMGR_NAND_L3MST_OFST 0x4
6617 
6618 #ifndef __ASSEMBLY__
6619 
6630 {
6633 };
6634 
6636 typedef volatile struct ALT_SYSMGR_NAND_s ALT_SYSMGR_NAND_t;
6639 {
6640  volatile uint32_t bootstrap;
6641  volatile uint32_t l3master;
6642 };
6643 
6646 #endif /* __ASSEMBLY__ */
6647 
6705 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_OPCODE 0x0
6706 
6711 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_E_DATA 0x1
6712 
6714 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_LSB 0
6715 
6716 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_MSB 0
6717 
6718 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_WIDTH 1
6719 
6720 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET_MSK 0x00000001
6721 
6722 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_CLR_MSK 0xfffffffe
6723 
6724 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_RESET 0x1
6725 
6726 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_GET(value) (((value) & 0x00000001) >> 0)
6727 
6728 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_0_SET(value) (((value) << 0) & 0x00000001)
6729 
6752 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_OPCODE 0x0
6753 
6758 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_E_DATA 0x1
6759 
6761 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_LSB 1
6762 
6763 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_MSB 1
6764 
6765 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_WIDTH 1
6766 
6767 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET_MSK 0x00000002
6768 
6769 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_CLR_MSK 0xfffffffd
6770 
6771 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_RESET 0x1
6772 
6773 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_GET(value) (((value) & 0x00000002) >> 1)
6774 
6775 #define ALT_SYSMGR_USB_L3MST_HPROTDATA_1_SET(value) (((value) << 1) & 0x00000002)
6776 
6788 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_LSB 2
6789 
6790 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_MSB 2
6791 
6792 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_WIDTH 1
6793 
6794 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET_MSK 0x00000004
6795 
6796 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_CLR_MSK 0xfffffffb
6797 
6798 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_RESET 0x1
6799 
6800 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_GET(value) (((value) & 0x00000004) >> 2)
6801 
6802 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_0_SET(value) (((value) << 2) & 0x00000004)
6803 
6815 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_LSB 3
6816 
6817 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_MSB 3
6818 
6819 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_WIDTH 1
6820 
6821 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET_MSK 0x00000008
6822 
6823 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_CLR_MSK 0xfffffff7
6824 
6825 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_RESET 0x1
6826 
6827 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_GET(value) (((value) & 0x00000008) >> 3)
6828 
6829 #define ALT_SYSMGR_USB_L3MST_HPROTPRIV_1_SET(value) (((value) << 3) & 0x00000008)
6830 
6842 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_LSB 4
6843 
6844 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_MSB 4
6845 
6846 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_WIDTH 1
6847 
6848 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET_MSK 0x00000010
6849 
6850 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_CLR_MSK 0xffffffef
6851 
6852 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_RESET 0x0
6853 
6854 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_GET(value) (((value) & 0x00000010) >> 4)
6855 
6856 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_0_SET(value) (((value) << 4) & 0x00000010)
6857 
6869 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_LSB 5
6870 
6871 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_MSB 5
6872 
6873 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_WIDTH 1
6874 
6875 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET_MSK 0x00000020
6876 
6877 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_CLR_MSK 0xffffffdf
6878 
6879 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_RESET 0x0
6880 
6881 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_GET(value) (((value) & 0x00000020) >> 5)
6882 
6883 #define ALT_SYSMGR_USB_L3MST_HPROTBUFF_1_SET(value) (((value) << 5) & 0x00000020)
6884 
6896 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_LSB 6
6897 
6898 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_MSB 6
6899 
6900 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_WIDTH 1
6901 
6902 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET_MSK 0x00000040
6903 
6904 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_CLR_MSK 0xffffffbf
6905 
6906 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_RESET 0x0
6907 
6908 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_GET(value) (((value) & 0x00000040) >> 6)
6909 
6910 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_0_SET(value) (((value) << 6) & 0x00000040)
6911 
6923 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_LSB 7
6924 
6925 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_MSB 7
6926 
6927 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_WIDTH 1
6928 
6929 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET_MSK 0x00000080
6930 
6931 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_CLR_MSK 0xffffff7f
6932 
6933 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_RESET 0x0
6934 
6935 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_GET(value) (((value) & 0x00000080) >> 7)
6936 
6937 #define ALT_SYSMGR_USB_L3MST_HPROTCACHE_1_SET(value) (((value) << 7) & 0x00000080)
6938 
6939 #ifndef __ASSEMBLY__
6940 
6951 {
6952  uint32_t hprotdata_0 : 1;
6953  uint32_t hprotdata_1 : 1;
6954  uint32_t hprotpriv_0 : 1;
6955  uint32_t hprotpriv_1 : 1;
6956  uint32_t hprotbuff_0 : 1;
6957  uint32_t hprotbuff_1 : 1;
6958  uint32_t hprotcache_0 : 1;
6959  uint32_t hprotcache_1 : 1;
6960  uint32_t : 24;
6961 };
6962 
6965 #endif /* __ASSEMBLY__ */
6966 
6968 #define ALT_SYSMGR_USB_L3MST_OFST 0x0
6969 
6970 #ifndef __ASSEMBLY__
6971 
6982 {
6984 };
6985 
6987 typedef volatile struct ALT_SYSMGR_USB_s ALT_SYSMGR_USB_t;
6990 {
6991  volatile uint32_t l3master;
6992 };
6993 
6996 #endif /* __ASSEMBLY__ */
6997 
7034 #define ALT_SYSMGR_ECC_L2_EN_LSB 0
7035 
7036 #define ALT_SYSMGR_ECC_L2_EN_MSB 0
7037 
7038 #define ALT_SYSMGR_ECC_L2_EN_WIDTH 1
7039 
7040 #define ALT_SYSMGR_ECC_L2_EN_SET_MSK 0x00000001
7041 
7042 #define ALT_SYSMGR_ECC_L2_EN_CLR_MSK 0xfffffffe
7043 
7044 #define ALT_SYSMGR_ECC_L2_EN_RESET 0x0
7045 
7046 #define ALT_SYSMGR_ECC_L2_EN_GET(value) (((value) & 0x00000001) >> 0)
7047 
7048 #define ALT_SYSMGR_ECC_L2_EN_SET(value) (((value) << 0) & 0x00000001)
7049 
7060 #define ALT_SYSMGR_ECC_L2_INJS_LSB 1
7061 
7062 #define ALT_SYSMGR_ECC_L2_INJS_MSB 1
7063 
7064 #define ALT_SYSMGR_ECC_L2_INJS_WIDTH 1
7065 
7066 #define ALT_SYSMGR_ECC_L2_INJS_SET_MSK 0x00000002
7067 
7068 #define ALT_SYSMGR_ECC_L2_INJS_CLR_MSK 0xfffffffd
7069 
7070 #define ALT_SYSMGR_ECC_L2_INJS_RESET 0x0
7071 
7072 #define ALT_SYSMGR_ECC_L2_INJS_GET(value) (((value) & 0x00000002) >> 1)
7073 
7074 #define ALT_SYSMGR_ECC_L2_INJS_SET(value) (((value) << 1) & 0x00000002)
7075 
7086 #define ALT_SYSMGR_ECC_L2_INJD_LSB 2
7087 
7088 #define ALT_SYSMGR_ECC_L2_INJD_MSB 2
7089 
7090 #define ALT_SYSMGR_ECC_L2_INJD_WIDTH 1
7091 
7092 #define ALT_SYSMGR_ECC_L2_INJD_SET_MSK 0x00000004
7093 
7094 #define ALT_SYSMGR_ECC_L2_INJD_CLR_MSK 0xfffffffb
7095 
7096 #define ALT_SYSMGR_ECC_L2_INJD_RESET 0x0
7097 
7098 #define ALT_SYSMGR_ECC_L2_INJD_GET(value) (((value) & 0x00000004) >> 2)
7099 
7100 #define ALT_SYSMGR_ECC_L2_INJD_SET(value) (((value) << 2) & 0x00000004)
7101 
7102 #ifndef __ASSEMBLY__
7103 
7114 {
7115  uint32_t en : 1;
7116  uint32_t injs : 1;
7117  uint32_t injd : 1;
7118  uint32_t : 29;
7119 };
7120 
7123 #endif /* __ASSEMBLY__ */
7124 
7126 #define ALT_SYSMGR_ECC_L2_OFST 0x0
7127 
7158 #define ALT_SYSMGR_ECC_OCRAM_EN_LSB 0
7159 
7160 #define ALT_SYSMGR_ECC_OCRAM_EN_MSB 0
7161 
7162 #define ALT_SYSMGR_ECC_OCRAM_EN_WIDTH 1
7163 
7164 #define ALT_SYSMGR_ECC_OCRAM_EN_SET_MSK 0x00000001
7165 
7166 #define ALT_SYSMGR_ECC_OCRAM_EN_CLR_MSK 0xfffffffe
7167 
7168 #define ALT_SYSMGR_ECC_OCRAM_EN_RESET 0x0
7169 
7170 #define ALT_SYSMGR_ECC_OCRAM_EN_GET(value) (((value) & 0x00000001) >> 0)
7171 
7172 #define ALT_SYSMGR_ECC_OCRAM_EN_SET(value) (((value) << 0) & 0x00000001)
7173 
7184 #define ALT_SYSMGR_ECC_OCRAM_INJS_LSB 1
7185 
7186 #define ALT_SYSMGR_ECC_OCRAM_INJS_MSB 1
7187 
7188 #define ALT_SYSMGR_ECC_OCRAM_INJS_WIDTH 1
7189 
7190 #define ALT_SYSMGR_ECC_OCRAM_INJS_SET_MSK 0x00000002
7191 
7192 #define ALT_SYSMGR_ECC_OCRAM_INJS_CLR_MSK 0xfffffffd
7193 
7194 #define ALT_SYSMGR_ECC_OCRAM_INJS_RESET 0x0
7195 
7196 #define ALT_SYSMGR_ECC_OCRAM_INJS_GET(value) (((value) & 0x00000002) >> 1)
7197 
7198 #define ALT_SYSMGR_ECC_OCRAM_INJS_SET(value) (((value) << 1) & 0x00000002)
7199 
7210 #define ALT_SYSMGR_ECC_OCRAM_INJD_LSB 2
7211 
7212 #define ALT_SYSMGR_ECC_OCRAM_INJD_MSB 2
7213 
7214 #define ALT_SYSMGR_ECC_OCRAM_INJD_WIDTH 1
7215 
7216 #define ALT_SYSMGR_ECC_OCRAM_INJD_SET_MSK 0x00000004
7217 
7218 #define ALT_SYSMGR_ECC_OCRAM_INJD_CLR_MSK 0xfffffffb
7219 
7220 #define ALT_SYSMGR_ECC_OCRAM_INJD_RESET 0x0
7221 
7222 #define ALT_SYSMGR_ECC_OCRAM_INJD_GET(value) (((value) & 0x00000004) >> 2)
7223 
7224 #define ALT_SYSMGR_ECC_OCRAM_INJD_SET(value) (((value) << 2) & 0x00000004)
7225 
7237 #define ALT_SYSMGR_ECC_OCRAM_SERR_LSB 3
7238 
7239 #define ALT_SYSMGR_ECC_OCRAM_SERR_MSB 3
7240 
7241 #define ALT_SYSMGR_ECC_OCRAM_SERR_WIDTH 1
7242 
7243 #define ALT_SYSMGR_ECC_OCRAM_SERR_SET_MSK 0x00000008
7244 
7245 #define ALT_SYSMGR_ECC_OCRAM_SERR_CLR_MSK 0xfffffff7
7246 
7247 #define ALT_SYSMGR_ECC_OCRAM_SERR_RESET 0x0
7248 
7249 #define ALT_SYSMGR_ECC_OCRAM_SERR_GET(value) (((value) & 0x00000008) >> 3)
7250 
7251 #define ALT_SYSMGR_ECC_OCRAM_SERR_SET(value) (((value) << 3) & 0x00000008)
7252 
7265 #define ALT_SYSMGR_ECC_OCRAM_DERR_LSB 4
7266 
7267 #define ALT_SYSMGR_ECC_OCRAM_DERR_MSB 4
7268 
7269 #define ALT_SYSMGR_ECC_OCRAM_DERR_WIDTH 1
7270 
7271 #define ALT_SYSMGR_ECC_OCRAM_DERR_SET_MSK 0x00000010
7272 
7273 #define ALT_SYSMGR_ECC_OCRAM_DERR_CLR_MSK 0xffffffef
7274 
7275 #define ALT_SYSMGR_ECC_OCRAM_DERR_RESET 0x0
7276 
7277 #define ALT_SYSMGR_ECC_OCRAM_DERR_GET(value) (((value) & 0x00000010) >> 4)
7278 
7279 #define ALT_SYSMGR_ECC_OCRAM_DERR_SET(value) (((value) << 4) & 0x00000010)
7280 
7281 #ifndef __ASSEMBLY__
7282 
7293 {
7294  uint32_t en : 1;
7295  uint32_t injs : 1;
7296  uint32_t injd : 1;
7297  uint32_t serr : 1;
7298  uint32_t derr : 1;
7299  uint32_t : 27;
7300 };
7301 
7304 #endif /* __ASSEMBLY__ */
7305 
7307 #define ALT_SYSMGR_ECC_OCRAM_OFST 0x4
7308 
7339 #define ALT_SYSMGR_ECC_USB0_EN_LSB 0
7340 
7341 #define ALT_SYSMGR_ECC_USB0_EN_MSB 0
7342 
7343 #define ALT_SYSMGR_ECC_USB0_EN_WIDTH 1
7344 
7345 #define ALT_SYSMGR_ECC_USB0_EN_SET_MSK 0x00000001
7346 
7347 #define ALT_SYSMGR_ECC_USB0_EN_CLR_MSK 0xfffffffe
7348 
7349 #define ALT_SYSMGR_ECC_USB0_EN_RESET 0x0
7350 
7351 #define ALT_SYSMGR_ECC_USB0_EN_GET(value) (((value) & 0x00000001) >> 0)
7352 
7353 #define ALT_SYSMGR_ECC_USB0_EN_SET(value) (((value) << 0) & 0x00000001)
7354 
7365 #define ALT_SYSMGR_ECC_USB0_INJS_LSB 1
7366 
7367 #define ALT_SYSMGR_ECC_USB0_INJS_MSB 1
7368 
7369 #define ALT_SYSMGR_ECC_USB0_INJS_WIDTH 1
7370 
7371 #define ALT_SYSMGR_ECC_USB0_INJS_SET_MSK 0x00000002
7372 
7373 #define ALT_SYSMGR_ECC_USB0_INJS_CLR_MSK 0xfffffffd
7374 
7375 #define ALT_SYSMGR_ECC_USB0_INJS_RESET 0x0
7376 
7377 #define ALT_SYSMGR_ECC_USB0_INJS_GET(value) (((value) & 0x00000002) >> 1)
7378 
7379 #define ALT_SYSMGR_ECC_USB0_INJS_SET(value) (((value) << 1) & 0x00000002)
7380 
7391 #define ALT_SYSMGR_ECC_USB0_INJD_LSB 2
7392 
7393 #define ALT_SYSMGR_ECC_USB0_INJD_MSB 2
7394 
7395 #define ALT_SYSMGR_ECC_USB0_INJD_WIDTH 1
7396 
7397 #define ALT_SYSMGR_ECC_USB0_INJD_SET_MSK 0x00000004
7398 
7399 #define ALT_SYSMGR_ECC_USB0_INJD_CLR_MSK 0xfffffffb
7400 
7401 #define ALT_SYSMGR_ECC_USB0_INJD_RESET 0x0
7402 
7403 #define ALT_SYSMGR_ECC_USB0_INJD_GET(value) (((value) & 0x00000004) >> 2)
7404 
7405 #define ALT_SYSMGR_ECC_USB0_INJD_SET(value) (((value) << 2) & 0x00000004)
7406 
7418 #define ALT_SYSMGR_ECC_USB0_SERR_LSB 3
7419 
7420 #define ALT_SYSMGR_ECC_USB0_SERR_MSB 3
7421 
7422 #define ALT_SYSMGR_ECC_USB0_SERR_WIDTH 1
7423 
7424 #define ALT_SYSMGR_ECC_USB0_SERR_SET_MSK 0x00000008
7425 
7426 #define ALT_SYSMGR_ECC_USB0_SERR_CLR_MSK 0xfffffff7
7427 
7428 #define ALT_SYSMGR_ECC_USB0_SERR_RESET 0x0
7429 
7430 #define ALT_SYSMGR_ECC_USB0_SERR_GET(value) (((value) & 0x00000008) >> 3)
7431 
7432 #define ALT_SYSMGR_ECC_USB0_SERR_SET(value) (((value) << 3) & 0x00000008)
7433 
7445 #define ALT_SYSMGR_ECC_USB0_DERR_LSB 4
7446 
7447 #define ALT_SYSMGR_ECC_USB0_DERR_MSB 4
7448 
7449 #define ALT_SYSMGR_ECC_USB0_DERR_WIDTH 1
7450 
7451 #define ALT_SYSMGR_ECC_USB0_DERR_SET_MSK 0x00000010
7452 
7453 #define ALT_SYSMGR_ECC_USB0_DERR_CLR_MSK 0xffffffef
7454 
7455 #define ALT_SYSMGR_ECC_USB0_DERR_RESET 0x0
7456 
7457 #define ALT_SYSMGR_ECC_USB0_DERR_GET(value) (((value) & 0x00000010) >> 4)
7458 
7459 #define ALT_SYSMGR_ECC_USB0_DERR_SET(value) (((value) << 4) & 0x00000010)
7460 
7461 #ifndef __ASSEMBLY__
7462 
7473 {
7474  uint32_t en : 1;
7475  uint32_t injs : 1;
7476  uint32_t injd : 1;
7477  uint32_t serr : 1;
7478  uint32_t derr : 1;
7479  uint32_t : 27;
7480 };
7481 
7484 #endif /* __ASSEMBLY__ */
7485 
7487 #define ALT_SYSMGR_ECC_USB0_OFST 0x8
7488 
7519 #define ALT_SYSMGR_ECC_USB1_EN_LSB 0
7520 
7521 #define ALT_SYSMGR_ECC_USB1_EN_MSB 0
7522 
7523 #define ALT_SYSMGR_ECC_USB1_EN_WIDTH 1
7524 
7525 #define ALT_SYSMGR_ECC_USB1_EN_SET_MSK 0x00000001
7526 
7527 #define ALT_SYSMGR_ECC_USB1_EN_CLR_MSK 0xfffffffe
7528 
7529 #define ALT_SYSMGR_ECC_USB1_EN_RESET 0x0
7530 
7531 #define ALT_SYSMGR_ECC_USB1_EN_GET(value) (((value) & 0x00000001) >> 0)
7532 
7533 #define ALT_SYSMGR_ECC_USB1_EN_SET(value) (((value) << 0) & 0x00000001)
7534 
7545 #define ALT_SYSMGR_ECC_USB1_INJS_LSB 1
7546 
7547 #define ALT_SYSMGR_ECC_USB1_INJS_MSB 1
7548 
7549 #define ALT_SYSMGR_ECC_USB1_INJS_WIDTH 1
7550 
7551 #define ALT_SYSMGR_ECC_USB1_INJS_SET_MSK 0x00000002
7552 
7553 #define ALT_SYSMGR_ECC_USB1_INJS_CLR_MSK 0xfffffffd
7554 
7555 #define ALT_SYSMGR_ECC_USB1_INJS_RESET 0x0
7556 
7557 #define ALT_SYSMGR_ECC_USB1_INJS_GET(value) (((value) & 0x00000002) >> 1)
7558 
7559 #define ALT_SYSMGR_ECC_USB1_INJS_SET(value) (((value) << 1) & 0x00000002)
7560 
7571 #define ALT_SYSMGR_ECC_USB1_INJD_LSB 2
7572 
7573 #define ALT_SYSMGR_ECC_USB1_INJD_MSB 2
7574 
7575 #define ALT_SYSMGR_ECC_USB1_INJD_WIDTH 1
7576 
7577 #define ALT_SYSMGR_ECC_USB1_INJD_SET_MSK 0x00000004
7578 
7579 #define ALT_SYSMGR_ECC_USB1_INJD_CLR_MSK 0xfffffffb
7580 
7581 #define ALT_SYSMGR_ECC_USB1_INJD_RESET 0x0
7582 
7583 #define ALT_SYSMGR_ECC_USB1_INJD_GET(value) (((value) & 0x00000004) >> 2)
7584 
7585 #define ALT_SYSMGR_ECC_USB1_INJD_SET(value) (((value) << 2) & 0x00000004)
7586 
7598 #define ALT_SYSMGR_ECC_USB1_SERR_LSB 3
7599 
7600 #define ALT_SYSMGR_ECC_USB1_SERR_MSB 3
7601 
7602 #define ALT_SYSMGR_ECC_USB1_SERR_WIDTH 1
7603 
7604 #define ALT_SYSMGR_ECC_USB1_SERR_SET_MSK 0x00000008
7605 
7606 #define ALT_SYSMGR_ECC_USB1_SERR_CLR_MSK 0xfffffff7
7607 
7608 #define ALT_SYSMGR_ECC_USB1_SERR_RESET 0x0
7609 
7610 #define ALT_SYSMGR_ECC_USB1_SERR_GET(value) (((value) & 0x00000008) >> 3)
7611 
7612 #define ALT_SYSMGR_ECC_USB1_SERR_SET(value) (((value) << 3) & 0x00000008)
7613 
7625 #define ALT_SYSMGR_ECC_USB1_DERR_LSB 4
7626 
7627 #define ALT_SYSMGR_ECC_USB1_DERR_MSB 4
7628 
7629 #define ALT_SYSMGR_ECC_USB1_DERR_WIDTH 1
7630 
7631 #define ALT_SYSMGR_ECC_USB1_DERR_SET_MSK 0x00000010
7632 
7633 #define ALT_SYSMGR_ECC_USB1_DERR_CLR_MSK 0xffffffef
7634 
7635 #define ALT_SYSMGR_ECC_USB1_DERR_RESET 0x0
7636 
7637 #define ALT_SYSMGR_ECC_USB1_DERR_GET(value) (((value) & 0x00000010) >> 4)
7638 
7639 #define ALT_SYSMGR_ECC_USB1_DERR_SET(value) (((value) << 4) & 0x00000010)
7640 
7641 #ifndef __ASSEMBLY__
7642 
7653 {
7654  uint32_t en : 1;
7655  uint32_t injs : 1;
7656  uint32_t injd : 1;
7657  uint32_t serr : 1;
7658  uint32_t derr : 1;
7659  uint32_t : 27;
7660 };
7661 
7664 #endif /* __ASSEMBLY__ */
7665 
7667 #define ALT_SYSMGR_ECC_USB1_OFST 0xc
7668 
7703 #define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0
7704 
7705 #define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0
7706 
7707 #define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1
7708 
7709 #define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001
7710 
7711 #define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe
7712 
7713 #define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0
7714 
7715 #define ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0)
7716 
7717 #define ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001)
7718 
7729 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1
7730 
7731 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1
7732 
7733 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1
7734 
7735 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002
7736 
7737 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd
7738 
7739 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0
7740 
7741 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
7742 
7743 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
7744 
7756 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2
7757 
7758 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2
7759 
7760 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1
7761 
7762 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004
7763 
7764 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb
7765 
7766 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0
7767 
7768 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
7769 
7770 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
7771 
7782 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3
7783 
7784 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3
7785 
7786 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1
7787 
7788 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008
7789 
7790 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7
7791 
7792 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0
7793 
7794 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
7795 
7796 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
7797 
7809 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4
7810 
7811 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4
7812 
7813 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1
7814 
7815 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010
7816 
7817 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef
7818 
7819 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0
7820 
7821 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
7822 
7823 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
7824 
7837 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5
7838 
7839 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5
7840 
7841 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1
7842 
7843 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020
7844 
7845 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf
7846 
7847 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0
7848 
7849 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
7850 
7851 #define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
7852 
7865 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6
7866 
7867 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6
7868 
7869 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1
7870 
7871 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040
7872 
7873 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf
7874 
7875 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0
7876 
7877 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
7878 
7879 #define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
7880 
7893 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7
7894 
7895 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7
7896 
7897 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1
7898 
7899 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080
7900 
7901 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f
7902 
7903 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0
7904 
7905 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
7906 
7907 #define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
7908 
7921 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8
7922 
7923 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8
7924 
7925 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1
7926 
7927 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100
7928 
7929 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff
7930 
7931 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0
7932 
7933 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
7934 
7935 #define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
7936 
7937 #ifndef __ASSEMBLY__
7938 
7949 {
7950  uint32_t en : 1;
7951  uint32_t txfifoinjs : 1;
7952  uint32_t txfifoinjd : 1;
7953  uint32_t rxfifoinjs : 1;
7954  uint32_t rxfifoinjd : 1;
7955  uint32_t txfifoserr : 1;
7956  uint32_t txfifoderr : 1;
7957  uint32_t rxfifoserr : 1;
7958  uint32_t rxfifoderr : 1;
7959  uint32_t : 23;
7960 };
7961 
7964 #endif /* __ASSEMBLY__ */
7965 
7967 #define ALT_SYSMGR_ECC_EMAC0_OFST 0x10
7968 
8003 #define ALT_SYSMGR_ECC_EMAC1_EN_LSB 0
8004 
8005 #define ALT_SYSMGR_ECC_EMAC1_EN_MSB 0
8006 
8007 #define ALT_SYSMGR_ECC_EMAC1_EN_WIDTH 1
8008 
8009 #define ALT_SYSMGR_ECC_EMAC1_EN_SET_MSK 0x00000001
8010 
8011 #define ALT_SYSMGR_ECC_EMAC1_EN_CLR_MSK 0xfffffffe
8012 
8013 #define ALT_SYSMGR_ECC_EMAC1_EN_RESET 0x0
8014 
8015 #define ALT_SYSMGR_ECC_EMAC1_EN_GET(value) (((value) & 0x00000001) >> 0)
8016 
8017 #define ALT_SYSMGR_ECC_EMAC1_EN_SET(value) (((value) << 0) & 0x00000001)
8018 
8029 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_LSB 1
8030 
8031 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_MSB 1
8032 
8033 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_WIDTH 1
8034 
8035 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET_MSK 0x00000002
8036 
8037 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_CLR_MSK 0xfffffffd
8038 
8039 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_RESET 0x0
8040 
8041 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1)
8042 
8043 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002)
8044 
8056 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_LSB 2
8057 
8058 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_MSB 2
8059 
8060 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_WIDTH 1
8061 
8062 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET_MSK 0x00000004
8063 
8064 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_CLR_MSK 0xfffffffb
8065 
8066 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_RESET 0x0
8067 
8068 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2)
8069 
8070 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004)
8071 
8082 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_LSB 3
8083 
8084 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_MSB 3
8085 
8086 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_WIDTH 1
8087 
8088 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET_MSK 0x00000008
8089 
8090 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_CLR_MSK 0xfffffff7
8091 
8092 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_RESET 0x0
8093 
8094 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8095 
8096 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8097 
8109 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_LSB 4
8110 
8111 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_MSB 4
8112 
8113 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_WIDTH 1
8114 
8115 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET_MSK 0x00000010
8116 
8117 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_CLR_MSK 0xffffffef
8118 
8119 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_RESET 0x0
8120 
8121 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8122 
8123 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8124 
8137 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_LSB 5
8138 
8139 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_MSB 5
8140 
8141 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_WIDTH 1
8142 
8143 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET_MSK 0x00000020
8144 
8145 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_CLR_MSK 0xffffffdf
8146 
8147 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_RESET 0x0
8148 
8149 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5)
8150 
8151 #define ALT_SYSMGR_ECC_EMAC1_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020)
8152 
8165 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_LSB 6
8166 
8167 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_MSB 6
8168 
8169 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_WIDTH 1
8170 
8171 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET_MSK 0x00000040
8172 
8173 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_CLR_MSK 0xffffffbf
8174 
8175 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_RESET 0x0
8176 
8177 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6)
8178 
8179 #define ALT_SYSMGR_ECC_EMAC1_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040)
8180 
8193 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_LSB 7
8194 
8195 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_MSB 7
8196 
8197 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_WIDTH 1
8198 
8199 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET_MSK 0x00000080
8200 
8201 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_CLR_MSK 0xffffff7f
8202 
8203 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_RESET 0x0
8204 
8205 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7)
8206 
8207 #define ALT_SYSMGR_ECC_EMAC1_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080)
8208 
8221 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_LSB 8
8222 
8223 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_MSB 8
8224 
8225 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_WIDTH 1
8226 
8227 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET_MSK 0x00000100
8228 
8229 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_CLR_MSK 0xfffffeff
8230 
8231 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_RESET 0x0
8232 
8233 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8)
8234 
8235 #define ALT_SYSMGR_ECC_EMAC1_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100)
8236 
8237 #ifndef __ASSEMBLY__
8238 
8249 {
8250  uint32_t en : 1;
8251  uint32_t txfifoinjs : 1;
8252  uint32_t txfifoinjd : 1;
8253  uint32_t rxfifoinjs : 1;
8254  uint32_t rxfifoinjd : 1;
8255  uint32_t txfifoserr : 1;
8256  uint32_t txfifoderr : 1;
8257  uint32_t rxfifoserr : 1;
8258  uint32_t rxfifoderr : 1;
8259  uint32_t : 23;
8260 };
8261 
8264 #endif /* __ASSEMBLY__ */
8265 
8267 #define ALT_SYSMGR_ECC_EMAC1_OFST 0x14
8268 
8299 #define ALT_SYSMGR_ECC_DMA_EN_LSB 0
8300 
8301 #define ALT_SYSMGR_ECC_DMA_EN_MSB 0
8302 
8303 #define ALT_SYSMGR_ECC_DMA_EN_WIDTH 1
8304 
8305 #define ALT_SYSMGR_ECC_DMA_EN_SET_MSK 0x00000001
8306 
8307 #define ALT_SYSMGR_ECC_DMA_EN_CLR_MSK 0xfffffffe
8308 
8309 #define ALT_SYSMGR_ECC_DMA_EN_RESET 0x0
8310 
8311 #define ALT_SYSMGR_ECC_DMA_EN_GET(value) (((value) & 0x00000001) >> 0)
8312 
8313 #define ALT_SYSMGR_ECC_DMA_EN_SET(value) (((value) << 0) & 0x00000001)
8314 
8325 #define ALT_SYSMGR_ECC_DMA_INJS_LSB 1
8326 
8327 #define ALT_SYSMGR_ECC_DMA_INJS_MSB 1
8328 
8329 #define ALT_SYSMGR_ECC_DMA_INJS_WIDTH 1
8330 
8331 #define ALT_SYSMGR_ECC_DMA_INJS_SET_MSK 0x00000002
8332 
8333 #define ALT_SYSMGR_ECC_DMA_INJS_CLR_MSK 0xfffffffd
8334 
8335 #define ALT_SYSMGR_ECC_DMA_INJS_RESET 0x0
8336 
8337 #define ALT_SYSMGR_ECC_DMA_INJS_GET(value) (((value) & 0x00000002) >> 1)
8338 
8339 #define ALT_SYSMGR_ECC_DMA_INJS_SET(value) (((value) << 1) & 0x00000002)
8340 
8351 #define ALT_SYSMGR_ECC_DMA_INJD_LSB 2
8352 
8353 #define ALT_SYSMGR_ECC_DMA_INJD_MSB 2
8354 
8355 #define ALT_SYSMGR_ECC_DMA_INJD_WIDTH 1
8356 
8357 #define ALT_SYSMGR_ECC_DMA_INJD_SET_MSK 0x00000004
8358 
8359 #define ALT_SYSMGR_ECC_DMA_INJD_CLR_MSK 0xfffffffb
8360 
8361 #define ALT_SYSMGR_ECC_DMA_INJD_RESET 0x0
8362 
8363 #define ALT_SYSMGR_ECC_DMA_INJD_GET(value) (((value) & 0x00000004) >> 2)
8364 
8365 #define ALT_SYSMGR_ECC_DMA_INJD_SET(value) (((value) << 2) & 0x00000004)
8366 
8378 #define ALT_SYSMGR_ECC_DMA_SERR_LSB 3
8379 
8380 #define ALT_SYSMGR_ECC_DMA_SERR_MSB 3
8381 
8382 #define ALT_SYSMGR_ECC_DMA_SERR_WIDTH 1
8383 
8384 #define ALT_SYSMGR_ECC_DMA_SERR_SET_MSK 0x00000008
8385 
8386 #define ALT_SYSMGR_ECC_DMA_SERR_CLR_MSK 0xfffffff7
8387 
8388 #define ALT_SYSMGR_ECC_DMA_SERR_RESET 0x0
8389 
8390 #define ALT_SYSMGR_ECC_DMA_SERR_GET(value) (((value) & 0x00000008) >> 3)
8391 
8392 #define ALT_SYSMGR_ECC_DMA_SERR_SET(value) (((value) << 3) & 0x00000008)
8393 
8405 #define ALT_SYSMGR_ECC_DMA_DERR_LSB 4
8406 
8407 #define ALT_SYSMGR_ECC_DMA_DERR_MSB 4
8408 
8409 #define ALT_SYSMGR_ECC_DMA_DERR_WIDTH 1
8410 
8411 #define ALT_SYSMGR_ECC_DMA_DERR_SET_MSK 0x00000010
8412 
8413 #define ALT_SYSMGR_ECC_DMA_DERR_CLR_MSK 0xffffffef
8414 
8415 #define ALT_SYSMGR_ECC_DMA_DERR_RESET 0x0
8416 
8417 #define ALT_SYSMGR_ECC_DMA_DERR_GET(value) (((value) & 0x00000010) >> 4)
8418 
8419 #define ALT_SYSMGR_ECC_DMA_DERR_SET(value) (((value) << 4) & 0x00000010)
8420 
8421 #ifndef __ASSEMBLY__
8422 
8433 {
8434  uint32_t en : 1;
8435  uint32_t injs : 1;
8436  uint32_t injd : 1;
8437  uint32_t serr : 1;
8438  uint32_t derr : 1;
8439  uint32_t : 27;
8440 };
8441 
8444 #endif /* __ASSEMBLY__ */
8445 
8447 #define ALT_SYSMGR_ECC_DMA_OFST 0x18
8448 
8479 #define ALT_SYSMGR_ECC_CAN0_EN_LSB 0
8480 
8481 #define ALT_SYSMGR_ECC_CAN0_EN_MSB 0
8482 
8483 #define ALT_SYSMGR_ECC_CAN0_EN_WIDTH 1
8484 
8485 #define ALT_SYSMGR_ECC_CAN0_EN_SET_MSK 0x00000001
8486 
8487 #define ALT_SYSMGR_ECC_CAN0_EN_CLR_MSK 0xfffffffe
8488 
8489 #define ALT_SYSMGR_ECC_CAN0_EN_RESET 0x0
8490 
8491 #define ALT_SYSMGR_ECC_CAN0_EN_GET(value) (((value) & 0x00000001) >> 0)
8492 
8493 #define ALT_SYSMGR_ECC_CAN0_EN_SET(value) (((value) << 0) & 0x00000001)
8494 
8505 #define ALT_SYSMGR_ECC_CAN0_INJS_LSB 1
8506 
8507 #define ALT_SYSMGR_ECC_CAN0_INJS_MSB 1
8508 
8509 #define ALT_SYSMGR_ECC_CAN0_INJS_WIDTH 1
8510 
8511 #define ALT_SYSMGR_ECC_CAN0_INJS_SET_MSK 0x00000002
8512 
8513 #define ALT_SYSMGR_ECC_CAN0_INJS_CLR_MSK 0xfffffffd
8514 
8515 #define ALT_SYSMGR_ECC_CAN0_INJS_RESET 0x0
8516 
8517 #define ALT_SYSMGR_ECC_CAN0_INJS_GET(value) (((value) & 0x00000002) >> 1)
8518 
8519 #define ALT_SYSMGR_ECC_CAN0_INJS_SET(value) (((value) << 1) & 0x00000002)
8520 
8531 #define ALT_SYSMGR_ECC_CAN0_INJD_LSB 2
8532 
8533 #define ALT_SYSMGR_ECC_CAN0_INJD_MSB 2
8534 
8535 #define ALT_SYSMGR_ECC_CAN0_INJD_WIDTH 1
8536 
8537 #define ALT_SYSMGR_ECC_CAN0_INJD_SET_MSK 0x00000004
8538 
8539 #define ALT_SYSMGR_ECC_CAN0_INJD_CLR_MSK 0xfffffffb
8540 
8541 #define ALT_SYSMGR_ECC_CAN0_INJD_RESET 0x0
8542 
8543 #define ALT_SYSMGR_ECC_CAN0_INJD_GET(value) (((value) & 0x00000004) >> 2)
8544 
8545 #define ALT_SYSMGR_ECC_CAN0_INJD_SET(value) (((value) << 2) & 0x00000004)
8546 
8558 #define ALT_SYSMGR_ECC_CAN0_SERR_LSB 3
8559 
8560 #define ALT_SYSMGR_ECC_CAN0_SERR_MSB 3
8561 
8562 #define ALT_SYSMGR_ECC_CAN0_SERR_WIDTH 1
8563 
8564 #define ALT_SYSMGR_ECC_CAN0_SERR_SET_MSK 0x00000008
8565 
8566 #define ALT_SYSMGR_ECC_CAN0_SERR_CLR_MSK 0xfffffff7
8567 
8568 #define ALT_SYSMGR_ECC_CAN0_SERR_RESET 0x0
8569 
8570 #define ALT_SYSMGR_ECC_CAN0_SERR_GET(value) (((value) & 0x00000008) >> 3)
8571 
8572 #define ALT_SYSMGR_ECC_CAN0_SERR_SET(value) (((value) << 3) & 0x00000008)
8573 
8585 #define ALT_SYSMGR_ECC_CAN0_DERR_LSB 4
8586 
8587 #define ALT_SYSMGR_ECC_CAN0_DERR_MSB 4
8588 
8589 #define ALT_SYSMGR_ECC_CAN0_DERR_WIDTH 1
8590 
8591 #define ALT_SYSMGR_ECC_CAN0_DERR_SET_MSK 0x00000010
8592 
8593 #define ALT_SYSMGR_ECC_CAN0_DERR_CLR_MSK 0xffffffef
8594 
8595 #define ALT_SYSMGR_ECC_CAN0_DERR_RESET 0x0
8596 
8597 #define ALT_SYSMGR_ECC_CAN0_DERR_GET(value) (((value) & 0x00000010) >> 4)
8598 
8599 #define ALT_SYSMGR_ECC_CAN0_DERR_SET(value) (((value) << 4) & 0x00000010)
8600 
8601 #ifndef __ASSEMBLY__
8602 
8613 {
8614  uint32_t en : 1;
8615  uint32_t injs : 1;
8616  uint32_t injd : 1;
8617  uint32_t serr : 1;
8618  uint32_t derr : 1;
8619  uint32_t : 27;
8620 };
8621 
8624 #endif /* __ASSEMBLY__ */
8625 
8627 #define ALT_SYSMGR_ECC_CAN0_OFST 0x1c
8628 
8659 #define ALT_SYSMGR_ECC_CAN1_EN_LSB 0
8660 
8661 #define ALT_SYSMGR_ECC_CAN1_EN_MSB 0
8662 
8663 #define ALT_SYSMGR_ECC_CAN1_EN_WIDTH 1
8664 
8665 #define ALT_SYSMGR_ECC_CAN1_EN_SET_MSK 0x00000001
8666 
8667 #define ALT_SYSMGR_ECC_CAN1_EN_CLR_MSK 0xfffffffe
8668 
8669 #define ALT_SYSMGR_ECC_CAN1_EN_RESET 0x0
8670 
8671 #define ALT_SYSMGR_ECC_CAN1_EN_GET(value) (((value) & 0x00000001) >> 0)
8672 
8673 #define ALT_SYSMGR_ECC_CAN1_EN_SET(value) (((value) << 0) & 0x00000001)
8674 
8685 #define ALT_SYSMGR_ECC_CAN1_INJS_LSB 1
8686 
8687 #define ALT_SYSMGR_ECC_CAN1_INJS_MSB 1
8688 
8689 #define ALT_SYSMGR_ECC_CAN1_INJS_WIDTH 1
8690 
8691 #define ALT_SYSMGR_ECC_CAN1_INJS_SET_MSK 0x00000002
8692 
8693 #define ALT_SYSMGR_ECC_CAN1_INJS_CLR_MSK 0xfffffffd
8694 
8695 #define ALT_SYSMGR_ECC_CAN1_INJS_RESET 0x0
8696 
8697 #define ALT_SYSMGR_ECC_CAN1_INJS_GET(value) (((value) & 0x00000002) >> 1)
8698 
8699 #define ALT_SYSMGR_ECC_CAN1_INJS_SET(value) (((value) << 1) & 0x00000002)
8700 
8711 #define ALT_SYSMGR_ECC_CAN1_INJD_LSB 2
8712 
8713 #define ALT_SYSMGR_ECC_CAN1_INJD_MSB 2
8714 
8715 #define ALT_SYSMGR_ECC_CAN1_INJD_WIDTH 1
8716 
8717 #define ALT_SYSMGR_ECC_CAN1_INJD_SET_MSK 0x00000004
8718 
8719 #define ALT_SYSMGR_ECC_CAN1_INJD_CLR_MSK 0xfffffffb
8720 
8721 #define ALT_SYSMGR_ECC_CAN1_INJD_RESET 0x0
8722 
8723 #define ALT_SYSMGR_ECC_CAN1_INJD_GET(value) (((value) & 0x00000004) >> 2)
8724 
8725 #define ALT_SYSMGR_ECC_CAN1_INJD_SET(value) (((value) << 2) & 0x00000004)
8726 
8738 #define ALT_SYSMGR_ECC_CAN1_SERR_LSB 3
8739 
8740 #define ALT_SYSMGR_ECC_CAN1_SERR_MSB 3
8741 
8742 #define ALT_SYSMGR_ECC_CAN1_SERR_WIDTH 1
8743 
8744 #define ALT_SYSMGR_ECC_CAN1_SERR_SET_MSK 0x00000008
8745 
8746 #define ALT_SYSMGR_ECC_CAN1_SERR_CLR_MSK 0xfffffff7
8747 
8748 #define ALT_SYSMGR_ECC_CAN1_SERR_RESET 0x0
8749 
8750 #define ALT_SYSMGR_ECC_CAN1_SERR_GET(value) (((value) & 0x00000008) >> 3)
8751 
8752 #define ALT_SYSMGR_ECC_CAN1_SERR_SET(value) (((value) << 3) & 0x00000008)
8753 
8765 #define ALT_SYSMGR_ECC_CAN1_DERR_LSB 4
8766 
8767 #define ALT_SYSMGR_ECC_CAN1_DERR_MSB 4
8768 
8769 #define ALT_SYSMGR_ECC_CAN1_DERR_WIDTH 1
8770 
8771 #define ALT_SYSMGR_ECC_CAN1_DERR_SET_MSK 0x00000010
8772 
8773 #define ALT_SYSMGR_ECC_CAN1_DERR_CLR_MSK 0xffffffef
8774 
8775 #define ALT_SYSMGR_ECC_CAN1_DERR_RESET 0x0
8776 
8777 #define ALT_SYSMGR_ECC_CAN1_DERR_GET(value) (((value) & 0x00000010) >> 4)
8778 
8779 #define ALT_SYSMGR_ECC_CAN1_DERR_SET(value) (((value) << 4) & 0x00000010)
8780 
8781 #ifndef __ASSEMBLY__
8782 
8793 {
8794  uint32_t en : 1;
8795  uint32_t injs : 1;
8796  uint32_t injd : 1;
8797  uint32_t serr : 1;
8798  uint32_t derr : 1;
8799  uint32_t : 27;
8800 };
8801 
8804 #endif /* __ASSEMBLY__ */
8805 
8807 #define ALT_SYSMGR_ECC_CAN1_OFST 0x20
8808 
8847 #define ALT_SYSMGR_ECC_NAND_EN_LSB 0
8848 
8849 #define ALT_SYSMGR_ECC_NAND_EN_MSB 0
8850 
8851 #define ALT_SYSMGR_ECC_NAND_EN_WIDTH 1
8852 
8853 #define ALT_SYSMGR_ECC_NAND_EN_SET_MSK 0x00000001
8854 
8855 #define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK 0xfffffffe
8856 
8857 #define ALT_SYSMGR_ECC_NAND_EN_RESET 0x0
8858 
8859 #define ALT_SYSMGR_ECC_NAND_EN_GET(value) (((value) & 0x00000001) >> 0)
8860 
8861 #define ALT_SYSMGR_ECC_NAND_EN_SET(value) (((value) << 0) & 0x00000001)
8862 
8873 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB 1
8874 
8875 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB 1
8876 
8877 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH 1
8878 
8879 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK 0x00000002
8880 
8881 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK 0xfffffffd
8882 
8883 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET 0x0
8884 
8885 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value) (((value) & 0x00000002) >> 1)
8886 
8887 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value) (((value) << 1) & 0x00000002)
8888 
8900 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB 2
8901 
8902 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB 2
8903 
8904 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH 1
8905 
8906 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK 0x00000004
8907 
8908 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK 0xfffffffb
8909 
8910 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET 0x0
8911 
8912 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value) (((value) & 0x00000004) >> 2)
8913 
8914 #define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value) (((value) << 2) & 0x00000004)
8915 
8926 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB 3
8927 
8928 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB 3
8929 
8930 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH 1
8931 
8932 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK 0x00000008
8933 
8934 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK 0xfffffff7
8935 
8936 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET 0x0
8937 
8938 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value) (((value) & 0x00000008) >> 3)
8939 
8940 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value) (((value) << 3) & 0x00000008)
8941 
8953 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB 4
8954 
8955 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB 4
8956 
8957 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH 1
8958 
8959 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK 0x00000010
8960 
8961 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK 0xffffffef
8962 
8963 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET 0x0
8964 
8965 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value) (((value) & 0x00000010) >> 4)
8966 
8967 #define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value) (((value) << 4) & 0x00000010)
8968 
8979 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB 5
8980 
8981 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB 5
8982 
8983 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH 1
8984 
8985 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK 0x00000020
8986 
8987 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK 0xffffffdf
8988 
8989 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET 0x0
8990 
8991 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value) (((value) & 0x00000020) >> 5)
8992 
8993 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value) (((value) << 5) & 0x00000020)
8994 
9006 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB 6
9007 
9008 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB 6
9009 
9010 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH 1
9011 
9012 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK 0x00000040
9013 
9014 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK 0xffffffbf
9015 
9016 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET 0x0
9017 
9018 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value) (((value) & 0x00000040) >> 6)
9019 
9020 #define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value) (((value) << 6) & 0x00000040)
9021 
9034 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB 7
9035 
9036 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB 7
9037 
9038 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH 1
9039 
9040 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK 0x00000080
9041 
9042 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK 0xffffff7f
9043 
9044 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET 0x0
9045 
9046 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value) (((value) & 0x00000080) >> 7)
9047 
9048 #define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value) (((value) << 7) & 0x00000080)
9049 
9062 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB 8
9063 
9064 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB 8
9065 
9066 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH 1
9067 
9068 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK 0x00000100
9069 
9070 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK 0xfffffeff
9071 
9072 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET 0x0
9073 
9074 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value) (((value) & 0x00000100) >> 8)
9075 
9076 #define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value) (((value) << 8) & 0x00000100)
9077 
9090 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB 9
9091 
9092 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB 9
9093 
9094 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH 1
9095 
9096 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK 0x00000200
9097 
9098 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK 0xfffffdff
9099 
9100 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET 0x0
9101 
9102 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value) (((value) & 0x00000200) >> 9)
9103 
9104 #define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value) (((value) << 9) & 0x00000200)
9105 
9118 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB 10
9119 
9120 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB 10
9121 
9122 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH 1
9123 
9124 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK 0x00000400
9125 
9126 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK 0xfffffbff
9127 
9128 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET 0x0
9129 
9130 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value) (((value) & 0x00000400) >> 10)
9131 
9132 #define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value) (((value) << 10) & 0x00000400)
9133 
9146 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB 11
9147 
9148 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB 11
9149 
9150 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH 1
9151 
9152 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK 0x00000800
9153 
9154 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK 0xfffff7ff
9155 
9156 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET 0x0
9157 
9158 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value) (((value) & 0x00000800) >> 11)
9159 
9160 #define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value) (((value) << 11) & 0x00000800)
9161 
9174 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB 12
9175 
9176 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB 12
9177 
9178 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH 1
9179 
9180 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK 0x00001000
9181 
9182 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK 0xffffefff
9183 
9184 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET 0x0
9185 
9186 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value) (((value) & 0x00001000) >> 12)
9187 
9188 #define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value) (((value) << 12) & 0x00001000)
9189 
9190 #ifndef __ASSEMBLY__
9191 
9202 {
9203  uint32_t en : 1;
9204  uint32_t eccbufinjs : 1;
9205  uint32_t eccbufinjd : 1;
9206  uint32_t wrfifoinjs : 1;
9207  uint32_t wrfifoinjd : 1;
9208  uint32_t rdfifoinjs : 1;
9209  uint32_t rdfifoinjd : 1;
9210  uint32_t eccbufserr : 1;
9211  uint32_t eccbufderr : 1;
9212  uint32_t wrfifoserr : 1;
9213  uint32_t wrfifoderr : 1;
9214  uint32_t rdfifoserr : 1;
9215  uint32_t rdfifoderr : 1;
9216  uint32_t : 19;
9217 };
9218 
9221 #endif /* __ASSEMBLY__ */
9222 
9224 #define ALT_SYSMGR_ECC_NAND_OFST 0x24
9225 
9256 #define ALT_SYSMGR_ECC_QSPI_EN_LSB 0
9257 
9258 #define ALT_SYSMGR_ECC_QSPI_EN_MSB 0
9259 
9260 #define ALT_SYSMGR_ECC_QSPI_EN_WIDTH 1
9261 
9262 #define ALT_SYSMGR_ECC_QSPI_EN_SET_MSK 0x00000001
9263 
9264 #define ALT_SYSMGR_ECC_QSPI_EN_CLR_MSK 0xfffffffe
9265 
9266 #define ALT_SYSMGR_ECC_QSPI_EN_RESET 0x0
9267 
9268 #define ALT_SYSMGR_ECC_QSPI_EN_GET(value) (((value) & 0x00000001) >> 0)
9269 
9270 #define ALT_SYSMGR_ECC_QSPI_EN_SET(value) (((value) << 0) & 0x00000001)
9271 
9282 #define ALT_SYSMGR_ECC_QSPI_INJS_LSB 1
9283 
9284 #define ALT_SYSMGR_ECC_QSPI_INJS_MSB 1
9285 
9286 #define ALT_SYSMGR_ECC_QSPI_INJS_WIDTH 1
9287 
9288 #define ALT_SYSMGR_ECC_QSPI_INJS_SET_MSK 0x00000002
9289 
9290 #define ALT_SYSMGR_ECC_QSPI_INJS_CLR_MSK 0xfffffffd
9291 
9292 #define ALT_SYSMGR_ECC_QSPI_INJS_RESET 0x0
9293 
9294 #define ALT_SYSMGR_ECC_QSPI_INJS_GET(value) (((value) & 0x00000002) >> 1)
9295 
9296 #define ALT_SYSMGR_ECC_QSPI_INJS_SET(value) (((value) << 1) & 0x00000002)
9297 
9308 #define ALT_SYSMGR_ECC_QSPI_INJD_LSB 2
9309 
9310 #define ALT_SYSMGR_ECC_QSPI_INJD_MSB 2
9311 
9312 #define ALT_SYSMGR_ECC_QSPI_INJD_WIDTH 1
9313 
9314 #define ALT_SYSMGR_ECC_QSPI_INJD_SET_MSK 0x00000004
9315 
9316 #define ALT_SYSMGR_ECC_QSPI_INJD_CLR_MSK 0xfffffffb
9317 
9318 #define ALT_SYSMGR_ECC_QSPI_INJD_RESET 0x0
9319 
9320 #define ALT_SYSMGR_ECC_QSPI_INJD_GET(value) (((value) & 0x00000004) >> 2)
9321 
9322 #define ALT_SYSMGR_ECC_QSPI_INJD_SET(value) (((value) << 2) & 0x00000004)
9323 
9335 #define ALT_SYSMGR_ECC_QSPI_SERR_LSB 3
9336 
9337 #define ALT_SYSMGR_ECC_QSPI_SERR_MSB 3
9338 
9339 #define ALT_SYSMGR_ECC_QSPI_SERR_WIDTH 1
9340 
9341 #define ALT_SYSMGR_ECC_QSPI_SERR_SET_MSK 0x00000008
9342 
9343 #define ALT_SYSMGR_ECC_QSPI_SERR_CLR_MSK 0xfffffff7
9344 
9345 #define ALT_SYSMGR_ECC_QSPI_SERR_RESET 0x0
9346 
9347 #define ALT_SYSMGR_ECC_QSPI_SERR_GET(value) (((value) & 0x00000008) >> 3)
9348 
9349 #define ALT_SYSMGR_ECC_QSPI_SERR_SET(value) (((value) << 3) & 0x00000008)
9350 
9362 #define ALT_SYSMGR_ECC_QSPI_DERR_LSB 4
9363 
9364 #define ALT_SYSMGR_ECC_QSPI_DERR_MSB 4
9365 
9366 #define ALT_SYSMGR_ECC_QSPI_DERR_WIDTH 1
9367 
9368 #define ALT_SYSMGR_ECC_QSPI_DERR_SET_MSK 0x00000010
9369 
9370 #define ALT_SYSMGR_ECC_QSPI_DERR_CLR_MSK 0xffffffef
9371 
9372 #define ALT_SYSMGR_ECC_QSPI_DERR_RESET 0x0
9373 
9374 #define ALT_SYSMGR_ECC_QSPI_DERR_GET(value) (((value) & 0x00000010) >> 4)
9375 
9376 #define ALT_SYSMGR_ECC_QSPI_DERR_SET(value) (((value) << 4) & 0x00000010)
9377 
9378 #ifndef __ASSEMBLY__
9379 
9390 {
9391  uint32_t en : 1;
9392  uint32_t injs : 1;
9393  uint32_t injd : 1;
9394  uint32_t serr : 1;
9395  uint32_t derr : 1;
9396  uint32_t : 27;
9397 };
9398 
9401 #endif /* __ASSEMBLY__ */
9402 
9404 #define ALT_SYSMGR_ECC_QSPI_OFST 0x28
9405 
9439 #define ALT_SYSMGR_ECC_SDMMC_EN_LSB 0
9440 
9441 #define ALT_SYSMGR_ECC_SDMMC_EN_MSB 0
9442 
9443 #define ALT_SYSMGR_ECC_SDMMC_EN_WIDTH 1
9444 
9445 #define ALT_SYSMGR_ECC_SDMMC_EN_SET_MSK 0x00000001
9446 
9447 #define ALT_SYSMGR_ECC_SDMMC_EN_CLR_MSK 0xfffffffe
9448 
9449 #define ALT_SYSMGR_ECC_SDMMC_EN_RESET 0x0
9450 
9451 #define ALT_SYSMGR_ECC_SDMMC_EN_GET(value) (((value) & 0x00000001) >> 0)
9452 
9453 #define ALT_SYSMGR_ECC_SDMMC_EN_SET(value) (((value) << 0) & 0x00000001)
9454 
9465 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_LSB 1
9466 
9467 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_MSB 1
9468 
9469 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_WIDTH 1
9470 
9471 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET_MSK 0x00000002
9472 
9473 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_CLR_MSK 0xfffffffd
9474 
9475 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_RESET 0x0
9476 
9477 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_GET(value) (((value) & 0x00000002) >> 1)
9478 
9479 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTA_SET(value) (((value) << 1) & 0x00000002)
9480 
9492 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_LSB 2
9493 
9494 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_MSB 2
9495 
9496 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_WIDTH 1
9497 
9498 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET_MSK 0x00000004
9499 
9500 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_CLR_MSK 0xfffffffb
9501 
9502 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_RESET 0x0
9503 
9504 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_GET(value) (((value) & 0x00000004) >> 2)
9505 
9506 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTA_SET(value) (((value) << 2) & 0x00000004)
9507 
9518 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_LSB 3
9519 
9520 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_MSB 3
9521 
9522 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_WIDTH 1
9523 
9524 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET_MSK 0x00000008
9525 
9526 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_CLR_MSK 0xfffffff7
9527 
9528 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_RESET 0x0
9529 
9530 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_GET(value) (((value) & 0x00000008) >> 3)
9531 
9532 #define ALT_SYSMGR_ECC_SDMMC_INJSPORTB_SET(value) (((value) << 3) & 0x00000008)
9533 
9545 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_LSB 4
9546 
9547 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_MSB 4
9548 
9549 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_WIDTH 1
9550 
9551 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET_MSK 0x00000010
9552 
9553 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_CLR_MSK 0xffffffef
9554 
9555 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_RESET 0x0
9556 
9557 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_GET(value) (((value) & 0x00000010) >> 4)
9558 
9559 #define ALT_SYSMGR_ECC_SDMMC_INJDPORTB_SET(value) (((value) << 4) & 0x00000010)
9560 
9572 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_LSB 5
9573 
9574 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_MSB 5
9575 
9576 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_WIDTH 1
9577 
9578 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET_MSK 0x00000020
9579 
9580 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_CLR_MSK 0xffffffdf
9581 
9582 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_RESET 0x0
9583 
9584 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_GET(value) (((value) & 0x00000020) >> 5)
9585 
9586 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTA_SET(value) (((value) << 5) & 0x00000020)
9587 
9600 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_LSB 6
9601 
9602 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_MSB 6
9603 
9604 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_WIDTH 1
9605 
9606 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET_MSK 0x00000040
9607 
9608 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_CLR_MSK 0xffffffbf
9609 
9610 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_RESET 0x0
9611 
9612 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_GET(value) (((value) & 0x00000040) >> 6)
9613 
9614 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTA_SET(value) (((value) << 6) & 0x00000040)
9615 
9627 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_LSB 7
9628 
9629 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_MSB 7
9630 
9631 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_WIDTH 1
9632 
9633 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET_MSK 0x00000080
9634 
9635 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_CLR_MSK 0xffffff7f
9636 
9637 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_RESET 0x0
9638 
9639 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_GET(value) (((value) & 0x00000080) >> 7)
9640 
9641 #define ALT_SYSMGR_ECC_SDMMC_SERRPORTB_SET(value) (((value) << 7) & 0x00000080)
9642 
9655 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_LSB 8
9656 
9657 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_MSB 8
9658 
9659 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_WIDTH 1
9660 
9661 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET_MSK 0x00000100
9662 
9663 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_CLR_MSK 0xfffffeff
9664 
9665 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_RESET 0x0
9666 
9667 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_GET(value) (((value) & 0x00000100) >> 8)
9668 
9669 #define ALT_SYSMGR_ECC_SDMMC_DERRPORTB_SET(value) (((value) << 8) & 0x00000100)
9670 
9671 #ifndef __ASSEMBLY__
9672 
9683 {
9684  uint32_t en : 1;
9685  uint32_t injsporta : 1;
9686  uint32_t injdporta : 1;
9687  uint32_t injsportb : 1;
9688  uint32_t injdportb : 1;
9689  uint32_t serrporta : 1;
9690  uint32_t derrporta : 1;
9691  uint32_t serrportb : 1;
9692  uint32_t derrportb : 1;
9693  uint32_t : 23;
9694 };
9695 
9698 #endif /* __ASSEMBLY__ */
9699 
9701 #define ALT_SYSMGR_ECC_SDMMC_OFST 0x2c
9702 
9703 #ifndef __ASSEMBLY__
9704 
9715 {
9728  volatile uint32_t _pad_0x30_0x40[4];
9729 };
9730 
9732 typedef volatile struct ALT_SYSMGR_ECC_s ALT_SYSMGR_ECC_t;
9735 {
9736  volatile uint32_t l2;
9737  volatile uint32_t ocram;
9738  volatile uint32_t usb0;
9739  volatile uint32_t usb1;
9740  volatile uint32_t emac0;
9741  volatile uint32_t emac1;
9742  volatile uint32_t dma;
9743  volatile uint32_t can0;
9744  volatile uint32_t can1;
9745  volatile uint32_t nand;
9746  volatile uint32_t qspi;
9747  volatile uint32_t sdmmc;
9748  volatile uint32_t _pad_0x30_0x40[4];
9749 };
9750 
9753 #endif /* __ASSEMBLY__ */
9754 
9801 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_LSB 0
9802 
9803 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_MSB 1
9804 
9805 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_WIDTH 2
9806 
9807 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET_MSK 0x00000003
9808 
9809 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_CLR_MSK 0xfffffffc
9810 
9811 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_RESET 0x0
9812 
9813 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
9814 
9815 #define ALT_SYSMGR_PINMUX_EMACIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
9816 
9817 #ifndef __ASSEMBLY__
9818 
9829 {
9830  uint32_t sel : 2;
9831  uint32_t : 30;
9832 };
9833 
9836 #endif /* __ASSEMBLY__ */
9837 
9839 #define ALT_SYSMGR_PINMUX_EMACIO0_OFST 0x0
9840 
9876 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_LSB 0
9877 
9878 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_MSB 1
9879 
9880 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_WIDTH 2
9881 
9882 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET_MSK 0x00000003
9883 
9884 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_CLR_MSK 0xfffffffc
9885 
9886 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_RESET 0x0
9887 
9888 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
9889 
9890 #define ALT_SYSMGR_PINMUX_EMACIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
9891 
9892 #ifndef __ASSEMBLY__
9893 
9904 {
9905  uint32_t sel : 2;
9906  uint32_t : 30;
9907 };
9908 
9911 #endif /* __ASSEMBLY__ */
9912 
9914 #define ALT_SYSMGR_PINMUX_EMACIO1_OFST 0x4
9915 
9951 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_LSB 0
9952 
9953 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_MSB 1
9954 
9955 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_WIDTH 2
9956 
9957 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET_MSK 0x00000003
9958 
9959 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_CLR_MSK 0xfffffffc
9960 
9961 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_RESET 0x0
9962 
9963 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
9964 
9965 #define ALT_SYSMGR_PINMUX_EMACIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
9966 
9967 #ifndef __ASSEMBLY__
9968 
9979 {
9980  uint32_t sel : 2;
9981  uint32_t : 30;
9982 };
9983 
9986 #endif /* __ASSEMBLY__ */
9987 
9989 #define ALT_SYSMGR_PINMUX_EMACIO2_OFST 0x8
9990 
10026 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_LSB 0
10027 
10028 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_MSB 1
10029 
10030 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_WIDTH 2
10031 
10032 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET_MSK 0x00000003
10033 
10034 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_CLR_MSK 0xfffffffc
10035 
10036 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_RESET 0x0
10037 
10038 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
10039 
10040 #define ALT_SYSMGR_PINMUX_EMACIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
10041 
10042 #ifndef __ASSEMBLY__
10043 
10054 {
10055  uint32_t sel : 2;
10056  uint32_t : 30;
10057 };
10058 
10061 #endif /* __ASSEMBLY__ */
10062 
10064 #define ALT_SYSMGR_PINMUX_EMACIO3_OFST 0xc
10065 
10101 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_LSB 0
10102 
10103 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_MSB 1
10104 
10105 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_WIDTH 2
10106 
10107 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET_MSK 0x00000003
10108 
10109 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_CLR_MSK 0xfffffffc
10110 
10111 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_RESET 0x0
10112 
10113 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
10114 
10115 #define ALT_SYSMGR_PINMUX_EMACIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
10116 
10117 #ifndef __ASSEMBLY__
10118 
10129 {
10130  uint32_t sel : 2;
10131  uint32_t : 30;
10132 };
10133 
10136 #endif /* __ASSEMBLY__ */
10137 
10139 #define ALT_SYSMGR_PINMUX_EMACIO4_OFST 0x10
10140 
10176 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_LSB 0
10177 
10178 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_MSB 1
10179 
10180 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_WIDTH 2
10181 
10182 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET_MSK 0x00000003
10183 
10184 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_CLR_MSK 0xfffffffc
10185 
10186 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_RESET 0x0
10187 
10188 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
10189 
10190 #define ALT_SYSMGR_PINMUX_EMACIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
10191 
10192 #ifndef __ASSEMBLY__
10193 
10204 {
10205  uint32_t sel : 2;
10206  uint32_t : 30;
10207 };
10208 
10211 #endif /* __ASSEMBLY__ */
10212 
10214 #define ALT_SYSMGR_PINMUX_EMACIO5_OFST 0x14
10215 
10251 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_LSB 0
10252 
10253 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_MSB 1
10254 
10255 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_WIDTH 2
10256 
10257 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET_MSK 0x00000003
10258 
10259 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_CLR_MSK 0xfffffffc
10260 
10261 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_RESET 0x0
10262 
10263 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
10264 
10265 #define ALT_SYSMGR_PINMUX_EMACIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
10266 
10267 #ifndef __ASSEMBLY__
10268 
10279 {
10280  uint32_t sel : 2;
10281  uint32_t : 30;
10282 };
10283 
10286 #endif /* __ASSEMBLY__ */
10287 
10289 #define ALT_SYSMGR_PINMUX_EMACIO6_OFST 0x18
10290 
10326 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_LSB 0
10327 
10328 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_MSB 1
10329 
10330 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_WIDTH 2
10331 
10332 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET_MSK 0x00000003
10333 
10334 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_CLR_MSK 0xfffffffc
10335 
10336 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_RESET 0x0
10337 
10338 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
10339 
10340 #define ALT_SYSMGR_PINMUX_EMACIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
10341 
10342 #ifndef __ASSEMBLY__
10343 
10354 {
10355  uint32_t sel : 2;
10356  uint32_t : 30;
10357 };
10358 
10361 #endif /* __ASSEMBLY__ */
10362 
10364 #define ALT_SYSMGR_PINMUX_EMACIO7_OFST 0x1c
10365 
10401 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_LSB 0
10402 
10403 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_MSB 1
10404 
10405 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_WIDTH 2
10406 
10407 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET_MSK 0x00000003
10408 
10409 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_CLR_MSK 0xfffffffc
10410 
10411 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_RESET 0x0
10412 
10413 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
10414 
10415 #define ALT_SYSMGR_PINMUX_EMACIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
10416 
10417 #ifndef __ASSEMBLY__
10418 
10429 {
10430  uint32_t sel : 2;
10431  uint32_t : 30;
10432 };
10433 
10436 #endif /* __ASSEMBLY__ */
10437 
10439 #define ALT_SYSMGR_PINMUX_EMACIO8_OFST 0x20
10440 
10476 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_LSB 0
10477 
10478 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_MSB 1
10479 
10480 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_WIDTH 2
10481 
10482 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET_MSK 0x00000003
10483 
10484 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_CLR_MSK 0xfffffffc
10485 
10486 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_RESET 0x0
10487 
10488 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
10489 
10490 #define ALT_SYSMGR_PINMUX_EMACIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
10491 
10492 #ifndef __ASSEMBLY__
10493 
10504 {
10505  uint32_t sel : 2;
10506  uint32_t : 30;
10507 };
10508 
10511 #endif /* __ASSEMBLY__ */
10512 
10514 #define ALT_SYSMGR_PINMUX_EMACIO9_OFST 0x24
10515 
10551 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_LSB 0
10552 
10553 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_MSB 1
10554 
10555 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_WIDTH 2
10556 
10557 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET_MSK 0x00000003
10558 
10559 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_CLR_MSK 0xfffffffc
10560 
10561 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_RESET 0x0
10562 
10563 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
10564 
10565 #define ALT_SYSMGR_PINMUX_EMACIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
10566 
10567 #ifndef __ASSEMBLY__
10568 
10579 {
10580  uint32_t sel : 2;
10581  uint32_t : 30;
10582 };
10583 
10586 #endif /* __ASSEMBLY__ */
10587 
10589 #define ALT_SYSMGR_PINMUX_EMACIO10_OFST 0x28
10590 
10626 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_LSB 0
10627 
10628 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_MSB 1
10629 
10630 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_WIDTH 2
10631 
10632 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET_MSK 0x00000003
10633 
10634 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_CLR_MSK 0xfffffffc
10635 
10636 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_RESET 0x0
10637 
10638 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
10639 
10640 #define ALT_SYSMGR_PINMUX_EMACIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
10641 
10642 #ifndef __ASSEMBLY__
10643 
10654 {
10655  uint32_t sel : 2;
10656  uint32_t : 30;
10657 };
10658 
10661 #endif /* __ASSEMBLY__ */
10662 
10664 #define ALT_SYSMGR_PINMUX_EMACIO11_OFST 0x2c
10665 
10701 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_LSB 0
10702 
10703 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_MSB 1
10704 
10705 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_WIDTH 2
10706 
10707 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET_MSK 0x00000003
10708 
10709 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_CLR_MSK 0xfffffffc
10710 
10711 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_RESET 0x0
10712 
10713 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
10714 
10715 #define ALT_SYSMGR_PINMUX_EMACIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
10716 
10717 #ifndef __ASSEMBLY__
10718 
10729 {
10730  uint32_t sel : 2;
10731  uint32_t : 30;
10732 };
10733 
10736 #endif /* __ASSEMBLY__ */
10737 
10739 #define ALT_SYSMGR_PINMUX_EMACIO12_OFST 0x30
10740 
10776 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_LSB 0
10777 
10778 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_MSB 1
10779 
10780 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_WIDTH 2
10781 
10782 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET_MSK 0x00000003
10783 
10784 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_CLR_MSK 0xfffffffc
10785 
10786 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_RESET 0x0
10787 
10788 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
10789 
10790 #define ALT_SYSMGR_PINMUX_EMACIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
10791 
10792 #ifndef __ASSEMBLY__
10793 
10804 {
10805  uint32_t sel : 2;
10806  uint32_t : 30;
10807 };
10808 
10811 #endif /* __ASSEMBLY__ */
10812 
10814 #define ALT_SYSMGR_PINMUX_EMACIO13_OFST 0x34
10815 
10851 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_LSB 0
10852 
10853 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_MSB 1
10854 
10855 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_WIDTH 2
10856 
10857 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET_MSK 0x00000003
10858 
10859 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_CLR_MSK 0xfffffffc
10860 
10861 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_RESET 0x0
10862 
10863 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
10864 
10865 #define ALT_SYSMGR_PINMUX_EMACIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
10866 
10867 #ifndef __ASSEMBLY__
10868 
10879 {
10880  uint32_t sel : 2;
10881  uint32_t : 30;
10882 };
10883 
10886 #endif /* __ASSEMBLY__ */
10887 
10889 #define ALT_SYSMGR_PINMUX_EMACIO14_OFST 0x38
10890 
10926 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_LSB 0
10927 
10928 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_MSB 1
10929 
10930 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_WIDTH 2
10931 
10932 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET_MSK 0x00000003
10933 
10934 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_CLR_MSK 0xfffffffc
10935 
10936 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_RESET 0x0
10937 
10938 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
10939 
10940 #define ALT_SYSMGR_PINMUX_EMACIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
10941 
10942 #ifndef __ASSEMBLY__
10943 
10954 {
10955  uint32_t sel : 2;
10956  uint32_t : 30;
10957 };
10958 
10961 #endif /* __ASSEMBLY__ */
10962 
10964 #define ALT_SYSMGR_PINMUX_EMACIO15_OFST 0x3c
10965 
11001 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_LSB 0
11002 
11003 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_MSB 1
11004 
11005 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_WIDTH 2
11006 
11007 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET_MSK 0x00000003
11008 
11009 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_CLR_MSK 0xfffffffc
11010 
11011 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_RESET 0x0
11012 
11013 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
11014 
11015 #define ALT_SYSMGR_PINMUX_EMACIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
11016 
11017 #ifndef __ASSEMBLY__
11018 
11029 {
11030  uint32_t sel : 2;
11031  uint32_t : 30;
11032 };
11033 
11036 #endif /* __ASSEMBLY__ */
11037 
11039 #define ALT_SYSMGR_PINMUX_EMACIO16_OFST 0x40
11040 
11076 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_LSB 0
11077 
11078 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_MSB 1
11079 
11080 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_WIDTH 2
11081 
11082 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET_MSK 0x00000003
11083 
11084 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_CLR_MSK 0xfffffffc
11085 
11086 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_RESET 0x0
11087 
11088 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
11089 
11090 #define ALT_SYSMGR_PINMUX_EMACIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
11091 
11092 #ifndef __ASSEMBLY__
11093 
11104 {
11105  uint32_t sel : 2;
11106  uint32_t : 30;
11107 };
11108 
11111 #endif /* __ASSEMBLY__ */
11112 
11114 #define ALT_SYSMGR_PINMUX_EMACIO17_OFST 0x44
11115 
11151 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_LSB 0
11152 
11153 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_MSB 1
11154 
11155 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_WIDTH 2
11156 
11157 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET_MSK 0x00000003
11158 
11159 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_CLR_MSK 0xfffffffc
11160 
11161 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_RESET 0x0
11162 
11163 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
11164 
11165 #define ALT_SYSMGR_PINMUX_EMACIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
11166 
11167 #ifndef __ASSEMBLY__
11168 
11179 {
11180  uint32_t sel : 2;
11181  uint32_t : 30;
11182 };
11183 
11186 #endif /* __ASSEMBLY__ */
11187 
11189 #define ALT_SYSMGR_PINMUX_EMACIO18_OFST 0x48
11190 
11226 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_LSB 0
11227 
11228 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_MSB 1
11229 
11230 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_WIDTH 2
11231 
11232 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET_MSK 0x00000003
11233 
11234 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_CLR_MSK 0xfffffffc
11235 
11236 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_RESET 0x0
11237 
11238 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
11239 
11240 #define ALT_SYSMGR_PINMUX_EMACIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
11241 
11242 #ifndef __ASSEMBLY__
11243 
11254 {
11255  uint32_t sel : 2;
11256  uint32_t : 30;
11257 };
11258 
11261 #endif /* __ASSEMBLY__ */
11262 
11264 #define ALT_SYSMGR_PINMUX_EMACIO19_OFST 0x4c
11265 
11301 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_LSB 0
11302 
11303 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_MSB 1
11304 
11305 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_WIDTH 2
11306 
11307 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET_MSK 0x00000003
11308 
11309 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_CLR_MSK 0xfffffffc
11310 
11311 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_RESET 0x0
11312 
11313 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
11314 
11315 #define ALT_SYSMGR_PINMUX_FLSHIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
11316 
11317 #ifndef __ASSEMBLY__
11318 
11329 {
11330  uint32_t sel : 2;
11331  uint32_t : 30;
11332 };
11333 
11336 #endif /* __ASSEMBLY__ */
11337 
11339 #define ALT_SYSMGR_PINMUX_FLSHIO0_OFST 0x50
11340 
11376 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_LSB 0
11377 
11378 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_MSB 1
11379 
11380 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_WIDTH 2
11381 
11382 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET_MSK 0x00000003
11383 
11384 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_CLR_MSK 0xfffffffc
11385 
11386 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_RESET 0x0
11387 
11388 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
11389 
11390 #define ALT_SYSMGR_PINMUX_FLSHIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
11391 
11392 #ifndef __ASSEMBLY__
11393 
11404 {
11405  uint32_t sel : 2;
11406  uint32_t : 30;
11407 };
11408 
11411 #endif /* __ASSEMBLY__ */
11412 
11414 #define ALT_SYSMGR_PINMUX_FLSHIO1_OFST 0x54
11415 
11451 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_LSB 0
11452 
11453 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_MSB 1
11454 
11455 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_WIDTH 2
11456 
11457 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET_MSK 0x00000003
11458 
11459 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_CLR_MSK 0xfffffffc
11460 
11461 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_RESET 0x0
11462 
11463 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
11464 
11465 #define ALT_SYSMGR_PINMUX_FLSHIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
11466 
11467 #ifndef __ASSEMBLY__
11468 
11479 {
11480  uint32_t sel : 2;
11481  uint32_t : 30;
11482 };
11483 
11486 #endif /* __ASSEMBLY__ */
11487 
11489 #define ALT_SYSMGR_PINMUX_FLSHIO2_OFST 0x58
11490 
11526 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_LSB 0
11527 
11528 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_MSB 1
11529 
11530 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_WIDTH 2
11531 
11532 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET_MSK 0x00000003
11533 
11534 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_CLR_MSK 0xfffffffc
11535 
11536 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_RESET 0x0
11537 
11538 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
11539 
11540 #define ALT_SYSMGR_PINMUX_FLSHIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
11541 
11542 #ifndef __ASSEMBLY__
11543 
11554 {
11555  uint32_t sel : 2;
11556  uint32_t : 30;
11557 };
11558 
11561 #endif /* __ASSEMBLY__ */
11562 
11564 #define ALT_SYSMGR_PINMUX_FLSHIO3_OFST 0x5c
11565 
11601 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_LSB 0
11602 
11603 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_MSB 1
11604 
11605 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_WIDTH 2
11606 
11607 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET_MSK 0x00000003
11608 
11609 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_CLR_MSK 0xfffffffc
11610 
11611 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_RESET 0x0
11612 
11613 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
11614 
11615 #define ALT_SYSMGR_PINMUX_FLSHIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
11616 
11617 #ifndef __ASSEMBLY__
11618 
11629 {
11630  uint32_t sel : 2;
11631  uint32_t : 30;
11632 };
11633 
11636 #endif /* __ASSEMBLY__ */
11637 
11639 #define ALT_SYSMGR_PINMUX_FLSHIO4_OFST 0x60
11640 
11676 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_LSB 0
11677 
11678 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_MSB 1
11679 
11680 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_WIDTH 2
11681 
11682 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET_MSK 0x00000003
11683 
11684 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_CLR_MSK 0xfffffffc
11685 
11686 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_RESET 0x0
11687 
11688 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
11689 
11690 #define ALT_SYSMGR_PINMUX_FLSHIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
11691 
11692 #ifndef __ASSEMBLY__
11693 
11704 {
11705  uint32_t sel : 2;
11706  uint32_t : 30;
11707 };
11708 
11711 #endif /* __ASSEMBLY__ */
11712 
11714 #define ALT_SYSMGR_PINMUX_FLSHIO5_OFST 0x64
11715 
11751 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_LSB 0
11752 
11753 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_MSB 1
11754 
11755 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_WIDTH 2
11756 
11757 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET_MSK 0x00000003
11758 
11759 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_CLR_MSK 0xfffffffc
11760 
11761 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_RESET 0x0
11762 
11763 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
11764 
11765 #define ALT_SYSMGR_PINMUX_FLSHIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
11766 
11767 #ifndef __ASSEMBLY__
11768 
11779 {
11780  uint32_t sel : 2;
11781  uint32_t : 30;
11782 };
11783 
11786 #endif /* __ASSEMBLY__ */
11787 
11789 #define ALT_SYSMGR_PINMUX_FLSHIO6_OFST 0x68
11790 
11826 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_LSB 0
11827 
11828 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_MSB 1
11829 
11830 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_WIDTH 2
11831 
11832 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET_MSK 0x00000003
11833 
11834 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_CLR_MSK 0xfffffffc
11835 
11836 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_RESET 0x0
11837 
11838 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
11839 
11840 #define ALT_SYSMGR_PINMUX_FLSHIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
11841 
11842 #ifndef __ASSEMBLY__
11843 
11854 {
11855  uint32_t sel : 2;
11856  uint32_t : 30;
11857 };
11858 
11861 #endif /* __ASSEMBLY__ */
11862 
11864 #define ALT_SYSMGR_PINMUX_FLSHIO7_OFST 0x6c
11865 
11901 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_LSB 0
11902 
11903 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_MSB 1
11904 
11905 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_WIDTH 2
11906 
11907 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET_MSK 0x00000003
11908 
11909 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_CLR_MSK 0xfffffffc
11910 
11911 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_RESET 0x0
11912 
11913 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
11914 
11915 #define ALT_SYSMGR_PINMUX_FLSHIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
11916 
11917 #ifndef __ASSEMBLY__
11918 
11929 {
11930  uint32_t sel : 2;
11931  uint32_t : 30;
11932 };
11933 
11936 #endif /* __ASSEMBLY__ */
11937 
11939 #define ALT_SYSMGR_PINMUX_FLSHIO8_OFST 0x70
11940 
11976 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_LSB 0
11977 
11978 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_MSB 1
11979 
11980 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_WIDTH 2
11981 
11982 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET_MSK 0x00000003
11983 
11984 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_CLR_MSK 0xfffffffc
11985 
11986 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_RESET 0x0
11987 
11988 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
11989 
11990 #define ALT_SYSMGR_PINMUX_FLSHIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
11991 
11992 #ifndef __ASSEMBLY__
11993 
12004 {
12005  uint32_t sel : 2;
12006  uint32_t : 30;
12007 };
12008 
12011 #endif /* __ASSEMBLY__ */
12012 
12014 #define ALT_SYSMGR_PINMUX_FLSHIO9_OFST 0x74
12015 
12051 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_LSB 0
12052 
12053 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_MSB 1
12054 
12055 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_WIDTH 2
12056 
12057 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET_MSK 0x00000003
12058 
12059 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_CLR_MSK 0xfffffffc
12060 
12061 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_RESET 0x0
12062 
12063 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12064 
12065 #define ALT_SYSMGR_PINMUX_FLSHIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12066 
12067 #ifndef __ASSEMBLY__
12068 
12079 {
12080  uint32_t sel : 2;
12081  uint32_t : 30;
12082 };
12083 
12086 #endif /* __ASSEMBLY__ */
12087 
12089 #define ALT_SYSMGR_PINMUX_FLSHIO10_OFST 0x78
12090 
12126 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_LSB 0
12127 
12128 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_MSB 1
12129 
12130 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_WIDTH 2
12131 
12132 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET_MSK 0x00000003
12133 
12134 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_CLR_MSK 0xfffffffc
12135 
12136 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_RESET 0x0
12137 
12138 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
12139 
12140 #define ALT_SYSMGR_PINMUX_FLSHIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
12141 
12142 #ifndef __ASSEMBLY__
12143 
12154 {
12155  uint32_t sel : 2;
12156  uint32_t : 30;
12157 };
12158 
12161 #endif /* __ASSEMBLY__ */
12162 
12164 #define ALT_SYSMGR_PINMUX_FLSHIO11_OFST 0x7c
12165 
12201 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_LSB 0
12202 
12203 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_MSB 1
12204 
12205 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_WIDTH 2
12206 
12207 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET_MSK 0x00000003
12208 
12209 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_CLR_MSK 0xfffffffc
12210 
12211 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_RESET 0x0
12212 
12213 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
12214 
12215 #define ALT_SYSMGR_PINMUX_GENERALIO0_SEL_SET(value) (((value) << 0) & 0x00000003)
12216 
12217 #ifndef __ASSEMBLY__
12218 
12229 {
12230  uint32_t sel : 2;
12231  uint32_t : 30;
12232 };
12233 
12236 #endif /* __ASSEMBLY__ */
12237 
12239 #define ALT_SYSMGR_PINMUX_GENERALIO0_OFST 0x80
12240 
12276 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_LSB 0
12277 
12278 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_MSB 1
12279 
12280 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_WIDTH 2
12281 
12282 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET_MSK 0x00000003
12283 
12284 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_CLR_MSK 0xfffffffc
12285 
12286 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_RESET 0x0
12287 
12288 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
12289 
12290 #define ALT_SYSMGR_PINMUX_GENERALIO1_SEL_SET(value) (((value) << 0) & 0x00000003)
12291 
12292 #ifndef __ASSEMBLY__
12293 
12304 {
12305  uint32_t sel : 2;
12306  uint32_t : 30;
12307 };
12308 
12311 #endif /* __ASSEMBLY__ */
12312 
12314 #define ALT_SYSMGR_PINMUX_GENERALIO1_OFST 0x84
12315 
12351 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_LSB 0
12352 
12353 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_MSB 1
12354 
12355 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_WIDTH 2
12356 
12357 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET_MSK 0x00000003
12358 
12359 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_CLR_MSK 0xfffffffc
12360 
12361 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_RESET 0x0
12362 
12363 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
12364 
12365 #define ALT_SYSMGR_PINMUX_GENERALIO2_SEL_SET(value) (((value) << 0) & 0x00000003)
12366 
12367 #ifndef __ASSEMBLY__
12368 
12379 {
12380  uint32_t sel : 2;
12381  uint32_t : 30;
12382 };
12383 
12386 #endif /* __ASSEMBLY__ */
12387 
12389 #define ALT_SYSMGR_PINMUX_GENERALIO2_OFST 0x88
12390 
12426 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_LSB 0
12427 
12428 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_MSB 1
12429 
12430 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_WIDTH 2
12431 
12432 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET_MSK 0x00000003
12433 
12434 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_CLR_MSK 0xfffffffc
12435 
12436 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_RESET 0x0
12437 
12438 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
12439 
12440 #define ALT_SYSMGR_PINMUX_GENERALIO3_SEL_SET(value) (((value) << 0) & 0x00000003)
12441 
12442 #ifndef __ASSEMBLY__
12443 
12454 {
12455  uint32_t sel : 2;
12456  uint32_t : 30;
12457 };
12458 
12461 #endif /* __ASSEMBLY__ */
12462 
12464 #define ALT_SYSMGR_PINMUX_GENERALIO3_OFST 0x8c
12465 
12501 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_LSB 0
12502 
12503 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_MSB 1
12504 
12505 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_WIDTH 2
12506 
12507 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET_MSK 0x00000003
12508 
12509 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_CLR_MSK 0xfffffffc
12510 
12511 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_RESET 0x0
12512 
12513 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
12514 
12515 #define ALT_SYSMGR_PINMUX_GENERALIO4_SEL_SET(value) (((value) << 0) & 0x00000003)
12516 
12517 #ifndef __ASSEMBLY__
12518 
12529 {
12530  uint32_t sel : 2;
12531  uint32_t : 30;
12532 };
12533 
12536 #endif /* __ASSEMBLY__ */
12537 
12539 #define ALT_SYSMGR_PINMUX_GENERALIO4_OFST 0x90
12540 
12576 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB 0
12577 
12578 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB 1
12579 
12580 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH 2
12581 
12582 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK 0x00000003
12583 
12584 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK 0xfffffffc
12585 
12586 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET 0x0
12587 
12588 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
12589 
12590 #define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value) (((value) << 0) & 0x00000003)
12591 
12592 #ifndef __ASSEMBLY__
12593 
12604 {
12605  uint32_t sel : 2;
12606  uint32_t : 30;
12607 };
12608 
12611 #endif /* __ASSEMBLY__ */
12612 
12614 #define ALT_SYSMGR_PINMUX_GENERALIO5_OFST 0x94
12615 
12651 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_LSB 0
12652 
12653 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_MSB 1
12654 
12655 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_WIDTH 2
12656 
12657 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET_MSK 0x00000003
12658 
12659 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_CLR_MSK 0xfffffffc
12660 
12661 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_RESET 0x0
12662 
12663 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
12664 
12665 #define ALT_SYSMGR_PINMUX_GENERALIO6_SEL_SET(value) (((value) << 0) & 0x00000003)
12666 
12667 #ifndef __ASSEMBLY__
12668 
12679 {
12680  uint32_t sel : 2;
12681  uint32_t : 30;
12682 };
12683 
12686 #endif /* __ASSEMBLY__ */
12687 
12689 #define ALT_SYSMGR_PINMUX_GENERALIO6_OFST 0x98
12690 
12726 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_LSB 0
12727 
12728 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_MSB 1
12729 
12730 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_WIDTH 2
12731 
12732 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET_MSK 0x00000003
12733 
12734 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_CLR_MSK 0xfffffffc
12735 
12736 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_RESET 0x0
12737 
12738 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
12739 
12740 #define ALT_SYSMGR_PINMUX_GENERALIO7_SEL_SET(value) (((value) << 0) & 0x00000003)
12741 
12742 #ifndef __ASSEMBLY__
12743 
12754 {
12755  uint32_t sel : 2;
12756  uint32_t : 30;
12757 };
12758 
12761 #endif /* __ASSEMBLY__ */
12762 
12764 #define ALT_SYSMGR_PINMUX_GENERALIO7_OFST 0x9c
12765 
12801 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_LSB 0
12802 
12803 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_MSB 1
12804 
12805 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_WIDTH 2
12806 
12807 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET_MSK 0x00000003
12808 
12809 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_CLR_MSK 0xfffffffc
12810 
12811 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_RESET 0x0
12812 
12813 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
12814 
12815 #define ALT_SYSMGR_PINMUX_GENERALIO8_SEL_SET(value) (((value) << 0) & 0x00000003)
12816 
12817 #ifndef __ASSEMBLY__
12818 
12829 {
12830  uint32_t sel : 2;
12831  uint32_t : 30;
12832 };
12833 
12836 #endif /* __ASSEMBLY__ */
12837 
12839 #define ALT_SYSMGR_PINMUX_GENERALIO8_OFST 0xa0
12840 
12876 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_LSB 0
12877 
12878 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_MSB 1
12879 
12880 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_WIDTH 2
12881 
12882 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET_MSK 0x00000003
12883 
12884 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_CLR_MSK 0xfffffffc
12885 
12886 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_RESET 0x0
12887 
12888 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
12889 
12890 #define ALT_SYSMGR_PINMUX_GENERALIO9_SEL_SET(value) (((value) << 0) & 0x00000003)
12891 
12892 #ifndef __ASSEMBLY__
12893 
12904 {
12905  uint32_t sel : 2;
12906  uint32_t : 30;
12907 };
12908 
12911 #endif /* __ASSEMBLY__ */
12912 
12914 #define ALT_SYSMGR_PINMUX_GENERALIO9_OFST 0xa4
12915 
12951 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_LSB 0
12952 
12953 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_MSB 1
12954 
12955 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_WIDTH 2
12956 
12957 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET_MSK 0x00000003
12958 
12959 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_CLR_MSK 0xfffffffc
12960 
12961 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_RESET 0x0
12962 
12963 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
12964 
12965 #define ALT_SYSMGR_PINMUX_GENERALIO10_SEL_SET(value) (((value) << 0) & 0x00000003)
12966 
12967 #ifndef __ASSEMBLY__
12968 
12979 {
12980  uint32_t sel : 2;
12981  uint32_t : 30;
12982 };
12983 
12986 #endif /* __ASSEMBLY__ */
12987 
12989 #define ALT_SYSMGR_PINMUX_GENERALIO10_OFST 0xa8
12990 
13026 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_LSB 0
13027 
13028 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_MSB 1
13029 
13030 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_WIDTH 2
13031 
13032 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET_MSK 0x00000003
13033 
13034 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_CLR_MSK 0xfffffffc
13035 
13036 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_RESET 0x0
13037 
13038 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
13039 
13040 #define ALT_SYSMGR_PINMUX_GENERALIO11_SEL_SET(value) (((value) << 0) & 0x00000003)
13041 
13042 #ifndef __ASSEMBLY__
13043 
13054 {
13055  uint32_t sel : 2;
13056  uint32_t : 30;
13057 };
13058 
13061 #endif /* __ASSEMBLY__ */
13062 
13064 #define ALT_SYSMGR_PINMUX_GENERALIO11_OFST 0xac
13065 
13101 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_LSB 0
13102 
13103 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_MSB 1
13104 
13105 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_WIDTH 2
13106 
13107 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET_MSK 0x00000003
13108 
13109 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_CLR_MSK 0xfffffffc
13110 
13111 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_RESET 0x0
13112 
13113 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
13114 
13115 #define ALT_SYSMGR_PINMUX_GENERALIO12_SEL_SET(value) (((value) << 0) & 0x00000003)
13116 
13117 #ifndef __ASSEMBLY__
13118 
13129 {
13130  uint32_t sel : 2;
13131  uint32_t : 30;
13132 };
13133 
13136 #endif /* __ASSEMBLY__ */
13137 
13139 #define ALT_SYSMGR_PINMUX_GENERALIO12_OFST 0xb0
13140 
13176 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_LSB 0
13177 
13178 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_MSB 1
13179 
13180 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_WIDTH 2
13181 
13182 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET_MSK 0x00000003
13183 
13184 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_CLR_MSK 0xfffffffc
13185 
13186 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_RESET 0x0
13187 
13188 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
13189 
13190 #define ALT_SYSMGR_PINMUX_GENERALIO13_SEL_SET(value) (((value) << 0) & 0x00000003)
13191 
13192 #ifndef __ASSEMBLY__
13193 
13204 {
13205  uint32_t sel : 2;
13206  uint32_t : 30;
13207 };
13208 
13211 #endif /* __ASSEMBLY__ */
13212 
13214 #define ALT_SYSMGR_PINMUX_GENERALIO13_OFST 0xb4
13215 
13251 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_LSB 0
13252 
13253 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_MSB 1
13254 
13255 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_WIDTH 2
13256 
13257 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET_MSK 0x00000003
13258 
13259 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_CLR_MSK 0xfffffffc
13260 
13261 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_RESET 0x0
13262 
13263 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
13264 
13265 #define ALT_SYSMGR_PINMUX_GENERALIO14_SEL_SET(value) (((value) << 0) & 0x00000003)
13266 
13267 #ifndef __ASSEMBLY__
13268 
13279 {
13280  uint32_t sel : 2;
13281  uint32_t : 30;
13282 };
13283 
13286 #endif /* __ASSEMBLY__ */
13287 
13289 #define ALT_SYSMGR_PINMUX_GENERALIO14_OFST 0xb8
13290 
13326 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_LSB 0
13327 
13328 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_MSB 1
13329 
13330 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_WIDTH 2
13331 
13332 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET_MSK 0x00000003
13333 
13334 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_CLR_MSK 0xfffffffc
13335 
13336 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_RESET 0x0
13337 
13338 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
13339 
13340 #define ALT_SYSMGR_PINMUX_GENERALIO15_SEL_SET(value) (((value) << 0) & 0x00000003)
13341 
13342 #ifndef __ASSEMBLY__
13343 
13354 {
13355  uint32_t sel : 2;
13356  uint32_t : 30;
13357 };
13358 
13361 #endif /* __ASSEMBLY__ */
13362 
13364 #define ALT_SYSMGR_PINMUX_GENERALIO15_OFST 0xbc
13365 
13401 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_LSB 0
13402 
13403 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_MSB 1
13404 
13405 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_WIDTH 2
13406 
13407 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET_MSK 0x00000003
13408 
13409 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_CLR_MSK 0xfffffffc
13410 
13411 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_RESET 0x0
13412 
13413 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
13414 
13415 #define ALT_SYSMGR_PINMUX_GENERALIO16_SEL_SET(value) (((value) << 0) & 0x00000003)
13416 
13417 #ifndef __ASSEMBLY__
13418 
13429 {
13430  uint32_t sel : 2;
13431  uint32_t : 30;
13432 };
13433 
13436 #endif /* __ASSEMBLY__ */
13437 
13439 #define ALT_SYSMGR_PINMUX_GENERALIO16_OFST 0xc0
13440 
13476 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_LSB 0
13477 
13478 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_MSB 1
13479 
13480 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_WIDTH 2
13481 
13482 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET_MSK 0x00000003
13483 
13484 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_CLR_MSK 0xfffffffc
13485 
13486 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_RESET 0x0
13487 
13488 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
13489 
13490 #define ALT_SYSMGR_PINMUX_GENERALIO17_SEL_SET(value) (((value) << 0) & 0x00000003)
13491 
13492 #ifndef __ASSEMBLY__
13493 
13504 {
13505  uint32_t sel : 2;
13506  uint32_t : 30;
13507 };
13508 
13511 #endif /* __ASSEMBLY__ */
13512 
13514 #define ALT_SYSMGR_PINMUX_GENERALIO17_OFST 0xc4
13515 
13551 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_LSB 0
13552 
13553 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_MSB 1
13554 
13555 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_WIDTH 2
13556 
13557 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET_MSK 0x00000003
13558 
13559 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_CLR_MSK 0xfffffffc
13560 
13561 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_RESET 0x0
13562 
13563 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
13564 
13565 #define ALT_SYSMGR_PINMUX_GENERALIO18_SEL_SET(value) (((value) << 0) & 0x00000003)
13566 
13567 #ifndef __ASSEMBLY__
13568 
13579 {
13580  uint32_t sel : 2;
13581  uint32_t : 30;
13582 };
13583 
13586 #endif /* __ASSEMBLY__ */
13587 
13589 #define ALT_SYSMGR_PINMUX_GENERALIO18_OFST 0xc8
13590 
13626 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_LSB 0
13627 
13628 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_MSB 1
13629 
13630 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_WIDTH 2
13631 
13632 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET_MSK 0x00000003
13633 
13634 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_CLR_MSK 0xfffffffc
13635 
13636 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_RESET 0x0
13637 
13638 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
13639 
13640 #define ALT_SYSMGR_PINMUX_GENERALIO19_SEL_SET(value) (((value) << 0) & 0x00000003)
13641 
13642 #ifndef __ASSEMBLY__
13643 
13654 {
13655  uint32_t sel : 2;
13656  uint32_t : 30;
13657 };
13658 
13661 #endif /* __ASSEMBLY__ */
13662 
13664 #define ALT_SYSMGR_PINMUX_GENERALIO19_OFST 0xcc
13665 
13701 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_LSB 0
13702 
13703 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_MSB 1
13704 
13705 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_WIDTH 2
13706 
13707 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET_MSK 0x00000003
13708 
13709 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_CLR_MSK 0xfffffffc
13710 
13711 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_RESET 0x0
13712 
13713 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
13714 
13715 #define ALT_SYSMGR_PINMUX_GENERALIO20_SEL_SET(value) (((value) << 0) & 0x00000003)
13716 
13717 #ifndef __ASSEMBLY__
13718 
13729 {
13730  uint32_t sel : 2;
13731  uint32_t : 30;
13732 };
13733 
13736 #endif /* __ASSEMBLY__ */
13737 
13739 #define ALT_SYSMGR_PINMUX_GENERALIO20_OFST 0xd0
13740 
13776 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_LSB 0
13777 
13778 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_MSB 1
13779 
13780 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_WIDTH 2
13781 
13782 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET_MSK 0x00000003
13783 
13784 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_CLR_MSK 0xfffffffc
13785 
13786 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_RESET 0x0
13787 
13788 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
13789 
13790 #define ALT_SYSMGR_PINMUX_GENERALIO21_SEL_SET(value) (((value) << 0) & 0x00000003)
13791 
13792 #ifndef __ASSEMBLY__
13793 
13804 {
13805  uint32_t sel : 2;
13806  uint32_t : 30;
13807 };
13808 
13811 #endif /* __ASSEMBLY__ */
13812 
13814 #define ALT_SYSMGR_PINMUX_GENERALIO21_OFST 0xd4
13815 
13851 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_LSB 0
13852 
13853 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_MSB 1
13854 
13855 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_WIDTH 2
13856 
13857 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET_MSK 0x00000003
13858 
13859 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_CLR_MSK 0xfffffffc
13860 
13861 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_RESET 0x0
13862 
13863 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_GET(value) (((value) & 0x00000003) >> 0)
13864 
13865 #define ALT_SYSMGR_PINMUX_GENERALIO22_SEL_SET(value) (((value) << 0) & 0x00000003)
13866 
13867 #ifndef __ASSEMBLY__
13868 
13879 {
13880  uint32_t sel : 2;
13881  uint32_t : 30;
13882 };
13883 
13886 #endif /* __ASSEMBLY__ */
13887 
13889 #define ALT_SYSMGR_PINMUX_GENERALIO22_OFST 0xd8
13890 
13926 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_LSB 0
13927 
13928 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_MSB 1
13929 
13930 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_WIDTH 2
13931 
13932 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET_MSK 0x00000003
13933 
13934 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_CLR_MSK 0xfffffffc
13935 
13936 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_RESET 0x0
13937 
13938 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_GET(value) (((value) & 0x00000003) >> 0)
13939 
13940 #define ALT_SYSMGR_PINMUX_GENERALIO23_SEL_SET(value) (((value) << 0) & 0x00000003)
13941 
13942 #ifndef __ASSEMBLY__
13943 
13954 {
13955  uint32_t sel : 2;
13956  uint32_t : 30;
13957 };
13958 
13961 #endif /* __ASSEMBLY__ */
13962 
13964 #define ALT_SYSMGR_PINMUX_GENERALIO23_OFST 0xdc
13965 
14001 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_LSB 0
14002 
14003 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_MSB 1
14004 
14005 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_WIDTH 2
14006 
14007 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET_MSK 0x00000003
14008 
14009 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_CLR_MSK 0xfffffffc
14010 
14011 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_RESET 0x0
14012 
14013 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_GET(value) (((value) & 0x00000003) >> 0)
14014 
14015 #define ALT_SYSMGR_PINMUX_GENERALIO24_SEL_SET(value) (((value) << 0) & 0x00000003)
14016 
14017 #ifndef __ASSEMBLY__
14018 
14029 {
14030  uint32_t sel : 2;
14031  uint32_t : 30;
14032 };
14033 
14036 #endif /* __ASSEMBLY__ */
14037 
14039 #define ALT_SYSMGR_PINMUX_GENERALIO24_OFST 0xe0
14040 
14076 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_LSB 0
14077 
14078 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_MSB 1
14079 
14080 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_WIDTH 2
14081 
14082 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET_MSK 0x00000003
14083 
14084 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_CLR_MSK 0xfffffffc
14085 
14086 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_RESET 0x0
14087 
14088 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_GET(value) (((value) & 0x00000003) >> 0)
14089 
14090 #define ALT_SYSMGR_PINMUX_GENERALIO25_SEL_SET(value) (((value) << 0) & 0x00000003)
14091 
14092 #ifndef __ASSEMBLY__
14093 
14104 {
14105  uint32_t sel : 2;
14106  uint32_t : 30;
14107 };
14108 
14111 #endif /* __ASSEMBLY__ */
14112 
14114 #define ALT_SYSMGR_PINMUX_GENERALIO25_OFST 0xe4
14115 
14151 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_LSB 0
14152 
14153 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_MSB 1
14154 
14155 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_WIDTH 2
14156 
14157 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET_MSK 0x00000003
14158 
14159 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_CLR_MSK 0xfffffffc
14160 
14161 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_RESET 0x0
14162 
14163 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_GET(value) (((value) & 0x00000003) >> 0)
14164 
14165 #define ALT_SYSMGR_PINMUX_GENERALIO26_SEL_SET(value) (((value) << 0) & 0x00000003)
14166 
14167 #ifndef __ASSEMBLY__
14168 
14179 {
14180  uint32_t sel : 2;
14181  uint32_t : 30;
14182 };
14183 
14186 #endif /* __ASSEMBLY__ */
14187 
14189 #define ALT_SYSMGR_PINMUX_GENERALIO26_OFST 0xe8
14190 
14226 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_LSB 0
14227 
14228 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_MSB 1
14229 
14230 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_WIDTH 2
14231 
14232 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET_MSK 0x00000003
14233 
14234 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_CLR_MSK 0xfffffffc
14235 
14236 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_RESET 0x0
14237 
14238 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_GET(value) (((value) & 0x00000003) >> 0)
14239 
14240 #define ALT_SYSMGR_PINMUX_GENERALIO27_SEL_SET(value) (((value) << 0) & 0x00000003)
14241 
14242 #ifndef __ASSEMBLY__
14243 
14254 {
14255  uint32_t sel : 2;
14256  uint32_t : 30;
14257 };
14258 
14261 #endif /* __ASSEMBLY__ */
14262 
14264 #define ALT_SYSMGR_PINMUX_GENERALIO27_OFST 0xec
14265 
14301 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_LSB 0
14302 
14303 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_MSB 1
14304 
14305 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_WIDTH 2
14306 
14307 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET_MSK 0x00000003
14308 
14309 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_CLR_MSK 0xfffffffc
14310 
14311 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_RESET 0x0
14312 
14313 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_GET(value) (((value) & 0x00000003) >> 0)
14314 
14315 #define ALT_SYSMGR_PINMUX_GENERALIO28_SEL_SET(value) (((value) << 0) & 0x00000003)
14316 
14317 #ifndef __ASSEMBLY__
14318 
14329 {
14330  uint32_t sel : 2;
14331  uint32_t : 30;
14332 };
14333 
14336 #endif /* __ASSEMBLY__ */
14337 
14339 #define ALT_SYSMGR_PINMUX_GENERALIO28_OFST 0xf0
14340 
14376 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_LSB 0
14377 
14378 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_MSB 1
14379 
14380 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_WIDTH 2
14381 
14382 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET_MSK 0x00000003
14383 
14384 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_CLR_MSK 0xfffffffc
14385 
14386 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_RESET 0x0
14387 
14388 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_GET(value) (((value) & 0x00000003) >> 0)
14389 
14390 #define ALT_SYSMGR_PINMUX_GENERALIO29_SEL_SET(value) (((value) << 0) & 0x00000003)
14391 
14392 #ifndef __ASSEMBLY__
14393 
14404 {
14405  uint32_t sel : 2;
14406  uint32_t : 30;
14407 };
14408 
14411 #endif /* __ASSEMBLY__ */
14412 
14414 #define ALT_SYSMGR_PINMUX_GENERALIO29_OFST 0xf4
14415 
14451 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_LSB 0
14452 
14453 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_MSB 1
14454 
14455 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_WIDTH 2
14456 
14457 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET_MSK 0x00000003
14458 
14459 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_CLR_MSK 0xfffffffc
14460 
14461 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_RESET 0x0
14462 
14463 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_GET(value) (((value) & 0x00000003) >> 0)
14464 
14465 #define ALT_SYSMGR_PINMUX_GENERALIO30_SEL_SET(value) (((value) << 0) & 0x00000003)
14466 
14467 #ifndef __ASSEMBLY__
14468 
14479 {
14480  uint32_t sel : 2;
14481  uint32_t : 30;
14482 };
14483 
14486 #endif /* __ASSEMBLY__ */
14487 
14489 #define ALT_SYSMGR_PINMUX_GENERALIO30_OFST 0xf8
14490 
14526 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_LSB 0
14527 
14528 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_MSB 1
14529 
14530 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_WIDTH 2
14531 
14532 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET_MSK 0x00000003
14533 
14534 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_CLR_MSK 0xfffffffc
14535 
14536 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_RESET 0x0
14537 
14538 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_GET(value) (((value) & 0x00000003) >> 0)
14539 
14540 #define ALT_SYSMGR_PINMUX_GENERALIO31_SEL_SET(value) (((value) << 0) & 0x00000003)
14541 
14542 #ifndef __ASSEMBLY__
14543 
14554 {
14555  uint32_t sel : 2;
14556  uint32_t : 30;
14557 };
14558 
14561 #endif /* __ASSEMBLY__ */
14562 
14564 #define ALT_SYSMGR_PINMUX_GENERALIO31_OFST 0xfc
14565 
14601 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_LSB 0
14602 
14603 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_MSB 1
14604 
14605 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_WIDTH 2
14606 
14607 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET_MSK 0x00000003
14608 
14609 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_CLR_MSK 0xfffffffc
14610 
14611 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_RESET 0x0
14612 
14613 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
14614 
14615 #define ALT_SYSMGR_PINMUX_MIXED1IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
14616 
14617 #ifndef __ASSEMBLY__
14618 
14629 {
14630  uint32_t sel : 2;
14631  uint32_t : 30;
14632 };
14633 
14636 #endif /* __ASSEMBLY__ */
14637 
14639 #define ALT_SYSMGR_PINMUX_MIXED1IO0_OFST 0x100
14640 
14676 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_LSB 0
14677 
14678 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_MSB 1
14679 
14680 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_WIDTH 2
14681 
14682 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET_MSK 0x00000003
14683 
14684 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_CLR_MSK 0xfffffffc
14685 
14686 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_RESET 0x0
14687 
14688 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
14689 
14690 #define ALT_SYSMGR_PINMUX_MIXED1IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
14691 
14692 #ifndef __ASSEMBLY__
14693 
14704 {
14705  uint32_t sel : 2;
14706  uint32_t : 30;
14707 };
14708 
14711 #endif /* __ASSEMBLY__ */
14712 
14714 #define ALT_SYSMGR_PINMUX_MIXED1IO1_OFST 0x104
14715 
14751 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_LSB 0
14752 
14753 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_MSB 1
14754 
14755 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_WIDTH 2
14756 
14757 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET_MSK 0x00000003
14758 
14759 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_CLR_MSK 0xfffffffc
14760 
14761 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_RESET 0x0
14762 
14763 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
14764 
14765 #define ALT_SYSMGR_PINMUX_MIXED1IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
14766 
14767 #ifndef __ASSEMBLY__
14768 
14779 {
14780  uint32_t sel : 2;
14781  uint32_t : 30;
14782 };
14783 
14786 #endif /* __ASSEMBLY__ */
14787 
14789 #define ALT_SYSMGR_PINMUX_MIXED1IO2_OFST 0x108
14790 
14826 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_LSB 0
14827 
14828 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_MSB 1
14829 
14830 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_WIDTH 2
14831 
14832 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET_MSK 0x00000003
14833 
14834 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_CLR_MSK 0xfffffffc
14835 
14836 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_RESET 0x0
14837 
14838 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
14839 
14840 #define ALT_SYSMGR_PINMUX_MIXED1IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
14841 
14842 #ifndef __ASSEMBLY__
14843 
14854 {
14855  uint32_t sel : 2;
14856  uint32_t : 30;
14857 };
14858 
14861 #endif /* __ASSEMBLY__ */
14862 
14864 #define ALT_SYSMGR_PINMUX_MIXED1IO3_OFST 0x10c
14865 
14901 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_LSB 0
14902 
14903 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_MSB 1
14904 
14905 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_WIDTH 2
14906 
14907 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET_MSK 0x00000003
14908 
14909 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_CLR_MSK 0xfffffffc
14910 
14911 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_RESET 0x0
14912 
14913 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
14914 
14915 #define ALT_SYSMGR_PINMUX_MIXED1IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
14916 
14917 #ifndef __ASSEMBLY__
14918 
14929 {
14930  uint32_t sel : 2;
14931  uint32_t : 30;
14932 };
14933 
14936 #endif /* __ASSEMBLY__ */
14937 
14939 #define ALT_SYSMGR_PINMUX_MIXED1IO4_OFST 0x110
14940 
14976 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_LSB 0
14977 
14978 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_MSB 1
14979 
14980 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_WIDTH 2
14981 
14982 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET_MSK 0x00000003
14983 
14984 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_CLR_MSK 0xfffffffc
14985 
14986 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_RESET 0x0
14987 
14988 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
14989 
14990 #define ALT_SYSMGR_PINMUX_MIXED1IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
14991 
14992 #ifndef __ASSEMBLY__
14993 
15004 {
15005  uint32_t sel : 2;
15006  uint32_t : 30;
15007 };
15008 
15011 #endif /* __ASSEMBLY__ */
15012 
15014 #define ALT_SYSMGR_PINMUX_MIXED1IO5_OFST 0x114
15015 
15051 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_LSB 0
15052 
15053 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_MSB 1
15054 
15055 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_WIDTH 2
15056 
15057 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET_MSK 0x00000003
15058 
15059 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_CLR_MSK 0xfffffffc
15060 
15061 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_RESET 0x0
15062 
15063 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
15064 
15065 #define ALT_SYSMGR_PINMUX_MIXED1IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
15066 
15067 #ifndef __ASSEMBLY__
15068 
15079 {
15080  uint32_t sel : 2;
15081  uint32_t : 30;
15082 };
15083 
15086 #endif /* __ASSEMBLY__ */
15087 
15089 #define ALT_SYSMGR_PINMUX_MIXED1IO6_OFST 0x118
15090 
15126 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_LSB 0
15127 
15128 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_MSB 1
15129 
15130 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_WIDTH 2
15131 
15132 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET_MSK 0x00000003
15133 
15134 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_CLR_MSK 0xfffffffc
15135 
15136 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_RESET 0x0
15137 
15138 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
15139 
15140 #define ALT_SYSMGR_PINMUX_MIXED1IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
15141 
15142 #ifndef __ASSEMBLY__
15143 
15154 {
15155  uint32_t sel : 2;
15156  uint32_t : 30;
15157 };
15158 
15161 #endif /* __ASSEMBLY__ */
15162 
15164 #define ALT_SYSMGR_PINMUX_MIXED1IO7_OFST 0x11c
15165 
15201 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_LSB 0
15202 
15203 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_MSB 1
15204 
15205 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_WIDTH 2
15206 
15207 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET_MSK 0x00000003
15208 
15209 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_CLR_MSK 0xfffffffc
15210 
15211 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_RESET 0x0
15212 
15213 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_GET(value) (((value) & 0x00000003) >> 0)
15214 
15215 #define ALT_SYSMGR_PINMUX_MIXED1IO8_SEL_SET(value) (((value) << 0) & 0x00000003)
15216 
15217 #ifndef __ASSEMBLY__
15218 
15229 {
15230  uint32_t sel : 2;
15231  uint32_t : 30;
15232 };
15233 
15236 #endif /* __ASSEMBLY__ */
15237 
15239 #define ALT_SYSMGR_PINMUX_MIXED1IO8_OFST 0x120
15240 
15276 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_LSB 0
15277 
15278 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_MSB 1
15279 
15280 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_WIDTH 2
15281 
15282 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET_MSK 0x00000003
15283 
15284 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_CLR_MSK 0xfffffffc
15285 
15286 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_RESET 0x0
15287 
15288 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_GET(value) (((value) & 0x00000003) >> 0)
15289 
15290 #define ALT_SYSMGR_PINMUX_MIXED1IO9_SEL_SET(value) (((value) << 0) & 0x00000003)
15291 
15292 #ifndef __ASSEMBLY__
15293 
15304 {
15305  uint32_t sel : 2;
15306  uint32_t : 30;
15307 };
15308 
15311 #endif /* __ASSEMBLY__ */
15312 
15314 #define ALT_SYSMGR_PINMUX_MIXED1IO9_OFST 0x124
15315 
15351 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_LSB 0
15352 
15353 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_MSB 1
15354 
15355 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_WIDTH 2
15356 
15357 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET_MSK 0x00000003
15358 
15359 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_CLR_MSK 0xfffffffc
15360 
15361 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_RESET 0x0
15362 
15363 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_GET(value) (((value) & 0x00000003) >> 0)
15364 
15365 #define ALT_SYSMGR_PINMUX_MIXED1IO10_SEL_SET(value) (((value) << 0) & 0x00000003)
15366 
15367 #ifndef __ASSEMBLY__
15368 
15379 {
15380  uint32_t sel : 2;
15381  uint32_t : 30;
15382 };
15383 
15386 #endif /* __ASSEMBLY__ */
15387 
15389 #define ALT_SYSMGR_PINMUX_MIXED1IO10_OFST 0x128
15390 
15426 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_LSB 0
15427 
15428 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_MSB 1
15429 
15430 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_WIDTH 2
15431 
15432 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET_MSK 0x00000003
15433 
15434 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_CLR_MSK 0xfffffffc
15435 
15436 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_RESET 0x0
15437 
15438 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_GET(value) (((value) & 0x00000003) >> 0)
15439 
15440 #define ALT_SYSMGR_PINMUX_MIXED1IO11_SEL_SET(value) (((value) << 0) & 0x00000003)
15441 
15442 #ifndef __ASSEMBLY__
15443 
15454 {
15455  uint32_t sel : 2;
15456  uint32_t : 30;
15457 };
15458 
15461 #endif /* __ASSEMBLY__ */
15462 
15464 #define ALT_SYSMGR_PINMUX_MIXED1IO11_OFST 0x12c
15465 
15501 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_LSB 0
15502 
15503 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_MSB 1
15504 
15505 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_WIDTH 2
15506 
15507 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET_MSK 0x00000003
15508 
15509 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_CLR_MSK 0xfffffffc
15510 
15511 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_RESET 0x0
15512 
15513 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_GET(value) (((value) & 0x00000003) >> 0)
15514 
15515 #define ALT_SYSMGR_PINMUX_MIXED1IO12_SEL_SET(value) (((value) << 0) & 0x00000003)
15516 
15517 #ifndef __ASSEMBLY__
15518 
15529 {
15530  uint32_t sel : 2;
15531  uint32_t : 30;
15532 };
15533 
15536 #endif /* __ASSEMBLY__ */
15537 
15539 #define ALT_SYSMGR_PINMUX_MIXED1IO12_OFST 0x130
15540 
15576 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_LSB 0
15577 
15578 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_MSB 1
15579 
15580 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_WIDTH 2
15581 
15582 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET_MSK 0x00000003
15583 
15584 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_CLR_MSK 0xfffffffc
15585 
15586 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_RESET 0x0
15587 
15588 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_GET(value) (((value) & 0x00000003) >> 0)
15589 
15590 #define ALT_SYSMGR_PINMUX_MIXED1IO13_SEL_SET(value) (((value) << 0) & 0x00000003)
15591 
15592 #ifndef __ASSEMBLY__
15593 
15604 {
15605  uint32_t sel : 2;
15606  uint32_t : 30;
15607 };
15608 
15611 #endif /* __ASSEMBLY__ */
15612 
15614 #define ALT_SYSMGR_PINMUX_MIXED1IO13_OFST 0x134
15615 
15651 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_LSB 0
15652 
15653 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_MSB 1
15654 
15655 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_WIDTH 2
15656 
15657 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET_MSK 0x00000003
15658 
15659 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_CLR_MSK 0xfffffffc
15660 
15661 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_RESET 0x0
15662 
15663 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_GET(value) (((value) & 0x00000003) >> 0)
15664 
15665 #define ALT_SYSMGR_PINMUX_MIXED1IO14_SEL_SET(value) (((value) << 0) & 0x00000003)
15666 
15667 #ifndef __ASSEMBLY__
15668 
15679 {
15680  uint32_t sel : 2;
15681  uint32_t : 30;
15682 };
15683 
15686 #endif /* __ASSEMBLY__ */
15687 
15689 #define ALT_SYSMGR_PINMUX_MIXED1IO14_OFST 0x138
15690 
15726 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_LSB 0
15727 
15728 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_MSB 1
15729 
15730 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_WIDTH 2
15731 
15732 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET_MSK 0x00000003
15733 
15734 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_CLR_MSK 0xfffffffc
15735 
15736 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_RESET 0x0
15737 
15738 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_GET(value) (((value) & 0x00000003) >> 0)
15739 
15740 #define ALT_SYSMGR_PINMUX_MIXED1IO15_SEL_SET(value) (((value) << 0) & 0x00000003)
15741 
15742 #ifndef __ASSEMBLY__
15743 
15754 {
15755  uint32_t sel : 2;
15756  uint32_t : 30;
15757 };
15758 
15761 #endif /* __ASSEMBLY__ */
15762 
15764 #define ALT_SYSMGR_PINMUX_MIXED1IO15_OFST 0x13c
15765 
15801 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_LSB 0
15802 
15803 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_MSB 1
15804 
15805 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_WIDTH 2
15806 
15807 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET_MSK 0x00000003
15808 
15809 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_CLR_MSK 0xfffffffc
15810 
15811 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_RESET 0x0
15812 
15813 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_GET(value) (((value) & 0x00000003) >> 0)
15814 
15815 #define ALT_SYSMGR_PINMUX_MIXED1IO16_SEL_SET(value) (((value) << 0) & 0x00000003)
15816 
15817 #ifndef __ASSEMBLY__
15818 
15829 {
15830  uint32_t sel : 2;
15831  uint32_t : 30;
15832 };
15833 
15836 #endif /* __ASSEMBLY__ */
15837 
15839 #define ALT_SYSMGR_PINMUX_MIXED1IO16_OFST 0x140
15840 
15876 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_LSB 0
15877 
15878 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_MSB 1
15879 
15880 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_WIDTH 2
15881 
15882 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET_MSK 0x00000003
15883 
15884 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_CLR_MSK 0xfffffffc
15885 
15886 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_RESET 0x0
15887 
15888 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_GET(value) (((value) & 0x00000003) >> 0)
15889 
15890 #define ALT_SYSMGR_PINMUX_MIXED1IO17_SEL_SET(value) (((value) << 0) & 0x00000003)
15891 
15892 #ifndef __ASSEMBLY__
15893 
15904 {
15905  uint32_t sel : 2;
15906  uint32_t : 30;
15907 };
15908 
15911 #endif /* __ASSEMBLY__ */
15912 
15914 #define ALT_SYSMGR_PINMUX_MIXED1IO17_OFST 0x144
15915 
15951 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_LSB 0
15952 
15953 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_MSB 1
15954 
15955 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_WIDTH 2
15956 
15957 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET_MSK 0x00000003
15958 
15959 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_CLR_MSK 0xfffffffc
15960 
15961 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_RESET 0x0
15962 
15963 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_GET(value) (((value) & 0x00000003) >> 0)
15964 
15965 #define ALT_SYSMGR_PINMUX_MIXED1IO18_SEL_SET(value) (((value) << 0) & 0x00000003)
15966 
15967 #ifndef __ASSEMBLY__
15968 
15979 {
15980  uint32_t sel : 2;
15981  uint32_t : 30;
15982 };
15983 
15986 #endif /* __ASSEMBLY__ */
15987 
15989 #define ALT_SYSMGR_PINMUX_MIXED1IO18_OFST 0x148
15990 
16026 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_LSB 0
16027 
16028 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_MSB 1
16029 
16030 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_WIDTH 2
16031 
16032 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET_MSK 0x00000003
16033 
16034 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_CLR_MSK 0xfffffffc
16035 
16036 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_RESET 0x0
16037 
16038 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_GET(value) (((value) & 0x00000003) >> 0)
16039 
16040 #define ALT_SYSMGR_PINMUX_MIXED1IO19_SEL_SET(value) (((value) << 0) & 0x00000003)
16041 
16042 #ifndef __ASSEMBLY__
16043 
16054 {
16055  uint32_t sel : 2;
16056  uint32_t : 30;
16057 };
16058 
16061 #endif /* __ASSEMBLY__ */
16062 
16064 #define ALT_SYSMGR_PINMUX_MIXED1IO19_OFST 0x14c
16065 
16101 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_LSB 0
16102 
16103 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_MSB 1
16104 
16105 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_WIDTH 2
16106 
16107 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET_MSK 0x00000003
16108 
16109 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_CLR_MSK 0xfffffffc
16110 
16111 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_RESET 0x0
16112 
16113 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_GET(value) (((value) & 0x00000003) >> 0)
16114 
16115 #define ALT_SYSMGR_PINMUX_MIXED1IO20_SEL_SET(value) (((value) << 0) & 0x00000003)
16116 
16117 #ifndef __ASSEMBLY__
16118 
16129 {
16130  uint32_t sel : 2;
16131  uint32_t : 30;
16132 };
16133 
16136 #endif /* __ASSEMBLY__ */
16137 
16139 #define ALT_SYSMGR_PINMUX_MIXED1IO20_OFST 0x150
16140 
16176 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_LSB 0
16177 
16178 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_MSB 1
16179 
16180 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_WIDTH 2
16181 
16182 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET_MSK 0x00000003
16183 
16184 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_CLR_MSK 0xfffffffc
16185 
16186 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_RESET 0x0
16187 
16188 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_GET(value) (((value) & 0x00000003) >> 0)
16189 
16190 #define ALT_SYSMGR_PINMUX_MIXED1IO21_SEL_SET(value) (((value) << 0) & 0x00000003)
16191 
16192 #ifndef __ASSEMBLY__
16193 
16204 {
16205  uint32_t sel : 2;
16206  uint32_t : 30;
16207 };
16208 
16211 #endif /* __ASSEMBLY__ */
16212 
16214 #define ALT_SYSMGR_PINMUX_MIXED1IO21_OFST 0x154
16215 
16251 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_LSB 0
16252 
16253 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_MSB 1
16254 
16255 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_WIDTH 2
16256 
16257 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET_MSK 0x00000003
16258 
16259 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_CLR_MSK 0xfffffffc
16260 
16261 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_RESET 0x0
16262 
16263 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_GET(value) (((value) & 0x00000003) >> 0)
16264 
16265 #define ALT_SYSMGR_PINMUX_MIXED2IO0_SEL_SET(value) (((value) << 0) & 0x00000003)
16266 
16267 #ifndef __ASSEMBLY__
16268 
16279 {
16280  uint32_t sel : 2;
16281  uint32_t : 30;
16282 };
16283 
16286 #endif /* __ASSEMBLY__ */
16287 
16289 #define ALT_SYSMGR_PINMUX_MIXED2IO0_OFST 0x158
16290 
16326 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_LSB 0
16327 
16328 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_MSB 1
16329 
16330 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_WIDTH 2
16331 
16332 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET_MSK 0x00000003
16333 
16334 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_CLR_MSK 0xfffffffc
16335 
16336 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_RESET 0x0
16337 
16338 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_GET(value) (((value) & 0x00000003) >> 0)
16339 
16340 #define ALT_SYSMGR_PINMUX_MIXED2IO1_SEL_SET(value) (((value) << 0) & 0x00000003)
16341 
16342 #ifndef __ASSEMBLY__
16343 
16354 {
16355  uint32_t sel : 2;
16356  uint32_t : 30;
16357 };
16358 
16361 #endif /* __ASSEMBLY__ */
16362 
16364 #define ALT_SYSMGR_PINMUX_MIXED2IO1_OFST 0x15c
16365 
16401 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_LSB 0
16402 
16403 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_MSB 1
16404 
16405 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_WIDTH 2
16406 
16407 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET_MSK 0x00000003
16408 
16409 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_CLR_MSK 0xfffffffc
16410 
16411 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_RESET 0x0
16412 
16413 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_GET(value) (((value) & 0x00000003) >> 0)
16414 
16415 #define ALT_SYSMGR_PINMUX_MIXED2IO2_SEL_SET(value) (((value) << 0) & 0x00000003)
16416 
16417 #ifndef __ASSEMBLY__
16418 
16429 {
16430  uint32_t sel : 2;
16431  uint32_t : 30;
16432 };
16433 
16436 #endif /* __ASSEMBLY__ */
16437 
16439 #define ALT_SYSMGR_PINMUX_MIXED2IO2_OFST 0x160
16440 
16476 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_LSB 0
16477 
16478 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_MSB 1
16479 
16480 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_WIDTH 2
16481 
16482 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET_MSK 0x00000003
16483 
16484 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_CLR_MSK 0xfffffffc
16485 
16486 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_RESET 0x0
16487 
16488 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_GET(value) (((value) & 0x00000003) >> 0)
16489 
16490 #define ALT_SYSMGR_PINMUX_MIXED2IO3_SEL_SET(value) (((value) << 0) & 0x00000003)
16491 
16492 #ifndef __ASSEMBLY__
16493 
16504 {
16505  uint32_t sel : 2;
16506  uint32_t : 30;
16507 };
16508 
16511 #endif /* __ASSEMBLY__ */
16512 
16514 #define ALT_SYSMGR_PINMUX_MIXED2IO3_OFST 0x164
16515 
16551 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_LSB 0
16552 
16553 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_MSB 1
16554 
16555 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_WIDTH 2
16556 
16557 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET_MSK 0x00000003
16558 
16559 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_CLR_MSK 0xfffffffc
16560 
16561 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_RESET 0x0
16562 
16563 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_GET(value) (((value) & 0x00000003) >> 0)
16564 
16565 #define ALT_SYSMGR_PINMUX_MIXED2IO4_SEL_SET(value) (((value) << 0) & 0x00000003)
16566 
16567 #ifndef __ASSEMBLY__
16568 
16579 {
16580  uint32_t sel : 2;
16581  uint32_t : 30;
16582 };
16583 
16586 #endif /* __ASSEMBLY__ */
16587 
16589 #define ALT_SYSMGR_PINMUX_MIXED2IO4_OFST 0x168
16590 
16626 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_LSB 0
16627 
16628 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_MSB 1
16629 
16630 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_WIDTH 2
16631 
16632 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET_MSK 0x00000003
16633 
16634 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_CLR_MSK 0xfffffffc
16635 
16636 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_RESET 0x0
16637 
16638 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_GET(value) (((value) & 0x00000003) >> 0)
16639 
16640 #define ALT_SYSMGR_PINMUX_MIXED2IO5_SEL_SET(value) (((value) << 0) & 0x00000003)
16641 
16642 #ifndef __ASSEMBLY__
16643 
16654 {
16655  uint32_t sel : 2;
16656  uint32_t : 30;
16657 };
16658 
16661 #endif /* __ASSEMBLY__ */
16662 
16664 #define ALT_SYSMGR_PINMUX_MIXED2IO5_OFST 0x16c
16665 
16701 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_LSB 0
16702 
16703 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_MSB 1
16704 
16705 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_WIDTH 2
16706 
16707 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET_MSK 0x00000003
16708 
16709 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_CLR_MSK 0xfffffffc
16710 
16711 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_RESET 0x0
16712 
16713 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_GET(value) (((value) & 0x00000003) >> 0)
16714 
16715 #define ALT_SYSMGR_PINMUX_MIXED2IO6_SEL_SET(value) (((value) << 0) & 0x00000003)
16716 
16717 #ifndef __ASSEMBLY__
16718 
16729 {
16730  uint32_t sel : 2;
16731  uint32_t : 30;
16732 };
16733 
16736 #endif /* __ASSEMBLY__ */
16737 
16739 #define ALT_SYSMGR_PINMUX_MIXED2IO6_OFST 0x170
16740 
16776 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_LSB 0
16777 
16778 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_MSB 1
16779 
16780 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_WIDTH 2
16781 
16782 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET_MSK 0x00000003
16783 
16784 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_CLR_MSK 0xfffffffc
16785 
16786 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_RESET 0x0
16787 
16788 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_GET(value) (((value) & 0x00000003) >> 0)
16789 
16790 #define ALT_SYSMGR_PINMUX_MIXED2IO7_SEL_SET(value) (((value) << 0) & 0x00000003)
16791 
16792 #ifndef __ASSEMBLY__
16793 
16804 {
16805  uint32_t sel : 2;
16806  uint32_t : 30;
16807 };
16808 
16811 #endif /* __ASSEMBLY__ */
16812 
16814 #define ALT_SYSMGR_PINMUX_MIXED2IO7_OFST 0x174
16815 
16848 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_LSB 0
16849 
16850 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_MSB 0
16851 
16852 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_WIDTH 1
16853 
16854 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET_MSK 0x00000001
16855 
16856 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_CLR_MSK 0xfffffffe
16857 
16858 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_RESET 0x0
16859 
16860 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
16861 
16862 #define ALT_SYSMGR_PINMUX_GPLINMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
16863 
16864 #ifndef __ASSEMBLY__
16865 
16876 {
16877  uint32_t sel : 1;
16878  uint32_t : 31;
16879 };
16880 
16883 #endif /* __ASSEMBLY__ */
16884 
16886 #define ALT_SYSMGR_PINMUX_GPLINMUX48_OFST 0x178
16887 
16920 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_LSB 0
16921 
16922 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_MSB 0
16923 
16924 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_WIDTH 1
16925 
16926 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET_MSK 0x00000001
16927 
16928 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_CLR_MSK 0xfffffffe
16929 
16930 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_RESET 0x0
16931 
16932 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
16933 
16934 #define ALT_SYSMGR_PINMUX_GPLINMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
16935 
16936 #ifndef __ASSEMBLY__
16937 
16948 {
16949  uint32_t sel : 1;
16950  uint32_t : 31;
16951 };
16952 
16955 #endif /* __ASSEMBLY__ */
16956 
16958 #define ALT_SYSMGR_PINMUX_GPLINMUX49_OFST 0x17c
16959 
16992 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_LSB 0
16993 
16994 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_MSB 0
16995 
16996 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_WIDTH 1
16997 
16998 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET_MSK 0x00000001
16999 
17000 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_CLR_MSK 0xfffffffe
17001 
17002 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_RESET 0x0
17003 
17004 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
17005 
17006 #define ALT_SYSMGR_PINMUX_GPLINMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
17007 
17008 #ifndef __ASSEMBLY__
17009 
17020 {
17021  uint32_t sel : 1;
17022  uint32_t : 31;
17023 };
17024 
17027 #endif /* __ASSEMBLY__ */
17028 
17030 #define ALT_SYSMGR_PINMUX_GPLINMUX50_OFST 0x180
17031 
17064 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_LSB 0
17065 
17066 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_MSB 0
17067 
17068 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_WIDTH 1
17069 
17070 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET_MSK 0x00000001
17071 
17072 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_CLR_MSK 0xfffffffe
17073 
17074 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_RESET 0x0
17075 
17076 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
17077 
17078 #define ALT_SYSMGR_PINMUX_GPLINMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
17079 
17080 #ifndef __ASSEMBLY__
17081 
17092 {
17093  uint32_t sel : 1;
17094  uint32_t : 31;
17095 };
17096 
17099 #endif /* __ASSEMBLY__ */
17100 
17102 #define ALT_SYSMGR_PINMUX_GPLINMUX51_OFST 0x184
17103 
17136 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_LSB 0
17137 
17138 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_MSB 0
17139 
17140 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_WIDTH 1
17141 
17142 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET_MSK 0x00000001
17143 
17144 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_CLR_MSK 0xfffffffe
17145 
17146 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_RESET 0x0
17147 
17148 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
17149 
17150 #define ALT_SYSMGR_PINMUX_GPLINMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
17151 
17152 #ifndef __ASSEMBLY__
17153 
17164 {
17165  uint32_t sel : 1;
17166  uint32_t : 31;
17167 };
17168 
17171 #endif /* __ASSEMBLY__ */
17172 
17174 #define ALT_SYSMGR_PINMUX_GPLINMUX52_OFST 0x188
17175 
17208 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_LSB 0
17209 
17210 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_MSB 0
17211 
17212 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_WIDTH 1
17213 
17214 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET_MSK 0x00000001
17215 
17216 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_CLR_MSK 0xfffffffe
17217 
17218 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_RESET 0x0
17219 
17220 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
17221 
17222 #define ALT_SYSMGR_PINMUX_GPLINMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
17223 
17224 #ifndef __ASSEMBLY__
17225 
17236 {
17237  uint32_t sel : 1;
17238  uint32_t : 31;
17239 };
17240 
17243 #endif /* __ASSEMBLY__ */
17244 
17246 #define ALT_SYSMGR_PINMUX_GPLINMUX53_OFST 0x18c
17247 
17280 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_LSB 0
17281 
17282 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_MSB 0
17283 
17284 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_WIDTH 1
17285 
17286 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET_MSK 0x00000001
17287 
17288 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_CLR_MSK 0xfffffffe
17289 
17290 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_RESET 0x0
17291 
17292 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
17293 
17294 #define ALT_SYSMGR_PINMUX_GPLINMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
17295 
17296 #ifndef __ASSEMBLY__
17297 
17308 {
17309  uint32_t sel : 1;
17310  uint32_t : 31;
17311 };
17312 
17315 #endif /* __ASSEMBLY__ */
17316 
17318 #define ALT_SYSMGR_PINMUX_GPLINMUX54_OFST 0x190
17319 
17352 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_LSB 0
17353 
17354 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_MSB 0
17355 
17356 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_WIDTH 1
17357 
17358 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET_MSK 0x00000001
17359 
17360 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_CLR_MSK 0xfffffffe
17361 
17362 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_RESET 0x0
17363 
17364 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
17365 
17366 #define ALT_SYSMGR_PINMUX_GPLINMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
17367 
17368 #ifndef __ASSEMBLY__
17369 
17380 {
17381  uint32_t sel : 1;
17382  uint32_t : 31;
17383 };
17384 
17387 #endif /* __ASSEMBLY__ */
17388 
17390 #define ALT_SYSMGR_PINMUX_GPLINMUX55_OFST 0x194
17391 
17424 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_LSB 0
17425 
17426 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_MSB 0
17427 
17428 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_WIDTH 1
17429 
17430 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET_MSK 0x00000001
17431 
17432 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_CLR_MSK 0xfffffffe
17433 
17434 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_RESET 0x0
17435 
17436 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
17437 
17438 #define ALT_SYSMGR_PINMUX_GPLINMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
17439 
17440 #ifndef __ASSEMBLY__
17441 
17452 {
17453  uint32_t sel : 1;
17454  uint32_t : 31;
17455 };
17456 
17459 #endif /* __ASSEMBLY__ */
17460 
17462 #define ALT_SYSMGR_PINMUX_GPLINMUX56_OFST 0x198
17463 
17496 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_LSB 0
17497 
17498 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_MSB 0
17499 
17500 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_WIDTH 1
17501 
17502 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET_MSK 0x00000001
17503 
17504 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_CLR_MSK 0xfffffffe
17505 
17506 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_RESET 0x0
17507 
17508 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
17509 
17510 #define ALT_SYSMGR_PINMUX_GPLINMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
17511 
17512 #ifndef __ASSEMBLY__
17513 
17524 {
17525  uint32_t sel : 1;
17526  uint32_t : 31;
17527 };
17528 
17531 #endif /* __ASSEMBLY__ */
17532 
17534 #define ALT_SYSMGR_PINMUX_GPLINMUX57_OFST 0x19c
17535 
17568 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_LSB 0
17569 
17570 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_MSB 0
17571 
17572 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_WIDTH 1
17573 
17574 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET_MSK 0x00000001
17575 
17576 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_CLR_MSK 0xfffffffe
17577 
17578 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_RESET 0x0
17579 
17580 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
17581 
17582 #define ALT_SYSMGR_PINMUX_GPLINMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
17583 
17584 #ifndef __ASSEMBLY__
17585 
17596 {
17597  uint32_t sel : 1;
17598  uint32_t : 31;
17599 };
17600 
17603 #endif /* __ASSEMBLY__ */
17604 
17606 #define ALT_SYSMGR_PINMUX_GPLINMUX58_OFST 0x1a0
17607 
17640 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_LSB 0
17641 
17642 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_MSB 0
17643 
17644 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_WIDTH 1
17645 
17646 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET_MSK 0x00000001
17647 
17648 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_CLR_MSK 0xfffffffe
17649 
17650 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_RESET 0x0
17651 
17652 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
17653 
17654 #define ALT_SYSMGR_PINMUX_GPLINMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
17655 
17656 #ifndef __ASSEMBLY__
17657 
17668 {
17669  uint32_t sel : 1;
17670  uint32_t : 31;
17671 };
17672 
17675 #endif /* __ASSEMBLY__ */
17676 
17678 #define ALT_SYSMGR_PINMUX_GPLINMUX59_OFST 0x1a4
17679 
17712 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_LSB 0
17713 
17714 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_MSB 0
17715 
17716 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_WIDTH 1
17717 
17718 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET_MSK 0x00000001
17719 
17720 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_CLR_MSK 0xfffffffe
17721 
17722 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_RESET 0x0
17723 
17724 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
17725 
17726 #define ALT_SYSMGR_PINMUX_GPLINMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
17727 
17728 #ifndef __ASSEMBLY__
17729 
17740 {
17741  uint32_t sel : 1;
17742  uint32_t : 31;
17743 };
17744 
17747 #endif /* __ASSEMBLY__ */
17748 
17750 #define ALT_SYSMGR_PINMUX_GPLINMUX60_OFST 0x1a8
17751 
17784 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_LSB 0
17785 
17786 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_MSB 0
17787 
17788 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_WIDTH 1
17789 
17790 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET_MSK 0x00000001
17791 
17792 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_CLR_MSK 0xfffffffe
17793 
17794 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_RESET 0x0
17795 
17796 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
17797 
17798 #define ALT_SYSMGR_PINMUX_GPLINMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
17799 
17800 #ifndef __ASSEMBLY__
17801 
17812 {
17813  uint32_t sel : 1;
17814  uint32_t : 31;
17815 };
17816 
17819 #endif /* __ASSEMBLY__ */
17820 
17822 #define ALT_SYSMGR_PINMUX_GPLINMUX61_OFST 0x1ac
17823 
17856 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_LSB 0
17857 
17858 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_MSB 0
17859 
17860 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_WIDTH 1
17861 
17862 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET_MSK 0x00000001
17863 
17864 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_CLR_MSK 0xfffffffe
17865 
17866 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_RESET 0x0
17867 
17868 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
17869 
17870 #define ALT_SYSMGR_PINMUX_GPLINMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
17871 
17872 #ifndef __ASSEMBLY__
17873 
17884 {
17885  uint32_t sel : 1;
17886  uint32_t : 31;
17887 };
17888 
17891 #endif /* __ASSEMBLY__ */
17892 
17894 #define ALT_SYSMGR_PINMUX_GPLINMUX62_OFST 0x1b0
17895 
17928 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_LSB 0
17929 
17930 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_MSB 0
17931 
17932 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_WIDTH 1
17933 
17934 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET_MSK 0x00000001
17935 
17936 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_CLR_MSK 0xfffffffe
17937 
17938 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_RESET 0x0
17939 
17940 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
17941 
17942 #define ALT_SYSMGR_PINMUX_GPLINMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
17943 
17944 #ifndef __ASSEMBLY__
17945 
17956 {
17957  uint32_t sel : 1;
17958  uint32_t : 31;
17959 };
17960 
17963 #endif /* __ASSEMBLY__ */
17964 
17966 #define ALT_SYSMGR_PINMUX_GPLINMUX63_OFST 0x1b4
17967 
18000 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_LSB 0
18001 
18002 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_MSB 0
18003 
18004 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_WIDTH 1
18005 
18006 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET_MSK 0x00000001
18007 
18008 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_CLR_MSK 0xfffffffe
18009 
18010 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_RESET 0x0
18011 
18012 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
18013 
18014 #define ALT_SYSMGR_PINMUX_GPLINMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
18015 
18016 #ifndef __ASSEMBLY__
18017 
18028 {
18029  uint32_t sel : 1;
18030  uint32_t : 31;
18031 };
18032 
18035 #endif /* __ASSEMBLY__ */
18036 
18038 #define ALT_SYSMGR_PINMUX_GPLINMUX64_OFST 0x1b8
18039 
18072 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_LSB 0
18073 
18074 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_MSB 0
18075 
18076 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_WIDTH 1
18077 
18078 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET_MSK 0x00000001
18079 
18080 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_CLR_MSK 0xfffffffe
18081 
18082 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_RESET 0x0
18083 
18084 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
18085 
18086 #define ALT_SYSMGR_PINMUX_GPLINMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
18087 
18088 #ifndef __ASSEMBLY__
18089 
18100 {
18101  uint32_t sel : 1;
18102  uint32_t : 31;
18103 };
18104 
18107 #endif /* __ASSEMBLY__ */
18108 
18110 #define ALT_SYSMGR_PINMUX_GPLINMUX65_OFST 0x1bc
18111 
18144 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_LSB 0
18145 
18146 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_MSB 0
18147 
18148 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_WIDTH 1
18149 
18150 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET_MSK 0x00000001
18151 
18152 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_CLR_MSK 0xfffffffe
18153 
18154 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_RESET 0x0
18155 
18156 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
18157 
18158 #define ALT_SYSMGR_PINMUX_GPLINMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
18159 
18160 #ifndef __ASSEMBLY__
18161 
18172 {
18173  uint32_t sel : 1;
18174  uint32_t : 31;
18175 };
18176 
18179 #endif /* __ASSEMBLY__ */
18180 
18182 #define ALT_SYSMGR_PINMUX_GPLINMUX66_OFST 0x1c0
18183 
18216 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_LSB 0
18217 
18218 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_MSB 0
18219 
18220 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_WIDTH 1
18221 
18222 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET_MSK 0x00000001
18223 
18224 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_CLR_MSK 0xfffffffe
18225 
18226 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_RESET 0x0
18227 
18228 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
18229 
18230 #define ALT_SYSMGR_PINMUX_GPLINMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
18231 
18232 #ifndef __ASSEMBLY__
18233 
18244 {
18245  uint32_t sel : 1;
18246  uint32_t : 31;
18247 };
18248 
18251 #endif /* __ASSEMBLY__ */
18252 
18254 #define ALT_SYSMGR_PINMUX_GPLINMUX67_OFST 0x1c4
18255 
18288 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_LSB 0
18289 
18290 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_MSB 0
18291 
18292 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_WIDTH 1
18293 
18294 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET_MSK 0x00000001
18295 
18296 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_CLR_MSK 0xfffffffe
18297 
18298 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_RESET 0x0
18299 
18300 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
18301 
18302 #define ALT_SYSMGR_PINMUX_GPLINMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
18303 
18304 #ifndef __ASSEMBLY__
18305 
18316 {
18317  uint32_t sel : 1;
18318  uint32_t : 31;
18319 };
18320 
18323 #endif /* __ASSEMBLY__ */
18324 
18326 #define ALT_SYSMGR_PINMUX_GPLINMUX68_OFST 0x1c8
18327 
18360 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_LSB 0
18361 
18362 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_MSB 0
18363 
18364 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_WIDTH 1
18365 
18366 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET_MSK 0x00000001
18367 
18368 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_CLR_MSK 0xfffffffe
18369 
18370 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_RESET 0x0
18371 
18372 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
18373 
18374 #define ALT_SYSMGR_PINMUX_GPLINMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
18375 
18376 #ifndef __ASSEMBLY__
18377 
18388 {
18389  uint32_t sel : 1;
18390  uint32_t : 31;
18391 };
18392 
18395 #endif /* __ASSEMBLY__ */
18396 
18398 #define ALT_SYSMGR_PINMUX_GPLINMUX69_OFST 0x1cc
18399 
18432 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_LSB 0
18433 
18434 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_MSB 0
18435 
18436 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_WIDTH 1
18437 
18438 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET_MSK 0x00000001
18439 
18440 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_CLR_MSK 0xfffffffe
18441 
18442 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_RESET 0x0
18443 
18444 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
18445 
18446 #define ALT_SYSMGR_PINMUX_GPLINMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
18447 
18448 #ifndef __ASSEMBLY__
18449 
18460 {
18461  uint32_t sel : 1;
18462  uint32_t : 31;
18463 };
18464 
18467 #endif /* __ASSEMBLY__ */
18468 
18470 #define ALT_SYSMGR_PINMUX_GPLINMUX70_OFST 0x1d0
18471 
18505 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_LSB 0
18506 
18507 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_MSB 0
18508 
18509 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_WIDTH 1
18510 
18511 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET_MSK 0x00000001
18512 
18513 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_CLR_MSK 0xfffffffe
18514 
18515 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_RESET 0x0
18516 
18517 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_GET(value) (((value) & 0x00000001) >> 0)
18518 
18519 #define ALT_SYSMGR_PINMUX_GPLMUX0_SEL_SET(value) (((value) << 0) & 0x00000001)
18520 
18521 #ifndef __ASSEMBLY__
18522 
18533 {
18534  uint32_t sel : 1;
18535  uint32_t : 31;
18536 };
18537 
18540 #endif /* __ASSEMBLY__ */
18541 
18543 #define ALT_SYSMGR_PINMUX_GPLMUX0_OFST 0x1d4
18544 
18578 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_LSB 0
18579 
18580 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_MSB 0
18581 
18582 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_WIDTH 1
18583 
18584 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET_MSK 0x00000001
18585 
18586 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_CLR_MSK 0xfffffffe
18587 
18588 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_RESET 0x0
18589 
18590 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_GET(value) (((value) & 0x00000001) >> 0)
18591 
18592 #define ALT_SYSMGR_PINMUX_GPLMUX1_SEL_SET(value) (((value) << 0) & 0x00000001)
18593 
18594 #ifndef __ASSEMBLY__
18595 
18606 {
18607  uint32_t sel : 1;
18608  uint32_t : 31;
18609 };
18610 
18613 #endif /* __ASSEMBLY__ */
18614 
18616 #define ALT_SYSMGR_PINMUX_GPLMUX1_OFST 0x1d8
18617 
18651 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_LSB 0
18652 
18653 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_MSB 0
18654 
18655 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_WIDTH 1
18656 
18657 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET_MSK 0x00000001
18658 
18659 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_CLR_MSK 0xfffffffe
18660 
18661 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_RESET 0x0
18662 
18663 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_GET(value) (((value) & 0x00000001) >> 0)
18664 
18665 #define ALT_SYSMGR_PINMUX_GPLMUX2_SEL_SET(value) (((value) << 0) & 0x00000001)
18666 
18667 #ifndef __ASSEMBLY__
18668 
18679 {
18680  uint32_t sel : 1;
18681  uint32_t : 31;
18682 };
18683 
18686 #endif /* __ASSEMBLY__ */
18687 
18689 #define ALT_SYSMGR_PINMUX_GPLMUX2_OFST 0x1dc
18690 
18724 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_LSB 0
18725 
18726 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_MSB 0
18727 
18728 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_WIDTH 1
18729 
18730 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET_MSK 0x00000001
18731 
18732 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_CLR_MSK 0xfffffffe
18733 
18734 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_RESET 0x0
18735 
18736 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_GET(value) (((value) & 0x00000001) >> 0)
18737 
18738 #define ALT_SYSMGR_PINMUX_GPLMUX3_SEL_SET(value) (((value) << 0) & 0x00000001)
18739 
18740 #ifndef __ASSEMBLY__
18741 
18752 {
18753  uint32_t sel : 1;
18754  uint32_t : 31;
18755 };
18756 
18759 #endif /* __ASSEMBLY__ */
18760 
18762 #define ALT_SYSMGR_PINMUX_GPLMUX3_OFST 0x1e0
18763 
18797 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_LSB 0
18798 
18799 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_MSB 0
18800 
18801 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_WIDTH 1
18802 
18803 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET_MSK 0x00000001
18804 
18805 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_CLR_MSK 0xfffffffe
18806 
18807 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_RESET 0x0
18808 
18809 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_GET(value) (((value) & 0x00000001) >> 0)
18810 
18811 #define ALT_SYSMGR_PINMUX_GPLMUX4_SEL_SET(value) (((value) << 0) & 0x00000001)
18812 
18813 #ifndef __ASSEMBLY__
18814 
18825 {
18826  uint32_t sel : 1;
18827  uint32_t : 31;
18828 };
18829 
18832 #endif /* __ASSEMBLY__ */
18833 
18835 #define ALT_SYSMGR_PINMUX_GPLMUX4_OFST 0x1e4
18836 
18870 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_LSB 0
18871 
18872 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_MSB 0
18873 
18874 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_WIDTH 1
18875 
18876 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET_MSK 0x00000001
18877 
18878 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_CLR_MSK 0xfffffffe
18879 
18880 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_RESET 0x0
18881 
18882 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_GET(value) (((value) & 0x00000001) >> 0)
18883 
18884 #define ALT_SYSMGR_PINMUX_GPLMUX5_SEL_SET(value) (((value) << 0) & 0x00000001)
18885 
18886 #ifndef __ASSEMBLY__
18887 
18898 {
18899  uint32_t sel : 1;
18900  uint32_t : 31;
18901 };
18902 
18905 #endif /* __ASSEMBLY__ */
18906 
18908 #define ALT_SYSMGR_PINMUX_GPLMUX5_OFST 0x1e8
18909 
18943 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_LSB 0
18944 
18945 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_MSB 0
18946 
18947 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_WIDTH 1
18948 
18949 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET_MSK 0x00000001
18950 
18951 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_CLR_MSK 0xfffffffe
18952 
18953 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_RESET 0x0
18954 
18955 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_GET(value) (((value) & 0x00000001) >> 0)
18956 
18957 #define ALT_SYSMGR_PINMUX_GPLMUX6_SEL_SET(value) (((value) << 0) & 0x00000001)
18958 
18959 #ifndef __ASSEMBLY__
18960 
18971 {
18972  uint32_t sel : 1;
18973  uint32_t : 31;
18974 };
18975 
18978 #endif /* __ASSEMBLY__ */
18979 
18981 #define ALT_SYSMGR_PINMUX_GPLMUX6_OFST 0x1ec
18982 
19016 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_LSB 0
19017 
19018 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_MSB 0
19019 
19020 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_WIDTH 1
19021 
19022 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET_MSK 0x00000001
19023 
19024 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_CLR_MSK 0xfffffffe
19025 
19026 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_RESET 0x0
19027 
19028 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_GET(value) (((value) & 0x00000001) >> 0)
19029 
19030 #define ALT_SYSMGR_PINMUX_GPLMUX7_SEL_SET(value) (((value) << 0) & 0x00000001)
19031 
19032 #ifndef __ASSEMBLY__
19033 
19044 {
19045  uint32_t sel : 1;
19046  uint32_t : 31;
19047 };
19048 
19051 #endif /* __ASSEMBLY__ */
19052 
19054 #define ALT_SYSMGR_PINMUX_GPLMUX7_OFST 0x1f0
19055 
19089 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_LSB 0
19090 
19091 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_MSB 0
19092 
19093 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_WIDTH 1
19094 
19095 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET_MSK 0x00000001
19096 
19097 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_CLR_MSK 0xfffffffe
19098 
19099 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_RESET 0x0
19100 
19101 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_GET(value) (((value) & 0x00000001) >> 0)
19102 
19103 #define ALT_SYSMGR_PINMUX_GPLMUX8_SEL_SET(value) (((value) << 0) & 0x00000001)
19104 
19105 #ifndef __ASSEMBLY__
19106 
19117 {
19118  uint32_t sel : 1;
19119  uint32_t : 31;
19120 };
19121 
19124 #endif /* __ASSEMBLY__ */
19125 
19127 #define ALT_SYSMGR_PINMUX_GPLMUX8_OFST 0x1f4
19128 
19162 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_LSB 0
19163 
19164 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_MSB 0
19165 
19166 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_WIDTH 1
19167 
19168 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET_MSK 0x00000001
19169 
19170 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_CLR_MSK 0xfffffffe
19171 
19172 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_RESET 0x0
19173 
19174 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_GET(value) (((value) & 0x00000001) >> 0)
19175 
19176 #define ALT_SYSMGR_PINMUX_GPLMUX9_SEL_SET(value) (((value) << 0) & 0x00000001)
19177 
19178 #ifndef __ASSEMBLY__
19179 
19190 {
19191  uint32_t sel : 1;
19192  uint32_t : 31;
19193 };
19194 
19197 #endif /* __ASSEMBLY__ */
19198 
19200 #define ALT_SYSMGR_PINMUX_GPLMUX9_OFST 0x1f8
19201 
19235 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_LSB 0
19236 
19237 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_MSB 0
19238 
19239 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_WIDTH 1
19240 
19241 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET_MSK 0x00000001
19242 
19243 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_CLR_MSK 0xfffffffe
19244 
19245 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_RESET 0x0
19246 
19247 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_GET(value) (((value) & 0x00000001) >> 0)
19248 
19249 #define ALT_SYSMGR_PINMUX_GPLMUX10_SEL_SET(value) (((value) << 0) & 0x00000001)
19250 
19251 #ifndef __ASSEMBLY__
19252 
19263 {
19264  uint32_t sel : 1;
19265  uint32_t : 31;
19266 };
19267 
19270 #endif /* __ASSEMBLY__ */
19271 
19273 #define ALT_SYSMGR_PINMUX_GPLMUX10_OFST 0x1fc
19274 
19308 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_LSB 0
19309 
19310 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_MSB 0
19311 
19312 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_WIDTH 1
19313 
19314 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET_MSK 0x00000001
19315 
19316 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_CLR_MSK 0xfffffffe
19317 
19318 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_RESET 0x0
19319 
19320 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_GET(value) (((value) & 0x00000001) >> 0)
19321 
19322 #define ALT_SYSMGR_PINMUX_GPLMUX11_SEL_SET(value) (((value) << 0) & 0x00000001)
19323 
19324 #ifndef __ASSEMBLY__
19325 
19336 {
19337  uint32_t sel : 1;
19338  uint32_t : 31;
19339 };
19340 
19343 #endif /* __ASSEMBLY__ */
19344 
19346 #define ALT_SYSMGR_PINMUX_GPLMUX11_OFST 0x200
19347 
19381 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_LSB 0
19382 
19383 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_MSB 0
19384 
19385 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_WIDTH 1
19386 
19387 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET_MSK 0x00000001
19388 
19389 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_CLR_MSK 0xfffffffe
19390 
19391 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_RESET 0x0
19392 
19393 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_GET(value) (((value) & 0x00000001) >> 0)
19394 
19395 #define ALT_SYSMGR_PINMUX_GPLMUX12_SEL_SET(value) (((value) << 0) & 0x00000001)
19396 
19397 #ifndef __ASSEMBLY__
19398 
19409 {
19410  uint32_t sel : 1;
19411  uint32_t : 31;
19412 };
19413 
19416 #endif /* __ASSEMBLY__ */
19417 
19419 #define ALT_SYSMGR_PINMUX_GPLMUX12_OFST 0x204
19420 
19454 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_LSB 0
19455 
19456 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_MSB 0
19457 
19458 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_WIDTH 1
19459 
19460 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET_MSK 0x00000001
19461 
19462 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_CLR_MSK 0xfffffffe
19463 
19464 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_RESET 0x0
19465 
19466 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_GET(value) (((value) & 0x00000001) >> 0)
19467 
19468 #define ALT_SYSMGR_PINMUX_GPLMUX13_SEL_SET(value) (((value) << 0) & 0x00000001)
19469 
19470 #ifndef __ASSEMBLY__
19471 
19482 {
19483  uint32_t sel : 1;
19484  uint32_t : 31;
19485 };
19486 
19489 #endif /* __ASSEMBLY__ */
19490 
19492 #define ALT_SYSMGR_PINMUX_GPLMUX13_OFST 0x208
19493 
19527 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_LSB 0
19528 
19529 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_MSB 0
19530 
19531 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_WIDTH 1
19532 
19533 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET_MSK 0x00000001
19534 
19535 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_CLR_MSK 0xfffffffe
19536 
19537 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_RESET 0x0
19538 
19539 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_GET(value) (((value) & 0x00000001) >> 0)
19540 
19541 #define ALT_SYSMGR_PINMUX_GPLMUX14_SEL_SET(value) (((value) << 0) & 0x00000001)
19542 
19543 #ifndef __ASSEMBLY__
19544 
19555 {
19556  uint32_t sel : 1;
19557  uint32_t : 31;
19558 };
19559 
19562 #endif /* __ASSEMBLY__ */
19563 
19565 #define ALT_SYSMGR_PINMUX_GPLMUX14_OFST 0x20c
19566 
19600 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_LSB 0
19601 
19602 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_MSB 0
19603 
19604 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_WIDTH 1
19605 
19606 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET_MSK 0x00000001
19607 
19608 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_CLR_MSK 0xfffffffe
19609 
19610 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_RESET 0x0
19611 
19612 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_GET(value) (((value) & 0x00000001) >> 0)
19613 
19614 #define ALT_SYSMGR_PINMUX_GPLMUX15_SEL_SET(value) (((value) << 0) & 0x00000001)
19615 
19616 #ifndef __ASSEMBLY__
19617 
19628 {
19629  uint32_t sel : 1;
19630  uint32_t : 31;
19631 };
19632 
19635 #endif /* __ASSEMBLY__ */
19636 
19638 #define ALT_SYSMGR_PINMUX_GPLMUX15_OFST 0x210
19639 
19673 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_LSB 0
19674 
19675 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_MSB 0
19676 
19677 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_WIDTH 1
19678 
19679 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET_MSK 0x00000001
19680 
19681 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_CLR_MSK 0xfffffffe
19682 
19683 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_RESET 0x0
19684 
19685 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_GET(value) (((value) & 0x00000001) >> 0)
19686 
19687 #define ALT_SYSMGR_PINMUX_GPLMUX16_SEL_SET(value) (((value) << 0) & 0x00000001)
19688 
19689 #ifndef __ASSEMBLY__
19690 
19701 {
19702  uint32_t sel : 1;
19703  uint32_t : 31;
19704 };
19705 
19708 #endif /* __ASSEMBLY__ */
19709 
19711 #define ALT_SYSMGR_PINMUX_GPLMUX16_OFST 0x214
19712 
19746 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_LSB 0
19747 
19748 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_MSB 0
19749 
19750 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_WIDTH 1
19751 
19752 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET_MSK 0x00000001
19753 
19754 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_CLR_MSK 0xfffffffe
19755 
19756 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_RESET 0x0
19757 
19758 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_GET(value) (((value) & 0x00000001) >> 0)
19759 
19760 #define ALT_SYSMGR_PINMUX_GPLMUX17_SEL_SET(value) (((value) << 0) & 0x00000001)
19761 
19762 #ifndef __ASSEMBLY__
19763 
19774 {
19775  uint32_t sel : 1;
19776  uint32_t : 31;
19777 };
19778 
19781 #endif /* __ASSEMBLY__ */
19782 
19784 #define ALT_SYSMGR_PINMUX_GPLMUX17_OFST 0x218
19785 
19819 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_LSB 0
19820 
19821 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_MSB 0
19822 
19823 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_WIDTH 1
19824 
19825 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET_MSK 0x00000001
19826 
19827 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_CLR_MSK 0xfffffffe
19828 
19829 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_RESET 0x0
19830 
19831 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_GET(value) (((value) & 0x00000001) >> 0)
19832 
19833 #define ALT_SYSMGR_PINMUX_GPLMUX18_SEL_SET(value) (((value) << 0) & 0x00000001)
19834 
19835 #ifndef __ASSEMBLY__
19836 
19847 {
19848  uint32_t sel : 1;
19849  uint32_t : 31;
19850 };
19851 
19854 #endif /* __ASSEMBLY__ */
19855 
19857 #define ALT_SYSMGR_PINMUX_GPLMUX18_OFST 0x21c
19858 
19892 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_LSB 0
19893 
19894 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_MSB 0
19895 
19896 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_WIDTH 1
19897 
19898 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET_MSK 0x00000001
19899 
19900 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_CLR_MSK 0xfffffffe
19901 
19902 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_RESET 0x0
19903 
19904 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_GET(value) (((value) & 0x00000001) >> 0)
19905 
19906 #define ALT_SYSMGR_PINMUX_GPLMUX19_SEL_SET(value) (((value) << 0) & 0x00000001)
19907 
19908 #ifndef __ASSEMBLY__
19909 
19920 {
19921  uint32_t sel : 1;
19922  uint32_t : 31;
19923 };
19924 
19927 #endif /* __ASSEMBLY__ */
19928 
19930 #define ALT_SYSMGR_PINMUX_GPLMUX19_OFST 0x220
19931 
19965 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_LSB 0
19966 
19967 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_MSB 0
19968 
19969 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_WIDTH 1
19970 
19971 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET_MSK 0x00000001
19972 
19973 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_CLR_MSK 0xfffffffe
19974 
19975 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_RESET 0x0
19976 
19977 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_GET(value) (((value) & 0x00000001) >> 0)
19978 
19979 #define ALT_SYSMGR_PINMUX_GPLMUX20_SEL_SET(value) (((value) << 0) & 0x00000001)
19980 
19981 #ifndef __ASSEMBLY__
19982 
19993 {
19994  uint32_t sel : 1;
19995  uint32_t : 31;
19996 };
19997 
20000 #endif /* __ASSEMBLY__ */
20001 
20003 #define ALT_SYSMGR_PINMUX_GPLMUX20_OFST 0x224
20004 
20038 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_LSB 0
20039 
20040 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_MSB 0
20041 
20042 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_WIDTH 1
20043 
20044 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET_MSK 0x00000001
20045 
20046 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_CLR_MSK 0xfffffffe
20047 
20048 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_RESET 0x0
20049 
20050 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_GET(value) (((value) & 0x00000001) >> 0)
20051 
20052 #define ALT_SYSMGR_PINMUX_GPLMUX21_SEL_SET(value) (((value) << 0) & 0x00000001)
20053 
20054 #ifndef __ASSEMBLY__
20055 
20066 {
20067  uint32_t sel : 1;
20068  uint32_t : 31;
20069 };
20070 
20073 #endif /* __ASSEMBLY__ */
20074 
20076 #define ALT_SYSMGR_PINMUX_GPLMUX21_OFST 0x228
20077 
20111 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_LSB 0
20112 
20113 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_MSB 0
20114 
20115 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_WIDTH 1
20116 
20117 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET_MSK 0x00000001
20118 
20119 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_CLR_MSK 0xfffffffe
20120 
20121 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_RESET 0x0
20122 
20123 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_GET(value) (((value) & 0x00000001) >> 0)
20124 
20125 #define ALT_SYSMGR_PINMUX_GPLMUX22_SEL_SET(value) (((value) << 0) & 0x00000001)
20126 
20127 #ifndef __ASSEMBLY__
20128 
20139 {
20140  uint32_t sel : 1;
20141  uint32_t : 31;
20142 };
20143 
20146 #endif /* __ASSEMBLY__ */
20147 
20149 #define ALT_SYSMGR_PINMUX_GPLMUX22_OFST 0x22c
20150 
20184 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_LSB 0
20185 
20186 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_MSB 0
20187 
20188 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_WIDTH 1
20189 
20190 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET_MSK 0x00000001
20191 
20192 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_CLR_MSK 0xfffffffe
20193 
20194 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_RESET 0x0
20195 
20196 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_GET(value) (((value) & 0x00000001) >> 0)
20197 
20198 #define ALT_SYSMGR_PINMUX_GPLMUX23_SEL_SET(value) (((value) << 0) & 0x00000001)
20199 
20200 #ifndef __ASSEMBLY__
20201 
20212 {
20213  uint32_t sel : 1;
20214  uint32_t : 31;
20215 };
20216 
20219 #endif /* __ASSEMBLY__ */
20220 
20222 #define ALT_SYSMGR_PINMUX_GPLMUX23_OFST 0x230
20223 
20257 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_LSB 0
20258 
20259 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_MSB 0
20260 
20261 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_WIDTH 1
20262 
20263 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET_MSK 0x00000001
20264 
20265 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_CLR_MSK 0xfffffffe
20266 
20267 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_RESET 0x0
20268 
20269 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_GET(value) (((value) & 0x00000001) >> 0)
20270 
20271 #define ALT_SYSMGR_PINMUX_GPLMUX24_SEL_SET(value) (((value) << 0) & 0x00000001)
20272 
20273 #ifndef __ASSEMBLY__
20274 
20285 {
20286  uint32_t sel : 1;
20287  uint32_t : 31;
20288 };
20289 
20292 #endif /* __ASSEMBLY__ */
20293 
20295 #define ALT_SYSMGR_PINMUX_GPLMUX24_OFST 0x234
20296 
20330 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_LSB 0
20331 
20332 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_MSB 0
20333 
20334 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_WIDTH 1
20335 
20336 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET_MSK 0x00000001
20337 
20338 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_CLR_MSK 0xfffffffe
20339 
20340 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_RESET 0x0
20341 
20342 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_GET(value) (((value) & 0x00000001) >> 0)
20343 
20344 #define ALT_SYSMGR_PINMUX_GPLMUX25_SEL_SET(value) (((value) << 0) & 0x00000001)
20345 
20346 #ifndef __ASSEMBLY__
20347 
20358 {
20359  uint32_t sel : 1;
20360  uint32_t : 31;
20361 };
20362 
20365 #endif /* __ASSEMBLY__ */
20366 
20368 #define ALT_SYSMGR_PINMUX_GPLMUX25_OFST 0x238
20369 
20403 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_LSB 0
20404 
20405 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_MSB 0
20406 
20407 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_WIDTH 1
20408 
20409 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET_MSK 0x00000001
20410 
20411 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_CLR_MSK 0xfffffffe
20412 
20413 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_RESET 0x0
20414 
20415 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_GET(value) (((value) & 0x00000001) >> 0)
20416 
20417 #define ALT_SYSMGR_PINMUX_GPLMUX26_SEL_SET(value) (((value) << 0) & 0x00000001)
20418 
20419 #ifndef __ASSEMBLY__
20420 
20431 {
20432  uint32_t sel : 1;
20433  uint32_t : 31;
20434 };
20435 
20438 #endif /* __ASSEMBLY__ */
20439 
20441 #define ALT_SYSMGR_PINMUX_GPLMUX26_OFST 0x23c
20442 
20476 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_LSB 0
20477 
20478 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_MSB 0
20479 
20480 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_WIDTH 1
20481 
20482 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET_MSK 0x00000001
20483 
20484 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_CLR_MSK 0xfffffffe
20485 
20486 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_RESET 0x0
20487 
20488 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_GET(value) (((value) & 0x00000001) >> 0)
20489 
20490 #define ALT_SYSMGR_PINMUX_GPLMUX27_SEL_SET(value) (((value) << 0) & 0x00000001)
20491 
20492 #ifndef __ASSEMBLY__
20493 
20504 {
20505  uint32_t sel : 1;
20506  uint32_t : 31;
20507 };
20508 
20511 #endif /* __ASSEMBLY__ */
20512 
20514 #define ALT_SYSMGR_PINMUX_GPLMUX27_OFST 0x240
20515 
20549 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_LSB 0
20550 
20551 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_MSB 0
20552 
20553 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_WIDTH 1
20554 
20555 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET_MSK 0x00000001
20556 
20557 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_CLR_MSK 0xfffffffe
20558 
20559 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_RESET 0x0
20560 
20561 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_GET(value) (((value) & 0x00000001) >> 0)
20562 
20563 #define ALT_SYSMGR_PINMUX_GPLMUX28_SEL_SET(value) (((value) << 0) & 0x00000001)
20564 
20565 #ifndef __ASSEMBLY__
20566 
20577 {
20578  uint32_t sel : 1;
20579  uint32_t : 31;
20580 };
20581 
20584 #endif /* __ASSEMBLY__ */
20585 
20587 #define ALT_SYSMGR_PINMUX_GPLMUX28_OFST 0x244
20588 
20622 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_LSB 0
20623 
20624 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_MSB 0
20625 
20626 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_WIDTH 1
20627 
20628 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET_MSK 0x00000001
20629 
20630 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_CLR_MSK 0xfffffffe
20631 
20632 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_RESET 0x0
20633 
20634 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_GET(value) (((value) & 0x00000001) >> 0)
20635 
20636 #define ALT_SYSMGR_PINMUX_GPLMUX29_SEL_SET(value) (((value) << 0) & 0x00000001)
20637 
20638 #ifndef __ASSEMBLY__
20639 
20650 {
20651  uint32_t sel : 1;
20652  uint32_t : 31;
20653 };
20654 
20657 #endif /* __ASSEMBLY__ */
20658 
20660 #define ALT_SYSMGR_PINMUX_GPLMUX29_OFST 0x248
20661 
20695 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_LSB 0
20696 
20697 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_MSB 0
20698 
20699 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_WIDTH 1
20700 
20701 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET_MSK 0x00000001
20702 
20703 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_CLR_MSK 0xfffffffe
20704 
20705 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_RESET 0x0
20706 
20707 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_GET(value) (((value) & 0x00000001) >> 0)
20708 
20709 #define ALT_SYSMGR_PINMUX_GPLMUX30_SEL_SET(value) (((value) << 0) & 0x00000001)
20710 
20711 #ifndef __ASSEMBLY__
20712 
20723 {
20724  uint32_t sel : 1;
20725  uint32_t : 31;
20726 };
20727 
20730 #endif /* __ASSEMBLY__ */
20731 
20733 #define ALT_SYSMGR_PINMUX_GPLMUX30_OFST 0x24c
20734 
20768 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_LSB 0
20769 
20770 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_MSB 0
20771 
20772 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_WIDTH 1
20773 
20774 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET_MSK 0x00000001
20775 
20776 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_CLR_MSK 0xfffffffe
20777 
20778 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_RESET 0x0
20779 
20780 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_GET(value) (((value) & 0x00000001) >> 0)
20781 
20782 #define ALT_SYSMGR_PINMUX_GPLMUX31_SEL_SET(value) (((value) << 0) & 0x00000001)
20783 
20784 #ifndef __ASSEMBLY__
20785 
20796 {
20797  uint32_t sel : 1;
20798  uint32_t : 31;
20799 };
20800 
20803 #endif /* __ASSEMBLY__ */
20804 
20806 #define ALT_SYSMGR_PINMUX_GPLMUX31_OFST 0x250
20807 
20841 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_LSB 0
20842 
20843 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_MSB 0
20844 
20845 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_WIDTH 1
20846 
20847 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET_MSK 0x00000001
20848 
20849 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_CLR_MSK 0xfffffffe
20850 
20851 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_RESET 0x0
20852 
20853 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_GET(value) (((value) & 0x00000001) >> 0)
20854 
20855 #define ALT_SYSMGR_PINMUX_GPLMUX32_SEL_SET(value) (((value) << 0) & 0x00000001)
20856 
20857 #ifndef __ASSEMBLY__
20858 
20869 {
20870  uint32_t sel : 1;
20871  uint32_t : 31;
20872 };
20873 
20876 #endif /* __ASSEMBLY__ */
20877 
20879 #define ALT_SYSMGR_PINMUX_GPLMUX32_OFST 0x254
20880 
20914 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_LSB 0
20915 
20916 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_MSB 0
20917 
20918 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_WIDTH 1
20919 
20920 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET_MSK 0x00000001
20921 
20922 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_CLR_MSK 0xfffffffe
20923 
20924 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_RESET 0x0
20925 
20926 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_GET(value) (((value) & 0x00000001) >> 0)
20927 
20928 #define ALT_SYSMGR_PINMUX_GPLMUX33_SEL_SET(value) (((value) << 0) & 0x00000001)
20929 
20930 #ifndef __ASSEMBLY__
20931 
20942 {
20943  uint32_t sel : 1;
20944  uint32_t : 31;
20945 };
20946 
20949 #endif /* __ASSEMBLY__ */
20950 
20952 #define ALT_SYSMGR_PINMUX_GPLMUX33_OFST 0x258
20953 
20987 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_LSB 0
20988 
20989 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_MSB 0
20990 
20991 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_WIDTH 1
20992 
20993 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET_MSK 0x00000001
20994 
20995 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_CLR_MSK 0xfffffffe
20996 
20997 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_RESET 0x0
20998 
20999 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_GET(value) (((value) & 0x00000001) >> 0)
21000 
21001 #define ALT_SYSMGR_PINMUX_GPLMUX34_SEL_SET(value) (((value) << 0) & 0x00000001)
21002 
21003 #ifndef __ASSEMBLY__
21004 
21015 {
21016  uint32_t sel : 1;
21017  uint32_t : 31;
21018 };
21019 
21022 #endif /* __ASSEMBLY__ */
21023 
21025 #define ALT_SYSMGR_PINMUX_GPLMUX34_OFST 0x25c
21026 
21060 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_LSB 0
21061 
21062 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_MSB 0
21063 
21064 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_WIDTH 1
21065 
21066 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET_MSK 0x00000001
21067 
21068 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_CLR_MSK 0xfffffffe
21069 
21070 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_RESET 0x0
21071 
21072 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_GET(value) (((value) & 0x00000001) >> 0)
21073 
21074 #define ALT_SYSMGR_PINMUX_GPLMUX35_SEL_SET(value) (((value) << 0) & 0x00000001)
21075 
21076 #ifndef __ASSEMBLY__
21077 
21088 {
21089  uint32_t sel : 1;
21090  uint32_t : 31;
21091 };
21092 
21095 #endif /* __ASSEMBLY__ */
21096 
21098 #define ALT_SYSMGR_PINMUX_GPLMUX35_OFST 0x260
21099 
21133 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_LSB 0
21134 
21135 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_MSB 0
21136 
21137 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_WIDTH 1
21138 
21139 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET_MSK 0x00000001
21140 
21141 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_CLR_MSK 0xfffffffe
21142 
21143 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_RESET 0x0
21144 
21145 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_GET(value) (((value) & 0x00000001) >> 0)
21146 
21147 #define ALT_SYSMGR_PINMUX_GPLMUX36_SEL_SET(value) (((value) << 0) & 0x00000001)
21148 
21149 #ifndef __ASSEMBLY__
21150 
21161 {
21162  uint32_t sel : 1;
21163  uint32_t : 31;
21164 };
21165 
21168 #endif /* __ASSEMBLY__ */
21169 
21171 #define ALT_SYSMGR_PINMUX_GPLMUX36_OFST 0x264
21172 
21206 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_LSB 0
21207 
21208 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_MSB 0
21209 
21210 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_WIDTH 1
21211 
21212 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET_MSK 0x00000001
21213 
21214 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_CLR_MSK 0xfffffffe
21215 
21216 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_RESET 0x0
21217 
21218 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_GET(value) (((value) & 0x00000001) >> 0)
21219 
21220 #define ALT_SYSMGR_PINMUX_GPLMUX37_SEL_SET(value) (((value) << 0) & 0x00000001)
21221 
21222 #ifndef __ASSEMBLY__
21223 
21234 {
21235  uint32_t sel : 1;
21236  uint32_t : 31;
21237 };
21238 
21241 #endif /* __ASSEMBLY__ */
21242 
21244 #define ALT_SYSMGR_PINMUX_GPLMUX37_OFST 0x268
21245 
21279 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_LSB 0
21280 
21281 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_MSB 0
21282 
21283 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_WIDTH 1
21284 
21285 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET_MSK 0x00000001
21286 
21287 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_CLR_MSK 0xfffffffe
21288 
21289 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_RESET 0x0
21290 
21291 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_GET(value) (((value) & 0x00000001) >> 0)
21292 
21293 #define ALT_SYSMGR_PINMUX_GPLMUX38_SEL_SET(value) (((value) << 0) & 0x00000001)
21294 
21295 #ifndef __ASSEMBLY__
21296 
21307 {
21308  uint32_t sel : 1;
21309  uint32_t : 31;
21310 };
21311 
21314 #endif /* __ASSEMBLY__ */
21315 
21317 #define ALT_SYSMGR_PINMUX_GPLMUX38_OFST 0x26c
21318 
21352 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_LSB 0
21353 
21354 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_MSB 0
21355 
21356 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_WIDTH 1
21357 
21358 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET_MSK 0x00000001
21359 
21360 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_CLR_MSK 0xfffffffe
21361 
21362 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_RESET 0x0
21363 
21364 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_GET(value) (((value) & 0x00000001) >> 0)
21365 
21366 #define ALT_SYSMGR_PINMUX_GPLMUX39_SEL_SET(value) (((value) << 0) & 0x00000001)
21367 
21368 #ifndef __ASSEMBLY__
21369 
21380 {
21381  uint32_t sel : 1;
21382  uint32_t : 31;
21383 };
21384 
21387 #endif /* __ASSEMBLY__ */
21388 
21390 #define ALT_SYSMGR_PINMUX_GPLMUX39_OFST 0x270
21391 
21425 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_LSB 0
21426 
21427 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_MSB 0
21428 
21429 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_WIDTH 1
21430 
21431 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET_MSK 0x00000001
21432 
21433 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_CLR_MSK 0xfffffffe
21434 
21435 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_RESET 0x0
21436 
21437 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_GET(value) (((value) & 0x00000001) >> 0)
21438 
21439 #define ALT_SYSMGR_PINMUX_GPLMUX40_SEL_SET(value) (((value) << 0) & 0x00000001)
21440 
21441 #ifndef __ASSEMBLY__
21442 
21453 {
21454  uint32_t sel : 1;
21455  uint32_t : 31;
21456 };
21457 
21460 #endif /* __ASSEMBLY__ */
21461 
21463 #define ALT_SYSMGR_PINMUX_GPLMUX40_OFST 0x274
21464 
21498 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_LSB 0
21499 
21500 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_MSB 0
21501 
21502 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_WIDTH 1
21503 
21504 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET_MSK 0x00000001
21505 
21506 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_CLR_MSK 0xfffffffe
21507 
21508 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_RESET 0x0
21509 
21510 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_GET(value) (((value) & 0x00000001) >> 0)
21511 
21512 #define ALT_SYSMGR_PINMUX_GPLMUX41_SEL_SET(value) (((value) << 0) & 0x00000001)
21513 
21514 #ifndef __ASSEMBLY__
21515 
21526 {
21527  uint32_t sel : 1;
21528  uint32_t : 31;
21529 };
21530 
21533 #endif /* __ASSEMBLY__ */
21534 
21536 #define ALT_SYSMGR_PINMUX_GPLMUX41_OFST 0x278
21537 
21571 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_LSB 0
21572 
21573 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_MSB 0
21574 
21575 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_WIDTH 1
21576 
21577 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET_MSK 0x00000001
21578 
21579 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_CLR_MSK 0xfffffffe
21580 
21581 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_RESET 0x0
21582 
21583 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_GET(value) (((value) & 0x00000001) >> 0)
21584 
21585 #define ALT_SYSMGR_PINMUX_GPLMUX42_SEL_SET(value) (((value) << 0) & 0x00000001)
21586 
21587 #ifndef __ASSEMBLY__
21588 
21599 {
21600  uint32_t sel : 1;
21601  uint32_t : 31;
21602 };
21603 
21606 #endif /* __ASSEMBLY__ */
21607 
21609 #define ALT_SYSMGR_PINMUX_GPLMUX42_OFST 0x27c
21610 
21644 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_LSB 0
21645 
21646 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_MSB 0
21647 
21648 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_WIDTH 1
21649 
21650 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET_MSK 0x00000001
21651 
21652 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_CLR_MSK 0xfffffffe
21653 
21654 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_RESET 0x0
21655 
21656 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_GET(value) (((value) & 0x00000001) >> 0)
21657 
21658 #define ALT_SYSMGR_PINMUX_GPLMUX43_SEL_SET(value) (((value) << 0) & 0x00000001)
21659 
21660 #ifndef __ASSEMBLY__
21661 
21672 {
21673  uint32_t sel : 1;
21674  uint32_t : 31;
21675 };
21676 
21679 #endif /* __ASSEMBLY__ */
21680 
21682 #define ALT_SYSMGR_PINMUX_GPLMUX43_OFST 0x280
21683 
21717 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_LSB 0
21718 
21719 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_MSB 0
21720 
21721 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_WIDTH 1
21722 
21723 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET_MSK 0x00000001
21724 
21725 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_CLR_MSK 0xfffffffe
21726 
21727 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_RESET 0x0
21728 
21729 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_GET(value) (((value) & 0x00000001) >> 0)
21730 
21731 #define ALT_SYSMGR_PINMUX_GPLMUX44_SEL_SET(value) (((value) << 0) & 0x00000001)
21732 
21733 #ifndef __ASSEMBLY__
21734 
21745 {
21746  uint32_t sel : 1;
21747  uint32_t : 31;
21748 };
21749 
21752 #endif /* __ASSEMBLY__ */
21753 
21755 #define ALT_SYSMGR_PINMUX_GPLMUX44_OFST 0x284
21756 
21790 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_LSB 0
21791 
21792 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_MSB 0
21793 
21794 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_WIDTH 1
21795 
21796 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET_MSK 0x00000001
21797 
21798 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_CLR_MSK 0xfffffffe
21799 
21800 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_RESET 0x0
21801 
21802 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_GET(value) (((value) & 0x00000001) >> 0)
21803 
21804 #define ALT_SYSMGR_PINMUX_GPLMUX45_SEL_SET(value) (((value) << 0) & 0x00000001)
21805 
21806 #ifndef __ASSEMBLY__
21807 
21818 {
21819  uint32_t sel : 1;
21820  uint32_t : 31;
21821 };
21822 
21825 #endif /* __ASSEMBLY__ */
21826 
21828 #define ALT_SYSMGR_PINMUX_GPLMUX45_OFST 0x288
21829 
21863 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_LSB 0
21864 
21865 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_MSB 0
21866 
21867 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_WIDTH 1
21868 
21869 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET_MSK 0x00000001
21870 
21871 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_CLR_MSK 0xfffffffe
21872 
21873 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_RESET 0x0
21874 
21875 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_GET(value) (((value) & 0x00000001) >> 0)
21876 
21877 #define ALT_SYSMGR_PINMUX_GPLMUX46_SEL_SET(value) (((value) << 0) & 0x00000001)
21878 
21879 #ifndef __ASSEMBLY__
21880 
21891 {
21892  uint32_t sel : 1;
21893  uint32_t : 31;
21894 };
21895 
21898 #endif /* __ASSEMBLY__ */
21899 
21901 #define ALT_SYSMGR_PINMUX_GPLMUX46_OFST 0x28c
21902 
21936 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_LSB 0
21937 
21938 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_MSB 0
21939 
21940 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_WIDTH 1
21941 
21942 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET_MSK 0x00000001
21943 
21944 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_CLR_MSK 0xfffffffe
21945 
21946 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_RESET 0x0
21947 
21948 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_GET(value) (((value) & 0x00000001) >> 0)
21949 
21950 #define ALT_SYSMGR_PINMUX_GPLMUX47_SEL_SET(value) (((value) << 0) & 0x00000001)
21951 
21952 #ifndef __ASSEMBLY__
21953 
21964 {
21965  uint32_t sel : 1;
21966  uint32_t : 31;
21967 };
21968 
21971 #endif /* __ASSEMBLY__ */
21972 
21974 #define ALT_SYSMGR_PINMUX_GPLMUX47_OFST 0x290
21975 
22009 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_LSB 0
22010 
22011 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_MSB 0
22012 
22013 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_WIDTH 1
22014 
22015 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET_MSK 0x00000001
22016 
22017 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_CLR_MSK 0xfffffffe
22018 
22019 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_RESET 0x0
22020 
22021 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_GET(value) (((value) & 0x00000001) >> 0)
22022 
22023 #define ALT_SYSMGR_PINMUX_GPLMUX48_SEL_SET(value) (((value) << 0) & 0x00000001)
22024 
22025 #ifndef __ASSEMBLY__
22026 
22037 {
22038  uint32_t sel : 1;
22039  uint32_t : 31;
22040 };
22041 
22044 #endif /* __ASSEMBLY__ */
22045 
22047 #define ALT_SYSMGR_PINMUX_GPLMUX48_OFST 0x294
22048 
22082 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_LSB 0
22083 
22084 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_MSB 0
22085 
22086 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_WIDTH 1
22087 
22088 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET_MSK 0x00000001
22089 
22090 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_CLR_MSK 0xfffffffe
22091 
22092 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_RESET 0x0
22093 
22094 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_GET(value) (((value) & 0x00000001) >> 0)
22095 
22096 #define ALT_SYSMGR_PINMUX_GPLMUX49_SEL_SET(value) (((value) << 0) & 0x00000001)
22097 
22098 #ifndef __ASSEMBLY__
22099 
22110 {
22111  uint32_t sel : 1;
22112  uint32_t : 31;
22113 };
22114 
22117 #endif /* __ASSEMBLY__ */
22118 
22120 #define ALT_SYSMGR_PINMUX_GPLMUX49_OFST 0x298
22121 
22155 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_LSB 0
22156 
22157 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_MSB 0
22158 
22159 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_WIDTH 1
22160 
22161 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET_MSK 0x00000001
22162 
22163 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_CLR_MSK 0xfffffffe
22164 
22165 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_RESET 0x0
22166 
22167 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_GET(value) (((value) & 0x00000001) >> 0)
22168 
22169 #define ALT_SYSMGR_PINMUX_GPLMUX50_SEL_SET(value) (((value) << 0) & 0x00000001)
22170 
22171 #ifndef __ASSEMBLY__
22172 
22183 {
22184  uint32_t sel : 1;
22185  uint32_t : 31;
22186 };
22187 
22190 #endif /* __ASSEMBLY__ */
22191 
22193 #define ALT_SYSMGR_PINMUX_GPLMUX50_OFST 0x29c
22194 
22228 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_LSB 0
22229 
22230 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_MSB 0
22231 
22232 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_WIDTH 1
22233 
22234 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET_MSK 0x00000001
22235 
22236 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_CLR_MSK 0xfffffffe
22237 
22238 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_RESET 0x0
22239 
22240 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_GET(value) (((value) & 0x00000001) >> 0)
22241 
22242 #define ALT_SYSMGR_PINMUX_GPLMUX51_SEL_SET(value) (((value) << 0) & 0x00000001)
22243 
22244 #ifndef __ASSEMBLY__
22245 
22256 {
22257  uint32_t sel : 1;
22258  uint32_t : 31;
22259 };
22260 
22263 #endif /* __ASSEMBLY__ */
22264 
22266 #define ALT_SYSMGR_PINMUX_GPLMUX51_OFST 0x2a0
22267 
22301 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_LSB 0
22302 
22303 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_MSB 0
22304 
22305 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_WIDTH 1
22306 
22307 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET_MSK 0x00000001
22308 
22309 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_CLR_MSK 0xfffffffe
22310 
22311 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_RESET 0x0
22312 
22313 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_GET(value) (((value) & 0x00000001) >> 0)
22314 
22315 #define ALT_SYSMGR_PINMUX_GPLMUX52_SEL_SET(value) (((value) << 0) & 0x00000001)
22316 
22317 #ifndef __ASSEMBLY__
22318 
22329 {
22330  uint32_t sel : 1;
22331  uint32_t : 31;
22332 };
22333 
22336 #endif /* __ASSEMBLY__ */
22337 
22339 #define ALT_SYSMGR_PINMUX_GPLMUX52_OFST 0x2a4
22340 
22374 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_LSB 0
22375 
22376 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_MSB 0
22377 
22378 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_WIDTH 1
22379 
22380 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET_MSK 0x00000001
22381 
22382 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_CLR_MSK 0xfffffffe
22383 
22384 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_RESET 0x0
22385 
22386 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_GET(value) (((value) & 0x00000001) >> 0)
22387 
22388 #define ALT_SYSMGR_PINMUX_GPLMUX53_SEL_SET(value) (((value) << 0) & 0x00000001)
22389 
22390 #ifndef __ASSEMBLY__
22391 
22402 {
22403  uint32_t sel : 1;
22404  uint32_t : 31;
22405 };
22406 
22409 #endif /* __ASSEMBLY__ */
22410 
22412 #define ALT_SYSMGR_PINMUX_GPLMUX53_OFST 0x2a8
22413 
22447 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_LSB 0
22448 
22449 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_MSB 0
22450 
22451 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_WIDTH 1
22452 
22453 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET_MSK 0x00000001
22454 
22455 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_CLR_MSK 0xfffffffe
22456 
22457 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_RESET 0x0
22458 
22459 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_GET(value) (((value) & 0x00000001) >> 0)
22460 
22461 #define ALT_SYSMGR_PINMUX_GPLMUX54_SEL_SET(value) (((value) << 0) & 0x00000001)
22462 
22463 #ifndef __ASSEMBLY__
22464 
22475 {
22476  uint32_t sel : 1;
22477  uint32_t : 31;
22478 };
22479 
22482 #endif /* __ASSEMBLY__ */
22483 
22485 #define ALT_SYSMGR_PINMUX_GPLMUX54_OFST 0x2ac
22486 
22520 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_LSB 0
22521 
22522 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_MSB 0
22523 
22524 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_WIDTH 1
22525 
22526 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET_MSK 0x00000001
22527 
22528 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_CLR_MSK 0xfffffffe
22529 
22530 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_RESET 0x0
22531 
22532 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_GET(value) (((value) & 0x00000001) >> 0)
22533 
22534 #define ALT_SYSMGR_PINMUX_GPLMUX55_SEL_SET(value) (((value) << 0) & 0x00000001)
22535 
22536 #ifndef __ASSEMBLY__
22537 
22548 {
22549  uint32_t sel : 1;
22550  uint32_t : 31;
22551 };
22552 
22555 #endif /* __ASSEMBLY__ */
22556 
22558 #define ALT_SYSMGR_PINMUX_GPLMUX55_OFST 0x2b0
22559 
22593 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_LSB 0
22594 
22595 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_MSB 0
22596 
22597 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_WIDTH 1
22598 
22599 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET_MSK 0x00000001
22600 
22601 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_CLR_MSK 0xfffffffe
22602 
22603 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_RESET 0x0
22604 
22605 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_GET(value) (((value) & 0x00000001) >> 0)
22606 
22607 #define ALT_SYSMGR_PINMUX_GPLMUX56_SEL_SET(value) (((value) << 0) & 0x00000001)
22608 
22609 #ifndef __ASSEMBLY__
22610 
22621 {
22622  uint32_t sel : 1;
22623  uint32_t : 31;
22624 };
22625 
22628 #endif /* __ASSEMBLY__ */
22629 
22631 #define ALT_SYSMGR_PINMUX_GPLMUX56_OFST 0x2b4
22632 
22666 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_LSB 0
22667 
22668 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_MSB 0
22669 
22670 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_WIDTH 1
22671 
22672 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET_MSK 0x00000001
22673 
22674 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_CLR_MSK 0xfffffffe
22675 
22676 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_RESET 0x0
22677 
22678 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_GET(value) (((value) & 0x00000001) >> 0)
22679 
22680 #define ALT_SYSMGR_PINMUX_GPLMUX57_SEL_SET(value) (((value) << 0) & 0x00000001)
22681 
22682 #ifndef __ASSEMBLY__
22683 
22694 {
22695  uint32_t sel : 1;
22696  uint32_t : 31;
22697 };
22698 
22701 #endif /* __ASSEMBLY__ */
22702 
22704 #define ALT_SYSMGR_PINMUX_GPLMUX57_OFST 0x2b8
22705 
22739 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_LSB 0
22740 
22741 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_MSB 0
22742 
22743 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_WIDTH 1
22744 
22745 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET_MSK 0x00000001
22746 
22747 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_CLR_MSK 0xfffffffe
22748 
22749 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_RESET 0x0
22750 
22751 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_GET(value) (((value) & 0x00000001) >> 0)
22752 
22753 #define ALT_SYSMGR_PINMUX_GPLMUX58_SEL_SET(value) (((value) << 0) & 0x00000001)
22754 
22755 #ifndef __ASSEMBLY__
22756 
22767 {
22768  uint32_t sel : 1;
22769  uint32_t : 31;
22770 };
22771 
22774 #endif /* __ASSEMBLY__ */
22775 
22777 #define ALT_SYSMGR_PINMUX_GPLMUX58_OFST 0x2bc
22778 
22812 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_LSB 0
22813 
22814 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_MSB 0
22815 
22816 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_WIDTH 1
22817 
22818 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET_MSK 0x00000001
22819 
22820 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_CLR_MSK 0xfffffffe
22821 
22822 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_RESET 0x0
22823 
22824 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_GET(value) (((value) & 0x00000001) >> 0)
22825 
22826 #define ALT_SYSMGR_PINMUX_GPLMUX59_SEL_SET(value) (((value) << 0) & 0x00000001)
22827 
22828 #ifndef __ASSEMBLY__
22829 
22840 {
22841  uint32_t sel : 1;
22842  uint32_t : 31;
22843 };
22844 
22847 #endif /* __ASSEMBLY__ */
22848 
22850 #define ALT_SYSMGR_PINMUX_GPLMUX59_OFST 0x2c0
22851 
22885 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_LSB 0
22886 
22887 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_MSB 0
22888 
22889 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_WIDTH 1
22890 
22891 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET_MSK 0x00000001
22892 
22893 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_CLR_MSK 0xfffffffe
22894 
22895 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_RESET 0x0
22896 
22897 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_GET(value) (((value) & 0x00000001) >> 0)
22898 
22899 #define ALT_SYSMGR_PINMUX_GPLMUX60_SEL_SET(value) (((value) << 0) & 0x00000001)
22900 
22901 #ifndef __ASSEMBLY__
22902 
22913 {
22914  uint32_t sel : 1;
22915  uint32_t : 31;
22916 };
22917 
22920 #endif /* __ASSEMBLY__ */
22921 
22923 #define ALT_SYSMGR_PINMUX_GPLMUX60_OFST 0x2c4
22924 
22958 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_LSB 0
22959 
22960 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_MSB 0
22961 
22962 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_WIDTH 1
22963 
22964 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET_MSK 0x00000001
22965 
22966 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_CLR_MSK 0xfffffffe
22967 
22968 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_RESET 0x0
22969 
22970 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_GET(value) (((value) & 0x00000001) >> 0)
22971 
22972 #define ALT_SYSMGR_PINMUX_GPLMUX61_SEL_SET(value) (((value) << 0) & 0x00000001)
22973 
22974 #ifndef __ASSEMBLY__
22975 
22986 {
22987  uint32_t sel : 1;
22988  uint32_t : 31;
22989 };
22990 
22993 #endif /* __ASSEMBLY__ */
22994 
22996 #define ALT_SYSMGR_PINMUX_GPLMUX61_OFST 0x2c8
22997 
23031 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_LSB 0
23032 
23033 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_MSB 0
23034 
23035 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_WIDTH 1
23036 
23037 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET_MSK 0x00000001
23038 
23039 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_CLR_MSK 0xfffffffe
23040 
23041 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_RESET 0x0
23042 
23043 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_GET(value) (((value) & 0x00000001) >> 0)
23044 
23045 #define ALT_SYSMGR_PINMUX_GPLMUX62_SEL_SET(value) (((value) << 0) & 0x00000001)
23046 
23047 #ifndef __ASSEMBLY__
23048 
23059 {
23060  uint32_t sel : 1;
23061  uint32_t : 31;
23062 };
23063 
23066 #endif /* __ASSEMBLY__ */
23067 
23069 #define ALT_SYSMGR_PINMUX_GPLMUX62_OFST 0x2cc
23070 
23104 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_LSB 0
23105 
23106 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_MSB 0
23107 
23108 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_WIDTH 1
23109 
23110 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET_MSK 0x00000001
23111 
23112 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_CLR_MSK 0xfffffffe
23113 
23114 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_RESET 0x0
23115 
23116 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_GET(value) (((value) & 0x00000001) >> 0)
23117 
23118 #define ALT_SYSMGR_PINMUX_GPLMUX63_SEL_SET(value) (((value) << 0) & 0x00000001)
23119 
23120 #ifndef __ASSEMBLY__
23121 
23132 {
23133  uint32_t sel : 1;
23134  uint32_t : 31;
23135 };
23136 
23139 #endif /* __ASSEMBLY__ */
23140 
23142 #define ALT_SYSMGR_PINMUX_GPLMUX63_OFST 0x2d0
23143 
23177 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_LSB 0
23178 
23179 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_MSB 0
23180 
23181 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_WIDTH 1
23182 
23183 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET_MSK 0x00000001
23184 
23185 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_CLR_MSK 0xfffffffe
23186 
23187 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_RESET 0x0
23188 
23189 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_GET(value) (((value) & 0x00000001) >> 0)
23190 
23191 #define ALT_SYSMGR_PINMUX_GPLMUX64_SEL_SET(value) (((value) << 0) & 0x00000001)
23192 
23193 #ifndef __ASSEMBLY__
23194 
23205 {
23206  uint32_t sel : 1;
23207  uint32_t : 31;
23208 };
23209 
23212 #endif /* __ASSEMBLY__ */
23213 
23215 #define ALT_SYSMGR_PINMUX_GPLMUX64_OFST 0x2d4
23216 
23250 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_LSB 0
23251 
23252 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_MSB 0
23253 
23254 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_WIDTH 1
23255 
23256 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET_MSK 0x00000001
23257 
23258 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_CLR_MSK 0xfffffffe
23259 
23260 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_RESET 0x0
23261 
23262 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_GET(value) (((value) & 0x00000001) >> 0)
23263 
23264 #define ALT_SYSMGR_PINMUX_GPLMUX65_SEL_SET(value) (((value) << 0) & 0x00000001)
23265 
23266 #ifndef __ASSEMBLY__
23267 
23278 {
23279  uint32_t sel : 1;
23280  uint32_t : 31;
23281 };
23282 
23285 #endif /* __ASSEMBLY__ */
23286 
23288 #define ALT_SYSMGR_PINMUX_GPLMUX65_OFST 0x2d8
23289 
23323 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_LSB 0
23324 
23325 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_MSB 0
23326 
23327 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_WIDTH 1
23328 
23329 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET_MSK 0x00000001
23330 
23331 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_CLR_MSK 0xfffffffe
23332 
23333 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_RESET 0x0
23334 
23335 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_GET(value) (((value) & 0x00000001) >> 0)
23336 
23337 #define ALT_SYSMGR_PINMUX_GPLMUX66_SEL_SET(value) (((value) << 0) & 0x00000001)
23338 
23339 #ifndef __ASSEMBLY__
23340 
23351 {
23352  uint32_t sel : 1;
23353  uint32_t : 31;
23354 };
23355 
23358 #endif /* __ASSEMBLY__ */
23359 
23361 #define ALT_SYSMGR_PINMUX_GPLMUX66_OFST 0x2dc
23362 
23396 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_LSB 0
23397 
23398 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_MSB 0
23399 
23400 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_WIDTH 1
23401 
23402 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET_MSK 0x00000001
23403 
23404 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_CLR_MSK 0xfffffffe
23405 
23406 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_RESET 0x0
23407 
23408 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_GET(value) (((value) & 0x00000001) >> 0)
23409 
23410 #define ALT_SYSMGR_PINMUX_GPLMUX67_SEL_SET(value) (((value) << 0) & 0x00000001)
23411 
23412 #ifndef __ASSEMBLY__
23413 
23424 {
23425  uint32_t sel : 1;
23426  uint32_t : 31;
23427 };
23428 
23431 #endif /* __ASSEMBLY__ */
23432 
23434 #define ALT_SYSMGR_PINMUX_GPLMUX67_OFST 0x2e0
23435 
23469 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_LSB 0
23470 
23471 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_MSB 0
23472 
23473 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_WIDTH 1
23474 
23475 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET_MSK 0x00000001
23476 
23477 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_CLR_MSK 0xfffffffe
23478 
23479 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_RESET 0x0
23480 
23481 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_GET(value) (((value) & 0x00000001) >> 0)
23482 
23483 #define ALT_SYSMGR_PINMUX_GPLMUX68_SEL_SET(value) (((value) << 0) & 0x00000001)
23484 
23485 #ifndef __ASSEMBLY__
23486 
23497 {
23498  uint32_t sel : 1;
23499  uint32_t : 31;
23500 };
23501 
23504 #endif /* __ASSEMBLY__ */
23505 
23507 #define ALT_SYSMGR_PINMUX_GPLMUX68_OFST 0x2e4
23508 
23542 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_LSB 0
23543 
23544 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_MSB 0
23545 
23546 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_WIDTH 1
23547 
23548 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET_MSK 0x00000001
23549 
23550 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_CLR_MSK 0xfffffffe
23551 
23552 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_RESET 0x0
23553 
23554 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_GET(value) (((value) & 0x00000001) >> 0)
23555 
23556 #define ALT_SYSMGR_PINMUX_GPLMUX69_SEL_SET(value) (((value) << 0) & 0x00000001)
23557 
23558 #ifndef __ASSEMBLY__
23559 
23570 {
23571  uint32_t sel : 1;
23572  uint32_t : 31;
23573 };
23574 
23577 #endif /* __ASSEMBLY__ */
23578 
23580 #define ALT_SYSMGR_PINMUX_GPLMUX69_OFST 0x2e8
23581 
23615 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_LSB 0
23616 
23617 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_MSB 0
23618 
23619 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_WIDTH 1
23620 
23621 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET_MSK 0x00000001
23622 
23623 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_CLR_MSK 0xfffffffe
23624 
23625 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_RESET 0x0
23626 
23627 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_GET(value) (((value) & 0x00000001) >> 0)
23628 
23629 #define ALT_SYSMGR_PINMUX_GPLMUX70_SEL_SET(value) (((value) << 0) & 0x00000001)
23630 
23631 #ifndef __ASSEMBLY__
23632 
23643 {
23644  uint32_t sel : 1;
23645  uint32_t : 31;
23646 };
23647 
23650 #endif /* __ASSEMBLY__ */
23651 
23653 #define ALT_SYSMGR_PINMUX_GPLMUX70_OFST 0x2ec
23654 
23686 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_LSB 0
23687 
23688 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_MSB 0
23689 
23690 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_WIDTH 1
23691 
23692 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET_MSK 0x00000001
23693 
23694 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_CLR_MSK 0xfffffffe
23695 
23696 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_RESET 0x0
23697 
23698 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23699 
23700 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23701 
23702 #ifndef __ASSEMBLY__
23703 
23714 {
23715  uint32_t sel : 1;
23716  uint32_t : 31;
23717 };
23718 
23721 #endif /* __ASSEMBLY__ */
23722 
23724 #define ALT_SYSMGR_PINMUX_NANDUSEFPGA_OFST 0x2f0
23725 
23757 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_LSB 0
23758 
23759 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_MSB 0
23760 
23761 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_WIDTH 1
23762 
23763 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET_MSK 0x00000001
23764 
23765 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_CLR_MSK 0xfffffffe
23766 
23767 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_RESET 0x0
23768 
23769 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23770 
23771 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23772 
23773 #ifndef __ASSEMBLY__
23774 
23785 {
23786  uint32_t sel : 1;
23787  uint32_t : 31;
23788 };
23789 
23792 #endif /* __ASSEMBLY__ */
23793 
23795 #define ALT_SYSMGR_PINMUX_RGMII1USEFPGA_OFST 0x2f8
23796 
23828 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_LSB 0
23829 
23830 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_MSB 0
23831 
23832 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_WIDTH 1
23833 
23834 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET_MSK 0x00000001
23835 
23836 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_CLR_MSK 0xfffffffe
23837 
23838 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_RESET 0x0
23839 
23840 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23841 
23842 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23843 
23844 #ifndef __ASSEMBLY__
23845 
23856 {
23857  uint32_t sel : 1;
23858  uint32_t : 31;
23859 };
23860 
23863 #endif /* __ASSEMBLY__ */
23864 
23866 #define ALT_SYSMGR_PINMUX_I2C0USEFPGA_OFST 0x304
23867 
23899 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_LSB 0
23900 
23901 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_MSB 0
23902 
23903 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_WIDTH 1
23904 
23905 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET_MSK 0x00000001
23906 
23907 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_CLR_MSK 0xfffffffe
23908 
23909 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_RESET 0x0
23910 
23911 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23912 
23913 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23914 
23915 #ifndef __ASSEMBLY__
23916 
23927 {
23928  uint32_t sel : 1;
23929  uint32_t : 31;
23930 };
23931 
23934 #endif /* __ASSEMBLY__ */
23935 
23937 #define ALT_SYSMGR_PINMUX_RGMII0USEFPGA_OFST 0x314
23938 
23970 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_LSB 0
23971 
23972 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_MSB 0
23973 
23974 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_WIDTH 1
23975 
23976 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET_MSK 0x00000001
23977 
23978 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_CLR_MSK 0xfffffffe
23979 
23980 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_RESET 0x0
23981 
23982 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
23983 
23984 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
23985 
23986 #ifndef __ASSEMBLY__
23987 
23998 {
23999  uint32_t sel : 1;
24000  uint32_t : 31;
24001 };
24002 
24005 #endif /* __ASSEMBLY__ */
24006 
24008 #define ALT_SYSMGR_PINMUX_I2C3USEFPGA_OFST 0x324
24009 
24041 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_LSB 0
24042 
24043 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_MSB 0
24044 
24045 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_WIDTH 1
24046 
24047 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET_MSK 0x00000001
24048 
24049 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_CLR_MSK 0xfffffffe
24050 
24051 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_RESET 0x0
24052 
24053 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24054 
24055 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24056 
24057 #ifndef __ASSEMBLY__
24058 
24069 {
24070  uint32_t sel : 1;
24071  uint32_t : 31;
24072 };
24073 
24076 #endif /* __ASSEMBLY__ */
24077 
24079 #define ALT_SYSMGR_PINMUX_I2C2USEFPGA_OFST 0x328
24080 
24112 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_LSB 0
24113 
24114 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_MSB 0
24115 
24116 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_WIDTH 1
24117 
24118 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET_MSK 0x00000001
24119 
24120 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_CLR_MSK 0xfffffffe
24121 
24122 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_RESET 0x0
24123 
24124 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24125 
24126 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24127 
24128 #ifndef __ASSEMBLY__
24129 
24140 {
24141  uint32_t sel : 1;
24142  uint32_t : 31;
24143 };
24144 
24147 #endif /* __ASSEMBLY__ */
24148 
24150 #define ALT_SYSMGR_PINMUX_I2C1USEFPGA_OFST 0x32c
24151 
24183 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_LSB 0
24184 
24185 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_MSB 0
24186 
24187 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_WIDTH 1
24188 
24189 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET_MSK 0x00000001
24190 
24191 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_CLR_MSK 0xfffffffe
24192 
24193 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_RESET 0x0
24194 
24195 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24196 
24197 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24198 
24199 #ifndef __ASSEMBLY__
24200 
24211 {
24212  uint32_t sel : 1;
24213  uint32_t : 31;
24214 };
24215 
24218 #endif /* __ASSEMBLY__ */
24219 
24221 #define ALT_SYSMGR_PINMUX_SPIM1USEFPGA_OFST 0x330
24222 
24254 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_LSB 0
24255 
24256 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_MSB 0
24257 
24258 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_WIDTH 1
24259 
24260 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET_MSK 0x00000001
24261 
24262 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_CLR_MSK 0xfffffffe
24263 
24264 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_RESET 0x0
24265 
24266 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_GET(value) (((value) & 0x00000001) >> 0)
24267 
24268 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_SEL_SET(value) (((value) << 0) & 0x00000001)
24269 
24270 #ifndef __ASSEMBLY__
24271 
24282 {
24283  uint32_t sel : 1;
24284  uint32_t : 31;
24285 };
24286 
24289 #endif /* __ASSEMBLY__ */
24290 
24292 #define ALT_SYSMGR_PINMUX_SPIM0USEFPGA_OFST 0x338
24293 
24294 #ifndef __ASSEMBLY__
24295 
24306 {
24496  volatile uint32_t _pad_0x2f4_0x2f7;
24498  volatile uint32_t _pad_0x2fc_0x303[2];
24500  volatile uint32_t _pad_0x308_0x313[3];
24502  volatile uint32_t _pad_0x318_0x323[3];
24507  volatile uint32_t _pad_0x334_0x337;
24509  volatile uint32_t _pad_0x33c_0x400[49];
24510 };
24511 
24516 {
24517  volatile uint32_t EMACIO0;
24518  volatile uint32_t EMACIO1;
24519  volatile uint32_t EMACIO2;
24520  volatile uint32_t EMACIO3;
24521  volatile uint32_t EMACIO4;
24522  volatile uint32_t EMACIO5;
24523  volatile uint32_t EMACIO6;
24524  volatile uint32_t EMACIO7;
24525  volatile uint32_t EMACIO8;
24526  volatile uint32_t EMACIO9;
24527  volatile uint32_t EMACIO10;
24528  volatile uint32_t EMACIO11;
24529  volatile uint32_t EMACIO12;
24530  volatile uint32_t EMACIO13;
24531  volatile uint32_t EMACIO14;
24532  volatile uint32_t EMACIO15;
24533  volatile uint32_t EMACIO16;
24534  volatile uint32_t EMACIO17;
24535  volatile uint32_t EMACIO18;
24536  volatile uint32_t EMACIO19;
24537  volatile uint32_t FLASHIO0;
24538  volatile uint32_t FLASHIO1;
24539  volatile uint32_t FLASHIO2;
24540  volatile uint32_t FLASHIO3;
24541  volatile uint32_t FLASHIO4;
24542  volatile uint32_t FLASHIO5;
24543  volatile uint32_t FLASHIO6;
24544  volatile uint32_t FLASHIO7;
24545  volatile uint32_t FLASHIO8;
24546  volatile uint32_t FLASHIO9;
24547  volatile uint32_t FLASHIO10;
24548  volatile uint32_t FLASHIO11;
24549  volatile uint32_t GENERALIO0;
24550  volatile uint32_t GENERALIO1;
24551  volatile uint32_t GENERALIO2;
24552  volatile uint32_t GENERALIO3;
24553  volatile uint32_t GENERALIO4;
24554  volatile uint32_t GENERALIO5;
24555  volatile uint32_t GENERALIO6;
24556  volatile uint32_t GENERALIO7;
24557  volatile uint32_t GENERALIO8;
24558  volatile uint32_t GENERALIO9;
24559  volatile uint32_t GENERALIO10;
24560  volatile uint32_t GENERALIO11;
24561  volatile uint32_t GENERALIO12;
24562  volatile uint32_t GENERALIO13;
24563  volatile uint32_t GENERALIO14;
24564  volatile uint32_t GENERALIO15;
24565  volatile uint32_t GENERALIO16;
24566  volatile uint32_t GENERALIO17;
24567  volatile uint32_t GENERALIO18;
24568  volatile uint32_t GENERALIO19;
24569  volatile uint32_t GENERALIO20;
24570  volatile uint32_t GENERALIO21;
24571  volatile uint32_t GENERALIO22;
24572  volatile uint32_t GENERALIO23;
24573  volatile uint32_t GENERALIO24;
24574  volatile uint32_t GENERALIO25;
24575  volatile uint32_t GENERALIO26;
24576  volatile uint32_t GENERALIO27;
24577  volatile uint32_t GENERALIO28;
24578  volatile uint32_t GENERALIO29;
24579  volatile uint32_t GENERALIO30;
24580  volatile uint32_t GENERALIO31;
24581  volatile uint32_t MIXED1IO0;
24582  volatile uint32_t MIXED1IO1;
24583  volatile uint32_t MIXED1IO2;
24584  volatile uint32_t MIXED1IO3;
24585  volatile uint32_t MIXED1IO4;
24586  volatile uint32_t MIXED1IO5;
24587  volatile uint32_t MIXED1IO6;
24588  volatile uint32_t MIXED1IO7;
24589  volatile uint32_t MIXED1IO8;
24590  volatile uint32_t MIXED1IO9;
24591  volatile uint32_t MIXED1IO10;
24592  volatile uint32_t MIXED1IO11;
24593  volatile uint32_t MIXED1IO12;
24594  volatile uint32_t MIXED1IO13;
24595  volatile uint32_t MIXED1IO14;
24596  volatile uint32_t MIXED1IO15;
24597  volatile uint32_t MIXED1IO16;
24598  volatile uint32_t MIXED1IO17;
24599  volatile uint32_t MIXED1IO18;
24600  volatile uint32_t MIXED1IO19;
24601  volatile uint32_t MIXED1IO20;
24602  volatile uint32_t MIXED1IO21;
24603  volatile uint32_t MIXED2IO0;
24604  volatile uint32_t MIXED2IO1;
24605  volatile uint32_t MIXED2IO2;
24606  volatile uint32_t MIXED2IO3;
24607  volatile uint32_t MIXED2IO4;
24608  volatile uint32_t MIXED2IO5;
24609  volatile uint32_t MIXED2IO6;
24610  volatile uint32_t MIXED2IO7;
24611  volatile uint32_t GPLINMUX48;
24612  volatile uint32_t GPLINMUX49;
24613  volatile uint32_t GPLINMUX50;
24614  volatile uint32_t GPLINMUX51;
24615  volatile uint32_t GPLINMUX52;
24616  volatile uint32_t GPLINMUX53;
24617  volatile uint32_t GPLINMUX54;
24618  volatile uint32_t GPLINMUX55;
24619  volatile uint32_t GPLINMUX56;
24620  volatile uint32_t GPLINMUX57;
24621  volatile uint32_t GPLINMUX58;
24622  volatile uint32_t GPLINMUX59;
24623  volatile uint32_t GPLINMUX60;
24624  volatile uint32_t GPLINMUX61;
24625  volatile uint32_t GPLINMUX62;
24626  volatile uint32_t GPLINMUX63;
24627  volatile uint32_t GPLINMUX64;
24628  volatile uint32_t GPLINMUX65;
24629  volatile uint32_t GPLINMUX66;
24630  volatile uint32_t GPLINMUX67;
24631  volatile uint32_t GPLINMUX68;
24632  volatile uint32_t GPLINMUX69;
24633  volatile uint32_t GPLINMUX70;
24634  volatile uint32_t GPLMUX0;
24635  volatile uint32_t GPLMUX1;
24636  volatile uint32_t GPLMUX2;
24637  volatile uint32_t GPLMUX3;
24638  volatile uint32_t GPLMUX4;
24639  volatile uint32_t GPLMUX5;
24640  volatile uint32_t GPLMUX6;
24641  volatile uint32_t GPLMUX7;
24642  volatile uint32_t GPLMUX8;
24643  volatile uint32_t GPLMUX9;
24644  volatile uint32_t GPLMUX10;
24645  volatile uint32_t GPLMUX11;
24646  volatile uint32_t GPLMUX12;
24647  volatile uint32_t GPLMUX13;
24648  volatile uint32_t GPLMUX14;
24649  volatile uint32_t GPLMUX15;
24650  volatile uint32_t GPLMUX16;
24651  volatile uint32_t GPLMUX17;
24652  volatile uint32_t GPLMUX18;
24653  volatile uint32_t GPLMUX19;
24654  volatile uint32_t GPLMUX20;
24655  volatile uint32_t GPLMUX21;
24656  volatile uint32_t GPLMUX22;
24657  volatile uint32_t GPLMUX23;
24658  volatile uint32_t GPLMUX24;
24659  volatile uint32_t GPLMUX25;
24660  volatile uint32_t GPLMUX26;
24661  volatile uint32_t GPLMUX27;
24662  volatile uint32_t GPLMUX28;
24663  volatile uint32_t GPLMUX29;
24664  volatile uint32_t GPLMUX30;
24665  volatile uint32_t GPLMUX31;
24666  volatile uint32_t GPLMUX32;
24667  volatile uint32_t GPLMUX33;
24668  volatile uint32_t GPLMUX34;
24669  volatile uint32_t GPLMUX35;
24670  volatile uint32_t GPLMUX36;
24671  volatile uint32_t GPLMUX37;
24672  volatile uint32_t GPLMUX38;
24673  volatile uint32_t GPLMUX39;
24674  volatile uint32_t GPLMUX40;
24675  volatile uint32_t GPLMUX41;
24676  volatile uint32_t GPLMUX42;
24677  volatile uint32_t GPLMUX43;
24678  volatile uint32_t GPLMUX44;
24679  volatile uint32_t GPLMUX45;
24680  volatile uint32_t GPLMUX46;
24681  volatile uint32_t GPLMUX47;
24682  volatile uint32_t GPLMUX48;
24683  volatile uint32_t GPLMUX49;
24684  volatile uint32_t GPLMUX50;
24685  volatile uint32_t GPLMUX51;
24686  volatile uint32_t GPLMUX52;
24687  volatile uint32_t GPLMUX53;
24688  volatile uint32_t GPLMUX54;
24689  volatile uint32_t GPLMUX55;
24690  volatile uint32_t GPLMUX56;
24691  volatile uint32_t GPLMUX57;
24692  volatile uint32_t GPLMUX58;
24693  volatile uint32_t GPLMUX59;
24694  volatile uint32_t GPLMUX60;
24695  volatile uint32_t GPLMUX61;
24696  volatile uint32_t GPLMUX62;
24697  volatile uint32_t GPLMUX63;
24698  volatile uint32_t GPLMUX64;
24699  volatile uint32_t GPLMUX65;
24700  volatile uint32_t GPLMUX66;
24701  volatile uint32_t GPLMUX67;
24702  volatile uint32_t GPLMUX68;
24703  volatile uint32_t GPLMUX69;
24704  volatile uint32_t GPLMUX70;
24705  volatile uint32_t NANDUSEFPGA;
24706  volatile uint32_t _pad_0x2f4_0x2f7;
24707  volatile uint32_t RGMII1USEFPGA;
24708  volatile uint32_t _pad_0x2fc_0x303[2];
24709  volatile uint32_t I2C0USEFPGA;
24710  volatile uint32_t _pad_0x308_0x313[3];
24711  volatile uint32_t RGMII0USEFPGA;
24712  volatile uint32_t _pad_0x318_0x323[3];
24713  volatile uint32_t I2C3USEFPGA;
24714  volatile uint32_t I2C2USEFPGA;
24715  volatile uint32_t I2C1USEFPGA;
24716  volatile uint32_t SPIM1USEFPGA;
24717  volatile uint32_t _pad_0x334_0x337;
24718  volatile uint32_t SPIM0USEFPGA;
24719  volatile uint32_t _pad_0x33c_0x400[49];
24720 };
24721 
24724 #endif /* __ASSEMBLY__ */
24725 
24727 #ifndef __ASSEMBLY__
24728 
24739 {
24742  volatile uint32_t _pad_0x8_0xf[2];
24749  volatile uint32_t _pad_0x34_0x3f[3];
24753  volatile uint32_t _pad_0x78_0x7f[2];
24755  volatile uint32_t _pad_0xa0_0xbf[8];
24758  volatile uint32_t _pad_0x104_0x107;
24762  volatile uint32_t _pad_0x11c_0x13f[9];
24764  volatile uint32_t _pad_0x180_0x3ff[160];
24766  volatile uint32_t _pad_0x800_0x4000[3584];
24767 };
24768 
24770 typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
24773 {
24774  volatile uint32_t siliconid1;
24775  volatile uint32_t siliconid2;
24776  volatile uint32_t _pad_0x8_0xf[2];
24777  volatile uint32_t wddbg;
24778  volatile uint32_t bootinfo;
24779  volatile uint32_t hpsinfo;
24780  volatile uint32_t parityinj;
24783  volatile uint32_t _pad_0x34_0x3f[3];
24787  volatile uint32_t _pad_0x78_0x7f[2];
24789  volatile uint32_t _pad_0xa0_0xbf[8];
24792  volatile uint32_t _pad_0x104_0x107;
24796  volatile uint32_t _pad_0x11c_0x13f[9];
24798  volatile uint32_t _pad_0x180_0x3ff[160];
24800  volatile uint32_t _pad_0x800_0x4000[3584];
24801 };
24802 
24804 typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
24805 #endif /* __ASSEMBLY__ */
24806 
24808 #ifdef __cplusplus
24809 }
24810 #endif /* __cplusplus */
24811 #endif /* __ALTERA_ALT_SYSMGR_H__ */
24812