Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Shadow RBR and THR - srbr_sthr_0

Description

This is multi-function register. It is shadow register for Receive Buffer Register and Transmit Holding Register.

Register Layout

Bits Access Reset Description
[7:0] R 0x0 ALT_UART_SRBR_SRBR_STHR_0
[31:8] R 0x0 ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8

Field : srbr_sthr_0

This is shadow register for RBR and THR and has been allocated sixteen 32-bit locations so as to accomodate burst accesses from the master.

srbr :

This register contains the data byte received on the serial input port (sin) in UART mode or the serial infrared input (sir_in) in infrared mode. The data in this register is valid only if the Data Ready (DR) bit in the Line status Register (LSR) is set. If in non-FIFO mode (FIFO_MODE == NONE) or FIFOs are disabled (FCR[0] set to zero), the data in the RBR must be read before the next data arrives, otherwise it is overwritten, resulting in an overrun error. If in FIFO mode (FIFO_MODE != NONE) and FIFOs are enabled (FCR[0] set to one), this register accesses the head of the receive FIFO. If the receive FIFO is full and this register is not read before the next data character arrives, then the data already in the FIFO are preserved, but any incoming data is lost. An overrun error also occurs.

sthr:

This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit (LSR[5]) is set. If in non-FIFO mode or FIFOs are disabled (FCR[0] set to zero) and THRE is set, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If in FIFO mode and FIFOs are enabled (FCR[0] set to one) and THRE is set, x number of characters of data may be written to the THR before the FIFO is full. The number x (default=16) is determined by the value of FIFO Depth that you set during configuration. Any attempt to write data when the FIFO is full results in the write data being lost.

Field Access Macros:

#define ALT_UART_SRBR_SRBR_STHR_0_LSB   0
 
#define ALT_UART_SRBR_SRBR_STHR_0_MSB   7
 
#define ALT_UART_SRBR_SRBR_STHR_0_WIDTH   8
 
#define ALT_UART_SRBR_SRBR_STHR_0_SET_MSK   0x000000ff
 
#define ALT_UART_SRBR_SRBR_STHR_0_CLR_MSK   0xffffff00
 
#define ALT_UART_SRBR_SRBR_STHR_0_RESET   0x0
 
#define ALT_UART_SRBR_SRBR_STHR_0_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_UART_SRBR_SRBR_STHR_0_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : rsvd_srbr_sthr_0_31to8

Reserved bits [31:8] - Read Only

Field Access Macros:

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_LSB   8
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_MSB   31
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_WIDTH   24
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET_MSK   0xffffff00
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_CLR_MSK   0x000000ff
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_RESET   0x0
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_GET(value)   (((value) & 0xffffff00) >> 8)
 
#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET(value)   (((value) << 8) & 0xffffff00)
 

Data Structures

struct  ALT_UART_SRBR_s
 

Macros

#define ALT_UART_SRBR_RESET   0x00000000
 
#define ALT_UART_SRBR_OFST   0x30
 
#define ALT_UART_SRBR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))
 

Typedefs

typedef struct ALT_UART_SRBR_s ALT_UART_SRBR_t
 

Data Structure Documentation

struct ALT_UART_SRBR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_SRBR.

Data Fields
const uint32_t srbr_sthr_0: 8 ALT_UART_SRBR_SRBR_STHR_0
const uint32_t rsvd_srbr_sthr_0_31to8: 24 ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8

Macro Definitions

#define ALT_UART_SRBR_SRBR_STHR_0_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_SRBR_SRBR_STHR_0 register field.

#define ALT_UART_SRBR_SRBR_STHR_0_MSB   7

The Most Significant Bit (MSB) position of the ALT_UART_SRBR_SRBR_STHR_0 register field.

#define ALT_UART_SRBR_SRBR_STHR_0_WIDTH   8

The width in bits of the ALT_UART_SRBR_SRBR_STHR_0 register field.

#define ALT_UART_SRBR_SRBR_STHR_0_SET_MSK   0x000000ff

The mask used to set the ALT_UART_SRBR_SRBR_STHR_0 register field value.

#define ALT_UART_SRBR_SRBR_STHR_0_CLR_MSK   0xffffff00

The mask used to clear the ALT_UART_SRBR_SRBR_STHR_0 register field value.

#define ALT_UART_SRBR_SRBR_STHR_0_RESET   0x0

The reset value of the ALT_UART_SRBR_SRBR_STHR_0 register field.

#define ALT_UART_SRBR_SRBR_STHR_0_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_UART_SRBR_SRBR_STHR_0 field value from a register.

#define ALT_UART_SRBR_SRBR_STHR_0_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_UART_SRBR_SRBR_STHR_0 register field value suitable for setting the register.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_LSB   8

The Least Significant Bit (LSB) position of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_MSB   31

The Most Significant Bit (MSB) position of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_WIDTH   24

The width in bits of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET_MSK   0xffffff00

The mask used to set the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_CLR_MSK   0x000000ff

The mask used to clear the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_RESET   0x0

The reset value of the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_GET (   value)    (((value) & 0xffffff00) >> 8)

Extracts the ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 field value from a register.

#define ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8_SET (   value)    (((value) << 8) & 0xffffff00)

Produces a ALT_UART_SRBR_RSVD_SRBR_STHR_0_31TO8 register field value suitable for setting the register.

#define ALT_UART_SRBR_RESET   0x00000000

The reset value of the ALT_UART_SRBR register.

#define ALT_UART_SRBR_OFST   0x30

The byte offset of the ALT_UART_SRBR register from the beginning of the component.

#define ALT_UART_SRBR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRBR_OFST))

The address of the ALT_UART_SRBR register.

Typedef Documentation

The typedef declaration for register ALT_UART_SRBR.