Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Status Register - miscstat

Description

The MISCSTAT register contains bits that indicate the timeout event. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset.

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s) de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0.

After a warm reset is complete, the bit(s) that indicate the source of the warm reset are set to 1. A warm reset doesn't clear any of the bits in the MISCSTAT register; these bits must be cleared by software writing the STAT register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 SDRAM Self-Refresh Timeout
[1] RW 0x0 FPGA manager handshake Timeout
[2] RW 0x0 FPGA handshake Timeout
[3] RW 0x0 ETR Stall Timeout
[31:4] ??? 0x0 UNDEFINED

Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout

A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_LSB   0
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_MSB   0
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_WIDTH   1
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET_MSK   0x00000001
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_RESET   0x0
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET(value)   (((value) << 0) & 0x00000001)
 

Field : FPGA manager handshake Timeout - fpgamgrhstimeout

A 1 indicates that Reset Manager's request to the FPGA manager to stop driving configuration clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_LSB   1
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_MSB   1
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_WIDTH   1
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET_MSK   0x00000002
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_RESET   0x0
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET(value)   (((value) << 1) & 0x00000002)
 

Field : FPGA handshake Timeout - fpgahstimeout

A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_LSB   2
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_MSB   2
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_WIDTH   1
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET_MSK   0x00000004
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_RESET   0x0
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET(value)   (((value) << 2) & 0x00000004)
 

Field : ETR Stall Timeout - etrstalltimeout

A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm reset timed- out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_LSB   3
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_MSB   3
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_WIDTH   1
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET_MSK   0x00000008
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_RESET   0x0
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET(value)   (((value) << 3) & 0x00000008)
 

Data Structures

struct  ALT_RSTMGR_MISCSTAT_s
 

Macros

#define ALT_RSTMGR_MISCSTAT_RESET   0x00000000
 
#define ALT_RSTMGR_MISCSTAT_OFST   0x8
 

Typedefs

typedef struct
ALT_RSTMGR_MISCSTAT_s 
ALT_RSTMGR_MISCSTAT_t
 

Data Structure Documentation

struct ALT_RSTMGR_MISCSTAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_MISCSTAT.

Data Fields
uint32_t sdrselfreftimeout: 1 SDRAM Self-Refresh Timeout
uint32_t fpgamgrhstimeout: 1 FPGA manager handshake Timeout
uint32_t fpgahstimeout: 1 FPGA handshake Timeout
uint32_t etrstalltimeout: 1 ETR Stall Timeout
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_RESET   0x0

The reset value of the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO field value from a register.

#define ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_MISCSTAT_SDRSELFREFTMO register field value suitable for setting the register.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_RESET   0x0

The reset value of the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO field value from a register.

#define ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_MISCSTAT_FPGAMGRHSTMO register field value suitable for setting the register.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_RESET   0x0

The reset value of the ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_MISCSTAT_FPGAHSTMO field value from a register.

#define ALT_RSTMGR_MISCSTAT_FPGAHSTMO_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_MISCSTAT_FPGAHSTMO register field value suitable for setting the register.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_RESET   0x0

The reset value of the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_MISCSTAT_ETRSTALLTMO field value from a register.

#define ALT_RSTMGR_MISCSTAT_ETRSTALLTMO_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_MISCSTAT_ETRSTALLTMO register field value suitable for setting the register.

#define ALT_RSTMGR_MISCSTAT_RESET   0x00000000

The reset value of the ALT_RSTMGR_MISCSTAT register.

#define ALT_RSTMGR_MISCSTAT_OFST   0x8

The byte offset of the ALT_RSTMGR_MISCSTAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_MISCSTAT.