Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 12 (LPI Control and Status Register) - LPI_Control_Status

Description

The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read.

Register Layout

Bits Access Reset Description
[0] R 0x0 Transmit LPI Entry
[1] R 0x0 Transmit LPI Exit
[2] R 0x0 Receive LPI Entry
[3] R 0x0 Receive LPI Exit
[7:4] ??? 0x0 UNDEFINED
[8] R 0x0 Transmit LPI State
[9] R 0x0 Receive LPI State
[15:10] ??? 0x0 UNDEFINED
[16] RW 0x0 LPI Enable
[17] RW 0x0 PHY Link Status
[18] RW 0x0 PHY Link Status Enable
[19] RW 0x0 LPI TX Automate
[31:20] ??? 0x0 UNDEFINED

Field : Transmit LPI Entry - tlpien

When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0 MAC Transmitter Not in LPI State
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1 MAC Transmitter Entered LPI State

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB   0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB   0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit LPI Exit - tlpiex

When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0 MAC Transmitter Non LPI State
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1 MAC Transmitter Exited LPI State

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Receive LPI Entry - rlpien

When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register.

Note:

This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of l3_sp_clk.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0 MAC Receiver Not In LPI State
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1 MAC Receiver In LPI State

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB   2
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB   2
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Receive LPI Exit - rlpiex

When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register.

Note:

This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of l3_sp_clk.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0 MAC RX receiving LPI Patterns
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1 MAC RX Stopped receiving LPI Patterns

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB   3
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB   3
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Transmit LPI State - tlpist

When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0 MAC Transmitting LPI Pattern
ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1 MAC Transmitting LPI Pattern

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB   8
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB   8
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Receive LPI State - rlpist

When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0 MAC is not receiving LPI Pattern
ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1 MAC receiving LPI Pattern

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB   9
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB   9
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value)   (((value) << 9) & 0x00000200)
 

Field : LPI Enable - lpien

When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission.

This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0 MAC Transmitter exit LPI State
ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1 MAC Transmitter enters LPI State

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB   16
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB   16
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value)   (((value) << 16) & 0x00010000)
 

Field : PHY Link Status - pls

This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER.

When set, the link is considered to be okay (up) and when reset, the link is considered to be down.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0 Link Down
ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1 Link Up (okay)

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB   17
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB   17
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK   0x00020000
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK   0xfffdffff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value)   (((value) << 17) & 0x00020000)
 

Field : PHY Link Status Enable - plsen

This bit enables the link status received on the RGMII receive paths to be used for activating the LPI LS TIMER.

When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0 MAC Ignores Link Status Bits
ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1 MAC Uses Link Status Bits

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB   18
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB   18
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value)   (((value) << 18) & 0x00040000)
 

Field : LPI TX Automate - lpitxa

This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode.

If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode.

When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0 LPI TX Automate Disabled
ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1 LPI TX Automate Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END   0x1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB   19
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB   19
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH   1
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value)   (((value) << 19) & 0x00080000)
 

Data Structures

struct  ALT_EMAC_GMAC_LPI_CTL_STAT_s
 

Macros

#define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST   0x30
 
#define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_LPI_CTL_STAT_s 
ALT_EMAC_GMAC_LPI_CTL_STAT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_LPI_CTL_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.

Data Fields
const uint32_t tlpien: 1 Transmit LPI Entry
const uint32_t tlpiex: 1 Transmit LPI Exit
const uint32_t rlpien: 1 Receive LPI Entry
const uint32_t rlpiex: 1 Receive LPI Exit
uint32_t __pad0__: 4 UNDEFINED
const uint32_t tlpist: 1 Transmit LPI State
const uint32_t rlpist: 1 Receive LPI State
uint32_t __pad1__: 6 UNDEFINED
uint32_t lpien: 1 LPI Enable
uint32_t pls: 1 PHY Link Status
uint32_t plsen: 1 PHY Link Status Enable
uint32_t lpitxa: 1 LPI TX Automate
uint32_t __pad2__: 12 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN

MAC Transmitter Not in LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN

MAC Transmitter Entered LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX

MAC Transmitter Non LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX

MAC Transmitter Exited LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN

MAC Receiver Not In LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN

MAC Receiver In LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX

MAC RX receiving LPI Patterns

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX

MAC RX Stopped receiving LPI Patterns

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST

MAC Transmitting LPI Pattern

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST

MAC Transmitting LPI Pattern

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST

MAC is not receiving LPI Pattern

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST

MAC receiving LPI Pattern

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN

MAC Transmitter exit LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN

MAC Transmitter enters LPI State

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS

Link Down

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS

Link Up (okay)

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK   0x00020000

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK   0xfffdffff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN

MAC Ignores Link Status Bits

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN

MAC Uses Link Status Bits

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA

LPI TX Automate Disabled

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA

LPI TX Automate Enabled

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST   0x30

The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component.

#define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST))

The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.