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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 8 (Missed Frame and Buffer Overflow Counter Register)
The DMA maintains two counters to track the number of frames missed during reception. This register reports the current value of the counter. The counter is used for diagnostic purposes. Bits[15:0] indicate missed frames because of the host buffer being unavailable. Bits[27:17] indicate missed frames because of buffer overflow conditions (MTL and MAC) and runt frames (good frames of less than 64 bytes) dropped by the MTL.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[15:0] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT |
[16] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF |
[27:17] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT |
[28] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF |
[31:29] | R | 0x0 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 |
Field : misfrmcnt | |
Missed Frame Counter This field indicates the number of frames missed by the controller because of the Host Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read with mci_be_i[0] at 1'b1. Field Access Macros: | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB 0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB 15 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH 16 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK 0x0000ffff |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK 0xffff0000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET 0x0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET(value) (((value) & 0x0000ffff) >> 0) |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET(value) (((value) << 0) & 0x0000ffff) |
Field : miscntovf | |
Overflow Bit for Missed Frame Counter This bit is set every time Missed Frame Counter (Bits[15:0]) overflows, that is, the DMA discards an incoming frame because of the Host Receive Buffer being unavailable with the missed frame counter at maximum value. In such a scenario, the Missed frame counter is reset to all-zeros and this bit indicates that the rollover happened. Field Access Macros: | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB 16 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB 16 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH 1 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK 0x00010000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET 0x0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET(value) (((value) << 16) & 0x00010000) |
Field : ovffrmcnt | |
Overflow Frame Counter This field indicates the number of frames missed by the application. This counter is incremented each time the MTL FIFO overflows. The counter is cleared when this register is read with mci_be_i[2] at 1'b1. Field Access Macros: | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB 17 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB 27 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH 11 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK 0x0ffe0000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK 0xf001ffff |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET 0x0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET(value) (((value) & 0x0ffe0000) >> 17) |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET(value) (((value) << 17) & 0x0ffe0000) |
Field : ovfcntovf | |
Overflow Bit for FIFO Overflow Counter This bit is set every time the Overflow Frame Counter (Bits[27:17]) overflows, that is, the Rx FIFO overflows with the overflow frame counter at maximum value. In such a scenario, the overflow frame counter is reset to all-zeros and this bit indicates that the rollover happened. Field Access Macros: | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB 28 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB 28 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH 1 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK 0x10000000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK 0xefffffff |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET 0x0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET(value) (((value) & 0x10000000) >> 28) |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET(value) (((value) << 28) & 0x10000000) |
Field : reserved_31_29 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_LSB 29 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_MSB 31 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_WIDTH 3 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET_MSK 0xe0000000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_CLR_MSK 0x1fffffff |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_RESET 0x0 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29) |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000) |
Data Structures | |
struct | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s |
Macros | |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RESET 0x00000000 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST 0x1020 |
#define | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t |
struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR.
Data Fields | ||
---|---|---|
const uint32_t | misfrmcnt: 16 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT |
const uint32_t | miscntovf: 1 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF |
const uint32_t | ovffrmcnt: 11 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT |
const uint32_t | ovfcntovf: 1 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF |
const uint32_t | reserved_31_29: 3 | ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 |
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_WIDTH 16 |
The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET_MSK 0x0000ffff |
The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_CLR_MSK 0xffff0000 |
The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_GET | ( | value | ) | (((value) & 0x0000ffff) >> 0) |
Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT field value from a register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT_SET | ( | value | ) | (((value) << 0) & 0x0000ffff) |
Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISFRMCNT register field value suitable for setting the register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF field value from a register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_MISCNTOVF register field value suitable for setting the register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_WIDTH 11 |
The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET_MSK 0x0ffe0000 |
The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_CLR_MSK 0xf001ffff |
The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_GET | ( | value | ) | (((value) & 0x0ffe0000) >> 17) |
Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT field value from a register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT_SET | ( | value | ) | (((value) << 17) & 0x0ffe0000) |
Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFFRMCNT register field value suitable for setting the register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET_MSK 0x10000000 |
The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_CLR_MSK 0xefffffff |
The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF field value from a register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OVFCNTOVF register field value suitable for setting the register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_WIDTH 3 |
The width in bits of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET_MSK 0xe0000000 |
The mask used to set the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_CLR_MSK 0x1fffffff |
The mask used to clear the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_GET | ( | value | ) | (((value) & 0xe0000000) >> 29) |
Extracts the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 field value from a register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29_SET | ( | value | ) | (((value) << 29) & 0xe0000000) |
Produces a ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RSVD_31_29 register field value suitable for setting the register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_RESET 0x00000000 |
The reset value of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST 0x1020 |
The byte offset of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register from the beginning of the component.
#define ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_OFST)) |
The address of the ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR register.
typedef struct ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_s ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR_t |
The typedef declaration for register ALT_EMAC_DMA_MFRM_BUF_OVF_CNTR.