Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : FIFO Control (when written) - fcr

Description

Controls FIFO Operations when written.

Register Layout

Bits Access Reset Description
[0] W Unknown FIFO Enable
[1] W Unknown Rx FIFO Reset
[2] W Unknown Tx FIFO Reset
[3] W Unknown DMA Mode
[5:4] W Unknown Tx Empty Trigger Level
[7:6] W Unknown Rx Trigger Level
[31:8] ??? 0x0 UNDEFINED

Field : FIFO Enable - fifoe

Enables/disables the transmit (Tx) and receive (Rx ) FIFO's. Whenever the value of this bit is changed both the Tx and Rx controller portion of FIFO's will be reset.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_FIFOE_E_DISD 0x0 FIFOs disabled
ALT_UART_FCR_FIFOE_E_END 0x1 FIFOs enabled

Field Access Macros:

#define ALT_UART_FCR_FIFOE_E_DISD   0x0
 
#define ALT_UART_FCR_FIFOE_E_END   0x1
 
#define ALT_UART_FCR_FIFOE_LSB   0
 
#define ALT_UART_FCR_FIFOE_MSB   0
 
#define ALT_UART_FCR_FIFOE_WIDTH   1
 
#define ALT_UART_FCR_FIFOE_SET_MSK   0x00000001
 
#define ALT_UART_FCR_FIFOE_CLR_MSK   0xfffffffe
 
#define ALT_UART_FCR_FIFOE_RESET   0x0
 
#define ALT_UART_FCR_FIFOE_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_UART_FCR_FIFOE_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Rx FIFO Reset - rfifor

Resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA Rxrequest and single signals. Note that this bit is self-clearing' and it is not necessary to clear this bit.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_RFIFOR_E_NORST 0x0 No Reset of Rx FIFO Control
ALT_UART_FCR_RFIFOR_E_RST 0x1 Resets of Rx FIFO Control

Field Access Macros:

#define ALT_UART_FCR_RFIFOR_E_NORST   0x0
 
#define ALT_UART_FCR_RFIFOR_E_RST   0x1
 
#define ALT_UART_FCR_RFIFOR_LSB   1
 
#define ALT_UART_FCR_RFIFOR_MSB   1
 
#define ALT_UART_FCR_RFIFOR_WIDTH   1
 
#define ALT_UART_FCR_RFIFOR_SET_MSK   0x00000002
 
#define ALT_UART_FCR_RFIFOR_CLR_MSK   0xfffffffd
 
#define ALT_UART_FCR_RFIFOR_RESET   0x0
 
#define ALT_UART_FCR_RFIFOR_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_UART_FCR_RFIFOR_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Tx FIFO Reset - xfifor

Resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA Tx request and single signals when additional DMA handshaking is used.

Note that this bit is 'self-clearing' and it is not necessary to clear this bit.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_XFIFOR_E_NORST 0x0 No Reset of Tx FIFO Control
ALT_UART_FCR_XFIFOR_E_RST 0x1 Resets Tx FIFO Control

Field Access Macros:

#define ALT_UART_FCR_XFIFOR_E_NORST   0x0
 
#define ALT_UART_FCR_XFIFOR_E_RST   0x1
 
#define ALT_UART_FCR_XFIFOR_LSB   2
 
#define ALT_UART_FCR_XFIFOR_MSB   2
 
#define ALT_UART_FCR_XFIFOR_WIDTH   1
 
#define ALT_UART_FCR_XFIFOR_SET_MSK   0x00000004
 
#define ALT_UART_FCR_XFIFOR_CLR_MSK   0xfffffffb
 
#define ALT_UART_FCR_XFIFOR_RESET   0x0
 
#define ALT_UART_FCR_XFIFOR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_UART_FCR_XFIFOR_SET(value)   (((value) << 2) & 0x00000004)
 

Field : DMA Mode - dmam

This determines the DMA signalling mode used for the uart_dma_tx_req_n and uart_dma_rx_req_n output signals when additional DMA handshaking signals are not selected. DMA mode 0 supports single DMA data transfers at a time. In mode 0, the uart_dma_tx_req_n signal goes active low under the following conditions:

  • When the Transmitter Holding Register is empty in non-FIFO mode.
  • When the transmitter FIFO is empty in FIFO mode with Programmable THRE interrupt mode disabled.
  • When the transmitter FIFO is at or below the programmed threshold with Programmable THRE interrupt mode enabled.

It goes inactive under the following conditions

  • When a single character has been written into the Transmitter Holding Register or transmitter FIFO with Programmable THRE interrupt mode disabled.
  • When the transmitter FIFO is above the threshold with Programmable THRE interrupt mode enabled.

DMA mode 1 supports multi-DMA data transfers, where multiple transfers are made continuously until the receiver FIFO has been emptied or the transmit FIFO has been filled. In mode 1 the uart_dma_tx_req_n signal is asserted under the following conditions:

  • When the transmitter FIFO is empty with Programmable THRE interrupt mode disabled.
  • When the transmitter FIFO is at or below the programmed threshold with Programmable THRE interrupt mode enabled.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_DMAM_E_SINGLE 0x0 Single DMA Transfer Mode
ALT_UART_FCR_DMAM_E_MULT 0x1 Multiple DMA Transfer Mode

Field Access Macros:

#define ALT_UART_FCR_DMAM_E_SINGLE   0x0
 
#define ALT_UART_FCR_DMAM_E_MULT   0x1
 
#define ALT_UART_FCR_DMAM_LSB   3
 
#define ALT_UART_FCR_DMAM_MSB   3
 
#define ALT_UART_FCR_DMAM_WIDTH   1
 
#define ALT_UART_FCR_DMAM_SET_MSK   0x00000008
 
#define ALT_UART_FCR_DMAM_CLR_MSK   0xfffffff7
 
#define ALT_UART_FCR_DMAM_RESET   0x0
 
#define ALT_UART_FCR_DMAM_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_UART_FCR_DMAM_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Tx Empty Trigger Level - tet

This is used to select the empty threshold level at which the THRE Interrupts will be generated when the mode is active. It also determines when the uart DMA transmit request signal uart_dma_tx_req_n will be asserted when in certain modes of operation.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_TET_E_FIFOEMPTY 0x0 FIFO empty
ALT_UART_FCR_TET_E_TWOCHARS 0x1 Two characters in FIFO
ALT_UART_FCR_TET_E_QUARTERFULL 0x2 FIFO 1/4 full
ALT_UART_FCR_TET_E_HALFFULL 0x3 FIFO 1/2 full

Field Access Macros:

#define ALT_UART_FCR_TET_E_FIFOEMPTY   0x0
 
#define ALT_UART_FCR_TET_E_TWOCHARS   0x1
 
#define ALT_UART_FCR_TET_E_QUARTERFULL   0x2
 
#define ALT_UART_FCR_TET_E_HALFFULL   0x3
 
#define ALT_UART_FCR_TET_LSB   4
 
#define ALT_UART_FCR_TET_MSB   5
 
#define ALT_UART_FCR_TET_WIDTH   2
 
#define ALT_UART_FCR_TET_SET_MSK   0x00000030
 
#define ALT_UART_FCR_TET_CLR_MSK   0xffffffcf
 
#define ALT_UART_FCR_TET_RESET   0x0
 
#define ALT_UART_FCR_TET_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_UART_FCR_TET_SET(value)   (((value) << 4) & 0x00000030)
 

Field : Rx Trigger Level - rt

This register is configured to implement FIFOs. Bits[7:6], Rx Trigger (or RT): This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the uart_rts_n signal will be de-asserted. It also determines when the uart_dma_rx_req_n signal will be asserted when in certain modes of operation.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_RT_E_ONECHAR 0x0 one character in fifo
ALT_UART_FCR_RT_E_QUARTERFULL 0x1 FIFO 1/4 full
ALT_UART_FCR_RT_E_HALFFULL 0x2 FIFO 1/2 full
ALT_UART_FCR_RT_E_FULLLESS2 0x3 FIFO 2 less than full

Field Access Macros:

#define ALT_UART_FCR_RT_E_ONECHAR   0x0
 
#define ALT_UART_FCR_RT_E_QUARTERFULL   0x1
 
#define ALT_UART_FCR_RT_E_HALFFULL   0x2
 
#define ALT_UART_FCR_RT_E_FULLLESS2   0x3
 
#define ALT_UART_FCR_RT_LSB   6
 
#define ALT_UART_FCR_RT_MSB   7
 
#define ALT_UART_FCR_RT_WIDTH   2
 
#define ALT_UART_FCR_RT_SET_MSK   0x000000c0
 
#define ALT_UART_FCR_RT_CLR_MSK   0xffffff3f
 
#define ALT_UART_FCR_RT_RESET   0x0
 
#define ALT_UART_FCR_RT_GET(value)   (((value) & 0x000000c0) >> 6)
 
#define ALT_UART_FCR_RT_SET(value)   (((value) << 6) & 0x000000c0)
 

Data Structures

struct  ALT_UART_FCR_s
 

Macros

#define ALT_UART_FCR_OFST   0x8
 
#define ALT_UART_FCR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))
 

Typedefs

typedef struct ALT_UART_FCR_s ALT_UART_FCR_t
 

Data Structure Documentation

struct ALT_UART_FCR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_FCR.

Data Fields
uint32_t fifoe: 1 FIFO Enable
uint32_t rfifor: 1 Rx FIFO Reset
uint32_t xfifor: 1 Tx FIFO Reset
uint32_t dmam: 1 DMA Mode
uint32_t tet: 2 Tx Empty Trigger Level
uint32_t rt: 2 Rx Trigger Level
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_UART_FCR_FIFOE_E_DISD   0x0

Enumerated value for register field ALT_UART_FCR_FIFOE

FIFOs disabled

#define ALT_UART_FCR_FIFOE_E_END   0x1

Enumerated value for register field ALT_UART_FCR_FIFOE

FIFOs enabled

#define ALT_UART_FCR_FIFOE_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_MSB   0

The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_WIDTH   1

The width in bits of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_SET_MSK   0x00000001

The mask used to set the ALT_UART_FCR_FIFOE register field value.

#define ALT_UART_FCR_FIFOE_CLR_MSK   0xfffffffe

The mask used to clear the ALT_UART_FCR_FIFOE register field value.

#define ALT_UART_FCR_FIFOE_RESET   0x0

The reset value of the ALT_UART_FCR_FIFOE register field is UNKNOWN.

#define ALT_UART_FCR_FIFOE_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_UART_FCR_FIFOE field value from a register.

#define ALT_UART_FCR_FIFOE_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register.

#define ALT_UART_FCR_RFIFOR_E_NORST   0x0

Enumerated value for register field ALT_UART_FCR_RFIFOR

No Reset of Rx FIFO Control

#define ALT_UART_FCR_RFIFOR_E_RST   0x1

Enumerated value for register field ALT_UART_FCR_RFIFOR

Resets of Rx FIFO Control

#define ALT_UART_FCR_RFIFOR_LSB   1

The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_MSB   1

The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_WIDTH   1

The width in bits of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_SET_MSK   0x00000002

The mask used to set the ALT_UART_FCR_RFIFOR register field value.

#define ALT_UART_FCR_RFIFOR_CLR_MSK   0xfffffffd

The mask used to clear the ALT_UART_FCR_RFIFOR register field value.

#define ALT_UART_FCR_RFIFOR_RESET   0x0

The reset value of the ALT_UART_FCR_RFIFOR register field is UNKNOWN.

#define ALT_UART_FCR_RFIFOR_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_UART_FCR_RFIFOR field value from a register.

#define ALT_UART_FCR_RFIFOR_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register.

#define ALT_UART_FCR_XFIFOR_E_NORST   0x0

Enumerated value for register field ALT_UART_FCR_XFIFOR

No Reset of Tx FIFO Control

#define ALT_UART_FCR_XFIFOR_E_RST   0x1

Enumerated value for register field ALT_UART_FCR_XFIFOR

Resets Tx FIFO Control

#define ALT_UART_FCR_XFIFOR_LSB   2

The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_MSB   2

The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_WIDTH   1

The width in bits of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_SET_MSK   0x00000004

The mask used to set the ALT_UART_FCR_XFIFOR register field value.

#define ALT_UART_FCR_XFIFOR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_UART_FCR_XFIFOR register field value.

#define ALT_UART_FCR_XFIFOR_RESET   0x0

The reset value of the ALT_UART_FCR_XFIFOR register field is UNKNOWN.

#define ALT_UART_FCR_XFIFOR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_UART_FCR_XFIFOR field value from a register.

#define ALT_UART_FCR_XFIFOR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register.

#define ALT_UART_FCR_DMAM_E_SINGLE   0x0

Enumerated value for register field ALT_UART_FCR_DMAM

Single DMA Transfer Mode

#define ALT_UART_FCR_DMAM_E_MULT   0x1

Enumerated value for register field ALT_UART_FCR_DMAM

Multiple DMA Transfer Mode

#define ALT_UART_FCR_DMAM_LSB   3

The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_MSB   3

The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_WIDTH   1

The width in bits of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_SET_MSK   0x00000008

The mask used to set the ALT_UART_FCR_DMAM register field value.

#define ALT_UART_FCR_DMAM_CLR_MSK   0xfffffff7

The mask used to clear the ALT_UART_FCR_DMAM register field value.

#define ALT_UART_FCR_DMAM_RESET   0x0

The reset value of the ALT_UART_FCR_DMAM register field is UNKNOWN.

#define ALT_UART_FCR_DMAM_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_UART_FCR_DMAM field value from a register.

#define ALT_UART_FCR_DMAM_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register.

#define ALT_UART_FCR_TET_E_FIFOEMPTY   0x0

Enumerated value for register field ALT_UART_FCR_TET

FIFO empty

#define ALT_UART_FCR_TET_E_TWOCHARS   0x1

Enumerated value for register field ALT_UART_FCR_TET

Two characters in FIFO

#define ALT_UART_FCR_TET_E_QUARTERFULL   0x2

Enumerated value for register field ALT_UART_FCR_TET

FIFO 1/4 full

#define ALT_UART_FCR_TET_E_HALFFULL   0x3

Enumerated value for register field ALT_UART_FCR_TET

FIFO 1/2 full

#define ALT_UART_FCR_TET_LSB   4

The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_MSB   5

The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_WIDTH   2

The width in bits of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_SET_MSK   0x00000030

The mask used to set the ALT_UART_FCR_TET register field value.

#define ALT_UART_FCR_TET_CLR_MSK   0xffffffcf

The mask used to clear the ALT_UART_FCR_TET register field value.

#define ALT_UART_FCR_TET_RESET   0x0

The reset value of the ALT_UART_FCR_TET register field is UNKNOWN.

#define ALT_UART_FCR_TET_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_UART_FCR_TET field value from a register.

#define ALT_UART_FCR_TET_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_UART_FCR_TET register field value suitable for setting the register.

#define ALT_UART_FCR_RT_E_ONECHAR   0x0

Enumerated value for register field ALT_UART_FCR_RT

one character in fifo

#define ALT_UART_FCR_RT_E_QUARTERFULL   0x1

Enumerated value for register field ALT_UART_FCR_RT

FIFO 1/4 full

#define ALT_UART_FCR_RT_E_HALFFULL   0x2

Enumerated value for register field ALT_UART_FCR_RT

FIFO 1/2 full

#define ALT_UART_FCR_RT_E_FULLLESS2   0x3

Enumerated value for register field ALT_UART_FCR_RT

FIFO 2 less than full

#define ALT_UART_FCR_RT_LSB   6

The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_MSB   7

The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_WIDTH   2

The width in bits of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_SET_MSK   0x000000c0

The mask used to set the ALT_UART_FCR_RT register field value.

#define ALT_UART_FCR_RT_CLR_MSK   0xffffff3f

The mask used to clear the ALT_UART_FCR_RT register field value.

#define ALT_UART_FCR_RT_RESET   0x0

The reset value of the ALT_UART_FCR_RT register field is UNKNOWN.

#define ALT_UART_FCR_RT_GET (   value)    (((value) & 0x000000c0) >> 6)

Extracts the ALT_UART_FCR_RT field value from a register.

#define ALT_UART_FCR_RT_SET (   value)    (((value) << 6) & 0x000000c0)

Produces a ALT_UART_FCR_RT register field value suitable for setting the register.

#define ALT_UART_FCR_OFST   0x8

The byte offset of the ALT_UART_FCR register from the beginning of the component.

#define ALT_UART_FCR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))

The address of the ALT_UART_FCR register.

Typedef Documentation

The typedef declaration for register ALT_UART_FCR.