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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Clears Master Region Enable field when written with 1
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN |
[1] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN |
[2] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN |
[3] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN |
[4] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN |
[5] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN |
[6] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN |
[7] | W | 0x0 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : hpsregion0enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion0enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001) |
Field : hpsregion1enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion1enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002) |
Field : hpsregion2enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion2enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004) |
Field : hpsregion3enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion3enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008) |
Field : hpsregion4enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion4enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010) |
Field : hpsregion5enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion5enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020) |
Field : hpsregion6enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion6enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040) |
Field : hpsregion7enable | |
HPS Region 0 Enable Clear. Writing zero has no effect Writing one will clear the hpsregion7enable bit to zero Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080) |
Data Structures | |
struct | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s |
Macros | |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000 |
#define | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8 |
Typedefs | |
typedef struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t |
struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_CLR.
Data Fields | ||
---|---|---|
uint32_t | hpsregion0enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN |
uint32_t | hpsregion1enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN |
uint32_t | hpsregion2enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN |
uint32_t | hpsregion3enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN |
uint32_t | hpsregion4enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN |
uint32_t | hpsregion5enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN |
uint32_t | hpsregion6enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN |
uint32_t | hpsregion7enable: 1 | ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR register.
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8 |
The byte offset of the ALT_NOC_FW_DDR_L3_SCR_EN_CLR register from the beginning of the component.
typedef struct ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t |
The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_EN_CLR.