Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Debug Trace Divide Register - tracediv

Description

Contains a field that controls the clock divider for the debug trace clock derived from the Main PLL

Only reset by a cold reset.

Register Layout

Bits Access Reset Description
[2:0] RW 0x0 Debug Trace Clock Divider
[31:3] ??? 0x0 UNDEFINED

Field : Debug Trace Clock Divider - traceclk

The dbg_trace_clk is divided down from the C2 output of the Main PLL by the value specified in this field.

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0 Divide By 1
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1 Divide By 2
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2 Divide By 4
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3 Divide By 8
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4 Divide By 16
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5 Reserved
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6 Reserved
ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7 Reserved

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1   0x0
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2   0x1
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4   0x2
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8   0x3
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16   0x4
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1   0x5
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2   0x6
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3   0x7
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB   0
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB   2
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH   3
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK   0x00000007
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK   0xfffffff8
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET   0x0
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value)   (((value) & 0x00000007) >> 0)
 
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value)   (((value) << 0) & 0x00000007)
 

Data Structures

struct  ALT_CLKMGR_MAINPLL_TRACEDIV_s
 

Macros

#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST   0x2c
 

Typedefs

typedef struct
ALT_CLKMGR_MAINPLL_TRACEDIV_s 
ALT_CLKMGR_MAINPLL_TRACEDIV_t
 

Data Structure Documentation

struct ALT_CLKMGR_MAINPLL_TRACEDIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV.

Data Fields
uint32_t traceclk: 3 Debug Trace Clock Divider
uint32_t __pad0__: 29 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1   0x0

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Divide By 1

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2   0x1

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Divide By 2

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4   0x2

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Divide By 4

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8   0x3

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Divide By 8

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16   0x4

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Divide By 16

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1   0x5

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Reserved

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2   0x6

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Reserved

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3   0x7

Enumerated value for register field ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK

Reserved

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB   2

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH   3

The width in bits of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK   0x00000007

The mask used to set the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK   0xfffffff8

The mask used to clear the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET   0x0

The reset value of the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET (   value)    (((value) & 0x00000007) >> 0)

Extracts the ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK field value from a register.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET (   value)    (((value) << 0) & 0x00000007)

Produces a ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST   0x2c

The byte offset of the ALT_CLKMGR_MAINPLL_TRACEDIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_MAINPLL_TRACEDIV.