Altera SoCAL  16.0
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alt_noc_fw_ddr_l3_scr.h
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32 
35 #ifndef __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
36 #define __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
82 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_LSB 0
83 
84 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_MSB 0
85 
86 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_WIDTH 1
87 
88 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET_MSK 0x00000001
89 
90 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_CLR_MSK 0xfffffffe
91 
92 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_RESET 0x0
93 
94 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
95 
96 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
97 
108 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_LSB 1
109 
110 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_MSB 1
111 
112 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_WIDTH 1
113 
114 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET_MSK 0x00000002
115 
116 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_CLR_MSK 0xfffffffd
117 
118 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_RESET 0x0
119 
120 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
121 
122 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
123 
134 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_LSB 2
135 
136 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_MSB 2
137 
138 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_WIDTH 1
139 
140 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET_MSK 0x00000004
141 
142 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_CLR_MSK 0xfffffffb
143 
144 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_RESET 0x0
145 
146 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
147 
148 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
149 
160 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_LSB 3
161 
162 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_MSB 3
163 
164 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_WIDTH 1
165 
166 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET_MSK 0x00000008
167 
168 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_CLR_MSK 0xfffffff7
169 
170 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_RESET 0x0
171 
172 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
173 
174 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
175 
186 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_LSB 4
187 
188 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_MSB 4
189 
190 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_WIDTH 1
191 
192 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET_MSK 0x00000010
193 
194 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_CLR_MSK 0xffffffef
195 
196 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_RESET 0x0
197 
198 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
199 
200 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
201 
212 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_LSB 5
213 
214 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_MSB 5
215 
216 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_WIDTH 1
217 
218 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET_MSK 0x00000020
219 
220 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_CLR_MSK 0xffffffdf
221 
222 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_RESET 0x0
223 
224 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
225 
226 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
227 
238 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_LSB 6
239 
240 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_MSB 6
241 
242 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_WIDTH 1
243 
244 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET_MSK 0x00000040
245 
246 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_CLR_MSK 0xffffffbf
247 
248 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_RESET 0x0
249 
250 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
251 
252 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
253 
264 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_LSB 7
265 
266 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_MSB 7
267 
268 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_WIDTH 1
269 
270 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET_MSK 0x00000080
271 
272 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_CLR_MSK 0xffffff7f
273 
274 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_RESET 0x0
275 
276 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
277 
278 #define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
279 
280 #ifndef __ASSEMBLY__
281 
292 {
293  uint32_t hpsregion0enable : 1;
294  uint32_t hpsregion1enable : 1;
295  uint32_t hpsregion2enable : 1;
296  uint32_t hpsregion3enable : 1;
297  uint32_t hpsregion4enable : 1;
298  uint32_t hpsregion5enable : 1;
299  uint32_t hpsregion6enable : 1;
300  uint32_t hpsregion7enable : 1;
301  uint32_t : 24;
302 };
303 
306 #endif /* __ASSEMBLY__ */
307 
309 #define ALT_NOC_FW_DDR_L3_SCR_EN_RESET 0x00000000
310 
311 #define ALT_NOC_FW_DDR_L3_SCR_EN_OFST 0x0
312 
346 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_LSB 0
347 
348 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_MSB 0
349 
350 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_WIDTH 1
351 
352 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET_MSK 0x00000001
353 
354 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_CLR_MSK 0xfffffffe
355 
356 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_RESET 0x0
357 
358 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
359 
360 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
361 
375 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_LSB 1
376 
377 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_MSB 1
378 
379 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_WIDTH 1
380 
381 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET_MSK 0x00000002
382 
383 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_CLR_MSK 0xfffffffd
384 
385 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_RESET 0x0
386 
387 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
388 
389 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
390 
404 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_LSB 2
405 
406 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_MSB 2
407 
408 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_WIDTH 1
409 
410 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET_MSK 0x00000004
411 
412 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_CLR_MSK 0xfffffffb
413 
414 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_RESET 0x0
415 
416 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
417 
418 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
419 
433 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_LSB 3
434 
435 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_MSB 3
436 
437 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_WIDTH 1
438 
439 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET_MSK 0x00000008
440 
441 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_CLR_MSK 0xfffffff7
442 
443 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_RESET 0x0
444 
445 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
446 
447 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
448 
462 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_LSB 4
463 
464 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_MSB 4
465 
466 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_WIDTH 1
467 
468 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET_MSK 0x00000010
469 
470 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_CLR_MSK 0xffffffef
471 
472 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_RESET 0x0
473 
474 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
475 
476 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
477 
491 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_LSB 5
492 
493 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_MSB 5
494 
495 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_WIDTH 1
496 
497 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET_MSK 0x00000020
498 
499 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_CLR_MSK 0xffffffdf
500 
501 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_RESET 0x0
502 
503 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
504 
505 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
506 
520 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_LSB 6
521 
522 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_MSB 6
523 
524 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_WIDTH 1
525 
526 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET_MSK 0x00000040
527 
528 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_CLR_MSK 0xffffffbf
529 
530 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_RESET 0x0
531 
532 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
533 
534 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
535 
549 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_LSB 7
550 
551 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_MSB 7
552 
553 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_WIDTH 1
554 
555 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET_MSK 0x00000080
556 
557 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_CLR_MSK 0xffffff7f
558 
559 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_RESET 0x0
560 
561 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
562 
563 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
564 
565 #ifndef __ASSEMBLY__
566 
577 {
578  uint32_t hpsregion0enable : 1;
579  uint32_t hpsregion1enable : 1;
580  uint32_t hpsregion2enable : 1;
581  uint32_t hpsregion3enable : 1;
582  uint32_t hpsregion4enable : 1;
583  uint32_t hpsregion5enable : 1;
584  uint32_t hpsregion6enable : 1;
585  uint32_t hpsregion7enable : 1;
586  uint32_t : 24;
587 };
588 
591 #endif /* __ASSEMBLY__ */
592 
594 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_RESET 0x00000000
595 
596 #define ALT_NOC_FW_DDR_L3_SCR_EN_SET_OFST 0x4
597 
631 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0
632 
633 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0
634 
635 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1
636 
637 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001
638 
639 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe
640 
641 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0
642 
643 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
644 
645 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
646 
660 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1
661 
662 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1
663 
664 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1
665 
666 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002
667 
668 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd
669 
670 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0
671 
672 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
673 
674 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
675 
689 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2
690 
691 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2
692 
693 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1
694 
695 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004
696 
697 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb
698 
699 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0
700 
701 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
702 
703 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
704 
718 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3
719 
720 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3
721 
722 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1
723 
724 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008
725 
726 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7
727 
728 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0
729 
730 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
731 
732 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
733 
747 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4
748 
749 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4
750 
751 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1
752 
753 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010
754 
755 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef
756 
757 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0
758 
759 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
760 
761 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
762 
776 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5
777 
778 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5
779 
780 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1
781 
782 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020
783 
784 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf
785 
786 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0
787 
788 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
789 
790 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
791 
805 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6
806 
807 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6
808 
809 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1
810 
811 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040
812 
813 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf
814 
815 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0
816 
817 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
818 
819 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
820 
834 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7
835 
836 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7
837 
838 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1
839 
840 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080
841 
842 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f
843 
844 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0
845 
846 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
847 
848 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
849 
850 #ifndef __ASSEMBLY__
851 
862 {
863  uint32_t hpsregion0enable : 1;
864  uint32_t hpsregion1enable : 1;
865  uint32_t hpsregion2enable : 1;
866  uint32_t hpsregion3enable : 1;
867  uint32_t hpsregion4enable : 1;
868  uint32_t hpsregion5enable : 1;
869  uint32_t hpsregion6enable : 1;
870  uint32_t hpsregion7enable : 1;
871  uint32_t : 24;
872 };
873 
876 #endif /* __ASSEMBLY__ */
877 
879 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000
880 
881 #define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8
882 
906 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_LSB 0
907 
908 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_MSB 15
909 
910 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_WIDTH 16
911 
912 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET_MSK 0x0000ffff
913 
914 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_CLR_MSK 0xffff0000
915 
916 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_RESET 0x0
917 
918 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
919 
920 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
921 
932 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_LSB 16
933 
934 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_MSB 31
935 
936 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_WIDTH 16
937 
938 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET_MSK 0xffff0000
939 
940 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
941 
942 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_RESET 0x0
943 
944 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
945 
946 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
947 
948 #ifndef __ASSEMBLY__
949 
960 {
961  uint32_t base : 16;
962  uint32_t limit : 16;
963 };
964 
967 #endif /* __ASSEMBLY__ */
968 
970 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_RESET 0x00000000
971 
972 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_OFST 0xc
973 
997 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_LSB 0
998 
999 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_MSB 15
1000 
1001 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_WIDTH 16
1002 
1003 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET_MSK 0x0000ffff
1004 
1005 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_CLR_MSK 0xffff0000
1006 
1007 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_RESET 0x0
1008 
1009 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1010 
1011 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1012 
1023 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_LSB 16
1024 
1025 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_MSB 31
1026 
1027 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_WIDTH 16
1028 
1029 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET_MSK 0xffff0000
1030 
1031 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1032 
1033 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_RESET 0x0
1034 
1035 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1036 
1037 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1038 
1039 #ifndef __ASSEMBLY__
1040 
1051 {
1052  uint32_t base : 16;
1053  uint32_t limit : 16;
1054 };
1055 
1058 #endif /* __ASSEMBLY__ */
1059 
1061 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_RESET 0x00000000
1062 
1063 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_OFST 0x10
1064 
1088 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_LSB 0
1089 
1090 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_MSB 15
1091 
1092 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_WIDTH 16
1093 
1094 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET_MSK 0x0000ffff
1095 
1096 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_CLR_MSK 0xffff0000
1097 
1098 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_RESET 0x0
1099 
1100 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1101 
1102 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1103 
1114 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_LSB 16
1115 
1116 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_MSB 31
1117 
1118 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_WIDTH 16
1119 
1120 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET_MSK 0xffff0000
1121 
1122 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1123 
1124 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_RESET 0x0
1125 
1126 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1127 
1128 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1129 
1130 #ifndef __ASSEMBLY__
1131 
1142 {
1143  uint32_t base : 16;
1144  uint32_t limit : 16;
1145 };
1146 
1149 #endif /* __ASSEMBLY__ */
1150 
1152 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_RESET 0x00000000
1153 
1154 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_OFST 0x14
1155 
1179 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_LSB 0
1180 
1181 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_MSB 15
1182 
1183 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_WIDTH 16
1184 
1185 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET_MSK 0x0000ffff
1186 
1187 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_CLR_MSK 0xffff0000
1188 
1189 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_RESET 0x0
1190 
1191 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1192 
1193 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1194 
1205 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_LSB 16
1206 
1207 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_MSB 31
1208 
1209 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_WIDTH 16
1210 
1211 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET_MSK 0xffff0000
1212 
1213 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1214 
1215 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_RESET 0x0
1216 
1217 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1218 
1219 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1220 
1221 #ifndef __ASSEMBLY__
1222 
1233 {
1234  uint32_t base : 16;
1235  uint32_t limit : 16;
1236 };
1237 
1240 #endif /* __ASSEMBLY__ */
1241 
1243 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_RESET 0x00000000
1244 
1245 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_OFST 0x18
1246 
1270 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0
1271 
1272 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15
1273 
1274 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16
1275 
1276 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff
1277 
1278 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000
1279 
1280 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0
1281 
1282 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1283 
1284 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1285 
1296 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16
1297 
1298 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31
1299 
1300 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16
1301 
1302 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000
1303 
1304 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff
1305 
1306 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0
1307 
1308 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1309 
1310 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1311 
1312 #ifndef __ASSEMBLY__
1313 
1324 {
1325  uint32_t base : 16;
1326  uint32_t limit : 16;
1327 };
1328 
1331 #endif /* __ASSEMBLY__ */
1332 
1334 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000
1335 
1336 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c
1337 
1361 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_LSB 0
1362 
1363 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_MSB 15
1364 
1365 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_WIDTH 16
1366 
1367 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET_MSK 0x0000ffff
1368 
1369 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_CLR_MSK 0xffff0000
1370 
1371 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_RESET 0x0
1372 
1373 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1374 
1375 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1376 
1387 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_LSB 16
1388 
1389 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_MSB 31
1390 
1391 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_WIDTH 16
1392 
1393 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET_MSK 0xffff0000
1394 
1395 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_CLR_MSK 0x0000ffff
1396 
1397 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_RESET 0x0
1398 
1399 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1400 
1401 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1402 
1403 #ifndef __ASSEMBLY__
1404 
1415 {
1416  uint32_t base : 16;
1417  uint32_t limit : 16;
1418 };
1419 
1422 #endif /* __ASSEMBLY__ */
1423 
1425 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_RESET 0x00000000
1426 
1427 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_OFST 0x20
1428 
1452 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_LSB 0
1453 
1454 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_MSB 15
1455 
1456 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_WIDTH 16
1457 
1458 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET_MSK 0x0000ffff
1459 
1460 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_CLR_MSK 0xffff0000
1461 
1462 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_RESET 0x0
1463 
1464 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1465 
1466 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1467 
1478 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_LSB 16
1479 
1480 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_MSB 31
1481 
1482 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_WIDTH 16
1483 
1484 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET_MSK 0xffff0000
1485 
1486 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_CLR_MSK 0x0000ffff
1487 
1488 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_RESET 0x0
1489 
1490 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1491 
1492 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1493 
1494 #ifndef __ASSEMBLY__
1495 
1506 {
1507  uint32_t base : 16;
1508  uint32_t limit : 16;
1509 };
1510 
1513 #endif /* __ASSEMBLY__ */
1514 
1516 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_RESET 0x00000000
1517 
1518 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_OFST 0x24
1519 
1543 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_LSB 0
1544 
1545 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_MSB 15
1546 
1547 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_WIDTH 16
1548 
1549 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET_MSK 0x0000ffff
1550 
1551 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_CLR_MSK 0xffff0000
1552 
1553 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_RESET 0x0
1554 
1555 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1556 
1557 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1558 
1569 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_LSB 16
1570 
1571 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_MSB 31
1572 
1573 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_WIDTH 16
1574 
1575 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET_MSK 0xffff0000
1576 
1577 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_CLR_MSK 0x0000ffff
1578 
1579 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_RESET 0x0
1580 
1581 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1582 
1583 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1584 
1585 #ifndef __ASSEMBLY__
1586 
1597 {
1598  uint32_t base : 16;
1599  uint32_t limit : 16;
1600 };
1601 
1604 #endif /* __ASSEMBLY__ */
1605 
1607 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_RESET 0x00000000
1608 
1609 #define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_OFST 0x28
1610 
1636 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_LSB 0
1637 
1638 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_MSB 0
1639 
1640 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_WIDTH 1
1641 
1642 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET_MSK 0x00000001
1643 
1644 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_CLR_MSK 0xfffffffe
1645 
1646 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_RESET 0x0
1647 
1648 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_GET(value) (((value) & 0x00000001) >> 0)
1649 
1650 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET(value) (((value) << 0) & 0x00000001)
1651 
1652 #ifndef __ASSEMBLY__
1653 
1664 {
1665  uint32_t error_response : 1;
1666  uint32_t : 31;
1667 };
1668 
1671 #endif /* __ASSEMBLY__ */
1672 
1674 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_RESET 0x00000000
1675 
1676 #define ALT_NOC_FW_DDR_L3_SCR_GLOB_OFST 0x2c
1677 
1678 #ifndef __ASSEMBLY__
1679 
1690 {
1703  volatile uint32_t _pad_0x30_0x100[52];
1704 };
1705 
1710 {
1711  volatile uint32_t enable;
1712  volatile uint32_t enable_set;
1713  volatile uint32_t enable_clear;
1714  volatile uint32_t hpsregion0addr;
1715  volatile uint32_t hpsregion1addr;
1716  volatile uint32_t hpsregion2addr;
1717  volatile uint32_t hpsregion3addr;
1718  volatile uint32_t hpsregion4addr;
1719  volatile uint32_t hpsregion5addr;
1720  volatile uint32_t hpsregion6addr;
1721  volatile uint32_t hpsregion7addr;
1722  volatile uint32_t global;
1723  volatile uint32_t _pad_0x30_0x100[52];
1724 };
1725 
1728 #endif /* __ASSEMBLY__ */
1729 
1731 #ifdef __cplusplus
1732 }
1733 #endif /* __cplusplus */
1734 #endif /* __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__ */
1735