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Altera HWLIB
16.0
The Altera HW Manager API Reference Manual
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This module defines an API for configuring and managing the Cortex-A9 MMU.
The APIs in this module are divided into two categories:
The functions in the low-level MMU API provide capabilities to:
The low-level API does not directly support any particular virtual address implementation model. Many features of the MMU hardware are oriented toward efficient implementation of protected virtual addressing in a multi-tasking operating system environment.
While the functions in the low-level MMU API could be used to facilitate a port to an operating system exploiting these MMU features, the API itself does not directly implement any particular virtual address implementation model or policy.
The other API does directly support a simplified virtual address space implementation model. This API provides a client facility to programmatically define a simplified virtual address space from a set of high level memory region configurations. The API also provides a convenient method to enable the virtual address space once it is defined.
For a complete understanding of the possible configurations and operation of the MMU, consult the following references:
Members | |
MMU Management | |
MMU Virtual Address Space Creation | |
MMU Virtual Address to Physical Address | |
Typedefs | |
typedef enum ALT_MMU_TTB_S_e | ALT_MMU_TTB_S_t |
typedef enum ALT_MMU_TTB_NS_e | ALT_MMU_TTB_NS_t |
typedef enum ALT_MMU_TTB_XN_e | ALT_MMU_TTB_XN_t |
typedef enum ALT_MMU_DAP_e | ALT_MMU_DAP_t |
typedef enum ALT_MMU_AP_e | ALT_MMU_AP_t |
typedef enum ALT_MMU_ATTR_e | ALT_MMU_ATTR_t |
typedef enum ALT_MMU_TTB_S_e ALT_MMU_TTB_S_t |
This type enumerates the options for Shareability (S) properties in translation table descriptors. This control determines whether the addressed region is Shareable memory or not.
The Shareability property (S bit):
typedef enum ALT_MMU_TTB_NS_e ALT_MMU_TTB_NS_t |
This type enumerates the options for Non-Secure (NS) controls in translation table descriptors. This control specifies whether memory accesses made from the secure state translate physical address in the secure or non-secure address map. The value of the NS bit in the first level page table descriptor applies to all entries in the corresponding second-level translation table.
typedef enum ALT_MMU_TTB_XN_e ALT_MMU_TTB_XN_t |
This type enumerates the options for Execute Never (XN) controls in translation table descriptors that determine whether the processor can execute instructions from the addressed region.
typedef enum ALT_MMU_DAP_e ALT_MMU_DAP_t |
This type enumerates the Domain Access Permission (DAP) options that can be set in the Domain Access Control Register (DACR).
typedef enum ALT_MMU_AP_e ALT_MMU_AP_t |
Typedef name for enum ALT_MMU_AP_e
typedef enum ALT_MMU_ATTR_e ALT_MMU_ATTR_t |
Typedef name for enum ALT_MMU_ATTR_e
enum ALT_MMU_TTB_S_e |
This type enumerates the options for Shareability (S) properties in translation table descriptors. This control determines whether the addressed region is Shareable memory or not.
The Shareability property (S bit):
enum ALT_MMU_TTB_NS_e |
This type enumerates the options for Non-Secure (NS) controls in translation table descriptors. This control specifies whether memory accesses made from the secure state translate physical address in the secure or non-secure address map. The value of the NS bit in the first level page table descriptor applies to all entries in the corresponding second-level translation table.
enum ALT_MMU_TTB_XN_e |
This type enumerates the options for Execute Never (XN) controls in translation table descriptors that determine whether the processor can execute instructions from the addressed region.
enum ALT_MMU_DAP_e |
This type enumerates the Domain Access Permission (DAP) options that can be set in the Domain Access Control Register (DACR).
enum ALT_MMU_AP_e |
This type enumerates the Access Permissions that can be specified for a memory region.
Memory access control is defined using access permission bits in translation table descriptors that control access to the corresponding memory region.
The HWLIB uses the short-descriptor translation table format for defining the access permissions where three bits, AP[2:0], define the access permissions. The SCTLR.AFE must be set to 0.
The following table provides a summary of the enumerations, AP bit encodings, and access permission descriptions for this type.
Enumeration | AP Value | Privileged (PL1) Access | User (PL0) Access | Description |
---|---|---|---|---|
ALT_MMU_AP_NO_ACCESS | 000 | No Access | No Access | No Access |
ALT_MMU_AP_PRIV_ACCESS | 001 | Read/Write | No Access | Privileged access only |
ALT_MMU_AP_USER_READ_ONLY | 010 | Read/Write | Read Only | Write in user mode generates a fault |
ALT_MMU_AP_FULL_ACCESS | 011 | Read/Write | Read/Write | Full Access |
N/A | 100 | Unknown | Unknown | Reserved |
ALT_MMU_AP_PRIV_READ_ONLY | 101 | Read Only | No Access | Privileged read only |
N/A | 110 | Read Only | Read Only | Read Only - deprecated |
ALT_MMU_AP_READ_ONLY | 111 | Read Only | Read Only | Read Only |
enum ALT_MMU_ATTR_e |
This type enumerates the Memory Region attributes that can be specifed in MMU translation table entries. Memory attributes determine the memory ordering and cache policies for inner/outer domains used for a particular range of memory.
Within the translation table entries, the memory region attributes are encoded using a combination of the descriptor entry data fields (TEX, C, B). Memory attribute settings also affect the meaning of other memory region properties such as shareability (S).
The tables below describe the available enumerations for specifying different memory region attributes and their affect on shareability.
The memory attributes enumerated here are meant to be used is a system where TEX remap is disabled (i.e. SCTLR.TRE is set to 0).
Enumeration | TEX | C | B | Description | Shareability |
---|---|---|---|---|---|
ALT_MMU_ATTR_STRONG | 000 | 0 | 0 | Strongly Ordered | Shareable |
ALT_MMU_ATTR_DEVICE | 000 | 0 | 1 | Device | Shareable |
ALT_MMU_ATTR_WT | 000 | 1 | 0 | Inner/Outer Write-Through, No Write Allocate | Determined by descriptor [S] bit |
ALT_MMU_ATTR_WB | 000 | 1 | 1 | Inner/Outer Write-Back, No Write Allocate | Determined by descriptor [S] bit |
ALT_MMU_ATTR_NC | 001 | 0 | 0 | Inner/Outer Non-Cacheable | Determined by descriptor [S] bit |
N/A | 001 | 0 | 1 | Reserved | Reserved |
N/A | 001 | 1 | 0 | Implementation Defined | - |
ALT_MMU_ATTR_WBA | 001 | 1 | 1 | Inner/Outer Write-Back, Write Allocate | Determined by descriptor [S] bit |
ALT_MMU_ATTR_DEVICE_NS | 010 | 0 | 0 | Device | Non-Shareable |
N/A | 010 | 0 | 1 | Reserved | Reserved |
N/A | 010 | 1 | 0 | Reserved | Reserved |
N/A | 010 | 1 | 1 | Reserved | Reserved |
ALT_MMU_ATTR_AA_BB | 1BB | A | A | Cached where AA = Inner Policy, BB = Outer Policy | Determined by descriptor [S] bit |
Cache Policy Encoding for AA, BB
Mnemonic Encoding | Bit Encoding | Cache Policy |
---|---|---|
NC | 00 | Non-Cacheable |
WBA | 01 | Write-Back, Write Allocate |
WT | 10 | Write-Through, No Write Allocate |
WB | 11 | Write-Back, No Write Allocate |