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alt_spis.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALTERA_ALT_SPIS_H__
36
#define __ALTERA_ALT_SPIS_H__
37
38
#ifdef __cplusplus
39
extern
"C"
40
{
41
#endif
/* __cplusplus */
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101
#define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
102
107
#define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
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#define ALT_SPIS_CTLR0_DFS_LSB 0
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#define ALT_SPIS_CTLR0_DFS_MSB 3
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#define ALT_SPIS_CTLR0_DFS_WIDTH 4
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#define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
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#define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
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#define ALT_SPIS_CTLR0_DFS_RESET 0x7
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#define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
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#define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
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177
#define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
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#define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
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#define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
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#define ALT_SPIS_CTLR0_FRF_LSB 4
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#define ALT_SPIS_CTLR0_FRF_MSB 5
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#define ALT_SPIS_CTLR0_FRF_WIDTH 2
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#define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
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#define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
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#define ALT_SPIS_CTLR0_FRF_RESET 0x0
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#define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
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#define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
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232
#define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
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#define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
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#define ALT_SPIS_CTLR0_SCPH_LSB 6
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#define ALT_SPIS_CTLR0_SCPH_MSB 6
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#define ALT_SPIS_CTLR0_SCPH_WIDTH 1
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#define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
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#define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
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#define ALT_SPIS_CTLR0_SCPH_RESET 0x0
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#define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
256
279
#define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
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#define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
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#define ALT_SPIS_CTLR0_SCPOL_LSB 7
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#define ALT_SPIS_CTLR0_SCPOL_MSB 7
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#define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
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#define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
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#define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
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#define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
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#define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
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#define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
340
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#define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
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#define ALT_SPIS_CTLR0_TMOD_LSB 8
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#define ALT_SPIS_CTLR0_TMOD_MSB 9
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#define ALT_SPIS_CTLR0_TMOD_WIDTH 2
353
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#define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
355
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#define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
357
358
#define ALT_SPIS_CTLR0_TMOD_RESET 0x0
359
360
#define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
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#define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
363
392
#define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
393
398
#define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
399
401
#define ALT_SPIS_CTLR0_SLV_OE_LSB 10
402
403
#define ALT_SPIS_CTLR0_SLV_OE_MSB 10
404
405
#define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
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#define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
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#define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
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#define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
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413
#define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
414
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#define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
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#define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
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#define ALT_SPIS_CTLR0_SRL_LSB 11
448
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#define ALT_SPIS_CTLR0_SRL_MSB 11
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#define ALT_SPIS_CTLR0_SRL_WIDTH 1
452
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#define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
454
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#define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
456
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#define ALT_SPIS_CTLR0_SRL_RESET 0x0
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#define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
460
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#define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
462
473
#define ALT_SPIS_CTLR0_CFS_LSB 12
474
475
#define ALT_SPIS_CTLR0_CFS_MSB 15
476
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#define ALT_SPIS_CTLR0_CFS_WIDTH 4
478
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#define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
480
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#define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
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#define ALT_SPIS_CTLR0_CFS_RESET 0x0
484
485
#define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
486
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#define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
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#ifndef __ASSEMBLY__
490
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struct
ALT_SPIS_CTLR0_s
501
{
502
uint32_t
dfs
: 4;
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uint32_t
frf
: 2;
504
uint32_t
scph
: 1;
505
uint32_t
scpol
: 1;
506
uint32_t
tmod
: 2;
507
uint32_t
slv_oe
: 1;
508
uint32_t
srl
: 1;
509
uint32_t
cfs
: 4;
510
uint32_t : 16;
511
};
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typedef
volatile
struct
ALT_SPIS_CTLR0_s
ALT_SPIS_CTLR0_t
;
515
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIS_CTLR0_OFST 0x0
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#define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
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#define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
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#define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
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#define ALT_SPIS_SPIENR_SPI_EN_LSB 0
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#define ALT_SPIS_SPIENR_SPI_EN_MSB 0
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#define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
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#define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
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#define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
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#define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
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#define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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struct
ALT_SPIS_SPIENR_s
594
{
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uint32_t
spi_en
: 1;
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uint32_t : 31;
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};
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typedef
volatile
struct
ALT_SPIS_SPIENR_s
ALT_SPIS_SPIENR_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_SPIS_SPIENR_OFST 0x8
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#define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
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#define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
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#define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
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#define ALT_SPIS_MWCR_MWMOD_LSB 0
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#define ALT_SPIS_MWCR_MWMOD_MSB 0
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#define ALT_SPIS_MWCR_MWMOD_WIDTH 1
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#define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
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#define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
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#define ALT_SPIS_MWCR_MWMOD_RESET 0x0
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#define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
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#define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
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#define ALT_SPIS_MWCR_MDD_LSB 1
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#define ALT_SPIS_MWCR_MDD_MSB 1
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#define ALT_SPIS_MWCR_MDD_WIDTH 1
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#define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
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#define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
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#define ALT_SPIS_MWCR_MDD_RESET 0x0
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#define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
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#ifndef __ASSEMBLY__
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struct
ALT_SPIS_MWCR_s
731
{
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uint32_t
mwmod
: 1;
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uint32_t
mdd
: 1;
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uint32_t : 30;
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};
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typedef
volatile
struct
ALT_SPIS_MWCR_s
ALT_SPIS_MWCR_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_SPIS_MWCR_OFST 0xc
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#define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
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#define ALT_SPIS_TXFTLR_TFT_LSB 0
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#define ALT_SPIS_TXFTLR_TFT_MSB 7
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#define ALT_SPIS_TXFTLR_TFT_WIDTH 8
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#define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
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#define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
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#define ALT_SPIS_TXFTLR_TFT_RESET 0x0
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#define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
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#define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
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#ifndef __ASSEMBLY__
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struct
ALT_SPIS_TXFTLR_s
800
{
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uint32_t
tft
: 8;
802
uint32_t : 24;
803
};
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typedef
volatile
struct
ALT_SPIS_TXFTLR_s
ALT_SPIS_TXFTLR_t
;
807
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIS_TXFTLR_OFST 0x18
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#define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
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#define ALT_SPIS_RXFTLR_RFT_LSB 0
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#define ALT_SPIS_RXFTLR_RFT_MSB 7
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#define ALT_SPIS_RXFTLR_RFT_WIDTH 8
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#define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
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#define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
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#define ALT_SPIS_RXFTLR_RFT_RESET 0x0
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#define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
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#define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
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#ifndef __ASSEMBLY__
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867
struct
ALT_SPIS_RXFTLR_s
868
{
869
uint32_t
rft
: 8;
870
uint32_t : 24;
871
};
872
874
typedef
volatile
struct
ALT_SPIS_RXFTLR_s
ALT_SPIS_RXFTLR_t
;
875
#endif
/* __ASSEMBLY__ */
876
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#define ALT_SPIS_RXFTLR_OFST 0x1c
879
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#define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
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#define ALT_SPIS_TXFLR_TXTFL_LSB 0
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#define ALT_SPIS_TXFLR_TXTFL_MSB 8
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#define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
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911
#define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
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#define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
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915
#define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
916
917
#define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
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919
#define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
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921
#ifndef __ASSEMBLY__
922
932
struct
ALT_SPIS_TXFLR_s
933
{
934
const
uint32_t
txtfl
: 9;
935
uint32_t : 23;
936
};
937
939
typedef
volatile
struct
ALT_SPIS_TXFLR_s
ALT_SPIS_TXFLR_t
;
940
#endif
/* __ASSEMBLY__ */
941
943
#define ALT_SPIS_TXFLR_OFST 0x20
944
945
#define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
946
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#define ALT_SPIS_RXFLR_RXTFL_LSB 0
971
972
#define ALT_SPIS_RXFLR_RXTFL_MSB 8
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#define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
975
976
#define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
977
978
#define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
979
980
#define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
981
982
#define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
983
984
#define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
985
986
#ifndef __ASSEMBLY__
987
997
struct
ALT_SPIS_RXFLR_s
998
{
999
const
uint32_t
rxtfl
: 9;
1000
uint32_t : 23;
1001
};
1002
1004
typedef
volatile
struct
ALT_SPIS_RXFLR_s
ALT_SPIS_RXFLR_t
;
1005
#endif
/* __ASSEMBLY__ */
1006
1008
#define ALT_SPIS_RXFLR_OFST 0x24
1009
1010
#define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1011
1052
#define ALT_SPIS_SR_BUSY_E_INACT 0x0
1053
1058
#define ALT_SPIS_SR_BUSY_E_ACT 0x1
1059
1061
#define ALT_SPIS_SR_BUSY_LSB 0
1062
1063
#define ALT_SPIS_SR_BUSY_MSB 0
1064
1065
#define ALT_SPIS_SR_BUSY_WIDTH 1
1066
1067
#define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1068
1069
#define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1070
1071
#define ALT_SPIS_SR_BUSY_RESET 0x0
1072
1073
#define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1074
1075
#define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1076
1097
#define ALT_SPIS_SR_TFNF_E_FULL 0x0
1098
1103
#define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1104
1106
#define ALT_SPIS_SR_TFNF_LSB 1
1107
1108
#define ALT_SPIS_SR_TFNF_MSB 1
1109
1110
#define ALT_SPIS_SR_TFNF_WIDTH 1
1111
1112
#define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1113
1114
#define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1115
1116
#define ALT_SPIS_SR_TFNF_RESET 0x1
1117
1118
#define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1119
1120
#define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1121
1143
#define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1144
1149
#define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1150
1152
#define ALT_SPIS_SR_TFE_LSB 2
1153
1154
#define ALT_SPIS_SR_TFE_MSB 2
1155
1156
#define ALT_SPIS_SR_TFE_WIDTH 1
1157
1158
#define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1159
1160
#define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1161
1162
#define ALT_SPIS_SR_TFE_RESET 0x1
1163
1164
#define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1165
1166
#define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1167
1188
#define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1189
1194
#define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1195
1197
#define ALT_SPIS_SR_RFNE_LSB 3
1198
1199
#define ALT_SPIS_SR_RFNE_MSB 3
1200
1201
#define ALT_SPIS_SR_RFNE_WIDTH 1
1202
1203
#define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1204
1205
#define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1206
1207
#define ALT_SPIS_SR_RFNE_RESET 0x0
1208
1209
#define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1210
1211
#define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1212
1233
#define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1234
1239
#define ALT_SPIS_SR_RFF_E_FULL 0x1
1240
1242
#define ALT_SPIS_SR_RFF_LSB 4
1243
1244
#define ALT_SPIS_SR_RFF_MSB 4
1245
1246
#define ALT_SPIS_SR_RFF_WIDTH 1
1247
1248
#define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1249
1250
#define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1251
1252
#define ALT_SPIS_SR_RFF_RESET 0x0
1253
1254
#define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1255
1256
#define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1257
1279
#define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1280
1285
#define ALT_SPIS_SR_TXE_E_ERROR 0x1
1286
1288
#define ALT_SPIS_SR_TXE_LSB 5
1289
1290
#define ALT_SPIS_SR_TXE_MSB 5
1291
1292
#define ALT_SPIS_SR_TXE_WIDTH 1
1293
1294
#define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1295
1296
#define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1297
1298
#define ALT_SPIS_SR_TXE_RESET 0x0
1299
1300
#define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1301
1302
#define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1303
1304
#ifndef __ASSEMBLY__
1305
1315
struct
ALT_SPIS_SR_s
1316
{
1317
const
uint32_t
busy
: 1;
1318
const
uint32_t
tfnf
: 1;
1319
const
uint32_t
tfe
: 1;
1320
const
uint32_t
rfne
: 1;
1321
const
uint32_t
rff
: 1;
1322
const
uint32_t
txe
: 1;
1323
uint32_t : 26;
1324
};
1325
1327
typedef
volatile
struct
ALT_SPIS_SR_s
ALT_SPIS_SR_t
;
1328
#endif
/* __ASSEMBLY__ */
1329
1331
#define ALT_SPIS_SR_OFST 0x28
1332
1333
#define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1334
1372
#define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1373
1378
#define ALT_SPIS_IMR_TXEIM_E_END 0x1
1379
1381
#define ALT_SPIS_IMR_TXEIM_LSB 0
1382
1383
#define ALT_SPIS_IMR_TXEIM_MSB 0
1384
1385
#define ALT_SPIS_IMR_TXEIM_WIDTH 1
1386
1387
#define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1388
1389
#define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1390
1391
#define ALT_SPIS_IMR_TXEIM_RESET 0x1
1392
1393
#define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1394
1395
#define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1396
1417
#define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1418
1423
#define ALT_SPIS_IMR_TXOIM_E_END 0x1
1424
1426
#define ALT_SPIS_IMR_TXOIM_LSB 1
1427
1428
#define ALT_SPIS_IMR_TXOIM_MSB 1
1429
1430
#define ALT_SPIS_IMR_TXOIM_WIDTH 1
1431
1432
#define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1433
1434
#define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1435
1436
#define ALT_SPIS_IMR_TXOIM_RESET 0x1
1437
1438
#define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1439
1440
#define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1441
1462
#define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1463
1468
#define ALT_SPIS_IMR_RXUIM_E_END 0x1
1469
1471
#define ALT_SPIS_IMR_RXUIM_LSB 2
1472
1473
#define ALT_SPIS_IMR_RXUIM_MSB 2
1474
1475
#define ALT_SPIS_IMR_RXUIM_WIDTH 1
1476
1477
#define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1478
1479
#define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1480
1481
#define ALT_SPIS_IMR_RXUIM_RESET 0x1
1482
1483
#define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1484
1485
#define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1486
1507
#define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1508
1513
#define ALT_SPIS_IMR_RXOIM_E_END 0x1
1514
1516
#define ALT_SPIS_IMR_RXOIM_LSB 3
1517
1518
#define ALT_SPIS_IMR_RXOIM_MSB 3
1519
1520
#define ALT_SPIS_IMR_RXOIM_WIDTH 1
1521
1522
#define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1523
1524
#define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1525
1526
#define ALT_SPIS_IMR_RXOIM_RESET 0x1
1527
1528
#define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1529
1530
#define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1531
1552
#define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1553
1558
#define ALT_SPIS_IMR_RXFIM_E_END 0x1
1559
1561
#define ALT_SPIS_IMR_RXFIM_LSB 4
1562
1563
#define ALT_SPIS_IMR_RXFIM_MSB 4
1564
1565
#define ALT_SPIS_IMR_RXFIM_WIDTH 1
1566
1567
#define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1568
1569
#define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1570
1571
#define ALT_SPIS_IMR_RXFIM_RESET 0x1
1572
1573
#define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1574
1575
#define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1576
1577
#ifndef __ASSEMBLY__
1578
1588
struct
ALT_SPIS_IMR_s
1589
{
1590
uint32_t
txeim
: 1;
1591
uint32_t
txoim
: 1;
1592
uint32_t
rxuim
: 1;
1593
uint32_t
rxoim
: 1;
1594
uint32_t
rxfim
: 1;
1595
uint32_t : 27;
1596
};
1597
1599
typedef
volatile
struct
ALT_SPIS_IMR_s
ALT_SPIS_IMR_t
;
1600
#endif
/* __ASSEMBLY__ */
1601
1603
#define ALT_SPIS_IMR_OFST 0x2c
1604
1605
#define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
1606
1646
#define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
1647
1652
#define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
1653
1655
#define ALT_SPIS_ISR_TXEIS_LSB 0
1656
1657
#define ALT_SPIS_ISR_TXEIS_MSB 0
1658
1659
#define ALT_SPIS_ISR_TXEIS_WIDTH 1
1660
1661
#define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
1662
1663
#define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
1664
1665
#define ALT_SPIS_ISR_TXEIS_RESET 0x0
1666
1667
#define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
1668
1669
#define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
1670
1692
#define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
1693
1698
#define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
1699
1701
#define ALT_SPIS_ISR_TXOIS_LSB 1
1702
1703
#define ALT_SPIS_ISR_TXOIS_MSB 1
1704
1705
#define ALT_SPIS_ISR_TXOIS_WIDTH 1
1706
1707
#define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
1708
1709
#define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
1710
1711
#define ALT_SPIS_ISR_TXOIS_RESET 0x0
1712
1713
#define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
1714
1715
#define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
1716
1738
#define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
1739
1744
#define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
1745
1747
#define ALT_SPIS_ISR_RXUIS_LSB 2
1748
1749
#define ALT_SPIS_ISR_RXUIS_MSB 2
1750
1751
#define ALT_SPIS_ISR_RXUIS_WIDTH 1
1752
1753
#define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
1754
1755
#define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
1756
1757
#define ALT_SPIS_ISR_RXUIS_RESET 0x0
1758
1759
#define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
1760
1761
#define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
1762
1784
#define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
1785
1790
#define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
1791
1793
#define ALT_SPIS_ISR_RXOIS_LSB 3
1794
1795
#define ALT_SPIS_ISR_RXOIS_MSB 3
1796
1797
#define ALT_SPIS_ISR_RXOIS_WIDTH 1
1798
1799
#define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
1800
1801
#define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
1802
1803
#define ALT_SPIS_ISR_RXOIS_RESET 0x0
1804
1805
#define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
1806
1807
#define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
1808
1830
#define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
1831
1836
#define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
1837
1839
#define ALT_SPIS_ISR_RXFIS_LSB 4
1840
1841
#define ALT_SPIS_ISR_RXFIS_MSB 4
1842
1843
#define ALT_SPIS_ISR_RXFIS_WIDTH 1
1844
1845
#define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
1846
1847
#define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
1848
1849
#define ALT_SPIS_ISR_RXFIS_RESET 0x0
1850
1851
#define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
1852
1853
#define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
1854
1855
#ifndef __ASSEMBLY__
1856
1866
struct
ALT_SPIS_ISR_s
1867
{
1868
const
uint32_t
txeis
: 1;
1869
const
uint32_t
txois
: 1;
1870
const
uint32_t
rxuis
: 1;
1871
const
uint32_t
rxois
: 1;
1872
const
uint32_t
rxfis
: 1;
1873
uint32_t : 27;
1874
};
1875
1877
typedef
volatile
struct
ALT_SPIS_ISR_s
ALT_SPIS_ISR_t
;
1878
#endif
/* __ASSEMBLY__ */
1879
1881
#define ALT_SPIS_ISR_OFST 0x30
1882
1883
#define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
1884
1923
#define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
1924
1929
#define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
1930
1932
#define ALT_SPIS_RISR_TXEIR_LSB 0
1933
1934
#define ALT_SPIS_RISR_TXEIR_MSB 0
1935
1936
#define ALT_SPIS_RISR_TXEIR_WIDTH 1
1937
1938
#define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
1939
1940
#define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
1941
1942
#define ALT_SPIS_RISR_TXEIR_RESET 0x0
1943
1944
#define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
1945
1946
#define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
1947
1969
#define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
1970
1975
#define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
1976
1978
#define ALT_SPIS_RISR_TXOIR_LSB 1
1979
1980
#define ALT_SPIS_RISR_TXOIR_MSB 1
1981
1982
#define ALT_SPIS_RISR_TXOIR_WIDTH 1
1983
1984
#define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
1985
1986
#define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
1987
1988
#define ALT_SPIS_RISR_TXOIR_RESET 0x0
1989
1990
#define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
1991
1992
#define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
1993
2016
#define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2017
2022
#define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2023
2025
#define ALT_SPIS_RISR_RXUIR_LSB 2
2026
2027
#define ALT_SPIS_RISR_RXUIR_MSB 2
2028
2029
#define ALT_SPIS_RISR_RXUIR_WIDTH 1
2030
2031
#define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2032
2033
#define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2034
2035
#define ALT_SPIS_RISR_RXUIR_RESET 0x0
2036
2037
#define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2038
2039
#define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2040
2062
#define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2063
2068
#define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2069
2071
#define ALT_SPIS_RISR_RXOIR_LSB 3
2072
2073
#define ALT_SPIS_RISR_RXOIR_MSB 3
2074
2075
#define ALT_SPIS_RISR_RXOIR_WIDTH 1
2076
2077
#define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2078
2079
#define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2080
2081
#define ALT_SPIS_RISR_RXOIR_RESET 0x0
2082
2083
#define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2084
2085
#define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2086
2109
#define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2110
2115
#define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2116
2118
#define ALT_SPIS_RISR_RXFIR_LSB 4
2119
2120
#define ALT_SPIS_RISR_RXFIR_MSB 4
2121
2122
#define ALT_SPIS_RISR_RXFIR_WIDTH 1
2123
2124
#define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2125
2126
#define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2127
2128
#define ALT_SPIS_RISR_RXFIR_RESET 0x0
2129
2130
#define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2131
2132
#define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2133
2134
#ifndef __ASSEMBLY__
2135
2145
struct
ALT_SPIS_RISR_s
2146
{
2147
const
uint32_t
txeir
: 1;
2148
const
uint32_t
txoir
: 1;
2149
const
uint32_t
rxuir
: 1;
2150
const
uint32_t
rxoir
: 1;
2151
const
uint32_t
rxfir
: 1;
2152
uint32_t : 27;
2153
};
2154
2156
typedef
volatile
struct
ALT_SPIS_RISR_s
ALT_SPIS_RISR_t
;
2157
#endif
/* __ASSEMBLY__ */
2158
2160
#define ALT_SPIS_RISR_OFST 0x34
2161
2162
#define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2163
2185
#define ALT_SPIS_TXOICR_TXOICR_LSB 0
2186
2187
#define ALT_SPIS_TXOICR_TXOICR_MSB 0
2188
2189
#define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2190
2191
#define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2192
2193
#define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2194
2195
#define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2196
2197
#define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2198
2199
#define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2200
2201
#ifndef __ASSEMBLY__
2202
2212
struct
ALT_SPIS_TXOICR_s
2213
{
2214
const
uint32_t
txoicr
: 1;
2215
uint32_t : 31;
2216
};
2217
2219
typedef
volatile
struct
ALT_SPIS_TXOICR_s
ALT_SPIS_TXOICR_t
;
2220
#endif
/* __ASSEMBLY__ */
2221
2223
#define ALT_SPIS_TXOICR_OFST 0x38
2224
2225
#define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2226
2248
#define ALT_SPIS_RXOICR_RXOICR_LSB 0
2249
2250
#define ALT_SPIS_RXOICR_RXOICR_MSB 0
2251
2252
#define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2253
2254
#define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2255
2256
#define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2257
2258
#define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2259
2260
#define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2261
2262
#define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2263
2264
#ifndef __ASSEMBLY__
2265
2275
struct
ALT_SPIS_RXOICR_s
2276
{
2277
const
uint32_t
rxoicr
: 1;
2278
uint32_t : 31;
2279
};
2280
2282
typedef
volatile
struct
ALT_SPIS_RXOICR_s
ALT_SPIS_RXOICR_t
;
2283
#endif
/* __ASSEMBLY__ */
2284
2286
#define ALT_SPIS_RXOICR_OFST 0x3c
2287
2288
#define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2289
2311
#define ALT_SPIS_RXUICR_RXUICR_LSB 0
2312
2313
#define ALT_SPIS_RXUICR_RXUICR_MSB 0
2314
2315
#define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2316
2317
#define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2318
2319
#define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2320
2321
#define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2322
2323
#define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2324
2325
#define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2326
2327
#ifndef __ASSEMBLY__
2328
2338
struct
ALT_SPIS_RXUICR_s
2339
{
2340
const
uint32_t
rxuicr
: 1;
2341
uint32_t : 31;
2342
};
2343
2345
typedef
volatile
struct
ALT_SPIS_RXUICR_s
ALT_SPIS_RXUICR_t
;
2346
#endif
/* __ASSEMBLY__ */
2347
2349
#define ALT_SPIS_RXUICR_OFST 0x40
2350
2351
#define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2352
2375
#define ALT_SPIS_ICR_ICR_LSB 0
2376
2377
#define ALT_SPIS_ICR_ICR_MSB 0
2378
2379
#define ALT_SPIS_ICR_ICR_WIDTH 1
2380
2381
#define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2382
2383
#define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2384
2385
#define ALT_SPIS_ICR_ICR_RESET 0x0
2386
2387
#define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2388
2389
#define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2390
2391
#ifndef __ASSEMBLY__
2392
2402
struct
ALT_SPIS_ICR_s
2403
{
2404
const
uint32_t
icr
: 1;
2405
uint32_t : 31;
2406
};
2407
2409
typedef
volatile
struct
ALT_SPIS_ICR_s
ALT_SPIS_ICR_t
;
2410
#endif
/* __ASSEMBLY__ */
2411
2413
#define ALT_SPIS_ICR_OFST 0x48
2414
2415
#define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
2416
2451
#define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
2452
2457
#define ALT_SPIS_DMACR_RDMAE_E_END 0x1
2458
2460
#define ALT_SPIS_DMACR_RDMAE_LSB 0
2461
2462
#define ALT_SPIS_DMACR_RDMAE_MSB 0
2463
2464
#define ALT_SPIS_DMACR_RDMAE_WIDTH 1
2465
2466
#define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
2467
2468
#define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
2469
2470
#define ALT_SPIS_DMACR_RDMAE_RESET 0x0
2471
2472
#define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
2473
2474
#define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
2475
2496
#define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
2497
2502
#define ALT_SPIS_DMACR_TDMAE_E_END 0x1
2503
2505
#define ALT_SPIS_DMACR_TDMAE_LSB 1
2506
2507
#define ALT_SPIS_DMACR_TDMAE_MSB 1
2508
2509
#define ALT_SPIS_DMACR_TDMAE_WIDTH 1
2510
2511
#define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
2512
2513
#define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
2514
2515
#define ALT_SPIS_DMACR_TDMAE_RESET 0x0
2516
2517
#define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
2518
2519
#define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
2520
2521
#ifndef __ASSEMBLY__
2522
2532
struct
ALT_SPIS_DMACR_s
2533
{
2534
uint32_t
rdmae
: 1;
2535
uint32_t
tdmae
: 1;
2536
uint32_t : 30;
2537
};
2538
2540
typedef
volatile
struct
ALT_SPIS_DMACR_s
ALT_SPIS_DMACR_t
;
2541
#endif
/* __ASSEMBLY__ */
2542
2544
#define ALT_SPIS_DMACR_OFST 0x4c
2545
2546
#define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
2547
2573
#define ALT_SPIS_DMATDLR_DMATDL_LSB 0
2574
2575
#define ALT_SPIS_DMATDLR_DMATDL_MSB 7
2576
2577
#define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
2578
2579
#define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
2580
2581
#define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
2582
2583
#define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
2584
2585
#define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
2586
2587
#define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
2588
2589
#ifndef __ASSEMBLY__
2590
2600
struct
ALT_SPIS_DMATDLR_s
2601
{
2602
uint32_t
dmatdl
: 8;
2603
uint32_t : 24;
2604
};
2605
2607
typedef
volatile
struct
ALT_SPIS_DMATDLR_s
ALT_SPIS_DMATDLR_t
;
2608
#endif
/* __ASSEMBLY__ */
2609
2611
#define ALT_SPIS_DMATDLR_OFST 0x50
2612
2613
#define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
2614
2640
#define ALT_SPIS_DMARDLR_DMARDL_LSB 0
2641
2642
#define ALT_SPIS_DMARDLR_DMARDL_MSB 7
2643
2644
#define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
2645
2646
#define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
2647
2648
#define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
2649
2650
#define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
2651
2652
#define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
2653
2654
#define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
2655
2656
#ifndef __ASSEMBLY__
2657
2667
struct
ALT_SPIS_DMARDLR_s
2668
{
2669
uint32_t
dmardl
: 8;
2670
uint32_t : 24;
2671
};
2672
2674
typedef
volatile
struct
ALT_SPIS_DMARDLR_s
ALT_SPIS_DMARDLR_t
;
2675
#endif
/* __ASSEMBLY__ */
2676
2678
#define ALT_SPIS_DMARDLR_OFST 0x54
2679
2680
#define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
2681
2703
#define ALT_SPIS_IDR_IDR_LSB 0
2704
2705
#define ALT_SPIS_IDR_IDR_MSB 31
2706
2707
#define ALT_SPIS_IDR_IDR_WIDTH 32
2708
2709
#define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
2710
2711
#define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
2712
2713
#define ALT_SPIS_IDR_IDR_RESET 0x5510005
2714
2715
#define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
2716
2717
#define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
2718
2719
#ifndef __ASSEMBLY__
2720
2730
struct
ALT_SPIS_IDR_s
2731
{
2732
const
uint32_t
idr
: 32;
2733
};
2734
2736
typedef
volatile
struct
ALT_SPIS_IDR_s
ALT_SPIS_IDR_t
;
2737
#endif
/* __ASSEMBLY__ */
2738
2740
#define ALT_SPIS_IDR_OFST 0x58
2741
2742
#define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
2743
2766
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
2767
2768
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
2769
2770
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
2771
2772
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
2773
2774
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
2775
2776
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a
2777
2778
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
2779
2780
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
2781
2782
#ifndef __ASSEMBLY__
2783
2793
struct
ALT_SPIS_SPI_VER_ID_s
2794
{
2795
uint32_t
spi_version_id
: 32;
2796
};
2797
2799
typedef
volatile
struct
ALT_SPIS_SPI_VER_ID_s
ALT_SPIS_SPI_VER_ID_t
;
2800
#endif
/* __ASSEMBLY__ */
2801
2803
#define ALT_SPIS_SPI_VER_ID_OFST 0x5c
2804
2805
#define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
2806
2837
#define ALT_SPIS_DR_DR_LSB 0
2838
2839
#define ALT_SPIS_DR_DR_MSB 15
2840
2841
#define ALT_SPIS_DR_DR_WIDTH 16
2842
2843
#define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
2844
2845
#define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
2846
2847
#define ALT_SPIS_DR_DR_RESET 0x0
2848
2849
#define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
2850
2851
#define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
2852
2853
#ifndef __ASSEMBLY__
2854
2864
struct
ALT_SPIS_DR_s
2865
{
2866
uint32_t
dr
: 16;
2867
uint32_t : 16;
2868
};
2869
2871
typedef
volatile
struct
ALT_SPIS_DR_s
ALT_SPIS_DR_t
;
2872
#endif
/* __ASSEMBLY__ */
2873
2875
#define ALT_SPIS_DR_OFST 0x60
2876
2877
#define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
2878
2879
#ifndef __ASSEMBLY__
2880
2890
struct
ALT_SPIS_s
2891
{
2892
volatile
ALT_SPIS_CTLR0_t
ctrlr0
;
2893
volatile
uint32_t
_pad_0x4_0x7
;
2894
volatile
ALT_SPIS_SPIENR_t
spienr
;
2895
volatile
ALT_SPIS_MWCR_t
mwcr
;
2896
volatile
uint32_t
_pad_0x10_0x17
[2];
2897
volatile
ALT_SPIS_TXFTLR_t
txftlr
;
2898
volatile
ALT_SPIS_RXFTLR_t
rxftlr
;
2899
volatile
ALT_SPIS_TXFLR_t
txflr
;
2900
volatile
ALT_SPIS_RXFLR_t
rxflr
;
2901
volatile
ALT_SPIS_SR_t
sr
;
2902
volatile
ALT_SPIS_IMR_t
imr
;
2903
volatile
ALT_SPIS_ISR_t
isr
;
2904
volatile
ALT_SPIS_RISR_t
risr
;
2905
volatile
ALT_SPIS_TXOICR_t
txoicr
;
2906
volatile
ALT_SPIS_RXOICR_t
rxoicr
;
2907
volatile
ALT_SPIS_RXUICR_t
rxuicr
;
2908
volatile
uint32_t
_pad_0x44_0x47
;
2909
volatile
ALT_SPIS_ICR_t
icr
;
2910
volatile
ALT_SPIS_DMACR_t
dmacr
;
2911
volatile
ALT_SPIS_DMATDLR_t
dmatdlr
;
2912
volatile
ALT_SPIS_DMARDLR_t
dmardlr
;
2913
volatile
ALT_SPIS_IDR_t
idr
;
2914
volatile
ALT_SPIS_SPI_VER_ID_t
spi_version_id
;
2915
volatile
ALT_SPIS_DR_t
dr
;
2916
volatile
uint32_t
_pad_0x64_0x80
[7];
2917
};
2918
2920
typedef
volatile
struct
ALT_SPIS_s
ALT_SPIS_t
;
2922
struct
ALT_SPIS_raw_s
2923
{
2924
volatile
uint32_t
ctrlr0
;
2925
volatile
uint32_t
_pad_0x4_0x7
;
2926
volatile
uint32_t
spienr
;
2927
volatile
uint32_t
mwcr
;
2928
volatile
uint32_t
_pad_0x10_0x17
[2];
2929
volatile
uint32_t
txftlr
;
2930
volatile
uint32_t
rxftlr
;
2931
volatile
uint32_t
txflr
;
2932
volatile
uint32_t
rxflr
;
2933
volatile
uint32_t
sr
;
2934
volatile
uint32_t
imr
;
2935
volatile
uint32_t
isr
;
2936
volatile
uint32_t
risr
;
2937
volatile
uint32_t
txoicr
;
2938
volatile
uint32_t
rxoicr
;
2939
volatile
uint32_t
rxuicr
;
2940
volatile
uint32_t
_pad_0x44_0x47
;
2941
volatile
uint32_t
icr
;
2942
volatile
uint32_t
dmacr
;
2943
volatile
uint32_t
dmatdlr
;
2944
volatile
uint32_t
dmardlr
;
2945
volatile
uint32_t
idr
;
2946
volatile
uint32_t
spi_version_id
;
2947
volatile
uint32_t
dr
;
2948
volatile
uint32_t
_pad_0x64_0x80
[7];
2949
};
2950
2952
typedef
volatile
struct
ALT_SPIS_raw_s
ALT_SPIS_raw_t
;
2953
#endif
/* __ASSEMBLY__ */
2954
2956
#ifdef __cplusplus
2957
}
2958
#endif
/* __cplusplus */
2959
#endif
/* __ALTERA_ALT_SPIS_H__ */
2960
include
soc_cv_av
socal
alt_spis.h
Generated on Tue Sep 8 2015 13:28:44 for Altera SoCAL by
1.8.2