Altera HWLIB  16.0
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alt_clock_manager.h
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1 
6 /******************************************************************************
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36 ******************************************************************************/
37 
38 /*
39  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_clock_manager.h#1 $
40  */
41 
42 #ifndef __ALT_CLK_MGR_H__
43 #define __ALT_CLK_MGR_H__
44 
45 #include "hwlib.h"
46 #include "alt_clock_group.h"
47 
48 #ifdef __cplusplus
49 extern "C"
50 {
51 #endif /* __cplusplus */
52 
61 /******************************************************************************/
66 typedef uint32_t alt_freq_t;
67 
68 /******************************************************************************/
73 typedef enum ALT_CLK_e
74 {
75  /* Clock Input Pins */
98  /* FPGA Clock Sources External to HPS */
99  ALT_CLK_F2H_PERIPH_REF,
100  /*<! Alternate clock source from FPGA
101  * for HPS Peripheral PLL. */
102 
103  ALT_CLK_F2H_SDRAM_REF,
104  /*<! Alternate clock source from FPGA
105  * for HPS SDRAM PLL. */
106 
107 
108  /* Other Clock Sources External to HPS */
142  /* PLLs */
165  /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
166  * directly from the osc_clk_1_HPS pin */
177  /* Main Clock Group - The following clocks are derived from the Main PLL. */
305  /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
396  /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
442  /* Clock Output Pins */
503  ALT_CLK_UNKNOWN
504 } ALT_CLK_t;
505 
506 /******************************************************************************/
514 /******************************************************************************/
521 {
522  ALT_MAIN_PLL_LOCK_ACHV = 0x00000001,
532  ALT_SDR_PLL_LOCK_ACHV = 0x00000004,
537  ALT_MAIN_PLL_LOCK_LOST = 0x00000008,
547  ALT_SDR_PLL_LOCK_LOST = 0x00000020
553 
554 /******************************************************************************/
573 ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
574 
575 /******************************************************************************/
585 uint32_t alt_clk_lock_status_get(void);
586 
587 /******************************************************************************/
608 ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
609 
612 /******************************************************************************/
650 /******************************************************************************/
656 {
668 
669 /******************************************************************************/
679 ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
680 
681 /******************************************************************************/
692 
695 /******************************************************************************/
719 /******************************************************************************/
732 ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
733 
734 /******************************************************************************/
753 ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
754  bool use_input_mux);
755 
756 /******************************************************************************/
774 ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
775 
778 /******************************************************************************/
823 /******************************************************************************/
836 ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
837 
838 /******************************************************************************/
851 ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
852 
853 /******************************************************************************/
865 ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
866 
869 /******************************************************************************/
916 /******************************************************************************/
934 
935 /******************************************************************************/
955 ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
956  ALT_CLK_t ref_clk);
957 
960 /******************************************************************************/
969 /******************************************************************************/
996 ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
997  alt_freq_t freq);
998 
999 /******************************************************************************/
1017 alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
1018 
1019 /******************************************************************************/
1024 typedef struct ALT_CLK_PLL_CFG_s
1025 {
1027  uint32_t mult;
1030  uint32_t div;
1033  uint32_t cntrs[6];
1036  uint32_t pshift[6];
1041 
1042 /******************************************************************************/
1056 ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
1057  ALT_CLK_PLL_CFG_t* pll_cfg);
1058 
1059 /******************************************************************************/
1074 ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
1075  const ALT_CLK_PLL_CFG_t* pll_cfg);
1076 
1077 /******************************************************************************/
1095 ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
1096  uint32_t* mult,
1097  uint32_t* div);
1098 
1099 /******************************************************************************/
1116 ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
1117  uint32_t mult,
1118  uint32_t div);
1119 
1120 /******************************************************************************/
1138 ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
1139  alt_freq_t* freq);
1140 
1141 /******************************************************************************/
1151 
1152 /******************************************************************************/
1182 ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
1183  uint32_t guard_band);
1184 
1185 /******************************************************************************/
1208 ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
1209  uint32_t* div);
1210 
1211 /******************************************************************************/
1236 ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
1237  uint32_t div);
1238 
1239 /******************************************************************************/
1257 ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
1258  alt_freq_t* freq);
1259 
1262 /******************************************************************************/
1307 /******************************************************************************/
1329 ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1330 
1331 /******************************************************************************/
1353 ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
1354 
1357 /******************************************************************************/
1388 /******************************************************************************/
1407 ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
1408  ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1409 
1410 /******************************************************************************/
1429 ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
1430 
1431 /******************************************************************************/
1441 ALT_STATUS_CODE alt_clk_clkmgr_init(void);
1442 
1443 /******************************************************************************/
1451 ALT_STATUS_CODE alt_clk_clkmgr_uninit(void);
1452 
1456 #ifdef __cplusplus
1457 }
1458 
1459 #endif /* __cplusplus */
1460 #endif /* __ALT_CLK_MGR_H__ */