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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Interrupt status
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA |
[1] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA |
[2] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA |
[15:3] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG |
[17] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG |
[18] | RW | 0x0 | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG |
[31:19] | ??? | 0x0 | UNDEFINED |
Field : SERRPENA | |
Single-bit error pending This bit is used to clear the pending SBE. 1'b0: No effect. 1'b1: indicates SBE is pending. Write of one will clear the pending. This will de-assert the serr_req signal. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_LSB 0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_MSB 0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001 |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001) |
Field : DERRPENA | |
Double bit error pending This bit is used to clear the pending DBE. 1'b0: No effect. 1'b1: indicates DBE is pending. Write of one will clear the pending DBE. This will de-assert the derr_req signal. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_LSB 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_MSB 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET(value) (((value) << 1) & 0x00000002) |
Field : HMI_PENA | |
HMI interrupt pending This bit is used to clear the pending hmi interrupt bit. 1'b0: No effect 1'b1: indicates hmi interrupt is pending. Write of one will clear the pending interrupt. This will de-assert the hmi_intr signal. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_LSB 2 |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_MSB 2 |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET_MSK 0x00000004 |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET(value) (((value) << 2) & 0x00000004) |
Field : ADDRMTCFLG | |
Address mismatch error flag. This bit is used to flag the last transaction was flagged with address mismatch error. 1'b0: No effect. 1'b1: indicates address mismatch error has occured. This will drive the bus to respond the read with bus error. Write of one will clears this register address mismatch error. Bus error occurs as part of the transaction but this indicates the SW the cause of the error. This should occur once per transaction. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_LSB 16 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_MSB 16 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET(value) (((value) << 16) & 0x00010000) |
Field : ADDRPARFLG | |
External address parity flag for DDR4 memory. This bit is used to flag external address parity flag which is driven with derr_req port. 1'b0: No Effect. 1'b1: Read of one indicates double-bit interrupt has occurred. Write of one will clear this register last address parity flag. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_LSB 17 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_MSB 17 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET(value) (((value) << 17) & 0x00020000) |
Field : DERRBUSFLG | |
This bit is used to flag the last transaction was flagged with double-bit error. 1'b0: no effect. 1'b1: indicates double-bit error has occured. This will drive the bus to respond the read with bus error. Write of one will clear this register double-but bus error. Bus error occurs as part of the transaction but this indicates the SW the cause of the error. This should only occur once per transaction Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_LSB 18 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_MSB 18 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET(value) (((value) << 18) & 0x00040000) |
Data Structures | |
struct | ALT_ECC_HMC_OCP_INTSTAT_s |
Macros | |
#define | ALT_ECC_HMC_OCP_INTSTAT_RESET 0x00000000 |
#define | ALT_ECC_HMC_OCP_INTSTAT_OFST 0x120 |
Typedefs | |
typedef struct ALT_ECC_HMC_OCP_INTSTAT_s | ALT_ECC_HMC_OCP_INTSTAT_t |
struct ALT_ECC_HMC_OCP_INTSTAT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_HMC_OCP_INTSTAT.
Data Fields | ||
---|---|---|
uint32_t | SERRPENA: 1 | ALT_ECC_HMC_OCP_INTSTAT_SERRPENA |
uint32_t | DERRPENA: 1 | ALT_ECC_HMC_OCP_INTSTAT_DERRPENA |
uint32_t | HMI_PENA: 1 | ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA |
uint32_t | __pad0__: 13 | UNDEFINED |
uint32_t | ADDRMTCFLG: 1 | ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG |
uint32_t | ADDRPARFLG: 1 | ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG |
uint32_t | DERRBUSFLG: 1 | ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG |
uint32_t | __pad1__: 13 | UNDEFINED |
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET_MSK 0x00000001 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_SERRPENA field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_SERRPENA_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_SERRPENA register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET_MSK 0x00000002 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_DERRPENA field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRPENA_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_DERRPENA register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET_MSK 0x00000004 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_HMI_PENA register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET_MSK 0x00010000 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_ADDRMTCFLG register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET_MSK 0x00020000 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_ADDRPARFLG register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET_MSK 0x00040000 |
The mask used to set the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG field value from a register.
#define ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_ECC_HMC_OCP_INTSTAT_DERRBUSFLG register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_INTSTAT_RESET 0x00000000 |
The reset value of the ALT_ECC_HMC_OCP_INTSTAT register.
#define ALT_ECC_HMC_OCP_INTSTAT_OFST 0x120 |
The byte offset of the ALT_ECC_HMC_OCP_INTSTAT register from the beginning of the component.
typedef struct ALT_ECC_HMC_OCP_INTSTAT_s ALT_ECC_HMC_OCP_INTSTAT_t |
The typedef declaration for register ALT_ECC_HMC_OCP_INTSTAT.