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alt_spis.h
1
/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_SPIS_H__
36
#define __ALT_SOCAL_SPIS_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
43
#else
/* __cplusplus */
44
#include <stdint.h>
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#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
47
121
#define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3
122
127
#define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4
128
133
#define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5
134
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7
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#define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8
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157
#define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9
158
163
#define ALT_SPIS_CTLR0_DFS_E_WIDTH11BIT 0xa
164
169
#define ALT_SPIS_CTLR0_DFS_E_WIDTH12BIT 0xb
170
175
#define ALT_SPIS_CTLR0_DFS_E_WIDTH13BIT 0xc
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181
#define ALT_SPIS_CTLR0_DFS_E_WIDTH14BIT 0xd
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187
#define ALT_SPIS_CTLR0_DFS_E_WIDTH15BIT 0xe
188
193
#define ALT_SPIS_CTLR0_DFS_E_WIDTH16BIT 0xf
194
196
#define ALT_SPIS_CTLR0_DFS_LSB 0
197
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#define ALT_SPIS_CTLR0_DFS_MSB 3
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#define ALT_SPIS_CTLR0_DFS_WIDTH 4
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#define ALT_SPIS_CTLR0_DFS_SET_MSK 0x0000000f
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#define ALT_SPIS_CTLR0_DFS_CLR_MSK 0xfffffff0
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#define ALT_SPIS_CTLR0_DFS_RESET 0x7
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#define ALT_SPIS_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
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#define ALT_SPIS_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
211
243
#define ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0
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249
#define ALT_SPIS_CTLR0_FRF_E_TISSP 0x1
250
255
#define ALT_SPIS_CTLR0_FRF_E_NATMW 0x2
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258
#define ALT_SPIS_CTLR0_FRF_LSB 4
259
260
#define ALT_SPIS_CTLR0_FRF_MSB 5
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#define ALT_SPIS_CTLR0_FRF_WIDTH 2
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264
#define ALT_SPIS_CTLR0_FRF_SET_MSK 0x00000030
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266
#define ALT_SPIS_CTLR0_FRF_CLR_MSK 0xffffffcf
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268
#define ALT_SPIS_CTLR0_FRF_RESET 0x0
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270
#define ALT_SPIS_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
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#define ALT_SPIS_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
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310
#define ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0
311
316
#define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1
317
319
#define ALT_SPIS_CTLR0_SCPH_LSB 6
320
321
#define ALT_SPIS_CTLR0_SCPH_MSB 6
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#define ALT_SPIS_CTLR0_SCPH_WIDTH 1
324
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#define ALT_SPIS_CTLR0_SCPH_SET_MSK 0x00000040
326
327
#define ALT_SPIS_CTLR0_SCPH_CLR_MSK 0xffffffbf
328
329
#define ALT_SPIS_CTLR0_SCPH_RESET 0x0
330
331
#define ALT_SPIS_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
332
333
#define ALT_SPIS_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
334
365
#define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0
366
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#define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1
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#define ALT_SPIS_CTLR0_SCPOL_LSB 7
375
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#define ALT_SPIS_CTLR0_SCPOL_MSB 7
377
378
#define ALT_SPIS_CTLR0_SCPOL_WIDTH 1
379
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#define ALT_SPIS_CTLR0_SCPOL_SET_MSK 0x00000080
381
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#define ALT_SPIS_CTLR0_SCPOL_CLR_MSK 0xffffff7f
383
384
#define ALT_SPIS_CTLR0_SCPOL_RESET 0x0
385
386
#define ALT_SPIS_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
387
388
#define ALT_SPIS_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
389
441
#define ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0
442
447
#define ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1
448
453
#define ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2
454
456
#define ALT_SPIS_CTLR0_TMOD_LSB 8
457
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#define ALT_SPIS_CTLR0_TMOD_MSB 9
459
460
#define ALT_SPIS_CTLR0_TMOD_WIDTH 2
461
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#define ALT_SPIS_CTLR0_TMOD_SET_MSK 0x00000300
463
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#define ALT_SPIS_CTLR0_TMOD_CLR_MSK 0xfffffcff
465
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#define ALT_SPIS_CTLR0_TMOD_RESET 0x0
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#define ALT_SPIS_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
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#define ALT_SPIS_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
471
520
#define ALT_SPIS_CTLR0_SLV_OE_E_END 0x0
521
526
#define ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1
527
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#define ALT_SPIS_CTLR0_SLV_OE_LSB 10
530
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#define ALT_SPIS_CTLR0_SLV_OE_MSB 10
532
533
#define ALT_SPIS_CTLR0_SLV_OE_WIDTH 1
534
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#define ALT_SPIS_CTLR0_SLV_OE_SET_MSK 0x00000400
536
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#define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK 0xfffffbff
538
539
#define ALT_SPIS_CTLR0_SLV_OE_RESET 0x0
540
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#define ALT_SPIS_CTLR0_SLV_OE_GET(value) (((value) & 0x00000400) >> 10)
542
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#define ALT_SPIS_CTLR0_SLV_OE_SET(value) (((value) << 10) & 0x00000400)
544
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#define ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0
574
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#define ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1
580
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#define ALT_SPIS_CTLR0_SRL_LSB 11
583
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#define ALT_SPIS_CTLR0_SRL_MSB 11
585
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#define ALT_SPIS_CTLR0_SRL_WIDTH 1
587
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#define ALT_SPIS_CTLR0_SRL_SET_MSK 0x00000800
589
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#define ALT_SPIS_CTLR0_SRL_CLR_MSK 0xfffff7ff
591
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#define ALT_SPIS_CTLR0_SRL_RESET 0x0
593
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#define ALT_SPIS_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
595
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#define ALT_SPIS_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
597
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#define ALT_SPIS_CTLR0_CFS_E_SIZE1BIT 0x0
635
640
#define ALT_SPIS_CTLR0_CFS_E_SIZE2BIT 0x1
641
646
#define ALT_SPIS_CTLR0_CFS_E_SIZE3BIT 0x2
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652
#define ALT_SPIS_CTLR0_CFS_E_SIZE4BIT 0x3
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#define ALT_SPIS_CTLR0_CFS_E_SIZE5BIT 0x4
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#define ALT_SPIS_CTLR0_CFS_E_SIZE6BIT 0x5
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#define ALT_SPIS_CTLR0_CFS_E_SIZE7BIT 0x6
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#define ALT_SPIS_CTLR0_CFS_E_SIZE8BIT 0x7
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#define ALT_SPIS_CTLR0_CFS_E_SIZE9BIT 0x8
683
688
#define ALT_SPIS_CTLR0_CFS_E_SIZE10BIT 0x9
689
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#define ALT_SPIS_CTLR0_CFS_E_SIZE11BIT 0xa
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700
#define ALT_SPIS_CTLR0_CFS_E_SIZE12BIT 0xb
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706
#define ALT_SPIS_CTLR0_CFS_E_SIZE13BIT 0xc
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712
#define ALT_SPIS_CTLR0_CFS_E_SIZE14BIT 0xd
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718
#define ALT_SPIS_CTLR0_CFS_E_SIZE15BIT 0xe
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724
#define ALT_SPIS_CTLR0_CFS_E_SIZE16BIT 0xf
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#define ALT_SPIS_CTLR0_CFS_LSB 12
728
729
#define ALT_SPIS_CTLR0_CFS_MSB 15
730
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#define ALT_SPIS_CTLR0_CFS_WIDTH 4
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#define ALT_SPIS_CTLR0_CFS_SET_MSK 0x0000f000
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#define ALT_SPIS_CTLR0_CFS_CLR_MSK 0xffff0fff
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737
#define ALT_SPIS_CTLR0_CFS_RESET 0x0
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#define ALT_SPIS_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
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#define ALT_SPIS_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
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743
#ifndef __ASSEMBLY__
744
754
struct
ALT_SPIS_CTLR0_s
755
{
756
uint32_t
dfs
: 4;
757
uint32_t
frf
: 2;
758
uint32_t
scph
: 1;
759
uint32_t
scpol
: 1;
760
uint32_t
tmod
: 2;
761
uint32_t
slv_oe
: 1;
762
uint32_t
srl
: 1;
763
uint32_t
cfs
: 4;
764
uint32_t : 16;
765
};
766
768
typedef
volatile
struct
ALT_SPIS_CTLR0_s
ALT_SPIS_CTLR0_t
;
769
#endif
/* __ASSEMBLY__ */
770
772
#define ALT_SPIS_CTLR0_RESET 0x00000007
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774
#define ALT_SPIS_CTLR0_OFST 0x0
775
776
#define ALT_SPIS_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
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823
#define ALT_SPIS_SPIENR_SPI_EN_E_DISD 0x0
824
829
#define ALT_SPIS_SPIENR_SPI_EN_E_END 0x1
830
832
#define ALT_SPIS_SPIENR_SPI_EN_LSB 0
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#define ALT_SPIS_SPIENR_SPI_EN_MSB 0
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#define ALT_SPIS_SPIENR_SPI_EN_WIDTH 1
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#define ALT_SPIS_SPIENR_SPI_EN_SET_MSK 0x00000001
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#define ALT_SPIS_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
841
842
#define ALT_SPIS_SPIENR_SPI_EN_RESET 0x0
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#define ALT_SPIS_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SPIS_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
847
848
#ifndef __ASSEMBLY__
849
859
struct
ALT_SPIS_SPIENR_s
860
{
861
uint32_t
spi_en
: 1;
862
uint32_t : 31;
863
};
864
866
typedef
volatile
struct
ALT_SPIS_SPIENR_s
ALT_SPIS_SPIENR_t
;
867
#endif
/* __ASSEMBLY__ */
868
870
#define ALT_SPIS_SPIENR_RESET 0x00000000
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#define ALT_SPIS_SPIENR_OFST 0x8
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#define ALT_SPIS_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPIENR_OFST))
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#define ALT_SPIS_MWCR_MWMOD_E_NONSEQ 0x0
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938
#define ALT_SPIS_MWCR_MWMOD_E_SEQ 0x1
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#define ALT_SPIS_MWCR_MWMOD_LSB 0
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#define ALT_SPIS_MWCR_MWMOD_MSB 0
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#define ALT_SPIS_MWCR_MWMOD_WIDTH 1
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#define ALT_SPIS_MWCR_MWMOD_SET_MSK 0x00000001
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#define ALT_SPIS_MWCR_MWMOD_CLR_MSK 0xfffffffe
950
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#define ALT_SPIS_MWCR_MWMOD_RESET 0x0
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#define ALT_SPIS_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
954
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#define ALT_SPIS_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_SPIS_MWCR_MDD_E_RXMOD 0x0
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#define ALT_SPIS_MWCR_MDD_E_TXMOD 0x1
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#define ALT_SPIS_MWCR_MDD_LSB 1
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#define ALT_SPIS_MWCR_MDD_MSB 1
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#define ALT_SPIS_MWCR_MDD_WIDTH 1
1001
1002
#define ALT_SPIS_MWCR_MDD_SET_MSK 0x00000002
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1004
#define ALT_SPIS_MWCR_MDD_CLR_MSK 0xfffffffd
1005
1006
#define ALT_SPIS_MWCR_MDD_RESET 0x0
1007
1008
#define ALT_SPIS_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1009
1010
#define ALT_SPIS_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1011
1012
#ifndef __ASSEMBLY__
1013
1023
struct
ALT_SPIS_MWCR_s
1024
{
1025
uint32_t
mwmod
: 1;
1026
uint32_t
mdd
: 1;
1027
uint32_t : 30;
1028
};
1029
1031
typedef
volatile
struct
ALT_SPIS_MWCR_s
ALT_SPIS_MWCR_t
;
1032
#endif
/* __ASSEMBLY__ */
1033
1035
#define ALT_SPIS_MWCR_RESET 0x00000000
1036
1037
#define ALT_SPIS_MWCR_OFST 0xc
1038
1039
#define ALT_SPIS_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MWCR_OFST))
1040
1081
#define ALT_SPIS_TXFTLR_TFT_LSB 0
1082
1083
#define ALT_SPIS_TXFTLR_TFT_MSB 7
1084
1085
#define ALT_SPIS_TXFTLR_TFT_WIDTH 8
1086
1087
#define ALT_SPIS_TXFTLR_TFT_SET_MSK 0x000000ff
1088
1089
#define ALT_SPIS_TXFTLR_TFT_CLR_MSK 0xffffff00
1090
1091
#define ALT_SPIS_TXFTLR_TFT_RESET 0x0
1092
1093
#define ALT_SPIS_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1094
1095
#define ALT_SPIS_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1096
1097
#ifndef __ASSEMBLY__
1098
1108
struct
ALT_SPIS_TXFTLR_s
1109
{
1110
uint32_t
tft
: 8;
1111
uint32_t : 24;
1112
};
1113
1115
typedef
volatile
struct
ALT_SPIS_TXFTLR_s
ALT_SPIS_TXFTLR_t
;
1116
#endif
/* __ASSEMBLY__ */
1117
1119
#define ALT_SPIS_TXFTLR_RESET 0x00000000
1120
1121
#define ALT_SPIS_TXFTLR_OFST 0x18
1122
1123
#define ALT_SPIS_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
1124
1165
#define ALT_SPIS_RXFTLR_RFT_LSB 0
1166
1167
#define ALT_SPIS_RXFTLR_RFT_MSB 7
1168
1169
#define ALT_SPIS_RXFTLR_RFT_WIDTH 8
1170
1171
#define ALT_SPIS_RXFTLR_RFT_SET_MSK 0x000000ff
1172
1173
#define ALT_SPIS_RXFTLR_RFT_CLR_MSK 0xffffff00
1174
1175
#define ALT_SPIS_RXFTLR_RFT_RESET 0x0
1176
1177
#define ALT_SPIS_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1178
1179
#define ALT_SPIS_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1180
1181
#ifndef __ASSEMBLY__
1182
1192
struct
ALT_SPIS_RXFTLR_s
1193
{
1194
uint32_t
rft
: 8;
1195
uint32_t : 24;
1196
};
1197
1199
typedef
volatile
struct
ALT_SPIS_RXFTLR_s
ALT_SPIS_RXFTLR_t
;
1200
#endif
/* __ASSEMBLY__ */
1201
1203
#define ALT_SPIS_RXFTLR_RESET 0x00000000
1204
1205
#define ALT_SPIS_RXFTLR_OFST 0x1c
1206
1207
#define ALT_SPIS_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFTLR_OFST))
1208
1233
#define ALT_SPIS_TXFLR_TXTFL_LSB 0
1234
1235
#define ALT_SPIS_TXFLR_TXTFL_MSB 8
1236
1237
#define ALT_SPIS_TXFLR_TXTFL_WIDTH 9
1238
1239
#define ALT_SPIS_TXFLR_TXTFL_SET_MSK 0x000001ff
1240
1241
#define ALT_SPIS_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1242
1243
#define ALT_SPIS_TXFLR_TXTFL_RESET 0x0
1244
1245
#define ALT_SPIS_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1246
1247
#define ALT_SPIS_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1248
1249
#ifndef __ASSEMBLY__
1250
1260
struct
ALT_SPIS_TXFLR_s
1261
{
1262
const
uint32_t
txtfl
: 9;
1263
uint32_t : 23;
1264
};
1265
1267
typedef
volatile
struct
ALT_SPIS_TXFLR_s
ALT_SPIS_TXFLR_t
;
1268
#endif
/* __ASSEMBLY__ */
1269
1271
#define ALT_SPIS_TXFLR_RESET 0x00000000
1272
1273
#define ALT_SPIS_TXFLR_OFST 0x20
1274
1275
#define ALT_SPIS_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFLR_OFST))
1276
1301
#define ALT_SPIS_RXFLR_RXTFL_LSB 0
1302
1303
#define ALT_SPIS_RXFLR_RXTFL_MSB 8
1304
1305
#define ALT_SPIS_RXFLR_RXTFL_WIDTH 9
1306
1307
#define ALT_SPIS_RXFLR_RXTFL_SET_MSK 0x000001ff
1308
1309
#define ALT_SPIS_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1310
1311
#define ALT_SPIS_RXFLR_RXTFL_RESET 0x0
1312
1313
#define ALT_SPIS_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1314
1315
#define ALT_SPIS_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1316
1317
#ifndef __ASSEMBLY__
1318
1328
struct
ALT_SPIS_RXFLR_s
1329
{
1330
const
uint32_t
rxtfl
: 9;
1331
uint32_t : 23;
1332
};
1333
1335
typedef
volatile
struct
ALT_SPIS_RXFLR_s
ALT_SPIS_RXFLR_t
;
1336
#endif
/* __ASSEMBLY__ */
1337
1339
#define ALT_SPIS_RXFLR_RESET 0x00000000
1340
1341
#define ALT_SPIS_RXFLR_OFST 0x24
1342
1343
#define ALT_SPIS_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXFLR_OFST))
1344
1399
#define ALT_SPIS_SR_BUSY_E_INACT 0x0
1400
1405
#define ALT_SPIS_SR_BUSY_E_ACT 0x1
1406
1408
#define ALT_SPIS_SR_BUSY_LSB 0
1409
1410
#define ALT_SPIS_SR_BUSY_MSB 0
1411
1412
#define ALT_SPIS_SR_BUSY_WIDTH 1
1413
1414
#define ALT_SPIS_SR_BUSY_SET_MSK 0x00000001
1415
1416
#define ALT_SPIS_SR_BUSY_CLR_MSK 0xfffffffe
1417
1418
#define ALT_SPIS_SR_BUSY_RESET 0x0
1419
1420
#define ALT_SPIS_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1421
1422
#define ALT_SPIS_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1423
1450
#define ALT_SPIS_SR_TFNF_E_FULL 0x0
1451
1456
#define ALT_SPIS_SR_TFNF_E_NOTFULL 0x1
1457
1459
#define ALT_SPIS_SR_TFNF_LSB 1
1460
1461
#define ALT_SPIS_SR_TFNF_MSB 1
1462
1463
#define ALT_SPIS_SR_TFNF_WIDTH 1
1464
1465
#define ALT_SPIS_SR_TFNF_SET_MSK 0x00000002
1466
1467
#define ALT_SPIS_SR_TFNF_CLR_MSK 0xfffffffd
1468
1469
#define ALT_SPIS_SR_TFNF_RESET 0x1
1470
1471
#define ALT_SPIS_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1472
1473
#define ALT_SPIS_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1474
1505
#define ALT_SPIS_SR_TFE_E_NOTEMPTY 0x0
1506
1511
#define ALT_SPIS_SR_TFE_E_EMPTY 0x1
1512
1514
#define ALT_SPIS_SR_TFE_LSB 2
1515
1516
#define ALT_SPIS_SR_TFE_MSB 2
1517
1518
#define ALT_SPIS_SR_TFE_WIDTH 1
1519
1520
#define ALT_SPIS_SR_TFE_SET_MSK 0x00000004
1521
1522
#define ALT_SPIS_SR_TFE_CLR_MSK 0xfffffffb
1523
1524
#define ALT_SPIS_SR_TFE_RESET 0x1
1525
1526
#define ALT_SPIS_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1527
1528
#define ALT_SPIS_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1529
1560
#define ALT_SPIS_SR_RFNE_E_EMPTY 0x0
1561
1566
#define ALT_SPIS_SR_RFNE_E_NOTEMPTY 0x1
1567
1569
#define ALT_SPIS_SR_RFNE_LSB 3
1570
1571
#define ALT_SPIS_SR_RFNE_MSB 3
1572
1573
#define ALT_SPIS_SR_RFNE_WIDTH 1
1574
1575
#define ALT_SPIS_SR_RFNE_SET_MSK 0x00000008
1576
1577
#define ALT_SPIS_SR_RFNE_CLR_MSK 0xfffffff7
1578
1579
#define ALT_SPIS_SR_RFNE_RESET 0x0
1580
1581
#define ALT_SPIS_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1582
1583
#define ALT_SPIS_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1584
1613
#define ALT_SPIS_SR_RFF_E_NOTFULL 0x0
1614
1619
#define ALT_SPIS_SR_RFF_E_FULL 0x1
1620
1622
#define ALT_SPIS_SR_RFF_LSB 4
1623
1624
#define ALT_SPIS_SR_RFF_MSB 4
1625
1626
#define ALT_SPIS_SR_RFF_WIDTH 1
1627
1628
#define ALT_SPIS_SR_RFF_SET_MSK 0x00000010
1629
1630
#define ALT_SPIS_SR_RFF_CLR_MSK 0xffffffef
1631
1632
#define ALT_SPIS_SR_RFF_RESET 0x0
1633
1634
#define ALT_SPIS_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1635
1636
#define ALT_SPIS_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1637
1670
#define ALT_SPIS_SR_TXE_E_NOERROR 0x0
1671
1676
#define ALT_SPIS_SR_TXE_E_ERROR 0x1
1677
1679
#define ALT_SPIS_SR_TXE_LSB 5
1680
1681
#define ALT_SPIS_SR_TXE_MSB 5
1682
1683
#define ALT_SPIS_SR_TXE_WIDTH 1
1684
1685
#define ALT_SPIS_SR_TXE_SET_MSK 0x00000020
1686
1687
#define ALT_SPIS_SR_TXE_CLR_MSK 0xffffffdf
1688
1689
#define ALT_SPIS_SR_TXE_RESET 0x0
1690
1691
#define ALT_SPIS_SR_TXE_GET(value) (((value) & 0x00000020) >> 5)
1692
1693
#define ALT_SPIS_SR_TXE_SET(value) (((value) << 5) & 0x00000020)
1694
1695
#ifndef __ASSEMBLY__
1696
1706
struct
ALT_SPIS_SR_s
1707
{
1708
const
uint32_t
busy
: 1;
1709
const
uint32_t
tfnf
: 1;
1710
const
uint32_t
tfe
: 1;
1711
const
uint32_t
rfne
: 1;
1712
const
uint32_t
rff
: 1;
1713
const
uint32_t
txe
: 1;
1714
uint32_t : 26;
1715
};
1716
1718
typedef
volatile
struct
ALT_SPIS_SR_s
ALT_SPIS_SR_t
;
1719
#endif
/* __ASSEMBLY__ */
1720
1722
#define ALT_SPIS_SR_RESET 0x00000006
1723
1724
#define ALT_SPIS_SR_OFST 0x28
1725
1726
#define ALT_SPIS_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SR_OFST))
1727
1769
#define ALT_SPIS_IMR_TXEIM_E_MSKED 0x0
1770
1775
#define ALT_SPIS_IMR_TXEIM_E_END 0x1
1776
1778
#define ALT_SPIS_IMR_TXEIM_LSB 0
1779
1780
#define ALT_SPIS_IMR_TXEIM_MSB 0
1781
1782
#define ALT_SPIS_IMR_TXEIM_WIDTH 1
1783
1784
#define ALT_SPIS_IMR_TXEIM_SET_MSK 0x00000001
1785
1786
#define ALT_SPIS_IMR_TXEIM_CLR_MSK 0xfffffffe
1787
1788
#define ALT_SPIS_IMR_TXEIM_RESET 0x1
1789
1790
#define ALT_SPIS_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1791
1792
#define ALT_SPIS_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1793
1818
#define ALT_SPIS_IMR_TXOIM_E_MSKED 0x0
1819
1824
#define ALT_SPIS_IMR_TXOIM_E_END 0x1
1825
1827
#define ALT_SPIS_IMR_TXOIM_LSB 1
1828
1829
#define ALT_SPIS_IMR_TXOIM_MSB 1
1830
1831
#define ALT_SPIS_IMR_TXOIM_WIDTH 1
1832
1833
#define ALT_SPIS_IMR_TXOIM_SET_MSK 0x00000002
1834
1835
#define ALT_SPIS_IMR_TXOIM_CLR_MSK 0xfffffffd
1836
1837
#define ALT_SPIS_IMR_TXOIM_RESET 0x1
1838
1839
#define ALT_SPIS_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1840
1841
#define ALT_SPIS_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1842
1867
#define ALT_SPIS_IMR_RXUIM_E_MSKED 0x0
1868
1873
#define ALT_SPIS_IMR_RXUIM_E_END 0x1
1874
1876
#define ALT_SPIS_IMR_RXUIM_LSB 2
1877
1878
#define ALT_SPIS_IMR_RXUIM_MSB 2
1879
1880
#define ALT_SPIS_IMR_RXUIM_WIDTH 1
1881
1882
#define ALT_SPIS_IMR_RXUIM_SET_MSK 0x00000004
1883
1884
#define ALT_SPIS_IMR_RXUIM_CLR_MSK 0xfffffffb
1885
1886
#define ALT_SPIS_IMR_RXUIM_RESET 0x1
1887
1888
#define ALT_SPIS_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1889
1890
#define ALT_SPIS_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1891
1916
#define ALT_SPIS_IMR_RXOIM_E_MSKED 0x0
1917
1922
#define ALT_SPIS_IMR_RXOIM_E_END 0x1
1923
1925
#define ALT_SPIS_IMR_RXOIM_LSB 3
1926
1927
#define ALT_SPIS_IMR_RXOIM_MSB 3
1928
1929
#define ALT_SPIS_IMR_RXOIM_WIDTH 1
1930
1931
#define ALT_SPIS_IMR_RXOIM_SET_MSK 0x00000008
1932
1933
#define ALT_SPIS_IMR_RXOIM_CLR_MSK 0xfffffff7
1934
1935
#define ALT_SPIS_IMR_RXOIM_RESET 0x1
1936
1937
#define ALT_SPIS_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1938
1939
#define ALT_SPIS_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1940
1965
#define ALT_SPIS_IMR_RXFIM_E_MSKED 0x0
1966
1971
#define ALT_SPIS_IMR_RXFIM_E_END 0x1
1972
1974
#define ALT_SPIS_IMR_RXFIM_LSB 4
1975
1976
#define ALT_SPIS_IMR_RXFIM_MSB 4
1977
1978
#define ALT_SPIS_IMR_RXFIM_WIDTH 1
1979
1980
#define ALT_SPIS_IMR_RXFIM_SET_MSK 0x00000010
1981
1982
#define ALT_SPIS_IMR_RXFIM_CLR_MSK 0xffffffef
1983
1984
#define ALT_SPIS_IMR_RXFIM_RESET 0x1
1985
1986
#define ALT_SPIS_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1987
1988
#define ALT_SPIS_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1989
1990
#ifndef __ASSEMBLY__
1991
2001
struct
ALT_SPIS_IMR_s
2002
{
2003
uint32_t
txeim
: 1;
2004
uint32_t
txoim
: 1;
2005
uint32_t
rxuim
: 1;
2006
uint32_t
rxoim
: 1;
2007
uint32_t
rxfim
: 1;
2008
uint32_t : 27;
2009
};
2010
2012
typedef
volatile
struct
ALT_SPIS_IMR_s
ALT_SPIS_IMR_t
;
2013
#endif
/* __ASSEMBLY__ */
2014
2016
#define ALT_SPIS_IMR_RESET 0x0000001f
2017
2018
#define ALT_SPIS_IMR_OFST 0x2c
2019
2020
#define ALT_SPIS_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IMR_OFST))
2021
2064
#define ALT_SPIS_ISR_TXEIS_E_INACT 0x0
2065
2070
#define ALT_SPIS_ISR_TXEIS_E_ACT 0x1
2071
2073
#define ALT_SPIS_ISR_TXEIS_LSB 0
2074
2075
#define ALT_SPIS_ISR_TXEIS_MSB 0
2076
2077
#define ALT_SPIS_ISR_TXEIS_WIDTH 1
2078
2079
#define ALT_SPIS_ISR_TXEIS_SET_MSK 0x00000001
2080
2081
#define ALT_SPIS_ISR_TXEIS_CLR_MSK 0xfffffffe
2082
2083
#define ALT_SPIS_ISR_TXEIS_RESET 0x0
2084
2085
#define ALT_SPIS_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2086
2087
#define ALT_SPIS_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2088
2114
#define ALT_SPIS_ISR_TXOIS_E_INACT 0x0
2115
2120
#define ALT_SPIS_ISR_TXOIS_E_ACT 0x1
2121
2123
#define ALT_SPIS_ISR_TXOIS_LSB 1
2124
2125
#define ALT_SPIS_ISR_TXOIS_MSB 1
2126
2127
#define ALT_SPIS_ISR_TXOIS_WIDTH 1
2128
2129
#define ALT_SPIS_ISR_TXOIS_SET_MSK 0x00000002
2130
2131
#define ALT_SPIS_ISR_TXOIS_CLR_MSK 0xfffffffd
2132
2133
#define ALT_SPIS_ISR_TXOIS_RESET 0x0
2134
2135
#define ALT_SPIS_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2136
2137
#define ALT_SPIS_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2138
2164
#define ALT_SPIS_ISR_RXUIS_E_INACT 0x0
2165
2170
#define ALT_SPIS_ISR_RXUIS_E_ACT 0x1
2171
2173
#define ALT_SPIS_ISR_RXUIS_LSB 2
2174
2175
#define ALT_SPIS_ISR_RXUIS_MSB 2
2176
2177
#define ALT_SPIS_ISR_RXUIS_WIDTH 1
2178
2179
#define ALT_SPIS_ISR_RXUIS_SET_MSK 0x00000004
2180
2181
#define ALT_SPIS_ISR_RXUIS_CLR_MSK 0xfffffffb
2182
2183
#define ALT_SPIS_ISR_RXUIS_RESET 0x0
2184
2185
#define ALT_SPIS_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2186
2187
#define ALT_SPIS_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2188
2214
#define ALT_SPIS_ISR_RXOIS_E_INACT 0x0
2215
2220
#define ALT_SPIS_ISR_RXOIS_E_ACT 0x1
2221
2223
#define ALT_SPIS_ISR_RXOIS_LSB 3
2224
2225
#define ALT_SPIS_ISR_RXOIS_MSB 3
2226
2227
#define ALT_SPIS_ISR_RXOIS_WIDTH 1
2228
2229
#define ALT_SPIS_ISR_RXOIS_SET_MSK 0x00000008
2230
2231
#define ALT_SPIS_ISR_RXOIS_CLR_MSK 0xfffffff7
2232
2233
#define ALT_SPIS_ISR_RXOIS_RESET 0x0
2234
2235
#define ALT_SPIS_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2236
2237
#define ALT_SPIS_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2238
2264
#define ALT_SPIS_ISR_RXFIS_E_INACT 0x0
2265
2270
#define ALT_SPIS_ISR_RXFIS_E_ACT 0x1
2271
2273
#define ALT_SPIS_ISR_RXFIS_LSB 4
2274
2275
#define ALT_SPIS_ISR_RXFIS_MSB 4
2276
2277
#define ALT_SPIS_ISR_RXFIS_WIDTH 1
2278
2279
#define ALT_SPIS_ISR_RXFIS_SET_MSK 0x00000010
2280
2281
#define ALT_SPIS_ISR_RXFIS_CLR_MSK 0xffffffef
2282
2283
#define ALT_SPIS_ISR_RXFIS_RESET 0x0
2284
2285
#define ALT_SPIS_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2286
2287
#define ALT_SPIS_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2288
2289
#ifndef __ASSEMBLY__
2290
2300
struct
ALT_SPIS_ISR_s
2301
{
2302
const
uint32_t
txeis
: 1;
2303
const
uint32_t
txois
: 1;
2304
const
uint32_t
rxuis
: 1;
2305
const
uint32_t
rxois
: 1;
2306
const
uint32_t
rxfis
: 1;
2307
uint32_t : 27;
2308
};
2309
2311
typedef
volatile
struct
ALT_SPIS_ISR_s
ALT_SPIS_ISR_t
;
2312
#endif
/* __ASSEMBLY__ */
2313
2315
#define ALT_SPIS_ISR_RESET 0x00000000
2316
2317
#define ALT_SPIS_ISR_OFST 0x30
2318
2319
#define ALT_SPIS_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ISR_OFST))
2320
2363
#define ALT_SPIS_RISR_TXEIR_E_INACT 0x0
2364
2369
#define ALT_SPIS_RISR_TXEIR_E_ACT 0x1
2370
2372
#define ALT_SPIS_RISR_TXEIR_LSB 0
2373
2374
#define ALT_SPIS_RISR_TXEIR_MSB 0
2375
2376
#define ALT_SPIS_RISR_TXEIR_WIDTH 1
2377
2378
#define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001
2379
2380
#define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe
2381
2382
#define ALT_SPIS_RISR_TXEIR_RESET 0x0
2383
2384
#define ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2385
2386
#define ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2387
2413
#define ALT_SPIS_RISR_TXOIR_E_INACT 0x0
2414
2419
#define ALT_SPIS_RISR_TXOIR_E_ACT 0x1
2420
2422
#define ALT_SPIS_RISR_TXOIR_LSB 1
2423
2424
#define ALT_SPIS_RISR_TXOIR_MSB 1
2425
2426
#define ALT_SPIS_RISR_TXOIR_WIDTH 1
2427
2428
#define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002
2429
2430
#define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd
2431
2432
#define ALT_SPIS_RISR_TXOIR_RESET 0x0
2433
2434
#define ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2435
2436
#define ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2437
2464
#define ALT_SPIS_RISR_RXUIR_E_INACT 0x0
2465
2470
#define ALT_SPIS_RISR_RXUIR_E_ACT 0x1
2471
2473
#define ALT_SPIS_RISR_RXUIR_LSB 2
2474
2475
#define ALT_SPIS_RISR_RXUIR_MSB 2
2476
2477
#define ALT_SPIS_RISR_RXUIR_WIDTH 1
2478
2479
#define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004
2480
2481
#define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb
2482
2483
#define ALT_SPIS_RISR_RXUIR_RESET 0x0
2484
2485
#define ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2486
2487
#define ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2488
2514
#define ALT_SPIS_RISR_RXOIR_E_INACT 0x0
2515
2520
#define ALT_SPIS_RISR_RXOIR_E_ACT 0x1
2521
2523
#define ALT_SPIS_RISR_RXOIR_LSB 3
2524
2525
#define ALT_SPIS_RISR_RXOIR_MSB 3
2526
2527
#define ALT_SPIS_RISR_RXOIR_WIDTH 1
2528
2529
#define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008
2530
2531
#define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7
2532
2533
#define ALT_SPIS_RISR_RXOIR_RESET 0x0
2534
2535
#define ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2536
2537
#define ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2538
2565
#define ALT_SPIS_RISR_RXFIR_E_INACT 0x0
2566
2571
#define ALT_SPIS_RISR_RXFIR_E_ACT 0x1
2572
2574
#define ALT_SPIS_RISR_RXFIR_LSB 4
2575
2576
#define ALT_SPIS_RISR_RXFIR_MSB 4
2577
2578
#define ALT_SPIS_RISR_RXFIR_WIDTH 1
2579
2580
#define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010
2581
2582
#define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef
2583
2584
#define ALT_SPIS_RISR_RXFIR_RESET 0x0
2585
2586
#define ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2587
2588
#define ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2589
2590
#ifndef __ASSEMBLY__
2591
2601
struct
ALT_SPIS_RISR_s
2602
{
2603
const
uint32_t
txeir
: 1;
2604
const
uint32_t
txoir
: 1;
2605
const
uint32_t
rxuir
: 1;
2606
const
uint32_t
rxoir
: 1;
2607
const
uint32_t
rxfir
: 1;
2608
uint32_t : 27;
2609
};
2610
2612
typedef
volatile
struct
ALT_SPIS_RISR_s
ALT_SPIS_RISR_t
;
2613
#endif
/* __ASSEMBLY__ */
2614
2616
#define ALT_SPIS_RISR_RESET 0x00000000
2617
2618
#define ALT_SPIS_RISR_OFST 0x34
2619
2620
#define ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST))
2621
2648
#define ALT_SPIS_TXOICR_TXOICR_LSB 0
2649
2650
#define ALT_SPIS_TXOICR_TXOICR_MSB 0
2651
2652
#define ALT_SPIS_TXOICR_TXOICR_WIDTH 1
2653
2654
#define ALT_SPIS_TXOICR_TXOICR_SET_MSK 0x00000001
2655
2656
#define ALT_SPIS_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2657
2658
#define ALT_SPIS_TXOICR_TXOICR_RESET 0x0
2659
2660
#define ALT_SPIS_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2661
2662
#define ALT_SPIS_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2663
2664
#ifndef __ASSEMBLY__
2665
2675
struct
ALT_SPIS_TXOICR_s
2676
{
2677
const
uint32_t
txoicr
: 1;
2678
uint32_t : 31;
2679
};
2680
2682
typedef
volatile
struct
ALT_SPIS_TXOICR_s
ALT_SPIS_TXOICR_t
;
2683
#endif
/* __ASSEMBLY__ */
2684
2686
#define ALT_SPIS_TXOICR_RESET 0x00000000
2687
2688
#define ALT_SPIS_TXOICR_OFST 0x38
2689
2690
#define ALT_SPIS_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXOICR_OFST))
2691
2718
#define ALT_SPIS_RXOICR_RXOICR_LSB 0
2719
2720
#define ALT_SPIS_RXOICR_RXOICR_MSB 0
2721
2722
#define ALT_SPIS_RXOICR_RXOICR_WIDTH 1
2723
2724
#define ALT_SPIS_RXOICR_RXOICR_SET_MSK 0x00000001
2725
2726
#define ALT_SPIS_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2727
2728
#define ALT_SPIS_RXOICR_RXOICR_RESET 0x0
2729
2730
#define ALT_SPIS_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2731
2732
#define ALT_SPIS_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2733
2734
#ifndef __ASSEMBLY__
2735
2745
struct
ALT_SPIS_RXOICR_s
2746
{
2747
const
uint32_t
rxoicr
: 1;
2748
uint32_t : 31;
2749
};
2750
2752
typedef
volatile
struct
ALT_SPIS_RXOICR_s
ALT_SPIS_RXOICR_t
;
2753
#endif
/* __ASSEMBLY__ */
2754
2756
#define ALT_SPIS_RXOICR_RESET 0x00000000
2757
2758
#define ALT_SPIS_RXOICR_OFST 0x3c
2759
2760
#define ALT_SPIS_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXOICR_OFST))
2761
2788
#define ALT_SPIS_RXUICR_RXUICR_LSB 0
2789
2790
#define ALT_SPIS_RXUICR_RXUICR_MSB 0
2791
2792
#define ALT_SPIS_RXUICR_RXUICR_WIDTH 1
2793
2794
#define ALT_SPIS_RXUICR_RXUICR_SET_MSK 0x00000001
2795
2796
#define ALT_SPIS_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2797
2798
#define ALT_SPIS_RXUICR_RXUICR_RESET 0x0
2799
2800
#define ALT_SPIS_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2801
2802
#define ALT_SPIS_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2803
2804
#ifndef __ASSEMBLY__
2805
2815
struct
ALT_SPIS_RXUICR_s
2816
{
2817
const
uint32_t
rxuicr
: 1;
2818
uint32_t : 31;
2819
};
2820
2822
typedef
volatile
struct
ALT_SPIS_RXUICR_s
ALT_SPIS_RXUICR_t
;
2823
#endif
/* __ASSEMBLY__ */
2824
2826
#define ALT_SPIS_RXUICR_RESET 0x00000000
2827
2828
#define ALT_SPIS_RXUICR_OFST 0x40
2829
2830
#define ALT_SPIS_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RXUICR_OFST))
2831
2858
#define ALT_SPIS_MSTICR_MSTICR_LSB 0
2859
2860
#define ALT_SPIS_MSTICR_MSTICR_MSB 0
2861
2862
#define ALT_SPIS_MSTICR_MSTICR_WIDTH 1
2863
2864
#define ALT_SPIS_MSTICR_MSTICR_SET_MSK 0x00000001
2865
2866
#define ALT_SPIS_MSTICR_MSTICR_CLR_MSK 0xfffffffe
2867
2868
#define ALT_SPIS_MSTICR_MSTICR_RESET 0x0
2869
2870
#define ALT_SPIS_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
2871
2872
#define ALT_SPIS_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
2873
2874
#ifndef __ASSEMBLY__
2875
2885
struct
ALT_SPIS_MSTICR_s
2886
{
2887
const
uint32_t
msticr
: 1;
2888
uint32_t : 31;
2889
};
2890
2892
typedef
volatile
struct
ALT_SPIS_MSTICR_s
ALT_SPIS_MSTICR_t
;
2893
#endif
/* __ASSEMBLY__ */
2894
2896
#define ALT_SPIS_MSTICR_RESET 0x00000000
2897
2898
#define ALT_SPIS_MSTICR_OFST 0x44
2899
2900
#define ALT_SPIS_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_MSTICR_OFST))
2901
2930
#define ALT_SPIS_ICR_ICR_LSB 0
2931
2932
#define ALT_SPIS_ICR_ICR_MSB 0
2933
2934
#define ALT_SPIS_ICR_ICR_WIDTH 1
2935
2936
#define ALT_SPIS_ICR_ICR_SET_MSK 0x00000001
2937
2938
#define ALT_SPIS_ICR_ICR_CLR_MSK 0xfffffffe
2939
2940
#define ALT_SPIS_ICR_ICR_RESET 0x0
2941
2942
#define ALT_SPIS_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2943
2944
#define ALT_SPIS_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2945
2946
#ifndef __ASSEMBLY__
2947
2957
struct
ALT_SPIS_ICR_s
2958
{
2959
const
uint32_t
icr
: 1;
2960
uint32_t : 31;
2961
};
2962
2964
typedef
volatile
struct
ALT_SPIS_ICR_s
ALT_SPIS_ICR_t
;
2965
#endif
/* __ASSEMBLY__ */
2966
2968
#define ALT_SPIS_ICR_RESET 0x00000000
2969
2970
#define ALT_SPIS_ICR_OFST 0x48
2971
2972
#define ALT_SPIS_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_ICR_OFST))
2973
3026
#define ALT_SPIS_DMACR_RDMAE_E_DISD 0x0
3027
3032
#define ALT_SPIS_DMACR_RDMAE_E_END 0x1
3033
3035
#define ALT_SPIS_DMACR_RDMAE_LSB 0
3036
3037
#define ALT_SPIS_DMACR_RDMAE_MSB 0
3038
3039
#define ALT_SPIS_DMACR_RDMAE_WIDTH 1
3040
3041
#define ALT_SPIS_DMACR_RDMAE_SET_MSK 0x00000001
3042
3043
#define ALT_SPIS_DMACR_RDMAE_CLR_MSK 0xfffffffe
3044
3045
#define ALT_SPIS_DMACR_RDMAE_RESET 0x0
3046
3047
#define ALT_SPIS_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3048
3049
#define ALT_SPIS_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3050
3077
#define ALT_SPIS_DMACR_TDMAE_E_DISD 0x0
3078
3083
#define ALT_SPIS_DMACR_TDMAE_E_END 0x1
3084
3086
#define ALT_SPIS_DMACR_TDMAE_LSB 1
3087
3088
#define ALT_SPIS_DMACR_TDMAE_MSB 1
3089
3090
#define ALT_SPIS_DMACR_TDMAE_WIDTH 1
3091
3092
#define ALT_SPIS_DMACR_TDMAE_SET_MSK 0x00000002
3093
3094
#define ALT_SPIS_DMACR_TDMAE_CLR_MSK 0xfffffffd
3095
3096
#define ALT_SPIS_DMACR_TDMAE_RESET 0x0
3097
3098
#define ALT_SPIS_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3099
3100
#define ALT_SPIS_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3101
3102
#ifndef __ASSEMBLY__
3103
3113
struct
ALT_SPIS_DMACR_s
3114
{
3115
uint32_t
rdmae
: 1;
3116
uint32_t
tdmae
: 1;
3117
uint32_t : 30;
3118
};
3119
3121
typedef
volatile
struct
ALT_SPIS_DMACR_s
ALT_SPIS_DMACR_t
;
3122
#endif
/* __ASSEMBLY__ */
3123
3125
#define ALT_SPIS_DMACR_RESET 0x00000000
3126
3127
#define ALT_SPIS_DMACR_OFST 0x4c
3128
3129
#define ALT_SPIS_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMACR_OFST))
3130
3171
#define ALT_SPIS_DMATDLR_DMATDL_LSB 0
3172
3173
#define ALT_SPIS_DMATDLR_DMATDL_MSB 7
3174
3175
#define ALT_SPIS_DMATDLR_DMATDL_WIDTH 8
3176
3177
#define ALT_SPIS_DMATDLR_DMATDL_SET_MSK 0x000000ff
3178
3179
#define ALT_SPIS_DMATDLR_DMATDL_CLR_MSK 0xffffff00
3180
3181
#define ALT_SPIS_DMATDLR_DMATDL_RESET 0x0
3182
3183
#define ALT_SPIS_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
3184
3185
#define ALT_SPIS_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
3186
3187
#ifndef __ASSEMBLY__
3188
3198
struct
ALT_SPIS_DMATDLR_s
3199
{
3200
uint32_t
dmatdl
: 8;
3201
uint32_t : 24;
3202
};
3203
3205
typedef
volatile
struct
ALT_SPIS_DMATDLR_s
ALT_SPIS_DMATDLR_t
;
3206
#endif
/* __ASSEMBLY__ */
3207
3209
#define ALT_SPIS_DMATDLR_RESET 0x00000000
3210
3211
#define ALT_SPIS_DMATDLR_OFST 0x50
3212
3213
#define ALT_SPIS_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMATDLR_OFST))
3214
3253
#define ALT_SPIS_DMARDLR_DMARDL_LSB 0
3254
3255
#define ALT_SPIS_DMARDLR_DMARDL_MSB 7
3256
3257
#define ALT_SPIS_DMARDLR_DMARDL_WIDTH 8
3258
3259
#define ALT_SPIS_DMARDLR_DMARDL_SET_MSK 0x000000ff
3260
3261
#define ALT_SPIS_DMARDLR_DMARDL_CLR_MSK 0xffffff00
3262
3263
#define ALT_SPIS_DMARDLR_DMARDL_RESET 0x0
3264
3265
#define ALT_SPIS_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
3266
3267
#define ALT_SPIS_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
3268
3269
#ifndef __ASSEMBLY__
3270
3280
struct
ALT_SPIS_DMARDLR_s
3281
{
3282
uint32_t
dmardl
: 8;
3283
uint32_t : 24;
3284
};
3285
3287
typedef
volatile
struct
ALT_SPIS_DMARDLR_s
ALT_SPIS_DMARDLR_t
;
3288
#endif
/* __ASSEMBLY__ */
3289
3291
#define ALT_SPIS_DMARDLR_RESET 0x00000000
3292
3293
#define ALT_SPIS_DMARDLR_OFST 0x54
3294
3295
#define ALT_SPIS_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DMARDLR_OFST))
3296
3322
#define ALT_SPIS_IDR_IDR_LSB 0
3323
3324
#define ALT_SPIS_IDR_IDR_MSB 31
3325
3326
#define ALT_SPIS_IDR_IDR_WIDTH 32
3327
3328
#define ALT_SPIS_IDR_IDR_SET_MSK 0xffffffff
3329
3330
#define ALT_SPIS_IDR_IDR_CLR_MSK 0x00000000
3331
3332
#define ALT_SPIS_IDR_IDR_RESET 0x5510005
3333
3334
#define ALT_SPIS_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
3335
3336
#define ALT_SPIS_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
3337
3338
#ifndef __ASSEMBLY__
3339
3349
struct
ALT_SPIS_IDR_s
3350
{
3351
const
uint32_t
idr
: 32;
3352
};
3353
3355
typedef
volatile
struct
ALT_SPIS_IDR_s
ALT_SPIS_IDR_t
;
3356
#endif
/* __ASSEMBLY__ */
3357
3359
#define ALT_SPIS_IDR_RESET 0x05510005
3360
3361
#define ALT_SPIS_IDR_OFST 0x58
3362
3363
#define ALT_SPIS_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_IDR_OFST))
3364
3387
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_LSB 0
3388
3389
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_MSB 31
3390
3391
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3392
3393
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3394
3395
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3396
3397
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_RESET 0x3332322a
3398
3399
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3400
3401
#define ALT_SPIS_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3402
3403
#ifndef __ASSEMBLY__
3404
3414
struct
ALT_SPIS_SPI_VER_ID_s
3415
{
3416
uint32_t
spi_version_id
: 32;
3417
};
3418
3420
typedef
volatile
struct
ALT_SPIS_SPI_VER_ID_s
ALT_SPIS_SPI_VER_ID_t
;
3421
#endif
/* __ASSEMBLY__ */
3422
3424
#define ALT_SPIS_SPI_VER_ID_RESET 0x3332322a
3425
3426
#define ALT_SPIS_SPI_VER_ID_OFST 0x5c
3427
3428
#define ALT_SPIS_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_SPI_VER_ID_OFST))
3429
3468
#define ALT_SPIS_DR_DR_LSB 0
3469
3470
#define ALT_SPIS_DR_DR_MSB 15
3471
3472
#define ALT_SPIS_DR_DR_WIDTH 16
3473
3474
#define ALT_SPIS_DR_DR_SET_MSK 0x0000ffff
3475
3476
#define ALT_SPIS_DR_DR_CLR_MSK 0xffff0000
3477
3478
#define ALT_SPIS_DR_DR_RESET 0x0
3479
3480
#define ALT_SPIS_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3481
3482
#define ALT_SPIS_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3483
3484
#ifndef __ASSEMBLY__
3485
3495
struct
ALT_SPIS_DR_s
3496
{
3497
uint32_t
dr
: 16;
3498
uint32_t : 16;
3499
};
3500
3502
typedef
volatile
struct
ALT_SPIS_DR_s
ALT_SPIS_DR_t
;
3503
#endif
/* __ASSEMBLY__ */
3504
3506
#define ALT_SPIS_DR_RESET 0x00000000
3507
3508
#define ALT_SPIS_DR_OFST 0x60
3509
3510
#define ALT_SPIS_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_DR_OFST))
3511
3512
#ifndef __ASSEMBLY__
3513
3523
struct
ALT_SPIS_s
3524
{
3525
volatile
ALT_SPIS_CTLR0_t
ctrlr0
;
3526
volatile
uint32_t
_pad_0x4_0x7
;
3527
volatile
ALT_SPIS_SPIENR_t
spienr
;
3528
volatile
ALT_SPIS_MWCR_t
mwcr
;
3529
volatile
uint32_t
_pad_0x10_0x17
[2];
3530
volatile
ALT_SPIS_TXFTLR_t
txftlr
;
3531
volatile
ALT_SPIS_RXFTLR_t
rxftlr
;
3532
volatile
ALT_SPIS_TXFLR_t
txflr
;
3533
volatile
ALT_SPIS_RXFLR_t
rxflr
;
3534
volatile
ALT_SPIS_SR_t
sr
;
3535
volatile
ALT_SPIS_IMR_t
imr
;
3536
volatile
ALT_SPIS_ISR_t
isr
;
3537
volatile
ALT_SPIS_RISR_t
risr
;
3538
volatile
ALT_SPIS_TXOICR_t
txoicr
;
3539
volatile
ALT_SPIS_RXOICR_t
rxoicr
;
3540
volatile
ALT_SPIS_RXUICR_t
rxuicr
;
3541
volatile
ALT_SPIS_MSTICR_t
msticr
;
3542
volatile
ALT_SPIS_ICR_t
icr
;
3543
volatile
ALT_SPIS_DMACR_t
dmacr
;
3544
volatile
ALT_SPIS_DMATDLR_t
dmatdlr
;
3545
volatile
ALT_SPIS_DMARDLR_t
dmardlr
;
3546
volatile
ALT_SPIS_IDR_t
idr
;
3547
volatile
ALT_SPIS_SPI_VER_ID_t
spi_version_id
;
3548
volatile
ALT_SPIS_DR_t
dr
;
3549
volatile
uint32_t
_pad_0x64_0x80
[7];
3550
};
3551
3553
typedef
volatile
struct
ALT_SPIS_s
ALT_SPIS_t
;
3555
struct
ALT_SPIS_raw_s
3556
{
3557
volatile
uint32_t
ctrlr0
;
3558
volatile
uint32_t
_pad_0x4_0x7
;
3559
volatile
uint32_t
spienr
;
3560
volatile
uint32_t
mwcr
;
3561
volatile
uint32_t
_pad_0x10_0x17
[2];
3562
volatile
uint32_t
txftlr
;
3563
volatile
uint32_t
rxftlr
;
3564
volatile
uint32_t
txflr
;
3565
volatile
uint32_t
rxflr
;
3566
volatile
uint32_t
sr
;
3567
volatile
uint32_t
imr
;
3568
volatile
uint32_t
isr
;
3569
volatile
uint32_t
risr
;
3570
volatile
uint32_t
txoicr
;
3571
volatile
uint32_t
rxoicr
;
3572
volatile
uint32_t
rxuicr
;
3573
volatile
uint32_t
msticr
;
3574
volatile
uint32_t
icr
;
3575
volatile
uint32_t
dmacr
;
3576
volatile
uint32_t
dmatdlr
;
3577
volatile
uint32_t
dmardlr
;
3578
volatile
uint32_t
idr
;
3579
volatile
uint32_t
spi_version_id
;
3580
volatile
uint32_t
dr
;
3581
volatile
uint32_t
_pad_0x64_0x80
[7];
3582
};
3583
3585
typedef
volatile
struct
ALT_SPIS_raw_s
ALT_SPIS_raw_t
;
3586
#endif
/* __ASSEMBLY__ */
3587
3589
#ifdef __cplusplus
3590
}
3591
#endif
/* __cplusplus */
3592
#endif
/* __ALT_SOCAL_SPIS_H__ */
3593
include
soc_a10
socal
alt_spis.h
Generated on Tue Sep 8 2015 13:33:04 for Altera SoCAL by
1.8.2