Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ctrl

Description

The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de- assert the warm reset.

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Software Cold Reset Request
[1] RW 0x0 Software Warm Reset Request
[3:2] ??? 0x0 UNDEFINED
[4] RW 0x0 SDRAM Self-Refresh Enable
[5] RW 0x0 SDRAM Self-Refresh Request
[6] R 0x0 SDRAM Self-Refresh Acknowledge
[7] ??? 0x0 UNDEFINED
[8] RW 0x0 FPGA Manager Handshake Enable
[9] RW 0x0 FPGA Manager Handshake Request
[10] R Unknown FPGA Manager Handshake Acknowledge
[11] ??? 0x0 UNDEFINED
[12] RW 0x0 SCAN Manager Handshake Enable
[13] RW 0x0 SCAN Manager Handshake Request
[14] R Unknown SCAN Manager Handshake Acknowledge
[15] ??? 0x0 UNDEFINED
[16] RW 0x0 FPGA Handshake Enable
[17] RW 0x0 FPGA Handshake Request
[18] R Unknown FPGA Handshake Acknowledge
[19] ??? 0x0 UNDEFINED
[20] RW 0x1 ETR (Embedded Trace Router) Stall Enable
[21] RW 0x0 ETR (Embedded Trace Router) Stall Request
[22] R 0x0 ETR (Embedded Trace Router) Stall Acknowledge
[23] RW 0x0 ETR (Embedded Trace Router) Stall After Warm Reset
[31:24] ??? 0x0 UNDEFINED

Field : Software Cold Reset Request - swcoldrstreq

This is a one-shot bit written by software to 1 to trigger a cold reset. It always reads the value 0.

Field Access Macros:

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB   0
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB   0
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK   0x00000001
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Software Warm Reset Request - swwarmrstreq

This is a one-shot bit written by software to 1 to trigger a hardware sequenced warm reset. It always reads the value 0.

Field Access Macros:

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB   1
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB   1
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK   0x00000002
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET(value)   (((value) << 1) & 0x00000002)
 

Field : SDRAM Self-Refresh Enable - sdrselfrefen

This field controls whether the contents of SDRAM devices survive a hardware sequenced warm reset. If set to 1, the Reset Manager makes a request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before asserting warm reset signals. However, if SDRAM is already in warm reset, Handshake with SDRAM is not performed.

Field Access Macros:

#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB   4
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB   4
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH   1
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK   0x00000010
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK   0xffffffef
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET   0x0
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET(value)   (((value) << 4) & 0x00000010)
 

Field : SDRAM Self-Refresh Request - sdrselfrefreq

Software writes this field 1 to request to the SDRAM Controller Subsystem that it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM contents across a software warm reset.

Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted.

Field Access Macros:

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB   5
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB   5
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK   0x00000020
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK   0xffffffdf
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET(value)   (((value) << 5) & 0x00000020)
 

Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack

This is the acknowlege for a SDRAM self-refresh mode request initiated by the SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put the SDRAM devices into self-refresh mode.

Field Access Macros:

#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB   6
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB   6
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH   1
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK   0x00000040
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK   0xffffffbf
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET   0x0
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET(value)   (((value) << 6) & 0x00000040)
 

Field : FPGA Manager Handshake Enable - fpgamgrhsen

Enables a handshake between the Reset Manager and FPGA Manager before a warm reset. The handshake is used to warn the FPGA Manager that a warm reset it coming so it can prepare for it. When the FPGA Manager receives a warm reset handshake, the FPGA Manager drives its output clock to a quiescent state to avoid glitches.

If set to 1, the Manager makes a request to the FPGA Managerbefore asserting warm reset signals. However if the FPGA Manager is already in warm reset, the handshake is skipped.

If set to 0, the handshake is skipped.

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB   8
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB   8
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK   0x00000100
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK   0xfffffeff
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : FPGA Manager Handshake Request - fpgamgrhsreq

Software writes this field 1 to request to the FPGA Manager to idle its output clock.

Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so software should timeout in this case.

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB   9
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB   9
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK   0x00000200
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK   0xfffffdff
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET(value)   (((value) << 9) & 0x00000200)
 

Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack

This is the acknowlege (high active) that the FPGA manager has successfully idled its output clock.

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB   10
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB   10
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK   0x00000400
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK   0xfffffbff
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET(value)   (((value) << 10) & 0x00000400)
 

Field : SCAN Manager Handshake Enable - scanmgrhsen

Enables a handshake between the Reset Manager and Scan Manager before a warm reset. The handshake is used to warn the Scan Manager that a warm reset it coming so it can prepare for it. When the Scan Manager receives a warm reset handshake, the Scan Manager drives its output clocks to a quiescent state to avoid glitches.

If set to 1, the Reset Manager makes a request to the Scan Managerbefore asserting warm reset signals. However if the Scan Manager is already in warm reset, the handshake is skipped.

If set to 0, the handshake is skipped.

Field Access Macros:

#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB   12
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB   12
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH   1
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK   0x00001000
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK   0xffffefff
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET   0x0
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET(value)   (((value) << 12) & 0x00001000)
 

Field : SCAN Manager Handshake Request - scanmgrhsreq

Software writes this field 1 to request to the SCAN manager to idle its output clocks.

Software waits for the SCANMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the Scan Manager to never assert SCANMGRHSACK (e.g. its input clock is disabled) so software should timeout in this case.

Field Access Macros:

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB   13
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB   13
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK   0x00002000
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK   0xffffdfff
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET(value)   (((value) << 13) & 0x00002000)
 

Field : SCAN Manager Handshake Acknowledge - scanmgrhsack

This is the acknowlege (high active) that the SCAN manager has successfully idled its output clocks.

Field Access Macros:

#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB   14
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB   14
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH   1
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK   0x00004000
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK   0xffffbfff
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET   0x0
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET(value)   (((value) << 14) & 0x00004000)
 

Field : FPGA Handshake Enable - fpgahsen

This field controls whether to perform handshake with FPGA before asserting warm reset.

If set to 1, the Reset Manager makes a request to the FPGAbefore asserting warm reset signals. However if FPGA is already in warm reset state, the handshake is not performed.

If set to 0, the handshake is not performed

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAHSEN_LSB   16
 
#define ALT_RSTMGR_CTL_FPGAHSEN_MSB   16
 
#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK   0x00010000
 
#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK   0xfffeffff
 
#define ALT_RSTMGR_CTL_FPGAHSEN_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAHSEN_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_RSTMGR_CTL_FPGAHSEN_SET(value)   (((value) << 16) & 0x00010000)
 

Field : FPGA Handshake Request - fpgahsreq

Software writes this field 1 to initiate handshake request to FPGA .

Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case.

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB   17
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB   17
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK   0x00020000
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK   0xfffdffff
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_RSTMGR_CTL_FPGAHSREQ_SET(value)   (((value) << 17) & 0x00020000)
 

Field : FPGA Handshake Acknowledge - fpgahsack

This is the acknowlege (high active) that the FPGA handshake acknowledge has been received by Reset Manager.

Field Access Macros:

#define ALT_RSTMGR_CTL_FPGAHSACK_LSB   18
 
#define ALT_RSTMGR_CTL_FPGAHSACK_MSB   18
 
#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH   1
 
#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK   0x00040000
 
#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK   0xfffbffff
 
#define ALT_RSTMGR_CTL_FPGAHSACK_RESET   0x0
 
#define ALT_RSTMGR_CTL_FPGAHSACK_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_RSTMGR_CTL_FPGAHSACK_SET(value)   (((value) << 18) & 0x00040000)
 

Field : ETR (Embedded Trace Router) Stall Enable - etrstallen

This field controls whether the ETR is requested to idle its AXI master interface (i.e. finish outstanding transactions and not initiate any more) to the L3 Interconnect before a warm or debug reset. If set to 1, the Reset Manager makes a request to the ETR to stall its AXI master and waits for it to finish any outstanding AXI transactions before a warm reset of the L3 Interconnect or a debug reset of the ETR. This stalling is required because the debug logic (including the ETR) is reset on a debug reset and the ETR AXI master is connected to the L3 Interconnect which is reset on a warm reset and these resets can happen independently.

Field Access Macros:

#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB   20
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB   20
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH   1
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK   0x00100000
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK   0xffefffff
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET   0x1
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_RSTMGR_CTL_ETRSTALLEN_SET(value)   (((value) << 20) & 0x00100000)
 

Field : ETR (Embedded Trace Router) Stall Request - etrstallreq

Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect.

Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted.

Field Access Macros:

#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB   21
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB   21
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH   1
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK   0x00200000
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK   0xffdfffff
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET   0x0
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET(value)   (((value) << 21) & 0x00200000)
 

Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack

This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ field. A 1 indicates that the ETR has stalled its AXI master

Field Access Macros:

#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB   22
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB   22
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH   1
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK   0x00400000
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK   0xffbfffff
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET   0x0
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_RSTMGR_CTL_ETRSTALLACK_SET(value)   (((value) << 22) & 0x00400000)
 

Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst

If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master is pending. Hardware leaves the ETR stalled until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.

Field Access Macros:

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB   23
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB   23
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH   1
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK   0x00800000
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK   0xff7fffff
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET   0x0
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET(value)   (((value) << 23) & 0x00800000)
 

Data Structures

struct  ALT_RSTMGR_CTL_s
 

Macros

#define ALT_RSTMGR_CTL_OFST   0x4
 

Typedefs

typedef struct ALT_RSTMGR_CTL_s ALT_RSTMGR_CTL_t
 

Data Structure Documentation

struct ALT_RSTMGR_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_CTL.

Data Fields
uint32_t swcoldrstreq: 1 Software Cold Reset Request
uint32_t swwarmrstreq: 1 Software Warm Reset Request
uint32_t __pad0__: 2 UNDEFINED
uint32_t sdrselfrefen: 1 SDRAM Self-Refresh Enable
uint32_t sdrselfrefreq: 1 SDRAM Self-Refresh Request
const uint32_t sdrselfreqack: 1 SDRAM Self-Refresh Acknowledge
uint32_t __pad1__: 1 UNDEFINED
uint32_t fpgamgrhsen: 1 FPGA Manager Handshake Enable
uint32_t fpgamgrhsreq: 1 FPGA Manager Handshake Request
const uint32_t fpgamgrhsack: 1 FPGA Manager Handshake Acknowledge
uint32_t __pad2__: 1 UNDEFINED
uint32_t scanmgrhsen: 1 SCAN Manager Handshake Enable
uint32_t scanmgrhsreq: 1 SCAN Manager Handshake Request
const uint32_t scanmgrhsack: 1 SCAN Manager Handshake Acknowledge
uint32_t __pad3__: 1 UNDEFINED
uint32_t fpgahsen: 1 FPGA Handshake Enable
uint32_t fpgahsreq: 1 FPGA Handshake Request
const uint32_t fpgahsack: 1 FPGA Handshake Acknowledge
uint32_t __pad4__: 1 UNDEFINED
uint32_t etrstallen: 1 ETR (Embedded Trace Router) Stall Enable
uint32_t etrstallreq: 1 ETR (Embedded Trace Router) Stall Request
const uint32_t etrstallack: 1 ETR (Embedded Trace Router) Stall Acknowledge
uint32_t etrstallwarmrst: 1 ETR (Embedded Trace Router) Stall After Warm Reset
uint32_t __pad5__: 8 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SWCOLDRSTREQ register field.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_CTL_SWCOLDRSTREQ field value from a register.

#define ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_CTL_SWCOLDRSTREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_CTL_SWWARMRSTREQ register field value.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SWWARMRSTREQ register field.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_CTL_SWWARMRSTREQ field value from a register.

#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_CTL_SWWARMRSTREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_LSB   4

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_MSB   4

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFEN register field.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFEN register field.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET_MSK   0x00000010

The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFEN register field value.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_CLR_MSK   0xffffffef

The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFEN register field value.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SDRSELFREFEN register field.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_RSTMGR_CTL_SDRSELFREFEN field value from a register.

#define ALT_RSTMGR_CTL_SDRSELFREFEN_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_RSTMGR_CTL_SDRSELFREFEN register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_LSB   5

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_MSB   5

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET_MSK   0x00000020

The mask used to set the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_CLR_MSK   0xffffffdf

The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREFREQ register field value.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SDRSELFREFREQ register field.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_RSTMGR_CTL_SDRSELFREFREQ field value from a register.

#define ALT_RSTMGR_CTL_SDRSELFREFREQ_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_RSTMGR_CTL_SDRSELFREFREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_LSB   6

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_MSB   6

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SDRSELFREQACK register field.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SDRSELFREQACK register field.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET_MSK   0x00000040

The mask used to set the ALT_RSTMGR_CTL_SDRSELFREQACK register field value.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_CLR_MSK   0xffffffbf

The mask used to clear the ALT_RSTMGR_CTL_SDRSELFREQACK register field value.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SDRSELFREQACK register field.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_RSTMGR_CTL_SDRSELFREQACK field value from a register.

#define ALT_RSTMGR_CTL_SDRSELFREQACK_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_RSTMGR_CTL_SDRSELFREQACK register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_LSB   8

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_MSB   8

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET_MSK   0x00000100

The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSEN register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSEN register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_RSTMGR_CTL_FPGAMGRHSEN field value from a register.

#define ALT_RSTMGR_CTL_FPGAMGRHSEN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_RSTMGR_CTL_FPGAMGRHSEN register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_LSB   9

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_MSB   9

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET_MSK   0x00000200

The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_CLR_MSK   0xfffffdff

The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_RSTMGR_CTL_FPGAMGRHSREQ field value from a register.

#define ALT_RSTMGR_CTL_FPGAMGRHSREQ_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_RSTMGR_CTL_FPGAMGRHSREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_LSB   10

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_MSB   10

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET_MSK   0x00000400

The mask used to set the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_CLR_MSK   0xfffffbff

The mask used to clear the ALT_RSTMGR_CTL_FPGAMGRHSACK register field value.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAMGRHSACK register field is UNKNOWN.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_RSTMGR_CTL_FPGAMGRHSACK field value from a register.

#define ALT_RSTMGR_CTL_FPGAMGRHSACK_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_RSTMGR_CTL_FPGAMGRHSACK register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_LSB   12

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_MSB   12

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSEN register field.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSEN register field.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET_MSK   0x00001000

The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSEN register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_CLR_MSK   0xffffefff

The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSEN register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SCANMGRHSEN register field.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_RSTMGR_CTL_SCANMGRHSEN field value from a register.

#define ALT_RSTMGR_CTL_SCANMGRHSEN_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_RSTMGR_CTL_SCANMGRHSEN register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_LSB   13

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_MSB   13

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET_MSK   0x00002000

The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_CLR_MSK   0xffffdfff

The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSREQ register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SCANMGRHSREQ register field.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_RSTMGR_CTL_SCANMGRHSREQ field value from a register.

#define ALT_RSTMGR_CTL_SCANMGRHSREQ_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_RSTMGR_CTL_SCANMGRHSREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_LSB   14

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_MSB   14

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_SCANMGRHSACK register field.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_SCANMGRHSACK register field.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET_MSK   0x00004000

The mask used to set the ALT_RSTMGR_CTL_SCANMGRHSACK register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_CLR_MSK   0xffffbfff

The mask used to clear the ALT_RSTMGR_CTL_SCANMGRHSACK register field value.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_SCANMGRHSACK register field is UNKNOWN.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_RSTMGR_CTL_SCANMGRHSACK field value from a register.

#define ALT_RSTMGR_CTL_SCANMGRHSACK_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_RSTMGR_CTL_SCANMGRHSACK register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAHSEN_LSB   16

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field.

#define ALT_RSTMGR_CTL_FPGAHSEN_MSB   16

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSEN register field.

#define ALT_RSTMGR_CTL_FPGAHSEN_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAHSEN register field.

#define ALT_RSTMGR_CTL_FPGAHSEN_SET_MSK   0x00010000

The mask used to set the ALT_RSTMGR_CTL_FPGAHSEN register field value.

#define ALT_RSTMGR_CTL_FPGAHSEN_CLR_MSK   0xfffeffff

The mask used to clear the ALT_RSTMGR_CTL_FPGAHSEN register field value.

#define ALT_RSTMGR_CTL_FPGAHSEN_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAHSEN register field.

#define ALT_RSTMGR_CTL_FPGAHSEN_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_RSTMGR_CTL_FPGAHSEN field value from a register.

#define ALT_RSTMGR_CTL_FPGAHSEN_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_RSTMGR_CTL_FPGAHSEN register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAHSREQ_LSB   17

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAHSREQ_MSB   17

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAHSREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAHSREQ_SET_MSK   0x00020000

The mask used to set the ALT_RSTMGR_CTL_FPGAHSREQ register field value.

#define ALT_RSTMGR_CTL_FPGAHSREQ_CLR_MSK   0xfffdffff

The mask used to clear the ALT_RSTMGR_CTL_FPGAHSREQ register field value.

#define ALT_RSTMGR_CTL_FPGAHSREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAHSREQ register field.

#define ALT_RSTMGR_CTL_FPGAHSREQ_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_RSTMGR_CTL_FPGAHSREQ field value from a register.

#define ALT_RSTMGR_CTL_FPGAHSREQ_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_RSTMGR_CTL_FPGAHSREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_FPGAHSACK_LSB   18

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field.

#define ALT_RSTMGR_CTL_FPGAHSACK_MSB   18

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_FPGAHSACK register field.

#define ALT_RSTMGR_CTL_FPGAHSACK_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_FPGAHSACK register field.

#define ALT_RSTMGR_CTL_FPGAHSACK_SET_MSK   0x00040000

The mask used to set the ALT_RSTMGR_CTL_FPGAHSACK register field value.

#define ALT_RSTMGR_CTL_FPGAHSACK_CLR_MSK   0xfffbffff

The mask used to clear the ALT_RSTMGR_CTL_FPGAHSACK register field value.

#define ALT_RSTMGR_CTL_FPGAHSACK_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_FPGAHSACK register field is UNKNOWN.

#define ALT_RSTMGR_CTL_FPGAHSACK_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_RSTMGR_CTL_FPGAHSACK field value from a register.

#define ALT_RSTMGR_CTL_FPGAHSACK_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_RSTMGR_CTL_FPGAHSACK register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_ETRSTALLEN_LSB   20

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field.

#define ALT_RSTMGR_CTL_ETRSTALLEN_MSB   20

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLEN register field.

#define ALT_RSTMGR_CTL_ETRSTALLEN_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_ETRSTALLEN register field.

#define ALT_RSTMGR_CTL_ETRSTALLEN_SET_MSK   0x00100000

The mask used to set the ALT_RSTMGR_CTL_ETRSTALLEN register field value.

#define ALT_RSTMGR_CTL_ETRSTALLEN_CLR_MSK   0xffefffff

The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLEN register field value.

#define ALT_RSTMGR_CTL_ETRSTALLEN_RESET   0x1

The reset value of the ALT_RSTMGR_CTL_ETRSTALLEN register field.

#define ALT_RSTMGR_CTL_ETRSTALLEN_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_RSTMGR_CTL_ETRSTALLEN field value from a register.

#define ALT_RSTMGR_CTL_ETRSTALLEN_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_RSTMGR_CTL_ETRSTALLEN register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_LSB   21

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_MSB   21

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLREQ register field.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_ETRSTALLREQ register field.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET_MSK   0x00200000

The mask used to set the ALT_RSTMGR_CTL_ETRSTALLREQ register field value.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_CLR_MSK   0xffdfffff

The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLREQ register field value.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_ETRSTALLREQ register field.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_RSTMGR_CTL_ETRSTALLREQ field value from a register.

#define ALT_RSTMGR_CTL_ETRSTALLREQ_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_RSTMGR_CTL_ETRSTALLREQ register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_ETRSTALLACK_LSB   22

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field.

#define ALT_RSTMGR_CTL_ETRSTALLACK_MSB   22

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLACK register field.

#define ALT_RSTMGR_CTL_ETRSTALLACK_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_ETRSTALLACK register field.

#define ALT_RSTMGR_CTL_ETRSTALLACK_SET_MSK   0x00400000

The mask used to set the ALT_RSTMGR_CTL_ETRSTALLACK register field value.

#define ALT_RSTMGR_CTL_ETRSTALLACK_CLR_MSK   0xffbfffff

The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLACK register field value.

#define ALT_RSTMGR_CTL_ETRSTALLACK_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_ETRSTALLACK register field.

#define ALT_RSTMGR_CTL_ETRSTALLACK_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_RSTMGR_CTL_ETRSTALLACK field value from a register.

#define ALT_RSTMGR_CTL_ETRSTALLACK_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_RSTMGR_CTL_ETRSTALLACK register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_LSB   23

The Least Significant Bit (LSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_MSB   23

The Most Significant Bit (MSB) position of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET_MSK   0x00800000

The mask used to set the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_CLR_MSK   0xff7fffff

The mask used to clear the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_CTL_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_RSTMGR_CTL_ETRSTALLWARMRST field value from a register.

#define ALT_RSTMGR_CTL_ETRSTALLWARMRST_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_RSTMGR_CTL_ETRSTALLWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_CTL_OFST   0x4

The byte offset of the ALT_RSTMGR_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_CTL.