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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Registers used by the DMA Controller. All fields are reset by a cold or warm reset.
These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Channel Select |
[1] | RW | 0x0 | Channel Select |
[2] | RW | 0x0 | Channel Select |
[3] | RW | 0x0 | Channel Select |
[4] | RW | 0x0 | Manager Thread Security |
[12:5] | RW | 0x0 | IRQ Security |
[31:13] | ??? | 0x0 | UNDEFINED |
Field : Channel Select - chansel_0 | ||||||||||
Controls mux that selects whether FPGA or CAN connects to one of the DMA peripheral request interfaces.The peripheral request interface index equals the array index + 4. For example, array index 0 is for peripheral request index 4. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : Channel Select - chansel_1 | ||||||||||
Controls mux that selects whether FPGA or CAN connects to one of the DMA peripheral request interfaces.The peripheral request interface index equals the array index + 4. For example, array index 0 is for peripheral request index 4. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Channel Select - chansel_2 | ||||||||||
Controls mux that selects whether FPGA or CAN connects to one of the DMA peripheral request interfaces.The peripheral request interface index equals the array index + 4. For example, array index 0 is for peripheral request index 4. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : Channel Select - chansel_3 | ||||||||||
Controls mux that selects whether FPGA or CAN connects to one of the DMA peripheral request interfaces.The peripheral request interface index equals the array index + 4. For example, array index 0 is for peripheral request index 4. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Manager Thread Security - mgrnonsecure | |
Specifies the security state of the DMA manager thread. 0 = assigns DMA manager to the Secure state. 1 = assigns DMA manager to the Non-secure state. Sampled by the DMA controller when it exits from reset. Field Access Macros: | |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET(value) (((value) << 4) & 0x00000010) |
Field : IRQ Security - irqnonsecure | |
Specifies the security state of an event-interrupt resource. If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state. If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure state. Field Access Macros: | |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET(value) (((value) & 0x00001fe0) >> 5) |
#define | ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET(value) (((value) << 5) & 0x00001fe0) |
Data Structures | |
struct | ALT_SYSMGR_DMA_CTL_s |
Macros | |
#define | ALT_SYSMGR_DMA_CTL_OFST 0x0 |
Typedefs | |
typedef struct ALT_SYSMGR_DMA_CTL_s | ALT_SYSMGR_DMA_CTL_t |
struct ALT_SYSMGR_DMA_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_DMA_CTL.
Data Fields | ||
---|---|---|
uint32_t | chansel_0: 1 | Channel Select |
uint32_t | chansel_1: 1 | Channel Select |
uint32_t | chansel_2: 1 | Channel Select |
uint32_t | chansel_3: 1 | Channel Select |
uint32_t | mgrnonsecure: 1 | Manager Thread Security |
uint32_t | irqnonsecure: 8 | IRQ Security |
uint32_t | __pad0__: 19 | UNDEFINED |
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
FPGA drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_E_CAN 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_0
CAN drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_0 field value from a register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_0 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
FPGA drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_E_CAN 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_1
CAN drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_1 field value from a register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_1_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_1 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
FPGA drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_E_CAN 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_2
CAN drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET_MSK 0x00000004 |
The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_2 field value from a register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_2_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_2 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
FPGA drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_E_CAN 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CTL_CHANSEL_3
CAN drives peripheral request interface
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET_MSK 0x00000008 |
The mask used to set the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SYSMGR_DMA_CTL_CHANSEL_3 field value from a register.
#define ALT_SYSMGR_DMA_CTL_CHANSEL_3_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SYSMGR_DMA_CTL_CHANSEL_3 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_DMA_CTL_MGRNONSECURE field value from a register.
#define ALT_SYSMGR_DMA_CTL_MGRNONSECURE_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_DMA_CTL_MGRNONSECURE register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_WIDTH 8 |
The width in bits of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET_MSK 0x00001fe0 |
The mask used to set the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_CLR_MSK 0xffffe01f |
The mask used to clear the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_GET | ( | value | ) | (((value) & 0x00001fe0) >> 5) |
Extracts the ALT_SYSMGR_DMA_CTL_IRQNONSECURE field value from a register.
#define ALT_SYSMGR_DMA_CTL_IRQNONSECURE_SET | ( | value | ) | (((value) << 5) & 0x00001fe0) |
Produces a ALT_SYSMGR_DMA_CTL_IRQNONSECURE register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CTL_OFST 0x0 |
The byte offset of the ALT_SYSMGR_DMA_CTL register from the beginning of the component.
typedef struct ALT_SYSMGR_DMA_CTL_s ALT_SYSMGR_DMA_CTL_t |
The typedef declaration for register ALT_SYSMGR_DMA_CTL.