Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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MMU Management Macros - Second Level Translation Table

Description

The macro definitions in this section support access to the short-descriptor second-level table entries and their constituent fields.

These macros may be used to create descriptor entry values that are passed to a second level translation table contruction function such as alt_mmu_ttb2_desc_set().

Each short-descriptor has a set of macro definitions of the following form:

Second Level Translation Table Large Page Table Entry [B]

The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute.

#define ALT_MMU_TTB2_LARGE_PAGE_B_MASK   0x00000004
 
#define ALT_MMU_TTB2_LARGE_PAGE_B_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) >> 2)
 
#define ALT_MMU_TTB2_LARGE_PAGE_B_SET(val)   (((val) << 2) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK)
 

Second Level Translation Table Large Page Table Entry [C]

The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute.

#define ALT_MMU_TTB2_LARGE_PAGE_C_MASK   0x00000008
 
#define ALT_MMU_TTB2_LARGE_PAGE_C_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) >> 3)
 
#define ALT_MMU_TTB2_LARGE_PAGE_C_SET(val)   (((val) << 3) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK)
 

Second Level Translation Table Large Page Table Entry [AP]

Access Permissions bits.

#define ALT_MMU_TTB2_LARGE_PAGE_AP_MASK   0x00000230
 
#define ALT_MMU_TTB2_LARGE_PAGE_AP_GET(desc)   ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
 
#define ALT_MMU_TTB2_LARGE_PAGE_AP_SET(val)   ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
 

Second Level Translation Table Large Page Table Entry [S]

The Shareable bit. Determines whether the addressed region is shareable memory.

#define ALT_MMU_TTB2_LARGE_PAGE_S_MASK   0x00000400
 
#define ALT_MMU_TTB2_LARGE_PAGE_S_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) >> 10)
 
#define ALT_MMU_TTB2_LARGE_PAGE_S_SET(val)   (((val) << 10) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK)
 

Second Level Translation Table Large Page Table Entry [nG]

The not global bit. Determines how the translation is marked in the TLB.

#define ALT_MMU_TTB2_LARGE_PAGE_NG_MASK   0x00000800
 
#define ALT_MMU_TTB2_LARGE_PAGE_NG_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) >> 11)
 
#define ALT_MMU_TTB2_LARGE_PAGE_NG_SET(val)   (((val) << 11) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK)
 

Second Level Translation Table Large Page Table Entry [TEX]

The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute.

#define ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK   0x00007000
 
#define ALT_MMU_TTB2_LARGE_PAGE_TEX_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) >> 12)
 
#define ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(val)   (((val) << 12) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK)
 

Second Level Translation Table Large Page Table Entry [XN]

The Execute-Never bit. Determines whether the processor can execute software from the addressed region.

#define ALT_MMU_TTB2_LARGE_PAGE_XN_MASK   0x00008000
 
#define ALT_MMU_TTB2_LARGE_PAGE_XN_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) >> 15)
 
#define ALT_MMU_TTB2_LARGE_PAGE_XN_SET(val)   (((val) << 15) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK)
 

Second Level Translation Table Large Page Table Entry Large Page Base Address

#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK   0xffff0000
 
#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_GET(desc)   (((desc) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) >> 16)
 
#define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(val)   (((val) << 16) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK)
 

Second Level Translation Table Small Page Table Entry [XN]

The Execute-Never bit. Determines whether the processor can execute software from the addressed region.

#define ALT_MMU_TTB2_SMALL_PAGE_XN_MASK   0x00000001
 
#define ALT_MMU_TTB2_SMALL_PAGE_XN_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) >> 0)
 
#define ALT_MMU_TTB2_SMALL_PAGE_XN_SET(val)   (((val) << 0) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK)
 

Second Level Translation Table Small Page Table Entry [B]

The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute.

#define ALT_MMU_TTB2_SMALL_PAGE_B_MASK   0x00000004
 
#define ALT_MMU_TTB2_SMALL_PAGE_B_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) >> 2)
 
#define ALT_MMU_TTB2_SMALL_PAGE_B_SET(val)   (((val) << 2) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK)
 

Second Level Translation Table Small Page Table Entry [C]

The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute.

#define ALT_MMU_TTB2_SMALL_PAGE_C_MASK   0x00000008
 
#define ALT_MMU_TTB2_SMALL_PAGE_C_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) >> 3)
 
#define ALT_MMU_TTB2_SMALL_PAGE_C_SET(val)   (((val) << 3) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK)
 

Second Level Translation Table Small Page Table Entry [AP]

Access Permissions bits.

#define ALT_MMU_TTB2_SMALL_PAGE_AP_MASK   0x00000230
 
#define ALT_MMU_TTB2_SMALL_PAGE_AP_GET(desc)   ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
 
#define ALT_MMU_TTB2_SMALL_PAGE_AP_SET(val)   ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
 

Second Level Translation Table Small Page Table Entry [TEX]

The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute.

#define ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK   0x000001c0
 
#define ALT_MMU_TTB2_SMALL_PAGE_TEX_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) >> 6)
 
#define ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(val)   (((val) << 6) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK)
 

Second Level Translation Table Small Page Table Entry [S]

The Shareable bit. Determines whether the addressed region is shareable memory.

#define ALT_MMU_TTB2_SMALL_PAGE_S_MASK   0x00000400
 
#define ALT_MMU_TTB2_SMALL_PAGE_S_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) >> 10)
 
#define ALT_MMU_TTB2_SMALL_PAGE_S_SET(val)   (((val) << 10) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK)
 

Second Level Translation Table Small Page Table Entry [nG]

The not global bit. Determines how the translation is marked in the TLB.

#define ALT_MMU_TTB2_SMALL_PAGE_NG_MASK   0x00000800
 
#define ALT_MMU_TTB2_SMALL_PAGE_NG_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) >> 11)
 
#define ALT_MMU_TTB2_SMALL_PAGE_NG_SET(val)   (((val) << 11) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK)
 

Second Level Translation Table Small Page Table Entry Large Page Base Address

#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK   0xfffff000
 
#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_GET(desc)   (((desc) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) >> 12)
 
#define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(val)   (((val) << 12) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK)