Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : fifoth

Description

FIFO Threshold Watermark Register

Register Layout

Bits Access Reset Description
[11:0] RW 0x0 ALT_SDMMC_FIFOTH_TX_WMARK
[15:12] ??? 0x0 UNDEFINED
[27:16] RW 0x3ff ALT_SDMMC_FIFOTH_RX_WMARK
[30:28] RW 0x0 ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
[31] ??? 0x0 UNDEFINED

Field : tx_wmark

FIFO threshold watermark level when transmitting data to card.

When FIFO data count is less than or equal to this number,DMA/FIFO request is raised. If Interrupt is enabled, then interrupt occurs. During end of packet, request or interrupt is generated,regardless of threshold programming.

In non-DMA mode, when transmit FIFO threshold (TXDR) interrupt is enabled, then interrupt is generated instead of DMA request. During end of packet, on last interrupt, host is responsible for filling FIFO with only required remaining bytes (not before FIFO is full or after CIU completes data transfers, because FIFO may not be empty).

In DMA mode, at end of packet, if last transfer is less than burst size, DMA controller does single cycles until required bytes are transferred.

12 bits-1 bit less than FIFO-count of status register, which is 13 bits.

Limitation: TX_WMark >= 1;

Recommended: FIFO_DEPTH/2; (means less than or equal to FIFO_DEPTH/2)

Field Access Macros:

#define ALT_SDMMC_FIFOTH_TX_WMARK_LSB   0
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_MSB   11
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH   12
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK   0x00000fff
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK   0xfffff000
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_RESET   0x0
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value)   (((value) & 0x00000fff) >> 0)
 
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value)   (((value) << 0) & 0x00000fff)
 

Field : rx_wmark

FIFO threshold watermark level when receiving data to card.

When FIFO data count reaches greater than this number,DMA/FIFO request is raised. During end of packet, request is

generated regardless of threshold programming in order to complete any remaining data.

In non-DMA mode, when receiver FIFO threshold (RXDR) interrupt is enabled, then interrupt is generated instead of DMA request.

During end of packet, interrupt is not generated if threshold programming is larger than any remaining data. It is responsibility of host to read remaining bytes on seeing Data Transfer Done interrupt.

In DMA mode, at end of packet, even if remaining bytes are less than threshold, DMA request does single transfers to flush out any remaining bytes before Data Transfer Done interrupt is set.

12 bits-1 bit less than FIFO-count of status register, which is 13 bits.

Limitation: RX_WMark <= FIFO_DEPTH-2

Recommended: (FIFO_DEPTH/2) - 1; (means greater than (FIFO_DEPTH/2) - 1)

NOTE: In DMA mode during CCS time-out, the DMA does not generate the request at the end of packet, even if remaining bytes are less than threshold. In this case, there will be some data left in the FIFO. It is the responsibility of the application to reset the FIFO after the CCS timeout.

Field Access Macros:

#define ALT_SDMMC_FIFOTH_RX_WMARK_LSB   16
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_MSB   27
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH   12
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK   0x0fff0000
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK   0xf000ffff
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_RESET   0x3ff
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value)   (((value) & 0x0fff0000) >> 16)
 
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value)   (((value) << 16) & 0x0fff0000)
 

Field : dw_dma_multiple_transaction_size

Burst size of multiple transaction; should be programmed same as

DW-DMA controller multiple-transaction-size SRC/DEST_MSIZE.

000 1 transfers

001 4

010 8

011 16

100 32

101 64

110 128

111 256

The units for transfers is the H_DATA_WIDTH parameter. A single transfer (dw_dma_single assertion in case of Non DW DMA interface) would be signalled based on this value.

Value should be sub-multiple of (RX_WMark + 1)* (F_DATA_WIDTH/H_DATA_WIDTH) and

(FIFO_DEPTH - TX_WMark)* (F_DATA_WIDTH/H_DATA_WIDTH)

For example, if FIFO_DEPTH = 16,

FDATA_WIDTH == H_DATA_WIDTH

Allowed combinations for MSize and TX_WMark are:

MSize = 1, TX_WMARK = 1-15

MSize = 4, TX_WMark = 8

MSize = 4, TX_WMark = 4

MSize = 4, TX_WMark = 12

MSize = 8, TX_WMark = 8

MSize = 8, TX_WMark = 4

Allowed combinations for MSize and RX_WMark are:

MSize = 1, RX_WMARK = 0-14

MSize = 4, RX_WMark = 3

MSize = 4, RX_WMark = 7

MSize = 4, RX_WMark = 11

MSize = 8, RX_WMark = 7

Recommended:

MSize = 8, TX_WMark = 8, RX_WMark = 7

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0 Msize 1 and TX_WMARK 1-1023
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1 Msize 4 and TX_WMARK 256
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2 Msize 8 and TX_WMARK 128
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3 Msize 16 and TX_WMARK 64
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5 Msize 1 and RX_WMARK 512
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6 Msize 4 and RX_WMARK 128
ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7 Msize 8 and RX_WMARK 64

Field Access Macros:

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1   0x0
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4   0x1
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8   0x2
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16   0x3
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1   0x5
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4   0x6
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8   0x7
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB   28
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB   30
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH   3
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK   0x70000000
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK   0x8fffffff
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET   0x0
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value)   (((value) & 0x70000000) >> 28)
 
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value)   (((value) << 28) & 0x70000000)
 

Data Structures

struct  ALT_SDMMC_FIFOTH_s
 

Macros

#define ALT_SDMMC_FIFOTH_RESET   0x03ff0000
 
#define ALT_SDMMC_FIFOTH_OFST   0x4c
 

Typedefs

typedef struct ALT_SDMMC_FIFOTH_s ALT_SDMMC_FIFOTH_t
 

Data Structure Documentation

struct ALT_SDMMC_FIFOTH_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_FIFOTH.

Data Fields
uint32_t tx_wmark: 12 ALT_SDMMC_FIFOTH_TX_WMARK
uint32_t __pad0__: 4 UNDEFINED
uint32_t rx_wmark: 12 ALT_SDMMC_FIFOTH_RX_WMARK
uint32_t dw_dma_multiple_transaction_size: 3 ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE
uint32_t __pad1__: 1 UNDEFINED

Macro Definitions

#define ALT_SDMMC_FIFOTH_TX_WMARK_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field.

#define ALT_SDMMC_FIFOTH_TX_WMARK_MSB   11

The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_TX_WMARK register field.

#define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH   12

The width in bits of the ALT_SDMMC_FIFOTH_TX_WMARK register field.

#define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK   0x00000fff

The mask used to set the ALT_SDMMC_FIFOTH_TX_WMARK register field value.

#define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK   0xfffff000

The mask used to clear the ALT_SDMMC_FIFOTH_TX_WMARK register field value.

#define ALT_SDMMC_FIFOTH_TX_WMARK_RESET   0x0

The reset value of the ALT_SDMMC_FIFOTH_TX_WMARK register field.

#define ALT_SDMMC_FIFOTH_TX_WMARK_GET (   value)    (((value) & 0x00000fff) >> 0)

Extracts the ALT_SDMMC_FIFOTH_TX_WMARK field value from a register.

#define ALT_SDMMC_FIFOTH_TX_WMARK_SET (   value)    (((value) << 0) & 0x00000fff)

Produces a ALT_SDMMC_FIFOTH_TX_WMARK register field value suitable for setting the register.

#define ALT_SDMMC_FIFOTH_RX_WMARK_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field.

#define ALT_SDMMC_FIFOTH_RX_WMARK_MSB   27

The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_RX_WMARK register field.

#define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH   12

The width in bits of the ALT_SDMMC_FIFOTH_RX_WMARK register field.

#define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK   0x0fff0000

The mask used to set the ALT_SDMMC_FIFOTH_RX_WMARK register field value.

#define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK   0xf000ffff

The mask used to clear the ALT_SDMMC_FIFOTH_RX_WMARK register field value.

#define ALT_SDMMC_FIFOTH_RX_WMARK_RESET   0x3ff

The reset value of the ALT_SDMMC_FIFOTH_RX_WMARK register field.

#define ALT_SDMMC_FIFOTH_RX_WMARK_GET (   value)    (((value) & 0x0fff0000) >> 16)

Extracts the ALT_SDMMC_FIFOTH_RX_WMARK field value from a register.

#define ALT_SDMMC_FIFOTH_RX_WMARK_SET (   value)    (((value) << 16) & 0x0fff0000)

Produces a ALT_SDMMC_FIFOTH_RX_WMARK register field value suitable for setting the register.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1   0x0

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 1 and TX_WMARK 1-1023

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4   0x1

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 4 and TX_WMARK 256

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8   0x2

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 8 and TX_WMARK 128

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16   0x3

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 16 and TX_WMARK 64

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1   0x5

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 1 and RX_WMARK 512

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4   0x6

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 4 and RX_WMARK 128

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8   0x7

Enumerated value for register field ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE

Msize 8 and RX_WMARK 64

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB   28

The Least Significant Bit (LSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB   30

The Most Significant Bit (MSB) position of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH   3

The width in bits of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK   0x70000000

The mask used to set the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK   0x8fffffff

The mask used to clear the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET   0x0

The reset value of the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET (   value)    (((value) & 0x70000000) >> 28)

Extracts the ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE field value from a register.

#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET (   value)    (((value) << 28) & 0x70000000)

Produces a ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE register field value suitable for setting the register.

#define ALT_SDMMC_FIFOTH_RESET   0x03ff0000

The reset value of the ALT_SDMMC_FIFOTH register.

#define ALT_SDMMC_FIFOTH_OFST   0x4c

The byte offset of the ALT_SDMMC_FIFOTH register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_FIFOTH.