Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : idsts

Description

Internal DMAC Status Register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_SDMMC_IDSTS_TI
[1] RW 0x0 ALT_SDMMC_IDSTS_RI
[2] RW 0x0 ALT_SDMMC_IDSTS_FBE
[3] ??? 0x0 UNDEFINED
[4] RW 0x0 ALT_SDMMC_IDSTS_DU
[5] RW 0x0 ALT_SDMMC_IDSTS_CES
[7:6] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_SDMMC_IDSTS_NIS
[9] RW 0x0 ALT_SDMMC_IDSTS_AIS
[12:10] R 0x0 ALT_SDMMC_IDSTS_EB
[16:13] R 0x0 ALT_SDMMC_IDSTS_FSM
[31:17] ??? 0x0 UNDEFINED

Field : ti

Transmit Interrupt. Indicates that data transmission is finished for a descriptor. Writing a ‘1’ clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0 No Clear of Transmit Interrupt Status Bit
ALT_SDMMC_IDSTS_TI_E_CLR 0x1 Clears Transmit Interrupt Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_TI_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_TI_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_TI_LSB   0
 
#define ALT_SDMMC_IDSTS_TI_MSB   0
 
#define ALT_SDMMC_IDSTS_TI_WIDTH   1
 
#define ALT_SDMMC_IDSTS_TI_SET_MSK   0x00000001
 
#define ALT_SDMMC_IDSTS_TI_CLR_MSK   0xfffffffe
 
#define ALT_SDMMC_IDSTS_TI_RESET   0x0
 
#define ALT_SDMMC_IDSTS_TI_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SDMMC_IDSTS_TI_SET(value)   (((value) << 0) & 0x00000001)
 

Field : ri

Receive Interrupt. Indicates the completion of data reception for a descriptor. Writing a 1 clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0 No Clear of Receive Interrupt Status Bit
ALT_SDMMC_IDSTS_RI_E_CLR 0x1 Clears Receive Interrupt Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_RI_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_RI_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_RI_LSB   1
 
#define ALT_SDMMC_IDSTS_RI_MSB   1
 
#define ALT_SDMMC_IDSTS_RI_WIDTH   1
 
#define ALT_SDMMC_IDSTS_RI_SET_MSK   0x00000002
 
#define ALT_SDMMC_IDSTS_RI_CLR_MSK   0xfffffffd
 
#define ALT_SDMMC_IDSTS_RI_RESET   0x0
 
#define ALT_SDMMC_IDSTS_RI_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SDMMC_IDSTS_RI_SET(value)   (((value) << 1) & 0x00000002)
 

Field : fbe

Fatal Bus Error Interrupt. Indicates that a Bus Error occurred (IDSTS[12:10]). When this bit is set, the DMA disables all its bus accesses. Writing a 1 clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0 No Clear of Fatal Bus Error Interrupt Status Bit
ALT_SDMMC_IDSTS_FBE_E_CLR 0x1 Clears Fatal Bus Error Interrupt Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_FBE_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_FBE_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_FBE_LSB   2
 
#define ALT_SDMMC_IDSTS_FBE_MSB   2
 
#define ALT_SDMMC_IDSTS_FBE_WIDTH   1
 
#define ALT_SDMMC_IDSTS_FBE_SET_MSK   0x00000004
 
#define ALT_SDMMC_IDSTS_FBE_CLR_MSK   0xfffffffb
 
#define ALT_SDMMC_IDSTS_FBE_RESET   0x0
 
#define ALT_SDMMC_IDSTS_FBE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SDMMC_IDSTS_FBE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : du

Descriptor Unavailable Interrupt. This bit is set when the descriptor is unavailable due to OWN bit = 0 (DES0[31] =0). Writing a 1 clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0 No Clear of Descriptor Unavailable Interrupt
: Status Bit
ALT_SDMMC_IDSTS_DU_E_CLR 0x1 Clears Descriptor Unavailable Interrupt Status
: Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_DU_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_DU_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_DU_LSB   4
 
#define ALT_SDMMC_IDSTS_DU_MSB   4
 
#define ALT_SDMMC_IDSTS_DU_WIDTH   1
 
#define ALT_SDMMC_IDSTS_DU_SET_MSK   0x00000010
 
#define ALT_SDMMC_IDSTS_DU_CLR_MSK   0xffffffef
 
#define ALT_SDMMC_IDSTS_DU_RESET   0x0
 
#define ALT_SDMMC_IDSTS_DU_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SDMMC_IDSTS_DU_SET(value)   (((value) << 4) & 0x00000010)
 

Field : ces

Card Error Summary. Indicates the status of the transaction to/from the card; also present in RINTSTS. Indicates the logical OR of the following bits:

■ EBE End Bit Error

■ RTO Response Timeout/Boot Ack Timeout

■ RCRC Response CRC

■ SBE Start Bit Error

■ DRTO Data Read Timeout/BDS timeout

■ DCRC Data CRC for Receive

■ RE Response Error

Writing a 1 clears this bit.

The abort condition of the IDMAC depends on the setting of this CES bit. If the CES bit

is enabled, then the IDMAC aborts on a “response error”; however, it will not abort if the

CES bit is cleared.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0 No Clear Card Error Summary Interrupt Status Bit
ALT_SDMMC_IDSTS_CES_E_CLR 0x1 Clears Card Error Summary Interrupt Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_CES_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_CES_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_CES_LSB   5
 
#define ALT_SDMMC_IDSTS_CES_MSB   5
 
#define ALT_SDMMC_IDSTS_CES_WIDTH   1
 
#define ALT_SDMMC_IDSTS_CES_SET_MSK   0x00000020
 
#define ALT_SDMMC_IDSTS_CES_CLR_MSK   0xffffffdf
 
#define ALT_SDMMC_IDSTS_CES_RESET   0x0
 
#define ALT_SDMMC_IDSTS_CES_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SDMMC_IDSTS_CES_SET(value)   (((value) << 5) & 0x00000020)
 

Field : nis

Normal Interrupt Summary. Logical OR of the following:

■ IDSTS[0]-Transmit Interrupt

■ IDSTS[1]-Receive Interrupt

Only unmasked bits affect this bit.

This is a sticky bit and must be cleared each time a corresponding bit that causes NIS

to be set is cleared. Writing a 1 clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0 No Clear Normal Interrupt Summary Status Bit
ALT_SDMMC_IDSTS_NIS_E_CLR 0x1 Clears Normal Interrupt Summary Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_NIS_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_NIS_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_NIS_LSB   8
 
#define ALT_SDMMC_IDSTS_NIS_MSB   8
 
#define ALT_SDMMC_IDSTS_NIS_WIDTH   1
 
#define ALT_SDMMC_IDSTS_NIS_SET_MSK   0x00000100
 
#define ALT_SDMMC_IDSTS_NIS_CLR_MSK   0xfffffeff
 
#define ALT_SDMMC_IDSTS_NIS_RESET   0x0
 
#define ALT_SDMMC_IDSTS_NIS_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SDMMC_IDSTS_NIS_SET(value)   (((value) << 8) & 0x00000100)
 

Field : ais

Abnormal Interrupt Summary. Logical OR of the following:

■ IDSTS[2]-Fatal Bus Interrupt

■ IDSTS[4]-DU bit Interrupt

Only unmasked bits affect this bit.

This is a sticky bit and must be cleared each time a corresponding bit that causes AIS

to be set is cleared. Writing a 1 clears this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0 No Clear Abnormal Summary Interrupt Status Bit
ALT_SDMMC_IDSTS_AIS_E_CLR 0x1 Clears Abnormal Summary Interrupt Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_AIS_E_NOCLR   0x0
 
#define ALT_SDMMC_IDSTS_AIS_E_CLR   0x1
 
#define ALT_SDMMC_IDSTS_AIS_LSB   9
 
#define ALT_SDMMC_IDSTS_AIS_MSB   9
 
#define ALT_SDMMC_IDSTS_AIS_WIDTH   1
 
#define ALT_SDMMC_IDSTS_AIS_SET_MSK   0x00000200
 
#define ALT_SDMMC_IDSTS_AIS_CLR_MSK   0xfffffdff
 
#define ALT_SDMMC_IDSTS_AIS_RESET   0x0
 
#define ALT_SDMMC_IDSTS_AIS_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SDMMC_IDSTS_AIS_SET(value)   (((value) << 9) & 0x00000200)
 

Field : eb

Error Bits. Indicates the type of error that caused a Bus Error.

Valid only with Fatal Bus

Error bitIDSTS[2] set. This field does not generate an interrupt.

3’b001 Host Abort received during transmission

3’b010 Host Abort received during reception

Others: Reserved

EB is read-only.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1 Host Abort during transmission Status Bit
ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2 Host Abort received during reception Status Bit

Field Access Macros:

#define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX   0x1
 
#define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX   0x2
 
#define ALT_SDMMC_IDSTS_EB_LSB   10
 
#define ALT_SDMMC_IDSTS_EB_MSB   12
 
#define ALT_SDMMC_IDSTS_EB_WIDTH   3
 
#define ALT_SDMMC_IDSTS_EB_SET_MSK   0x00001c00
 
#define ALT_SDMMC_IDSTS_EB_CLR_MSK   0xffffe3ff
 
#define ALT_SDMMC_IDSTS_EB_RESET   0x0
 
#define ALT_SDMMC_IDSTS_EB_GET(value)   (((value) & 0x00001c00) >> 10)
 
#define ALT_SDMMC_IDSTS_EB_SET(value)   (((value) << 10) & 0x00001c00)
 

Field : fsm

DMAC FSM present state.

0 DMA_IDLE

1 DMA_SUSPEND

2 DESC_RD

3 DESC_CHK

4 DMA_RD_REQ_WAIT

5 DMA_WR_REQ_WAIT

6 DMA_RD

7 DMA_WR

8 DESC_CLOSE

This bit is read-only.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0 DMA IDLE
ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1 DMA SUSPEND
ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2 DESC_RD
ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3 DESC_CHK
ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4 DMA RD REQ WAIT
ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5 DMA WR REQ WAIT
ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6 DMA RD
ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7 DMA WR
ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8 DESC CLOSE

Field Access Macros:

#define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE   0x0
 
#define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND   0x1
 
#define ALT_SDMMC_IDSTS_FSM_E_DESCRD   0x2
 
#define ALT_SDMMC_IDSTS_FSM_E_DESCCHK   0x3
 
#define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT   0x4
 
#define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT   0x5
 
#define ALT_SDMMC_IDSTS_FSM_E_DMARD   0x6
 
#define ALT_SDMMC_IDSTS_FSM_E_DMAWR   0x7
 
#define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE   0x8
 
#define ALT_SDMMC_IDSTS_FSM_LSB   13
 
#define ALT_SDMMC_IDSTS_FSM_MSB   16
 
#define ALT_SDMMC_IDSTS_FSM_WIDTH   4
 
#define ALT_SDMMC_IDSTS_FSM_SET_MSK   0x0001e000
 
#define ALT_SDMMC_IDSTS_FSM_CLR_MSK   0xfffe1fff
 
#define ALT_SDMMC_IDSTS_FSM_RESET   0x0
 
#define ALT_SDMMC_IDSTS_FSM_GET(value)   (((value) & 0x0001e000) >> 13)
 
#define ALT_SDMMC_IDSTS_FSM_SET(value)   (((value) << 13) & 0x0001e000)
 

Data Structures

struct  ALT_SDMMC_IDSTS_s
 

Macros

#define ALT_SDMMC_IDSTS_RESET   0x00000000
 
#define ALT_SDMMC_IDSTS_OFST   0x8c
 

Typedefs

typedef struct ALT_SDMMC_IDSTS_s ALT_SDMMC_IDSTS_t
 

Data Structure Documentation

struct ALT_SDMMC_IDSTS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_IDSTS.

Data Fields
uint32_t ti: 1 ALT_SDMMC_IDSTS_TI
uint32_t ri: 1 ALT_SDMMC_IDSTS_RI
uint32_t fbe: 1 ALT_SDMMC_IDSTS_FBE
uint32_t __pad0__: 1 UNDEFINED
uint32_t du: 1 ALT_SDMMC_IDSTS_DU
uint32_t ces: 1 ALT_SDMMC_IDSTS_CES
uint32_t __pad1__: 2 UNDEFINED
uint32_t nis: 1 ALT_SDMMC_IDSTS_NIS
uint32_t ais: 1 ALT_SDMMC_IDSTS_AIS
const uint32_t eb: 3 ALT_SDMMC_IDSTS_EB
const uint32_t fsm: 4 ALT_SDMMC_IDSTS_FSM
uint32_t __pad2__: 15 UNDEFINED

Macro Definitions

#define ALT_SDMMC_IDSTS_TI_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_TI

No Clear of Transmit Interrupt Status Bit

#define ALT_SDMMC_IDSTS_TI_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_TI

Clears Transmit Interrupt Status Bit

#define ALT_SDMMC_IDSTS_TI_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_TI register field.

#define ALT_SDMMC_IDSTS_TI_MSB   0

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_TI register field.

#define ALT_SDMMC_IDSTS_TI_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_TI register field.

#define ALT_SDMMC_IDSTS_TI_SET_MSK   0x00000001

The mask used to set the ALT_SDMMC_IDSTS_TI register field value.

#define ALT_SDMMC_IDSTS_TI_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SDMMC_IDSTS_TI register field value.

#define ALT_SDMMC_IDSTS_TI_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_TI register field.

#define ALT_SDMMC_IDSTS_TI_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SDMMC_IDSTS_TI field value from a register.

#define ALT_SDMMC_IDSTS_TI_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SDMMC_IDSTS_TI register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_RI_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_RI

No Clear of Receive Interrupt Status Bit

#define ALT_SDMMC_IDSTS_RI_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_RI

Clears Receive Interrupt Status Bit

#define ALT_SDMMC_IDSTS_RI_LSB   1

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_RI register field.

#define ALT_SDMMC_IDSTS_RI_MSB   1

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_RI register field.

#define ALT_SDMMC_IDSTS_RI_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_RI register field.

#define ALT_SDMMC_IDSTS_RI_SET_MSK   0x00000002

The mask used to set the ALT_SDMMC_IDSTS_RI register field value.

#define ALT_SDMMC_IDSTS_RI_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SDMMC_IDSTS_RI register field value.

#define ALT_SDMMC_IDSTS_RI_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_RI register field.

#define ALT_SDMMC_IDSTS_RI_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SDMMC_IDSTS_RI field value from a register.

#define ALT_SDMMC_IDSTS_RI_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SDMMC_IDSTS_RI register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_FBE_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_FBE

No Clear of Fatal Bus Error Interrupt Status Bit

#define ALT_SDMMC_IDSTS_FBE_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_FBE

Clears Fatal Bus Error Interrupt Status Bit

#define ALT_SDMMC_IDSTS_FBE_LSB   2

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FBE register field.

#define ALT_SDMMC_IDSTS_FBE_MSB   2

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FBE register field.

#define ALT_SDMMC_IDSTS_FBE_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_FBE register field.

#define ALT_SDMMC_IDSTS_FBE_SET_MSK   0x00000004

The mask used to set the ALT_SDMMC_IDSTS_FBE register field value.

#define ALT_SDMMC_IDSTS_FBE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SDMMC_IDSTS_FBE register field value.

#define ALT_SDMMC_IDSTS_FBE_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_FBE register field.

#define ALT_SDMMC_IDSTS_FBE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SDMMC_IDSTS_FBE field value from a register.

#define ALT_SDMMC_IDSTS_FBE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SDMMC_IDSTS_FBE register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_DU_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_DU

No Clear of Descriptor Unavailable Interrupt Status Bit

#define ALT_SDMMC_IDSTS_DU_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_DU

Clears Descriptor Unavailable Interrupt Status Bit

#define ALT_SDMMC_IDSTS_DU_LSB   4

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_DU register field.

#define ALT_SDMMC_IDSTS_DU_MSB   4

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_DU register field.

#define ALT_SDMMC_IDSTS_DU_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_DU register field.

#define ALT_SDMMC_IDSTS_DU_SET_MSK   0x00000010

The mask used to set the ALT_SDMMC_IDSTS_DU register field value.

#define ALT_SDMMC_IDSTS_DU_CLR_MSK   0xffffffef

The mask used to clear the ALT_SDMMC_IDSTS_DU register field value.

#define ALT_SDMMC_IDSTS_DU_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_DU register field.

#define ALT_SDMMC_IDSTS_DU_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SDMMC_IDSTS_DU field value from a register.

#define ALT_SDMMC_IDSTS_DU_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SDMMC_IDSTS_DU register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_CES_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_CES

No Clear Card Error Summary Interrupt Status Bit

#define ALT_SDMMC_IDSTS_CES_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_CES

Clears Card Error Summary Interrupt Status Bit

#define ALT_SDMMC_IDSTS_CES_LSB   5

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_CES register field.

#define ALT_SDMMC_IDSTS_CES_MSB   5

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_CES register field.

#define ALT_SDMMC_IDSTS_CES_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_CES register field.

#define ALT_SDMMC_IDSTS_CES_SET_MSK   0x00000020

The mask used to set the ALT_SDMMC_IDSTS_CES register field value.

#define ALT_SDMMC_IDSTS_CES_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SDMMC_IDSTS_CES register field value.

#define ALT_SDMMC_IDSTS_CES_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_CES register field.

#define ALT_SDMMC_IDSTS_CES_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SDMMC_IDSTS_CES field value from a register.

#define ALT_SDMMC_IDSTS_CES_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SDMMC_IDSTS_CES register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_NIS_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_NIS

No Clear Normal Interrupt Summary Status Bit

#define ALT_SDMMC_IDSTS_NIS_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_NIS

Clears Normal Interrupt Summary Status Bit

#define ALT_SDMMC_IDSTS_NIS_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_NIS register field.

#define ALT_SDMMC_IDSTS_NIS_MSB   8

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_NIS register field.

#define ALT_SDMMC_IDSTS_NIS_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_NIS register field.

#define ALT_SDMMC_IDSTS_NIS_SET_MSK   0x00000100

The mask used to set the ALT_SDMMC_IDSTS_NIS register field value.

#define ALT_SDMMC_IDSTS_NIS_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SDMMC_IDSTS_NIS register field value.

#define ALT_SDMMC_IDSTS_NIS_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_NIS register field.

#define ALT_SDMMC_IDSTS_NIS_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SDMMC_IDSTS_NIS field value from a register.

#define ALT_SDMMC_IDSTS_NIS_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SDMMC_IDSTS_NIS register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_AIS_E_NOCLR   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_AIS

No Clear Abnormal Summary Interrupt Status Bit

#define ALT_SDMMC_IDSTS_AIS_E_CLR   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_AIS

Clears Abnormal Summary Interrupt Status Bit

#define ALT_SDMMC_IDSTS_AIS_LSB   9

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_AIS register field.

#define ALT_SDMMC_IDSTS_AIS_MSB   9

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_AIS register field.

#define ALT_SDMMC_IDSTS_AIS_WIDTH   1

The width in bits of the ALT_SDMMC_IDSTS_AIS register field.

#define ALT_SDMMC_IDSTS_AIS_SET_MSK   0x00000200

The mask used to set the ALT_SDMMC_IDSTS_AIS register field value.

#define ALT_SDMMC_IDSTS_AIS_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SDMMC_IDSTS_AIS register field value.

#define ALT_SDMMC_IDSTS_AIS_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_AIS register field.

#define ALT_SDMMC_IDSTS_AIS_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SDMMC_IDSTS_AIS field value from a register.

#define ALT_SDMMC_IDSTS_AIS_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SDMMC_IDSTS_AIS register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_EB

Host Abort during transmission Status Bit

#define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX   0x2

Enumerated value for register field ALT_SDMMC_IDSTS_EB

Host Abort received during reception Status Bit

#define ALT_SDMMC_IDSTS_EB_LSB   10

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_EB register field.

#define ALT_SDMMC_IDSTS_EB_MSB   12

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_EB register field.

#define ALT_SDMMC_IDSTS_EB_WIDTH   3

The width in bits of the ALT_SDMMC_IDSTS_EB register field.

#define ALT_SDMMC_IDSTS_EB_SET_MSK   0x00001c00

The mask used to set the ALT_SDMMC_IDSTS_EB register field value.

#define ALT_SDMMC_IDSTS_EB_CLR_MSK   0xffffe3ff

The mask used to clear the ALT_SDMMC_IDSTS_EB register field value.

#define ALT_SDMMC_IDSTS_EB_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_EB register field.

#define ALT_SDMMC_IDSTS_EB_GET (   value)    (((value) & 0x00001c00) >> 10)

Extracts the ALT_SDMMC_IDSTS_EB field value from a register.

#define ALT_SDMMC_IDSTS_EB_SET (   value)    (((value) << 10) & 0x00001c00)

Produces a ALT_SDMMC_IDSTS_EB register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE   0x0

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA IDLE

#define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND   0x1

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA SUSPEND

#define ALT_SDMMC_IDSTS_FSM_E_DESCRD   0x2

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DESC_RD

#define ALT_SDMMC_IDSTS_FSM_E_DESCCHK   0x3

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DESC_CHK

#define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT   0x4

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA RD REQ WAIT

#define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT   0x5

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA WR REQ WAIT

#define ALT_SDMMC_IDSTS_FSM_E_DMARD   0x6

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA RD

#define ALT_SDMMC_IDSTS_FSM_E_DMAWR   0x7

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DMA WR

#define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE   0x8

Enumerated value for register field ALT_SDMMC_IDSTS_FSM

DESC CLOSE

#define ALT_SDMMC_IDSTS_FSM_LSB   13

The Least Significant Bit (LSB) position of the ALT_SDMMC_IDSTS_FSM register field.

#define ALT_SDMMC_IDSTS_FSM_MSB   16

The Most Significant Bit (MSB) position of the ALT_SDMMC_IDSTS_FSM register field.

#define ALT_SDMMC_IDSTS_FSM_WIDTH   4

The width in bits of the ALT_SDMMC_IDSTS_FSM register field.

#define ALT_SDMMC_IDSTS_FSM_SET_MSK   0x0001e000

The mask used to set the ALT_SDMMC_IDSTS_FSM register field value.

#define ALT_SDMMC_IDSTS_FSM_CLR_MSK   0xfffe1fff

The mask used to clear the ALT_SDMMC_IDSTS_FSM register field value.

#define ALT_SDMMC_IDSTS_FSM_RESET   0x0

The reset value of the ALT_SDMMC_IDSTS_FSM register field.

#define ALT_SDMMC_IDSTS_FSM_GET (   value)    (((value) & 0x0001e000) >> 13)

Extracts the ALT_SDMMC_IDSTS_FSM field value from a register.

#define ALT_SDMMC_IDSTS_FSM_SET (   value)    (((value) << 13) & 0x0001e000)

Produces a ALT_SDMMC_IDSTS_FSM register field value suitable for setting the register.

#define ALT_SDMMC_IDSTS_RESET   0x00000000

The reset value of the ALT_SDMMC_IDSTS register.

#define ALT_SDMMC_IDSTS_OFST   0x8c

The byte offset of the ALT_SDMMC_IDSTS register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_IDSTS.