Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ctrlcfg7

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN
[7:1] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY
[14:8] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY
[31:15] ??? 0x0 UNDEFINED

Field : cfg_clkgating_en

Set to 1 to enable the clock gating. The clock is shut off for the whole HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_LSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_MSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET_MSK   0x00000001
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_CLR_MSK   0xfffffffe
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : cfg_rb_reserved_entry

Specify how many enties are reserved in read buffer before almost full is asserted

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_LSB   1
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_MSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_WIDTH   7
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET_MSK   0x000000fe
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_CLR_MSK   0xffffff01
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_GET(value)   (((value) & 0x000000fe) >> 1)
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET(value)   (((value) << 1) & 0x000000fe)
 

Field : cfg_wb_reserved_entry

Specify how many enties are reserved in write buffer before almost full is asserted

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_LSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_MSB   14
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_WIDTH   7
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET_MSK   0x00007f00
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_CLR_MSK   0xffff80ff
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_GET(value)   (((value) & 0x00007f00) >> 8)
 
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET(value)   (((value) << 8) & 0x00007f00)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CTLCFG7_s
 

Macros

#define ALT_IO48_HMC_MMR_CTLCFG7_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CTLCFG7_OFST   0x44
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CTLCFG7_s 
ALT_IO48_HMC_MMR_CTLCFG7_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CTLCFG7_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG7.

Data Fields
uint32_t cfg_clkgating_en: 1 ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN
uint32_t cfg_rb_reserved_entry: 7 ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY
uint32_t cfg_wb_reserved_entry: 7 ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY
uint32_t __pad0__: 17 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET_MSK   0x00000001

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_LSB   1

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_MSB   7

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_WIDTH   7

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET_MSK   0x000000fe

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_CLR_MSK   0xffffff01

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_GET (   value)    (((value) & 0x000000fe) >> 1)

Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET (   value)    (((value) << 1) & 0x000000fe)

Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_LSB   8

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_MSB   14

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_WIDTH   7

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET_MSK   0x00007f00

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_CLR_MSK   0xffff80ff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_GET (   value)    (((value) & 0x00007f00) >> 8)

Extracts the ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET (   value)    (((value) << 8) & 0x00007f00)

Produces a ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG7_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CTLCFG7 register.

#define ALT_IO48_HMC_MMR_CTLCFG7_OFST   0x44

The byte offset of the ALT_IO48_HMC_MMR_CTLCFG7 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG7.