Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 456 (Target Time Nanoseconds Register) - gmacgrp_target_time_nanoseconds

Description

Target time

Register Layout

Bits Access Reset Description
[30:0] RW 0x0 Target Timestamp Low Register
[31] R 0x0 Target Time Register Busy

Field : Target Timestamp Low Register - ttslo

This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the both Target Timestamp registers, then based on the TRGTMODSEL0 field (Bits [6:5]) in Register 459 (PPS Control Register), the MAC starts or stops the PPS signal output and generates an interrupt (if enabled).

This value should not exceed 0x3B9A_C9FF when TSCTRLSSR is set in the Timestamp control register. The actual start or stop time of the PPS signal output may have an error margin up to one unit of sub-second increment value.

Field Access Macros:

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB   0
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB   30
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH   31
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK   0x7fffffff
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK   0x80000000
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET   0x0
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET(value)   (((value) & 0x7fffffff) >> 0)
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET(value)   (((value) << 0) & 0x7fffffff)
 

Field : Target Time Register Busy - trgtbusy

The MAC sets this bit when the PPSCMD field (Bits[3:0]) in Register 459 (PPS Control Register) is programmed to 010 or 011. Programming the PPSCMD field to 010 or 011, instructs the MAC to synchronize the Target Time Registers to the PTP clock domain.

The MAC clears this bit after synchronizing the Target Time Registers to the PTP clock domain The application must not update the Target Time Registers when this bit is read as 1. Otherwise, the synchronization of the previous programmed time gets corrupted. This bit is reserved when the Enable Flexible Pulse-Per-Second Output feature is not selected.

Field Access Macros:

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB   31
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB   31
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH   1
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK   0x80000000
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK   0x7fffffff
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET   0x0
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s
 

Macros

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_RESET   0x00000000
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST   0x720
 
#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s 
ALT_EMAC_GMAC_TGT_TIME_NANOSECS_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_TGT_TIME_NANOSECS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_TGT_TIME_NANOSECS.

Data Fields
uint32_t ttslo: 31 Target Timestamp Low Register
const uint32_t trgtbusy: 1 Target Time Register Busy

Macro Definitions

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_MSB   30

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_WIDTH   31

The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET_MSK   0x7fffffff

The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_CLR_MSK   0x80000000

The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_GET (   value)    (((value) & 0x7fffffff) >> 0)

Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO field value from a register.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO_SET (   value)    (((value) << 0) & 0x7fffffff)

Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TTSLO register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_LSB   31

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET_MSK   0x80000000

The mask used to set the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_CLR_MSK   0x7fffffff

The mask used to clear the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY field value from a register.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_EMAC_GMAC_TGT_TIME_NANOSECS_TRGTBUSY register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST   0x720

The byte offset of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register from the beginning of the component.

#define ALT_EMAC_GMAC_TGT_TIME_NANOSECS_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TGT_TIME_NANOSECS_OFST))

The address of the ALT_EMAC_GMAC_TGT_TIME_NANOSECS register.

Typedef Documentation