Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : gmacgrp_interrupt_mask

Description

Register 15 (Interrupt Mask Register)

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o in the GMAC-AHB, GMAC-AXI, and GMAC-DMA configuration and mci_intr_o in the GMAC-MTL and GMAC-CORE configuration.

Register Layout

Bits Access Reset Description
[0] R 0x0 ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
[1] R 0x0 ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM
[2] R 0x0 ALT_EMAC_GMAC_INT_MSK_PCSANCIM
[3] RW 0x0 ALT_EMAC_GMAC_INT_MSK_PMTIM
[8:4] R 0x0 ALT_EMAC_GMAC_INT_MSK_RSVD_8_4
[9] R 0x0 ALT_EMAC_GMAC_INT_MSK_TSIM
[10] RW 0x0 ALT_EMAC_GMAC_INT_MSK_LPIIM
[31:11] R 0x0 ALT_EMAC_GMAC_INT_MSK_RSVD_31_11

Field : rgsmiiim

RGMII or SMII Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register).

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD | 0x0 | ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB   0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB   0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value)   (((value) << 0) & 0x00000001)
 

Field : pcslchgim

PCS Link Status Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register).

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value)   (((value) << 1) & 0x00000002)
 

Field : pcsancim

PCS AN Completion Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register).

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB   2
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB   2
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value)   (((value) << 2) & 0x00000004)
 

Field : pmtim

PMT Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of PMT Interrupt Status bit in Register 14 (Interrupt Status Register).

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_LSB   3
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_MSB   3
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET(value)   (((value) << 3) & 0x00000008)
 

Field : reserved_8_4

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_LSB   4
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_MSB   8
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_WIDTH   5
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET_MSK   0x000001f0
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_CLR_MSK   0xfffffe0f
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_GET(value)   (((value) & 0x000001f0) >> 4)
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET(value)   (((value) << 4) & 0x000001f0)
 

Field : tsim

Timestamp Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register).

This bit is valid only when IEEE1588 timestamping is enabled. In all other modes, this bit is reserved.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD | 0x0 | ALT_EMAC_GMAC_INT_MSK_TSIM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB   9
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB   9
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value)   (((value) << 9) & 0x00000200)
 

Field : lpiim

LPI Interrupt Mask

When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register).

This bit is valid only when you select the Energy Efficient Ethernet feature during core configuration. In all other modes, this bit is reserved.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD | 0x0 | ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB   10
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB   10
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value)   (((value) << 10) & 0x00000400)
 

Field : reserved_31_11

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_LSB   11
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_MSB   31
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_WIDTH   21
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET_MSK   0xfffff800
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_CLR_MSK   0x000007ff
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_GET(value)   (((value) & 0xfffff800) >> 11)
 
#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET(value)   (((value) << 11) & 0xfffff800)
 

Data Structures

struct  ALT_EMAC_GMAC_INT_MSK_s
 

Macros

#define ALT_EMAC_GMAC_INT_MSK_RESET   0x00000000
 
#define ALT_EMAC_GMAC_INT_MSK_OFST   0x3c
 
#define ALT_EMAC_GMAC_INT_MSK_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_INT_MSK_s 
ALT_EMAC_GMAC_INT_MSK_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_INT_MSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_INT_MSK.

Data Fields
const uint32_t rgsmiiim: 1 ALT_EMAC_GMAC_INT_MSK_RGSMIIIM
const uint32_t pcslchgim: 1 ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM
const uint32_t pcsancim: 1 ALT_EMAC_GMAC_INT_MSK_PCSANCIM
uint32_t pmtim: 1 ALT_EMAC_GMAC_INT_MSK_PMTIM
const uint32_t reserved_8_4: 5 ALT_EMAC_GMAC_INT_MSK_RSVD_8_4
const uint32_t tsim: 1 ALT_EMAC_GMAC_INT_MSK_TSIM
uint32_t lpiim: 1 ALT_EMAC_GMAC_INT_MSK_LPIIM
const uint32_t reserved_31_11: 21 ALT_EMAC_GMAC_INT_MSK_RSVD_31_11

Macro Definitions

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_INT_MSK_PMTIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PMTIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_PMTIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_INT_MSK_PMTIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_PMTIM_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_INT_MSK_PMTIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET_MSK   0x000001f0

The mask used to set the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_CLR_MSK   0xfffffe0f

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_GET (   value)    (((value) & 0x000001f0) >> 4)

Extracts the ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_8_4_SET (   value)    (((value) << 4) & 0x000001f0)

Produces a ALT_EMAC_GMAC_INT_MSK_RSVD_8_4 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM

#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_WIDTH   21

The width in bits of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET_MSK   0xfffff800

The mask used to set the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_CLR_MSK   0x000007ff

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_GET (   value)    (((value) & 0xfffff800) >> 11)

Extracts the ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_RSVD_31_11_SET (   value)    (((value) << 11) & 0xfffff800)

Produces a ALT_EMAC_GMAC_INT_MSK_RSVD_31_11 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_INT_MSK register.

#define ALT_EMAC_GMAC_INT_MSK_OFST   0x3c

The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component.

#define ALT_EMAC_GMAC_INT_MSK_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))

The address of the ALT_EMAC_GMAC_INT_MSK register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_INT_MSK.