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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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These bits determine which byte of data/ecc to write to RAM.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR |
[1] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR |
[7:2] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR |
[31:9] | ??? | 0x0 | UNDEFINED |
Field : DATAOVR | |
RAM Data Override. Override the ECC_dataBUS register with RAM data in read mode set by ECC_RW. 1’b0: Data override disabled. 1’b1: Data override enabled. Field Access Macros: | |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_LSB 0 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_MSB 0 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001) |
Field : ECCOVR | |
ECC Data Override. Field Access Macros: | |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_LSB 1 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_MSB 1 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002) |
Field : RDWR | |
Control for read/write. Field Access Macros: | |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_LSB 8 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_MSB 8 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_WIDTH 1 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_RESET 0x0 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100) |
Data Structures | |
struct | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s |
Macros | |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RESET 0x00000000 |
#define | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_OFST 0x78 |
Typedefs | |
typedef struct ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_t |
struct ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL.
Data Fields | ||
---|---|---|
uint32_t | DATAOVR: 1 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR |
uint32_t | ECCOVR: 1 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR |
uint32_t | __pad0__: 6 | UNDEFINED |
uint32_t | RDWR: 1 | ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR |
uint32_t | __pad1__: 23 | UNDEFINED |
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1 |
The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001 |
The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0 |
The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR field value from a register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR register field value suitable for setting the register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1 |
The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002 |
The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0 |
The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR field value from a register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR register field value suitable for setting the register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_WIDTH 1 |
The width in bits of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100 |
The mask used to set the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_RESET 0x0 |
The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR field value from a register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR register field value suitable for setting the register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RESET 0x00000000 |
The reset value of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL register.
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_OFST 0x78 |
The byte offset of the ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL register from the beginning of the component.
The typedef declaration for register ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL.