Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
Main Page
Address Space
Data Structures
Files
File List
All
Data Structures
Variables
Typedefs
Groups
alt_io48_hmc_mmr.h
1
/***********************************************************************************
2
* *
3
* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4
* *
5
* Redistribution and use in source and binary forms, with or without *
6
* modification, are permitted provided that the following conditions are met: *
7
* *
8
* 1. Redistributions of source code must retain the above copyright notice, *
9
* this list of conditions and the following disclaimer. *
10
* *
11
* 2. Redistributions in binary form must reproduce the above copyright notice, *
12
* this list of conditions and the following disclaimer in the documentation *
13
* and/or other materials provided with the distribution. *
14
* *
15
* 3. Neither the name of the copyright holder nor the names of its contributors *
16
* may be used to endorse or promote products derived from this software without *
17
* specific prior written permission. *
18
* *
19
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29
* POSSIBILITY OF SUCH DAMAGE. *
30
* *
31
***********************************************************************************/
32
35
#ifndef __ALT_SOCAL_IO48_HMC_MMR_H__
36
#define __ALT_SOCAL_IO48_HMC_MMR_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
43
#else
/* __cplusplus */
44
#include <stdint.h>
45
#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
47
77
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB 0
78
79
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB 0
80
81
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH 1
82
83
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK 0x00000001
84
85
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK 0xfffffffe
86
87
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET 0x0
88
89
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value) (((value) & 0x00000001) >> 0)
90
91
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value) (((value) << 0) & 0x00000001)
92
102
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_LSB 1
103
104
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_MSB 1
105
106
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_WIDTH 1
107
108
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET_MSK 0x00000002
109
110
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_CLR_MSK 0xfffffffd
111
112
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_RESET 0x0
113
114
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_GET(value) (((value) & 0x00000002) >> 1)
115
116
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET(value) (((value) << 1) & 0x00000002)
117
127
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_LSB 2
128
129
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_MSB 2
130
131
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_WIDTH 1
132
133
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET_MSK 0x00000004
134
135
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_CLR_MSK 0xfffffffb
136
137
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_RESET 0x0
138
139
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_GET(value) (((value) & 0x00000004) >> 2)
140
141
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET(value) (((value) << 2) & 0x00000004)
142
152
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_LSB 3
153
154
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_MSB 3
155
156
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_WIDTH 1
157
158
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK 0x00000008
159
160
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK 0xfffffff7
161
162
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_RESET 0x0
163
164
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_GET(value) (((value) & 0x00000008) >> 3)
165
166
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET(value) (((value) << 3) & 0x00000008)
167
177
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB 4
178
179
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB 4
180
181
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH 1
182
183
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK 0x00000010
184
185
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK 0xffffffef
186
187
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET 0x0
188
189
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value) (((value) & 0x00000010) >> 4)
190
191
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value) (((value) << 4) & 0x00000010)
192
202
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_LSB 5
203
204
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_MSB 8
205
206
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_WIDTH 4
207
208
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET_MSK 0x000001e0
209
210
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_CLR_MSK 0xfffffe1f
211
212
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_RESET 0x0
213
214
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_GET(value) (((value) & 0x000001e0) >> 5)
215
216
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET(value) (((value) << 5) & 0x000001e0)
217
218
#ifndef __ASSEMBLY__
219
229
struct
ALT_IO48_HMC_MMR_DBGCFG0_s
230
{
231
uint32_t
cfg_wdata_driver_sel
: 1;
232
uint32_t
cfg_prbs_ctrl_sel
: 1;
233
uint32_t
cfg_mmr_driver_sel
: 1;
234
uint32_t
cfg_loopback_en
: 1;
235
uint32_t
cfg_cmd_driver_sel
: 1;
236
uint32_t
cfg_dbg_mode
: 4;
237
uint32_t : 23;
238
};
239
241
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG0_s
ALT_IO48_HMC_MMR_DBGCFG0_t
;
242
#endif
/* __ASSEMBLY__ */
243
245
#define ALT_IO48_HMC_MMR_DBGCFG0_RESET 0x00000000
246
247
#define ALT_IO48_HMC_MMR_DBGCFG0_OFST 0x0
248
268
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_LSB 0
269
270
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_MSB 31
271
272
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_WIDTH 32
273
274
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET_MSK 0xffffffff
275
276
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_CLR_MSK 0x00000000
277
278
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_RESET 0x0
279
280
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_GET(value) (((value) & 0xffffffff) >> 0)
281
282
#define ALT_IO48_HMC_MMR_DBGCFG1_CFG_DBG_CTL_SET(value) (((value) << 0) & 0xffffffff)
283
284
#ifndef __ASSEMBLY__
285
295
struct
ALT_IO48_HMC_MMR_DBGCFG1_s
296
{
297
uint32_t
cfg_dbg_ctrl
: 32;
298
};
299
301
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG1_s
ALT_IO48_HMC_MMR_DBGCFG1_t
;
302
#endif
/* __ASSEMBLY__ */
303
305
#define ALT_IO48_HMC_MMR_DBGCFG1_RESET 0x00000000
306
307
#define ALT_IO48_HMC_MMR_DBGCFG1_OFST 0x4
308
328
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_LSB 0
329
330
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_MSB 31
331
332
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_WIDTH 32
333
334
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET_MSK 0xffffffff
335
336
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_CLR_MSK 0x00000000
337
338
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_RESET 0x0
339
340
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_GET(value) (((value) & 0xffffffff) >> 0)
341
342
#define ALT_IO48_HMC_MMR_DBGCFG2_CFG_BIST_CMD0_U_SET(value) (((value) << 0) & 0xffffffff)
343
344
#ifndef __ASSEMBLY__
345
355
struct
ALT_IO48_HMC_MMR_DBGCFG2_s
356
{
357
uint32_t
cfg_bist_cmd0_u
: 32;
358
};
359
361
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG2_s
ALT_IO48_HMC_MMR_DBGCFG2_t
;
362
#endif
/* __ASSEMBLY__ */
363
365
#define ALT_IO48_HMC_MMR_DBGCFG2_RESET 0x00000000
366
367
#define ALT_IO48_HMC_MMR_DBGCFG2_OFST 0x8
368
388
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_LSB 0
389
390
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_MSB 31
391
392
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_WIDTH 32
393
394
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET_MSK 0xffffffff
395
396
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_CLR_MSK 0x00000000
397
398
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_RESET 0x0
399
400
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_GET(value) (((value) & 0xffffffff) >> 0)
401
402
#define ALT_IO48_HMC_MMR_DBGCFG3_CFG_BIST_CMD0_L_SET(value) (((value) << 0) & 0xffffffff)
403
404
#ifndef __ASSEMBLY__
405
415
struct
ALT_IO48_HMC_MMR_DBGCFG3_s
416
{
417
uint32_t
cfg_bist_cmd0_l
: 32;
418
};
419
421
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG3_s
ALT_IO48_HMC_MMR_DBGCFG3_t
;
422
#endif
/* __ASSEMBLY__ */
423
425
#define ALT_IO48_HMC_MMR_DBGCFG3_RESET 0x00000000
426
427
#define ALT_IO48_HMC_MMR_DBGCFG3_OFST 0xc
428
448
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_LSB 0
449
450
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_MSB 31
451
452
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32
453
454
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff
455
456
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000
457
458
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0
459
460
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0)
461
462
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff)
463
464
#ifndef __ASSEMBLY__
465
475
struct
ALT_IO48_HMC_MMR_DBGCFG4_s
476
{
477
uint32_t
cfg_bist_cmd1_u
: 32;
478
};
479
481
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG4_s
ALT_IO48_HMC_MMR_DBGCFG4_t
;
482
#endif
/* __ASSEMBLY__ */
483
485
#define ALT_IO48_HMC_MMR_DBGCFG4_RESET 0x00000000
486
487
#define ALT_IO48_HMC_MMR_DBGCFG4_OFST 0x10
488
508
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_LSB 0
509
510
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_MSB 31
511
512
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_WIDTH 32
513
514
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET_MSK 0xffffffff
515
516
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_CLR_MSK 0x00000000
517
518
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_RESET 0x0
519
520
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_GET(value) (((value) & 0xffffffff) >> 0)
521
522
#define ALT_IO48_HMC_MMR_DBGCFG5_CFG_BIST_CMD1_L_SET(value) (((value) << 0) & 0xffffffff)
523
524
#ifndef __ASSEMBLY__
525
535
struct
ALT_IO48_HMC_MMR_DBGCFG5_s
536
{
537
uint32_t
cfg_bist_cmd1_l
: 32;
538
};
539
541
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG5_s
ALT_IO48_HMC_MMR_DBGCFG5_t
;
542
#endif
/* __ASSEMBLY__ */
543
545
#define ALT_IO48_HMC_MMR_DBGCFG5_RESET 0x00000000
546
547
#define ALT_IO48_HMC_MMR_DBGCFG5_OFST 0x14
548
569
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_LSB 0
570
571
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_MSB 15
572
573
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_WIDTH 16
574
575
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET_MSK 0x0000ffff
576
577
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_CLR_MSK 0xffff0000
578
579
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_RESET 0x0
580
581
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_GET(value) (((value) & 0x0000ffff) >> 0)
582
583
#define ALT_IO48_HMC_MMR_DBGCFG6_CFG_DBG_OUT_SEL_SET(value) (((value) << 0) & 0x0000ffff)
584
585
#ifndef __ASSEMBLY__
586
596
struct
ALT_IO48_HMC_MMR_DBGCFG6_s
597
{
598
uint32_t
cfg_dbg_out_sel
: 16;
599
uint32_t : 16;
600
};
601
603
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGCFG6_s
ALT_IO48_HMC_MMR_DBGCFG6_t
;
604
#endif
/* __ASSEMBLY__ */
605
607
#define ALT_IO48_HMC_MMR_DBGCFG6_RESET 0x00000000
608
609
#define ALT_IO48_HMC_MMR_DBGCFG6_OFST 0x18
610
631
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_LSB 0
632
633
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_MSB 15
634
635
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_WIDTH 16
636
637
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET_MSK 0x0000ffff
638
639
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_CLR_MSK 0xffff0000
640
641
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_RESET 0x0
642
643
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
644
645
#define ALT_IO48_HMC_MMR_RESERVE0_CFG_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
646
647
#ifndef __ASSEMBLY__
648
658
struct
ALT_IO48_HMC_MMR_RESERVE0_s
659
{
660
uint32_t
cfg_reserve0
: 16;
661
uint32_t : 16;
662
};
663
665
typedef
volatile
struct
ALT_IO48_HMC_MMR_RESERVE0_s
ALT_IO48_HMC_MMR_RESERVE0_t
;
666
#endif
/* __ASSEMBLY__ */
667
669
#define ALT_IO48_HMC_MMR_RESERVE0_RESET 0x00000000
670
671
#define ALT_IO48_HMC_MMR_RESERVE0_OFST 0x1c
672
693
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_LSB 0
694
695
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_MSB 15
696
697
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_WIDTH 16
698
699
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET_MSK 0x0000ffff
700
701
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_CLR_MSK 0xffff0000
702
703
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_RESET 0x0
704
705
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
706
707
#define ALT_IO48_HMC_MMR_RESERVE1_CFG_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
708
709
#ifndef __ASSEMBLY__
710
720
struct
ALT_IO48_HMC_MMR_RESERVE1_s
721
{
722
uint32_t
cfg_reserve1
: 16;
723
uint32_t : 16;
724
};
725
727
typedef
volatile
struct
ALT_IO48_HMC_MMR_RESERVE1_s
ALT_IO48_HMC_MMR_RESERVE1_t
;
728
#endif
/* __ASSEMBLY__ */
729
731
#define ALT_IO48_HMC_MMR_RESERVE1_RESET 0x00000000
732
733
#define ALT_IO48_HMC_MMR_RESERVE1_OFST 0x20
734
755
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_LSB 0
756
757
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_MSB 15
758
759
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_WIDTH 16
760
761
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET_MSK 0x0000ffff
762
763
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_CLR_MSK 0xffff0000
764
765
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_RESET 0x0
766
767
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
768
769
#define ALT_IO48_HMC_MMR_RESERVE2_CFG_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
770
771
#ifndef __ASSEMBLY__
772
782
struct
ALT_IO48_HMC_MMR_RESERVE2_s
783
{
784
uint32_t
cfg_reserve2
: 16;
785
uint32_t : 16;
786
};
787
789
typedef
volatile
struct
ALT_IO48_HMC_MMR_RESERVE2_s
ALT_IO48_HMC_MMR_RESERVE2_t
;
790
#endif
/* __ASSEMBLY__ */
791
793
#define ALT_IO48_HMC_MMR_RESERVE2_RESET 0x00000000
794
795
#define ALT_IO48_HMC_MMR_RESERVE2_OFST 0x24
796
825
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_LSB 0
826
827
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_MSB 3
828
829
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_WIDTH 4
830
831
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET_MSK 0x0000000f
832
833
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_CLR_MSK 0xfffffff0
834
835
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_RESET 0x0
836
837
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_GET(value) (((value) & 0x0000000f) >> 0)
838
839
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET(value) (((value) << 0) & 0x0000000f)
840
851
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_LSB 4
852
853
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_MSB 6
854
855
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_WIDTH 3
856
857
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET_MSK 0x00000070
858
859
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_CLR_MSK 0xffffff8f
860
861
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_RESET 0x0
862
863
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_GET(value) (((value) & 0x00000070) >> 4)
864
865
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET(value) (((value) << 4) & 0x00000070)
866
876
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_LSB 7
877
878
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_MSB 8
879
880
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_WIDTH 2
881
882
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET_MSK 0x00000180
883
884
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_CLR_MSK 0xfffffe7f
885
886
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_RESET 0x0
887
888
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_GET(value) (((value) & 0x00000180) >> 7)
889
890
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET(value) (((value) << 7) & 0x00000180)
891
904
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_LSB 9
905
906
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_MSB 13
907
908
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_WIDTH 5
909
910
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET_MSK 0x00003e00
911
912
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_CLR_MSK 0xffffc1ff
913
914
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_RESET 0x0
915
916
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_GET(value) (((value) & 0x00003e00) >> 9)
917
918
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET(value) (((value) << 9) & 0x00003e00)
919
932
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_LSB 14
933
934
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_MSB 18
935
936
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_WIDTH 5
937
938
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET_MSK 0x0007c000
939
940
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_CLR_MSK 0xfff83fff
941
942
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_RESET 0x0
943
944
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_GET(value) (((value) & 0x0007c000) >> 14)
945
946
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET(value) (((value) << 14) & 0x0007c000)
947
960
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_LSB 19
961
962
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_MSB 23
963
964
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_WIDTH 5
965
966
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET_MSK 0x00f80000
967
968
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_CLR_MSK 0xff07ffff
969
970
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_RESET 0x0
971
972
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_GET(value) (((value) & 0x00f80000) >> 19)
973
974
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET(value) (((value) << 19) & 0x00f80000)
975
988
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_LSB 24
989
990
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_MSB 28
991
992
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_WIDTH 5
993
994
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET_MSK 0x1f000000
995
996
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_CLR_MSK 0xe0ffffff
997
998
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_RESET 0x0
999
1000
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_GET(value) (((value) & 0x1f000000) >> 24)
1001
1002
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET(value) (((value) << 24) & 0x1f000000)
1003
1004
#ifndef __ASSEMBLY__
1005
1015
struct
ALT_IO48_HMC_MMR_CTLCFG0_s
1016
{
1017
uint32_t
cfg_mem_type
: 4;
1018
uint32_t
cfg_dimm_type
: 3;
1019
uint32_t
cfg_ac_pos
: 2;
1020
uint32_t
cfg_ctrl_burst_length
: 5;
1021
uint32_t
cfg_dbc0_burst_length
: 5;
1022
uint32_t
cfg_dbc1_burst_length
: 5;
1023
uint32_t
cfg_dbc2_burst_length
: 5;
1024
uint32_t : 3;
1025
};
1026
1028
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG0_s
ALT_IO48_HMC_MMR_CTLCFG0_t
;
1029
#endif
/* __ASSEMBLY__ */
1030
1032
#define ALT_IO48_HMC_MMR_CTLCFG0_RESET 0x00000000
1033
1034
#define ALT_IO48_HMC_MMR_CTLCFG0_OFST 0x28
1035
1079
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_LSB 0
1080
1081
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_MSB 4
1082
1083
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_WIDTH 5
1084
1085
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET_MSK 0x0000001f
1086
1087
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_CLR_MSK 0xffffffe0
1088
1089
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_RESET 0x0
1090
1091
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_GET(value) (((value) & 0x0000001f) >> 0)
1092
1093
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET(value) (((value) << 0) & 0x0000001f)
1094
1108
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_LSB 5
1109
1110
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_MSB 6
1111
1112
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_WIDTH 2
1113
1114
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET_MSK 0x00000060
1115
1116
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_CLR_MSK 0xffffff9f
1117
1118
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_RESET 0x0
1119
1120
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_GET(value) (((value) & 0x00000060) >> 5)
1121
1122
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET(value) (((value) << 5) & 0x00000060)
1123
1133
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_LSB 7
1134
1135
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_MSB 7
1136
1137
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_WIDTH 1
1138
1139
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET_MSK 0x00000080
1140
1141
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_CLR_MSK 0xffffff7f
1142
1143
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_RESET 0x0
1144
1145
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_GET(value) (((value) & 0x00000080) >> 7)
1146
1147
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET(value) (((value) << 7) & 0x00000080)
1148
1158
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_LSB 8
1159
1160
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_MSB 8
1161
1162
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_WIDTH 1
1163
1164
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET_MSK 0x00000100
1165
1166
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_CLR_MSK 0xfffffeff
1167
1168
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_RESET 0x0
1169
1170
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_GET(value) (((value) & 0x00000100) >> 8)
1171
1172
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET(value) (((value) << 8) & 0x00000100)
1173
1183
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_LSB 9
1184
1185
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_MSB 9
1186
1187
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_WIDTH 1
1188
1189
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET_MSK 0x00000200
1190
1191
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_CLR_MSK 0xfffffdff
1192
1193
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_RESET 0x0
1194
1195
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_GET(value) (((value) & 0x00000200) >> 9)
1196
1197
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET(value) (((value) << 9) & 0x00000200)
1198
1208
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_LSB 10
1209
1210
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_MSB 10
1211
1212
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_WIDTH 1
1213
1214
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET_MSK 0x00000400
1215
1216
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_CLR_MSK 0xfffffbff
1217
1218
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_RESET 0x0
1219
1220
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_GET(value) (((value) & 0x00000400) >> 10)
1221
1222
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET(value) (((value) << 10) & 0x00000400)
1223
1233
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_LSB 11
1234
1235
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_MSB 11
1236
1237
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_WIDTH 1
1238
1239
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET_MSK 0x00000800
1240
1241
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_CLR_MSK 0xfffff7ff
1242
1243
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_RESET 0x0
1244
1245
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_GET(value) (((value) & 0x00000800) >> 11)
1246
1247
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET(value) (((value) << 11) & 0x00000800)
1248
1259
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_LSB 12
1260
1261
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_MSB 12
1262
1263
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_WIDTH 1
1264
1265
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET_MSK 0x00001000
1266
1267
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_CLR_MSK 0xffffefff
1268
1269
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_RESET 0x0
1270
1271
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_GET(value) (((value) & 0x00001000) >> 12)
1272
1273
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET(value) (((value) << 12) & 0x00001000)
1274
1284
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_LSB 13
1285
1286
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_MSB 13
1287
1288
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_WIDTH 1
1289
1290
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET_MSK 0x00002000
1291
1292
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_CLR_MSK 0xffffdfff
1293
1294
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_RESET 0x0
1295
1296
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_GET(value) (((value) & 0x00002000) >> 13)
1297
1298
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET(value) (((value) << 13) & 0x00002000)
1299
1309
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_LSB 14
1310
1311
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_MSB 14
1312
1313
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH 1
1314
1315
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK 0x00004000
1316
1317
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK 0xffffbfff
1318
1319
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_RESET 0x0
1320
1321
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_GET(value) (((value) & 0x00004000) >> 14)
1322
1323
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET(value) (((value) << 14) & 0x00004000)
1324
1334
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_LSB 15
1335
1336
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_MSB 15
1337
1338
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH 1
1339
1340
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK 0x00008000
1341
1342
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK 0xffff7fff
1343
1344
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_RESET 0x0
1345
1346
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_GET(value) (((value) & 0x00008000) >> 15)
1347
1348
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET(value) (((value) << 15) & 0x00008000)
1349
1359
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_LSB 16
1360
1361
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_MSB 16
1362
1363
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH 1
1364
1365
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK 0x00010000
1366
1367
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK 0xfffeffff
1368
1369
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_RESET 0x0
1370
1371
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_GET(value) (((value) & 0x00010000) >> 16)
1372
1373
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET(value) (((value) << 16) & 0x00010000)
1374
1384
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_LSB 17
1385
1386
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_MSB 17
1387
1388
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH 1
1389
1390
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK 0x00020000
1391
1392
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK 0xfffdffff
1393
1394
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_RESET 0x0
1395
1396
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_GET(value) (((value) & 0x00020000) >> 17)
1397
1398
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET(value) (((value) << 17) & 0x00020000)
1399
1409
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_LSB 18
1410
1411
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_MSB 18
1412
1413
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_WIDTH 1
1414
1415
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET_MSK 0x00040000
1416
1417
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_CLR_MSK 0xfffbffff
1418
1419
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_RESET 0x0
1420
1421
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_GET(value) (((value) & 0x00040000) >> 18)
1422
1423
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET(value) (((value) << 18) & 0x00040000)
1424
1436
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_LSB 19
1437
1438
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_MSB 24
1439
1440
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_WIDTH 6
1441
1442
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET_MSK 0x01f80000
1443
1444
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_CLR_MSK 0xfe07ffff
1445
1446
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_RESET 0x0
1447
1448
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_GET(value) (((value) & 0x01f80000) >> 19)
1449
1450
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET(value) (((value) << 19) & 0x01f80000)
1451
1461
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_LSB 25
1462
1463
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_MSB 25
1464
1465
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_WIDTH 1
1466
1467
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET_MSK 0x02000000
1468
1469
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_CLR_MSK 0xfdffffff
1470
1471
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_RESET 0x0
1472
1473
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_GET(value) (((value) & 0x02000000) >> 25)
1474
1475
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET(value) (((value) << 25) & 0x02000000)
1476
1486
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_LSB 26
1487
1488
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_MSB 26
1489
1490
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_WIDTH 1
1491
1492
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET_MSK 0x04000000
1493
1494
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_CLR_MSK 0xfbffffff
1495
1496
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_RESET 0x0
1497
1498
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_GET(value) (((value) & 0x04000000) >> 26)
1499
1500
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET(value) (((value) << 26) & 0x04000000)
1501
1511
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_LSB 27
1512
1513
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_MSB 27
1514
1515
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_WIDTH 1
1516
1517
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET_MSK 0x08000000
1518
1519
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_CLR_MSK 0xf7ffffff
1520
1521
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_RESET 0x0
1522
1523
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_GET(value) (((value) & 0x08000000) >> 27)
1524
1525
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET(value) (((value) << 27) & 0x08000000)
1526
1536
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_LSB 28
1537
1538
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_MSB 28
1539
1540
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_WIDTH 1
1541
1542
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET_MSK 0x10000000
1543
1544
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_CLR_MSK 0xefffffff
1545
1546
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_RESET 0x0
1547
1548
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_GET(value) (((value) & 0x10000000) >> 28)
1549
1550
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET(value) (((value) << 28) & 0x10000000)
1551
1561
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_LSB 29
1562
1563
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_MSB 29
1564
1565
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_WIDTH 1
1566
1567
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET_MSK 0x20000000
1568
1569
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_CLR_MSK 0xdfffffff
1570
1571
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_RESET 0x0
1572
1573
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_GET(value) (((value) & 0x20000000) >> 29)
1574
1575
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET(value) (((value) << 29) & 0x20000000)
1576
1586
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_LSB 30
1587
1588
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_MSB 30
1589
1590
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_WIDTH 1
1591
1592
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET_MSK 0x40000000
1593
1594
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_CLR_MSK 0xbfffffff
1595
1596
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_RESET 0x0
1597
1598
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_GET(value) (((value) & 0x40000000) >> 30)
1599
1600
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET(value) (((value) << 30) & 0x40000000)
1601
1602
#ifndef __ASSEMBLY__
1603
1613
struct
ALT_IO48_HMC_MMR_CTLCFG1_s
1614
{
1615
uint32_t
cfg_dbc3_burst_length
: 5;
1616
uint32_t
cfg_addr_order
: 2;
1617
uint32_t
cfg_ctrl_enable_ecc
: 1;
1618
uint32_t
cfg_dbc0_enable_ecc
: 1;
1619
uint32_t
cfg_dbc1_enable_ecc
: 1;
1620
uint32_t
cfg_dbc2_enable_ecc
: 1;
1621
uint32_t
cfg_dbc3_enable_ecc
: 1;
1622
uint32_t
cfg_reorder_data
: 1;
1623
uint32_t
cfg_ctrl_reorder_rdata
: 1;
1624
uint32_t
cfg_dbc0_reorder_rdata
: 1;
1625
uint32_t
cfg_dbc1_reorder_rdata
: 1;
1626
uint32_t
cfg_dbc2_reorder_rdata
: 1;
1627
uint32_t
cfg_dbc3_reorder_rdata
: 1;
1628
uint32_t
cfg_reorder_read
: 1;
1629
uint32_t
cfg_starve_limit
: 6;
1630
uint32_t
cfg_dqstrk_en
: 1;
1631
uint32_t
cfg_ctrl_enable_dm
: 1;
1632
uint32_t
cfg_dbc0_enable_dm
: 1;
1633
uint32_t
cfg_dbc1_enable_dm
: 1;
1634
uint32_t
cfg_dbc2_enable_dm
: 1;
1635
uint32_t
cfg_dbc3_enable_dm
: 1;
1636
uint32_t : 1;
1637
};
1638
1640
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG1_s
ALT_IO48_HMC_MMR_CTLCFG1_t
;
1641
#endif
/* __ASSEMBLY__ */
1642
1644
#define ALT_IO48_HMC_MMR_CTLCFG1_RESET 0x00000000
1645
1646
#define ALT_IO48_HMC_MMR_CTLCFG1_OFST 0x2c
1647
1683
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_LSB 0
1684
1685
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_MSB 0
1686
1687
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_WIDTH 1
1688
1689
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET_MSK 0x00000001
1690
1691
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_CLR_MSK 0xfffffffe
1692
1693
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_RESET 0x0
1694
1695
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_GET(value) (((value) & 0x00000001) >> 0)
1696
1697
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET(value) (((value) << 0) & 0x00000001)
1698
1708
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_LSB 1
1709
1710
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_MSB 1
1711
1712
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH 1
1713
1714
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK 0x00000002
1715
1716
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK 0xfffffffd
1717
1718
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_RESET 0x0
1719
1720
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value) (((value) & 0x00000002) >> 1)
1721
1722
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value) (((value) << 1) & 0x00000002)
1723
1733
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_LSB 2
1734
1735
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_MSB 2
1736
1737
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH 1
1738
1739
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK 0x00000004
1740
1741
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK 0xfffffffb
1742
1743
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_RESET 0x0
1744
1745
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value) (((value) & 0x00000004) >> 2)
1746
1747
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value) (((value) << 2) & 0x00000004)
1748
1758
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_LSB 3
1759
1760
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_MSB 3
1761
1762
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH 1
1763
1764
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK 0x00000008
1765
1766
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK 0xfffffff7
1767
1768
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_RESET 0x0
1769
1770
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value) (((value) & 0x00000008) >> 3)
1771
1772
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value) (((value) << 3) & 0x00000008)
1773
1783
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_LSB 4
1784
1785
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_MSB 4
1786
1787
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH 1
1788
1789
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK 0x00000010
1790
1791
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK 0xffffffef
1792
1793
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_RESET 0x0
1794
1795
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value) (((value) & 0x00000010) >> 4)
1796
1797
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value) (((value) << 4) & 0x00000010)
1798
1808
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_LSB 5
1809
1810
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_MSB 6
1811
1812
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_WIDTH 2
1813
1814
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET_MSK 0x00000060
1815
1816
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_CLR_MSK 0xffffff9f
1817
1818
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_RESET 0x0
1819
1820
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_GET(value) (((value) & 0x00000060) >> 5)
1821
1822
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET(value) (((value) << 5) & 0x00000060)
1823
1833
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_LSB 7
1834
1835
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_MSB 8
1836
1837
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_WIDTH 2
1838
1839
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET_MSK 0x00000180
1840
1841
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_CLR_MSK 0xfffffe7f
1842
1843
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_RESET 0x0
1844
1845
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_GET(value) (((value) & 0x00000180) >> 7)
1846
1847
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET(value) (((value) << 7) & 0x00000180)
1848
1858
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_LSB 9
1859
1860
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_MSB 9
1861
1862
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_WIDTH 1
1863
1864
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET_MSK 0x00000200
1865
1866
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_CLR_MSK 0xfffffdff
1867
1868
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_RESET 0x0
1869
1870
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_GET(value) (((value) & 0x00000200) >> 9)
1871
1872
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET(value) (((value) << 9) & 0x00000200)
1873
1883
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_LSB 10
1884
1885
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_MSB 10
1886
1887
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_WIDTH 1
1888
1889
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET_MSK 0x00000400
1890
1891
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_CLR_MSK 0xfffffbff
1892
1893
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_RESET 0x0
1894
1895
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_GET(value) (((value) & 0x00000400) >> 10)
1896
1897
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET(value) (((value) << 10) & 0x00000400)
1898
1908
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_LSB 11
1909
1910
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_MSB 11
1911
1912
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_WIDTH 1
1913
1914
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET_MSK 0x00000800
1915
1916
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_CLR_MSK 0xfffff7ff
1917
1918
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_RESET 0x0
1919
1920
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_GET(value) (((value) & 0x00000800) >> 11)
1921
1922
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET(value) (((value) << 11) & 0x00000800)
1923
1933
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_LSB 12
1934
1935
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_MSB 12
1936
1937
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_WIDTH 1
1938
1939
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET_MSK 0x00001000
1940
1941
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_CLR_MSK 0xffffefff
1942
1943
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_RESET 0x0
1944
1945
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_GET(value) (((value) & 0x00001000) >> 12)
1946
1947
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET(value) (((value) << 12) & 0x00001000)
1948
1958
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_LSB 13
1959
1960
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_MSB 14
1961
1962
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_WIDTH 2
1963
1964
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET_MSK 0x00006000
1965
1966
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_CLR_MSK 0xffff9fff
1967
1968
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_RESET 0x0
1969
1970
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_GET(value) (((value) & 0x00006000) >> 13)
1971
1972
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET(value) (((value) << 13) & 0x00006000)
1973
1984
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_LSB 15
1985
1986
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_MSB 17
1987
1988
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_WIDTH 3
1989
1990
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK 0x00038000
1991
1992
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK 0xfffc7fff
1993
1994
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_RESET 0x0
1995
1996
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_GET(value) (((value) & 0x00038000) >> 15)
1997
1998
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET(value) (((value) << 15) & 0x00038000)
1999
2010
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_LSB 18
2011
2012
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_MSB 20
2013
2014
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_WIDTH 3
2015
2016
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK 0x001c0000
2017
2018
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK 0xffe3ffff
2019
2020
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_RESET 0x0
2021
2022
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_GET(value) (((value) & 0x001c0000) >> 18)
2023
2024
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET(value) (((value) << 18) & 0x001c0000)
2025
2036
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_LSB 21
2037
2038
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_MSB 23
2039
2040
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_WIDTH 3
2041
2042
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK 0x00e00000
2043
2044
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK 0xff1fffff
2045
2046
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_RESET 0x0
2047
2048
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_GET(value) (((value) & 0x00e00000) >> 21)
2049
2050
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET(value) (((value) << 21) & 0x00e00000)
2051
2062
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_LSB 24
2063
2064
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_MSB 26
2065
2066
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_WIDTH 3
2067
2068
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK 0x07000000
2069
2070
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK 0xf8ffffff
2071
2072
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_RESET 0x0
2073
2074
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_GET(value) (((value) & 0x07000000) >> 24)
2075
2076
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET(value) (((value) << 24) & 0x07000000)
2077
2078
#ifndef __ASSEMBLY__
2079
2089
struct
ALT_IO48_HMC_MMR_CTLCFG2_s
2090
{
2091
uint32_t
cfg_ctrl_output_regd
: 1;
2092
uint32_t
cfg_dbc0_output_regd
: 1;
2093
uint32_t
cfg_dbc1_output_regd
: 1;
2094
uint32_t
cfg_dbc2_output_regd
: 1;
2095
uint32_t
cfg_dbc3_output_regd
: 1;
2096
uint32_t
cfg_ctrl2dbc_switch0
: 2;
2097
uint32_t
cfg_ctrl2dbc_switch1
: 2;
2098
uint32_t
cfg_dbc0_ctrl_sel
: 1;
2099
uint32_t
cfg_dbc1_ctrl_sel
: 1;
2100
uint32_t
cfg_dbc2_ctrl_sel
: 1;
2101
uint32_t
cfg_dbc3_ctrl_sel
: 1;
2102
uint32_t
cfg_dbc2ctrl_sel
: 2;
2103
uint32_t
cfg_dbc0_pipe_lat
: 3;
2104
uint32_t
cfg_dbc1_pipe_lat
: 3;
2105
uint32_t
cfg_dbc2_pipe_lat
: 3;
2106
uint32_t
cfg_dbc3_pipe_lat
: 3;
2107
uint32_t : 5;
2108
};
2109
2111
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG2_s
ALT_IO48_HMC_MMR_CTLCFG2_t
;
2112
#endif
/* __ASSEMBLY__ */
2113
2115
#define ALT_IO48_HMC_MMR_CTLCFG2_RESET 0x00000000
2116
2117
#define ALT_IO48_HMC_MMR_CTLCFG2_OFST 0x30
2118
2157
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_LSB 0
2158
2159
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_MSB 2
2160
2161
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_WIDTH 3
2162
2163
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET_MSK 0x00000007
2164
2165
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_CLR_MSK 0xfffffff8
2166
2167
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_RESET 0x0
2168
2169
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0)
2170
2171
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007)
2172
2182
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_LSB 3
2183
2184
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_MSB 5
2185
2186
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3
2187
2188
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038
2189
2190
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7
2191
2192
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0
2193
2194
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3)
2195
2196
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038)
2197
2207
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_LSB 6
2208
2209
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_MSB 8
2210
2211
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3
2212
2213
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0
2214
2215
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f
2216
2217
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0
2218
2219
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6)
2220
2221
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0)
2222
2232
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_LSB 9
2233
2234
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_MSB 11
2235
2236
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3
2237
2238
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00
2239
2240
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff
2241
2242
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0
2243
2244
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9)
2245
2246
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00)
2247
2257
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_LSB 12
2258
2259
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_MSB 14
2260
2261
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3
2262
2263
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000
2264
2265
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff
2266
2267
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0
2268
2269
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12)
2270
2271
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000)
2272
2282
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_LSB 15
2283
2284
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_MSB 15
2285
2286
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_WIDTH 1
2287
2288
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET_MSK 0x00008000
2289
2290
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_CLR_MSK 0xffff7fff
2291
2292
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_RESET 0x0
2293
2294
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15)
2295
2296
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000)
2297
2307
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16
2308
2309
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16
2310
2311
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1
2312
2313
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000
2314
2315
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff
2316
2317
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0
2318
2319
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16)
2320
2321
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000)
2322
2332
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17
2333
2334
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17
2335
2336
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1
2337
2338
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000
2339
2340
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff
2341
2342
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0
2343
2344
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17)
2345
2346
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000)
2347
2357
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18
2358
2359
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18
2360
2361
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1
2362
2363
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000
2364
2365
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff
2366
2367
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0
2368
2369
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18)
2370
2371
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000)
2372
2382
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19
2383
2384
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19
2385
2386
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1
2387
2388
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000
2389
2390
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff
2391
2392
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0
2393
2394
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19)
2395
2396
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000)
2397
2407
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_LSB 20
2408
2409
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_MSB 20
2410
2411
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_WIDTH 1
2412
2413
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET_MSK 0x00100000
2414
2415
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_CLR_MSK 0xffefffff
2416
2417
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_RESET 0x0
2418
2419
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20)
2420
2421
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000)
2422
2432
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21
2433
2434
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21
2435
2436
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1
2437
2438
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000
2439
2440
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff
2441
2442
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0
2443
2444
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21)
2445
2446
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000)
2447
2457
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22
2458
2459
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22
2460
2461
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1
2462
2463
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000
2464
2465
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff
2466
2467
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0
2468
2469
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22)
2470
2471
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000)
2472
2482
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23
2483
2484
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23
2485
2486
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1
2487
2488
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000
2489
2490
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff
2491
2492
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0
2493
2494
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23)
2495
2496
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000)
2497
2507
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24
2508
2509
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24
2510
2511
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1
2512
2513
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000
2514
2515
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff
2516
2517
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0
2518
2519
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24)
2520
2521
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000)
2522
2532
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_LSB 25
2533
2534
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_MSB 25
2535
2536
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_WIDTH 1
2537
2538
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000
2539
2540
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff
2541
2542
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_RESET 0x0
2543
2544
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25)
2545
2546
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000)
2547
2558
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_LSB 26
2559
2560
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_MSB 26
2561
2562
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1
2563
2564
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000
2565
2566
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff
2567
2568
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0
2569
2570
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26)
2571
2572
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000)
2573
2583
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_LSB 27
2584
2585
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_MSB 27
2586
2587
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_WIDTH 1
2588
2589
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000
2590
2591
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff
2592
2593
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_RESET 0x0
2594
2595
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27)
2596
2597
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000)
2598
2608
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_LSB 28
2609
2610
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_MSB 30
2611
2612
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_WIDTH 3
2613
2614
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET_MSK 0x70000000
2615
2616
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_CLR_MSK 0x8fffffff
2617
2618
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_RESET 0x0
2619
2620
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_GET(value) (((value) & 0x70000000) >> 28)
2621
2622
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET(value) (((value) << 28) & 0x70000000)
2623
2624
#ifndef __ASSEMBLY__
2625
2635
struct
ALT_IO48_HMC_MMR_CTLCFG3_s
2636
{
2637
uint32_t
cfg_ctrl_cmd_rate
: 3;
2638
uint32_t
cfg_dbc0_cmd_rate
: 3;
2639
uint32_t
cfg_dbc1_cmd_rate
: 3;
2640
uint32_t
cfg_dbc2_cmd_rate
: 3;
2641
uint32_t
cfg_dbc3_cmd_rate
: 3;
2642
uint32_t
cfg_ctrl_in_protocol
: 1;
2643
uint32_t
cfg_dbc0_in_protocol
: 1;
2644
uint32_t
cfg_dbc1_in_protocol
: 1;
2645
uint32_t
cfg_dbc2_in_protocol
: 1;
2646
uint32_t
cfg_dbc3_in_protocol
: 1;
2647
uint32_t
cfg_ctrl_dualport_en
: 1;
2648
uint32_t
cfg_dbc0_dualport_en
: 1;
2649
uint32_t
cfg_dbc1_dualport_en
: 1;
2650
uint32_t
cfg_dbc2_dualport_en
: 1;
2651
uint32_t
cfg_dbc3_dualport_en
: 1;
2652
uint32_t
cfg_arbiter_type
: 1;
2653
uint32_t
cfg_open_page_en
: 1;
2654
uint32_t
cfg_geardn_en
: 1;
2655
uint32_t
cfg_rld3_multibank_mode
: 3;
2656
uint32_t : 1;
2657
};
2658
2660
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG3_s
ALT_IO48_HMC_MMR_CTLCFG3_t
;
2661
#endif
/* __ASSEMBLY__ */
2662
2664
#define ALT_IO48_HMC_MMR_CTLCFG3_RESET 0x00000000
2665
2666
#define ALT_IO48_HMC_MMR_CTLCFG3_OFST 0x34
2667
2698
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_LSB 0
2699
2700
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_MSB 4
2701
2702
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_WIDTH 5
2703
2704
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f
2705
2706
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0
2707
2708
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_RESET 0x0
2709
2710
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0)
2711
2712
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f)
2713
2723
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_LSB 5
2724
2725
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_MSB 6
2726
2727
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_WIDTH 2
2728
2729
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET_MSK 0x00000060
2730
2731
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_CLR_MSK 0xffffff9f
2732
2733
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_RESET 0x0
2734
2735
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_GET(value) (((value) & 0x00000060) >> 5)
2736
2737
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET(value) (((value) << 5) & 0x00000060)
2738
2748
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_LSB 7
2749
2750
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_MSB 9
2751
2752
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_WIDTH 3
2753
2754
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET_MSK 0x00000380
2755
2756
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f
2757
2758
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_RESET 0x0
2759
2760
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7)
2761
2762
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380)
2763
2773
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10
2774
2775
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12
2776
2777
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3
2778
2779
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00
2780
2781
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff
2782
2783
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0
2784
2785
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10)
2786
2787
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00)
2788
2798
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13
2799
2800
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15
2801
2802
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3
2803
2804
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000
2805
2806
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff
2807
2808
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0
2809
2810
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13)
2811
2812
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000)
2813
2823
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16
2824
2825
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18
2826
2827
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3
2828
2829
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000
2830
2831
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff
2832
2833
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0
2834
2835
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16)
2836
2837
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000)
2838
2848
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19
2849
2850
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21
2851
2852
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3
2853
2854
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000
2855
2856
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff
2857
2858
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0
2859
2860
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19)
2861
2862
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000)
2863
2875
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_LSB 22
2876
2877
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_MSB 23
2878
2879
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_WIDTH 2
2880
2881
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET_MSK 0x00c00000
2882
2883
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_CLR_MSK 0xff3fffff
2884
2885
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_RESET 0x0
2886
2887
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22)
2888
2889
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000)
2890
2902
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24
2903
2904
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25
2905
2906
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2
2907
2908
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000
2909
2910
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff
2911
2912
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0
2913
2914
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24)
2915
2916
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000)
2917
2929
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26
2930
2931
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27
2932
2933
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2
2934
2935
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000
2936
2937
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff
2938
2939
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0
2940
2941
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26)
2942
2943
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000)
2944
2956
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28
2957
2958
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29
2959
2960
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2
2961
2962
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000
2963
2964
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff
2965
2966
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0
2967
2968
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28)
2969
2970
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000)
2971
2983
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30
2984
2985
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31
2986
2987
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2
2988
2989
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000
2990
2991
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff
2992
2993
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0
2994
2995
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30)
2996
2997
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000)
2998
2999
#ifndef __ASSEMBLY__
3000
3010
struct
ALT_IO48_HMC_MMR_CTLCFG4_s
3011
{
3012
uint32_t
cfg_tile_id
: 5;
3013
uint32_t
cfg_pingpong_mode
: 2;
3014
uint32_t
cfg_ctrl_slot_rotate_en
: 3;
3015
uint32_t
cfg_dbc0_slot_rotate_en
: 3;
3016
uint32_t
cfg_dbc1_slot_rotate_en
: 3;
3017
uint32_t
cfg_dbc2_slot_rotate_en
: 3;
3018
uint32_t
cfg_dbc3_slot_rotate_en
: 3;
3019
uint32_t
cfg_ctrl_slot_offset
: 2;
3020
uint32_t
cfg_dbc0_slot_offset
: 2;
3021
uint32_t
cfg_dbc1_slot_offset
: 2;
3022
uint32_t
cfg_dbc2_slot_offset
: 2;
3023
uint32_t
cfg_dbc3_slot_offset
: 2;
3024
};
3025
3027
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG4_s
ALT_IO48_HMC_MMR_CTLCFG4_t
;
3028
#endif
/* __ASSEMBLY__ */
3029
3031
#define ALT_IO48_HMC_MMR_CTLCFG4_RESET 0x00000000
3032
3033
#define ALT_IO48_HMC_MMR_CTLCFG4_OFST 0x38
3034
3061
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_LSB 0
3062
3063
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_MSB 3
3064
3065
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_WIDTH 4
3066
3067
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET_MSK 0x0000000f
3068
3069
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_CLR_MSK 0xfffffff0
3070
3071
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_RESET 0x0
3072
3073
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_GET(value) (((value) & 0x0000000f) >> 0)
3074
3075
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET(value) (((value) << 0) & 0x0000000f)
3076
3086
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_LSB 4
3087
3088
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_MSB 7
3089
3090
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_WIDTH 4
3091
3092
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET_MSK 0x000000f0
3093
3094
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK 0xffffff0f
3095
3096
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_RESET 0x0
3097
3098
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_GET(value) (((value) & 0x000000f0) >> 4)
3099
3100
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET(value) (((value) << 4) & 0x000000f0)
3101
3112
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_LSB 8
3113
3114
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_MSB 8
3115
3116
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_WIDTH 1
3117
3118
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET_MSK 0x00000100
3119
3120
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_CLR_MSK 0xfffffeff
3121
3122
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_RESET 0x0
3123
3124
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_GET(value) (((value) & 0x00000100) >> 8)
3125
3126
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET(value) (((value) << 8) & 0x00000100)
3127
3138
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_LSB 9
3139
3140
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_MSB 9
3141
3142
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_WIDTH 1
3143
3144
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET_MSK 0x00000200
3145
3146
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_CLR_MSK 0xfffffdff
3147
3148
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_RESET 0x0
3149
3150
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_GET(value) (((value) & 0x00000200) >> 9)
3151
3152
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET(value) (((value) << 9) & 0x00000200)
3153
3164
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_LSB 10
3165
3166
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_MSB 10
3167
3168
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_WIDTH 1
3169
3170
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET_MSK 0x00000400
3171
3172
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_CLR_MSK 0xfffffbff
3173
3174
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_RESET 0x0
3175
3176
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_GET(value) (((value) & 0x00000400) >> 10)
3177
3178
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET(value) (((value) << 10) & 0x00000400)
3179
3190
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_LSB 11
3191
3192
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_MSB 11
3193
3194
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_WIDTH 1
3195
3196
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET_MSK 0x00000800
3197
3198
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_CLR_MSK 0xfffff7ff
3199
3200
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_RESET 0x0
3201
3202
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_GET(value) (((value) & 0x00000800) >> 11)
3203
3204
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET(value) (((value) << 11) & 0x00000800)
3205
3216
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_LSB 12
3217
3218
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_MSB 12
3219
3220
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_WIDTH 1
3221
3222
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET_MSK 0x00001000
3223
3224
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_CLR_MSK 0xffffefff
3225
3226
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_RESET 0x0
3227
3228
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_GET(value) (((value) & 0x00001000) >> 12)
3229
3230
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET(value) (((value) << 12) & 0x00001000)
3231
3232
#ifndef __ASSEMBLY__
3233
3243
struct
ALT_IO48_HMC_MMR_CTLCFG5_s
3244
{
3245
uint32_t
cfg_col_cmd_slot
: 4;
3246
uint32_t
cfg_row_cmd_slot
: 4;
3247
uint32_t
cfg_ctrl_rc_en
: 1;
3248
uint32_t
cfg_dbc0_rc_en
: 1;
3249
uint32_t
cfg_dbc1_rc_en
: 1;
3250
uint32_t
cfg_dbc2_rc_en
: 1;
3251
uint32_t
cfg_dbc3_rc_en
: 1;
3252
uint32_t : 19;
3253
};
3254
3256
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG5_s
ALT_IO48_HMC_MMR_CTLCFG5_t
;
3257
#endif
/* __ASSEMBLY__ */
3258
3260
#define ALT_IO48_HMC_MMR_CTLCFG5_RESET 0x00000000
3261
3262
#define ALT_IO48_HMC_MMR_CTLCFG5_OFST 0x3c
3263
3286
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_LSB 0
3287
3288
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_MSB 15
3289
3290
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_WIDTH 16
3291
3292
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET_MSK 0x0000ffff
3293
3294
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_CLR_MSK 0xffff0000
3295
3296
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_RESET 0x0
3297
3298
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3299
3300
#define ALT_IO48_HMC_MMR_CTLCFG6_CFG_CS_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3301
3302
#ifndef __ASSEMBLY__
3303
3313
struct
ALT_IO48_HMC_MMR_CTLCFG6_s
3314
{
3315
uint32_t
cfg_cs_chip
: 16;
3316
uint32_t : 16;
3317
};
3318
3320
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG6_s
ALT_IO48_HMC_MMR_CTLCFG6_t
;
3321
#endif
/* __ASSEMBLY__ */
3322
3324
#define ALT_IO48_HMC_MMR_CTLCFG6_RESET 0x00000000
3325
3326
#define ALT_IO48_HMC_MMR_CTLCFG6_OFST 0x40
3327
3350
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_LSB 0
3351
3352
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_MSB 0
3353
3354
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_WIDTH 1
3355
3356
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET_MSK 0x00000001
3357
3358
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_CLR_MSK 0xfffffffe
3359
3360
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_RESET 0x0
3361
3362
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_GET(value) (((value) & 0x00000001) >> 0)
3363
3364
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_CLKGATING_EN_SET(value) (((value) << 0) & 0x00000001)
3365
3376
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_LSB 1
3377
3378
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_MSB 7
3379
3380
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_WIDTH 7
3381
3382
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET_MSK 0x000000fe
3383
3384
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_CLR_MSK 0xffffff01
3385
3386
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_RESET 0x0
3387
3388
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_GET(value) (((value) & 0x000000fe) >> 1)
3389
3390
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_RB_RSVD_ENTRY_SET(value) (((value) << 1) & 0x000000fe)
3391
3402
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_LSB 8
3403
3404
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_MSB 14
3405
3406
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_WIDTH 7
3407
3408
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET_MSK 0x00007f00
3409
3410
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_CLR_MSK 0xffff80ff
3411
3412
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_RESET 0x0
3413
3414
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_GET(value) (((value) & 0x00007f00) >> 8)
3415
3416
#define ALT_IO48_HMC_MMR_CTLCFG7_CFG_WB_RSVD_ENTRY_SET(value) (((value) << 8) & 0x00007f00)
3417
3418
#ifndef __ASSEMBLY__
3419
3429
struct
ALT_IO48_HMC_MMR_CTLCFG7_s
3430
{
3431
uint32_t
cfg_clkgating_en
: 1;
3432
uint32_t
cfg_rb_reserved_entry
: 7;
3433
uint32_t
cfg_wb_reserved_entry
: 7;
3434
uint32_t : 17;
3435
};
3436
3438
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG7_s
ALT_IO48_HMC_MMR_CTLCFG7_t
;
3439
#endif
/* __ASSEMBLY__ */
3440
3442
#define ALT_IO48_HMC_MMR_CTLCFG7_RESET 0x00000000
3443
3444
#define ALT_IO48_HMC_MMR_CTLCFG7_OFST 0x44
3445
3468
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_LSB 0
3469
3470
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_MSB 0
3471
3472
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_WIDTH 1
3473
3474
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET_MSK 0x00000001
3475
3476
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe
3477
3478
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_RESET 0x0
3479
3480
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0)
3481
3482
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001)
3483
3493
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_LSB 1
3494
3495
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_MSB 1
3496
3497
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_WIDTH 1
3498
3499
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET_MSK 0x00000002
3500
3501
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd
3502
3503
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_RESET 0x0
3504
3505
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1)
3506
3507
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002)
3508
3518
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_LSB 2
3519
3520
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_MSB 2
3521
3522
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_WIDTH 1
3523
3524
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET_MSK 0x00000004
3525
3526
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_CLR_MSK 0xfffffffb
3527
3528
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_RESET 0x0
3529
3530
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_GET(value) (((value) & 0x00000004) >> 2)
3531
3532
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET(value) (((value) << 2) & 0x00000004)
3533
3534
#ifndef __ASSEMBLY__
3535
3545
struct
ALT_IO48_HMC_MMR_CTLCFG8_s
3546
{
3547
uint32_t
cfg_3ds_en
: 1;
3548
uint32_t
cfg_ck_inv
: 1;
3549
uint32_t
cfg_addr_mplx_en
: 1;
3550
uint32_t : 29;
3551
};
3552
3554
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG8_s
ALT_IO48_HMC_MMR_CTLCFG8_t
;
3555
#endif
/* __ASSEMBLY__ */
3556
3558
#define ALT_IO48_HMC_MMR_CTLCFG8_RESET 0x00000000
3559
3560
#define ALT_IO48_HMC_MMR_CTLCFG8_OFST 0x48
3561
3582
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_LSB 0
3583
3584
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_MSB 0
3585
3586
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_WIDTH 1
3587
3588
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET_MSK 0x00000001
3589
3590
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_CLR_MSK 0xfffffffe
3591
3592
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_RESET 0x0
3593
3594
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_GET(value) (((value) & 0x00000001) >> 0)
3595
3596
#define ALT_IO48_HMC_MMR_CTLCFG9_CFG_DFX_BYPASS_EN_SET(value) (((value) << 0) & 0x00000001)
3597
3598
#ifndef __ASSEMBLY__
3599
3609
struct
ALT_IO48_HMC_MMR_CTLCFG9_s
3610
{
3611
uint32_t
cfg_dfx_bypass_en
: 1;
3612
uint32_t : 31;
3613
};
3614
3616
typedef
volatile
struct
ALT_IO48_HMC_MMR_CTLCFG9_s
ALT_IO48_HMC_MMR_CTLCFG9_t
;
3617
#endif
/* __ASSEMBLY__ */
3618
3620
#define ALT_IO48_HMC_MMR_CTLCFG9_RESET 0x00000000
3621
3622
#define ALT_IO48_HMC_MMR_CTLCFG9_OFST 0x4c
3623
3646
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_LSB 0
3647
3648
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_MSB 6
3649
3650
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_WIDTH 7
3651
3652
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET_MSK 0x0000007f
3653
3654
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_CLR_MSK 0xffffff80
3655
3656
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_RESET 0x0
3657
3658
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_GET(value) (((value) & 0x0000007f) >> 0)
3659
3660
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET(value) (((value) << 0) & 0x0000007f)
3661
3672
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB 7
3673
3674
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB 12
3675
3676
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH 6
3677
3678
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK 0x00001f80
3679
3680
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK 0xffffe07f
3681
3682
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET 0x0
3683
3684
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value) (((value) & 0x00001f80) >> 7)
3685
3686
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value) (((value) << 7) & 0x00001f80)
3687
3699
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_LSB 13
3700
3701
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_MSB 18
3702
3703
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_WIDTH 6
3704
3705
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET_MSK 0x0007e000
3706
3707
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_CLR_MSK 0xfff81fff
3708
3709
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_RESET 0x0
3710
3711
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_GET(value) (((value) & 0x0007e000) >> 13)
3712
3713
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET(value) (((value) << 13) & 0x0007e000)
3714
3715
#ifndef __ASSEMBLY__
3716
3726
struct
ALT_IO48_HMC_MMR_DRAMTIMING0_s
3727
{
3728
uint32_t
cfg_tcl
: 7;
3729
uint32_t
cfg_power_saving_exit_cycles
: 6;
3730
uint32_t
cfg_mem_clk_disable_entry_cycles
: 6;
3731
uint32_t : 13;
3732
};
3733
3735
typedef
volatile
struct
ALT_IO48_HMC_MMR_DRAMTIMING0_s
ALT_IO48_HMC_MMR_DRAMTIMING0_t
;
3736
#endif
/* __ASSEMBLY__ */
3737
3739
#define ALT_IO48_HMC_MMR_DRAMTIMING0_RESET 0x00000000
3740
3741
#define ALT_IO48_HMC_MMR_DRAMTIMING0_OFST 0x50
3742
3765
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_LSB 0
3766
3767
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_MSB 15
3768
3769
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_WIDTH 16
3770
3771
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET_MSK 0x0000ffff
3772
3773
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_CLR_MSK 0xffff0000
3774
3775
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_RESET 0x0
3776
3777
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000ffff) >> 0)
3778
3779
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000ffff)
3780
3792
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_LSB 16
3793
3794
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_MSB 31
3795
3796
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_WIDTH 16
3797
3798
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET_MSK 0xffff0000
3799
3800
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_CLR_MSK 0x0000ffff
3801
3802
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_RESET 0x0
3803
3804
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_GET(value) (((value) & 0xffff0000) >> 16)
3805
3806
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET(value) (((value) << 16) & 0xffff0000)
3807
3808
#ifndef __ASSEMBLY__
3809
3819
struct
ALT_IO48_HMC_MMR_DRAMODT0_s
3820
{
3821
uint32_t
cfg_write_odt_chip
: 16;
3822
uint32_t
cfg_read_odt_chip
: 16;
3823
};
3824
3826
typedef
volatile
struct
ALT_IO48_HMC_MMR_DRAMODT0_s
ALT_IO48_HMC_MMR_DRAMODT0_t
;
3827
#endif
/* __ASSEMBLY__ */
3828
3830
#define ALT_IO48_HMC_MMR_DRAMODT0_RESET 0x00000000
3831
3832
#define ALT_IO48_HMC_MMR_DRAMODT0_OFST 0x54
3833
3858
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_LSB 0
3859
3860
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_MSB 5
3861
3862
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_WIDTH 6
3863
3864
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET_MSK 0x0000003f
3865
3866
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK 0xffffffc0
3867
3868
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_RESET 0x0
3869
3870
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_GET(value) (((value) & 0x0000003f) >> 0)
3871
3872
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET(value) (((value) << 0) & 0x0000003f)
3873
3884
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_LSB 6
3885
3886
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_MSB 11
3887
3888
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_WIDTH 6
3889
3890
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET_MSK 0x00000fc0
3891
3892
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK 0xfffff03f
3893
3894
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_RESET 0x0
3895
3896
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_GET(value) (((value) & 0x00000fc0) >> 6)
3897
3898
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET(value) (((value) << 6) & 0x00000fc0)
3899
3910
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_LSB 12
3911
3912
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_MSB 17
3913
3914
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH 6
3915
3916
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK 0x0003f000
3917
3918
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK 0xfffc0fff
3919
3920
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_RESET 0x0
3921
3922
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value) (((value) & 0x0003f000) >> 12)
3923
3924
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value) (((value) << 12) & 0x0003f000)
3925
3936
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_LSB 18
3937
3938
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_MSB 23
3939
3940
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH 6
3941
3942
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK 0x00fc0000
3943
3944
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK 0xff03ffff
3945
3946
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_RESET 0x0
3947
3948
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value) (((value) & 0x00fc0000) >> 18)
3949
3950
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value) (((value) << 18) & 0x00fc0000)
3951
3952
#ifndef __ASSEMBLY__
3953
3963
struct
ALT_IO48_HMC_MMR_DRAMODT1_s
3964
{
3965
uint32_t
cfg_wr_odt_on
: 6;
3966
uint32_t
cfg_rd_odt_on
: 6;
3967
uint32_t
cfg_wr_odt_period
: 6;
3968
uint32_t
cfg_rd_odt_period
: 6;
3969
uint32_t : 8;
3970
};
3971
3973
typedef
volatile
struct
ALT_IO48_HMC_MMR_DRAMODT1_s
ALT_IO48_HMC_MMR_DRAMODT1_t
;
3974
#endif
/* __ASSEMBLY__ */
3975
3977
#define ALT_IO48_HMC_MMR_DRAMODT1_RESET 0x00000000
3978
3979
#define ALT_IO48_HMC_MMR_DRAMODT1_OFST 0x58
3980
4001
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB 0
4002
4003
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB 15
4004
4005
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH 16
4006
4007
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK 0x0000ffff
4008
4009
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK 0xffff0000
4010
4011
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET 0x0
4012
4013
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value) (((value) & 0x0000ffff) >> 0)
4014
4015
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value) (((value) << 0) & 0x0000ffff)
4016
4026
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB 16
4027
4028
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB 31
4029
4030
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH 16
4031
4032
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK 0xffff0000
4033
4034
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK 0x0000ffff
4035
4036
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET 0x0
4037
4038
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value) (((value) & 0xffff0000) >> 16)
4039
4040
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value) (((value) << 16) & 0xffff0000)
4041
4042
#ifndef __ASSEMBLY__
4043
4053
struct
ALT_IO48_HMC_MMR_SBCFG0_s
4054
{
4055
uint32_t
cfg_rld3_refresh_seq0
: 16;
4056
uint32_t
cfg_rld3_refresh_seq1
: 16;
4057
};
4058
4060
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG0_s
ALT_IO48_HMC_MMR_SBCFG0_t
;
4061
#endif
/* __ASSEMBLY__ */
4062
4064
#define ALT_IO48_HMC_MMR_SBCFG0_RESET 0x00000000
4065
4066
#define ALT_IO48_HMC_MMR_SBCFG0_OFST 0x5c
4067
4088
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_LSB 0
4089
4090
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_MSB 15
4091
4092
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_WIDTH 16
4093
4094
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET_MSK 0x0000ffff
4095
4096
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_CLR_MSK 0xffff0000
4097
4098
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_RESET 0x0
4099
4100
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_GET(value) (((value) & 0x0000ffff) >> 0)
4101
4102
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ2_SET(value) (((value) << 0) & 0x0000ffff)
4103
4113
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_LSB 16
4114
4115
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_MSB 31
4116
4117
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_WIDTH 16
4118
4119
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET_MSK 0xffff0000
4120
4121
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_CLR_MSK 0x0000ffff
4122
4123
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_RESET 0x0
4124
4125
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_GET(value) (((value) & 0xffff0000) >> 16)
4126
4127
#define ALT_IO48_HMC_MMR_SBCFG1_CFG_RLD3_REFRESH_SEQ3_SET(value) (((value) << 16) & 0xffff0000)
4128
4129
#ifndef __ASSEMBLY__
4130
4140
struct
ALT_IO48_HMC_MMR_SBCFG1_s
4141
{
4142
uint32_t
cfg_rld3_refresh_seq2
: 16;
4143
uint32_t
cfg_rld3_refresh_seq3
: 16;
4144
};
4145
4147
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG1_s
ALT_IO48_HMC_MMR_SBCFG1_t
;
4148
#endif
/* __ASSEMBLY__ */
4149
4151
#define ALT_IO48_HMC_MMR_SBCFG1_RESET 0x00000000
4152
4153
#define ALT_IO48_HMC_MMR_SBCFG1_OFST 0x60
4154
4181
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_LSB 0
4182
4183
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_MSB 0
4184
4185
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_WIDTH 1
4186
4187
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET_MSK 0x00000001
4188
4189
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_CLR_MSK 0xfffffffe
4190
4191
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_RESET 0x0
4192
4193
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_GET(value) (((value) & 0x00000001) >> 0)
4194
4195
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ZQCAL_DIS_SET(value) (((value) << 0) & 0x00000001)
4196
4206
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_LSB 1
4207
4208
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_MSB 1
4209
4210
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_WIDTH 1
4211
4212
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET_MSK 0x00000002
4213
4214
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_CLR_MSK 0xfffffffd
4215
4216
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_RESET 0x0
4217
4218
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_GET(value) (((value) & 0x00000002) >> 1)
4219
4220
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_ZQCAL_DIS_SET(value) (((value) << 1) & 0x00000002)
4221
4231
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_LSB 2
4232
4233
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_MSB 2
4234
4235
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_WIDTH 1
4236
4237
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET_MSK 0x00000004
4238
4239
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_CLR_MSK 0xfffffffb
4240
4241
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_RESET 0x0
4242
4243
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_GET(value) (((value) & 0x00000004) >> 2)
4244
4245
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_MPS_DQSTRK_DIS_SET(value) (((value) << 2) & 0x00000004)
4246
4256
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_LSB 3
4257
4258
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_MSB 3
4259
4260
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_WIDTH 1
4261
4262
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET_MSK 0x00000008
4263
4264
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_CLR_MSK 0xfffffff7
4265
4266
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_RESET 0x0
4267
4268
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_GET(value) (((value) & 0x00000008) >> 3)
4269
4270
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SB_CG_DIS_SET(value) (((value) << 3) & 0x00000008)
4271
4281
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_LSB 4
4282
4283
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_MSB 4
4284
4285
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_WIDTH 1
4286
4287
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET_MSK 0x00000010
4288
4289
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_CLR_MSK 0xffffffef
4290
4291
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_RESET 0x0
4292
4293
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_GET(value) (((value) & 0x00000010) >> 4)
4294
4295
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_USER_RFSH_EN_SET(value) (((value) << 4) & 0x00000010)
4296
4307
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_LSB 5
4308
4309
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_MSB 5
4310
4311
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_WIDTH 1
4312
4313
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET_MSK 0x00000020
4314
4315
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_CLR_MSK 0xffffffdf
4316
4317
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_RESET 0x0
4318
4319
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_GET(value) (((value) & 0x00000020) >> 5)
4320
4321
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_AUTOEXIT_EN_SET(value) (((value) << 5) & 0x00000020)
4322
4332
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_LSB 6
4333
4334
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_MSB 7
4335
4336
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_WIDTH 2
4337
4338
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET_MSK 0x000000c0
4339
4340
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_CLR_MSK 0xffffff3f
4341
4342
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_RESET 0x0
4343
4344
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_GET(value) (((value) & 0x000000c0) >> 6)
4345
4346
#define ALT_IO48_HMC_MMR_SBCFG2_CFG_SRF_ENTRY_EXIT_BLOCK_SET(value) (((value) << 6) & 0x000000c0)
4347
4348
#ifndef __ASSEMBLY__
4349
4359
struct
ALT_IO48_HMC_MMR_SBCFG2_s
4360
{
4361
uint32_t
cfg_srf_zqcal_disable
: 1;
4362
uint32_t
cfg_mps_zqcal_disable
: 1;
4363
uint32_t
cfg_mps_dqstrk_disable
: 1;
4364
uint32_t
cfg_sb_cg_disable
: 1;
4365
uint32_t
cfg_user_rfsh_en
: 1;
4366
uint32_t
cfg_srf_autoexit_en
: 1;
4367
uint32_t
cfg_srf_entry_exit_block
: 2;
4368
uint32_t : 24;
4369
};
4370
4372
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG2_s
ALT_IO48_HMC_MMR_SBCFG2_t
;
4373
#endif
/* __ASSEMBLY__ */
4374
4376
#define ALT_IO48_HMC_MMR_SBCFG2_RESET 0x00000000
4377
4378
#define ALT_IO48_HMC_MMR_SBCFG2_OFST 0x64
4379
4400
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_LSB 0
4401
4402
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_MSB 19
4403
4404
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_WIDTH 20
4405
4406
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET_MSK 0x000fffff
4407
4408
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_CLR_MSK 0xfff00000
4409
4410
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_RESET 0x0
4411
4412
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_GET(value) (((value) & 0x000fffff) >> 0)
4413
4414
#define ALT_IO48_HMC_MMR_SBCFG3_CFG_SB_DDR4_MR3_SET(value) (((value) << 0) & 0x000fffff)
4415
4416
#ifndef __ASSEMBLY__
4417
4427
struct
ALT_IO48_HMC_MMR_SBCFG3_s
4428
{
4429
uint32_t
cfg_sb_ddr4_mr3
: 20;
4430
uint32_t : 12;
4431
};
4432
4434
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG3_s
ALT_IO48_HMC_MMR_SBCFG3_t
;
4435
#endif
/* __ASSEMBLY__ */
4436
4438
#define ALT_IO48_HMC_MMR_SBCFG3_RESET 0x00000000
4439
4440
#define ALT_IO48_HMC_MMR_SBCFG3_OFST 0x68
4441
4462
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_LSB 0
4463
4464
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_MSB 19
4465
4466
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_WIDTH 20
4467
4468
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET_MSK 0x000fffff
4469
4470
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_CLR_MSK 0xfff00000
4471
4472
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_RESET 0x0
4473
4474
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_GET(value) (((value) & 0x000fffff) >> 0)
4475
4476
#define ALT_IO48_HMC_MMR_SBCFG4_CFG_SB_DDR4_MR4_SET(value) (((value) << 0) & 0x000fffff)
4477
4478
#ifndef __ASSEMBLY__
4479
4489
struct
ALT_IO48_HMC_MMR_SBCFG4_s
4490
{
4491
uint32_t
cfg_sb_ddr4_mr4
: 20;
4492
uint32_t : 12;
4493
};
4494
4496
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG4_s
ALT_IO48_HMC_MMR_SBCFG4_t
;
4497
#endif
/* __ASSEMBLY__ */
4498
4500
#define ALT_IO48_HMC_MMR_SBCFG4_RESET 0x00000000
4501
4502
#define ALT_IO48_HMC_MMR_SBCFG4_OFST 0x6c
4503
4526
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_LSB 0
4527
4528
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_MSB 0
4529
4530
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_WIDTH 1
4531
4532
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET_MSK 0x00000001
4533
4534
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_CLR_MSK 0xfffffffe
4535
4536
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_RESET 0x0
4537
4538
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000001) >> 0)
4539
4540
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET(value) (((value) << 0) & 0x00000001)
4541
4551
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_LSB 1
4552
4553
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_MSB 1
4554
4555
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_WIDTH 1
4556
4557
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET_MSK 0x00000002
4558
4559
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_CLR_MSK 0xfffffffd
4560
4561
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_RESET 0x0
4562
4563
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000002) >> 1)
4564
4565
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET(value) (((value) << 1) & 0x00000002)
4566
4567
#ifndef __ASSEMBLY__
4568
4578
struct
ALT_IO48_HMC_MMR_SBCFG5_s
4579
{
4580
uint32_t
cfg_short_dqstrk_ctrl_en
: 1;
4581
uint32_t
cfg_period_dqstrk_ctrl_en
: 1;
4582
uint32_t : 30;
4583
};
4584
4586
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG5_s
ALT_IO48_HMC_MMR_SBCFG5_t
;
4587
#endif
/* __ASSEMBLY__ */
4588
4590
#define ALT_IO48_HMC_MMR_SBCFG5_RESET 0x00000000
4591
4592
#define ALT_IO48_HMC_MMR_SBCFG5_OFST 0x70
4593
4615
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB 0
4616
4617
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB 15
4618
4619
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH 16
4620
4621
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK 0x0000ffff
4622
4623
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK 0xffff0000
4624
4625
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET 0x0
4626
4627
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value) (((value) & 0x0000ffff) >> 0)
4628
4629
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value) (((value) << 0) & 0x0000ffff)
4630
4640
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB 16
4641
4642
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB 23
4643
4644
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH 8
4645
4646
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK 0x00ff0000
4647
4648
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK 0xff00ffff
4649
4650
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET 0x0
4651
4652
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value) (((value) & 0x00ff0000) >> 16)
4653
4654
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value) (((value) << 16) & 0x00ff0000)
4655
4665
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB 24
4666
4667
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB 31
4668
4669
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH 8
4670
4671
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK 0xff000000
4672
4673
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK 0x00ffffff
4674
4675
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET 0x0
4676
4677
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value) (((value) & 0xff000000) >> 24)
4678
4679
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value) (((value) << 24) & 0xff000000)
4680
4681
#ifndef __ASSEMBLY__
4682
4692
struct
ALT_IO48_HMC_MMR_SBCFG6_s
4693
{
4694
uint32_t
cfg_period_dqstrk_interval
: 16;
4695
uint32_t
cfg_t_param_dqstrk_to_valid_last
: 8;
4696
uint32_t
cfg_t_param_dqstrk_to_valid
: 8;
4697
};
4698
4700
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG6_s
ALT_IO48_HMC_MMR_SBCFG6_t
;
4701
#endif
/* __ASSEMBLY__ */
4702
4704
#define ALT_IO48_HMC_MMR_SBCFG6_RESET 0x00000000
4705
4706
#define ALT_IO48_HMC_MMR_SBCFG6_OFST 0x74
4707
4729
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB 0
4730
4731
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB 6
4732
4733
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH 7
4734
4735
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK 0x0000007f
4736
4737
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK 0xffffff80
4738
4739
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET 0x0
4740
4741
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value) (((value) & 0x0000007f) >> 0)
4742
4743
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value) (((value) << 0) & 0x0000007f)
4744
4745
#ifndef __ASSEMBLY__
4746
4756
struct
ALT_IO48_HMC_MMR_SBCFG7_s
4757
{
4758
uint32_t
cfg_rfsh_warn_threshold
: 7;
4759
uint32_t : 25;
4760
};
4761
4763
typedef
volatile
struct
ALT_IO48_HMC_MMR_SBCFG7_s
ALT_IO48_HMC_MMR_SBCFG7_t
;
4764
#endif
/* __ASSEMBLY__ */
4765
4767
#define ALT_IO48_HMC_MMR_SBCFG7_RESET 0x00000000
4768
4769
#define ALT_IO48_HMC_MMR_SBCFG7_OFST 0x78
4770
4795
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_LSB 0
4796
4797
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_MSB 5
4798
4799
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_WIDTH 6
4800
4801
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET_MSK 0x0000003f
4802
4803
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_CLR_MSK 0xffffffc0
4804
4805
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_RESET 0x0
4806
4807
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_GET(value) (((value) & 0x0000003f) >> 0)
4808
4809
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_RDWR_SET(value) (((value) << 0) & 0x0000003f)
4810
4820
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_LSB 6
4821
4822
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_MSB 11
4823
4824
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_WIDTH 6
4825
4826
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET_MSK 0x00000fc0
4827
4828
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_CLR_MSK 0xfffff03f
4829
4830
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_RESET 0x0
4831
4832
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
4833
4834
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
4835
4845
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_LSB 12
4846
4847
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_MSB 17
4848
4849
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_WIDTH 6
4850
4851
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET_MSK 0x0003f000
4852
4853
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_CLR_MSK 0xfffc0fff
4854
4855
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_RESET 0x0
4856
4857
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_GET(value) (((value) & 0x0003f000) >> 12)
4858
4859
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_SET(value) (((value) << 12) & 0x0003f000)
4860
4870
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_LSB 18
4871
4872
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_MSB 23
4873
4874
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH 6
4875
4876
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET_MSK 0x00fc0000
4877
4878
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_CLR_MSK 0xff03ffff
4879
4880
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_RESET 0x0
4881
4882
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_GET(value) (((value) & 0x00fc0000) >> 18)
4883
4884
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BANK_SET(value) (((value) << 18) & 0x00fc0000)
4885
4895
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_LSB 24
4896
4897
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_MSB 29
4898
4899
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_WIDTH 6
4900
4901
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET_MSK 0x3f000000
4902
4903
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_CLR_MSK 0xc0ffffff
4904
4905
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_RESET 0x0
4906
4907
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_GET(value) (((value) & 0x3f000000) >> 24)
4908
4909
#define ALT_IO48_HMC_MMR_CALTIMING0_CFG_T_PARAM_ACT_TO_ACT_DIFF_BG_SET(value) (((value) << 24) & 0x3f000000)
4910
4911
#ifndef __ASSEMBLY__
4912
4922
struct
ALT_IO48_HMC_MMR_CALTIMING0_s
4923
{
4924
uint32_t
cfg_t_param_act_to_rdwr
: 6;
4925
uint32_t
cfg_t_param_act_to_pch
: 6;
4926
uint32_t
cfg_t_param_act_to_act
: 6;
4927
uint32_t
cfg_t_param_act_to_act_diff_bank
: 6;
4928
uint32_t
cfg_t_param_act_to_act_diff_bg
: 6;
4929
uint32_t : 2;
4930
};
4931
4933
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING0_s
ALT_IO48_HMC_MMR_CALTIMING0_t
;
4934
#endif
/* __ASSEMBLY__ */
4935
4937
#define ALT_IO48_HMC_MMR_CALTIMING0_RESET 0x00000000
4938
4939
#define ALT_IO48_HMC_MMR_CALTIMING0_OFST 0x7c
4940
4965
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0
4966
4967
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5
4968
4969
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6
4970
4971
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f
4972
4973
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0
4974
4975
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0
4976
4977
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0)
4978
4979
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f)
4980
4990
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6
4991
4992
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11
4993
4994
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6
4995
4996
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0
4997
4998
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f
4999
5000
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0
5001
5002
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6)
5003
5004
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0)
5005
5015
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12
5016
5017
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17
5018
5019
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6
5020
5021
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000
5022
5023
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff
5024
5025
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0
5026
5027
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12)
5028
5029
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000)
5030
5040
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18
5041
5042
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23
5043
5044
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6
5045
5046
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000
5047
5048
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff
5049
5050
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0
5051
5052
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5053
5054
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5055
5065
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24
5066
5067
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29
5068
5069
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6
5070
5071
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5072
5073
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5074
5075
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0
5076
5077
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5078
5079
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5080
5081
#ifndef __ASSEMBLY__
5082
5092
struct
ALT_IO48_HMC_MMR_CALTIMING1_s
5093
{
5094
uint32_t
cfg_t_param_rd_to_rd
: 6;
5095
uint32_t
cfg_t_param_rd_to_rd_diff_chip
: 6;
5096
uint32_t
cfg_t_param_rd_to_rd_diff_bg
: 6;
5097
uint32_t
cfg_t_param_rd_to_wr
: 6;
5098
uint32_t
cfg_t_param_rd_to_wr_diff_chip
: 6;
5099
uint32_t : 2;
5100
};
5101
5103
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING1_s
ALT_IO48_HMC_MMR_CALTIMING1_t
;
5104
#endif
/* __ASSEMBLY__ */
5105
5107
#define ALT_IO48_HMC_MMR_CALTIMING1_RESET 0x00000000
5108
5109
#define ALT_IO48_HMC_MMR_CALTIMING1_OFST 0x80
5110
5135
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_LSB 0
5136
5137
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_MSB 5
5138
5139
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_WIDTH 6
5140
5141
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5142
5143
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5144
5145
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_RESET 0x0
5146
5147
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5148
5149
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5150
5160
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_LSB 6
5161
5162
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_MSB 11
5163
5164
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_WIDTH 6
5165
5166
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET_MSK 0x00000fc0
5167
5168
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_CLR_MSK 0xfffff03f
5169
5170
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_RESET 0x0
5171
5172
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_GET(value) (((value) & 0x00000fc0) >> 6)
5173
5174
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_TO_PCH_SET(value) (((value) << 6) & 0x00000fc0)
5175
5185
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_LSB 12
5186
5187
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_MSB 17
5188
5189
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_WIDTH 6
5190
5191
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET_MSK 0x0003f000
5192
5193
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_CLR_MSK 0xfffc0fff
5194
5195
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_RESET 0x0
5196
5197
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5198
5199
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_RD_AP_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5200
5210
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_LSB 18
5211
5212
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_MSB 23
5213
5214
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_WIDTH 6
5215
5216
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET_MSK 0x00fc0000
5217
5218
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_CLR_MSK 0xff03ffff
5219
5220
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_RESET 0x0
5221
5222
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18)
5223
5224
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_SET(value) (((value) << 18) & 0x00fc0000)
5225
5235
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_LSB 24
5236
5237
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_MSB 29
5238
5239
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH 6
5240
5241
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000
5242
5243
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff
5244
5245
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_RESET 0x0
5246
5247
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24)
5248
5249
#define ALT_IO48_HMC_MMR_CALTIMING2_CFG_T_PARAM_WR_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000)
5250
5251
#ifndef __ASSEMBLY__
5252
5262
struct
ALT_IO48_HMC_MMR_CALTIMING2_s
5263
{
5264
uint32_t
cfg_t_param_rd_to_wr_diff_bg
: 6;
5265
uint32_t
cfg_t_param_rd_to_pch
: 6;
5266
uint32_t
cfg_t_param_rd_ap_to_valid
: 6;
5267
uint32_t
cfg_t_param_wr_to_wr
: 6;
5268
uint32_t
cfg_t_param_wr_to_wr_diff_chip
: 6;
5269
uint32_t : 2;
5270
};
5271
5273
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING2_s
ALT_IO48_HMC_MMR_CALTIMING2_t
;
5274
#endif
/* __ASSEMBLY__ */
5275
5277
#define ALT_IO48_HMC_MMR_CALTIMING2_RESET 0x00000000
5278
5279
#define ALT_IO48_HMC_MMR_CALTIMING2_OFST 0x84
5280
5305
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_LSB 0
5306
5307
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_MSB 5
5308
5309
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_WIDTH 6
5310
5311
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET_MSK 0x0000003f
5312
5313
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_CLR_MSK 0xffffffc0
5314
5315
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_RESET 0x0
5316
5317
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_GET(value) (((value) & 0x0000003f) >> 0)
5318
5319
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_WR_DIFF_BG_SET(value) (((value) << 0) & 0x0000003f)
5320
5330
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_LSB 6
5331
5332
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_MSB 11
5333
5334
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_WIDTH 6
5335
5336
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET_MSK 0x00000fc0
5337
5338
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_CLR_MSK 0xfffff03f
5339
5340
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_RESET 0x0
5341
5342
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_GET(value) (((value) & 0x00000fc0) >> 6)
5343
5344
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_SET(value) (((value) << 6) & 0x00000fc0)
5345
5355
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_LSB 12
5356
5357
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_MSB 17
5358
5359
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH 6
5360
5361
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET_MSK 0x0003f000
5362
5363
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_CLR_MSK 0xfffc0fff
5364
5365
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_RESET 0x0
5366
5367
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x0003f000) >> 12)
5368
5369
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_CHIP_SET(value) (((value) << 12) & 0x0003f000)
5370
5380
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_LSB 18
5381
5382
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_MSB 23
5383
5384
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_WIDTH 6
5385
5386
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET_MSK 0x00fc0000
5387
5388
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_CLR_MSK 0xff03ffff
5389
5390
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_RESET 0x0
5391
5392
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_GET(value) (((value) & 0x00fc0000) >> 18)
5393
5394
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_RD_DIFF_BG_SET(value) (((value) << 18) & 0x00fc0000)
5395
5405
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_LSB 24
5406
5407
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_MSB 29
5408
5409
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_WIDTH 6
5410
5411
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET_MSK 0x3f000000
5412
5413
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_CLR_MSK 0xc0ffffff
5414
5415
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_RESET 0x0
5416
5417
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_GET(value) (((value) & 0x3f000000) >> 24)
5418
5419
#define ALT_IO48_HMC_MMR_CALTIMING3_CFG_T_PARAM_WR_TO_PCH_SET(value) (((value) << 24) & 0x3f000000)
5420
5421
#ifndef __ASSEMBLY__
5422
5432
struct
ALT_IO48_HMC_MMR_CALTIMING3_s
5433
{
5434
uint32_t
cfg_t_param_wr_to_wr_diff_bg
: 6;
5435
uint32_t
cfg_t_param_wr_to_rd
: 6;
5436
uint32_t
cfg_t_param_wr_to_rd_diff_chip
: 6;
5437
uint32_t
cfg_t_param_wr_to_rd_diff_bg
: 6;
5438
uint32_t
cfg_t_param_wr_to_pch
: 6;
5439
uint32_t : 2;
5440
};
5441
5443
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING3_s
ALT_IO48_HMC_MMR_CALTIMING3_t
;
5444
#endif
/* __ASSEMBLY__ */
5445
5447
#define ALT_IO48_HMC_MMR_CALTIMING3_RESET 0x00000000
5448
5449
#define ALT_IO48_HMC_MMR_CALTIMING3_OFST 0x88
5450
5474
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB 0
5475
5476
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB 5
5477
5478
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH 6
5479
5480
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK 0x0000003f
5481
5482
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK 0xffffffc0
5483
5484
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET 0x0
5485
5486
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value) (((value) & 0x0000003f) >> 0)
5487
5488
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value) (((value) << 0) & 0x0000003f)
5489
5499
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB 6
5500
5501
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB 11
5502
5503
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH 6
5504
5505
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK 0x00000fc0
5506
5507
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK 0xfffff03f
5508
5509
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET 0x0
5510
5511
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value) (((value) & 0x00000fc0) >> 6)
5512
5513
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value) (((value) << 6) & 0x00000fc0)
5514
5524
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB 12
5525
5526
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB 17
5527
5528
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH 6
5529
5530
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK 0x0003f000
5531
5532
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK 0xfffc0fff
5533
5534
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET 0x0
5535
5536
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value) (((value) & 0x0003f000) >> 12)
5537
5538
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value) (((value) << 12) & 0x0003f000)
5539
5549
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB 18
5550
5551
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB 25
5552
5553
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH 8
5554
5555
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK 0x03fc0000
5556
5557
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK 0xfc03ffff
5558
5559
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET 0x0
5560
5561
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value) (((value) & 0x03fc0000) >> 18)
5562
5563
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value) (((value) << 18) & 0x03fc0000)
5564
5574
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB 26
5575
5576
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB 31
5577
5578
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH 6
5579
5580
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK 0xfc000000
5581
5582
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK 0x03ffffff
5583
5584
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET 0x0
5585
5586
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value) (((value) & 0xfc000000) >> 26)
5587
5588
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value) (((value) << 26) & 0xfc000000)
5589
5590
#ifndef __ASSEMBLY__
5591
5601
struct
ALT_IO48_HMC_MMR_CALTIMING4_s
5602
{
5603
uint32_t
cfg_t_param_wr_ap_to_valid
: 6;
5604
uint32_t
cfg_t_param_pch_to_valid
: 6;
5605
uint32_t
cfg_t_param_pch_all_to_valid
: 6;
5606
uint32_t
cfg_t_param_arf_to_valid
: 8;
5607
uint32_t
cfg_t_param_pdn_to_valid
: 6;
5608
};
5609
5611
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING4_s
ALT_IO48_HMC_MMR_CALTIMING4_t
;
5612
#endif
/* __ASSEMBLY__ */
5613
5615
#define ALT_IO48_HMC_MMR_CALTIMING4_RESET 0x00000000
5616
5617
#define ALT_IO48_HMC_MMR_CALTIMING4_OFST 0x8c
5618
5640
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB 0
5641
5642
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB 9
5643
5644
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH 10
5645
5646
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK 0x000003ff
5647
5648
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK 0xfffffc00
5649
5650
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET 0x0
5651
5652
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value) (((value) & 0x000003ff) >> 0)
5653
5654
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value) (((value) << 0) & 0x000003ff)
5655
5665
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB 10
5666
5667
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB 19
5668
5669
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH 10
5670
5671
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK 0x000ffc00
5672
5673
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK 0xfff003ff
5674
5675
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET 0x0
5676
5677
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value) (((value) & 0x000ffc00) >> 10)
5678
5679
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value) (((value) << 10) & 0x000ffc00)
5680
5681
#ifndef __ASSEMBLY__
5682
5692
struct
ALT_IO48_HMC_MMR_CALTIMING5_s
5693
{
5694
uint32_t
cfg_t_param_srf_to_valid
: 10;
5695
uint32_t
cfg_t_param_srf_to_zq_cal
: 10;
5696
uint32_t : 12;
5697
};
5698
5700
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING5_s
ALT_IO48_HMC_MMR_CALTIMING5_t
;
5701
#endif
/* __ASSEMBLY__ */
5702
5704
#define ALT_IO48_HMC_MMR_CALTIMING5_RESET 0x00000000
5705
5706
#define ALT_IO48_HMC_MMR_CALTIMING5_OFST 0x90
5707
5729
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_LSB 0
5730
5731
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_MSB 12
5732
5733
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_WIDTH 13
5734
5735
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET_MSK 0x00001fff
5736
5737
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_CLR_MSK 0xffffe000
5738
5739
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_RESET 0x0
5740
5741
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_GET(value) (((value) & 0x00001fff) >> 0)
5742
5743
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_ARF_PERIOD_SET(value) (((value) << 0) & 0x00001fff)
5744
5754
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_LSB 13
5755
5756
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_MSB 28
5757
5758
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_WIDTH 16
5759
5760
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET_MSK 0x1fffe000
5761
5762
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_CLR_MSK 0xe0001fff
5763
5764
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_RESET 0x0
5765
5766
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_GET(value) (((value) & 0x1fffe000) >> 13)
5767
5768
#define ALT_IO48_HMC_MMR_CALTIMING6_CFG_T_PARAM_PDN_PERIOD_SET(value) (((value) << 13) & 0x1fffe000)
5769
5770
#ifndef __ASSEMBLY__
5771
5781
struct
ALT_IO48_HMC_MMR_CALTIMING6_s
5782
{
5783
uint32_t
cfg_t_param_arf_period
: 13;
5784
uint32_t
cfg_t_param_pdn_period
: 16;
5785
uint32_t : 3;
5786
};
5787
5789
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING6_s
ALT_IO48_HMC_MMR_CALTIMING6_t
;
5790
#endif
/* __ASSEMBLY__ */
5791
5793
#define ALT_IO48_HMC_MMR_CALTIMING6_RESET 0x00000000
5794
5795
#define ALT_IO48_HMC_MMR_CALTIMING6_OFST 0x94
5796
5820
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB 0
5821
5822
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB 8
5823
5824
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH 9
5825
5826
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK 0x000001ff
5827
5828
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK 0xfffffe00
5829
5830
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET 0x0
5831
5832
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value) (((value) & 0x000001ff) >> 0)
5833
5834
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value) (((value) << 0) & 0x000001ff)
5835
5845
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB 9
5846
5847
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB 15
5848
5849
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH 7
5850
5851
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK 0x0000fe00
5852
5853
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK 0xffff01ff
5854
5855
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET 0x0
5856
5857
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value) (((value) & 0x0000fe00) >> 9)
5858
5859
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value) (((value) << 9) & 0x0000fe00)
5860
5870
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB 16
5871
5872
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB 19
5873
5874
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH 4
5875
5876
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK 0x000f0000
5877
5878
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK 0xfff0ffff
5879
5880
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET 0x0
5881
5882
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value) (((value) & 0x000f0000) >> 16)
5883
5884
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value) (((value) << 16) & 0x000f0000)
5885
5895
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB 20
5896
5897
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB 29
5898
5899
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH 10
5900
5901
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK 0x3ff00000
5902
5903
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK 0xc00fffff
5904
5905
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET 0x0
5906
5907
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value) (((value) & 0x3ff00000) >> 20)
5908
5909
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value) (((value) << 20) & 0x3ff00000)
5910
5911
#ifndef __ASSEMBLY__
5912
5922
struct
ALT_IO48_HMC_MMR_CALTIMING7_s
5923
{
5924
uint32_t
cfg_t_param_zqcl_to_valid
: 9;
5925
uint32_t
cfg_t_param_zqcs_to_valid
: 7;
5926
uint32_t
cfg_t_param_mrs_to_valid
: 4;
5927
uint32_t
cfg_t_param_mps_to_valid
: 10;
5928
uint32_t : 2;
5929
};
5930
5932
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING7_s
ALT_IO48_HMC_MMR_CALTIMING7_t
;
5933
#endif
/* __ASSEMBLY__ */
5934
5936
#define ALT_IO48_HMC_MMR_CALTIMING7_RESET 0x00000000
5937
5938
#define ALT_IO48_HMC_MMR_CALTIMING7_OFST 0x98
5939
5965
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_LSB 0
5966
5967
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_MSB 3
5968
5969
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_WIDTH 4
5970
5971
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET_MSK 0x0000000f
5972
5973
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_CLR_MSK 0xfffffff0
5974
5975
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_RESET 0x0
5976
5977
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_GET(value) (((value) & 0x0000000f) >> 0)
5978
5979
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MRR_TO_VALID_SET(value) (((value) << 0) & 0x0000000f)
5980
5990
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_LSB 4
5991
5992
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_MSB 8
5993
5994
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_WIDTH 5
5995
5996
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET_MSK 0x000001f0
5997
5998
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_CLR_MSK 0xfffffe0f
5999
6000
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_RESET 0x0
6001
6002
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_GET(value) (((value) & 0x000001f0) >> 4)
6003
6004
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPR_TO_VALID_SET(value) (((value) << 4) & 0x000001f0)
6005
6016
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_LSB 9
6017
6018
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_MSB 12
6019
6020
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_WIDTH 4
6021
6022
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET_MSK 0x00001e00
6023
6024
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_CLR_MSK 0xffffe1ff
6025
6026
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_RESET 0x0
6027
6028
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_GET(value) (((value) & 0x00001e00) >> 9)
6029
6030
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CS_TO_CKE_SET(value) (((value) << 9) & 0x00001e00)
6031
6042
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_LSB 13
6043
6044
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_MSB 16
6045
6046
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_WIDTH 4
6047
6048
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET_MSK 0x0001e000
6049
6050
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_CLR_MSK 0xfffe1fff
6051
6052
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_RESET 0x0
6053
6054
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_GET(value) (((value) & 0x0001e000) >> 13)
6055
6056
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MPS_EXIT_CKE_TO_CS_SET(value) (((value) << 13) & 0x0001e000)
6057
6067
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_LSB 17
6068
6069
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_MSB 19
6070
6071
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_WIDTH 3
6072
6073
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET_MSK 0x000e0000
6074
6075
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_CLR_MSK 0xfff1ffff
6076
6077
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_RESET 0x0
6078
6079
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_GET(value) (((value) & 0x000e0000) >> 17)
6080
6081
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_RLD3_MULTIBANK_REF_DELAY_SET(value) (((value) << 17) & 0x000e0000)
6082
6092
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_LSB 20
6093
6094
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_MSB 27
6095
6096
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_WIDTH 8
6097
6098
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET_MSK 0x0ff00000
6099
6100
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_CLR_MSK 0xf00fffff
6101
6102
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_RESET 0x0
6103
6104
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_GET(value) (((value) & 0x0ff00000) >> 20)
6105
6106
#define ALT_IO48_HMC_MMR_CALTIMING8_CFG_T_PARAM_MMR_CMD_TO_VALID_SET(value) (((value) << 20) & 0x0ff00000)
6107
6108
#ifndef __ASSEMBLY__
6109
6119
struct
ALT_IO48_HMC_MMR_CALTIMING8_s
6120
{
6121
uint32_t
cfg_t_param_mrr_to_valid
: 4;
6122
uint32_t
cfg_t_param_mpr_to_valid
: 5;
6123
uint32_t
cfg_t_param_mps_exit_cs_to_cke
: 4;
6124
uint32_t
cfg_t_param_mps_exit_cke_to_cs
: 4;
6125
uint32_t
cfg_t_param_rld3_multibank_ref_delay
: 3;
6126
uint32_t
cfg_t_param_mmr_cmd_to_valid
: 8;
6127
uint32_t : 4;
6128
};
6129
6131
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING8_s
ALT_IO48_HMC_MMR_CALTIMING8_t
;
6132
#endif
/* __ASSEMBLY__ */
6133
6135
#define ALT_IO48_HMC_MMR_CALTIMING8_RESET 0x00000000
6136
6137
#define ALT_IO48_HMC_MMR_CALTIMING8_OFST 0x9c
6138
6159
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_LSB 0
6160
6161
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_MSB 7
6162
6163
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_WIDTH 8
6164
6165
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET_MSK 0x000000ff
6166
6167
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_CLR_MSK 0xffffff00
6168
6169
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_RESET 0x0
6170
6171
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6172
6173
#define ALT_IO48_HMC_MMR_CALTIMING9_CFG_T_PARAM_4_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6174
6175
#ifndef __ASSEMBLY__
6176
6186
struct
ALT_IO48_HMC_MMR_CALTIMING9_s
6187
{
6188
uint32_t
cfg_t_param_4_act_to_act
: 8;
6189
uint32_t : 24;
6190
};
6191
6193
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING9_s
ALT_IO48_HMC_MMR_CALTIMING9_t
;
6194
#endif
/* __ASSEMBLY__ */
6195
6197
#define ALT_IO48_HMC_MMR_CALTIMING9_RESET 0x00000000
6198
6199
#define ALT_IO48_HMC_MMR_CALTIMING9_OFST 0xa0
6200
6221
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_LSB 0
6222
6223
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_MSB 7
6224
6225
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_WIDTH 8
6226
6227
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET_MSK 0x000000ff
6228
6229
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_CLR_MSK 0xffffff00
6230
6231
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_RESET 0x0
6232
6233
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_GET(value) (((value) & 0x000000ff) >> 0)
6234
6235
#define ALT_IO48_HMC_MMR_CALTIMING10_CFG_T_PARAM_16_ACT_TO_ACT_SET(value) (((value) << 0) & 0x000000ff)
6236
6237
#ifndef __ASSEMBLY__
6238
6248
struct
ALT_IO48_HMC_MMR_CALTIMING10_s
6249
{
6250
uint32_t
cfg_t_param_16_act_to_act
: 8;
6251
uint32_t : 24;
6252
};
6253
6255
typedef
volatile
struct
ALT_IO48_HMC_MMR_CALTIMING10_s
ALT_IO48_HMC_MMR_CALTIMING10_t
;
6256
#endif
/* __ASSEMBLY__ */
6257
6259
#define ALT_IO48_HMC_MMR_CALTIMING10_RESET 0x00000000
6260
6261
#define ALT_IO48_HMC_MMR_CALTIMING10_OFST 0xa4
6262
6288
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB 0
6289
6290
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB 4
6291
6292
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH 5
6293
6294
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK 0x0000001f
6295
6296
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK 0xffffffe0
6297
6298
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET 0x0
6299
6300
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value) (((value) & 0x0000001f) >> 0)
6301
6302
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value) (((value) << 0) & 0x0000001f)
6303
6313
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB 5
6314
6315
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB 9
6316
6317
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH 5
6318
6319
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK 0x000003e0
6320
6321
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK 0xfffffc1f
6322
6323
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET 0x0
6324
6325
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value) (((value) & 0x000003e0) >> 5)
6326
6327
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value) (((value) << 5) & 0x000003e0)
6328
6338
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB 10
6339
6340
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB 13
6341
6342
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH 4
6343
6344
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK 0x00003c00
6345
6346
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK 0xffffc3ff
6347
6348
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET 0x0
6349
6350
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value) (((value) & 0x00003c00) >> 10)
6351
6352
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value) (((value) << 10) & 0x00003c00)
6353
6364
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB 14
6365
6366
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB 15
6367
6368
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH 2
6369
6370
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK 0x0000c000
6371
6372
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK 0xffff3fff
6373
6374
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET 0x0
6375
6376
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value) (((value) & 0x0000c000) >> 14)
6377
6378
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value) (((value) << 14) & 0x0000c000)
6379
6390
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB 16
6391
6392
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB 18
6393
6394
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH 3
6395
6396
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK 0x00070000
6397
6398
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK 0xfff8ffff
6399
6400
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET 0x0
6401
6402
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value) (((value) & 0x00070000) >> 16)
6403
6404
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value) (((value) << 16) & 0x00070000)
6405
6406
#ifndef __ASSEMBLY__
6407
6417
struct
ALT_IO48_HMC_MMR_DRAMADDRW_s
6418
{
6419
uint32_t
cfg_col_addr_width
: 5;
6420
uint32_t
cfg_row_addr_width
: 5;
6421
uint32_t
cfg_bank_addr_width
: 4;
6422
uint32_t
cfg_bank_group_addr_width
: 2;
6423
uint32_t
cfg_cs_addr_width
: 3;
6424
uint32_t : 13;
6425
};
6426
6428
typedef
volatile
struct
ALT_IO48_HMC_MMR_DRAMADDRW_s
ALT_IO48_HMC_MMR_DRAMADDRW_t
;
6429
#endif
/* __ASSEMBLY__ */
6430
6432
#define ALT_IO48_HMC_MMR_DRAMADDRW_RESET 0x00000000
6433
6434
#define ALT_IO48_HMC_MMR_DRAMADDRW_OFST 0xa8
6435
6456
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_LSB 0
6457
6458
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_MSB 0
6459
6460
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_WIDTH 1
6461
6462
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET_MSK 0x00000001
6463
6464
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_CLR_MSK 0xfffffffe
6465
6466
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_RESET 0x0
6467
6468
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_GET(value) (((value) & 0x00000001) >> 0)
6469
6470
#define ALT_IO48_HMC_MMR_SIDEBAND0_MR_CMD_TRIGGER_SET(value) (((value) << 0) & 0x00000001)
6471
6472
#ifndef __ASSEMBLY__
6473
6483
struct
ALT_IO48_HMC_MMR_SIDEBAND0_s
6484
{
6485
uint32_t
mr_cmd_trigger
: 1;
6486
uint32_t : 31;
6487
};
6488
6490
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND0_s
ALT_IO48_HMC_MMR_SIDEBAND0_t
;
6491
#endif
/* __ASSEMBLY__ */
6492
6494
#define ALT_IO48_HMC_MMR_SIDEBAND0_RESET 0x00000000
6495
6496
#define ALT_IO48_HMC_MMR_SIDEBAND0_OFST 0xac
6497
6519
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_LSB 0
6520
6521
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_MSB 3
6522
6523
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_WIDTH 4
6524
6525
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET_MSK 0x0000000f
6526
6527
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_CLR_MSK 0xfffffff0
6528
6529
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_RESET 0x0
6530
6531
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6532
6533
#define ALT_IO48_HMC_MMR_SIDEBAND1_MMR_REFRESH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6534
6535
#ifndef __ASSEMBLY__
6536
6546
struct
ALT_IO48_HMC_MMR_SIDEBAND1_s
6547
{
6548
uint32_t
mmr_refresh_req
: 4;
6549
uint32_t : 28;
6550
};
6551
6553
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND1_s
ALT_IO48_HMC_MMR_SIDEBAND1_t
;
6554
#endif
/* __ASSEMBLY__ */
6555
6557
#define ALT_IO48_HMC_MMR_SIDEBAND1_RESET 0x00000000
6558
6559
#define ALT_IO48_HMC_MMR_SIDEBAND1_OFST 0xb0
6560
6581
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_LSB 0
6582
6583
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_MSB 0
6584
6585
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_WIDTH 1
6586
6587
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET_MSK 0x00000001
6588
6589
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_CLR_MSK 0xfffffffe
6590
6591
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_RESET 0x0
6592
6593
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_GET(value) (((value) & 0x00000001) >> 0)
6594
6595
#define ALT_IO48_HMC_MMR_SIDEBAND2_MMR_ZQCAL_LONG_REQ_SET(value) (((value) << 0) & 0x00000001)
6596
6597
#ifndef __ASSEMBLY__
6598
6608
struct
ALT_IO48_HMC_MMR_SIDEBAND2_s
6609
{
6610
uint32_t
mmr_zqcal_long_req
: 1;
6611
uint32_t : 31;
6612
};
6613
6615
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND2_s
ALT_IO48_HMC_MMR_SIDEBAND2_t
;
6616
#endif
/* __ASSEMBLY__ */
6617
6619
#define ALT_IO48_HMC_MMR_SIDEBAND2_RESET 0x00000000
6620
6621
#define ALT_IO48_HMC_MMR_SIDEBAND2_OFST 0xb4
6622
6643
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_LSB 0
6644
6645
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_MSB 0
6646
6647
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_WIDTH 1
6648
6649
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET_MSK 0x00000001
6650
6651
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_CLR_MSK 0xfffffffe
6652
6653
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_RESET 0x0
6654
6655
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_GET(value) (((value) & 0x00000001) >> 0)
6656
6657
#define ALT_IO48_HMC_MMR_SIDEBAND3_MMR_ZQCAL_SHORT_REQ_SET(value) (((value) << 0) & 0x00000001)
6658
6659
#ifndef __ASSEMBLY__
6660
6670
struct
ALT_IO48_HMC_MMR_SIDEBAND3_s
6671
{
6672
uint32_t
mmr_zqcal_short_req
: 1;
6673
uint32_t : 31;
6674
};
6675
6677
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND3_s
ALT_IO48_HMC_MMR_SIDEBAND3_t
;
6678
#endif
/* __ASSEMBLY__ */
6679
6681
#define ALT_IO48_HMC_MMR_SIDEBAND3_RESET 0x00000000
6682
6683
#define ALT_IO48_HMC_MMR_SIDEBAND3_OFST 0xb8
6684
6706
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_LSB 0
6707
6708
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_MSB 3
6709
6710
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_WIDTH 4
6711
6712
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET_MSK 0x0000000f
6713
6714
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_CLR_MSK 0xfffffff0
6715
6716
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_RESET 0x0
6717
6718
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_GET(value) (((value) & 0x0000000f) >> 0)
6719
6720
#define ALT_IO48_HMC_MMR_SIDEBAND4_MMR_SELF_RFSH_REQ_SET(value) (((value) << 0) & 0x0000000f)
6721
6722
#ifndef __ASSEMBLY__
6723
6733
struct
ALT_IO48_HMC_MMR_SIDEBAND4_s
6734
{
6735
uint32_t
mmr_self_rfsh_req
: 4;
6736
uint32_t : 28;
6737
};
6738
6740
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND4_s
ALT_IO48_HMC_MMR_SIDEBAND4_t
;
6741
#endif
/* __ASSEMBLY__ */
6742
6744
#define ALT_IO48_HMC_MMR_SIDEBAND4_RESET 0x00000000
6745
6746
#define ALT_IO48_HMC_MMR_SIDEBAND4_OFST 0xbc
6747
6769
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_LSB 0
6770
6771
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_MSB 0
6772
6773
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_WIDTH 1
6774
6775
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET_MSK 0x00000001
6776
6777
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_CLR_MSK 0xfffffffe
6778
6779
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_RESET 0x0
6780
6781
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_GET(value) (((value) & 0x00000001) >> 0)
6782
6783
#define ALT_IO48_HMC_MMR_SIDEBAND5_MMR_DPD_MPS_REQ_SET(value) (((value) << 0) & 0x00000001)
6784
6785
#ifndef __ASSEMBLY__
6786
6796
struct
ALT_IO48_HMC_MMR_SIDEBAND5_s
6797
{
6798
uint32_t
mmr_dpd_mps_req
: 1;
6799
uint32_t : 31;
6800
};
6801
6803
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND5_s
ALT_IO48_HMC_MMR_SIDEBAND5_t
;
6804
#endif
/* __ASSEMBLY__ */
6805
6807
#define ALT_IO48_HMC_MMR_SIDEBAND5_RESET 0x00000000
6808
6809
#define ALT_IO48_HMC_MMR_SIDEBAND5_OFST 0xc0
6810
6831
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_LSB 0
6832
6833
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_MSB 0
6834
6835
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_WIDTH 1
6836
6837
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET_MSK 0x00000001
6838
6839
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_CLR_MSK 0xfffffffe
6840
6841
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_RESET 0x0
6842
6843
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_GET(value) (((value) & 0x00000001) >> 0)
6844
6845
#define ALT_IO48_HMC_MMR_SIDEBAND6_MR_CMD_ACK_SET(value) (((value) << 0) & 0x00000001)
6846
6847
#ifndef __ASSEMBLY__
6848
6858
struct
ALT_IO48_HMC_MMR_SIDEBAND6_s
6859
{
6860
uint32_t
mr_cmd_ack
: 1;
6861
uint32_t : 31;
6862
};
6863
6865
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND6_s
ALT_IO48_HMC_MMR_SIDEBAND6_t
;
6866
#endif
/* __ASSEMBLY__ */
6867
6869
#define ALT_IO48_HMC_MMR_SIDEBAND6_RESET 0x00000000
6870
6871
#define ALT_IO48_HMC_MMR_SIDEBAND6_OFST 0xc4
6872
6893
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_LSB 0
6894
6895
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_MSB 0
6896
6897
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_WIDTH 1
6898
6899
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET_MSK 0x00000001
6900
6901
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_CLR_MSK 0xfffffffe
6902
6903
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_RESET 0x0
6904
6905
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_GET(value) (((value) & 0x00000001) >> 0)
6906
6907
#define ALT_IO48_HMC_MMR_SIDEBAND7_MMR_REFRESH_ACK_SET(value) (((value) << 0) & 0x00000001)
6908
6909
#ifndef __ASSEMBLY__
6910
6920
struct
ALT_IO48_HMC_MMR_SIDEBAND7_s
6921
{
6922
uint32_t
mmr_refresh_ack
: 1;
6923
uint32_t : 31;
6924
};
6925
6927
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND7_s
ALT_IO48_HMC_MMR_SIDEBAND7_t
;
6928
#endif
/* __ASSEMBLY__ */
6929
6931
#define ALT_IO48_HMC_MMR_SIDEBAND7_RESET 0x00000000
6932
6933
#define ALT_IO48_HMC_MMR_SIDEBAND7_OFST 0xc8
6934
6955
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_LSB 0
6956
6957
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_MSB 0
6958
6959
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_WIDTH 1
6960
6961
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET_MSK 0x00000001
6962
6963
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_CLR_MSK 0xfffffffe
6964
6965
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_RESET 0x0
6966
6967
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_GET(value) (((value) & 0x00000001) >> 0)
6968
6969
#define ALT_IO48_HMC_MMR_SIDEBAND8_MMR_ZQCAL_ACK_SET(value) (((value) << 0) & 0x00000001)
6970
6971
#ifndef __ASSEMBLY__
6972
6982
struct
ALT_IO48_HMC_MMR_SIDEBAND8_s
6983
{
6984
uint32_t
mmr_zqcal_ack
: 1;
6985
uint32_t : 31;
6986
};
6987
6989
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND8_s
ALT_IO48_HMC_MMR_SIDEBAND8_t
;
6990
#endif
/* __ASSEMBLY__ */
6991
6993
#define ALT_IO48_HMC_MMR_SIDEBAND8_RESET 0x00000000
6994
6995
#define ALT_IO48_HMC_MMR_SIDEBAND8_OFST 0xcc
6996
7017
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_LSB 0
7018
7019
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_MSB 0
7020
7021
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_WIDTH 1
7022
7023
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET_MSK 0x00000001
7024
7025
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_CLR_MSK 0xfffffffe
7026
7027
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_RESET 0x0
7028
7029
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_GET(value) (((value) & 0x00000001) >> 0)
7030
7031
#define ALT_IO48_HMC_MMR_SIDEBAND9_MMR_SELF_RFSH_ACK_SET(value) (((value) << 0) & 0x00000001)
7032
7033
#ifndef __ASSEMBLY__
7034
7044
struct
ALT_IO48_HMC_MMR_SIDEBAND9_s
7045
{
7046
uint32_t
mmr_self_rfsh_ack
: 1;
7047
uint32_t : 31;
7048
};
7049
7051
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND9_s
ALT_IO48_HMC_MMR_SIDEBAND9_t
;
7052
#endif
/* __ASSEMBLY__ */
7053
7055
#define ALT_IO48_HMC_MMR_SIDEBAND9_RESET 0x00000000
7056
7057
#define ALT_IO48_HMC_MMR_SIDEBAND9_OFST 0xd0
7058
7079
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_LSB 0
7080
7081
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_MSB 0
7082
7083
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_WIDTH 1
7084
7085
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET_MSK 0x00000001
7086
7087
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_CLR_MSK 0xfffffffe
7088
7089
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_RESET 0x0
7090
7091
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_GET(value) (((value) & 0x00000001) >> 0)
7092
7093
#define ALT_IO48_HMC_MMR_SIDEBAND10_MMR_DPD_MPS_ACK_SET(value) (((value) << 0) & 0x00000001)
7094
7095
#ifndef __ASSEMBLY__
7096
7106
struct
ALT_IO48_HMC_MMR_SIDEBAND10_s
7107
{
7108
uint32_t
mmr_dpd_mps_ack
: 1;
7109
uint32_t : 31;
7110
};
7111
7113
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND10_s
ALT_IO48_HMC_MMR_SIDEBAND10_t
;
7114
#endif
/* __ASSEMBLY__ */
7115
7117
#define ALT_IO48_HMC_MMR_SIDEBAND10_RESET 0x00000000
7118
7119
#define ALT_IO48_HMC_MMR_SIDEBAND10_OFST 0xd4
7120
7141
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_LSB 0
7142
7143
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_MSB 0
7144
7145
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_WIDTH 1
7146
7147
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET_MSK 0x00000001
7148
7149
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_CLR_MSK 0xfffffffe
7150
7151
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_RESET 0x0
7152
7153
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_GET(value) (((value) & 0x00000001) >> 0)
7154
7155
#define ALT_IO48_HMC_MMR_SIDEBAND11_MMR_AUTO_PD_ACK_SET(value) (((value) << 0) & 0x00000001)
7156
7157
#ifndef __ASSEMBLY__
7158
7168
struct
ALT_IO48_HMC_MMR_SIDEBAND11_s
7169
{
7170
uint32_t
mmr_auto_pd_ack
: 1;
7171
uint32_t : 31;
7172
};
7173
7175
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND11_s
ALT_IO48_HMC_MMR_SIDEBAND11_t
;
7176
#endif
/* __ASSEMBLY__ */
7177
7179
#define ALT_IO48_HMC_MMR_SIDEBAND11_RESET 0x00000000
7180
7181
#define ALT_IO48_HMC_MMR_SIDEBAND11_OFST 0xd8
7182
7204
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_LSB 0
7205
7206
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_MSB 2
7207
7208
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_WIDTH 3
7209
7210
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET_MSK 0x00000007
7211
7212
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_CLR_MSK 0xfffffff8
7213
7214
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_RESET 0x0
7215
7216
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_GET(value) (((value) & 0x00000007) >> 0)
7217
7218
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_TYPE_SET(value) (((value) << 0) & 0x00000007)
7219
7229
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_LSB 3
7230
7231
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_MSB 6
7232
7233
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_WIDTH 4
7234
7235
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET_MSK 0x00000078
7236
7237
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_CLR_MSK 0xffffff87
7238
7239
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_RESET 0x0
7240
7241
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_GET(value) (((value) & 0x00000078) >> 3)
7242
7243
#define ALT_IO48_HMC_MMR_SIDEBAND12_MR_CMD_RANK_SET(value) (((value) << 3) & 0x00000078)
7244
7245
#ifndef __ASSEMBLY__
7246
7256
struct
ALT_IO48_HMC_MMR_SIDEBAND12_s
7257
{
7258
uint32_t
mr_cmd_type
: 3;
7259
uint32_t
mr_cmd_rank
: 4;
7260
uint32_t : 25;
7261
};
7262
7264
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND12_s
ALT_IO48_HMC_MMR_SIDEBAND12_t
;
7265
#endif
/* __ASSEMBLY__ */
7266
7268
#define ALT_IO48_HMC_MMR_SIDEBAND12_RESET 0x00000000
7269
7270
#define ALT_IO48_HMC_MMR_SIDEBAND12_OFST 0xdc
7271
7296
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_LSB 0
7297
7298
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_MSB 31
7299
7300
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_WIDTH 32
7301
7302
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET_MSK 0xffffffff
7303
7304
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK 0x00000000
7305
7306
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_RESET 0x0
7307
7308
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_GET(value) (((value) & 0xffffffff) >> 0)
7309
7310
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET(value) (((value) << 0) & 0xffffffff)
7311
7312
#ifndef __ASSEMBLY__
7313
7323
struct
ALT_IO48_HMC_MMR_SIDEBAND13_s
7324
{
7325
uint32_t
mr_cmd_opcode
: 32;
7326
};
7327
7329
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND13_s
ALT_IO48_HMC_MMR_SIDEBAND13_t
;
7330
#endif
/* __ASSEMBLY__ */
7331
7333
#define ALT_IO48_HMC_MMR_SIDEBAND13_RESET 0x00000000
7334
7335
#define ALT_IO48_HMC_MMR_SIDEBAND13_OFST 0xe0
7336
7358
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_LSB 0
7359
7360
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_MSB 15
7361
7362
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_WIDTH 16
7363
7364
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET_MSK 0x0000ffff
7365
7366
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_CLR_MSK 0xffff0000
7367
7368
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_RESET 0x0
7369
7370
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_GET(value) (((value) & 0x0000ffff) >> 0)
7371
7372
#define ALT_IO48_HMC_MMR_SIDEBAND14_MMR_REFRESH_BANK_SET(value) (((value) << 0) & 0x0000ffff)
7373
7374
#ifndef __ASSEMBLY__
7375
7385
struct
ALT_IO48_HMC_MMR_SIDEBAND14_s
7386
{
7387
uint32_t
mmr_refresh_bank
: 16;
7388
uint32_t : 16;
7389
};
7390
7392
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND14_s
ALT_IO48_HMC_MMR_SIDEBAND14_t
;
7393
#endif
/* __ASSEMBLY__ */
7394
7396
#define ALT_IO48_HMC_MMR_SIDEBAND14_RESET 0x00000000
7397
7398
#define ALT_IO48_HMC_MMR_SIDEBAND14_OFST 0xe4
7399
7420
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_LSB 0
7421
7422
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_MSB 3
7423
7424
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_WIDTH 4
7425
7426
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET_MSK 0x0000000f
7427
7428
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_CLR_MSK 0xfffffff0
7429
7430
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_RESET 0x0
7431
7432
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_GET(value) (((value) & 0x0000000f) >> 0)
7433
7434
#define ALT_IO48_HMC_MMR_SIDEBAND15_MMR_STALL_RANK_SET(value) (((value) << 0) & 0x0000000f)
7435
7436
#ifndef __ASSEMBLY__
7437
7447
struct
ALT_IO48_HMC_MMR_SIDEBAND15_s
7448
{
7449
uint32_t
mmr_stall_rank
: 4;
7450
uint32_t : 28;
7451
};
7452
7454
typedef
volatile
struct
ALT_IO48_HMC_MMR_SIDEBAND15_s
ALT_IO48_HMC_MMR_SIDEBAND15_t
;
7455
#endif
/* __ASSEMBLY__ */
7456
7458
#define ALT_IO48_HMC_MMR_SIDEBAND15_RESET 0x00000000
7459
7460
#define ALT_IO48_HMC_MMR_SIDEBAND15_OFST 0xe8
7461
7483
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_LSB 0
7484
7485
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_MSB 0
7486
7487
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_WIDTH 1
7488
7489
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET_MSK 0x00000001
7490
7491
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_CLR_MSK 0xfffffffe
7492
7493
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_RESET 0x0
7494
7495
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_GET(value) (((value) & 0x00000001) >> 0)
7496
7497
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_SUCCESS_SET(value) (((value) << 0) & 0x00000001)
7498
7508
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_LSB 1
7509
7510
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_MSB 1
7511
7512
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_WIDTH 1
7513
7514
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET_MSK 0x00000002
7515
7516
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_CLR_MSK 0xfffffffd
7517
7518
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_RESET 0x0
7519
7520
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_GET(value) (((value) & 0x00000002) >> 1)
7521
7522
#define ALT_IO48_HMC_MMR_DRAMSTS_PHY_CAL_FAIL_SET(value) (((value) << 1) & 0x00000002)
7523
7524
#ifndef __ASSEMBLY__
7525
7535
struct
ALT_IO48_HMC_MMR_DRAMSTS_s
7536
{
7537
uint32_t
phy_cal_success
: 1;
7538
uint32_t
phy_cal_fail
: 1;
7539
uint32_t : 30;
7540
};
7541
7543
typedef
volatile
struct
ALT_IO48_HMC_MMR_DRAMSTS_s
ALT_IO48_HMC_MMR_DRAMSTS_t
;
7544
#endif
/* __ASSEMBLY__ */
7545
7547
#define ALT_IO48_HMC_MMR_DRAMSTS_RESET 0x00000000
7548
7549
#define ALT_IO48_HMC_MMR_DRAMSTS_OFST 0xec
7550
7571
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_LSB 0
7572
7573
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_MSB 0
7574
7575
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_WIDTH 1
7576
7577
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET_MSK 0x00000001
7578
7579
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_CLR_MSK 0xfffffffe
7580
7581
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_RESET 0x0
7582
7583
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_GET(value) (((value) & 0x00000001) >> 0)
7584
7585
#define ALT_IO48_HMC_MMR_DBGDONE_DBG_DONE_SET(value) (((value) << 0) & 0x00000001)
7586
7587
#ifndef __ASSEMBLY__
7588
7598
struct
ALT_IO48_HMC_MMR_DBGDONE_s
7599
{
7600
uint32_t
dbg_done
: 1;
7601
uint32_t : 31;
7602
};
7603
7605
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGDONE_s
ALT_IO48_HMC_MMR_DBGDONE_t
;
7606
#endif
/* __ASSEMBLY__ */
7607
7609
#define ALT_IO48_HMC_MMR_DBGDONE_RESET 0x00000000
7610
7611
#define ALT_IO48_HMC_MMR_DBGDONE_OFST 0xf0
7612
7632
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_LSB 0
7633
7634
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_MSB 31
7635
7636
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_WIDTH 32
7637
7638
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET_MSK 0xffffffff
7639
7640
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_CLR_MSK 0x00000000
7641
7642
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_RESET 0x0
7643
7644
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_GET(value) (((value) & 0xffffffff) >> 0)
7645
7646
#define ALT_IO48_HMC_MMR_DBGSIGNALS_DBG_SIGNALS_OUT_SET(value) (((value) << 0) & 0xffffffff)
7647
7648
#ifndef __ASSEMBLY__
7649
7659
struct
ALT_IO48_HMC_MMR_DBGSIGNALS_s
7660
{
7661
uint32_t
dbg_signals_out
: 32;
7662
};
7663
7665
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGSIGNALS_s
ALT_IO48_HMC_MMR_DBGSIGNALS_t
;
7666
#endif
/* __ASSEMBLY__ */
7667
7669
#define ALT_IO48_HMC_MMR_DBGSIGNALS_RESET 0x00000000
7670
7671
#define ALT_IO48_HMC_MMR_DBGSIGNALS_OFST 0xf4
7672
7695
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_LSB 0
7696
7697
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_MSB 0
7698
7699
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_WIDTH 1
7700
7701
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET_MSK 0x00000001
7702
7703
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_CLR_MSK 0xfffffffe
7704
7705
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_RESET 0x0
7706
7707
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_GET(value) (((value) & 0x00000001) >> 0)
7708
7709
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET(value) (((value) << 0) & 0x00000001)
7710
7721
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_LSB 1
7722
7723
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_MSB 1
7724
7725
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_WIDTH 1
7726
7727
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET_MSK 0x00000002
7728
7729
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_CLR_MSK 0xfffffffd
7730
7731
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_RESET 0x0
7732
7733
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_GET(value) (((value) & 0x00000002) >> 1)
7734
7735
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET(value) (((value) << 1) & 0x00000002)
7736
7737
#ifndef __ASSEMBLY__
7738
7748
struct
ALT_IO48_HMC_MMR_DBGRST_s
7749
{
7750
uint32_t
counter_zero_reset
: 1;
7751
uint32_t
counter_one_reset
: 1;
7752
uint32_t : 30;
7753
};
7754
7756
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGRST_s
ALT_IO48_HMC_MMR_DBGRST_t
;
7757
#endif
/* __ASSEMBLY__ */
7758
7760
#define ALT_IO48_HMC_MMR_DBGRST_RESET 0x00000000
7761
7762
#define ALT_IO48_HMC_MMR_DBGRST_OFST 0xf8
7763
7784
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_LSB 0
7785
7786
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_MSB 15
7787
7788
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_WIDTH 16
7789
7790
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET_MSK 0x0000ffff
7791
7792
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_CLR_MSK 0xffff0000
7793
7794
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_RESET 0x0
7795
7796
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_GET(value) (((value) & 0x0000ffff) >> 0)
7797
7798
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET(value) (((value) << 0) & 0x0000ffff)
7799
7809
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_LSB 16
7810
7811
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_MSB 31
7812
7813
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_WIDTH 16
7814
7815
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET_MSK 0xffff0000
7816
7817
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_CLR_MSK 0x0000ffff
7818
7819
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_RESET 0x0
7820
7821
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_GET(value) (((value) & 0xffff0000) >> 16)
7822
7823
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET(value) (((value) << 16) & 0xffff0000)
7824
7825
#ifndef __ASSEMBLY__
7826
7836
struct
ALT_IO48_HMC_MMR_DBGMATCH_s
7837
{
7838
uint32_t
counter_zero
: 16;
7839
uint32_t
counter_one
: 16;
7840
};
7841
7843
typedef
volatile
struct
ALT_IO48_HMC_MMR_DBGMATCH_s
ALT_IO48_HMC_MMR_DBGMATCH_t
;
7844
#endif
/* __ASSEMBLY__ */
7845
7847
#define ALT_IO48_HMC_MMR_DBGMATCH_RESET 0x00000000
7848
7849
#define ALT_IO48_HMC_MMR_DBGMATCH_OFST 0xfc
7850
7872
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_LSB 0
7873
7874
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_MSB 31
7875
7876
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_WIDTH 32
7877
7878
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET_MSK 0xffffffff
7879
7880
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_CLR_MSK 0x00000000
7881
7882
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_RESET 0x0
7883
7884
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7885
7886
#define ALT_IO48_HMC_MMR_CNTR0MSK_CNTR_ZERO_MSK_SET(value) (((value) << 0) & 0xffffffff)
7887
7888
#ifndef __ASSEMBLY__
7889
7899
struct
ALT_IO48_HMC_MMR_CNTR0MSK_s
7900
{
7901
uint32_t
counter_zero_mask
: 32;
7902
};
7903
7905
typedef
volatile
struct
ALT_IO48_HMC_MMR_CNTR0MSK_s
ALT_IO48_HMC_MMR_CNTR0MSK_t
;
7906
#endif
/* __ASSEMBLY__ */
7907
7909
#define ALT_IO48_HMC_MMR_CNTR0MSK_RESET 0x00000000
7910
7911
#define ALT_IO48_HMC_MMR_CNTR0MSK_OFST 0x100
7912
7934
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_LSB 0
7935
7936
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_MSB 31
7937
7938
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_WIDTH 32
7939
7940
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET_MSK 0xffffffff
7941
7942
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_CLR_MSK 0x00000000
7943
7944
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_RESET 0x0
7945
7946
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_GET(value) (((value) & 0xffffffff) >> 0)
7947
7948
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET(value) (((value) << 0) & 0xffffffff)
7949
7950
#ifndef __ASSEMBLY__
7951
7961
struct
ALT_IO48_HMC_MMR_CNTR1MSK_s
7962
{
7963
uint32_t
counter_one_mask
: 32;
7964
};
7965
7967
typedef
volatile
struct
ALT_IO48_HMC_MMR_CNTR1MSK_s
ALT_IO48_HMC_MMR_CNTR1MSK_t
;
7968
#endif
/* __ASSEMBLY__ */
7969
7971
#define ALT_IO48_HMC_MMR_CNTR1MSK_RESET 0x00000000
7972
7973
#define ALT_IO48_HMC_MMR_CNTR1MSK_OFST 0x104
7974
7995
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_LSB 0
7996
7997
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_MSB 31
7998
7999
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_WIDTH 32
8000
8001
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET_MSK 0xffffffff
8002
8003
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_CLR_MSK 0x00000000
8004
8005
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_RESET 0x0
8006
8007
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8008
8009
#define ALT_IO48_HMC_MMR_CNTR0MATCH_CNTR_ZERO_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8010
8011
#ifndef __ASSEMBLY__
8012
8022
struct
ALT_IO48_HMC_MMR_CNTR0MATCH_s
8023
{
8024
uint32_t
counter_zero_match
: 32;
8025
};
8026
8028
typedef
volatile
struct
ALT_IO48_HMC_MMR_CNTR0MATCH_s
ALT_IO48_HMC_MMR_CNTR0MATCH_t
;
8029
#endif
/* __ASSEMBLY__ */
8030
8032
#define ALT_IO48_HMC_MMR_CNTR0MATCH_RESET 0x00000000
8033
8034
#define ALT_IO48_HMC_MMR_CNTR0MATCH_OFST 0x108
8035
8056
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_LSB 0
8057
8058
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_MSB 31
8059
8060
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_WIDTH 32
8061
8062
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET_MSK 0xffffffff
8063
8064
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_CLR_MSK 0x00000000
8065
8066
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_RESET 0x0
8067
8068
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_GET(value) (((value) & 0xffffffff) >> 0)
8069
8070
#define ALT_IO48_HMC_MMR_CNTR1MATCH_CNTR_ONE_MATCH_SET(value) (((value) << 0) & 0xffffffff)
8071
8072
#ifndef __ASSEMBLY__
8073
8083
struct
ALT_IO48_HMC_MMR_CNTR1MATCH_s
8084
{
8085
uint32_t
counter_one_match
: 32;
8086
};
8087
8089
typedef
volatile
struct
ALT_IO48_HMC_MMR_CNTR1MATCH_s
ALT_IO48_HMC_MMR_CNTR1MATCH_t
;
8090
#endif
/* __ASSEMBLY__ */
8091
8093
#define ALT_IO48_HMC_MMR_CNTR1MATCH_RESET 0x00000000
8094
8095
#define ALT_IO48_HMC_MMR_CNTR1MATCH_OFST 0x10c
8096
8117
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_LSB 0
8118
8119
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_MSB 15
8120
8121
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_WIDTH 16
8122
8123
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET_MSK 0x0000ffff
8124
8125
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_CLR_MSK 0xffff0000
8126
8127
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_RESET 0x0
8128
8129
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_GET(value) (((value) & 0x0000ffff) >> 0)
8130
8131
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_NIOS_RESERVE0_SET(value) (((value) << 0) & 0x0000ffff)
8132
8133
#ifndef __ASSEMBLY__
8134
8144
struct
ALT_IO48_HMC_MMR_NIOSRESERVE0_s
8145
{
8146
uint32_t
nios_reserve0
: 16;
8147
uint32_t : 16;
8148
};
8149
8151
typedef
volatile
struct
ALT_IO48_HMC_MMR_NIOSRESERVE0_s
ALT_IO48_HMC_MMR_NIOSRESERVE0_t
;
8152
#endif
/* __ASSEMBLY__ */
8153
8155
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_RESET 0x00000000
8156
8157
#define ALT_IO48_HMC_MMR_NIOSRESERVE0_OFST 0x110
8158
8179
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_LSB 0
8180
8181
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_MSB 15
8182
8183
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_WIDTH 16
8184
8185
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET_MSK 0x0000ffff
8186
8187
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_CLR_MSK 0xffff0000
8188
8189
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_RESET 0x0
8190
8191
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_GET(value) (((value) & 0x0000ffff) >> 0)
8192
8193
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_NIOS_RESERVE1_SET(value) (((value) << 0) & 0x0000ffff)
8194
8195
#ifndef __ASSEMBLY__
8196
8206
struct
ALT_IO48_HMC_MMR_NIOSRESERVE1_s
8207
{
8208
uint32_t
nios_reserve1
: 16;
8209
uint32_t : 16;
8210
};
8211
8213
typedef
volatile
struct
ALT_IO48_HMC_MMR_NIOSRESERVE1_s
ALT_IO48_HMC_MMR_NIOSRESERVE1_t
;
8214
#endif
/* __ASSEMBLY__ */
8215
8217
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_RESET 0x00000000
8218
8219
#define ALT_IO48_HMC_MMR_NIOSRESERVE1_OFST 0x114
8220
8241
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_LSB 0
8242
8243
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_MSB 15
8244
8245
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_WIDTH 16
8246
8247
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET_MSK 0x0000ffff
8248
8249
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_CLR_MSK 0xffff0000
8250
8251
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_RESET 0x0
8252
8253
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_GET(value) (((value) & 0x0000ffff) >> 0)
8254
8255
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_NIOS_RESERVE2_SET(value) (((value) << 0) & 0x0000ffff)
8256
8257
#ifndef __ASSEMBLY__
8258
8268
struct
ALT_IO48_HMC_MMR_NIOSRESERVE2_s
8269
{
8270
uint32_t
nios_reserve2
: 16;
8271
uint32_t : 16;
8272
};
8273
8275
typedef
volatile
struct
ALT_IO48_HMC_MMR_NIOSRESERVE2_s
ALT_IO48_HMC_MMR_NIOSRESERVE2_t
;
8276
#endif
/* __ASSEMBLY__ */
8277
8279
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_RESET 0x00000000
8280
8281
#define ALT_IO48_HMC_MMR_NIOSRESERVE2_OFST 0x118
8282
8283
#ifndef __ASSEMBLY__
8284
8294
struct
ALT_IO48_HMC_MMR_s
8295
{
8296
volatile
ALT_IO48_HMC_MMR_DBGCFG0_t
dbgcfg0
;
8297
volatile
ALT_IO48_HMC_MMR_DBGCFG1_t
dbgcfg1
;
8298
volatile
ALT_IO48_HMC_MMR_DBGCFG2_t
dbgcfg2
;
8299
volatile
ALT_IO48_HMC_MMR_DBGCFG3_t
dbgcfg3
;
8300
volatile
ALT_IO48_HMC_MMR_DBGCFG4_t
dbgcfg4
;
8301
volatile
ALT_IO48_HMC_MMR_DBGCFG5_t
dbgcfg5
;
8302
volatile
ALT_IO48_HMC_MMR_DBGCFG6_t
dbgcfg6
;
8303
volatile
ALT_IO48_HMC_MMR_RESERVE0_t
reserve0
;
8304
volatile
ALT_IO48_HMC_MMR_RESERVE1_t
reserve1
;
8305
volatile
ALT_IO48_HMC_MMR_RESERVE2_t
reserve2
;
8306
volatile
ALT_IO48_HMC_MMR_CTLCFG0_t
ctrlcfg0
;
8307
volatile
ALT_IO48_HMC_MMR_CTLCFG1_t
ctrlcfg1
;
8308
volatile
ALT_IO48_HMC_MMR_CTLCFG2_t
ctrlcfg2
;
8309
volatile
ALT_IO48_HMC_MMR_CTLCFG3_t
ctrlcfg3
;
8310
volatile
ALT_IO48_HMC_MMR_CTLCFG4_t
ctrlcfg4
;
8311
volatile
ALT_IO48_HMC_MMR_CTLCFG5_t
ctrlcfg5
;
8312
volatile
ALT_IO48_HMC_MMR_CTLCFG6_t
ctrlcfg6
;
8313
volatile
ALT_IO48_HMC_MMR_CTLCFG7_t
ctrlcfg7
;
8314
volatile
ALT_IO48_HMC_MMR_CTLCFG8_t
ctrlcfg8
;
8315
volatile
ALT_IO48_HMC_MMR_CTLCFG9_t
ctrlcfg9
;
8316
volatile
ALT_IO48_HMC_MMR_DRAMTIMING0_t
dramtiming0
;
8317
volatile
ALT_IO48_HMC_MMR_DRAMODT0_t
dramodt0
;
8318
volatile
ALT_IO48_HMC_MMR_DRAMODT1_t
dramodt1
;
8319
volatile
ALT_IO48_HMC_MMR_SBCFG0_t
sbcfg0
;
8320
volatile
ALT_IO48_HMC_MMR_SBCFG1_t
sbcfg1
;
8321
volatile
ALT_IO48_HMC_MMR_SBCFG2_t
sbcfg2
;
8322
volatile
ALT_IO48_HMC_MMR_SBCFG3_t
sbcfg3
;
8323
volatile
ALT_IO48_HMC_MMR_SBCFG4_t
sbcfg4
;
8324
volatile
ALT_IO48_HMC_MMR_SBCFG5_t
sbcfg5
;
8325
volatile
ALT_IO48_HMC_MMR_SBCFG6_t
sbcfg6
;
8326
volatile
ALT_IO48_HMC_MMR_SBCFG7_t
sbcfg7
;
8327
volatile
ALT_IO48_HMC_MMR_CALTIMING0_t
caltiming0
;
8328
volatile
ALT_IO48_HMC_MMR_CALTIMING1_t
caltiming1
;
8329
volatile
ALT_IO48_HMC_MMR_CALTIMING2_t
caltiming2
;
8330
volatile
ALT_IO48_HMC_MMR_CALTIMING3_t
caltiming3
;
8331
volatile
ALT_IO48_HMC_MMR_CALTIMING4_t
caltiming4
;
8332
volatile
ALT_IO48_HMC_MMR_CALTIMING5_t
caltiming5
;
8333
volatile
ALT_IO48_HMC_MMR_CALTIMING6_t
caltiming6
;
8334
volatile
ALT_IO48_HMC_MMR_CALTIMING7_t
caltiming7
;
8335
volatile
ALT_IO48_HMC_MMR_CALTIMING8_t
caltiming8
;
8336
volatile
ALT_IO48_HMC_MMR_CALTIMING9_t
caltiming9
;
8337
volatile
ALT_IO48_HMC_MMR_CALTIMING10_t
caltiming10
;
8338
volatile
ALT_IO48_HMC_MMR_DRAMADDRW_t
dramaddrw
;
8339
volatile
ALT_IO48_HMC_MMR_SIDEBAND0_t
sideband0
;
8340
volatile
ALT_IO48_HMC_MMR_SIDEBAND1_t
sideband1
;
8341
volatile
ALT_IO48_HMC_MMR_SIDEBAND2_t
sideband2
;
8342
volatile
ALT_IO48_HMC_MMR_SIDEBAND3_t
sideband3
;
8343
volatile
ALT_IO48_HMC_MMR_SIDEBAND4_t
sideband4
;
8344
volatile
ALT_IO48_HMC_MMR_SIDEBAND5_t
sideband5
;
8345
volatile
ALT_IO48_HMC_MMR_SIDEBAND6_t
sideband6
;
8346
volatile
ALT_IO48_HMC_MMR_SIDEBAND7_t
sideband7
;
8347
volatile
ALT_IO48_HMC_MMR_SIDEBAND8_t
sideband8
;
8348
volatile
ALT_IO48_HMC_MMR_SIDEBAND9_t
sideband9
;
8349
volatile
ALT_IO48_HMC_MMR_SIDEBAND10_t
sideband10
;
8350
volatile
ALT_IO48_HMC_MMR_SIDEBAND11_t
sideband11
;
8351
volatile
ALT_IO48_HMC_MMR_SIDEBAND12_t
sideband12
;
8352
volatile
ALT_IO48_HMC_MMR_SIDEBAND13_t
sideband13
;
8353
volatile
ALT_IO48_HMC_MMR_SIDEBAND14_t
sideband14
;
8354
volatile
ALT_IO48_HMC_MMR_SIDEBAND15_t
sideband15
;
8355
volatile
ALT_IO48_HMC_MMR_DRAMSTS_t
dramsts
;
8356
volatile
ALT_IO48_HMC_MMR_DBGDONE_t
dbgdone
;
8357
volatile
ALT_IO48_HMC_MMR_DBGSIGNALS_t
dbgsignals
;
8358
volatile
ALT_IO48_HMC_MMR_DBGRST_t
dbgreset
;
8359
volatile
ALT_IO48_HMC_MMR_DBGMATCH_t
dbgmatch
;
8360
volatile
ALT_IO48_HMC_MMR_CNTR0MSK_t
counter0mask
;
8361
volatile
ALT_IO48_HMC_MMR_CNTR1MSK_t
counter1mask
;
8362
volatile
ALT_IO48_HMC_MMR_CNTR0MATCH_t
counter0match
;
8363
volatile
ALT_IO48_HMC_MMR_CNTR1MATCH_t
counter1match
;
8364
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE0_t
niosreserve0
;
8365
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE1_t
niosreserve1
;
8366
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE2_t
niosreserve2
;
8367
volatile
uint32_t
_pad_0x11c_0x1000
[953];
8368
};
8369
8371
typedef
volatile
struct
ALT_IO48_HMC_MMR_s
ALT_IO48_HMC_MMR_t
;
8373
struct
ALT_IO48_HMC_MMR_raw_s
8374
{
8375
volatile
uint32_t
dbgcfg0
;
8376
volatile
uint32_t
dbgcfg1
;
8377
volatile
uint32_t
dbgcfg2
;
8378
volatile
uint32_t
dbgcfg3
;
8379
volatile
uint32_t
dbgcfg4
;
8380
volatile
uint32_t
dbgcfg5
;
8381
volatile
uint32_t
dbgcfg6
;
8382
volatile
uint32_t
reserve0
;
8383
volatile
uint32_t
reserve1
;
8384
volatile
uint32_t
reserve2
;
8385
volatile
uint32_t
ctrlcfg0
;
8386
volatile
uint32_t
ctrlcfg1
;
8387
volatile
uint32_t
ctrlcfg2
;
8388
volatile
uint32_t
ctrlcfg3
;
8389
volatile
uint32_t
ctrlcfg4
;
8390
volatile
uint32_t
ctrlcfg5
;
8391
volatile
uint32_t
ctrlcfg6
;
8392
volatile
uint32_t
ctrlcfg7
;
8393
volatile
uint32_t
ctrlcfg8
;
8394
volatile
uint32_t
ctrlcfg9
;
8395
volatile
uint32_t
dramtiming0
;
8396
volatile
uint32_t
dramodt0
;
8397
volatile
uint32_t
dramodt1
;
8398
volatile
uint32_t
sbcfg0
;
8399
volatile
uint32_t
sbcfg1
;
8400
volatile
uint32_t
sbcfg2
;
8401
volatile
uint32_t
sbcfg3
;
8402
volatile
uint32_t
sbcfg4
;
8403
volatile
uint32_t
sbcfg5
;
8404
volatile
uint32_t
sbcfg6
;
8405
volatile
uint32_t
sbcfg7
;
8406
volatile
uint32_t
caltiming0
;
8407
volatile
uint32_t
caltiming1
;
8408
volatile
uint32_t
caltiming2
;
8409
volatile
uint32_t
caltiming3
;
8410
volatile
uint32_t
caltiming4
;
8411
volatile
uint32_t
caltiming5
;
8412
volatile
uint32_t
caltiming6
;
8413
volatile
uint32_t
caltiming7
;
8414
volatile
uint32_t
caltiming8
;
8415
volatile
uint32_t
caltiming9
;
8416
volatile
uint32_t
caltiming10
;
8417
volatile
uint32_t
dramaddrw
;
8418
volatile
uint32_t
sideband0
;
8419
volatile
uint32_t
sideband1
;
8420
volatile
uint32_t
sideband2
;
8421
volatile
uint32_t
sideband3
;
8422
volatile
uint32_t
sideband4
;
8423
volatile
uint32_t
sideband5
;
8424
volatile
uint32_t
sideband6
;
8425
volatile
uint32_t
sideband7
;
8426
volatile
uint32_t
sideband8
;
8427
volatile
uint32_t
sideband9
;
8428
volatile
uint32_t
sideband10
;
8429
volatile
uint32_t
sideband11
;
8430
volatile
uint32_t
sideband12
;
8431
volatile
uint32_t
sideband13
;
8432
volatile
uint32_t
sideband14
;
8433
volatile
uint32_t
sideband15
;
8434
volatile
uint32_t
dramsts
;
8435
volatile
uint32_t
dbgdone
;
8436
volatile
uint32_t
dbgsignals
;
8437
volatile
uint32_t
dbgreset
;
8438
volatile
uint32_t
dbgmatch
;
8439
volatile
uint32_t
counter0mask
;
8440
volatile
uint32_t
counter1mask
;
8441
volatile
uint32_t
counter0match
;
8442
volatile
uint32_t
counter1match
;
8443
volatile
uint32_t
niosreserve0
;
8444
volatile
uint32_t
niosreserve1
;
8445
volatile
uint32_t
niosreserve2
;
8446
volatile
uint32_t
_pad_0x11c_0x1000
[953];
8447
};
8448
8450
typedef
volatile
struct
ALT_IO48_HMC_MMR_raw_s
ALT_IO48_HMC_MMR_raw_t
;
8451
#endif
/* __ASSEMBLY__ */
8452
8454
#ifdef __cplusplus
8455
}
8456
#endif
/* __cplusplus */
8457
#endif
/* __ALT_SOCAL_IO48_HMC_MMR_H__ */
8458
include
soc_a10
socal
alt_io48_hmc_mmr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2