Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : CPU1 Start Address Register - cpu1startaddr

Description

When CPU1 is released from reset and the Boot ROM is located at the CPU1 reset exception address (the typical case), the Boot ROM reset handler code reads the address stored in this register and jumps it to hand off execution to user software.

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 Address

Field : Address - value

Address for CPU1 to start executing at after coming out of reset.

Field Access Macros:

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB   0
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB   31
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH   32
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK   0xffffffff
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK   0x00000000
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET   0x0
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s
 

Macros

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST   0x4
 

Typedefs

typedef struct
ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s 
ALT_SYSMGR_ROMCODE_CPU1STARTADDR_t
 

Data Structure Documentation

struct ALT_SYSMGR_ROMCODE_CPU1STARTADDR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_ROMCODE_CPU1STARTADDR.

Data Fields
uint32_t value: 32 Address

Macro Definitions

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_MSB   31

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_WIDTH   32

The width in bits of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET_MSK   0xffffffff

The mask used to set the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_CLR_MSK   0x00000000

The mask used to clear the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_RESET   0x0

The reset value of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE field value from a register.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_SYSMGR_ROMCODE_CPU1STARTADDR_VALUE register field value suitable for setting the register.

#define ALT_SYSMGR_ROMCODE_CPU1STARTADDR_OFST   0x4

The byte offset of the ALT_SYSMGR_ROMCODE_CPU1STARTADDR register from the beginning of the component.

Typedef Documentation