Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Individual Disable Register - indiv

Description

Used to disable individual interfaces between the FPGA and HPS.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Reset Request Interface
[1] RW 0x1 JTAG Enable Interface
[2] RW 0x1 CONFIG_IO Interface
[3] RW 0x1 Boundary-Scan Interface
[4] RW 0x1 Trace Interface
[5] ??? 0x1 UNDEFINED
[6] RW 0x1 STM Event Interface
[7] RW 0x1 Cross Trigger Interface (CTI)
[31:8] ??? 0x0 UNDEFINED

Field : Reset Request Interface - rstreqintf

Used to disable the reset request interface. This interface allows logic in the FPGA fabric to request HPS resets. This field disables the following reset request signals from the FPGA fabric to HPS:[list][*]f2h_cold_rst_req_n - Triggers a cold reset of the HPS[*]f2h_warm_rst_req_n - Triggers a warm reset of the HPS[*]f2h_dbg_rst_req_n - Triggers a debug reset of the HPS[/list]

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS 0x0 Reset request interface is disabled. Logic in
: the FPGA fabric cannot reset the HPS.
ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN 0x1 Reset request interface is enabled. Logic in the
: FPGA fabric can reset the HPS.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB   0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB   0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK   0x00000001
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET(value)   (((value) << 0) & 0x00000001)
 

Field : JTAG Enable Interface - jtagenintf

Used to disable the JTAG enable interface. This interface allows logic in the FPGA fabric to disable the HPS JTAG operation.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS 0x0 JTAG enable interface is disabled. Logic in the
: FPGA fabric cannot disable the HPS JTAG.
ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN 0x1 JTAG enable interface is enabled. Logic in the
: FPGA fabric can disable the HPS JTAG.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK   0x00000002
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK   0xfffffffd
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET(value)   (((value) << 1) & 0x00000002)
 

Field : CONFIG_IO Interface - configiointf

Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP controller to execute the CONFIG_IO instruction and configure all device I/Os (FPGA and HPS). This is typically done before executing boundary-scan instructions. The CONFIG_IO interface must be enabled before attempting to send the CONFIG_IO instruction to the FPGA JTAG TAP controller.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS 0x0 CONFIG_IO interface is disabled. Execution of
: the CONFIG_IO instruction in the FPGA JTAG TAP
: controller is unsupported and produces undefined
: results.
ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN 0x1 CONFIG_IO interface is enabled. Execution of the
: CONFIG_IO instruction in the FPGA JTAG TAP
: controller is supported.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB   2
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB   2
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK   0x00000004
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK   0xfffffffb
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Boundary-Scan Interface - bscanintf

Used to disable the boundary-scan interface. This interface allows the FPGA JTAG TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting to send the boundary-scan instructions to the FPGA JTAG TAP controller.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS 0x0 Boundary-scan interface is disabled. Execution
: of boundary-scan instructions in the FPGA JTAG
: TAP controller is unsupported and produces
: undefined results.
ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN 0x1 Boundary-scan interface is enabled. Execution of
: the boundary-scan instructions in the FPGA JTAG
: TAP controller is supported.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB   3
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB   3
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK   0x00000008
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK   0xfffffff7
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Trace Interface - traceintf

Used to disable the trace interface. This interface allows the HPS debug logic to send trace data to logic in the FPGA fabric.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS 0x0 Trace interface is disabled. HPS debug logic
: cannot send trace data to the FPGA fabric.
ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN 0x1 Trace interface is enabled. Other registers in
: the HPS debug logic must be programmmed to
: actually send trace data to the FPGA fabric.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB   4
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB   4
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK   0x00000010
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK   0xffffffef
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET(value)   (((value) << 4) & 0x00000010)
 

Field : STM Event Interface - stmeventintf

Used to disable the STM event interface. This interface allows logic in the FPGA fabric to trigger events to the STM debug module in the HPS.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS 0x0 STM event interface is disabled. Logic in the
: FPGA fabric cannot trigger STM events.
ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN 0x1 STM event interface is enabled. Logic in the
: FPGA fabric can trigger STM events.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB   6
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB   6
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK   0x00000040
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK   0xffffffbf
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Cross Trigger Interface (CTI) - crosstrigintf

Used to disable the FPGA Fabric from sending triggers to HPS debug logic. Note that this doesn't prevent the HPS debug logic from sending triggers to the FPGA Fabric.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS 0x0 FPGA Fabric cannot send triggers.
ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN 0x1 FPGA Fabric can send triggers.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB   7
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB   7
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK   0x00000080
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK   0xffffff7f
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET(value)   (((value) << 7) & 0x00000080)
 

Data Structures

struct  ALT_SYSMGR_FPGAINTF_INDIV_s
 

Macros

#define ALT_SYSMGR_FPGAINTF_INDIV_OFST   0x4
 

Typedefs

typedef struct
ALT_SYSMGR_FPGAINTF_INDIV_s 
ALT_SYSMGR_FPGAINTF_INDIV_t
 

Data Structure Documentation

struct ALT_SYSMGR_FPGAINTF_INDIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_FPGAINTF_INDIV.

Data Fields
uint32_t rstreqintf: 1 Reset Request Interface
uint32_t jtagenintf: 1 JTAG Enable Interface
uint32_t configiointf: 1 CONFIG_IO Interface
uint32_t bscanintf: 1 Boundary-Scan Interface
uint32_t traceintf: 1 Trace Interface
uint32_t __pad0__: 1 UNDEFINED
uint32_t stmeventintf: 1 STM Event Interface
uint32_t crosstrigintf: 1 Cross Trigger Interface (CTI)
uint32_t __pad1__: 24 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF

Reset request interface is disabled. Logic in the FPGA fabric cannot reset the HPS.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF

Reset request interface is enabled. Logic in the FPGA fabric can reset the HPS.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_RSTREQINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF

JTAG enable interface is disabled. Logic in the FPGA fabric cannot disable the HPS JTAG.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF

JTAG enable interface is enabled. Logic in the FPGA fabric can disable the HPS JTAG.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_LSB   1

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET_MSK   0x00000002

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_JTAGENINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF

CONFIG_IO interface is disabled. Execution of the CONFIG_IO instruction in the FPGA JTAG TAP controller is unsupported and produces undefined results.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF

CONFIG_IO interface is enabled. Execution of the CONFIG_IO instruction in the FPGA JTAG TAP controller is supported.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_LSB   2

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_MSB   2

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET_MSK   0x00000004

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_CFGIOINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF

Boundary-scan interface is disabled. Execution of boundary-scan instructions in the FPGA JTAG TAP controller is unsupported and produces undefined results.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF

Boundary-scan interface is enabled. Execution of the boundary-scan instructions in the FPGA JTAG TAP controller is supported.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_LSB   3

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_MSB   3

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET_MSK   0x00000008

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_BSCANINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF

Trace interface is disabled. HPS debug logic cannot send trace data to the FPGA fabric.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF

Trace interface is enabled. Other registers in the HPS debug logic must be programmmed to actually send trace data to the FPGA fabric.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_LSB   4

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_MSB   4

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET_MSK   0x00000010

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_CLR_MSK   0xffffffef

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_TRACEINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF

STM event interface is disabled. Logic in the FPGA fabric cannot trigger STM events.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF

STM event interface is enabled. Logic in the FPGA fabric can trigger STM events.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_LSB   6

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_MSB   6

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET_MSK   0x00000040

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_STMEVENTINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF

FPGA Fabric cannot send triggers.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF

FPGA Fabric can send triggers.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_LSB   7

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET_MSK   0x00000080

The mask used to set the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SYSMGR_FPGAINTF_INDIV_CROSSTRIGINTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_INDIV_OFST   0x4

The byte offset of the ALT_SYSMGR_FPGAINTF_INDIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_FPGAINTF_INDIV.