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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk, defined in this table as SPI master ref clock.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x0 | Clock Delay with n_ss_out |
[15:8] | RW | 0x0 | Clock Delay for Last Transaction Bit |
[23:16] | RW | 0x0 | Clock Delay for Chip Select Deactivation |
[31:24] | RW | 0x0 | Clock Delay for Chip Select Deassert |
Field : Clock Delay with n_ss_out - init | |
Delay in master reference clocks between setting n_ss_out low and first bit transfer. Field Access Macros: | |
#define | ALT_QSPI_DELAY_INIT_LSB 0 |
#define | ALT_QSPI_DELAY_INIT_MSB 7 |
#define | ALT_QSPI_DELAY_INIT_WIDTH 8 |
#define | ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff |
#define | ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 |
#define | ALT_QSPI_DELAY_INIT_RESET 0x0 |
#define | ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff) |
Field : Clock Delay for Last Transaction Bit - after | |
Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default, the chip select will be deasserted on the cycle following the completion of the current transaction. Field Access Macros: | |
#define | ALT_QSPI_DELAY_AFTER_LSB 8 |
#define | ALT_QSPI_DELAY_AFTER_MSB 15 |
#define | ALT_QSPI_DELAY_AFTER_WIDTH 8 |
#define | ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 |
#define | ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff |
#define | ALT_QSPI_DELAY_AFTER_RESET 0x0 |
#define | ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8) |
#define | ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00) |
Field : Clock Delay for Chip Select Deactivation - btwn | |
Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and requires the transmit FIFO to be empty. Field Access Macros: | |
#define | ALT_QSPI_DELAY_BTWN_LSB 16 |
#define | ALT_QSPI_DELAY_BTWN_MSB 23 |
#define | ALT_QSPI_DELAY_BTWN_WIDTH 8 |
#define | ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 |
#define | ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff |
#define | ALT_QSPI_DELAY_BTWN_RESET 0x0 |
#define | ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16) |
#define | ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000) |
Field : Clock Delay for Chip Select Deassert - nss | |
Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never re-asserted within an SCLK period. Field Access Macros: | |
#define | ALT_QSPI_DELAY_NSS_LSB 24 |
#define | ALT_QSPI_DELAY_NSS_MSB 31 |
#define | ALT_QSPI_DELAY_NSS_WIDTH 8 |
#define | ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 |
#define | ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff |
#define | ALT_QSPI_DELAY_NSS_RESET 0x0 |
#define | ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24) |
#define | ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000) |
Data Structures | |
struct | ALT_QSPI_DELAY_s |
Macros | |
#define | ALT_QSPI_DELAY_RESET 0x00000000 |
#define | ALT_QSPI_DELAY_OFST 0xc |
Typedefs | |
typedef struct ALT_QSPI_DELAY_s | ALT_QSPI_DELAY_t |
struct ALT_QSPI_DELAY_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_DELAY.
Data Fields | ||
---|---|---|
uint32_t | init: 8 | Clock Delay with n_ss_out |
uint32_t | after: 8 | Clock Delay for Last Transaction Bit |
uint32_t | btwn: 8 | Clock Delay for Chip Select Deactivation |
uint32_t | nss: 8 | Clock Delay for Chip Select Deassert |
#define ALT_QSPI_DELAY_INIT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_INIT register field.
#define ALT_QSPI_DELAY_INIT_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_INIT register field.
#define ALT_QSPI_DELAY_INIT_WIDTH 8 |
The width in bits of the ALT_QSPI_DELAY_INIT register field.
#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff |
The mask used to set the ALT_QSPI_DELAY_INIT register field value.
#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_QSPI_DELAY_INIT register field value.
#define ALT_QSPI_DELAY_INIT_RESET 0x0 |
The reset value of the ALT_QSPI_DELAY_INIT register field.
#define ALT_QSPI_DELAY_INIT_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_QSPI_DELAY_INIT field value from a register.
#define ALT_QSPI_DELAY_INIT_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_QSPI_DELAY_INIT register field value suitable for setting the register.
#define ALT_QSPI_DELAY_AFTER_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_AFTER register field.
#define ALT_QSPI_DELAY_AFTER_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_AFTER register field.
#define ALT_QSPI_DELAY_AFTER_WIDTH 8 |
The width in bits of the ALT_QSPI_DELAY_AFTER register field.
#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00 |
The mask used to set the ALT_QSPI_DELAY_AFTER register field value.
#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff |
The mask used to clear the ALT_QSPI_DELAY_AFTER register field value.
#define ALT_QSPI_DELAY_AFTER_RESET 0x0 |
The reset value of the ALT_QSPI_DELAY_AFTER register field.
#define ALT_QSPI_DELAY_AFTER_GET | ( | value | ) | (((value) & 0x0000ff00) >> 8) |
Extracts the ALT_QSPI_DELAY_AFTER field value from a register.
#define ALT_QSPI_DELAY_AFTER_SET | ( | value | ) | (((value) << 8) & 0x0000ff00) |
Produces a ALT_QSPI_DELAY_AFTER register field value suitable for setting the register.
#define ALT_QSPI_DELAY_BTWN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_BTWN register field.
#define ALT_QSPI_DELAY_BTWN_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_BTWN register field.
#define ALT_QSPI_DELAY_BTWN_WIDTH 8 |
The width in bits of the ALT_QSPI_DELAY_BTWN register field.
#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000 |
The mask used to set the ALT_QSPI_DELAY_BTWN register field value.
#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff |
The mask used to clear the ALT_QSPI_DELAY_BTWN register field value.
#define ALT_QSPI_DELAY_BTWN_RESET 0x0 |
The reset value of the ALT_QSPI_DELAY_BTWN register field.
#define ALT_QSPI_DELAY_BTWN_GET | ( | value | ) | (((value) & 0x00ff0000) >> 16) |
Extracts the ALT_QSPI_DELAY_BTWN field value from a register.
#define ALT_QSPI_DELAY_BTWN_SET | ( | value | ) | (((value) << 16) & 0x00ff0000) |
Produces a ALT_QSPI_DELAY_BTWN register field value suitable for setting the register.
#define ALT_QSPI_DELAY_NSS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DELAY_NSS register field.
#define ALT_QSPI_DELAY_NSS_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DELAY_NSS register field.
#define ALT_QSPI_DELAY_NSS_WIDTH 8 |
The width in bits of the ALT_QSPI_DELAY_NSS register field.
#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000 |
The mask used to set the ALT_QSPI_DELAY_NSS register field value.
#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff |
The mask used to clear the ALT_QSPI_DELAY_NSS register field value.
#define ALT_QSPI_DELAY_NSS_RESET 0x0 |
The reset value of the ALT_QSPI_DELAY_NSS register field.
#define ALT_QSPI_DELAY_NSS_GET | ( | value | ) | (((value) & 0xff000000) >> 24) |
Extracts the ALT_QSPI_DELAY_NSS field value from a register.
#define ALT_QSPI_DELAY_NSS_SET | ( | value | ) | (((value) << 24) & 0xff000000) |
Produces a ALT_QSPI_DELAY_NSS register field value suitable for setting the register.
#define ALT_QSPI_DELAY_RESET 0x00000000 |
The reset value of the ALT_QSPI_DELAY register.
#define ALT_QSPI_DELAY_OFST 0xc |
The byte offset of the ALT_QSPI_DELAY register from the beginning of the component.
typedef struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t |
The typedef declaration for register ALT_QSPI_DELAY.