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alt_clkmgr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALTERA_ALT_CLKMGR_H__
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#define __ALTERA_ALT_CLKMGR_H__
37
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#ifdef __cplusplus
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extern
"C"
40
{
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#endif
/* __cplusplus */
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#define ALT_CLKMGR_CTL_SAFEMOD_LSB 0
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#define ALT_CLKMGR_CTL_SAFEMOD_MSB 0
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#define ALT_CLKMGR_CTL_SAFEMOD_WIDTH 1
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#define ALT_CLKMGR_CTL_SAFEMOD_SET_MSK 0x00000001
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#define ALT_CLKMGR_CTL_SAFEMOD_CLR_MSK 0xfffffffe
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#define ALT_CLKMGR_CTL_SAFEMOD_RESET 0x1
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#define ALT_CLKMGR_CTL_SAFEMOD_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_CLKMGR_CTL_SAFEMOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_CLKMGR_CTL_ENSFMDWR_LSB 2
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#define ALT_CLKMGR_CTL_ENSFMDWR_MSB 2
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#define ALT_CLKMGR_CTL_ENSFMDWR_WIDTH 1
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#define ALT_CLKMGR_CTL_ENSFMDWR_SET_MSK 0x00000004
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#define ALT_CLKMGR_CTL_ENSFMDWR_CLR_MSK 0xfffffffb
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#define ALT_CLKMGR_CTL_ENSFMDWR_RESET 0x1
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#define ALT_CLKMGR_CTL_ENSFMDWR_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_CLKMGR_CTL_ENSFMDWR_SET(value) (((value) << 2) & 0x00000004)
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#ifndef __ASSEMBLY__
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struct
ALT_CLKMGR_CTL_s
141
{
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uint32_t
safemode
: 1;
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uint32_t : 1;
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uint32_t
ensfmdwr
: 1;
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uint32_t : 29;
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};
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typedef
volatile
struct
ALT_CLKMGR_CTL_s
ALT_CLKMGR_CTL_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_CLKMGR_CTL_OFST 0x0
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186
#define ALT_CLKMGR_BYPASS_MAINPLL_LSB 0
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#define ALT_CLKMGR_BYPASS_MAINPLL_MSB 0
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#define ALT_CLKMGR_BYPASS_MAINPLL_WIDTH 1
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#define ALT_CLKMGR_BYPASS_MAINPLL_SET_MSK 0x00000001
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#define ALT_CLKMGR_BYPASS_MAINPLL_CLR_MSK 0xfffffffe
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#define ALT_CLKMGR_BYPASS_MAINPLL_RESET 0x1
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#define ALT_CLKMGR_BYPASS_MAINPLL_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_CLKMGR_BYPASS_MAINPLL_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_CLKMGR_BYPASS_SDRPLL_LSB 1
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#define ALT_CLKMGR_BYPASS_SDRPLL_MSB 1
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#define ALT_CLKMGR_BYPASS_SDRPLL_WIDTH 1
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#define ALT_CLKMGR_BYPASS_SDRPLL_SET_MSK 0x00000002
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#define ALT_CLKMGR_BYPASS_SDRPLL_CLR_MSK 0xfffffffd
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#define ALT_CLKMGR_BYPASS_SDRPLL_RESET 0x1
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#define ALT_CLKMGR_BYPASS_SDRPLL_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_CLKMGR_BYPASS_SDRPLL_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_EOSC1 0x0
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_E_SELECT_INPUT_MUX 0x1
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_LSB 2
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_MSB 2
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_WIDTH 1
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET_MSK 0x00000004
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_CLR_MSK 0xfffffffb
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_RESET 0x0
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_CLKMGR_BYPASS_SDRPLLSRC_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_CLKMGR_BYPASS_PERPLL_LSB 3
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#define ALT_CLKMGR_BYPASS_PERPLL_MSB 3
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#define ALT_CLKMGR_BYPASS_PERPLL_WIDTH 1
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#define ALT_CLKMGR_BYPASS_PERPLL_SET_MSK 0x00000008
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#define ALT_CLKMGR_BYPASS_PERPLL_CLR_MSK 0xfffffff7
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#define ALT_CLKMGR_BYPASS_PERPLL_RESET 0x1
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#define ALT_CLKMGR_BYPASS_PERPLL_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_CLKMGR_BYPASS_PERPLL_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_EOSC1 0x0
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_E_SELECT_INPUT_MUX 0x1
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_LSB 4
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_MSB 4
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_WIDTH 1
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET_MSK 0x00000010
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_CLR_MSK 0xffffffef
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_RESET 0x0
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_CLKMGR_BYPASS_PERPLLSRC_SET(value) (((value) << 4) & 0x00000010)
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#ifndef __ASSEMBLY__
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struct
ALT_CLKMGR_BYPASS_s
382
{
383
uint32_t
mainpll
: 1;
384
uint32_t
sdrpll
: 1;
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uint32_t
sdrpllsrc
: 1;
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uint32_t
perpll
: 1;
387
uint32_t
perpllsrc
: 1;
388
uint32_t : 27;
389
};
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typedef
volatile
struct
ALT_CLKMGR_BYPASS_s
ALT_CLKMGR_BYPASS_t
;
393
#endif
/* __ASSEMBLY__ */
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#define ALT_CLKMGR_BYPASS_OFST 0x4
397
431
#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_LSB 0
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_MSB 0
434
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_WIDTH 1
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET_MSK 0x00000001
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_RESET 0x0
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_CLKMGR_INTER_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_LSB 1
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_MSB 1
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_WIDTH 1
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET_MSK 0x00000002
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_CLR_MSK 0xfffffffd
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_RESET 0x0
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_CLKMGR_INTER_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_LSB 2
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_MSB 2
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_WIDTH 1
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET_MSK 0x00000004
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_RESET 0x0
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_CLKMGR_INTER_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_CLKMGR_INTER_MAINPLLLOST_LSB 3
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#define ALT_CLKMGR_INTER_MAINPLLLOST_MSB 3
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#define ALT_CLKMGR_INTER_MAINPLLLOST_WIDTH 1
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#define ALT_CLKMGR_INTER_MAINPLLLOST_SET_MSK 0x00000008
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#define ALT_CLKMGR_INTER_MAINPLLLOST_CLR_MSK 0xfffffff7
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#define ALT_CLKMGR_INTER_MAINPLLLOST_RESET 0x0
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#define ALT_CLKMGR_INTER_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_CLKMGR_INTER_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_CLKMGR_INTER_PERPLLLOST_LSB 4
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#define ALT_CLKMGR_INTER_PERPLLLOST_MSB 4
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#define ALT_CLKMGR_INTER_PERPLLLOST_WIDTH 1
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#define ALT_CLKMGR_INTER_PERPLLLOST_SET_MSK 0x00000010
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#define ALT_CLKMGR_INTER_PERPLLLOST_CLR_MSK 0xffffffef
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#define ALT_CLKMGR_INTER_PERPLLLOST_RESET 0x0
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#define ALT_CLKMGR_INTER_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_CLKMGR_INTER_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_CLKMGR_INTER_SDRPLLLOST_LSB 5
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#define ALT_CLKMGR_INTER_SDRPLLLOST_MSB 5
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#define ALT_CLKMGR_INTER_SDRPLLLOST_WIDTH 1
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#define ALT_CLKMGR_INTER_SDRPLLLOST_SET_MSK 0x00000020
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#define ALT_CLKMGR_INTER_SDRPLLLOST_CLR_MSK 0xffffffdf
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#define ALT_CLKMGR_INTER_SDRPLLLOST_RESET 0x0
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#define ALT_CLKMGR_INTER_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_CLKMGR_INTER_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_LSB 6
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_MSB 6
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_WIDTH 1
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET_MSK 0x00000040
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_CLR_MSK 0xffffffbf
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_RESET 0x0
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_CLKMGR_INTER_MAINPLLLOCKED_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_LSB 7
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_MSB 7
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_WIDTH 1
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET_MSK 0x00000080
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_CLR_MSK 0xffffff7f
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_RESET 0x0
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_CLKMGR_INTER_PERPLLLOCKED_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_LSB 8
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_MSB 8
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_WIDTH 1
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET_MSK 0x00000100
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_CLR_MSK 0xfffffeff
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_RESET 0x0
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_CLKMGR_INTER_SDRPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
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#ifndef __ASSEMBLY__
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struct
ALT_CLKMGR_INTER_s
668
{
669
uint32_t
mainpllachieved
: 1;
670
uint32_t
perpllachieved
: 1;
671
uint32_t
sdrpllachieved
: 1;
672
uint32_t
mainplllost
: 1;
673
uint32_t
perplllost
: 1;
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uint32_t
sdrplllost
: 1;
675
const
uint32_t
mainplllocked
: 1;
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const
uint32_t
perplllocked
: 1;
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const
uint32_t
sdrplllocked
: 1;
678
uint32_t : 23;
679
};
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typedef
volatile
struct
ALT_CLKMGR_INTER_s
ALT_CLKMGR_INTER_t
;
683
#endif
/* __ASSEMBLY__ */
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#define ALT_CLKMGR_INTER_OFST 0x8
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_LSB 2
774
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_MSB 2
776
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_WIDTH 1
778
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET_MSK 0x00000004
780
781
#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_CLR_MSK 0xfffffffb
782
783
#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_RESET 0x0
784
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_GET(value) (((value) & 0x00000004) >> 2)
786
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#define ALT_CLKMGR_INTREN_SDRPLLACHIEVED_SET(value) (((value) << 2) & 0x00000004)
788
800
#define ALT_CLKMGR_INTREN_MAINPLLLOST_LSB 3
801
802
#define ALT_CLKMGR_INTREN_MAINPLLLOST_MSB 3
803
804
#define ALT_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
805
806
#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000008
807
808
#define ALT_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffff7
809
810
#define ALT_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
811
812
#define ALT_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
813
814
#define ALT_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 3) & 0x00000008)
815
827
#define ALT_CLKMGR_INTREN_PERPLLLOST_LSB 4
828
829
#define ALT_CLKMGR_INTREN_PERPLLLOST_MSB 4
830
831
#define ALT_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
832
833
#define ALT_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000010
834
835
#define ALT_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xffffffef
836
837
#define ALT_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
838
839
#define ALT_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000010) >> 4)
840
841
#define ALT_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 4) & 0x00000010)
842
854
#define ALT_CLKMGR_INTREN_SDRPLLLOST_LSB 5
855
856
#define ALT_CLKMGR_INTREN_SDRPLLLOST_MSB 5
857
858
#define ALT_CLKMGR_INTREN_SDRPLLLOST_WIDTH 1
859
860
#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET_MSK 0x00000020
861
862
#define ALT_CLKMGR_INTREN_SDRPLLLOST_CLR_MSK 0xffffffdf
863
864
#define ALT_CLKMGR_INTREN_SDRPLLLOST_RESET 0x0
865
866
#define ALT_CLKMGR_INTREN_SDRPLLLOST_GET(value) (((value) & 0x00000020) >> 5)
867
868
#define ALT_CLKMGR_INTREN_SDRPLLLOST_SET(value) (((value) << 5) & 0x00000020)
869
870
#ifndef __ASSEMBLY__
871
881
struct
ALT_CLKMGR_INTREN_s
882
{
883
uint32_t
mainpllachieved
: 1;
884
uint32_t
perpllachieved
: 1;
885
uint32_t
sdrpllachieved
: 1;
886
uint32_t
mainplllost
: 1;
887
uint32_t
perplllost
: 1;
888
uint32_t
sdrplllost
: 1;
889
uint32_t : 26;
890
};
891
893
typedef
volatile
struct
ALT_CLKMGR_INTREN_s
ALT_CLKMGR_INTREN_t
;
894
#endif
/* __ASSEMBLY__ */
895
897
#define ALT_CLKMGR_INTREN_OFST 0xc
898
929
#define ALT_CLKMGR_DBCTL_STAYOSC1_LSB 0
930
931
#define ALT_CLKMGR_DBCTL_STAYOSC1_MSB 0
932
933
#define ALT_CLKMGR_DBCTL_STAYOSC1_WIDTH 1
934
935
#define ALT_CLKMGR_DBCTL_STAYOSC1_SET_MSK 0x00000001
936
937
#define ALT_CLKMGR_DBCTL_STAYOSC1_CLR_MSK 0xfffffffe
938
939
#define ALT_CLKMGR_DBCTL_STAYOSC1_RESET 0x1
940
941
#define ALT_CLKMGR_DBCTL_STAYOSC1_GET(value) (((value) & 0x00000001) >> 0)
942
943
#define ALT_CLKMGR_DBCTL_STAYOSC1_SET(value) (((value) << 0) & 0x00000001)
944
962
#define ALT_CLKMGR_DBCTL_ENSFMDWR_LSB 1
963
964
#define ALT_CLKMGR_DBCTL_ENSFMDWR_MSB 1
965
966
#define ALT_CLKMGR_DBCTL_ENSFMDWR_WIDTH 1
967
968
#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET_MSK 0x00000002
969
970
#define ALT_CLKMGR_DBCTL_ENSFMDWR_CLR_MSK 0xfffffffd
971
972
#define ALT_CLKMGR_DBCTL_ENSFMDWR_RESET 0x1
973
974
#define ALT_CLKMGR_DBCTL_ENSFMDWR_GET(value) (((value) & 0x00000002) >> 1)
975
976
#define ALT_CLKMGR_DBCTL_ENSFMDWR_SET(value) (((value) << 1) & 0x00000002)
977
978
#ifndef __ASSEMBLY__
979
989
struct
ALT_CLKMGR_DBCTL_s
990
{
991
uint32_t
stayosc1
: 1;
992
uint32_t
ensfmdwr
: 1;
993
uint32_t : 30;
994
};
995
997
typedef
volatile
struct
ALT_CLKMGR_DBCTL_s
ALT_CLKMGR_DBCTL_t
;
998
#endif
/* __ASSEMBLY__ */
999
1001
#define ALT_CLKMGR_DBCTL_OFST 0x10
1002
1044
#define ALT_CLKMGR_STAT_BUSY_E_IDLE 0x0
1045
1050
#define ALT_CLKMGR_STAT_BUSY_E_BUSY 0x1
1051
1053
#define ALT_CLKMGR_STAT_BUSY_LSB 0
1054
1055
#define ALT_CLKMGR_STAT_BUSY_MSB 0
1056
1057
#define ALT_CLKMGR_STAT_BUSY_WIDTH 1
1058
1059
#define ALT_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1060
1061
#define ALT_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1062
1063
#define ALT_CLKMGR_STAT_BUSY_RESET 0x0
1064
1065
#define ALT_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1066
1067
#define ALT_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1068
1069
#ifndef __ASSEMBLY__
1070
1080
struct
ALT_CLKMGR_STAT_s
1081
{
1082
const
uint32_t
busy
: 1;
1083
uint32_t : 31;
1084
};
1085
1087
typedef
volatile
struct
ALT_CLKMGR_STAT_s
ALT_CLKMGR_STAT_t
;
1088
#endif
/* __ASSEMBLY__ */
1089
1091
#define ALT_CLKMGR_STAT_OFST 0x14
1092
1133
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_LSB 0
1134
1135
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_MSB 0
1136
1137
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_WIDTH 1
1138
1139
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET_MSK 0x00000001
1140
1141
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
1142
1143
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_RESET 0x1
1144
1145
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
1146
1147
#define ALT_CLKMGR_MAINPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
1148
1158
#define ALT_CLKMGR_MAINPLL_VCO_EN_LSB 1
1159
1160
#define ALT_CLKMGR_MAINPLL_VCO_EN_MSB 1
1161
1162
#define ALT_CLKMGR_MAINPLL_VCO_EN_WIDTH 1
1163
1164
#define ALT_CLKMGR_MAINPLL_VCO_EN_SET_MSK 0x00000002
1165
1166
#define ALT_CLKMGR_MAINPLL_VCO_EN_CLR_MSK 0xfffffffd
1167
1168
#define ALT_CLKMGR_MAINPLL_VCO_EN_RESET 0x0
1169
1170
#define ALT_CLKMGR_MAINPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
1171
1172
#define ALT_CLKMGR_MAINPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
1173
1183
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_LSB 2
1184
1185
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_MSB 2
1186
1187
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_WIDTH 1
1188
1189
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET_MSK 0x00000004
1190
1191
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
1192
1193
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_RESET 0x1
1194
1195
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
1196
1197
#define ALT_CLKMGR_MAINPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
1198
1211
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_LSB 3
1212
1213
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_MSB 15
1214
1215
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_WIDTH 13
1216
1217
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET_MSK 0x0000fff8
1218
1219
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_CLR_MSK 0xffff0007
1220
1221
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_RESET 0x1
1222
1223
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
1224
1225
#define ALT_CLKMGR_MAINPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
1226
1239
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_LSB 16
1240
1241
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_MSB 21
1242
1243
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_WIDTH 6
1244
1245
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET_MSK 0x003f0000
1246
1247
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
1248
1249
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_RESET 0x1
1250
1251
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
1252
1253
#define ALT_CLKMGR_MAINPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
1254
1271
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_LSB 24
1272
1273
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_MSB 24
1274
1275
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_WIDTH 1
1276
1277
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
1278
1279
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
1280
1281
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_RESET 0x0
1282
1283
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
1284
1285
#define ALT_CLKMGR_MAINPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
1286
1312
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_LSB 25
1313
1314
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_MSB 30
1315
1316
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_WIDTH 6
1317
1318
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET_MSK 0x7e000000
1319
1320
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
1321
1322
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_RESET 0x0
1323
1324
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
1325
1326
#define ALT_CLKMGR_MAINPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
1327
1349
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_LSB 31
1350
1351
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_MSB 31
1352
1353
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_WIDTH 1
1354
1355
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
1356
1357
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
1358
1359
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_RESET 0x1
1360
1361
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
1362
1363
#define ALT_CLKMGR_MAINPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
1364
1365
#ifndef __ASSEMBLY__
1366
1376
struct
ALT_CLKMGR_MAINPLL_VCO_s
1377
{
1378
uint32_t
bgpwrdn
: 1;
1379
uint32_t
en
: 1;
1380
uint32_t
pwrdn
: 1;
1381
uint32_t
numer
: 13;
1382
uint32_t
denom
: 6;
1383
uint32_t : 2;
1384
uint32_t
outresetall
: 1;
1385
uint32_t
outreset
: 6;
1386
uint32_t
regextsel
: 1;
1387
};
1388
1390
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_VCO_s
ALT_CLKMGR_MAINPLL_VCO_t
;
1391
#endif
/* __ASSEMBLY__ */
1392
1394
#define ALT_CLKMGR_MAINPLL_VCO_OFST 0x0
1395
1429
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_LSB 0
1430
1431
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_MSB 0
1432
1433
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_WIDTH 1
1434
1435
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET_MSK 0x00000001
1436
1437
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
1438
1439
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_RESET 0x0
1440
1441
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
1442
1443
#define ALT_CLKMGR_MAINPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
1444
1454
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_LSB 1
1455
1456
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_MSB 12
1457
1458
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_WIDTH 12
1459
1460
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET_MSK 0x00001ffe
1461
1462
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_CLR_MSK 0xffffe001
1463
1464
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_RESET 0x1
1465
1466
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
1467
1468
#define ALT_CLKMGR_MAINPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
1469
1479
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_LSB 13
1480
1481
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_MSB 13
1482
1483
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_WIDTH 1
1484
1485
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET_MSK 0x00002000
1486
1487
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
1488
1489
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_RESET 0x0
1490
1491
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
1492
1493
#define ALT_CLKMGR_MAINPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
1494
1504
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_LSB 14
1505
1506
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_MSB 14
1507
1508
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_WIDTH 1
1509
1510
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET_MSK 0x00004000
1511
1512
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_CLR_MSK 0xffffbfff
1513
1514
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_RESET 0x1
1515
1516
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
1517
1518
#define ALT_CLKMGR_MAINPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
1519
1520
#ifndef __ASSEMBLY__
1521
1531
struct
ALT_CLKMGR_MAINPLL_MISC_s
1532
{
1533
uint32_t
bwadjen
: 1;
1534
uint32_t
bwadj
: 12;
1535
uint32_t
fasten
: 1;
1536
uint32_t
saten
: 1;
1537
uint32_t : 17;
1538
};
1539
1541
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MISC_s
ALT_CLKMGR_MAINPLL_MISC_t
;
1542
#endif
/* __ASSEMBLY__ */
1543
1545
#define ALT_CLKMGR_MAINPLL_MISC_OFST 0x4
1546
1572
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
1573
1574
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 8
1575
1576
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 9
1577
1578
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000001ff
1579
1580
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffffe00
1581
1582
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
1583
1584
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1585
1586
#define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1587
1588
#ifndef __ASSEMBLY__
1589
1599
struct
ALT_CLKMGR_MAINPLL_MPUCLK_s
1600
{
1601
uint32_t
cnt
: 9;
1602
uint32_t : 23;
1603
};
1604
1606
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MPUCLK_s
ALT_CLKMGR_MAINPLL_MPUCLK_t
;
1607
#endif
/* __ASSEMBLY__ */
1608
1610
#define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x8
1611
1637
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_LSB 0
1638
1639
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_MSB 8
1640
1641
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_WIDTH 9
1642
1643
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET_MSK 0x000001ff
1644
1645
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_CLR_MSK 0xfffffe00
1646
1647
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_RESET 0x0
1648
1649
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1650
1651
#define ALT_CLKMGR_MAINPLL_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1652
1653
#ifndef __ASSEMBLY__
1654
1664
struct
ALT_CLKMGR_MAINPLL_MAINCLK_s
1665
{
1666
uint32_t
cnt
: 9;
1667
uint32_t : 23;
1668
};
1669
1671
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MAINCLK_s
ALT_CLKMGR_MAINPLL_MAINCLK_t
;
1672
#endif
/* __ASSEMBLY__ */
1673
1675
#define ALT_CLKMGR_MAINPLL_MAINCLK_OFST 0xc
1676
1702
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_LSB 0
1703
1704
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_MSB 8
1705
1706
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_WIDTH 9
1707
1708
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET_MSK 0x000001ff
1709
1710
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_CLR_MSK 0xfffffe00
1711
1712
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_RESET 0x0
1713
1714
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1715
1716
#define ALT_CLKMGR_MAINPLL_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1717
1718
#ifndef __ASSEMBLY__
1719
1729
struct
ALT_CLKMGR_MAINPLL_DBGATCLK_s
1730
{
1731
uint32_t
cnt
: 9;
1732
uint32_t : 23;
1733
};
1734
1736
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_DBGATCLK_s
ALT_CLKMGR_MAINPLL_DBGATCLK_t
;
1737
#endif
/* __ASSEMBLY__ */
1738
1740
#define ALT_CLKMGR_MAINPLL_DBGATCLK_OFST 0x10
1741
1767
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_LSB 0
1768
1769
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_MSB 8
1770
1771
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_WIDTH 9
1772
1773
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET_MSK 0x000001ff
1774
1775
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_CLR_MSK 0xfffffe00
1776
1777
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_RESET 0x3
1778
1779
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1780
1781
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1782
1783
#ifndef __ASSEMBLY__
1784
1794
struct
ALT_CLKMGR_MAINPLL_MAINQSPICLK_s
1795
{
1796
uint32_t
cnt
: 9;
1797
uint32_t : 23;
1798
};
1799
1801
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MAINQSPICLK_s
ALT_CLKMGR_MAINPLL_MAINQSPICLK_t
;
1802
#endif
/* __ASSEMBLY__ */
1803
1805
#define ALT_CLKMGR_MAINPLL_MAINQSPICLK_OFST 0x14
1806
1832
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_LSB 0
1833
1834
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_MSB 8
1835
1836
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_WIDTH 9
1837
1838
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
1839
1840
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
1841
1842
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_RESET 0x3
1843
1844
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1845
1846
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1847
1848
#ifndef __ASSEMBLY__
1849
1859
struct
ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s
1860
{
1861
uint32_t
cnt
: 9;
1862
uint32_t : 23;
1863
};
1864
1866
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_s
ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t
;
1867
#endif
/* __ASSEMBLY__ */
1868
1870
#define ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_OFST 0x18
1871
1899
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_LSB 0
1900
1901
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_MSB 8
1902
1903
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_WIDTH 9
1904
1905
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET_MSK 0x000001ff
1906
1907
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_CLR_MSK 0xfffffe00
1908
1909
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_RESET 0xf
1910
1911
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
1912
1913
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
1914
1915
#ifndef __ASSEMBLY__
1916
1926
struct
ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s
1927
{
1928
uint32_t
cnt
: 9;
1929
uint32_t : 23;
1930
};
1931
1933
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_s
ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t
;
1934
#endif
/* __ASSEMBLY__ */
1935
1937
#define ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_OFST 0x1c
1938
1976
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_LSB 0
1977
1978
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_MSB 0
1979
1980
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_WIDTH 1
1981
1982
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET_MSK 0x00000001
1983
1984
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_CLR_MSK 0xfffffffe
1985
1986
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_RESET 0x1
1987
1988
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_GET(value) (((value) & 0x00000001) >> 0)
1989
1990
#define ALT_CLKMGR_MAINPLL_EN_L4MAINCLK_SET(value) (((value) << 0) & 0x00000001)
1991
2001
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_LSB 1
2002
2003
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_MSB 1
2004
2005
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_WIDTH 1
2006
2007
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET_MSK 0x00000002
2008
2009
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_CLR_MSK 0xfffffffd
2010
2011
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_RESET 0x1
2012
2013
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_GET(value) (((value) & 0x00000002) >> 1)
2014
2015
#define ALT_CLKMGR_MAINPLL_EN_L3MPCLK_SET(value) (((value) << 1) & 0x00000002)
2016
2026
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_LSB 2
2027
2028
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_MSB 2
2029
2030
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_WIDTH 1
2031
2032
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET_MSK 0x00000004
2033
2034
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_CLR_MSK 0xfffffffb
2035
2036
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_RESET 0x1
2037
2038
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_GET(value) (((value) & 0x00000004) >> 2)
2039
2040
#define ALT_CLKMGR_MAINPLL_EN_L4MPCLK_SET(value) (((value) << 2) & 0x00000004)
2041
2051
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_LSB 3
2052
2053
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_MSB 3
2054
2055
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_WIDTH 1
2056
2057
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET_MSK 0x00000008
2058
2059
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_CLR_MSK 0xfffffff7
2060
2061
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_RESET 0x1
2062
2063
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_GET(value) (((value) & 0x00000008) >> 3)
2064
2065
#define ALT_CLKMGR_MAINPLL_EN_L4SPCLK_SET(value) (((value) << 3) & 0x00000008)
2066
2076
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_LSB 4
2077
2078
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_MSB 4
2079
2080
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_WIDTH 1
2081
2082
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET_MSK 0x00000010
2083
2084
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_CLR_MSK 0xffffffef
2085
2086
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_RESET 0x1
2087
2088
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_GET(value) (((value) & 0x00000010) >> 4)
2089
2090
#define ALT_CLKMGR_MAINPLL_EN_DBGATCLK_SET(value) (((value) << 4) & 0x00000010)
2091
2101
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_LSB 5
2102
2103
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_MSB 5
2104
2105
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_WIDTH 1
2106
2107
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET_MSK 0x00000020
2108
2109
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_CLR_MSK 0xffffffdf
2110
2111
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_RESET 0x1
2112
2113
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_GET(value) (((value) & 0x00000020) >> 5)
2114
2115
#define ALT_CLKMGR_MAINPLL_EN_DBGCLK_SET(value) (((value) << 5) & 0x00000020)
2116
2126
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_LSB 6
2127
2128
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_MSB 6
2129
2130
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_WIDTH 1
2131
2132
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET_MSK 0x00000040
2133
2134
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_CLR_MSK 0xffffffbf
2135
2136
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_RESET 0x1
2137
2138
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_GET(value) (((value) & 0x00000040) >> 6)
2139
2140
#define ALT_CLKMGR_MAINPLL_EN_DBGTRACECLK_SET(value) (((value) << 6) & 0x00000040)
2141
2151
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_LSB 7
2152
2153
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_MSB 7
2154
2155
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_WIDTH 1
2156
2157
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET_MSK 0x00000080
2158
2159
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_CLR_MSK 0xffffff7f
2160
2161
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_RESET 0x1
2162
2163
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_GET(value) (((value) & 0x00000080) >> 7)
2164
2165
#define ALT_CLKMGR_MAINPLL_EN_DBGTMRCLK_SET(value) (((value) << 7) & 0x00000080)
2166
2176
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_LSB 8
2177
2178
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_MSB 8
2179
2180
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_WIDTH 1
2181
2182
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET_MSK 0x00000100
2183
2184
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_CLR_MSK 0xfffffeff
2185
2186
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_RESET 0x1
2187
2188
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_GET(value) (((value) & 0x00000100) >> 8)
2189
2190
#define ALT_CLKMGR_MAINPLL_EN_CFGCLK_SET(value) (((value) << 8) & 0x00000100)
2191
2203
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_LSB 9
2204
2205
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_MSB 9
2206
2207
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_WIDTH 1
2208
2209
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET_MSK 0x00000200
2210
2211
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_CLR_MSK 0xfffffdff
2212
2213
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_RESET 0x1
2214
2215
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_GET(value) (((value) & 0x00000200) >> 9)
2216
2217
#define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLK_SET(value) (((value) << 9) & 0x00000200)
2218
2219
#ifndef __ASSEMBLY__
2220
2230
struct
ALT_CLKMGR_MAINPLL_EN_s
2231
{
2232
uint32_t
l4mainclk
: 1;
2233
uint32_t
l3mpclk
: 1;
2234
uint32_t
l4mpclk
: 1;
2235
uint32_t
l4spclk
: 1;
2236
uint32_t
dbgatclk
: 1;
2237
uint32_t
dbgclk
: 1;
2238
uint32_t
dbgtraceclk
: 1;
2239
uint32_t
dbgtimerclk
: 1;
2240
uint32_t
cfgclk
: 1;
2241
uint32_t
s2fuser0clk
: 1;
2242
uint32_t : 22;
2243
};
2244
2246
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_EN_s
ALT_CLKMGR_MAINPLL_EN_t
;
2247
#endif
/* __ASSEMBLY__ */
2248
2250
#define ALT_CLKMGR_MAINPLL_EN_OFST 0x20
2251
2292
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0
2293
2298
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1
2299
2301
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0
2302
2303
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1
2304
2305
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2
2306
2307
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003
2308
2309
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc
2310
2311
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0
2312
2313
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0)
2314
2315
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003)
2316
2338
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0
2339
2344
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1
2345
2347
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2
2348
2349
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3
2350
2351
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2
2352
2353
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c
2354
2355
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3
2356
2357
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0
2358
2359
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2)
2360
2361
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c)
2362
2390
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0
2391
2396
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1
2397
2402
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2
2403
2408
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3
2409
2414
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4
2415
2420
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5
2421
2426
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6
2427
2432
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7
2433
2435
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4
2436
2437
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6
2438
2439
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3
2440
2441
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070
2442
2443
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f
2444
2445
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0
2446
2447
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET(value) (((value) & 0x00000070) >> 4)
2448
2449
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET(value) (((value) << 4) & 0x00000070)
2450
2478
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0
2479
2484
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1
2485
2490
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2
2491
2496
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3
2497
2502
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4
2503
2508
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5
2509
2514
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6
2515
2520
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7
2521
2523
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7
2524
2525
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9
2526
2527
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3
2528
2529
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380
2530
2531
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f
2532
2533
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0
2534
2535
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7)
2536
2537
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380)
2538
2539
#ifndef __ASSEMBLY__
2540
2550
struct
ALT_CLKMGR_MAINPLL_MAINDIV_s
2551
{
2552
uint32_t
l3mpclk
: 2;
2553
uint32_t
l3spclk
: 2;
2554
uint32_t
l4mpclk
: 3;
2555
uint32_t
l4spclk
: 3;
2556
uint32_t : 22;
2557
};
2558
2560
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_MAINDIV_s
ALT_CLKMGR_MAINPLL_MAINDIV_t
;
2561
#endif
/* __ASSEMBLY__ */
2562
2564
#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24
2565
2605
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0
2606
2611
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1
2612
2617
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2
2618
2620
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0
2621
2622
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1
2623
2624
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2
2625
2626
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003
2627
2628
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc
2629
2630
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0
2631
2632
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET(value) (((value) & 0x00000003) >> 0)
2633
2634
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET(value) (((value) << 0) & 0x00000003)
2635
2657
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1
2658
2663
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2
2664
2666
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2
2667
2668
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3
2669
2670
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2
2671
2672
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c
2673
2674
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3
2675
2676
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1
2677
2678
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2)
2679
2680
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c)
2681
2682
#ifndef __ASSEMBLY__
2683
2693
struct
ALT_CLKMGR_MAINPLL_DBGDIV_s
2694
{
2695
uint32_t
dbgatclk
: 2;
2696
uint32_t
dbgclk
: 2;
2697
uint32_t : 28;
2698
};
2699
2701
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_DBGDIV_s
ALT_CLKMGR_MAINPLL_DBGDIV_t
;
2702
#endif
/* __ASSEMBLY__ */
2703
2705
#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28
2706
2750
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV1 0x0
2751
2756
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV2 0x1
2757
2762
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV4 0x2
2763
2768
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV8 0x3
2769
2774
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_DIV16 0x4
2775
2780
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_1 0x5
2781
2786
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_2 0x6
2787
2792
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_E_RSVD_3 0x7
2793
2795
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_LSB 0
2796
2797
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_MSB 2
2798
2799
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_WIDTH 3
2800
2801
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET_MSK 0x00000007
2802
2803
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_CLR_MSK 0xfffffff8
2804
2805
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_RESET 0x0
2806
2807
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_GET(value) (((value) & 0x00000007) >> 0)
2808
2809
#define ALT_CLKMGR_MAINPLL_TRACEDIV_TRACECLK_SET(value) (((value) << 0) & 0x00000007)
2810
2811
#ifndef __ASSEMBLY__
2812
2822
struct
ALT_CLKMGR_MAINPLL_TRACEDIV_s
2823
{
2824
uint32_t
traceclk
: 3;
2825
uint32_t : 29;
2826
};
2827
2829
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_TRACEDIV_s
ALT_CLKMGR_MAINPLL_TRACEDIV_t
;
2830
#endif
/* __ASSEMBLY__ */
2831
2833
#define ALT_CLKMGR_MAINPLL_TRACEDIV_OFST 0x2c
2834
2871
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0
2872
2877
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1
2878
2880
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB 0
2881
2882
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB 0
2883
2884
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH 1
2885
2886
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK 0x00000001
2887
2888
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK 0xfffffffe
2889
2890
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET 0x0
2891
2892
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value) (((value) & 0x00000001) >> 0)
2893
2894
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value) (((value) << 0) & 0x00000001)
2895
2916
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0
2917
2922
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1
2923
2925
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB 1
2926
2927
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB 1
2928
2929
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH 1
2930
2931
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK 0x00000002
2932
2933
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK 0xfffffffd
2934
2935
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET 0x0
2936
2937
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value) (((value) & 0x00000002) >> 1)
2938
2939
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value) (((value) << 1) & 0x00000002)
2940
2941
#ifndef __ASSEMBLY__
2942
2952
struct
ALT_CLKMGR_MAINPLL_L4SRC_s
2953
{
2954
uint32_t
l4mp
: 1;
2955
uint32_t
l4sp
: 1;
2956
uint32_t : 30;
2957
};
2958
2960
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_L4SRC_s
ALT_CLKMGR_MAINPLL_L4SRC_t
;
2961
#endif
/* __ASSEMBLY__ */
2962
2964
#define ALT_CLKMGR_MAINPLL_L4SRC_OFST 0x30
2965
3011
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_IDLE 0x0
3012
3017
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
3018
3020
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_LSB 0
3021
3022
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_MSB 5
3023
3024
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_WIDTH 6
3025
3026
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
3027
3028
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
3029
3030
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_RESET 0x0
3031
3032
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
3033
3034
#define ALT_CLKMGR_MAINPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
3035
3036
#ifndef __ASSEMBLY__
3037
3047
struct
ALT_CLKMGR_MAINPLL_STAT_s
3048
{
3049
const
uint32_t
outresetack
: 6;
3050
uint32_t : 26;
3051
};
3052
3054
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_STAT_s
ALT_CLKMGR_MAINPLL_STAT_t
;
3055
#endif
/* __ASSEMBLY__ */
3056
3058
#define ALT_CLKMGR_MAINPLL_STAT_OFST 0x34
3059
3060
#ifndef __ASSEMBLY__
3061
3071
struct
ALT_CLKMGR_MAINPLL_s
3072
{
3073
volatile
ALT_CLKMGR_MAINPLL_VCO_t
vco
;
3074
volatile
ALT_CLKMGR_MAINPLL_MISC_t
misc
;
3075
volatile
ALT_CLKMGR_MAINPLL_MPUCLK_t
mpuclk
;
3076
volatile
ALT_CLKMGR_MAINPLL_MAINCLK_t
mainclk
;
3077
volatile
ALT_CLKMGR_MAINPLL_DBGATCLK_t
dbgatclk
;
3078
volatile
ALT_CLKMGR_MAINPLL_MAINQSPICLK_t
mainqspiclk
;
3079
volatile
ALT_CLKMGR_MAINPLL_MAINNANDSDMMCCLK_t
mainnandsdmmcclk
;
3080
volatile
ALT_CLKMGR_MAINPLL_CFGS2FUSER0CLK_t
cfgs2fuser0clk
;
3081
volatile
ALT_CLKMGR_MAINPLL_EN_t
en
;
3082
volatile
ALT_CLKMGR_MAINPLL_MAINDIV_t
maindiv
;
3083
volatile
ALT_CLKMGR_MAINPLL_DBGDIV_t
dbgdiv
;
3084
volatile
ALT_CLKMGR_MAINPLL_TRACEDIV_t
tracediv
;
3085
volatile
ALT_CLKMGR_MAINPLL_L4SRC_t
l4src
;
3086
volatile
ALT_CLKMGR_MAINPLL_STAT_t
stat
;
3087
volatile
uint32_t
_pad_0x38_0x40
[2];
3088
};
3089
3091
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_s
ALT_CLKMGR_MAINPLL_t
;
3093
struct
ALT_CLKMGR_MAINPLL_raw_s
3094
{
3095
volatile
uint32_t
vco
;
3096
volatile
uint32_t
misc
;
3097
volatile
uint32_t
mpuclk
;
3098
volatile
uint32_t
mainclk
;
3099
volatile
uint32_t
dbgatclk
;
3100
volatile
uint32_t
mainqspiclk
;
3101
volatile
uint32_t
mainnandsdmmcclk
;
3102
volatile
uint32_t
cfgs2fuser0clk
;
3103
volatile
uint32_t
en
;
3104
volatile
uint32_t
maindiv
;
3105
volatile
uint32_t
dbgdiv
;
3106
volatile
uint32_t
tracediv
;
3107
volatile
uint32_t
l4src
;
3108
volatile
uint32_t
stat
;
3109
volatile
uint32_t
_pad_0x38_0x40
[2];
3110
};
3111
3113
typedef
volatile
struct
ALT_CLKMGR_MAINPLL_raw_s
ALT_CLKMGR_MAINPLL_raw_t
;
3114
#endif
/* __ASSEMBLY__ */
3115
3157
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_LSB 0
3158
3159
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_MSB 0
3160
3161
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_WIDTH 1
3162
3163
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET_MSK 0x00000001
3164
3165
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
3166
3167
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_RESET 0x1
3168
3169
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
3170
3171
#define ALT_CLKMGR_PERPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
3172
3182
#define ALT_CLKMGR_PERPLL_VCO_EN_LSB 1
3183
3184
#define ALT_CLKMGR_PERPLL_VCO_EN_MSB 1
3185
3186
#define ALT_CLKMGR_PERPLL_VCO_EN_WIDTH 1
3187
3188
#define ALT_CLKMGR_PERPLL_VCO_EN_SET_MSK 0x00000002
3189
3190
#define ALT_CLKMGR_PERPLL_VCO_EN_CLR_MSK 0xfffffffd
3191
3192
#define ALT_CLKMGR_PERPLL_VCO_EN_RESET 0x0
3193
3194
#define ALT_CLKMGR_PERPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
3195
3196
#define ALT_CLKMGR_PERPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
3197
3207
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_LSB 2
3208
3209
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_MSB 2
3210
3211
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_WIDTH 1
3212
3213
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET_MSK 0x00000004
3214
3215
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
3216
3217
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_RESET 0x1
3218
3219
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
3220
3221
#define ALT_CLKMGR_PERPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
3222
3235
#define ALT_CLKMGR_PERPLL_VCO_NUMER_LSB 3
3236
3237
#define ALT_CLKMGR_PERPLL_VCO_NUMER_MSB 15
3238
3239
#define ALT_CLKMGR_PERPLL_VCO_NUMER_WIDTH 13
3240
3241
#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET_MSK 0x0000fff8
3242
3243
#define ALT_CLKMGR_PERPLL_VCO_NUMER_CLR_MSK 0xffff0007
3244
3245
#define ALT_CLKMGR_PERPLL_VCO_NUMER_RESET 0x1
3246
3247
#define ALT_CLKMGR_PERPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
3248
3249
#define ALT_CLKMGR_PERPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
3250
3263
#define ALT_CLKMGR_PERPLL_VCO_DENOM_LSB 16
3264
3265
#define ALT_CLKMGR_PERPLL_VCO_DENOM_MSB 21
3266
3267
#define ALT_CLKMGR_PERPLL_VCO_DENOM_WIDTH 6
3268
3269
#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET_MSK 0x003f0000
3270
3271
#define ALT_CLKMGR_PERPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
3272
3273
#define ALT_CLKMGR_PERPLL_VCO_DENOM_RESET 0x1
3274
3275
#define ALT_CLKMGR_PERPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
3276
3277
#define ALT_CLKMGR_PERPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
3278
3302
#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC1 0x0
3303
3308
#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_EOSC2 0x1
3309
3314
#define ALT_CLKMGR_PERPLL_VCO_PSRC_E_F2S_PERIPH_REF 0x2
3315
3317
#define ALT_CLKMGR_PERPLL_VCO_PSRC_LSB 22
3318
3319
#define ALT_CLKMGR_PERPLL_VCO_PSRC_MSB 23
3320
3321
#define ALT_CLKMGR_PERPLL_VCO_PSRC_WIDTH 2
3322
3323
#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET_MSK 0x00c00000
3324
3325
#define ALT_CLKMGR_PERPLL_VCO_PSRC_CLR_MSK 0xff3fffff
3326
3327
#define ALT_CLKMGR_PERPLL_VCO_PSRC_RESET 0x0
3328
3329
#define ALT_CLKMGR_PERPLL_VCO_PSRC_GET(value) (((value) & 0x00c00000) >> 22)
3330
3331
#define ALT_CLKMGR_PERPLL_VCO_PSRC_SET(value) (((value) << 22) & 0x00c00000)
3332
3349
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_LSB 24
3350
3351
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_MSB 24
3352
3353
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_WIDTH 1
3354
3355
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
3356
3357
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
3358
3359
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_RESET 0x0
3360
3361
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
3362
3363
#define ALT_CLKMGR_PERPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
3364
3390
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_LSB 25
3391
3392
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_MSB 30
3393
3394
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_WIDTH 6
3395
3396
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET_MSK 0x7e000000
3397
3398
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
3399
3400
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_RESET 0x0
3401
3402
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
3403
3404
#define ALT_CLKMGR_PERPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
3405
3427
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_LSB 31
3428
3429
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_MSB 31
3430
3431
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_WIDTH 1
3432
3433
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
3434
3435
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
3436
3437
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_RESET 0x1
3438
3439
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
3440
3441
#define ALT_CLKMGR_PERPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
3442
3443
#ifndef __ASSEMBLY__
3444
3454
struct
ALT_CLKMGR_PERPLL_VCO_s
3455
{
3456
uint32_t
bgpwrdn
: 1;
3457
uint32_t
en
: 1;
3458
uint32_t
pwrdn
: 1;
3459
uint32_t
numer
: 13;
3460
uint32_t
denom
: 6;
3461
uint32_t
psrc
: 2;
3462
uint32_t
outresetall
: 1;
3463
uint32_t
outreset
: 6;
3464
uint32_t
regextsel
: 1;
3465
};
3466
3468
typedef
volatile
struct
ALT_CLKMGR_PERPLL_VCO_s
ALT_CLKMGR_PERPLL_VCO_t
;
3469
#endif
/* __ASSEMBLY__ */
3470
3472
#define ALT_CLKMGR_PERPLL_VCO_OFST 0x0
3473
3507
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_LSB 0
3508
3509
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_MSB 0
3510
3511
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_WIDTH 1
3512
3513
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET_MSK 0x00000001
3514
3515
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_CLR_MSK 0xfffffffe
3516
3517
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_RESET 0x0
3518
3519
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
3520
3521
#define ALT_CLKMGR_PERPLL_MISC_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
3522
3532
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_LSB 1
3533
3534
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_MSB 12
3535
3536
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_WIDTH 12
3537
3538
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET_MSK 0x00001ffe
3539
3540
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_CLR_MSK 0xffffe001
3541
3542
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_RESET 0x1
3543
3544
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
3545
3546
#define ALT_CLKMGR_PERPLL_MISC_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
3547
3557
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_LSB 13
3558
3559
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_MSB 13
3560
3561
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_WIDTH 1
3562
3563
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET_MSK 0x00002000
3564
3565
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_CLR_MSK 0xffffdfff
3566
3567
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_RESET 0x0
3568
3569
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
3570
3571
#define ALT_CLKMGR_PERPLL_MISC_FASTEN_SET(value) (((value) << 13) & 0x00002000)
3572
3582
#define ALT_CLKMGR_PERPLL_MISC_SATEN_LSB 14
3583
3584
#define ALT_CLKMGR_PERPLL_MISC_SATEN_MSB 14
3585
3586
#define ALT_CLKMGR_PERPLL_MISC_SATEN_WIDTH 1
3587
3588
#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET_MSK 0x00004000
3589
3590
#define ALT_CLKMGR_PERPLL_MISC_SATEN_CLR_MSK 0xffffbfff
3591
3592
#define ALT_CLKMGR_PERPLL_MISC_SATEN_RESET 0x1
3593
3594
#define ALT_CLKMGR_PERPLL_MISC_SATEN_GET(value) (((value) & 0x00004000) >> 14)
3595
3596
#define ALT_CLKMGR_PERPLL_MISC_SATEN_SET(value) (((value) << 14) & 0x00004000)
3597
3598
#ifndef __ASSEMBLY__
3599
3609
struct
ALT_CLKMGR_PERPLL_MISC_s
3610
{
3611
uint32_t
bwadjen
: 1;
3612
uint32_t
bwadj
: 12;
3613
uint32_t
fasten
: 1;
3614
uint32_t
saten
: 1;
3615
uint32_t : 17;
3616
};
3617
3619
typedef
volatile
struct
ALT_CLKMGR_PERPLL_MISC_s
ALT_CLKMGR_PERPLL_MISC_t
;
3620
#endif
/* __ASSEMBLY__ */
3621
3623
#define ALT_CLKMGR_PERPLL_MISC_OFST 0x4
3624
3650
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_LSB 0
3651
3652
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_MSB 8
3653
3654
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_WIDTH 9
3655
3656
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET_MSK 0x000001ff
3657
3658
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_CLR_MSK 0xfffffe00
3659
3660
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_RESET 0x1
3661
3662
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3663
3664
#define ALT_CLKMGR_PERPLL_EMAC0CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3665
3666
#ifndef __ASSEMBLY__
3667
3677
struct
ALT_CLKMGR_PERPLL_EMAC0CLK_s
3678
{
3679
uint32_t
cnt
: 9;
3680
uint32_t : 23;
3681
};
3682
3684
typedef
volatile
struct
ALT_CLKMGR_PERPLL_EMAC0CLK_s
ALT_CLKMGR_PERPLL_EMAC0CLK_t
;
3685
#endif
/* __ASSEMBLY__ */
3686
3688
#define ALT_CLKMGR_PERPLL_EMAC0CLK_OFST 0x8
3689
3715
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_LSB 0
3716
3717
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_MSB 8
3718
3719
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_WIDTH 9
3720
3721
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET_MSK 0x000001ff
3722
3723
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_CLR_MSK 0xfffffe00
3724
3725
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_RESET 0x1
3726
3727
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3728
3729
#define ALT_CLKMGR_PERPLL_EMAC1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3730
3731
#ifndef __ASSEMBLY__
3732
3742
struct
ALT_CLKMGR_PERPLL_EMAC1CLK_s
3743
{
3744
uint32_t
cnt
: 9;
3745
uint32_t : 23;
3746
};
3747
3749
typedef
volatile
struct
ALT_CLKMGR_PERPLL_EMAC1CLK_s
ALT_CLKMGR_PERPLL_EMAC1CLK_t
;
3750
#endif
/* __ASSEMBLY__ */
3751
3753
#define ALT_CLKMGR_PERPLL_EMAC1CLK_OFST 0xc
3754
3780
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_LSB 0
3781
3782
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_MSB 8
3783
3784
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_WIDTH 9
3785
3786
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET_MSK 0x000001ff
3787
3788
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_CLR_MSK 0xfffffe00
3789
3790
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_RESET 0x1
3791
3792
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3793
3794
#define ALT_CLKMGR_PERPLL_PERQSPICLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3795
3796
#ifndef __ASSEMBLY__
3797
3807
struct
ALT_CLKMGR_PERPLL_PERQSPICLK_s
3808
{
3809
uint32_t
cnt
: 9;
3810
uint32_t : 23;
3811
};
3812
3814
typedef
volatile
struct
ALT_CLKMGR_PERPLL_PERQSPICLK_s
ALT_CLKMGR_PERPLL_PERQSPICLK_t
;
3815
#endif
/* __ASSEMBLY__ */
3816
3818
#define ALT_CLKMGR_PERPLL_PERQSPICLK_OFST 0x10
3819
3845
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_LSB 0
3846
3847
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_MSB 8
3848
3849
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_WIDTH 9
3850
3851
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET_MSK 0x000001ff
3852
3853
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_CLR_MSK 0xfffffe00
3854
3855
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_RESET 0x1
3856
3857
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3858
3859
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3860
3861
#ifndef __ASSEMBLY__
3862
3872
struct
ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s
3873
{
3874
uint32_t
cnt
: 9;
3875
uint32_t : 23;
3876
};
3877
3879
typedef
volatile
struct
ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_s
ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t
;
3880
#endif
/* __ASSEMBLY__ */
3881
3883
#define ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_OFST 0x14
3884
3910
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_LSB 0
3911
3912
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_MSB 8
3913
3914
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_WIDTH 9
3915
3916
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET_MSK 0x000001ff
3917
3918
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_CLR_MSK 0xfffffe00
3919
3920
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_RESET 0x1
3921
3922
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3923
3924
#define ALT_CLKMGR_PERPLL_PERBASECLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3925
3926
#ifndef __ASSEMBLY__
3927
3937
struct
ALT_CLKMGR_PERPLL_PERBASECLK_s
3938
{
3939
uint32_t
cnt
: 9;
3940
uint32_t : 23;
3941
};
3942
3944
typedef
volatile
struct
ALT_CLKMGR_PERPLL_PERBASECLK_s
ALT_CLKMGR_PERPLL_PERBASECLK_t
;
3945
#endif
/* __ASSEMBLY__ */
3946
3948
#define ALT_CLKMGR_PERPLL_PERBASECLK_OFST 0x18
3949
3977
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_LSB 0
3978
3979
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_MSB 8
3980
3981
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_WIDTH 9
3982
3983
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET_MSK 0x000001ff
3984
3985
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_CLR_MSK 0xfffffe00
3986
3987
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_RESET 0x1
3988
3989
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
3990
3991
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
3992
3993
#ifndef __ASSEMBLY__
3994
4004
struct
ALT_CLKMGR_PERPLL_S2FUSER1CLK_s
4005
{
4006
uint32_t
cnt
: 9;
4007
uint32_t : 23;
4008
};
4009
4011
typedef
volatile
struct
ALT_CLKMGR_PERPLL_S2FUSER1CLK_s
ALT_CLKMGR_PERPLL_S2FUSER1CLK_t
;
4012
#endif
/* __ASSEMBLY__ */
4013
4015
#define ALT_CLKMGR_PERPLL_S2FUSER1CLK_OFST 0x1c
4016
4057
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_LSB 0
4058
4059
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_MSB 0
4060
4061
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_WIDTH 1
4062
4063
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET_MSK 0x00000001
4064
4065
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_CLR_MSK 0xfffffffe
4066
4067
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_RESET 0x1
4068
4069
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_GET(value) (((value) & 0x00000001) >> 0)
4070
4071
#define ALT_CLKMGR_PERPLL_EN_EMAC0CLK_SET(value) (((value) << 0) & 0x00000001)
4072
4082
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_LSB 1
4083
4084
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_MSB 1
4085
4086
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_WIDTH 1
4087
4088
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET_MSK 0x00000002
4089
4090
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_CLR_MSK 0xfffffffd
4091
4092
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_RESET 0x1
4093
4094
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_GET(value) (((value) & 0x00000002) >> 1)
4095
4096
#define ALT_CLKMGR_PERPLL_EN_EMAC1CLK_SET(value) (((value) << 1) & 0x00000002)
4097
4107
#define ALT_CLKMGR_PERPLL_EN_USBCLK_LSB 2
4108
4109
#define ALT_CLKMGR_PERPLL_EN_USBCLK_MSB 2
4110
4111
#define ALT_CLKMGR_PERPLL_EN_USBCLK_WIDTH 1
4112
4113
#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET_MSK 0x00000004
4114
4115
#define ALT_CLKMGR_PERPLL_EN_USBCLK_CLR_MSK 0xfffffffb
4116
4117
#define ALT_CLKMGR_PERPLL_EN_USBCLK_RESET 0x1
4118
4119
#define ALT_CLKMGR_PERPLL_EN_USBCLK_GET(value) (((value) & 0x00000004) >> 2)
4120
4121
#define ALT_CLKMGR_PERPLL_EN_USBCLK_SET(value) (((value) << 2) & 0x00000004)
4122
4132
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_LSB 3
4133
4134
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_MSB 3
4135
4136
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_WIDTH 1
4137
4138
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET_MSK 0x00000008
4139
4140
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_CLR_MSK 0xfffffff7
4141
4142
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_RESET 0x1
4143
4144
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_GET(value) (((value) & 0x00000008) >> 3)
4145
4146
#define ALT_CLKMGR_PERPLL_EN_SPIMCLK_SET(value) (((value) << 3) & 0x00000008)
4147
4157
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_LSB 4
4158
4159
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_MSB 4
4160
4161
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_WIDTH 1
4162
4163
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET_MSK 0x00000010
4164
4165
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_CLR_MSK 0xffffffef
4166
4167
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_RESET 0x1
4168
4169
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_GET(value) (((value) & 0x00000010) >> 4)
4170
4171
#define ALT_CLKMGR_PERPLL_EN_CAN0CLK_SET(value) (((value) << 4) & 0x00000010)
4172
4182
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_LSB 5
4183
4184
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_MSB 5
4185
4186
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_WIDTH 1
4187
4188
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET_MSK 0x00000020
4189
4190
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_CLR_MSK 0xffffffdf
4191
4192
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_RESET 0x1
4193
4194
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_GET(value) (((value) & 0x00000020) >> 5)
4195
4196
#define ALT_CLKMGR_PERPLL_EN_CAN1CLK_SET(value) (((value) << 5) & 0x00000020)
4197
4207
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_LSB 6
4208
4209
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_MSB 6
4210
4211
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_WIDTH 1
4212
4213
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET_MSK 0x00000040
4214
4215
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_CLR_MSK 0xffffffbf
4216
4217
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_RESET 0x1
4218
4219
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_GET(value) (((value) & 0x00000040) >> 6)
4220
4221
#define ALT_CLKMGR_PERPLL_EN_GPIOCLK_SET(value) (((value) << 6) & 0x00000040)
4222
4234
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_LSB 7
4235
4236
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_MSB 7
4237
4238
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_WIDTH 1
4239
4240
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET_MSK 0x00000080
4241
4242
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_CLR_MSK 0xffffff7f
4243
4244
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_RESET 0x1
4245
4246
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_GET(value) (((value) & 0x00000080) >> 7)
4247
4248
#define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLK_SET(value) (((value) << 7) & 0x00000080)
4249
4259
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_LSB 8
4260
4261
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_MSB 8
4262
4263
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_WIDTH 1
4264
4265
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET_MSK 0x00000100
4266
4267
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_CLR_MSK 0xfffffeff
4268
4269
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_RESET 0x1
4270
4271
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_GET(value) (((value) & 0x00000100) >> 8)
4272
4273
#define ALT_CLKMGR_PERPLL_EN_SDMMCCLK_SET(value) (((value) << 8) & 0x00000100)
4274
4289
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_LSB 9
4290
4291
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_MSB 9
4292
4293
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_WIDTH 1
4294
4295
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET_MSK 0x00000200
4296
4297
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_CLR_MSK 0xfffffdff
4298
4299
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_RESET 0x1
4300
4301
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_GET(value) (((value) & 0x00000200) >> 9)
4302
4303
#define ALT_CLKMGR_PERPLL_EN_NANDXCLK_SET(value) (((value) << 9) & 0x00000200)
4304
4319
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_LSB 10
4320
4321
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_MSB 10
4322
4323
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_WIDTH 1
4324
4325
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET_MSK 0x00000400
4326
4327
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_CLR_MSK 0xfffffbff
4328
4329
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_RESET 0x1
4330
4331
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_GET(value) (((value) & 0x00000400) >> 10)
4332
4333
#define ALT_CLKMGR_PERPLL_EN_NANDCLK_SET(value) (((value) << 10) & 0x00000400)
4334
4344
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_LSB 11
4345
4346
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_MSB 11
4347
4348
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_WIDTH 1
4349
4350
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET_MSK 0x00000800
4351
4352
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_CLR_MSK 0xfffff7ff
4353
4354
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_RESET 0x1
4355
4356
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_GET(value) (((value) & 0x00000800) >> 11)
4357
4358
#define ALT_CLKMGR_PERPLL_EN_QSPICLK_SET(value) (((value) << 11) & 0x00000800)
4359
4360
#ifndef __ASSEMBLY__
4361
4371
struct
ALT_CLKMGR_PERPLL_EN_s
4372
{
4373
uint32_t
emac0clk
: 1;
4374
uint32_t
emac1clk
: 1;
4375
uint32_t
usbclk
: 1;
4376
uint32_t
spimclk
: 1;
4377
uint32_t
can0clk
: 1;
4378
uint32_t
can1clk
: 1;
4379
uint32_t
gpioclk
: 1;
4380
uint32_t
s2fuser1clk
: 1;
4381
uint32_t
sdmmcclk
: 1;
4382
uint32_t
nandxclk
: 1;
4383
uint32_t
nandclk
: 1;
4384
uint32_t
qspiclk
: 1;
4385
uint32_t : 20;
4386
};
4387
4389
typedef
volatile
struct
ALT_CLKMGR_PERPLL_EN_s
ALT_CLKMGR_PERPLL_EN_t
;
4390
#endif
/* __ASSEMBLY__ */
4391
4393
#define ALT_CLKMGR_PERPLL_EN_OFST 0x20
4394
4441
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0
4442
4447
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1
4448
4453
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2
4454
4459
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3
4460
4465
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4
4466
4471
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5
4472
4477
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6
4478
4483
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7
4484
4486
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0
4487
4488
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2
4489
4490
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3
4491
4492
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007
4493
4494
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8
4495
4496
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0
4497
4498
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET(value) (((value) & 0x00000007) >> 0)
4499
4500
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET(value) (((value) << 0) & 0x00000007)
4501
4529
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0
4530
4535
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1
4536
4541
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2
4542
4547
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3
4548
4553
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4
4554
4559
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5
4560
4565
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6
4566
4571
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7
4572
4574
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3
4575
4576
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5
4577
4578
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3
4579
4580
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038
4581
4582
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7
4583
4584
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0
4585
4586
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3)
4587
4588
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038)
4589
4617
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0
4618
4623
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1
4624
4629
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2
4630
4635
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3
4636
4641
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4
4642
4647
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5
4648
4653
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6
4654
4659
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7
4660
4662
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6
4663
4664
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8
4665
4666
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3
4667
4668
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0
4669
4670
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f
4671
4672
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0
4673
4674
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6)
4675
4676
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0)
4677
4705
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0
4706
4711
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1
4712
4717
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2
4718
4723
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3
4724
4729
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4
4730
4735
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5
4736
4741
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6
4742
4747
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7
4748
4750
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9
4751
4752
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11
4753
4754
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3
4755
4756
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00
4757
4758
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff
4759
4760
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0
4761
4762
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9)
4763
4764
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00)
4765
4766
#ifndef __ASSEMBLY__
4767
4777
struct
ALT_CLKMGR_PERPLL_DIV_s
4778
{
4779
uint32_t
usbclk
: 3;
4780
uint32_t
spimclk
: 3;
4781
uint32_t
can0clk
: 3;
4782
uint32_t
can1clk
: 3;
4783
uint32_t : 20;
4784
};
4785
4787
typedef
volatile
struct
ALT_CLKMGR_PERPLL_DIV_s
ALT_CLKMGR_PERPLL_DIV_t
;
4788
#endif
/* __ASSEMBLY__ */
4789
4791
#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24
4792
4819
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
4820
4821
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 23
4822
4823
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 24
4824
4825
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x00ffffff
4826
4827
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xff000000
4828
4829
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
4830
4831
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x00ffffff) >> 0)
4832
4833
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x00ffffff)
4834
4835
#ifndef __ASSEMBLY__
4836
4846
struct
ALT_CLKMGR_PERPLL_GPIODIV_s
4847
{
4848
uint32_t
gpiodbclk
: 24;
4849
uint32_t : 8;
4850
};
4851
4853
typedef
volatile
struct
ALT_CLKMGR_PERPLL_GPIODIV_s
ALT_CLKMGR_PERPLL_GPIODIV_t
;
4854
#endif
/* __ASSEMBLY__ */
4855
4857
#define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x28
4858
4899
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0
4900
4905
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1
4906
4911
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2
4912
4914
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB 0
4915
4916
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB 1
4917
4918
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH 2
4919
4920
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK 0x00000003
4921
4922
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK 0xfffffffc
4923
4924
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET 0x1
4925
4926
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value) (((value) & 0x00000003) >> 0)
4927
4928
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value) (((value) << 0) & 0x00000003)
4929
4953
#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0
4954
4959
#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1
4960
4965
#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2
4966
4968
#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB 2
4969
4970
#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB 3
4971
4972
#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH 2
4973
4974
#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK 0x0000000c
4975
4976
#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK 0xfffffff3
4977
4978
#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET 0x1
4979
4980
#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value) (((value) & 0x0000000c) >> 2)
4981
4982
#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value) (((value) << 2) & 0x0000000c)
4983
5007
#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0
5008
5013
#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1
5014
5019
#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2
5020
5022
#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB 4
5023
5024
#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB 5
5025
5026
#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH 2
5027
5028
#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK 0x00000030
5029
5030
#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK 0xffffffcf
5031
5032
#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET 0x1
5033
5034
#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value) (((value) & 0x00000030) >> 4)
5035
5036
#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value) (((value) << 4) & 0x00000030)
5037
5038
#ifndef __ASSEMBLY__
5039
5049
struct
ALT_CLKMGR_PERPLL_SRC_s
5050
{
5051
uint32_t
sdmmc
: 2;
5052
uint32_t
nand
: 2;
5053
uint32_t
qspi
: 2;
5054
uint32_t : 26;
5055
};
5056
5058
typedef
volatile
struct
ALT_CLKMGR_PERPLL_SRC_s
ALT_CLKMGR_PERPLL_SRC_t
;
5059
#endif
/* __ASSEMBLY__ */
5060
5062
#define ALT_CLKMGR_PERPLL_SRC_OFST 0x2c
5063
5109
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_IDLE 0x0
5110
5115
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
5116
5118
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_LSB 0
5119
5120
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_MSB 5
5121
5122
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_WIDTH 6
5123
5124
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
5125
5126
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
5127
5128
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_RESET 0x0
5129
5130
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
5131
5132
#define ALT_CLKMGR_PERPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
5133
5134
#ifndef __ASSEMBLY__
5135
5145
struct
ALT_CLKMGR_PERPLL_STAT_s
5146
{
5147
const
uint32_t
outresetack
: 6;
5148
uint32_t : 26;
5149
};
5150
5152
typedef
volatile
struct
ALT_CLKMGR_PERPLL_STAT_s
ALT_CLKMGR_PERPLL_STAT_t
;
5153
#endif
/* __ASSEMBLY__ */
5154
5156
#define ALT_CLKMGR_PERPLL_STAT_OFST 0x30
5157
5158
#ifndef __ASSEMBLY__
5159
5169
struct
ALT_CLKMGR_PERPLL_s
5170
{
5171
volatile
ALT_CLKMGR_PERPLL_VCO_t
vco
;
5172
volatile
ALT_CLKMGR_PERPLL_MISC_t
misc
;
5173
volatile
ALT_CLKMGR_PERPLL_EMAC0CLK_t
emac0clk
;
5174
volatile
ALT_CLKMGR_PERPLL_EMAC1CLK_t
emac1clk
;
5175
volatile
ALT_CLKMGR_PERPLL_PERQSPICLK_t
perqspiclk
;
5176
volatile
ALT_CLKMGR_PERPLL_PERNANDSDMMCCLK_t
pernandsdmmcclk
;
5177
volatile
ALT_CLKMGR_PERPLL_PERBASECLK_t
perbaseclk
;
5178
volatile
ALT_CLKMGR_PERPLL_S2FUSER1CLK_t
s2fuser1clk
;
5179
volatile
ALT_CLKMGR_PERPLL_EN_t
en
;
5180
volatile
ALT_CLKMGR_PERPLL_DIV_t
div
;
5181
volatile
ALT_CLKMGR_PERPLL_GPIODIV_t
gpiodiv
;
5182
volatile
ALT_CLKMGR_PERPLL_SRC_t
src
;
5183
volatile
ALT_CLKMGR_PERPLL_STAT_t
stat
;
5184
volatile
uint32_t
_pad_0x34_0x40
[3];
5185
};
5186
5188
typedef
volatile
struct
ALT_CLKMGR_PERPLL_s
ALT_CLKMGR_PERPLL_t
;
5190
struct
ALT_CLKMGR_PERPLL_raw_s
5191
{
5192
volatile
uint32_t
vco
;
5193
volatile
uint32_t
misc
;
5194
volatile
uint32_t
emac0clk
;
5195
volatile
uint32_t
emac1clk
;
5196
volatile
uint32_t
perqspiclk
;
5197
volatile
uint32_t
pernandsdmmcclk
;
5198
volatile
uint32_t
perbaseclk
;
5199
volatile
uint32_t
s2fuser1clk
;
5200
volatile
uint32_t
en
;
5201
volatile
uint32_t
div
;
5202
volatile
uint32_t
gpiodiv
;
5203
volatile
uint32_t
src
;
5204
volatile
uint32_t
stat
;
5205
volatile
uint32_t
_pad_0x34_0x40
[3];
5206
};
5207
5209
typedef
volatile
struct
ALT_CLKMGR_PERPLL_raw_s
ALT_CLKMGR_PERPLL_raw_t
;
5210
#endif
/* __ASSEMBLY__ */
5211
5253
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0
5254
5255
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0
5256
5257
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1
5258
5259
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001
5260
5261
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe
5262
5263
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1
5264
5265
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5266
5267
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5268
5278
#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1
5279
5280
#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1
5281
5282
#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1
5283
5284
#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002
5285
5286
#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd
5287
5288
#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0
5289
5290
#define ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1)
5291
5292
#define ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002)
5293
5303
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2
5304
5305
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2
5306
5307
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1
5308
5309
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004
5310
5311
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb
5312
5313
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1
5314
5315
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2)
5316
5317
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004)
5318
5331
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3
5332
5333
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15
5334
5335
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13
5336
5337
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8
5338
5339
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007
5340
5341
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1
5342
5343
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3)
5344
5345
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8)
5346
5359
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16
5360
5361
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21
5362
5363
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6
5364
5365
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000
5366
5367
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff
5368
5369
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1
5370
5371
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
5372
5373
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000)
5374
5399
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0
5400
5405
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1
5406
5411
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2
5412
5414
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22
5415
5416
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23
5417
5418
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2
5419
5420
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000
5421
5422
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff
5423
5424
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0
5425
5426
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22)
5427
5428
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000)
5429
5446
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24
5447
5448
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24
5449
5450
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1
5451
5452
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000
5453
5454
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff
5455
5456
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0
5457
5458
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24)
5459
5460
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000)
5461
5487
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25
5488
5489
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30
5490
5491
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6
5492
5493
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000
5494
5495
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff
5496
5497
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0
5498
5499
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25)
5500
5501
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000)
5502
5524
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31
5525
5526
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31
5527
5528
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1
5529
5530
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000
5531
5532
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff
5533
5534
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1
5535
5536
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31)
5537
5538
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000)
5539
5540
#ifndef __ASSEMBLY__
5541
5551
struct
ALT_CLKMGR_SDRPLL_VCO_s
5552
{
5553
uint32_t
bgpwrdn
: 1;
5554
uint32_t
en
: 1;
5555
uint32_t
pwrdn
: 1;
5556
uint32_t
numer
: 13;
5557
uint32_t
denom
: 6;
5558
uint32_t
ssrc
: 2;
5559
uint32_t
outresetall
: 1;
5560
uint32_t
outreset
: 6;
5561
uint32_t
regextsel
: 1;
5562
};
5563
5565
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_VCO_s
ALT_CLKMGR_SDRPLL_VCO_t
;
5566
#endif
/* __ASSEMBLY__ */
5567
5569
#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0
5570
5604
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_LSB 0
5605
5606
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_MSB 0
5607
5608
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_WIDTH 1
5609
5610
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET_MSK 0x00000001
5611
5612
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_CLR_MSK 0xfffffffe
5613
5614
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_RESET 0x0
5615
5616
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_GET(value) (((value) & 0x00000001) >> 0)
5617
5618
#define ALT_CLKMGR_SDRPLL_CTL_BWADJEN_SET(value) (((value) << 0) & 0x00000001)
5619
5629
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_LSB 1
5630
5631
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_MSB 12
5632
5633
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_WIDTH 12
5634
5635
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET_MSK 0x00001ffe
5636
5637
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_CLR_MSK 0xffffe001
5638
5639
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_RESET 0x1
5640
5641
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_GET(value) (((value) & 0x00001ffe) >> 1)
5642
5643
#define ALT_CLKMGR_SDRPLL_CTL_BWADJ_SET(value) (((value) << 1) & 0x00001ffe)
5644
5654
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_LSB 13
5655
5656
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_MSB 13
5657
5658
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_WIDTH 1
5659
5660
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET_MSK 0x00002000
5661
5662
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_CLR_MSK 0xffffdfff
5663
5664
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_RESET 0x0
5665
5666
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_GET(value) (((value) & 0x00002000) >> 13)
5667
5668
#define ALT_CLKMGR_SDRPLL_CTL_FASTEN_SET(value) (((value) << 13) & 0x00002000)
5669
5679
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_LSB 14
5680
5681
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_MSB 14
5682
5683
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_WIDTH 1
5684
5685
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET_MSK 0x00004000
5686
5687
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_CLR_MSK 0xffffbfff
5688
5689
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_RESET 0x1
5690
5691
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_GET(value) (((value) & 0x00004000) >> 14)
5692
5693
#define ALT_CLKMGR_SDRPLL_CTL_SATEN_SET(value) (((value) << 14) & 0x00004000)
5694
5695
#ifndef __ASSEMBLY__
5696
5706
struct
ALT_CLKMGR_SDRPLL_CTL_s
5707
{
5708
uint32_t
bwadjen
: 1;
5709
uint32_t
bwadj
: 12;
5710
uint32_t
fasten
: 1;
5711
uint32_t
saten
: 1;
5712
uint32_t : 17;
5713
};
5714
5716
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_CTL_s
ALT_CLKMGR_SDRPLL_CTL_t
;
5717
#endif
/* __ASSEMBLY__ */
5718
5720
#define ALT_CLKMGR_SDRPLL_CTL_OFST 0x4
5721
5748
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_LSB 0
5749
5750
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_MSB 8
5751
5752
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_WIDTH 9
5753
5754
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET_MSK 0x000001ff
5755
5756
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_CLR_MSK 0xfffffe00
5757
5758
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_RESET 0x1
5759
5760
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5761
5762
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5763
5781
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_LSB 9
5782
5783
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_MSB 20
5784
5785
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_WIDTH 12
5786
5787
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET_MSK 0x001ffe00
5788
5789
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_CLR_MSK 0xffe001ff
5790
5791
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_RESET 0x0
5792
5793
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5794
5795
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5796
5797
#ifndef __ASSEMBLY__
5798
5808
struct
ALT_CLKMGR_SDRPLL_DDRDQSCLK_s
5809
{
5810
uint32_t
cnt
: 9;
5811
uint32_t
phase
: 12;
5812
uint32_t : 11;
5813
};
5814
5816
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_DDRDQSCLK_s
ALT_CLKMGR_SDRPLL_DDRDQSCLK_t
;
5817
#endif
/* __ASSEMBLY__ */
5818
5820
#define ALT_CLKMGR_SDRPLL_DDRDQSCLK_OFST 0x8
5821
5848
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_LSB 0
5849
5850
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_MSB 8
5851
5852
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_WIDTH 9
5853
5854
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET_MSK 0x000001ff
5855
5856
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_CLR_MSK 0xfffffe00
5857
5858
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_RESET 0x1
5859
5860
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5861
5862
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5863
5881
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_LSB 9
5882
5883
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_MSB 20
5884
5885
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_WIDTH 12
5886
5887
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET_MSK 0x001ffe00
5888
5889
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_CLR_MSK 0xffe001ff
5890
5891
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_RESET 0x0
5892
5893
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5894
5895
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5896
5897
#ifndef __ASSEMBLY__
5898
5908
struct
ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s
5909
{
5910
uint32_t
cnt
: 9;
5911
uint32_t
phase
: 12;
5912
uint32_t : 11;
5913
};
5914
5916
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_s
ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t
;
5917
#endif
/* __ASSEMBLY__ */
5918
5920
#define ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_OFST 0xc
5921
5948
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0
5949
5950
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8
5951
5952
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9
5953
5954
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff
5955
5956
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00
5957
5958
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1
5959
5960
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
5961
5962
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
5963
5981
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9
5982
5983
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20
5984
5985
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12
5986
5987
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00
5988
5989
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff
5990
5991
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0
5992
5993
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
5994
5995
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
5996
5997
#ifndef __ASSEMBLY__
5998
6008
struct
ALT_CLKMGR_SDRPLL_DDRDQCLK_s
6009
{
6010
uint32_t
cnt
: 9;
6011
uint32_t
phase
: 12;
6012
uint32_t : 11;
6013
};
6014
6016
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_DDRDQCLK_s
ALT_CLKMGR_SDRPLL_DDRDQCLK_t
;
6017
#endif
/* __ASSEMBLY__ */
6018
6020
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10
6021
6050
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_LSB 0
6051
6052
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_MSB 8
6053
6054
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_WIDTH 9
6055
6056
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET_MSK 0x000001ff
6057
6058
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_CLR_MSK 0xfffffe00
6059
6060
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_RESET 0x1
6061
6062
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6063
6064
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6065
6083
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_LSB 9
6084
6085
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_MSB 20
6086
6087
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_WIDTH 12
6088
6089
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET_MSK 0x001ffe00
6090
6091
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_CLR_MSK 0xffe001ff
6092
6093
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_RESET 0x0
6094
6095
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9)
6096
6097
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00)
6098
6099
#ifndef __ASSEMBLY__
6100
6110
struct
ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s
6111
{
6112
uint32_t
cnt
: 9;
6113
uint32_t
phase
: 12;
6114
uint32_t : 11;
6115
};
6116
6118
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_S2FUSER2CLK_s
ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t
;
6119
#endif
/* __ASSEMBLY__ */
6120
6122
#define ALT_CLKMGR_SDRPLL_S2FUSER2CLK_OFST 0x14
6123
6156
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB 0
6157
6158
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB 0
6159
6160
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH 1
6161
6162
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK 0x00000001
6163
6164
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK 0xfffffffe
6165
6166
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET 0x1
6167
6168
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value) (((value) & 0x00000001) >> 0)
6169
6170
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value) (((value) << 0) & 0x00000001)
6171
6181
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB 1
6182
6183
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB 1
6184
6185
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH 1
6186
6187
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK 0x00000002
6188
6189
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK 0xfffffffd
6190
6191
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET 0x1
6192
6193
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value) (((value) & 0x00000002) >> 1)
6194
6195
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value) (((value) << 1) & 0x00000002)
6196
6206
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB 2
6207
6208
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB 2
6209
6210
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH 1
6211
6212
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK 0x00000004
6213
6214
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK 0xfffffffb
6215
6216
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET 0x1
6217
6218
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value) (((value) & 0x00000004) >> 2)
6219
6220
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value) (((value) << 2) & 0x00000004)
6221
6233
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB 3
6234
6235
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB 3
6236
6237
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH 1
6238
6239
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK 0x00000008
6240
6241
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK 0xfffffff7
6242
6243
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET 0x1
6244
6245
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value) (((value) & 0x00000008) >> 3)
6246
6247
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value) (((value) << 3) & 0x00000008)
6248
6249
#ifndef __ASSEMBLY__
6250
6260
struct
ALT_CLKMGR_SDRPLL_EN_s
6261
{
6262
uint32_t
ddrdqsclk
: 1;
6263
uint32_t
ddr2xdqsclk
: 1;
6264
uint32_t
ddrdqclk
: 1;
6265
uint32_t
s2fuser2clk
: 1;
6266
uint32_t : 28;
6267
};
6268
6270
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_EN_s
ALT_CLKMGR_SDRPLL_EN_t
;
6271
#endif
/* __ASSEMBLY__ */
6272
6274
#define ALT_CLKMGR_SDRPLL_EN_OFST 0x18
6275
6321
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_IDLE 0x0
6322
6327
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_E_ACK_RXD 0x1
6328
6330
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_LSB 0
6331
6332
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_MSB 5
6333
6334
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_WIDTH 6
6335
6336
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET_MSK 0x0000003f
6337
6338
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_CLR_MSK 0xffffffc0
6339
6340
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_RESET 0x0
6341
6342
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_GET(value) (((value) & 0x0000003f) >> 0)
6343
6344
#define ALT_CLKMGR_SDRPLL_STAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000003f)
6345
6346
#ifndef __ASSEMBLY__
6347
6357
struct
ALT_CLKMGR_SDRPLL_STAT_s
6358
{
6359
const
uint32_t
outresetack
: 6;
6360
uint32_t : 26;
6361
};
6362
6364
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_STAT_s
ALT_CLKMGR_SDRPLL_STAT_t
;
6365
#endif
/* __ASSEMBLY__ */
6366
6368
#define ALT_CLKMGR_SDRPLL_STAT_OFST 0x1c
6369
6370
#ifndef __ASSEMBLY__
6371
6381
struct
ALT_CLKMGR_SDRPLL_s
6382
{
6383
volatile
ALT_CLKMGR_SDRPLL_VCO_t
vco
;
6384
volatile
ALT_CLKMGR_SDRPLL_CTL_t
ctrl
;
6385
volatile
ALT_CLKMGR_SDRPLL_DDRDQSCLK_t
ddrdqsclk
;
6386
volatile
ALT_CLKMGR_SDRPLL_DDR2XDQSCLK_t
ddr2xdqsclk
;
6387
volatile
ALT_CLKMGR_SDRPLL_DDRDQCLK_t
ddrdqclk
;
6388
volatile
ALT_CLKMGR_SDRPLL_S2FUSER2CLK_t
s2fuser2clk
;
6389
volatile
ALT_CLKMGR_SDRPLL_EN_t
en
;
6390
volatile
ALT_CLKMGR_SDRPLL_STAT_t
stat
;
6391
};
6392
6394
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_s
ALT_CLKMGR_SDRPLL_t
;
6396
struct
ALT_CLKMGR_SDRPLL_raw_s
6397
{
6398
volatile
uint32_t
vco
;
6399
volatile
uint32_t
ctrl
;
6400
volatile
uint32_t
ddrdqsclk
;
6401
volatile
uint32_t
ddr2xdqsclk
;
6402
volatile
uint32_t
ddrdqclk
;
6403
volatile
uint32_t
s2fuser2clk
;
6404
volatile
uint32_t
en
;
6405
volatile
uint32_t
stat
;
6406
};
6407
6409
typedef
volatile
struct
ALT_CLKMGR_SDRPLL_raw_s
ALT_CLKMGR_SDRPLL_raw_t
;
6410
#endif
/* __ASSEMBLY__ */
6411
6445
#define ALT_CLKMGR_MISC_MPUCLK_CNT_LSB 0
6446
6447
#define ALT_CLKMGR_MISC_MPUCLK_CNT_MSB 8
6448
6449
#define ALT_CLKMGR_MISC_MPUCLK_CNT_WIDTH 9
6450
6451
#define ALT_CLKMGR_MISC_MPUCLK_CNT_SET_MSK 0x000001ff
6452
6453
#define ALT_CLKMGR_MISC_MPUCLK_CNT_CLR_MSK 0xfffffe00
6454
6455
#define ALT_CLKMGR_MISC_MPUCLK_CNT_RESET 0x1
6456
6457
#define ALT_CLKMGR_MISC_MPUCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6458
6459
#define ALT_CLKMGR_MISC_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6460
6461
#ifndef __ASSEMBLY__
6462
6472
struct
ALT_CLKMGR_MISC_MPUCLK_s
6473
{
6474
uint32_t
cnt
: 9;
6475
uint32_t : 23;
6476
};
6477
6479
typedef
volatile
struct
ALT_CLKMGR_MISC_MPUCLK_s
ALT_CLKMGR_MISC_MPUCLK_t
;
6480
#endif
/* __ASSEMBLY__ */
6481
6483
#define ALT_CLKMGR_MISC_MPUCLK_OFST 0x0
6484
6510
#define ALT_CLKMGR_MISC_MAINCLK_CNT_LSB 0
6511
6512
#define ALT_CLKMGR_MISC_MAINCLK_CNT_MSB 8
6513
6514
#define ALT_CLKMGR_MISC_MAINCLK_CNT_WIDTH 9
6515
6516
#define ALT_CLKMGR_MISC_MAINCLK_CNT_SET_MSK 0x000001ff
6517
6518
#define ALT_CLKMGR_MISC_MAINCLK_CNT_CLR_MSK 0xfffffe00
6519
6520
#define ALT_CLKMGR_MISC_MAINCLK_CNT_RESET 0x3
6521
6522
#define ALT_CLKMGR_MISC_MAINCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6523
6524
#define ALT_CLKMGR_MISC_MAINCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6525
6526
#ifndef __ASSEMBLY__
6527
6537
struct
ALT_CLKMGR_MISC_MAINCLK_s
6538
{
6539
uint32_t
cnt
: 9;
6540
uint32_t : 23;
6541
};
6542
6544
typedef
volatile
struct
ALT_CLKMGR_MISC_MAINCLK_s
ALT_CLKMGR_MISC_MAINCLK_t
;
6545
#endif
/* __ASSEMBLY__ */
6546
6548
#define ALT_CLKMGR_MISC_MAINCLK_OFST 0x4
6549
6575
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_LSB 0
6576
6577
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_MSB 8
6578
6579
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_WIDTH 9
6580
6581
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET_MSK 0x000001ff
6582
6583
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_CLR_MSK 0xfffffe00
6584
6585
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_RESET 0x3
6586
6587
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0)
6588
6589
#define ALT_CLKMGR_MISC_DBGATCLK_CNT_SET(value) (((value) << 0) & 0x000001ff)
6590
6591
#ifndef __ASSEMBLY__
6592
6602
struct
ALT_CLKMGR_MISC_DBGATCLK_s
6603
{
6604
uint32_t
cnt
: 9;
6605
uint32_t : 23;
6606
};
6607
6609
typedef
volatile
struct
ALT_CLKMGR_MISC_DBGATCLK_s
ALT_CLKMGR_MISC_DBGATCLK_t
;
6610
#endif
/* __ASSEMBLY__ */
6611
6613
#define ALT_CLKMGR_MISC_DBGATCLK_OFST 0x8
6614
6615
#ifndef __ASSEMBLY__
6616
6626
struct
ALT_CLKMGR_MISCGRP_s
6627
{
6628
volatile
ALT_CLKMGR_MISC_MPUCLK_t
mpuclk
;
6629
volatile
ALT_CLKMGR_MISC_MAINCLK_t
mainclk
;
6630
volatile
ALT_CLKMGR_MISC_DBGATCLK_t
dbgatclk
;
6631
volatile
uint32_t
_pad_0xc_0x20
[5];
6632
};
6633
6635
typedef
volatile
struct
ALT_CLKMGR_MISCGRP_s
ALT_CLKMGR_MISCGRP_t
;
6637
struct
ALT_CLKMGR_MISCGRP_raw_s
6638
{
6639
volatile
uint32_t
mpuclk
;
6640
volatile
uint32_t
mainclk
;
6641
volatile
uint32_t
dbgatclk
;
6642
volatile
uint32_t
_pad_0xc_0x20
[5];
6643
};
6644
6646
typedef
volatile
struct
ALT_CLKMGR_MISCGRP_raw_s
ALT_CLKMGR_MISCGRP_raw_t
;
6647
#endif
/* __ASSEMBLY__ */
6648
6650
#ifndef __ASSEMBLY__
6651
6661
struct
ALT_CLKMGR_s
6662
{
6663
volatile
ALT_CLKMGR_CTL_t
ctrl
;
6664
volatile
ALT_CLKMGR_BYPASS_t
bypass
;
6665
volatile
ALT_CLKMGR_INTER_t
inter
;
6666
volatile
ALT_CLKMGR_INTREN_t
intren
;
6667
volatile
ALT_CLKMGR_DBCTL_t
dbctrl
;
6668
volatile
ALT_CLKMGR_STAT_t
stat
;
6669
volatile
uint32_t
_pad_0x18_0x3f
[10];
6670
volatile
ALT_CLKMGR_MAINPLL_t
mainpllgrp
;
6671
volatile
ALT_CLKMGR_PERPLL_t
perpllgrp
;
6672
volatile
ALT_CLKMGR_SDRPLL_t
sdrpllgrp
;
6673
volatile
ALT_CLKMGR_MISCGRP_t
miscgrp
;
6674
volatile
uint32_t
_pad_0x100_0x200
[64];
6675
};
6676
6678
typedef
volatile
struct
ALT_CLKMGR_s
ALT_CLKMGR_t
;
6680
struct
ALT_CLKMGR_raw_s
6681
{
6682
volatile
uint32_t
ctrl
;
6683
volatile
uint32_t
bypass
;
6684
volatile
uint32_t
inter
;
6685
volatile
uint32_t
intren
;
6686
volatile
uint32_t
dbctrl
;
6687
volatile
uint32_t
stat
;
6688
volatile
uint32_t
_pad_0x18_0x3f
[10];
6689
volatile
ALT_CLKMGR_MAINPLL_raw_t
mainpllgrp
;
6690
volatile
ALT_CLKMGR_PERPLL_raw_t
perpllgrp
;
6691
volatile
ALT_CLKMGR_SDRPLL_raw_t
sdrpllgrp
;
6692
volatile
ALT_CLKMGR_MISCGRP_raw_t
miscgrp
;
6693
volatile
uint32_t
_pad_0x100_0x200
[64];
6694
};
6695
6697
typedef
volatile
struct
ALT_CLKMGR_raw_s
ALT_CLKMGR_raw_t
;
6698
#endif
/* __ASSEMBLY__ */
6699
6701
#ifdef __cplusplus
6702
}
6703
#endif
/* __cplusplus */
6704
#endif
/* __ALTERA_ALT_CLKMGR_H__ */
6705
include
soc_cv_av
socal
alt_clkmgr.h
Generated on Tue Sep 8 2015 13:28:41 for Altera SoCAL by
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