Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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The General Purpose Timer Manager API

Description

There are nine on-chip general purpose timers. Seven timers are available to each CPU.

There are four types of timers available:

Members

 Enable, Disable, and Status
 
 Counters Interface
 
 Interrupts
 
 Mode Control
 

Typedefs

typedef enum ALT_GPT_TIMER_e ALT_GPT_TIMER_t
 
typedef enum ALT_GPT_RESTART_MODE_e ALT_GPT_RESTART_MODE_t
 

ENUMS

enum  ALT_GPT_TIMER_e {
  ALT_GPT_CPU_GLOBAL_TMR, ALT_GPT_CPU_PRIVATE_TMR, ALT_GPT_CPU_WDTGPT_TMR, ALT_GPT_OSC1_TMR0,
  ALT_GPT_OSC1_TMR1, ALT_GPT_SP_TMR0, ALT_GPT_SP_TMR1
}
 
enum  ALT_GPT_RESTART_MODE_e { ALT_GPT_RESTART_MODE_ONESHOT, ALT_GPT_RESTART_MODE_PERIODIC }
 

Typedef Documentation

This type definition enumerates the names of the timers managed by the General Purpose Timers Manager.

This type definition enumerates the possible rollover or restart modes of the general purpose timers.

Enumeration Type Documentation

This type definition enumerates the names of the timers managed by the General Purpose Timers Manager.

Enumerator:
ALT_GPT_CPU_GLOBAL_TMR 

CPU_GLOBAL_TMR - CPU Core Global timer - There is one 64-bit continuously incrementing counter for all CPU cores that is clocked by PERIPHCLK. CPU_GLOBAL_TMR selects the comparator value, compare enable, autoincrement value, autoincrement enable, and interrupt enable for the CPU this code is running on.

ALT_GPT_CPU_PRIVATE_TMR 

CPU_PRIVATE_TMR - CPU Core 32-bit Private Timer - The private timer for the CPU this code is running on. Clocked by PERIPHCLK. Counts down to zero and can either stop or restart.

ALT_GPT_CPU_WDTGPT_TMR 

CPU_WDTGPT_TMR - CPU Core 32-bit Watchdog Timer - The watchdog timer can be used as a general-purpose timer by calling alt_wdt_response_mode_set() to put the watchdog timer in general-purpose timer mode. It is recommended that programmers use the other available timers first before using the watchdog timer as there is more software overhead involved in using the watchdog timer in this mode. This enum is for the core watchdog timer of the CPU this code is running on. Counts down to zero and can either stop or restart.

ALT_GPT_OSC1_TMR0 

osc1_timer0 - 32-bit timer connected to the L4_OSC1 bus clocked by osc1_clk. Counts down to zero and can either stop or restart.

ALT_GPT_OSC1_TMR1 

osc1_timer1 - 32-bit timer connected to the L4_OSC1 bus clocked by osc1_clk. Counts down to zero and can either stop or restart.

ALT_GPT_SP_TMR0 

sp_timer0 - 32-bit timer connected to the L4_SP bus clocked by l4_sp_clk. Counts down to zero and can either stop or restart.

ALT_GPT_SP_TMR1 

sp_timer1 - 32-bit timer connected to the L4_SP bus clocked by l4_sp_clk. Counts down to zero and can either stop or restart.

This type definition enumerates the possible rollover or restart modes of the general purpose timers.

Enumerator:
ALT_GPT_RESTART_MODE_ONESHOT 

ONE-SHOT MODE - CPU_PRIVATE_TMR counts down from the value set with alt_gpt_counter_set() to zero, triggers an interrupt and stops.
The global timer CPU_GLOBAL_TMR counts up to the next compare value set by the compare value, triggers an interrupt and stops comparing.
OSC1_TMR0, OSC1_TMR1, SP_TMR0, and SP_TMR1 count down from the value set with alt_gpt_counter_set() to zero, trigger an interrupt, reset to their maximum values and begin counting down anew. The timer counter wrapping to its maximum value allows time to reprogram or disable the timer before another interrupt occurs. For true one-shot operation using these timers, use alt_gpt_tmr_stop() after the interrupt has triggered.

ALT_GPT_RESTART_MODE_PERIODIC 

USER-SUPPLIED COUNT - For CPU_PRIVATE_TMR, OSC1_TMR0, OSC1_TMR1, SP_TMR0, and SP_TMR1, the timer counts down to zero and then resets to a value previously set using alt_gpt_counter_set() and continues counting.
CPU_GLOBAL_TMR counts up to the comparator value, then adds the value set in alt_gpt_counter_set() to the comparator value and continues counting.