Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 54 (SGMII/RGMII/SMII Status Register) - gmacgrp_sgmii_rgmii_smii_control_status

Description

The SGMII/RGMII/SMII Status register indicates the status signals received by the RGMII interface (selected at reset) from the PHY.

Register Layout

Bits Access Reset Description
[0] R 0x0 Link Mode
[2:1] R 0x0 Link Speed
[3] R 0x0 Link Status
[31:4] ??? 0x0 UNDEFINED

Field : Link Mode - lnkmod

This bit indicates the current mode of operation of the link

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP | 0x0 | ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP   0x1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB   0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB   0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH   1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Link Speed - lnkspeed

This bit indicates the current speed of the link. Bit 2 is reserved when the MAC is configured for the SMII PHY interface.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ | 0x0 | ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ | 0x1 | ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ | 0x2 |

Field Access Macros:

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ   0x1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ   0x2
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB   1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB   2
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH   2
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK   0x00000006
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK   0xfffffff9
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET(value)   (((value) & 0x00000006) >> 1)
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET(value)   (((value) << 1) & 0x00000006)
 

Field : Link Status - lnksts

This bit indicates whether the link is up (1'b1) or down (1'b0).

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN | 0x0 | ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP   0x1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB   3
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB   3
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH   1
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET   0x0
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET(value)   (((value) << 3) & 0x00000008)
 

Data Structures

struct  ALT_EMAC_GMAC_MII_CTL_STAT_s
 

Macros

#define ALT_EMAC_GMAC_MII_CTL_STAT_RESET   0x00000000
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_OFST   0xd8
 
#define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MII_CTL_STAT_s 
ALT_EMAC_GMAC_MII_CTL_STAT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MII_CTL_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MII_CTL_STAT.

Data Fields
const uint32_t lnkmod: 1 Link Mode
const uint32_t lnkspeed: 2 Link Speed
const uint32_t lnksts: 1 Link Status
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_HALFDUP   0x0

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_E_FULLDUP   0x1

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD field value from a register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKMOD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED2POINT5MHZ   0x0

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED25MHZ   0x1

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_E_SPEED125MHZ   0x2

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET_MSK   0x00000006

The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_CLR_MSK   0xfffffff9

The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_GET (   value)    (((value) & 0x00000006) >> 1)

Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED field value from a register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED_SET (   value)    (((value) << 1) & 0x00000006)

Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSPEED register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKDOWN   0x0

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_E_LINKUP   0x1

Enumerated value for register field ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS field value from a register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MII_CTL_STAT_LNKSTS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_MII_CTL_STAT register.

#define ALT_EMAC_GMAC_MII_CTL_STAT_OFST   0xd8

The byte offset of the ALT_EMAC_GMAC_MII_CTL_STAT register from the beginning of the component.

#define ALT_EMAC_GMAC_MII_CTL_STAT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MII_CTL_STAT_OFST))

The address of the ALT_EMAC_GMAC_MII_CTL_STAT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_MII_CTL_STAT.