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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock dividers for main clocks derived from the Main PLL
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[25:0] | ??? | 0x0 | UNDEFINED |
[26] | RW | 0x0 | EMAC0 clock select |
[27] | RW | 0x0 | EMAC1 clock select |
[28] | RW | 0x0 | EMAC2 clock select |
[31:29] | ??? | 0x0 | UNDEFINED |
Field : EMAC0 clock select - emac0sel | ||||||||||
Selects the source for emac0_clk as either emaca_free_clk or emacb_free_clk. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET(value) (((value) & 0x04000000) >> 26) | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET(value) (((value) << 26) & 0x04000000) | |||||||||
Field : EMAC1 clock select - emac1sel | ||||||||||
Selects the source for emac1_clk as either emaca_free_clk or emacb_free_clk. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET(value) (((value) & 0x08000000) >> 27) | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET(value) (((value) << 27) & 0x08000000) | |||||||||
Field : EMAC2 clock select - emac2sel | ||||||||||
Selects the source for emac2_clk as either emaca_free_clk or emacb_free_clk. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0 | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET(value) (((value) & 0x10000000) >> 28) | |||||||||
#define | ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET(value) (((value) << 28) & 0x10000000) | |||||||||
Data Structures | |
struct | ALT_CLKMGR_PERPLL_EMACCTL_s |
Macros | |
#define | ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000 |
#define | ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x68 |
Typedefs | |
typedef struct ALT_CLKMGR_PERPLL_EMACCTL_s | ALT_CLKMGR_PERPLL_EMACCTL_t |
struct ALT_CLKMGR_PERPLL_EMACCTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_PERPLL_EMACCTL.
Data Fields | ||
---|---|---|
uint32_t | __pad0__: 26 | UNDEFINED |
uint32_t | emac0sel: 1 | EMAC0 clock select |
uint32_t | emac1sel: 1 | EMAC1 clock select |
uint32_t | emac2sel: 1 | EMAC2 clock select |
uint32_t | __pad1__: 3 | UNDEFINED |
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
EMAC A
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL
EMAC B
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000 |
The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL field value from a register.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
EMAC A
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL
EMAC B
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000 |
The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL field value from a register.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
EMAC A
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL
EMAC B
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000 |
The mask used to set the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff |
The mask used to clear the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL field value from a register.
#define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000 |
The reset value of the ALT_CLKMGR_PERPLL_EMACCTL register.
#define ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x68 |
The byte offset of the ALT_CLKMGR_PERPLL_EMACCTL register from the beginning of the component.
typedef struct ALT_CLKMGR_PERPLL_EMACCTL_s ALT_CLKMGR_PERPLL_EMACCTL_t |
The typedef declaration for register ALT_CLKMGR_PERPLL_EMACCTL.