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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock dividers for main clocks derived from the Main PLL
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x0 | L3 MP Clock Divider |
[3:2] | RW | 0x0 | L3 SP Clock Divider |
[6:4] | RW | 0x0 | L4 MP Clock Divider |
[9:7] | RW | 0x0 | L4 SP Clock Divider |
[31:10] | ??? | 0x0 | UNDEFINED |
Field : L3 MP Clock Divider - l3mpclk | ||||||||||
The l3_mp_clk is divided down from the l3_main_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET(value) (((value) & 0x00000003) >> 0) | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET(value) (((value) << 0) & 0x00000003) | |||||||||
Field : L3 SP Clock Divider - l3spclk | ||||||||||
The l3_sp_clk is divided down from the l3_mp_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET(value) (((value) & 0x0000000c) >> 2) | |||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET(value) (((value) << 2) & 0x0000000c) | |||||||||
Field : L4 SP Clock Divider - l4spclk | ||||||||||||||||||||||||||||
The l4_sp_clk is divided down from the periph_base_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET(value) (((value) & 0x00000380) >> 7) | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET(value) (((value) << 7) & 0x00000380) | |||||||||||||||||||||||||||
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_MAINDIV_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_MAINDIV_s | ALT_CLKMGR_MAINPLL_MAINDIV_t |
struct ALT_CLKMGR_MAINPLL_MAINDIV_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_MAINDIV.
Data Fields | ||
---|---|---|
uint32_t | l3mpclk: 2 | L3 MP Clock Divider |
uint32_t | l3spclk: 2 | L3 SP Clock Divider |
uint32_t | l4mpclk: 3 | L4 MP Clock Divider |
uint32_t | l4spclk: 3 | L4 SP Clock Divider |
uint32_t | __pad0__: 22 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
Divide by 1
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK
Divide by 2
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET_MSK 0x00000003 |
The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3MPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
Divide by 1
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK
Divide by 2
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET_MSK 0x0000000c |
The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L3SPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Divide By 16
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET_MSK 0x00000070 |
The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_CLR_MSK 0xffffff8f |
The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_GET | ( | value | ) | (((value) & 0x00000070) >> 4) |
Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK_SET | ( | value | ) | (((value) << 4) & 0x00000070) |
Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4MPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Divide By 16
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK
Reserved
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET_MSK 0x00000380 |
The mask used to set the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_CLR_MSK 0xfffffc7f |
The mask used to clear the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_GET | ( | value | ) | (((value) & 0x00000380) >> 7) |
Extracts the ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK_SET | ( | value | ) | (((value) << 7) & 0x00000380) |
Produces a ALT_CLKMGR_MAINPLL_MAINDIV_L4SPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_MAINDIV_OFST 0x24 |
The byte offset of the ALT_CLKMGR_MAINPLL_MAINDIV register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_MAINDIV_s ALT_CLKMGR_MAINPLL_MAINDIV_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_MAINDIV.