Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - hdskack

Description

The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de- assert the warm reset.

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[0] R 0x0 SDRAM Self-Refresh Acknowledge
[1] R 0x0 FPGA Manager Handshake Acknowledge
[2] R 0x0 FPGA Handshake Acknowledge
[3] R 0x0 ETR (Embedded Trace Router) Stall Acknowledge
[7:4] ??? 0x0 UNDEFINED
[8] RW 0x0 ETR (Embedded Trace Router) Stall After Warm Reset
[31:9] ??? Unknown UNDEFINED

Field : SDRAM Self-Refresh Acknowledge - sdrselfreqack

This is the acknowlege for a SDRAM self-refresh mode request initiated by the SDRSELFREFREQ field. A 1 indicates that the SDRAM Controller Subsystem has put the SDRAM devices into self-refresh mode.

Field Access Macros:

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB   0
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB   0
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH   1
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK   0x00000001
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET   0x0
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET(value)   (((value) << 0) & 0x00000001)
 

Field : FPGA Manager Handshake Acknowledge - fpgamgrhsack

This is the acknowlege (high active) that the FPGA manager has successfully idled its output clock.

Field Access Macros:

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_LSB   1
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_MSB   1
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_WIDTH   1
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET_MSK   0x00000002
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_RESET   0x0
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET(value)   (((value) << 1) & 0x00000002)
 

Field : FPGA Handshake Acknowledge - fpgahsack

This is the acknowlege (high active) that the FPGA handshake acknowledge has been received by Reset Manager.

Field Access Macros:

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB   2
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB   2
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH   1
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK   0x00000004
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET   0x0
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET(value)   (((value) << 2) & 0x00000004)
 

Field : ETR (Embedded Trace Router) Stall Acknowledge - etrstallack

This is the acknowlege for a ETR AXI master stall initiated by the ETRSTALLREQ field. A 1 indicates that the ETR has stalled its AXI master

Field Access Macros:

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB   3
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB   3
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH   1
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK   0x00000008
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET   0x0
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET(value)   (((value) << 3) & 0x00000008)
 

Field : ETR (Embedded Trace Router) Stall After Warm Reset - etrstallwarmrst

If a warm reset occurs and ETRSTALLEN is 1, hardware sets this bit to 1 to indicate that the stall of the ETR AXI master is pending. Hardware leaves the ETR stalled until software clears this field by writing it with 1. Software must only clear this field when it is ready to have the ETR AXI master start making AXI requests to write trace data.

Field Access Macros:

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_LSB   8
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_MSB   8
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_WIDTH   1
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET_MSK   0x00000100
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_CLR_MSK   0xfffffeff
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_RESET   0x0
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET(value)   (((value) << 8) & 0x00000100)
 

Data Structures

struct  ALT_RSTMGR_HDSKACK_s
 

Macros

#define ALT_RSTMGR_HDSKACK_RESET   0x00100000
 
#define ALT_RSTMGR_HDSKACK_OFST   0x18
 

Typedefs

typedef struct ALT_RSTMGR_HDSKACK_s ALT_RSTMGR_HDSKACK_t
 

Data Structure Documentation

struct ALT_RSTMGR_HDSKACK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_HDSKACK.

Data Fields
const uint32_t sdrselfreqack: 1 SDRAM Self-Refresh Acknowledge
const uint32_t fpgamgrhsack: 1 FPGA Manager Handshake Acknowledge
const uint32_t fpgahsack: 1 FPGA Handshake Acknowledge
const uint32_t etrstallack: 1 ETR (Embedded Trace Router) Stall Acknowledge
uint32_t __pad0__: 4 UNDEFINED
uint32_t etrstallwarmrst: 1 ETR (Embedded Trace Router) Stall After Warm Reset
uint32_t __pad1__: 23 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_HDSKACK_SDRSELFREQACK field value from a register.

#define ALT_RSTMGR_HDSKACK_SDRSELFREQACK_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_HDSKACK_SDRSELFREQACK register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_HDSKACK_FPGAMGRHSACK field value from a register.

#define ALT_RSTMGR_HDSKACK_FPGAMGRHSACK_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_HDSKACK_FPGAMGRHSACK register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_HDSKACK_FPGAHSACK register field value.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKACK_FPGAHSACK register field.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_HDSKACK_FPGAHSACK field value from a register.

#define ALT_RSTMGR_HDSKACK_FPGAHSACK_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_HDSKACK_FPGAHSACK register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKACK_ETRSTALLACK register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_HDSKACK_ETRSTALLACK field value from a register.

#define ALT_RSTMGR_HDSKACK_ETRSTALLACK_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_HDSKACK_ETRSTALLACK register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_LSB   8

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_MSB   8

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET_MSK   0x00000100

The mask used to set the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_CLR_MSK   0xfffffeff

The mask used to clear the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST field value from a register.

#define ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_RSTMGR_HDSKACK_ETRSTALLWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKACK_RESET   0x00100000

The reset value of the ALT_RSTMGR_HDSKACK register.

#define ALT_RSTMGR_HDSKACK_OFST   0x18

The byte offset of the ALT_RSTMGR_HDSKACK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_HDSKACK.