Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : wdt_comp_param_1

Description

Component Parameters Register 1

Register Layout

Bits Access Reset Description
[0] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
[1] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
[2] R 0x1 ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
[3] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
[4] R 0x1 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
[5] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
[6] R 0x1 ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
[7] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE
[9:8] R 0x2 ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
[12:10] R 0x0 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
[15:13] R 0x0 ALT_L4WD_COMP_PARAM_1_RSVD_15_13
[19:16] R 0xf ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
[23:20] R 0xf ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
[28:24] R 0x10 ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
[31:29] R 0x0 ALT_L4WD_COMP_PARAM_1_RSVD_31_29

Field : cp_wdt_always_en

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0 Watchdog disabled on reset

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB   0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB   0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK   0x00000001
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK   0xfffffffe
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : cp_wdt_dflt_rmod

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0 Generate a warm reset request (don't generate an
: interrupt first)

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK   0x00000002
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK   0xfffffffd
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET(value)   (((value) << 1) & 0x00000002)
 

Field : cp_wdt_dual_top

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1 Second timeout period is present

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB   2
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB   2
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK   0x00000004
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK   0xfffffffb
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET(value)   (((value) << 2) & 0x00000004)
 

Field : cp_wdt_hc_rmod

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0 Output response mode is programmable.

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB   3
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB   3
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK   0x00000008
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK   0xfffffff7
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET(value)   (((value) << 3) & 0x00000008)
 

Field : cp_wdt_hc_rpl

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1 Reset pulse length is hardcoded.

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB   4
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB   4
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK   0x00000010
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK   0xffffffef
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET(value)   (((value) << 4) & 0x00000010)
 

Field : cp_wdt_hc_top

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0 Timeout period is programmable.

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB   5
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB   5
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK   0x00000020
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK   0xffffffdf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET(value)   (((value) << 5) & 0x00000020)
 

Field : cp_wdt_use_fix_top

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1 Use pre-defined (fixed) timeout values (range
: from 2**16 to 2**31)

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB   6
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB   6
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK   0x00000040
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK   0xffffffbf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET   0x1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET(value)   (((value) << 6) & 0x00000040)
 

Field : cp_wdt_pause

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB   7
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB   7
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH   1
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK   0x00000080
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK   0xffffff7f
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET(value)   (((value) << 7) & 0x00000080)
 

Field : cp_wdt_apb_data_width

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 APB Data Width is 32 Bits

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS   0x2
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB   8
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB   9
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH   2
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK   0x00000300
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK   0xfffffcff
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET   0x2
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET(value)   (((value) & 0x00000300) >> 8)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET(value)   (((value) << 8) & 0x00000300)
 

Field : cp_wdt_dflt_rpl

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0 Reset pulse length of 2 cycles.

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB   10
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB   12
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH   3
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK   0x00001c00
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK   0xffffe3ff
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET(value)   (((value) & 0x00001c00) >> 10)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET(value)   (((value) << 10) & 0x00001c00)
 

Field : rsvd_15_13

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_LSB   13
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_MSB   15
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_WIDTH   3
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET_MSK   0x0000e000
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_CLR_MSK   0xffff1fff
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_GET(value)   (((value) & 0x0000e000) >> 13)
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET(value)   (((value) << 13) & 0x0000e000)
 

Field : cp_wdt_dflt_top

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf Timeout period is 15 (2**31 cycles).

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15   0xf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB   16
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB   19
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH   4
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK   0x000f0000
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK   0xfff0ffff
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET   0xf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET(value)   (((value) & 0x000f0000) >> 16)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET(value)   (((value) << 16) & 0x000f0000)
 

Field : cp_wdt_dflt_top_init

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf Initial timeout period is 15 (2**31 cycles).

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15   0xf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB   20
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB   23
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH   4
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK   0x00f00000
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK   0xff0fffff
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET   0xf
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET(value)   (((value) & 0x00f00000) >> 20)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET(value)   (((value) << 20) & 0x00f00000)
 

Field : cp_wdt_cnt_width

Field Enumeration Values:

Enum Value Description
ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10 Counter width is 32 bits

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS   0x10
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB   24
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB   28
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH   5
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK   0x1f000000
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK   0xe0ffffff
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET   0x10
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET(value)   (((value) & 0x1f000000) >> 24)
 
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET(value)   (((value) << 24) & 0x1f000000)
 

Field : rsvd_31_29

Field Access Macros:

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_LSB   29
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_MSB   31
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_WIDTH   3
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET_MSK   0xe0000000
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_CLR_MSK   0x1fffffff
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_RESET   0x0
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_GET(value)   (((value) & 0xe0000000) >> 29)
 
#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET(value)   (((value) << 29) & 0xe0000000)
 

Data Structures

struct  ALT_L4WD_COMP_PARAM_1_s
 

Macros

#define ALT_L4WD_COMP_PARAM_1_RESET   0x10ff0254
 
#define ALT_L4WD_COMP_PARAM_1_OFST   0xf4
 
#define ALT_L4WD_COMP_PARAM_1_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST))
 

Typedefs

typedef struct
ALT_L4WD_COMP_PARAM_1_s 
ALT_L4WD_COMP_PARAM_1_t
 

Data Structure Documentation

struct ALT_L4WD_COMP_PARAM_1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L4WD_COMP_PARAM_1.

Data Fields
const uint32_t cp_wdt_always_en: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
const uint32_t cp_wdt_dflt_rmod: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
const uint32_t cp_wdt_dual_top: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
const uint32_t cp_wdt_hc_rmod: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
const uint32_t cp_wdt_hc_rpl: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
const uint32_t cp_wdt_hc_top: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
const uint32_t cp_wdt_use_fix_top: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
const uint32_t cp_wdt_pause: 1 ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE
const uint32_t cp_wdt_apb_data_width: 2 ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
const uint32_t cp_wdt_dflt_rpl: 3 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
const uint32_t rsvd_15_13: 3 ALT_L4WD_COMP_PARAM_1_RSVD_15_13
const uint32_t cp_wdt_dflt_top: 4 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
const uint32_t cp_wdt_dflt_top_init: 4 ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
const uint32_t cp_wdt_cnt_width: 5 ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
const uint32_t rsvd_31_29: 3 ALT_L4WD_COMP_PARAM_1_RSVD_31_29

Macro Definitions

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD   0x0

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN

Watchdog disabled on reset

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK   0x00000001

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ   0x0

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD

Generate a warm reset request (don't generate an interrupt first)

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB   1

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB   1

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK   0x00000002

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP   0x1

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP

Second timeout period is present

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB   2

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB   2

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK   0x00000004

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK   0xfffffffb

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET   0x1

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML   0x0

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD

Output response mode is programmable.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB   3

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB   3

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK   0x00000008

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK   0xfffffff7

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED   0x1

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL

Reset pulse length is hardcoded.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB   4

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB   4

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK   0x00000010

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK   0xffffffef

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET   0x1

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML   0x0

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP

Timeout period is programmable.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB   5

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB   5

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK   0x00000020

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK   0xffffffdf

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED   0x1

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP

Use pre-defined (fixed) timeout values (range from 2**16 to 2**31)

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB   6

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB   6

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK   0x00000040

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK   0xffffffbf

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET   0x1

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB   7

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB   7

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH   1

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK   0x00000080

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK   0xffffff7f

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS   0x2

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH

APB Data Width is 32 Bits

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB   8

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB   9

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH   2

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK   0x00000300

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK   0xfffffcff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET   0x2

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET (   value)    (((value) & 0x00000300) >> 8)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET (   value)    (((value) << 8) & 0x00000300)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES   0x0

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL

Reset pulse length of 2 cycles.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB   10

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB   12

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH   3

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK   0x00001c00

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK   0xffffe3ff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET (   value)    (((value) & 0x00001c00) >> 10)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET (   value)    (((value) << 10) & 0x00001c00)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_LSB   13

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_MSB   15

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_WIDTH   3

The width in bits of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET_MSK   0x0000e000

The mask used to set the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_CLR_MSK   0xffff1fff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_GET (   value)    (((value) & 0x0000e000) >> 13)

Extracts the ALT_L4WD_COMP_PARAM_1_RSVD_15_13 field value from a register.

#define ALT_L4WD_COMP_PARAM_1_RSVD_15_13_SET (   value)    (((value) << 13) & 0x0000e000)

Produces a ALT_L4WD_COMP_PARAM_1_RSVD_15_13 register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15   0xf

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP

Timeout period is 15 (2**31 cycles).

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB   16

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB   19

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH   4

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK   0x000f0000

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK   0xfff0ffff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET   0xf

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET (   value)    (((value) & 0x000f0000) >> 16)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET (   value)    (((value) << 16) & 0x000f0000)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15   0xf

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT

Initial timeout period is 15 (2**31 cycles).

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB   20

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB   23

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH   4

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK   0x00f00000

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK   0xff0fffff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET   0xf

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET (   value)    (((value) & 0x00f00000) >> 20)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET (   value)    (((value) << 20) & 0x00f00000)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS   0x10

Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH

Counter width is 32 bits

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB   24

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB   28

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH   5

The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK   0x1f000000

The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK   0xe0ffffff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET   0x10

The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET (   value)    (((value) & 0x1f000000) >> 24)

Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH field value from a register.

#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET (   value)    (((value) << 24) & 0x1f000000)

Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_LSB   29

The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_MSB   31

The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_WIDTH   3

The width in bits of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET_MSK   0xe0000000

The mask used to set the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_CLR_MSK   0x1fffffff

The mask used to clear the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_RESET   0x0

The reset value of the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_GET (   value)    (((value) & 0xe0000000) >> 29)

Extracts the ALT_L4WD_COMP_PARAM_1_RSVD_31_29 field value from a register.

#define ALT_L4WD_COMP_PARAM_1_RSVD_31_29_SET (   value)    (((value) << 29) & 0xe0000000)

Produces a ALT_L4WD_COMP_PARAM_1_RSVD_31_29 register field value suitable for setting the register.

#define ALT_L4WD_COMP_PARAM_1_RESET   0x10ff0254

The reset value of the ALT_L4WD_COMP_PARAM_1 register.

#define ALT_L4WD_COMP_PARAM_1_OFST   0xf4

The byte offset of the ALT_L4WD_COMP_PARAM_1 register from the beginning of the component.

#define ALT_L4WD_COMP_PARAM_1_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST))

The address of the ALT_L4WD_COMP_PARAM_1 register.

Typedef Documentation

The typedef declaration for register ALT_L4WD_COMP_PARAM_1.