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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 4 (GMII Address Register)
The GMII Address register controls the management cycles to the external PHY through the management interface.
Note: This register is present for all PHY interface when you select the Station Management (MDIO) feature in coreConsultant.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GB |
[1] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GW |
[5:2] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_CR |
[10:6] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GR |
[15:11] | RW | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_PA |
[31:16] | R | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 |
Field : gb | |
GMII Busy This bit should read logic 0 before writing to Register 4 and Register 5. During a PHY or RevMII register access, the software sets this bit to 1'b1 to indicate that a Read or Write access is in progress. Register 5 is invalid until this bit is cleared by the MAC. Therefore, Register 5 (GMII Data) should be kept valid until the MAC clears this bit during a PHY Write operation. Similarly for a read operation, the contents of Register 5 are not valid until this bit is cleared. The subsequent read or write operation should happen only after the previous operation is complete. Because there is no acknowledgment from the PHY to MAC after a read or write operation is completed, there is no change in the functionality of this bit even when the PHY is not present. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GB_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_E_END 0x1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_LSB 0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_MSB 0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH 1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_GMII_ADDR_GB_SET(value) (((value) << 0) & 0x00000001) |
Field : gw | |
GMII Write When set, this bit indicates to the PHY or RevMII that this is a Write operation using the GMII Data register. If this bit is not set, it indicates that this is a Read operation, that is, placing the data in the GMII Data register. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_GW_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_E_END 0x1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_LSB 1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_MSB 1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH 1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_GMII_ADDR_GW_SET(value) (((value) << 1) & 0x00000002) |
Field : cr | |
CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design. The suggested range of CSR clock frequency applicable for each value (when Bit[5] = 0) ensures that the MDC clock is approximately between the frequency range 1.0 MHz - 2.5 MHz.
When Bit 5 is set, you can achieve MDC clock of frequency higher than the IEEE 802.3 specified frequency limit of 2.5 MHz and program a clock divider of lower value. For example, when CSR clock is of 100 MHz frequency and you program these bits as 1010, then the resultant MDC clock is of 12.5 MHz which is outside the limit of IEEE 802.3 specified range. Program the following values only if the interfacing chips support faster MDC clocks:
These bits are not used for accessing RevMII. These bits are read-only if the RevMII interface is selected as single PHY interface. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 | 0x0 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 | 0x1 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 | 0x2 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 | 0x3 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 | 0x4 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 | 0x5 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 | 0x8 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 | 0x9 | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 | 0xa | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 | 0xb | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 | 0xc | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 | 0xd | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN | 0xe | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 | 0xf | Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 0x1 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 0x2 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 0x3 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 0x5 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 0x8 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 0x9 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 0xa |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 0xb |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 0xc |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 0xd |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 0xf |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_LSB 2 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_MSB 5 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH 4 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK 0x0000003c |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK 0xffffffc3 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_GET(value) (((value) & 0x0000003c) >> 2) |
#define | ALT_EMAC_GMAC_GMII_ADDR_CR_SET(value) (((value) << 2) & 0x0000003c) |
Field : gr | |
GMII Register These bits select the desired GMII register in the selected PHY device. For RevMII, these bits select the desired CSR register in the RevMII Registers set. Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_LSB 6 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_MSB 10 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH 5 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK 0x000007c0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK 0xfffff83f |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_GET(value) (((value) & 0x000007c0) >> 6) |
#define | ALT_EMAC_GMAC_GMII_ADDR_GR_SET(value) (((value) << 6) & 0x000007c0) |
Field : pa | |
Physical Layer Address This field indicates which of the 32 possible PHY devices are being accessed. For RevMII, this field gives the PHY Address of the RevMII module. Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_LSB 11 |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_MSB 15 |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH 5 |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK 0x0000f800 |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK 0xffff07ff |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_GET(value) (((value) & 0x0000f800) >> 11) |
#define | ALT_EMAC_GMAC_GMII_ADDR_PA_SET(value) (((value) << 11) & 0x0000f800) |
Field : reserved_31_16 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_LSB 16 |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_MSB 31 |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_WIDTH 16 |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET_MSK 0xffff0000 |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_CLR_MSK 0x0000ffff |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_RESET 0x0 |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_GET(value) (((value) & 0xffff0000) >> 16) |
#define | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET(value) (((value) << 16) & 0xffff0000) |
Data Structures | |
struct | ALT_EMAC_GMAC_GMII_ADDR_s |
Macros | |
#define | ALT_EMAC_GMAC_GMII_ADDR_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_GMII_ADDR_OFST 0x10 |
#define | ALT_EMAC_GMAC_GMII_ADDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_GMII_ADDR_s | ALT_EMAC_GMAC_GMII_ADDR_t |
struct ALT_EMAC_GMAC_GMII_ADDR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_GMII_ADDR.
Data Fields | ||
---|---|---|
uint32_t | gb: 1 | ALT_EMAC_GMAC_GMII_ADDR_GB |
uint32_t | gw: 1 | ALT_EMAC_GMAC_GMII_ADDR_GW |
uint32_t | cr: 4 | ALT_EMAC_GMAC_GMII_ADDR_CR |
uint32_t | gr: 5 | ALT_EMAC_GMAC_GMII_ADDR_GR |
uint32_t | pa: 5 | ALT_EMAC_GMAC_GMII_ADDR_PA |
const uint32_t | reserved_31_16: 16 | ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 |
#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
#define ALT_EMAC_GMAC_GMII_ADDR_GB_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GB
#define ALT_EMAC_GMAC_GMII_ADDR_GB_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GB register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GB register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GB register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GB register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GB register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_GB field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_GB_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_GB register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
#define ALT_EMAC_GMAC_GMII_ADDR_GW_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_GW
#define ALT_EMAC_GMAC_GMII_ADDR_GW_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GW register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GW register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GW register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GW register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GW register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_GW field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_GW_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_GW register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV42 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV62 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16 0x2 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV26 0x3 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV102 0x4 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV124 0x5 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV4 0x8 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV6 0x9 |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV8 0xa |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV10 0xb |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV12 0xc |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV14 0xd |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV16AGAIN 0xe |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_E_DIV18 0xf |
Enumerated value for register field ALT_EMAC_GMAC_GMII_ADDR_CR
#define ALT_EMAC_GMAC_GMII_ADDR_CR_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_CR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_WIDTH 4 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_CR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET_MSK 0x0000003c |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_CR register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_CLR_MSK 0xffffffc3 |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_CR register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_CR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_GET | ( | value | ) | (((value) & 0x0000003c) >> 2) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_CR field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_CR_SET | ( | value | ) | (((value) << 2) & 0x0000003c) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_CR register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_GR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_WIDTH 5 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_GR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET_MSK 0x000007c0 |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_GR register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_CLR_MSK 0xfffff83f |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_GR register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_GR register field.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_GET | ( | value | ) | (((value) & 0x000007c0) >> 6) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_GR field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_GR_SET | ( | value | ) | (((value) << 6) & 0x000007c0) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_GR register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_PA register field.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_WIDTH 5 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_PA register field.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET_MSK 0x0000f800 |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_PA register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_CLR_MSK 0xffff07ff |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_PA register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_PA register field.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_GET | ( | value | ) | (((value) & 0x0000f800) >> 11) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_PA field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_PA_SET | ( | value | ) | (((value) << 11) & 0x0000f800) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_PA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_WIDTH 16 |
The width in bits of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET_MSK 0xffff0000 |
The mask used to set the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_CLR_MSK 0x0000ffff |
The mask used to clear the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_GET | ( | value | ) | (((value) & 0xffff0000) >> 16) |
Extracts the ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 field value from a register.
#define ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16_SET | ( | value | ) | (((value) << 16) & 0xffff0000) |
Produces a ALT_EMAC_GMAC_GMII_ADDR_RSVD_31_16 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_GMII_ADDR_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_GMII_ADDR register.
#define ALT_EMAC_GMAC_GMII_ADDR_OFST 0x10 |
The byte offset of the ALT_EMAC_GMAC_GMII_ADDR register from the beginning of the component.
#define ALT_EMAC_GMAC_GMII_ADDR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_GMII_ADDR_OFST)) |
The address of the ALT_EMAC_GMAC_GMII_ADDR register.
typedef struct ALT_EMAC_GMAC_GMII_ADDR_s ALT_EMAC_GMAC_GMII_ADDR_t |
The typedef declaration for register ALT_EMAC_GMAC_GMII_ADDR.