Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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FPGA Configuration

Description

This functional group provides the following services:

Members

 FPGA Full Configuration
 

Typedefs

typedef enum ALT_FPGA_CFG_MODE_e ALT_FPGA_CFG_MODE_t
 
typedef int32_t(* alt_fpga_istream_t )(void *buf, size_t buf_len, void *user_data)
 

ENUMS

enum  ALT_FPGA_CFG_MODE_e {
  ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC = 0x0, ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC = 0x1, ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC = 0x2, ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC = 0x4,
  ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC = 0x5, ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC = 0x6, ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC = 0x8, ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC = 0x9,
  ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC = 0xa, ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC = 0xc, ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC = 0xd, ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC = 0xe,
  ALT_FPGA_CFG_MODE_UNKNOWN = 0x20
}
 

Functions

ALT_FPGA_CFG_MODE_t alt_fpga_cfg_mode_get (void)
 
ALT_STATUS_CODE alt_fpga_cfg_mode_set (ALT_FPGA_CFG_MODE_t cfg_mode)
 

Typedef Documentation

This type definition enumerates the available modes for configuring the FPGA.

typedef int32_t(* alt_fpga_istream_t)(void *buf, size_t buf_len, void *user_data)

Type definition for the callback function prototype used by the FPGA Manager to read configuration bitstream data from a user defined input source stream.

The purpose of this callback function declaration is to provide a prototype for a user defined method of sequentially reading FPGA configuration bitstream data from an arbitrary input source. Example input sources include a file resident on a file system, a network stream socket, or a fixed address block in flash memory. The only requirement on the input source is that it is capable of supplying consecutive blocks of data of the requested size from the FPGA configuration bitstream as demanded by the FPGA Manager.

During FPGA configuration, the FPGA Manager periodically calls the user defined callback function to fetch the next buf_len consecutive configuration data bytes from the user defined input stream. The callback function fills the FPGA Manager supplied buffer buf with up to the next buf_len bytes of configuration bitsteam data as read from the input source stream. The callback function returns the number of configuration bytes read into buf or 0 upon reaching the end of the configuration bitstream data.

If an error occurs on the configuration bitstream input source, then the callback function should return an error code value less than 0.

Parameters
bufA pointer to a buffer to fill with FPGA configuration bitstream data bytes.
buf_lenThe length of the input buffer buf in bytes. The number of FPGA configuration bitstream data bytes copied into buf should not exceed buf_len.
user_dataA 32-bit data word for passing user defined data. The content of this parameter is user defined. The FPGA Manager merely forwards the user_data value when it invokes the callback.
Return values
>0The number of bytes returned in buf.
=0The end of the input stream has been reached.
<0An error occurred on the input stream.

Enumeration Type Documentation

This type definition enumerates the available modes for configuring the FPGA.

Enumerator:
ALT_FPGA_CFG_MODE_PP16_FAST_NOAES_NODC 

16-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP16_FAST_AES_NODC 

16-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP16_FAST_AESOPT_DC 

16-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP16_SLOW_NOAES_NODC 

16-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP16_SLOW_AES_NODC 

16-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP16_SLOW_AESOPT_DC 

16-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP32_FAST_NOAES_NODC 

32-bit Passive Parallel with Fast Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP32_FAST_AES_NODC 

32-bit Passive Parallel with Fast Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP32_FAST_AESOPT_DC 

32-bit Passive Parallel with Fast Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_PP32_SLOW_NOAES_NODC 

32-bit Passive Parallel with Slow Power on Reset Delay; No AES Encryption; No Data Compression. CDRATIO must be programmed to x1.

ALT_FPGA_CFG_MODE_PP32_SLOW_AES_NODC 

32-bit Passive Parallel with Slow Power on Reset Delay; With AES Encryption; No Data Compression. CDRATIO must be programmed to x4.

ALT_FPGA_CFG_MODE_PP32_SLOW_AESOPT_DC 

32-bit Passive Parallel with Slow Power on Reset Delay; AES Optional; With Data Compression. CDRATIO must be programmed to x8.

ALT_FPGA_CFG_MODE_UNKNOWN 

Unknown FPGA Configuration Mode.

Function Documentation

ALT_FPGA_CFG_MODE_t alt_fpga_cfg_mode_get ( void  )

Gets the FPGA configuration mode currently in effect.

Presently, the FPGA configuration mode is statically set by the external MSEL pin values and cannot be programmatically overridden by HPS software.

Returns
The current FPGA configuration mode as determined by the MSEL pin values.
ALT_STATUS_CODE alt_fpga_cfg_mode_set ( ALT_FPGA_CFG_MODE_t  cfg_mode)

Sets the FPGA configuration mode.

Presently, the FPGA configuration mode is statically set by the external MSEL pin values and cannot be programmatically overridden by HPS software. This function should always return ALT_E_ERROR at least for Hammerhead-P. This may change with future SoCFPGA devices.

Parameters
cfg_modeThe desired FPGA configuration mode.
Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORFailed to set the FPGA configuration mode.