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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Configuration Monitor (MON) Registers
The Configuration Monitor allows software to poll or be interrupted by changes in the FPGA state. The Configuration Monitor is an instantiation of a Synopsys GPIO. Only registers relevant to the MON operation are shown.
The GPIO inputs are connected to the following signals:[list][*]nSTATUS - Driven to 0 by the FPGA in this device if the FPGA is in Reset Phase or if the FPGA detected an error during the Configuration Phase.[*]CONF_DONE - Driven to 0 by the FPGA in this device during the Reset Phase and driven to 1 when the FPGA Configuration Phase is done.[*]INIT_DONE - Driven to 0 by the FPGA in this device during the Configuration Phase and driven to 1 when the FPGA Initialization Phase is done.[*]CRC_ERROR - CRC error indicator. A CRC_ERROR value of 1 indicates that the FPGA detected a CRC error while in User Mode.[*]CVP_CONF_DONE - Configuration via PCIe done indicator. A CVP_CONF_DONE value of 1 indicates that CVP is done.[*]PR_READY - Partial reconfiguration ready indicator. A PR_READY value of 1 indicates that the FPGA is ready to receive partial reconfiguration or external scrubbing data.[*]PR_ERROR - Partial reconfiguration error indicator. A PR_ERROR value of 1 indicates that the FPGA detected an error during partial reconfiguration or external scrubbing.[*]PR_DONE - Partial reconfiguration done indicator. A PR_DONE value of 1 indicates partial reconfiguration or external scrubbing is done.[*]nCONFIG Pin - Value of the nCONFIG pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the nCONFIG pin. See the description of the nCONFIG field in this register to understand when the FPGA in this device pulls-down the nCONFIG pin. Logic external to this device pulls-down the nCONFIG pin to put the FPGA into the Reset Phase.[*]nSTATUS Pin - Value of the nSTATUS pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the nSTATUS pin. See the description of the nSTATUS field in this register to understand when the FPGA in this device pulls- down the nSTATUS pin. Logic external to this device pulls-down the nSTATUS pin during Configuration Phase or Initialization Phase if it detected an error.[*]CONF_DONE Pin - Value of the CONF_DONE pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the CONF_DONE pin. See the description of the CONF_DONE field in this register to understand when the FPGA in this device pulls-down the CONF_DONE pin. See FPGA documentation to determine how logic external to this device drives CONF_DONE.[*]FPGA_POWER_ON - FPGA powered on indicator
[list][*]0 = FPGA portion of device is powered off.[*]1 = FPGA portion of device is powered on.[/list][/list]
Data Structures | |
struct | ALT_MON_s |
struct | ALT_MON_raw_s |
Typedefs | |
typedef struct ALT_MON_s | ALT_MON_t |
typedef struct ALT_MON_raw_s | ALT_MON_raw_t |
struct ALT_MON_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register group ALT_MON.
Data Fields | ||
---|---|---|
volatile uint32_t | _pad_0x0_0x2f | UNDEFINED |
volatile ALT_MON_GPIO_INTEN_t | gpio_inten | ALT_MON_GPIO_INTEN |
volatile ALT_MON_GPIO_INTMSK_t | gpio_intmask | ALT_MON_GPIO_INTMSK |
volatile ALT_MON_GPIO_INTTYPE_LEVEL_t |
gpio_inttype_level | ALT_MON_GPIO_INTTYPE_LEVEL |
volatile ALT_MON_GPIO_INT_POL_t | gpio_int_polarity | ALT_MON_GPIO_INT_POL |
volatile ALT_MON_GPIO_INTSTAT_t | gpio_intstatus | ALT_MON_GPIO_INTSTAT |
volatile ALT_MON_GPIO_RAW_INTSTAT_t | gpio_raw_intstatus | ALT_MON_GPIO_RAW_INTSTAT |
volatile uint32_t | _pad_0x48_0x4b | UNDEFINED |
volatile ALT_MON_GPIO_PORTA_EOI_t | gpio_porta_eoi | ALT_MON_GPIO_PORTA_EOI |
volatile ALT_MON_GPIO_EXT_PORTA_t | gpio_ext_porta | ALT_MON_GPIO_EXT_PORTA |
volatile uint32_t | _pad_0x54_0x5f | UNDEFINED |
volatile ALT_MON_GPIO_LS_SYNC_t | gpio_ls_sync | ALT_MON_GPIO_LS_SYNC |
volatile uint32_t | _pad_0x64_0x6b | UNDEFINED |
volatile ALT_MON_GPIO_VER_ID_CODE_t | gpio_ver_id_code | ALT_MON_GPIO_VER_ID_CODE |
volatile ALT_MON_GPIO_CFG_REG2_t | gpio_config_reg2 | ALT_MON_GPIO_CFG_REG2 |
volatile ALT_MON_GPIO_CFG_REG1_t | gpio_config_reg1 | ALT_MON_GPIO_CFG_REG1 |
volatile uint32_t | _pad_0x78_0x80 | UNDEFINED |
struct ALT_MON_raw_s |
The struct declaration for the raw register contents of register group ALT_MON.
Data Fields | ||
---|---|---|
volatile uint32_t | _pad_0x0_0x2f | UNDEFINED |
volatile uint32_t | gpio_inten | ALT_MON_GPIO_INTEN |
volatile uint32_t | gpio_intmask | ALT_MON_GPIO_INTMSK |
volatile uint32_t | gpio_inttype_level | ALT_MON_GPIO_INTTYPE_LEVEL |
volatile uint32_t | gpio_int_polarity | ALT_MON_GPIO_INT_POL |
volatile uint32_t | gpio_intstatus | ALT_MON_GPIO_INTSTAT |
volatile uint32_t | gpio_raw_intstatus | ALT_MON_GPIO_RAW_INTSTAT |
volatile uint32_t | _pad_0x48_0x4b | UNDEFINED |
volatile uint32_t | gpio_porta_eoi | ALT_MON_GPIO_PORTA_EOI |
volatile uint32_t | gpio_ext_porta | ALT_MON_GPIO_EXT_PORTA |
volatile uint32_t | _pad_0x54_0x5f | UNDEFINED |
volatile uint32_t | gpio_ls_sync | ALT_MON_GPIO_LS_SYNC |
volatile uint32_t | _pad_0x64_0x6b | UNDEFINED |
volatile uint32_t | gpio_ver_id_code | ALT_MON_GPIO_VER_ID_CODE |
volatile uint32_t | gpio_config_reg2 | ALT_MON_GPIO_CFG_REG2 |
volatile uint32_t | gpio_config_reg1 | ALT_MON_GPIO_CFG_REG1 |
volatile uint32_t | _pad_0x78_0x80 | UNDEFINED |
typedef struct ALT_MON_raw_s ALT_MON_raw_t |
The typedef declaration for the raw register contents of register group ALT_MON.