Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 257 (Layer 4 Address Register 0) - Layer4_Address0

Description

Because the Layer 3 and Layer 4 Address Registers are double-synchronized to the Rx clock domains, then the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Layer 3 and Layer 4 Address Registers are written. For proper synchronization updates, you should perform the consecutive writes to the same Layer 3 and Layer 4 Address Registers after at least four clock cycles delay of the destination clock.

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 Layer 4 Source Port Number Field
[31:16] RW 0x0 Layer 4 Destination Port Number Field

Field : Layer 4 Source Port Number Field - l4sp0

Layer 4 Source Port Number Field

When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 frames.

When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Source Port Number field in the IPv4 or IPv6 frames.

Field Access Macros:

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB   0
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB   15
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH   16
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK   0x0000ffff
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK   0xffff0000
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET   0x0
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : Layer 4 Destination Port Number Field - l4dp0

When Bit 16 (L4PEN0) is reset and Bit 20 (L4DPM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 frames.

When Bit 16 (L4PEN0) and Bit 20 (L4DPM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the UDP Destination Port Number field in the IPv4 or IPv6 frames.

Field Access Macros:

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB   16
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB   31
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH   16
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK   0xffff0000
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK   0x0000ffff
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET   0x0
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_EMAC_GMAC_LYR4_ADDR0_s
 

Macros

#define ALT_EMAC_GMAC_LYR4_ADDR0_OFST   0x404
 
#define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_LYR4_ADDR0_s 
ALT_EMAC_GMAC_LYR4_ADDR0_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_LYR4_ADDR0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_LYR4_ADDR0.

Data Fields
uint32_t l4sp0: 16 Layer 4 Source Port Number Field
uint32_t l4dp0: 16 Layer 4 Destination Port Number Field

Macro Definitions

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_WIDTH   16

The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET_MSK   0x0000ffff

The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_CLR_MSK   0xffff0000

The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 field value from a register.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4SP0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_WIDTH   16

The width in bits of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET_MSK   0xffff0000

The mask used to set the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_CLR_MSK   0x0000ffff

The mask used to clear the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 field value from a register.

#define ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_EMAC_GMAC_LYR4_ADDR0_L4DP0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LYR4_ADDR0_OFST   0x404

The byte offset of the ALT_EMAC_GMAC_LYR4_ADDR0 register from the beginning of the component.

#define ALT_EMAC_GMAC_LYR4_ADDR0_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR4_ADDR0_OFST))

The address of the ALT_EMAC_GMAC_LYR4_ADDR0 register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_LYR4_ADDR0.