Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : MPU Module Reset Register - mpumodrst

Description

The MPUMODRST register is used by software to trigger module resets (individual module reset signals). Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de-asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. For example, software should not assert the module reset to the CPU executing the software.

Software writes a bit to 1 to assert the module reset signal and to 0 to de- assert the module reset signal.

All fields except CPU1 are only reset by a cold reset. The CPU1 field is reset by a cold reset. The CPU1 field is also reset by a warm reset if not masked by the corresponding MPUWARMMASK field.

Register Layout

Bits Access Reset Description
[0] RW 0x0 CPU0
[1] RW 0x1 CPU1
[2] RW 0x0 Watchdogs
[3] RW 0x0 SCU/Peripherals
[4] RW 0x0 L2
[31:5] ??? 0x0 UNDEFINED

Field : CPU0 - cpu0

Resets Cortex-A9 CPU0 in MPU. Whe software changes this field from 0 to 1, ittriggers the following sequence: 1. CPU0 reset is asserted. cpu0 clkoff is de-asserted 2. after 32 osc1_clk cycles, cpu0 clkoff is asserted.

When software changes this field from 1 to 0, it triggers the following sequence: 1.CPU0 reset is de-asserted. 2. after 32 cycles, cpu0 clkoff is de- asserted.

Software needs to wait for at least 64 osc1_clk cycles between each change of this field to keep the proper reset/clkoff sequence.

Field Access Macros:

#define ALT_RSTMGR_MPUMODRST_CPU0_LSB   0
 
#define ALT_RSTMGR_MPUMODRST_CPU0_MSB   0
 
#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH   1
 
#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK   0x00000001
 
#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_MPUMODRST_CPU0_RESET   0x0
 
#define ALT_RSTMGR_MPUMODRST_CPU0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_MPUMODRST_CPU0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : CPU1 - cpu1

Resets Cortex-A9 CPU1 in MPU.

It is reset to 1 on a cold or warm reset. This holds CPU1 in reset until software is ready to release CPU1 from reset by writing 0 to this field.

On single-core devices, writes to this field are ignored.On dual-core devices, writes to this field trigger the same sequence as writes to the CPU0 field (except the sequence is performed on CPU1).

Field Access Macros:

#define ALT_RSTMGR_MPUMODRST_CPU1_LSB   1
 
#define ALT_RSTMGR_MPUMODRST_CPU1_MSB   1
 
#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH   1
 
#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK   0x00000002
 
#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_MPUMODRST_CPU1_RESET   0x1
 
#define ALT_RSTMGR_MPUMODRST_CPU1_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_MPUMODRST_CPU1_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Watchdogs - wds

Resets both per-CPU Watchdog Reset Status registers in MPU.

Field Access Macros:

#define ALT_RSTMGR_MPUMODRST_WDS_LSB   2
 
#define ALT_RSTMGR_MPUMODRST_WDS_MSB   2
 
#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH   1
 
#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK   0x00000004
 
#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_MPUMODRST_WDS_RESET   0x0
 
#define ALT_RSTMGR_MPUMODRST_WDS_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_MPUMODRST_WDS_SET(value)   (((value) << 2) & 0x00000004)
 

Field : SCU/Peripherals - scuper

Resets SCU and peripherals. Peripherals consist of the interrupt controller, global timer, both per-CPU private timers, and both per-CPU watchdogs (except for the Watchdog Reset Status registers).

Field Access Macros:

#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB   3
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB   3
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH   1
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK   0x00000008
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET   0x0
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_MPUMODRST_SCUPER_SET(value)   (((value) << 3) & 0x00000008)
 

Field : L2 - l2

Resets L2 cache controller

Field Access Macros:

#define ALT_RSTMGR_MPUMODRST_L2_LSB   4
 
#define ALT_RSTMGR_MPUMODRST_L2_MSB   4
 
#define ALT_RSTMGR_MPUMODRST_L2_WIDTH   1
 
#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK   0x00000010
 
#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK   0xffffffef
 
#define ALT_RSTMGR_MPUMODRST_L2_RESET   0x0
 
#define ALT_RSTMGR_MPUMODRST_L2_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_RSTMGR_MPUMODRST_L2_SET(value)   (((value) << 4) & 0x00000010)
 

Data Structures

struct  ALT_RSTMGR_MPUMODRST_s
 

Macros

#define ALT_RSTMGR_MPUMODRST_OFST   0x10
 

Typedefs

typedef struct
ALT_RSTMGR_MPUMODRST_s 
ALT_RSTMGR_MPUMODRST_t
 

Data Structure Documentation

struct ALT_RSTMGR_MPUMODRST_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_MPUMODRST.

Data Fields
uint32_t cpu0: 1 CPU0
uint32_t cpu1: 1 CPU1
uint32_t wds: 1 Watchdogs
uint32_t scuper: 1 SCU/Peripherals
uint32_t l2: 1 L2
uint32_t __pad0__: 27 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_MPUMODRST_CPU0_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field.

#define ALT_RSTMGR_MPUMODRST_CPU0_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU0 register field.

#define ALT_RSTMGR_MPUMODRST_CPU0_WIDTH   1

The width in bits of the ALT_RSTMGR_MPUMODRST_CPU0 register field.

#define ALT_RSTMGR_MPUMODRST_CPU0_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_MPUMODRST_CPU0 register field value.

#define ALT_RSTMGR_MPUMODRST_CPU0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU0 register field value.

#define ALT_RSTMGR_MPUMODRST_CPU0_RESET   0x0

The reset value of the ALT_RSTMGR_MPUMODRST_CPU0 register field.

#define ALT_RSTMGR_MPUMODRST_CPU0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_MPUMODRST_CPU0 field value from a register.

#define ALT_RSTMGR_MPUMODRST_CPU0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_MPUMODRST_CPU0 register field value suitable for setting the register.

#define ALT_RSTMGR_MPUMODRST_CPU1_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field.

#define ALT_RSTMGR_MPUMODRST_CPU1_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_CPU1 register field.

#define ALT_RSTMGR_MPUMODRST_CPU1_WIDTH   1

The width in bits of the ALT_RSTMGR_MPUMODRST_CPU1 register field.

#define ALT_RSTMGR_MPUMODRST_CPU1_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_MPUMODRST_CPU1 register field value.

#define ALT_RSTMGR_MPUMODRST_CPU1_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_MPUMODRST_CPU1 register field value.

#define ALT_RSTMGR_MPUMODRST_CPU1_RESET   0x1

The reset value of the ALT_RSTMGR_MPUMODRST_CPU1 register field.

#define ALT_RSTMGR_MPUMODRST_CPU1_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_MPUMODRST_CPU1 field value from a register.

#define ALT_RSTMGR_MPUMODRST_CPU1_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_MPUMODRST_CPU1 register field value suitable for setting the register.

#define ALT_RSTMGR_MPUMODRST_WDS_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field.

#define ALT_RSTMGR_MPUMODRST_WDS_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_WDS register field.

#define ALT_RSTMGR_MPUMODRST_WDS_WIDTH   1

The width in bits of the ALT_RSTMGR_MPUMODRST_WDS register field.

#define ALT_RSTMGR_MPUMODRST_WDS_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_MPUMODRST_WDS register field value.

#define ALT_RSTMGR_MPUMODRST_WDS_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_MPUMODRST_WDS register field value.

#define ALT_RSTMGR_MPUMODRST_WDS_RESET   0x0

The reset value of the ALT_RSTMGR_MPUMODRST_WDS register field.

#define ALT_RSTMGR_MPUMODRST_WDS_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_MPUMODRST_WDS field value from a register.

#define ALT_RSTMGR_MPUMODRST_WDS_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_MPUMODRST_WDS register field value suitable for setting the register.

#define ALT_RSTMGR_MPUMODRST_SCUPER_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field.

#define ALT_RSTMGR_MPUMODRST_SCUPER_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_SCUPER register field.

#define ALT_RSTMGR_MPUMODRST_SCUPER_WIDTH   1

The width in bits of the ALT_RSTMGR_MPUMODRST_SCUPER register field.

#define ALT_RSTMGR_MPUMODRST_SCUPER_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_MPUMODRST_SCUPER register field value.

#define ALT_RSTMGR_MPUMODRST_SCUPER_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_MPUMODRST_SCUPER register field value.

#define ALT_RSTMGR_MPUMODRST_SCUPER_RESET   0x0

The reset value of the ALT_RSTMGR_MPUMODRST_SCUPER register field.

#define ALT_RSTMGR_MPUMODRST_SCUPER_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_MPUMODRST_SCUPER field value from a register.

#define ALT_RSTMGR_MPUMODRST_SCUPER_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_MPUMODRST_SCUPER register field value suitable for setting the register.

#define ALT_RSTMGR_MPUMODRST_L2_LSB   4

The Least Significant Bit (LSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field.

#define ALT_RSTMGR_MPUMODRST_L2_MSB   4

The Most Significant Bit (MSB) position of the ALT_RSTMGR_MPUMODRST_L2 register field.

#define ALT_RSTMGR_MPUMODRST_L2_WIDTH   1

The width in bits of the ALT_RSTMGR_MPUMODRST_L2 register field.

#define ALT_RSTMGR_MPUMODRST_L2_SET_MSK   0x00000010

The mask used to set the ALT_RSTMGR_MPUMODRST_L2 register field value.

#define ALT_RSTMGR_MPUMODRST_L2_CLR_MSK   0xffffffef

The mask used to clear the ALT_RSTMGR_MPUMODRST_L2 register field value.

#define ALT_RSTMGR_MPUMODRST_L2_RESET   0x0

The reset value of the ALT_RSTMGR_MPUMODRST_L2 register field.

#define ALT_RSTMGR_MPUMODRST_L2_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_RSTMGR_MPUMODRST_L2 field value from a register.

#define ALT_RSTMGR_MPUMODRST_L2_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_RSTMGR_MPUMODRST_L2 register field value suitable for setting the register.

#define ALT_RSTMGR_MPUMODRST_OFST   0x10

The byte offset of the ALT_RSTMGR_MPUMODRST register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_MPUMODRST.