Altera SoCAL  16.0
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alt_qspi.h
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32 
35 #ifndef __ALTERA_ALT_QSPI_H__
36 #define __ALTERA_ALT_QSPI_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
97 #define ALT_QSPI_CFG_EN_E_DIS 0x0
98 
103 #define ALT_QSPI_CFG_EN_E_EN 0x1
104 
106 #define ALT_QSPI_CFG_EN_LSB 0
107 
108 #define ALT_QSPI_CFG_EN_MSB 0
109 
110 #define ALT_QSPI_CFG_EN_WIDTH 1
111 
112 #define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
113 
114 #define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
115 
116 #define ALT_QSPI_CFG_EN_RESET 0x0
117 
118 #define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
119 
120 #define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
121 
142 #define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
143 
148 #define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
149 
151 #define ALT_QSPI_CFG_SELCLKPOL_LSB 1
152 
153 #define ALT_QSPI_CFG_SELCLKPOL_MSB 1
154 
155 #define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
156 
157 #define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
158 
159 #define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
160 
161 #define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
162 
163 #define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
164 
165 #define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
166 
188 #define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
189 
194 #define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
195 
197 #define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
198 
199 #define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
200 
201 #define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
202 
203 #define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
204 
205 #define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
206 
207 #define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
208 
209 #define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
210 
211 #define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
212 
236 #define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
237 
242 #define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
243 
245 #define ALT_QSPI_CFG_ENDIRACC_LSB 7
246 
247 #define ALT_QSPI_CFG_ENDIRACC_MSB 7
248 
249 #define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
250 
251 #define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
252 
253 #define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
254 
255 #define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
256 
257 #define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
258 
259 #define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
260 
286 #define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
287 
292 #define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
293 
295 #define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
296 
297 #define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
298 
299 #define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
300 
301 #define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
302 
303 #define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
304 
305 #define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
306 
307 #define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
308 
309 #define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
310 
332 #define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
333 
338 #define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
339 
341 #define ALT_QSPI_CFG_PERSELDEC_LSB 9
342 
343 #define ALT_QSPI_CFG_PERSELDEC_MSB 9
344 
345 #define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
346 
347 #define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
348 
349 #define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
350 
351 #define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
352 
353 #define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
354 
355 #define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
356 
369 #define ALT_QSPI_CFG_PERCSLINES_LSB 10
370 
371 #define ALT_QSPI_CFG_PERCSLINES_MSB 13
372 
373 #define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
374 
375 #define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
376 
377 #define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
378 
379 #define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
380 
381 #define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
382 
383 #define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
384 
407 #define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
408 
413 #define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
414 
416 #define ALT_QSPI_CFG_WP_LSB 14
417 
418 #define ALT_QSPI_CFG_WP_MSB 14
419 
420 #define ALT_QSPI_CFG_WP_WIDTH 1
421 
422 #define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
423 
424 #define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
425 
426 #define ALT_QSPI_CFG_WP_RESET 0x0
427 
428 #define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
429 
430 #define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
431 
453 #define ALT_QSPI_CFG_ENDMA_E_EN 0x1
454 
459 #define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
460 
462 #define ALT_QSPI_CFG_ENDMA_LSB 15
463 
464 #define ALT_QSPI_CFG_ENDMA_MSB 15
465 
466 #define ALT_QSPI_CFG_ENDMA_WIDTH 1
467 
468 #define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
469 
470 #define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
471 
472 #define ALT_QSPI_CFG_ENDMA_RESET 0x0
473 
474 #define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
475 
476 #define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
477 
500 #define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
501 
506 #define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
507 
509 #define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
510 
511 #define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
512 
513 #define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
514 
515 #define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
516 
517 #define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
518 
519 #define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
520 
521 #define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
522 
523 #define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
524 
555 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
556 
561 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
562 
564 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
565 
566 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
567 
568 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
569 
570 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
571 
572 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
573 
574 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
575 
576 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
577 
578 #define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
579 
610 #define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
611 
616 #define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
617 
619 #define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
620 
621 #define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
622 
623 #define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
624 
625 #define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
626 
627 #define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
628 
629 #define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
630 
631 #define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
632 
633 #define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
634 
669 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
670 
675 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
676 
681 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
682 
687 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
688 
693 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
694 
699 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
700 
705 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
706 
711 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
712 
717 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
718 
723 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
724 
729 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
730 
735 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
736 
741 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
742 
747 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
748 
753 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
754 
759 #define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
760 
762 #define ALT_QSPI_CFG_BAUDDIV_LSB 19
763 
764 #define ALT_QSPI_CFG_BAUDDIV_MSB 22
765 
766 #define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
767 
768 #define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
769 
770 #define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
771 
772 #define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
773 
774 #define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
775 
776 #define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
777 
799 #define ALT_QSPI_CFG_IDLE_E_SET 0x1
800 
805 #define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
806 
808 #define ALT_QSPI_CFG_IDLE_LSB 31
809 
810 #define ALT_QSPI_CFG_IDLE_MSB 31
811 
812 #define ALT_QSPI_CFG_IDLE_WIDTH 1
813 
814 #define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
815 
816 #define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
817 
818 #define ALT_QSPI_CFG_IDLE_RESET 0x0
819 
820 #define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
821 
822 #define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
823 
824 #ifndef __ASSEMBLY__
825 
836 {
837  uint32_t en : 1;
838  uint32_t selclkpol : 1;
839  uint32_t selclkphase : 1;
840  uint32_t : 4;
841  uint32_t endiracc : 1;
842  uint32_t enlegacyip : 1;
843  uint32_t perseldec : 1;
844  uint32_t percslines : 4;
845  uint32_t wp : 1;
846  uint32_t endma : 1;
847  uint32_t enahbremap : 1;
848  uint32_t enterxipnextrd : 1;
849  uint32_t enterxipimm : 1;
850  uint32_t bauddiv : 4;
851  uint32_t : 8;
852  const uint32_t idle : 1;
853 };
854 
856 typedef volatile struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t;
857 #endif /* __ASSEMBLY__ */
858 
860 #define ALT_QSPI_CFG_OFST 0x0
861 
902 #define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
903 
908 #define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
909 
911 #define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
912 
913 #define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
914 
915 #define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
916 
917 #define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
918 
919 #define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
920 
921 #define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
922 
923 #define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
924 
925 #define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
926 
954 #define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
955 
961 #define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
962 
968 #define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
969 
971 #define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
972 
973 #define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
974 
975 #define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
976 
977 #define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
978 
979 #define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
980 
981 #define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
982 
983 #define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
984 
985 #define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
986 
1017 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1018 
1025 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1026 
1033 #define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1034 
1036 #define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1037 
1038 #define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1039 
1040 #define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1041 
1042 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1043 
1044 #define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1045 
1046 #define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1047 
1048 #define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1049 
1050 #define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1051 
1082 #define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1083 
1090 #define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1091 
1098 #define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1099 
1101 #define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1102 
1103 #define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1104 
1105 #define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1106 
1107 #define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1108 
1109 #define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1110 
1111 #define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1112 
1113 #define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1114 
1115 #define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1116 
1138 #define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1139 
1144 #define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1145 
1147 #define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1148 
1149 #define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1150 
1151 #define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1152 
1153 #define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1154 
1155 #define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1156 
1157 #define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1158 
1159 #define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1160 
1161 #define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1162 
1172 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1173 
1174 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1175 
1176 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1177 
1178 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1179 
1180 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1181 
1182 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1183 
1184 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1185 
1186 #define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1187 
1188 #ifndef __ASSEMBLY__
1189 
1200 {
1201  uint32_t rdopcode : 8;
1202  uint32_t instwidth : 2;
1203  uint32_t : 2;
1204  uint32_t addrwidth : 2;
1205  uint32_t : 2;
1206  uint32_t datawidth : 2;
1207  uint32_t : 2;
1208  uint32_t enmodebits : 1;
1209  uint32_t : 3;
1210  uint32_t dummyrdclks : 5;
1211  uint32_t : 3;
1212 };
1213 
1215 typedef volatile struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t;
1216 #endif /* __ASSEMBLY__ */
1217 
1219 #define ALT_QSPI_DEVRD_OFST 0x4
1220 
1247 #define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1248 
1249 #define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1250 
1251 #define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1252 
1253 #define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1254 
1255 #define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1256 
1257 #define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1258 
1259 #define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1260 
1261 #define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1262 
1293 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1294 
1301 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1302 
1309 #define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1310 
1312 #define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1313 
1314 #define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1315 
1316 #define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1317 
1318 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1319 
1320 #define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1321 
1322 #define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1323 
1324 #define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1325 
1326 #define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1327 
1358 #define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1359 
1366 #define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1367 
1374 #define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1375 
1377 #define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1378 
1379 #define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1380 
1381 #define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1382 
1383 #define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1384 
1385 #define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1386 
1387 #define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1388 
1389 #define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1390 
1391 #define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1392 
1402 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1403 
1404 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1405 
1406 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1407 
1408 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1409 
1410 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1411 
1412 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1413 
1414 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1415 
1416 #define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1417 
1418 #ifndef __ASSEMBLY__
1419 
1430 {
1431  uint32_t wropcode : 8;
1432  uint32_t : 4;
1433  uint32_t addrwidth : 2;
1434  uint32_t : 2;
1435  uint32_t datawidth : 2;
1436  uint32_t : 6;
1437  uint32_t dummywrclks : 5;
1438  uint32_t : 3;
1439 };
1440 
1442 typedef volatile struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t;
1443 #endif /* __ASSEMBLY__ */
1444 
1446 #define ALT_QSPI_DEVWR_OFST 0x8
1447 
1474 #define ALT_QSPI_DELAY_INIT_LSB 0
1475 
1476 #define ALT_QSPI_DELAY_INIT_MSB 7
1477 
1478 #define ALT_QSPI_DELAY_INIT_WIDTH 8
1479 
1480 #define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1481 
1482 #define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1483 
1484 #define ALT_QSPI_DELAY_INIT_RESET 0x0
1485 
1486 #define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1487 
1488 #define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1489 
1502 #define ALT_QSPI_DELAY_AFTER_LSB 8
1503 
1504 #define ALT_QSPI_DELAY_AFTER_MSB 15
1505 
1506 #define ALT_QSPI_DELAY_AFTER_WIDTH 8
1507 
1508 #define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1509 
1510 #define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1511 
1512 #define ALT_QSPI_DELAY_AFTER_RESET 0x0
1513 
1514 #define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1515 
1516 #define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1517 
1529 #define ALT_QSPI_DELAY_BTWN_LSB 16
1530 
1531 #define ALT_QSPI_DELAY_BTWN_MSB 23
1532 
1533 #define ALT_QSPI_DELAY_BTWN_WIDTH 8
1534 
1535 #define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1536 
1537 #define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1538 
1539 #define ALT_QSPI_DELAY_BTWN_RESET 0x0
1540 
1541 #define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1542 
1543 #define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1544 
1557 #define ALT_QSPI_DELAY_NSS_LSB 24
1558 
1559 #define ALT_QSPI_DELAY_NSS_MSB 31
1560 
1561 #define ALT_QSPI_DELAY_NSS_WIDTH 8
1562 
1563 #define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1564 
1565 #define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1566 
1567 #define ALT_QSPI_DELAY_NSS_RESET 0x0
1568 
1569 #define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1570 
1571 #define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1572 
1573 #ifndef __ASSEMBLY__
1574 
1585 {
1586  uint32_t init : 8;
1587  uint32_t after : 8;
1588  uint32_t btwn : 8;
1589  uint32_t nss : 8;
1590 };
1591 
1593 typedef volatile struct ALT_QSPI_DELAY_s ALT_QSPI_DELAY_t;
1594 #endif /* __ASSEMBLY__ */
1595 
1597 #define ALT_QSPI_DELAY_OFST 0xc
1598 
1631 #define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x0
1632 
1637 #define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x1
1638 
1640 #define ALT_QSPI_RDDATACAP_BYP_LSB 0
1641 
1642 #define ALT_QSPI_RDDATACAP_BYP_MSB 0
1643 
1644 #define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1645 
1646 #define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1647 
1648 #define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1649 
1650 #define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1651 
1652 #define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1653 
1654 #define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1655 
1665 #define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1666 
1667 #define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1668 
1669 #define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1670 
1671 #define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1672 
1673 #define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1674 
1675 #define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1676 
1677 #define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1678 
1679 #define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1680 
1681 #ifndef __ASSEMBLY__
1682 
1693 {
1694  uint32_t byp : 1;
1695  uint32_t delay : 4;
1696  uint32_t : 27;
1697 };
1698 
1701 #endif /* __ASSEMBLY__ */
1702 
1704 #define ALT_QSPI_RDDATACAP_OFST 0x10
1705 
1728 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
1729 
1730 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
1731 
1732 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
1733 
1734 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
1735 
1736 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
1737 
1738 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
1739 
1740 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1741 
1742 #define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
1743 
1754 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
1755 
1756 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
1757 
1758 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
1759 
1760 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
1761 
1762 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
1763 
1764 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
1765 
1766 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
1767 
1768 #define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
1769 
1781 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
1782 
1783 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
1784 
1785 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
1786 
1787 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
1788 
1789 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
1790 
1791 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
1792 
1793 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
1794 
1795 #define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
1796 
1797 #ifndef __ASSEMBLY__
1798 
1809 {
1810  uint32_t numaddrbytes : 4;
1811  uint32_t bytesperdevicepage : 12;
1812  uint32_t bytespersubsector : 5;
1813  uint32_t : 11;
1814 };
1815 
1817 typedef volatile struct ALT_QSPI_DEVSZ_s ALT_QSPI_DEVSZ_t;
1818 #endif /* __ASSEMBLY__ */
1819 
1821 #define ALT_QSPI_DEVSZ_OFST 0x14
1822 
1845 #define ALT_QSPI_SRAMPART_ADDR_LSB 0
1846 
1847 #define ALT_QSPI_SRAMPART_ADDR_MSB 6
1848 
1849 #define ALT_QSPI_SRAMPART_ADDR_WIDTH 7
1850 
1851 #define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x0000007f
1852 
1853 #define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff80
1854 
1855 #define ALT_QSPI_SRAMPART_ADDR_RESET 0x40
1856 
1857 #define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
1858 
1859 #define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x0000007f)
1860 
1861 #ifndef __ASSEMBLY__
1862 
1873 {
1874  uint32_t addr : 7;
1875  uint32_t : 25;
1876 };
1877 
1880 #endif /* __ASSEMBLY__ */
1881 
1883 #define ALT_QSPI_SRAMPART_OFST 0x18
1884 
1907 #define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
1908 
1909 #define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
1910 
1911 #define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
1912 
1913 #define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
1914 
1915 #define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
1916 
1917 #define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
1918 
1919 #define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
1920 
1921 #define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
1922 
1923 #ifndef __ASSEMBLY__
1924 
1935 {
1936  uint32_t addr : 32;
1937 };
1938 
1941 #endif /* __ASSEMBLY__ */
1942 
1944 #define ALT_QSPI_INDADDRTRIG_OFST 0x1c
1945 
1971 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
1972 
1973 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
1974 
1975 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
1976 
1977 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
1978 
1979 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
1980 
1981 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
1982 
1983 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
1984 
1985 #define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
1986 
1999 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2000 
2001 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2002 
2003 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2004 
2005 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2006 
2007 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2008 
2009 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2010 
2011 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2012 
2013 #define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2014 
2015 #ifndef __ASSEMBLY__
2016 
2027 {
2028  uint32_t numsglreqbytes : 4;
2029  uint32_t : 4;
2030  uint32_t numburstreqbytes : 4;
2031  uint32_t : 20;
2032 };
2033 
2035 typedef volatile struct ALT_QSPI_DMAPER_s ALT_QSPI_DMAPER_t;
2036 #endif /* __ASSEMBLY__ */
2037 
2039 #define ALT_QSPI_DMAPER_OFST 0x20
2040 
2064 #define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2065 
2066 #define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2067 
2068 #define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2069 
2070 #define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2071 
2072 #define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2073 
2074 #define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2075 
2076 #define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2077 
2078 #define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2079 
2080 #ifndef __ASSEMBLY__
2081 
2092 {
2093  uint32_t value : 32;
2094 };
2095 
2098 #endif /* __ASSEMBLY__ */
2099 
2101 #define ALT_QSPI_REMAPADDR_OFST 0x24
2102 
2124 #define ALT_QSPI_MODBIT_MOD_LSB 0
2125 
2126 #define ALT_QSPI_MODBIT_MOD_MSB 7
2127 
2128 #define ALT_QSPI_MODBIT_MOD_WIDTH 8
2129 
2130 #define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2131 
2132 #define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2133 
2134 #define ALT_QSPI_MODBIT_MOD_RESET 0x0
2135 
2136 #define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2137 
2138 #define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2139 
2140 #ifndef __ASSEMBLY__
2141 
2152 {
2153  uint32_t mode : 8;
2154  uint32_t : 24;
2155 };
2156 
2158 typedef volatile struct ALT_QSPI_MODBIT_s ALT_QSPI_MODBIT_t;
2159 #endif /* __ASSEMBLY__ */
2160 
2162 #define ALT_QSPI_MODBIT_OFST 0x28
2163 
2182 #define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2183 
2184 #define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2185 
2186 #define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2187 
2188 #define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2189 
2190 #define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2191 
2192 #define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2193 
2194 #define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2195 
2196 #define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2197 
2205 #define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2206 
2207 #define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2208 
2209 #define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2210 
2211 #define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2212 
2213 #define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2214 
2215 #define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2216 
2217 #define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2218 
2219 #define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2220 
2221 #ifndef __ASSEMBLY__
2222 
2233 {
2234  const uint32_t indrdpart : 16;
2235  const uint32_t indwrpart : 16;
2236 };
2237 
2240 #endif /* __ASSEMBLY__ */
2241 
2243 #define ALT_QSPI_SRAMFILL_OFST 0x2c
2244 
2265 #define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2266 
2267 #define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2268 
2269 #define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2270 
2271 #define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2272 
2273 #define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2274 
2275 #define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2276 
2277 #define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2278 
2279 #define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2280 
2281 #ifndef __ASSEMBLY__
2282 
2293 {
2294  uint32_t level : 4;
2295  uint32_t : 28;
2296 };
2297 
2300 #endif /* __ASSEMBLY__ */
2301 
2303 #define ALT_QSPI_TXTHRESH_OFST 0x30
2304 
2327 #define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2328 
2329 #define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2330 
2331 #define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2332 
2333 #define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2334 
2335 #define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2336 
2337 #define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2338 
2339 #define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2340 
2341 #define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2342 
2343 #ifndef __ASSEMBLY__
2344 
2355 {
2356  uint32_t level : 4;
2357  uint32_t : 28;
2358 };
2359 
2362 #endif /* __ASSEMBLY__ */
2363 
2365 #define ALT_QSPI_RXTHRESH_OFST 0x34
2366 
2419 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2420 
2425 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2426 
2428 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2429 
2430 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2431 
2432 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2433 
2434 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2435 
2436 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2437 
2438 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2439 
2440 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2441 
2442 #define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2443 
2464 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2465 
2470 #define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2471 
2473 #define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2474 
2475 #define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2476 
2477 #define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2478 
2479 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2480 
2481 #define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2482 
2483 #define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2484 
2485 #define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2486 
2487 #define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2488 
2510 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
2511 
2516 #define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
2517 
2519 #define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
2520 
2521 #define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
2522 
2523 #define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
2524 
2525 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
2526 
2527 #define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
2528 
2529 #define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
2530 
2531 #define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
2532 
2533 #define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
2534 
2555 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
2556 
2561 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
2562 
2564 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
2565 
2566 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
2567 
2568 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
2569 
2570 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
2571 
2572 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
2573 
2574 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
2575 
2576 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
2577 
2578 #define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
2579 
2601 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
2602 
2607 #define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
2608 
2610 #define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
2611 
2612 #define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
2613 
2614 #define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
2615 
2616 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
2617 
2618 #define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
2619 
2620 #define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
2621 
2622 #define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
2623 
2624 #define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
2625 
2646 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
2647 
2652 #define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
2653 
2655 #define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
2656 
2657 #define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
2658 
2659 #define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
2660 
2661 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
2662 
2663 #define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
2664 
2665 #define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
2666 
2667 #define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
2668 
2669 #define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
2670 
2695 #define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
2696 
2701 #define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
2702 
2704 #define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
2705 
2706 #define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
2707 
2708 #define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
2709 
2710 #define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
2711 
2712 #define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
2713 
2714 #define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
2715 
2716 #define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
2717 
2718 #define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
2719 
2741 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
2742 
2747 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
2748 
2750 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
2751 
2752 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
2753 
2754 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
2755 
2756 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
2757 
2758 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
2759 
2760 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
2761 
2762 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
2763 
2764 #define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
2765 
2787 #define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
2788 
2793 #define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
2794 
2796 #define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
2797 
2798 #define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
2799 
2800 #define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
2801 
2802 #define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
2803 
2804 #define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
2805 
2806 #define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
2807 
2808 #define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
2809 
2810 #define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
2811 
2833 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
2834 
2839 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
2840 
2842 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
2843 
2844 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
2845 
2846 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
2847 
2848 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
2849 
2850 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
2851 
2852 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
2853 
2854 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
2855 
2856 #define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
2857 
2879 #define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
2880 
2885 #define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
2886 
2888 #define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
2889 
2890 #define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
2891 
2892 #define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
2893 
2894 #define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
2895 
2896 #define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
2897 
2898 #define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
2899 
2900 #define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
2901 
2902 #define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
2903 
2925 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
2926 
2931 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
2932 
2934 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
2935 
2936 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
2937 
2938 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
2939 
2940 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
2941 
2942 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
2943 
2944 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
2945 
2946 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
2947 
2948 #define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
2949 
2950 #ifndef __ASSEMBLY__
2951 
2962 {
2963  uint32_t : 1;
2964  uint32_t underflowdet : 1;
2965  uint32_t indopdone : 1;
2966  uint32_t indrdreject : 1;
2967  uint32_t protwrattempt : 1;
2968  uint32_t illegalacc : 1;
2969  uint32_t indxfrlvl : 1;
2970  uint32_t rxover : 1;
2971  uint32_t txthreshcmp : 1;
2972  uint32_t txfull : 1;
2973  uint32_t rxthreshcmp : 1;
2974  uint32_t rxfull : 1;
2975  uint32_t indsramfull : 1;
2976  uint32_t : 19;
2977 };
2978 
2980 typedef volatile struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t;
2981 #endif /* __ASSEMBLY__ */
2982 
2984 #define ALT_QSPI_IRQSTAT_OFST 0x40
2985 
3031 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3032 
3037 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3038 
3040 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3041 
3042 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3043 
3044 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3045 
3046 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3047 
3048 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3049 
3050 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3051 
3052 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3053 
3054 #define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3055 
3074 #define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3075 
3080 #define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3081 
3083 #define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3084 
3085 #define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3086 
3087 #define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3088 
3089 #define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3090 
3091 #define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3092 
3093 #define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3094 
3095 #define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3096 
3097 #define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3098 
3117 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3118 
3123 #define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3124 
3126 #define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3127 
3128 #define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3129 
3130 #define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3131 
3132 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3133 
3134 #define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3135 
3136 #define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3137 
3138 #define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3139 
3140 #define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3141 
3160 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3161 
3166 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3167 
3169 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3170 
3171 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3172 
3173 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3174 
3175 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3176 
3177 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3178 
3179 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3180 
3181 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3182 
3183 #define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3184 
3203 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3204 
3209 #define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3210 
3212 #define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3213 
3214 #define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3215 
3216 #define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3217 
3218 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3219 
3220 #define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3221 
3222 #define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3223 
3224 #define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3225 
3226 #define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3227 
3246 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3247 
3252 #define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3253 
3255 #define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3256 
3257 #define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3258 
3259 #define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3260 
3261 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3262 
3263 #define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3264 
3265 #define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3266 
3267 #define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3268 
3269 #define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3270 
3289 #define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3290 
3295 #define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3296 
3298 #define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3299 
3300 #define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3301 
3302 #define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3303 
3304 #define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3305 
3306 #define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3307 
3308 #define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3309 
3310 #define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3311 
3312 #define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3313 
3332 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3333 
3338 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3339 
3341 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3342 
3343 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3344 
3345 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3346 
3347 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3348 
3349 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3350 
3351 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3352 
3353 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3354 
3355 #define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3356 
3375 #define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3376 
3381 #define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3382 
3384 #define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3385 
3386 #define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3387 
3388 #define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3389 
3390 #define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3391 
3392 #define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3393 
3394 #define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3395 
3396 #define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3397 
3398 #define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3399 
3418 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3419 
3424 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3425 
3427 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3428 
3429 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3430 
3431 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3432 
3433 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3434 
3435 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3436 
3437 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3438 
3439 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3440 
3441 #define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3442 
3461 #define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
3462 
3467 #define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
3468 
3470 #define ALT_QSPI_IRQMSK_RXFULL_LSB 11
3471 
3472 #define ALT_QSPI_IRQMSK_RXFULL_MSB 11
3473 
3474 #define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
3475 
3476 #define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
3477 
3478 #define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
3479 
3480 #define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
3481 
3482 #define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3483 
3484 #define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3485 
3504 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
3505 
3510 #define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
3511 
3513 #define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
3514 
3515 #define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
3516 
3517 #define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
3518 
3519 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
3520 
3521 #define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
3522 
3523 #define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
3524 
3525 #define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3526 
3527 #define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3528 
3529 #ifndef __ASSEMBLY__
3530 
3541 {
3542  uint32_t : 1;
3543  uint32_t underflowdet : 1;
3544  uint32_t indopdone : 1;
3545  uint32_t indrdreject : 1;
3546  uint32_t protwrattempt : 1;
3547  uint32_t illegalacc : 1;
3548  uint32_t indxfrlvl : 1;
3549  uint32_t rxover : 1;
3550  uint32_t txthreshcmp : 1;
3551  uint32_t txfull : 1;
3552  uint32_t rxthreshcmp : 1;
3553  uint32_t rxfull : 1;
3554  uint32_t indsramfull : 1;
3555  uint32_t : 19;
3556 };
3557 
3559 typedef volatile struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t;
3560 #endif /* __ASSEMBLY__ */
3561 
3563 #define ALT_QSPI_IRQMSK_OFST 0x44
3564 
3586 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
3587 
3588 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
3589 
3590 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
3591 
3592 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3593 
3594 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3595 
3596 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
3597 
3598 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3599 
3600 #define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3601 
3602 #ifndef __ASSEMBLY__
3603 
3614 {
3615  uint32_t subsector : 32;
3616 };
3617 
3620 #endif /* __ASSEMBLY__ */
3621 
3623 #define ALT_QSPI_LOWWRPROT_OFST 0x50
3624 
3646 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
3647 
3648 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
3649 
3650 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
3651 
3652 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
3653 
3654 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
3655 
3656 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
3657 
3658 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
3659 
3660 #define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
3661 
3662 #ifndef __ASSEMBLY__
3663 
3674 {
3675  uint32_t subsector : 32;
3676 };
3677 
3680 #endif /* __ASSEMBLY__ */
3681 
3683 #define ALT_QSPI_UPPWRPROT_OFST 0x54
3684 
3721 #define ALT_QSPI_WRPROT_INV_E_EN 0x1
3722 
3727 #define ALT_QSPI_WRPROT_INV_E_DIS 0x0
3728 
3730 #define ALT_QSPI_WRPROT_INV_LSB 0
3731 
3732 #define ALT_QSPI_WRPROT_INV_MSB 0
3733 
3734 #define ALT_QSPI_WRPROT_INV_WIDTH 1
3735 
3736 #define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
3737 
3738 #define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
3739 
3740 #define ALT_QSPI_WRPROT_INV_RESET 0x0
3741 
3742 #define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
3743 
3744 #define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
3745 
3769 #define ALT_QSPI_WRPROT_EN_E_EN 0x1
3770 
3775 #define ALT_QSPI_WRPROT_EN_E_DIS 0x0
3776 
3778 #define ALT_QSPI_WRPROT_EN_LSB 1
3779 
3780 #define ALT_QSPI_WRPROT_EN_MSB 1
3781 
3782 #define ALT_QSPI_WRPROT_EN_WIDTH 1
3783 
3784 #define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
3785 
3786 #define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
3787 
3788 #define ALT_QSPI_WRPROT_EN_RESET 0x0
3789 
3790 #define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
3791 
3792 #define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
3793 
3794 #ifndef __ASSEMBLY__
3795 
3806 {
3807  uint32_t inv : 1;
3808  uint32_t en : 1;
3809  uint32_t : 30;
3810 };
3811 
3813 typedef volatile struct ALT_QSPI_WRPROT_s ALT_QSPI_WRPROT_t;
3814 #endif /* __ASSEMBLY__ */
3815 
3817 #define ALT_QSPI_WRPROT_OFST 0x58
3818 
3858 #define ALT_QSPI_INDRD_START_E_END 0x1
3859 
3864 #define ALT_QSPI_INDRD_START_E_DISD 0x0
3865 
3867 #define ALT_QSPI_INDRD_START_LSB 0
3868 
3869 #define ALT_QSPI_INDRD_START_MSB 0
3870 
3871 #define ALT_QSPI_INDRD_START_WIDTH 1
3872 
3873 #define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
3874 
3875 #define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
3876 
3877 #define ALT_QSPI_INDRD_START_RESET 0x0
3878 
3879 #define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
3880 
3881 #define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
3882 
3903 #define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
3904 
3909 #define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
3910 
3912 #define ALT_QSPI_INDRD_CANCEL_LSB 1
3913 
3914 #define ALT_QSPI_INDRD_CANCEL_MSB 1
3915 
3916 #define ALT_QSPI_INDRD_CANCEL_WIDTH 1
3917 
3918 #define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
3919 
3920 #define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
3921 
3922 #define ALT_QSPI_INDRD_CANCEL_RESET 0x0
3923 
3924 #define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
3925 
3926 #define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
3927 
3948 #define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
3949 
3954 #define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
3955 
3957 #define ALT_QSPI_INDRD_RD_STAT_LSB 2
3958 
3959 #define ALT_QSPI_INDRD_RD_STAT_MSB 2
3960 
3961 #define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
3962 
3963 #define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
3964 
3965 #define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
3966 
3967 #define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
3968 
3969 #define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
3970 
3971 #define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
3972 
3994 #define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
3995 
4000 #define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4001 
4003 #define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4004 
4005 #define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4006 
4007 #define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4008 
4009 #define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4010 
4011 #define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4012 
4013 #define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4014 
4015 #define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4016 
4017 #define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4018 
4039 #define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4040 
4045 #define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4046 
4048 #define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4049 
4050 #define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4051 
4052 #define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4053 
4054 #define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4055 
4056 #define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4057 
4058 #define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4059 
4060 #define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4061 
4062 #define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4063 
4085 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4086 
4091 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4092 
4094 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4095 
4096 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4097 
4098 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4099 
4100 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4101 
4102 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4103 
4104 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4105 
4106 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4107 
4108 #define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4109 
4120 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4121 
4122 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4123 
4124 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4125 
4126 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4127 
4128 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4129 
4130 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4131 
4132 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4133 
4134 #define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4135 
4136 #ifndef __ASSEMBLY__
4137 
4148 {
4149  uint32_t start : 1;
4150  uint32_t cancel : 1;
4151  const uint32_t rd_status : 1;
4152  uint32_t sram_full : 1;
4153  const uint32_t rd_queued : 1;
4154  uint32_t ind_ops_done_status : 1;
4155  const uint32_t num_ind_ops_done : 2;
4156  uint32_t : 24;
4157 };
4158 
4160 typedef volatile struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t;
4161 #endif /* __ASSEMBLY__ */
4162 
4164 #define ALT_QSPI_INDRD_OFST 0x60
4165 
4188 #define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4189 
4190 #define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4191 
4192 #define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4193 
4194 #define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4195 
4196 #define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4197 
4198 #define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4199 
4200 #define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4201 
4202 #define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4203 
4204 #ifndef __ASSEMBLY__
4205 
4216 {
4217  uint32_t level : 32;
4218 };
4219 
4222 #endif /* __ASSEMBLY__ */
4223 
4225 #define ALT_QSPI_INDRDWATER_OFST 0x64
4226 
4247 #define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4248 
4249 #define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4250 
4251 #define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4252 
4253 #define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4254 
4255 #define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4256 
4257 #define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4258 
4259 #define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4260 
4261 #define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4262 
4263 #ifndef __ASSEMBLY__
4264 
4275 {
4276  uint32_t addr : 32;
4277 };
4278 
4281 #endif /* __ASSEMBLY__ */
4282 
4284 #define ALT_QSPI_INDRDSTADDR_OFST 0x68
4285 
4306 #define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4307 
4308 #define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4309 
4310 #define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4311 
4312 #define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4313 
4314 #define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4315 
4316 #define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4317 
4318 #define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4319 
4320 #define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4321 
4322 #ifndef __ASSEMBLY__
4323 
4334 {
4335  uint32_t value : 32;
4336 };
4337 
4340 #endif /* __ASSEMBLY__ */
4341 
4343 #define ALT_QSPI_INDRDCNT_OFST 0x6c
4344 
4384 #define ALT_QSPI_INDWR_START_E_END 0x1
4385 
4390 #define ALT_QSPI_INDWR_START_E_DISD 0x0
4391 
4393 #define ALT_QSPI_INDWR_START_LSB 0
4394 
4395 #define ALT_QSPI_INDWR_START_MSB 0
4396 
4397 #define ALT_QSPI_INDWR_START_WIDTH 1
4398 
4399 #define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
4400 
4401 #define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
4402 
4403 #define ALT_QSPI_INDWR_START_RESET 0x0
4404 
4405 #define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
4406 
4407 #define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
4408 
4429 #define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
4430 
4435 #define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
4436 
4438 #define ALT_QSPI_INDWR_CANCEL_LSB 1
4439 
4440 #define ALT_QSPI_INDWR_CANCEL_MSB 1
4441 
4442 #define ALT_QSPI_INDWR_CANCEL_WIDTH 1
4443 
4444 #define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
4445 
4446 #define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
4447 
4448 #define ALT_QSPI_INDWR_CANCEL_RESET 0x0
4449 
4450 #define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4451 
4452 #define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4453 
4474 #define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
4475 
4480 #define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
4481 
4483 #define ALT_QSPI_INDWR_RDSTAT_LSB 2
4484 
4485 #define ALT_QSPI_INDWR_RDSTAT_MSB 2
4486 
4487 #define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
4488 
4489 #define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
4490 
4491 #define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
4492 
4493 #define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
4494 
4495 #define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
4496 
4497 #define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
4498 
4506 #define ALT_QSPI_INDWR_SRAMFULL_LSB 3
4507 
4508 #define ALT_QSPI_INDWR_SRAMFULL_MSB 3
4509 
4510 #define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1
4511 
4512 #define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008
4513 
4514 #define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7
4515 
4516 #define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0
4517 
4518 #define ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3)
4519 
4520 #define ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008)
4521 
4542 #define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
4543 
4548 #define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
4549 
4551 #define ALT_QSPI_INDWR_RDQUEUED_LSB 4
4552 
4553 #define ALT_QSPI_INDWR_RDQUEUED_MSB 4
4554 
4555 #define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
4556 
4557 #define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
4558 
4559 #define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
4560 
4561 #define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
4562 
4563 #define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
4564 
4565 #define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
4566 
4588 #define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
4589 
4594 #define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
4595 
4597 #define ALT_QSPI_INDWR_INDDONE_LSB 5
4598 
4599 #define ALT_QSPI_INDWR_INDDONE_MSB 5
4600 
4601 #define ALT_QSPI_INDWR_INDDONE_WIDTH 1
4602 
4603 #define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
4604 
4605 #define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
4606 
4607 #define ALT_QSPI_INDWR_INDDONE_RESET 0x0
4608 
4609 #define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
4610 
4611 #define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
4612 
4623 #define ALT_QSPI_INDWR_INDCNT_LSB 6
4624 
4625 #define ALT_QSPI_INDWR_INDCNT_MSB 7
4626 
4627 #define ALT_QSPI_INDWR_INDCNT_WIDTH 2
4628 
4629 #define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
4630 
4631 #define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
4632 
4633 #define ALT_QSPI_INDWR_INDCNT_RESET 0x0
4634 
4635 #define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
4636 
4637 #define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
4638 
4639 #ifndef __ASSEMBLY__
4640 
4651 {
4652  uint32_t start : 1;
4653  uint32_t cancel : 1;
4654  const uint32_t rdstat : 1;
4655  const uint32_t sramfull : 1;
4656  const uint32_t rdqueued : 1;
4657  uint32_t inddone : 1;
4658  const uint32_t indcnt : 2;
4659  uint32_t : 24;
4660 };
4661 
4663 typedef volatile struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t;
4664 #endif /* __ASSEMBLY__ */
4665 
4667 #define ALT_QSPI_INDWR_OFST 0x70
4668 
4691 #define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
4692 
4693 #define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
4694 
4695 #define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
4696 
4697 #define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
4698 
4699 #define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
4700 
4701 #define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
4702 
4703 #define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4704 
4705 #define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4706 
4707 #ifndef __ASSEMBLY__
4708 
4719 {
4720  uint32_t level : 32;
4721 };
4722 
4725 #endif /* __ASSEMBLY__ */
4726 
4728 #define ALT_QSPI_INDWRWATER_OFST 0x74
4729 
4750 #define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
4751 
4752 #define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
4753 
4754 #define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
4755 
4756 #define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
4757 
4758 #define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
4759 
4760 #define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
4761 
4762 #define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4763 
4764 #define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4765 
4766 #ifndef __ASSEMBLY__
4767 
4778 {
4779  uint32_t addr : 32;
4780 };
4781 
4784 #endif /* __ASSEMBLY__ */
4785 
4787 #define ALT_QSPI_INDWRSTADDR_OFST 0x78
4788 
4809 #define ALT_QSPI_INDWRCNT_VALUE_LSB 0
4810 
4811 #define ALT_QSPI_INDWRCNT_VALUE_MSB 31
4812 
4813 #define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
4814 
4815 #define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
4816 
4817 #define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
4818 
4819 #define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
4820 
4821 #define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4822 
4823 #define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4824 
4825 #ifndef __ASSEMBLY__
4826 
4837 {
4838  uint32_t value : 32;
4839 };
4840 
4843 #endif /* __ASSEMBLY__ */
4844 
4846 #define ALT_QSPI_INDWRCNT_OFST 0x7c
4847 
4889 #define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
4890 
4895 #define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
4896 
4898 #define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
4899 
4900 #define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
4901 
4902 #define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
4903 
4904 #define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
4905 
4906 #define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
4907 
4908 #define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
4909 
4910 #define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
4911 
4912 #define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
4913 
4934 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
4935 
4940 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
4941 
4943 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
4944 
4945 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
4946 
4947 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
4948 
4949 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
4950 
4951 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
4952 
4953 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
4954 
4955 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
4956 
4957 #define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
4958 
4969 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
4970 
4971 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
4972 
4973 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
4974 
4975 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
4976 
4977 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
4978 
4979 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
4980 
4981 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
4982 
4983 #define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
4984 
5011 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5012 
5017 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5018 
5023 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5024 
5029 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5030 
5035 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5036 
5041 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5042 
5047 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5048 
5053 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5054 
5056 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5057 
5058 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5059 
5060 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5061 
5062 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5063 
5064 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5065 
5066 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5067 
5068 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5069 
5070 #define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5071 
5093 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5094 
5099 #define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5100 
5102 #define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5103 
5104 #define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5105 
5106 #define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5107 
5108 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5109 
5110 #define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5111 
5112 #define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5113 
5114 #define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5115 
5116 #define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5117 
5143 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5144 
5149 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5150 
5155 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5156 
5161 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5162 
5164 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5165 
5166 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5167 
5168 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5169 
5170 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5171 
5172 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5173 
5174 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5175 
5176 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5177 
5178 #define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5179 
5201 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5202 
5207 #define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5208 
5210 #define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5211 
5212 #define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5213 
5214 #define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5215 
5216 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5217 
5218 #define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5219 
5220 #define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5221 
5222 #define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5223 
5224 #define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5225 
5247 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5248 
5253 #define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5254 
5256 #define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5257 
5258 #define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5259 
5260 #define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5261 
5262 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5263 
5264 #define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5265 
5266 #define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5267 
5268 #define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5269 
5270 #define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5271 
5299 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
5300 
5305 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
5306 
5311 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
5312 
5317 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
5318 
5323 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
5324 
5329 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
5330 
5335 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
5336 
5341 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
5342 
5344 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
5345 
5346 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
5347 
5348 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
5349 
5350 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
5351 
5352 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
5353 
5354 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
5355 
5356 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
5357 
5358 #define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
5359 
5381 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
5382 
5387 #define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
5388 
5390 #define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
5391 
5392 #define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
5393 
5394 #define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
5395 
5396 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
5397 
5398 #define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
5399 
5400 #define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
5401 
5402 #define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
5403 
5404 #define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
5405 
5425 #define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
5426 
5427 #define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
5428 
5429 #define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
5430 
5431 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
5432 
5433 #define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
5434 
5435 #define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
5436 
5437 #define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
5438 
5439 #define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
5440 
5441 #ifndef __ASSEMBLY__
5442 
5453 {
5454  uint32_t execcmd : 1;
5455  const uint32_t cmdexecstat : 1;
5456  uint32_t : 5;
5457  uint32_t numdummybytes : 5;
5458  uint32_t numwrdatabytes : 3;
5459  uint32_t enwrdata : 1;
5460  uint32_t numaddrbytes : 2;
5461  uint32_t enmodebit : 1;
5462  uint32_t encmdaddr : 1;
5463  uint32_t numrddatabytes : 3;
5464  uint32_t enrddata : 1;
5465  uint32_t cmdopcode : 8;
5466 };
5467 
5469 typedef volatile struct ALT_QSPI_FLSHCMD_s ALT_QSPI_FLSHCMD_t;
5470 #endif /* __ASSEMBLY__ */
5471 
5473 #define ALT_QSPI_FLSHCMD_OFST 0x90
5474 
5497 #define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
5498 
5499 #define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
5500 
5501 #define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
5502 
5503 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
5504 
5505 #define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
5506 
5507 #define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
5508 
5509 #define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5510 
5511 #define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5512 
5513 #ifndef __ASSEMBLY__
5514 
5525 {
5526  uint32_t addr : 32;
5527 };
5528 
5531 #endif /* __ASSEMBLY__ */
5532 
5534 #define ALT_QSPI_FLSHCMDADDR_OFST 0x94
5535 
5558 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
5559 
5560 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
5561 
5562 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
5563 
5564 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
5565 
5566 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
5567 
5568 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
5569 
5570 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5571 
5572 #define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5573 
5574 #ifndef __ASSEMBLY__
5575 
5586 {
5587  uint32_t data : 32;
5588 };
5589 
5592 #endif /* __ASSEMBLY__ */
5593 
5595 #define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
5596 
5621 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
5622 
5623 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
5624 
5625 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
5626 
5627 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
5628 
5629 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
5630 
5631 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
5632 
5633 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5634 
5635 #define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5636 
5637 #ifndef __ASSEMBLY__
5638 
5649 {
5650  uint32_t data : 32;
5651 };
5652 
5655 #endif /* __ASSEMBLY__ */
5656 
5658 #define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
5659 
5683 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
5684 
5685 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
5686 
5687 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
5688 
5689 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
5690 
5691 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
5692 
5693 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
5694 
5695 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5696 
5697 #define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
5698 
5699 #ifndef __ASSEMBLY__
5700 
5711 {
5712  uint32_t data : 32;
5713 };
5714 
5717 #endif /* __ASSEMBLY__ */
5718 
5720 #define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
5721 
5745 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
5746 
5747 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
5748 
5749 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
5750 
5751 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
5752 
5753 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
5754 
5755 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
5756 
5757 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
5758 
5759 #define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
5760 
5761 #ifndef __ASSEMBLY__
5762 
5773 {
5774  uint32_t data : 32;
5775 };
5776 
5779 #endif /* __ASSEMBLY__ */
5780 
5782 #define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
5783 
5802 #define ALT_QSPI_MODULEID_VALUE_LSB 0
5803 
5804 #define ALT_QSPI_MODULEID_VALUE_MSB 24
5805 
5806 #define ALT_QSPI_MODULEID_VALUE_WIDTH 25
5807 
5808 #define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
5809 
5810 #define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
5811 
5812 #define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
5813 
5814 #define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
5815 
5816 #define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
5817 
5818 #ifndef __ASSEMBLY__
5819 
5830 {
5831  const uint32_t value : 25;
5832  uint32_t : 7;
5833 };
5834 
5837 #endif /* __ASSEMBLY__ */
5838 
5840 #define ALT_QSPI_MODULEID_OFST 0xfc
5841 
5842 #ifndef __ASSEMBLY__
5843 
5854 {
5855  volatile ALT_QSPI_CFG_t cfg;
5869  volatile uint32_t _pad_0x38_0x3f[2];
5872  volatile uint32_t _pad_0x48_0x4f[2];
5876  volatile uint32_t _pad_0x5c_0x5f;
5885  volatile uint32_t _pad_0x80_0x8f[4];
5888  volatile uint32_t _pad_0x98_0x9f[2];
5893  volatile uint32_t _pad_0xb0_0xfb[19];
5895 };
5896 
5898 typedef volatile struct ALT_QSPI_s ALT_QSPI_t;
5901 {
5902  volatile uint32_t cfg;
5903  volatile uint32_t devrd;
5904  volatile uint32_t devwr;
5905  volatile uint32_t delay;
5906  volatile uint32_t rddatacap;
5907  volatile uint32_t devsz;
5908  volatile uint32_t srampart;
5909  volatile uint32_t indaddrtrig;
5910  volatile uint32_t dmaper;
5911  volatile uint32_t remapaddr;
5912  volatile uint32_t modebit;
5913  volatile uint32_t sramfill;
5914  volatile uint32_t txthresh;
5915  volatile uint32_t rxthresh;
5916  volatile uint32_t _pad_0x38_0x3f[2];
5917  volatile uint32_t irqstat;
5918  volatile uint32_t irqmask;
5919  volatile uint32_t _pad_0x48_0x4f[2];
5920  volatile uint32_t lowwrprot;
5921  volatile uint32_t uppwrprot;
5922  volatile uint32_t wrprot;
5923  volatile uint32_t _pad_0x5c_0x5f;
5924  volatile uint32_t indrd;
5925  volatile uint32_t indrdwater;
5926  volatile uint32_t indrdstaddr;
5927  volatile uint32_t indrdcnt;
5928  volatile uint32_t indwr;
5929  volatile uint32_t indwrwater;
5930  volatile uint32_t indwrstaddr;
5931  volatile uint32_t indwrcnt;
5932  volatile uint32_t _pad_0x80_0x8f[4];
5933  volatile uint32_t flashcmd;
5934  volatile uint32_t flashcmdaddr;
5935  volatile uint32_t _pad_0x98_0x9f[2];
5936  volatile uint32_t flashcmdrddatalo;
5937  volatile uint32_t flashcmdrddataup;
5938  volatile uint32_t flashcmdwrdatalo;
5939  volatile uint32_t flashcmdwrdataup;
5940  volatile uint32_t _pad_0xb0_0xfb[19];
5941  volatile uint32_t moduleid;
5942 };
5943 
5945 typedef volatile struct ALT_QSPI_raw_s ALT_QSPI_raw_t;
5946 #endif /* __ASSEMBLY__ */
5947 
5949 #ifdef __cplusplus
5950 }
5951 #endif /* __cplusplus */
5952 #endif /* __ALTERA_ALT_QSPI_H__ */
5953