Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : RX FIFO Read - jtag_data_r

Description

A read to this field initiates a read to the RxFifo. Please note that the read always returns a 16 bit value. If the received number of bits are not aligned with 16, lower most n bits should be ignored by software. For example in the case of 6 bits received, rdata[15:10] will contain received bits and rdata[9:0] should be ignored. A read of the fifo while empty is not defined.

Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the FIFOs. If you have more than 128 bits to be transferred, and want continuous transfer software should make sure proper data flow to avoid a Tx-Fifo under-run or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx- Fifo under-run will stop the transfer, and will stop the TCK toggles, till another transfer is initiated by software.

At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1 word of data

At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1 word of data.

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 TDI Data
[31:16] RW 0x0 ALT_FPGAMGR_JTAG_DATA_R_RSVD

Field : TDI Data - tdiData

Field Access Macros:

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_LSB   0
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_MSB   15
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_WIDTH   16
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET_MSK   0x0000ffff
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_CLR_MSK   0xffff0000
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_RESET   0x0
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : Reserved

Field Access Macros:

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_LSB   16
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_MSB   31
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_WIDTH   16
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET_MSK   0xffff0000
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_CLR_MSK   0x0000ffff
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_RESET   0x0
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_FPGAMGR_JTAG_DATA_R_s
 

Macros

#define ALT_FPGAMGR_JTAG_DATA_R_RESET   0x00000000
 
#define ALT_FPGAMGR_JTAG_DATA_R_OFST   0x64
 

Typedefs

typedef struct
ALT_FPGAMGR_JTAG_DATA_R_s 
ALT_FPGAMGR_JTAG_DATA_R_t
 

Data Structure Documentation

struct ALT_FPGAMGR_JTAG_DATA_R_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_FPGAMGR_JTAG_DATA_R.

Data Fields
uint32_t tdiData: 16 TDI Data
uint32_t Reserved: 16 ALT_FPGAMGR_JTAG_DATA_R_RSVD

Macro Definitions

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_LSB   0

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_MSB   15

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_WIDTH   16

The width in bits of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET_MSK   0x0000ffff

The mask used to set the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_CLR_MSK   0xffff0000

The mask used to clear the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_RESET   0x0

The reset value of the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_FPGAMGR_JTAG_DATA_R_TDIDATA field value from a register.

#define ALT_FPGAMGR_JTAG_DATA_R_TDIDATA_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_FPGAMGR_JTAG_DATA_R_TDIDATA register field value suitable for setting the register.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_LSB   16

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_MSB   31

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_WIDTH   16

The width in bits of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET_MSK   0xffff0000

The mask used to set the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_CLR_MSK   0x0000ffff

The mask used to clear the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_RESET   0x0

The reset value of the ALT_FPGAMGR_JTAG_DATA_R_RSVD register field.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_FPGAMGR_JTAG_DATA_R_RSVD field value from a register.

#define ALT_FPGAMGR_JTAG_DATA_R_RSVD_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_FPGAMGR_JTAG_DATA_R_RSVD register field value suitable for setting the register.

#define ALT_FPGAMGR_JTAG_DATA_R_RESET   0x00000000

The reset value of the ALT_FPGAMGR_JTAG_DATA_R register.

#define ALT_FPGAMGR_JTAG_DATA_R_OFST   0x64

The byte offset of the ALT_FPGAMGR_JTAG_DATA_R register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_FPGAMGR_JTAG_DATA_R.