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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The Controller Configuration Register determines the behavior of the controller.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[2:0] | RW | Unknown | DRAM Memory Type |
[7:3] | RW | Unknown | DRAM Memory Burst Length |
[9:8] | RW | Unknown | Address Interleaving Order |
[10] | RW | Unknown | ECC Enable |
[11] | RW | Unknown | ECC Auto-Correction Enable |
[12] | RW | Unknown | TBD |
[13] | RW | Unknown | Generate Single Bit Errors |
[14] | RW | Unknown | Generate Double Bit Errors |
[15] | RW | Unknown | Command Reorder Enable |
[21:16] | RW | Unknown | Starvation Limit |
[22] | RW | Unknown | DQS Tracking Enable |
[23] | RW | Unknown | No DM Pins Present |
[24] | RW | Unknown | Burst Interrupt Enable |
[25] | RW | Unknown | Burst Terminate Enable |
[31:26] | ??? | Unknown | UNDEFINED |
Field : DRAM Memory Type - memtype | |
Selects memory type. Program this field with one of the following binary values, "001" for DDR2 SDRAM, "010" for DDR3 SDRAM, "011" for LPDDR1 SDRAM or "100" for LPDDR2 SDRAM. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0) |
#define | ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007) |
Field : DRAM Memory Burst Length - membl | |
Configures burst length as a static decimal value. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, this should be programmed with 8 (binary "01000"), for DDR2 it can be either 4 or 8 depending on the exact DRAM chip. LPDDR2 can be programmed with 4, 8, or 16 and LPDDR can be programmed with 2, 4, or 8. You must also program the membl field in the staticcfg register. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3) |
#define | ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8) |
Field : Address Interleaving Order - addrorder | |
Selects the order for address interleaving. Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering. "00" - chip, row, bank, column, "01" - chip, bank, row, column, "10"-row, chip, bank, column Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8) |
#define | ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300) |
Field : ECC Enable - eccen | |
Enable the generation and checking of ECC. This bit must only be set if the memory connected to the SDRAM interface is 24 or 40 bits wide. If you set this, you must clear the useeccasdata field in the staticcfg register. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400) |
Field : ECC Auto-Correction Enable - ecccorren | |
Enable auto correction of the read data returned when single bit error is detected. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800) |
Field : TBD - cfg_enable_ecc_code_overwrites | |
Set to a one to enable ECC overwrites. ECC overwrites occur when a correctable ECC error is seen and cause a new read/modify/write to be scheduled for that location to clear the ECC error. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000) |
Field : Generate Single Bit Errors - gensbe | |
Enable the deliberate insertion of single bit errors in data written to memory. This should only be used for testing purposes. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000) |
Field : Generate Double Bit Errors - gendbe | |
Enable the deliberate insertion of double bit errors in data written to memory. This should only be used for testing purposes. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000) |
Field : Command Reorder Enable - reorderen | |
This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth. It should generally be set to a one. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000) |
Field : Starvation Limit - starvelimit | |
Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16) |
#define | ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000) |
Field : DQS Tracking Enable - dqstrken | |
Enables DQS tracking in the PHY. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000) |
Field : No DM Pins Present - nodmpins | |
Set to a one to enable DRAM operation if no DM pins are connected. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000) |
Field : Burst Interrupt Enable - burstintren | |
Set to a one to enable the controller to issue burst interrupt commands. This must only be set when the DRAM memory type is LPDDR2. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000) |
Field : Burst Terminate Enable - bursttermen | |
Set to a one to enable the controller to issue burst terminate commands. This must only be set when the DRAM memory type is LPDDR2. Field Access Macros: | |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000) |
Data Structures | |
struct | ALT_SDR_CTL_CTLCFG_s |
Macros | |
#define | ALT_SDR_CTL_CTLCFG_OFST 0x0 |
Typedefs | |
typedef struct ALT_SDR_CTL_CTLCFG_s | ALT_SDR_CTL_CTLCFG_t |
struct ALT_SDR_CTL_CTLCFG_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_CTLCFG.
Data Fields | ||
---|---|---|
uint32_t | memtype: 3 | DRAM Memory Type |
uint32_t | membl: 5 | DRAM Memory Burst Length |
uint32_t | addrorder: 2 | Address Interleaving Order |
uint32_t | eccen: 1 | ECC Enable |
uint32_t | ecccorren: 1 | ECC Auto-Correction Enable |
uint32_t | cfg_enable_ecc_code_overwrites: 1 | TBD |
uint32_t | gensbe: 1 | Generate Single Bit Errors |
uint32_t | gendbe: 1 | Generate Double Bit Errors |
uint32_t | reorderen: 1 | Command Reorder Enable |
uint32_t | starvelimit: 6 | Starvation Limit |
uint32_t | dqstrken: 1 | DQS Tracking Enable |
uint32_t | nodmpins: 1 | No DM Pins Present |
uint32_t | burstintren: 1 | Burst Interrupt Enable |
uint32_t | bursttermen: 1 | Burst Terminate Enable |
uint32_t | __pad0__: 6 | UNDEFINED |
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3 |
The width in bits of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007 |
The mask used to set the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8 |
The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMTYPE register field value.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_MEMTYPE register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET | ( | value | ) | (((value) & 0x00000007) >> 0) |
Extracts the ALT_SDR_CTL_CTLCFG_MEMTYPE field value from a register.
#define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET | ( | value | ) | (((value) << 0) & 0x00000007) |
Produces a ALT_SDR_CTL_CTLCFG_MEMTYPE register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field.
#define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_MEMBL register field.
#define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5 |
The width in bits of the ALT_SDR_CTL_CTLCFG_MEMBL register field.
#define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8 |
The mask used to set the ALT_SDR_CTL_CTLCFG_MEMBL register field value.
#define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07 |
The mask used to clear the ALT_SDR_CTL_CTLCFG_MEMBL register field value.
#define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_MEMBL register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_MEMBL_GET | ( | value | ) | (((value) & 0x000000f8) >> 3) |
Extracts the ALT_SDR_CTL_CTLCFG_MEMBL field value from a register.
#define ALT_SDR_CTL_CTLCFG_MEMBL_SET | ( | value | ) | (((value) << 3) & 0x000000f8) |
Produces a ALT_SDR_CTL_CTLCFG_MEMBL register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2 |
The width in bits of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300 |
The mask used to set the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_ADDRORDER register field value.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_ADDRORDER register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_SDR_CTL_CTLCFG_ADDRORDER field value from a register.
#define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_SDR_CTL_CTLCFG_ADDRORDER register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field.
#define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCEN register field.
#define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_ECCEN register field.
#define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400 |
The mask used to set the ALT_SDR_CTL_CTLCFG_ECCEN register field value.
#define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCEN register field value.
#define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_ECCEN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_ECCEN_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_SDR_CTL_CTLCFG_ECCEN field value from a register.
#define ALT_SDR_CTL_CTLCFG_ECCEN_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_SDR_CTL_CTLCFG_ECCEN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800 |
The mask used to set the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_ECCCORREN register field value.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_ECCCORREN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_SDR_CTL_CTLCFG_ECCCORREN field value from a register.
#define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_SDR_CTL_CTLCFG_ECCCORREN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS field value from a register.
#define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field.
#define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENSBE register field.
#define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_GENSBE register field.
#define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_GENSBE register field value.
#define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_GENSBE register field value.
#define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_GENSBE register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_GENSBE_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_SDR_CTL_CTLCFG_GENSBE field value from a register.
#define ALT_SDR_CTL_CTLCFG_GENSBE_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_SDR_CTL_CTLCFG_GENSBE register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field.
#define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_GENDBE register field.
#define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_GENDBE register field.
#define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_GENDBE register field value.
#define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_GENDBE register field value.
#define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_GENDBE register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_GENDBE_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_SDR_CTL_CTLCFG_GENDBE field value from a register.
#define ALT_SDR_CTL_CTLCFG_GENDBE_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_SDR_CTL_CTLCFG_GENDBE register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_REORDEREN register field.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_REORDEREN register field.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_REORDEREN register field value.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_REORDEREN register field value.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_REORDEREN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_SDR_CTL_CTLCFG_REORDEREN field value from a register.
#define ALT_SDR_CTL_CTLCFG_REORDEREN_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_SDR_CTL_CTLCFG_REORDEREN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6 |
The width in bits of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_STARVELIMIT register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET | ( | value | ) | (((value) & 0x003f0000) >> 16) |
Extracts the ALT_SDR_CTL_CTLCFG_STARVELIMIT field value from a register.
#define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET | ( | value | ) | (((value) << 16) & 0x003f0000) |
Produces a ALT_SDR_CTL_CTLCFG_STARVELIMIT register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_DQSTRKEN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_SDR_CTL_CTLCFG_DQSTRKEN field value from a register.
#define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_SDR_CTL_CTLCFG_DQSTRKEN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_NODMPINS register field.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_NODMPINS register field.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_NODMPINS register field value.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_NODMPINS register field value.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_NODMPINS register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_SDR_CTL_CTLCFG_NODMPINS field value from a register.
#define ALT_SDR_CTL_CTLCFG_NODMPINS_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_SDR_CTL_CTLCFG_NODMPINS register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_BURSTINTREN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_SDR_CTL_CTLCFG_BURSTINTREN field value from a register.
#define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_SDR_CTL_CTLCFG_BURSTINTREN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000 |
The mask used to set the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field is UNKNOWN.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_SDR_CTL_CTLCFG_BURSTTERMEN field value from a register.
#define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_SDR_CTL_CTLCFG_BURSTTERMEN register field value suitable for setting the register.
#define ALT_SDR_CTL_CTLCFG_OFST 0x0 |
The byte offset of the ALT_SDR_CTL_CTLCFG register from the beginning of the component.
typedef struct ALT_SDR_CTL_CTLCFG_s ALT_SDR_CTL_CTLCFG_t |
The typedef declaration for register ALT_SDR_CTL_CTLCFG.