Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 6 (Flow Control Register) - Flow_Control

Description

The Flow Control register controls the generation and reception of the Control (Pause Command) frames by the MAC's Flow control block. A Write to a register with the Busy bit set to '1' triggers the Flow Control block to generate a Pause Control frame. The fields of the control frame are selected as specified in the 802.3x specification, and the Pause Time value from this register is used in the Pause Time field of the control frame. The Busy bit remains set until the control frame is transferred onto the cable. The Host must make sure that the Busy bit is cleared before writing to the register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Flow Control Busy or Backpressure Activate
[1] RW 0x0 Transmit Flow Control Enable
[2] RW 0x0 Receive Flow Control Enable
[3] RW 0x0 Unicast Pause Frame Detect
[5:4] RW 0x0 Pause Low Threshold
[6] ??? 0x0 UNDEFINED
[7] RW 0x0 Disable Zero-Quanta Pause
[15:8] ??? 0x0 UNDEFINED
[31:16] RW 0x0 Pause Time

Field : Flow Control Busy or Backpressure Activate - fca_bpa

This bit initiates a Pause Control frame in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set.

In the full-duplex mode, this bit should be read as 1'b0 before writing to the Flow Control register. To initiate a Pause control frame, the Application must set this bit to 1'b1. During a transfer of the Control Frame, this bit continues to be set to signify that a frame transmission is in progress. After the completion of Pause control frame transmission, the MAC resets this bit to 1'b0. The Flow Control register should not be written to until this bit is cleared.

In the half-duplex mode, when this bit is set (and TFE is set), then backpressure is asserted by the MAC. During backpressure, when the MAC receives a new frame, the transmitter starts sending a JAM pattern resulting in a collision. This control register bit is logically ORed with the mti_flowctrl_i input signal for the backpressure function. When the MAC is configured for the full-duplex mode, the BPA is automatically disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD 0x0 Pause Ctrl Frame and BPA off
ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END 0x1 Init Pause Ctrl Frame and BPA

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB   0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB   0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit Flow Control Enable - tfe

In the full-duplex mode, when this bit is set, the MAC enables the flow control operation to transmit Pause frames. When this bit is reset, the flow control operation in the MAC is disabled, and the MAC does not transmit any Pause frames.

In half-duplex mode, when this bit is set, the MAC enables the back-pressure operation. When this bit is reset, the back-pressure feature is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD 0x0 Transmit Flow Control Disable
ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END 0x1 Transmit Flow Control Enable

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Receive Flow Control Enable - rfe

When this bit is set, the MAC decodes the received Pause frame and disables its transmitter for a specified (Pause) time. When this bit is reset, the decode function of the Pause frame is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD 0x0 Decode Func. of Pause Frame Disabled
ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END 0x1 MAC decodes the received Pause

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Unicast Pause Frame Detect - up

When this bit is set, then in addition to the detecting Pause frames with the unique multicast address, the MAC detects the Pause frames with the station's unicast address specified in the MAC Address0 High Register and MAC Address0 Low Register. When this bit is reset, the MAC detects only a Pause frame with the unique multicast address specified in the 802.3x standard.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD 0x0 MAC Detects Pause MCA
ALT_EMAC_GMAC_FLOW_CTL_UP_E_END 0x1 MAC Detects Pause MCA and UCA

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB   3
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB   3
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Pause Low Threshold - plt

This field configures the threshold of the PAUSE timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of PAUSE Frame.

The threshold values should be always less than the Pause Time configured in Bits[31:16]. For example, if PT = 100H (256 slot-times), and PLT = 01, then a second PAUSE frame is automatically transmitted if the mti_flowctrl_i signal is asserted at 228 (256 - 28) slot times after the first PAUSE frame is transmitted.

The slot time is defined as the time taken to transmit 512 bits (64 bytes) on the GMII or MII interface.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4 0x0 Pause time - 4 slot times
ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28 0x1 Pause time - 28 slot times
ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144 0x2 Pause time - 144 slot times
ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256 0x3 Pause time - 256 slot times

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144   0x2
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256   0x3
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB   4
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB   5
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH   2
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK   0x00000030
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK   0xffffffcf
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET(value)   (((value) << 4) & 0x00000030)
 

Field : Disable Zero-Quanta Pause - dzpq

When this bit is set, it disables the automatic generation of the Zero-Quanta Pause Control frames on the de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i/mti_flowctrl_i).

When this bit is reset, normal operation with automatic Zero-Quanta Pause Control frame generation is enabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END 0x1 Disable Auto Gen. of Zero-Quanta Pause
ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD 0x0 Enable Auto Gen. of Zero-Quanta Pause

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END   0x1
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB   7
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB   7
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH   1
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Pause Time - pt

This field holds the value to be used in the Pause Time field in the transmit control frame. Because the Pause Time bits are double-synchronized to the (G)MII clock domain, then consecutive writes to this register should be performed only after at least four clock cycles in the destination clock domain.

Field Access Macros:

#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB   16
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB   31
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH   16
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK   0xffff0000
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK   0x0000ffff
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET   0x0
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_EMAC_GMAC_FLOW_CTL_s
 

Macros

#define ALT_EMAC_GMAC_FLOW_CTL_OFST   0x18
 
#define ALT_EMAC_GMAC_FLOW_CTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_FLOW_CTL_s 
ALT_EMAC_GMAC_FLOW_CTL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_FLOW_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_FLOW_CTL.

Data Fields
uint32_t fca_bpa: 1 Flow Control Busy or Backpressure Activate
uint32_t tfe: 1 Transmit Flow Control Enable
uint32_t rfe: 1 Receive Flow Control Enable
uint32_t up: 1 Unicast Pause Frame Detect
uint32_t plt: 2 Pause Low Threshold
uint32_t __pad0__: 1 UNDEFINED
uint32_t dzpq: 1 Disable Zero-Quanta Pause
uint32_t __pad1__: 8 UNDEFINED
uint32_t pt: 16 Pause Time

Macro Definitions

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA

Pause Ctrl Frame and BPA off

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA

Init Pause Ctrl Frame and BPA

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_FLOW_CTL_FCA_BPA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE

Transmit Flow Control Disable

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_TFE

Transmit Flow Control Enable

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_TFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_TFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_TFE field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_TFE_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_FLOW_CTL_TFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE

Decode Func. of Pause Frame Disabled

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_RFE

MAC decodes the received Pause

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_RFE register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_RFE register field.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_RFE field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_RFE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_FLOW_CTL_RFE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP

MAC Detects Pause MCA

#define ALT_EMAC_GMAC_FLOW_CTL_UP_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_UP

MAC Detects Pause MCA and UCA

#define ALT_EMAC_GMAC_FLOW_CTL_UP_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_UP register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_UP register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_UP register field.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_UP field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_UP_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_FLOW_CTL_UP register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_4   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

Pause time - 4 slot times

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_28   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

Pause time - 28 slot times

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_144   0x2

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

Pause time - 144 slot times

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_E_PAUSETIME_256   0x3

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_PLT

Pause time - 256 slot times

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET_MSK   0x00000030

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_CLR_MSK   0xffffffcf

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PLT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PLT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_PLT field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_PLT_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_EMAC_GMAC_FLOW_CTL_PLT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ

Disable Auto Gen. of Zero-Quanta Pause

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_FLOW_CTL_DZPQ

Enable Auto Gen. of Zero-Quanta Pause

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_DZPQ field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_DZPQ_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_FLOW_CTL_DZPQ register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_WIDTH   16

The width in bits of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET_MSK   0xffff0000

The mask used to set the ALT_EMAC_GMAC_FLOW_CTL_PT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_CLR_MSK   0x0000ffff

The mask used to clear the ALT_EMAC_GMAC_FLOW_CTL_PT register field value.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_FLOW_CTL_PT register field.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_EMAC_GMAC_FLOW_CTL_PT field value from a register.

#define ALT_EMAC_GMAC_FLOW_CTL_PT_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_EMAC_GMAC_FLOW_CTL_PT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_FLOW_CTL_OFST   0x18

The byte offset of the ALT_EMAC_GMAC_FLOW_CTL register from the beginning of the component.

#define ALT_EMAC_GMAC_FLOW_CTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_FLOW_CTL_OFST))

The address of the ALT_EMAC_GMAC_FLOW_CTL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_FLOW_CTL.