Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : DRAM Timings 3 Register - dramtiming3

Description

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.

Register Layout

Bits Access Reset Description
[3:0] RW Unknown Read to Precharge Time
[8:4] RW Unknown Activate to Precharge Time
[14:9] RW Unknown Row Cycle Time
[18:15] RW Unknown Mode Register Programming Delay
[22:19] RW Unknown CAS to CAS Delay
[31:23] ??? 0x0 UNDEFINED

Field : Read to Precharge Time - trtp

The read to precharge timing parameter.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB   0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB   3
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH   4
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK   0x0000000f
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK   0xfffffff0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : Activate to Precharge Time - tras

The activate to precharge timing parameter.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB   4
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB   8
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH   5
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK   0x000001f0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK   0xfffffe0f
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value)   (((value) & 0x000001f0) >> 4)
 
#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value)   (((value) << 4) & 0x000001f0)
 

Field : Row Cycle Time - trc

The activate to activate timing parameter.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB   9
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB   14
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH   6
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK   0x00007e00
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK   0xffff81ff
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value)   (((value) & 0x00007e00) >> 9)
 
#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value)   (((value) << 9) & 0x00007e00)
 

Field : Mode Register Programming Delay - tmrd

Mode register timing parameter.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB   15
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB   18
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH   4
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK   0x00078000
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK   0xfff87fff
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value)   (((value) & 0x00078000) >> 15)
 
#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value)   (((value) << 15) & 0x00078000)
 

Field : CAS to CAS Delay - tccd

The CAS to CAS delay time.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB   19
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB   22
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH   4
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK   0x00780000
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK   0xff87ffff
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value)   (((value) & 0x00780000) >> 19)
 
#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value)   (((value) << 19) & 0x00780000)
 

Data Structures

struct  ALT_SDR_CTL_DRAMTIMING3_s
 

Macros

#define ALT_SDR_CTL_DRAMTIMING3_OFST   0xc
 

Typedefs

typedef struct
ALT_SDR_CTL_DRAMTIMING3_s 
ALT_SDR_CTL_DRAMTIMING3_t
 

Data Structure Documentation

struct ALT_SDR_CTL_DRAMTIMING3_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDR_CTL_DRAMTIMING3.

Data Fields
uint32_t trtp: 4 Read to Precharge Time
uint32_t tras: 5 Activate to Precharge Time
uint32_t trc: 6 Row Cycle Time
uint32_t tmrd: 4 Mode Register Programming Delay
uint32_t tccd: 4 CAS to CAS Delay
uint32_t __pad0__: 9 UNDEFINED

Macro Definitions

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB   3

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH   4

The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK   0x0000000f

The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK   0xfffffff0

The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRTP register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRTP register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_SDR_CTL_DRAMTIMING3_TRTP field value from a register.

#define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_SDR_CTL_DRAMTIMING3_TRTP register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB   4

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB   8

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH   5

The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK   0x000001f0

The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK   0xfffffe0f

The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRAS register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRAS register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET (   value)    (((value) & 0x000001f0) >> 4)

Extracts the ALT_SDR_CTL_DRAMTIMING3_TRAS field value from a register.

#define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET (   value)    (((value) << 4) & 0x000001f0)

Produces a ALT_SDR_CTL_DRAMTIMING3_TRAS register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB   9

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB   14

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TRC register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH   6

The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TRC register field.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK   0x00007e00

The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TRC register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK   0xffff81ff

The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TRC register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING3_TRC register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_GET (   value)    (((value) & 0x00007e00) >> 9)

Extracts the ALT_SDR_CTL_DRAMTIMING3_TRC field value from a register.

#define ALT_SDR_CTL_DRAMTIMING3_TRC_SET (   value)    (((value) << 9) & 0x00007e00)

Produces a ALT_SDR_CTL_DRAMTIMING3_TRC register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB   15

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB   18

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH   4

The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK   0x00078000

The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK   0xfff87fff

The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TMRD register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING3_TMRD register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET (   value)    (((value) & 0x00078000) >> 15)

Extracts the ALT_SDR_CTL_DRAMTIMING3_TMRD field value from a register.

#define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET (   value)    (((value) << 15) & 0x00078000)

Produces a ALT_SDR_CTL_DRAMTIMING3_TMRD register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB   19

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB   22

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH   4

The width in bits of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK   0x00780000

The mask used to set the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK   0xff87ffff

The mask used to clear the ALT_SDR_CTL_DRAMTIMING3_TCCD register field value.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING3_TCCD register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET (   value)    (((value) & 0x00780000) >> 19)

Extracts the ALT_SDR_CTL_DRAMTIMING3_TCCD field value from a register.

#define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET (   value)    (((value) << 19) & 0x00780000)

Produces a ALT_SDR_CTL_DRAMTIMING3_TCCD register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING3_OFST   0xc

The byte offset of the ALT_SDR_CTL_DRAMTIMING3 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDR_CTL_DRAMTIMING3.