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alt_noc_fw_ddr_l3_scr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
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#define __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_LSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_MSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_LSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_MSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_LSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_MSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_LSB 3
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_MSB 3
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_LSB 4
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_MSB 4
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_LSB 5
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_MSB 5
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_LSB 6
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_MSB 6
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET_MSK 0x00000040
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_CLR_MSK 0xffffffbf
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_LSB 7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_MSB 7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET_MSK 0x00000080
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_CLR_MSK 0xffffff7f
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_DDR_L3_SCR_EN_s
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{
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uint32_t
hpsregion0enable
: 1;
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uint32_t
hpsregion1enable
: 1;
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uint32_t
hpsregion2enable
: 1;
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uint32_t
hpsregion3enable
: 1;
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uint32_t
hpsregion4enable
: 1;
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uint32_t
hpsregion5enable
: 1;
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uint32_t
hpsregion6enable
: 1;
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uint32_t
hpsregion7enable
: 1;
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uint32_t : 24;
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};
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typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_EN_s
ALT_NOC_FW_DDR_L3_SCR_EN_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_DDR_L3_SCR_EN_RESET 0x00000000
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#define ALT_NOC_FW_DDR_L3_SCR_EN_OFST 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_LSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_MSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_LSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_MSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_LSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_MSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_LSB 3
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_MSB 3
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_LSB 4
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_MSB 4
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_LSB 5
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_MSB 5
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_LSB 6
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_MSB 6
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET_MSK 0x00000040
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_CLR_MSK 0xffffffbf
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_LSB 7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_MSB 7
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET_MSK 0x00000080
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_CLR_MSK 0xffffff7f
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_DDR_L3_SCR_EN_SET_s
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{
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uint32_t
hpsregion0enable
: 1;
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uint32_t
hpsregion1enable
: 1;
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uint32_t
hpsregion2enable
: 1;
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uint32_t
hpsregion3enable
: 1;
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uint32_t
hpsregion4enable
: 1;
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uint32_t
hpsregion5enable
: 1;
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uint32_t
hpsregion6enable
: 1;
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uint32_t
hpsregion7enable
: 1;
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uint32_t : 24;
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};
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typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_EN_SET_s
ALT_NOC_FW_DDR_L3_SCR_EN_SET_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_RESET 0x00000000
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#define ALT_NOC_FW_DDR_L3_SCR_EN_SET_OFST 0x4
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_LSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_MSB 0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_LSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_MSB 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_LSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_MSB 2
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_LSB 3
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#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_MSB 3
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722
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_WIDTH 1
723
724
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET_MSK 0x00000008
725
726
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_CLR_MSK 0xfffffff7
727
728
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_RESET 0x0
729
730
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_GET(value) (((value) & 0x00000008) >> 3)
731
732
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG3EN_SET(value) (((value) << 3) & 0x00000008)
733
747
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_LSB 4
748
749
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_MSB 4
750
751
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_WIDTH 1
752
753
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET_MSK 0x00000010
754
755
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_CLR_MSK 0xffffffef
756
757
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_RESET 0x0
758
759
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_GET(value) (((value) & 0x00000010) >> 4)
760
761
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG4EN_SET(value) (((value) << 4) & 0x00000010)
762
776
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_LSB 5
777
778
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_MSB 5
779
780
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_WIDTH 1
781
782
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET_MSK 0x00000020
783
784
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_CLR_MSK 0xffffffdf
785
786
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_RESET 0x0
787
788
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_GET(value) (((value) & 0x00000020) >> 5)
789
790
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG5EN_SET(value) (((value) << 5) & 0x00000020)
791
805
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_LSB 6
806
807
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_MSB 6
808
809
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_WIDTH 1
810
811
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET_MSK 0x00000040
812
813
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_CLR_MSK 0xffffffbf
814
815
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_RESET 0x0
816
817
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_GET(value) (((value) & 0x00000040) >> 6)
818
819
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG6EN_SET(value) (((value) << 6) & 0x00000040)
820
834
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_LSB 7
835
836
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_MSB 7
837
838
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_WIDTH 1
839
840
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET_MSK 0x00000080
841
842
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_CLR_MSK 0xffffff7f
843
844
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_RESET 0x0
845
846
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_GET(value) (((value) & 0x00000080) >> 7)
847
848
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_HPSREG7EN_SET(value) (((value) << 7) & 0x00000080)
849
850
#ifndef __ASSEMBLY__
851
861
struct
ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s
862
{
863
uint32_t
hpsregion0enable
: 1;
864
uint32_t
hpsregion1enable
: 1;
865
uint32_t
hpsregion2enable
: 1;
866
uint32_t
hpsregion3enable
: 1;
867
uint32_t
hpsregion4enable
: 1;
868
uint32_t
hpsregion5enable
: 1;
869
uint32_t
hpsregion6enable
: 1;
870
uint32_t
hpsregion7enable
: 1;
871
uint32_t : 24;
872
};
873
875
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_EN_CLR_s
ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t
;
876
#endif
/* __ASSEMBLY__ */
877
879
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_RESET 0x00000000
880
881
#define ALT_NOC_FW_DDR_L3_SCR_EN_CLR_OFST 0x8
882
906
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_LSB 0
907
908
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_MSB 15
909
910
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_WIDTH 16
911
912
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET_MSK 0x0000ffff
913
914
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_CLR_MSK 0xffff0000
915
916
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_RESET 0x0
917
918
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
919
920
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
921
932
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_LSB 16
933
934
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_MSB 31
935
936
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_WIDTH 16
937
938
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET_MSK 0xffff0000
939
940
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
941
942
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_RESET 0x0
943
944
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
945
946
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
947
948
#ifndef __ASSEMBLY__
949
959
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s
960
{
961
uint32_t
base
: 16;
962
uint32_t
limit
: 16;
963
};
964
966
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t
;
967
#endif
/* __ASSEMBLY__ */
968
970
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_RESET 0x00000000
971
972
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_OFST 0xc
973
997
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_LSB 0
998
999
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_MSB 15
1000
1001
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_WIDTH 16
1002
1003
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET_MSK 0x0000ffff
1004
1005
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_CLR_MSK 0xffff0000
1006
1007
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_RESET 0x0
1008
1009
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1010
1011
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1012
1023
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_LSB 16
1024
1025
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_MSB 31
1026
1027
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_WIDTH 16
1028
1029
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET_MSK 0xffff0000
1030
1031
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1032
1033
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_RESET 0x0
1034
1035
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1036
1037
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1038
1039
#ifndef __ASSEMBLY__
1040
1050
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s
1051
{
1052
uint32_t
base
: 16;
1053
uint32_t
limit
: 16;
1054
};
1055
1057
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t
;
1058
#endif
/* __ASSEMBLY__ */
1059
1061
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_RESET 0x00000000
1062
1063
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_OFST 0x10
1064
1088
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_LSB 0
1089
1090
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_MSB 15
1091
1092
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_WIDTH 16
1093
1094
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET_MSK 0x0000ffff
1095
1096
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_CLR_MSK 0xffff0000
1097
1098
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_RESET 0x0
1099
1100
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1101
1102
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1103
1114
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_LSB 16
1115
1116
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_MSB 31
1117
1118
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_WIDTH 16
1119
1120
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET_MSK 0xffff0000
1121
1122
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1123
1124
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_RESET 0x0
1125
1126
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1127
1128
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1129
1130
#ifndef __ASSEMBLY__
1131
1141
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s
1142
{
1143
uint32_t
base
: 16;
1144
uint32_t
limit
: 16;
1145
};
1146
1148
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t
;
1149
#endif
/* __ASSEMBLY__ */
1150
1152
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_RESET 0x00000000
1153
1154
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_OFST 0x14
1155
1179
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_LSB 0
1180
1181
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_MSB 15
1182
1183
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_WIDTH 16
1184
1185
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET_MSK 0x0000ffff
1186
1187
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_CLR_MSK 0xffff0000
1188
1189
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_RESET 0x0
1190
1191
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1192
1193
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1194
1205
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_LSB 16
1206
1207
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_MSB 31
1208
1209
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_WIDTH 16
1210
1211
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET_MSK 0xffff0000
1212
1213
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1214
1215
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_RESET 0x0
1216
1217
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1218
1219
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1220
1221
#ifndef __ASSEMBLY__
1222
1232
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s
1233
{
1234
uint32_t
base
: 16;
1235
uint32_t
limit
: 16;
1236
};
1237
1239
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t
;
1240
#endif
/* __ASSEMBLY__ */
1241
1243
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_RESET 0x00000000
1244
1245
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_OFST 0x18
1246
1270
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0
1271
1272
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15
1273
1274
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16
1275
1276
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff
1277
1278
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000
1279
1280
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0
1281
1282
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1283
1284
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1285
1296
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16
1297
1298
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31
1299
1300
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16
1301
1302
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000
1303
1304
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff
1305
1306
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0
1307
1308
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1309
1310
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1311
1312
#ifndef __ASSEMBLY__
1313
1323
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s
1324
{
1325
uint32_t
base
: 16;
1326
uint32_t
limit
: 16;
1327
};
1328
1330
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t
;
1331
#endif
/* __ASSEMBLY__ */
1332
1334
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000
1335
1336
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c
1337
1361
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_LSB 0
1362
1363
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_MSB 15
1364
1365
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_WIDTH 16
1366
1367
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET_MSK 0x0000ffff
1368
1369
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_CLR_MSK 0xffff0000
1370
1371
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_RESET 0x0
1372
1373
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1374
1375
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1376
1387
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_LSB 16
1388
1389
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_MSB 31
1390
1391
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_WIDTH 16
1392
1393
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET_MSK 0xffff0000
1394
1395
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_CLR_MSK 0x0000ffff
1396
1397
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_RESET 0x0
1398
1399
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1400
1401
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1402
1403
#ifndef __ASSEMBLY__
1404
1414
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s
1415
{
1416
uint32_t
base
: 16;
1417
uint32_t
limit
: 16;
1418
};
1419
1421
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t
;
1422
#endif
/* __ASSEMBLY__ */
1423
1425
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_RESET 0x00000000
1426
1427
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_OFST 0x20
1428
1452
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_LSB 0
1453
1454
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_MSB 15
1455
1456
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_WIDTH 16
1457
1458
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET_MSK 0x0000ffff
1459
1460
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_CLR_MSK 0xffff0000
1461
1462
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_RESET 0x0
1463
1464
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1465
1466
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1467
1478
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_LSB 16
1479
1480
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_MSB 31
1481
1482
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_WIDTH 16
1483
1484
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET_MSK 0xffff0000
1485
1486
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_CLR_MSK 0x0000ffff
1487
1488
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_RESET 0x0
1489
1490
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1491
1492
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1493
1494
#ifndef __ASSEMBLY__
1495
1505
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s
1506
{
1507
uint32_t
base
: 16;
1508
uint32_t
limit
: 16;
1509
};
1510
1512
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t
;
1513
#endif
/* __ASSEMBLY__ */
1514
1516
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_RESET 0x00000000
1517
1518
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_OFST 0x24
1519
1543
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_LSB 0
1544
1545
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_MSB 15
1546
1547
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_WIDTH 16
1548
1549
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET_MSK 0x0000ffff
1550
1551
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_CLR_MSK 0xffff0000
1552
1553
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_RESET 0x0
1554
1555
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1556
1557
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1558
1569
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_LSB 16
1570
1571
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_MSB 31
1572
1573
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_WIDTH 16
1574
1575
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET_MSK 0xffff0000
1576
1577
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_CLR_MSK 0x0000ffff
1578
1579
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_RESET 0x0
1580
1581
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1582
1583
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1584
1585
#ifndef __ASSEMBLY__
1586
1596
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s
1597
{
1598
uint32_t
base
: 16;
1599
uint32_t
limit
: 16;
1600
};
1601
1603
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_s
ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t
;
1604
#endif
/* __ASSEMBLY__ */
1605
1607
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_RESET 0x00000000
1608
1609
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_OFST 0x28
1610
1636
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_LSB 0
1637
1638
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_MSB 0
1639
1640
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_WIDTH 1
1641
1642
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET_MSK 0x00000001
1643
1644
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_CLR_MSK 0xfffffffe
1645
1646
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_RESET 0x0
1647
1648
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_GET(value) (((value) & 0x00000001) >> 0)
1649
1650
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_ERROR_RESPONSE_SET(value) (((value) << 0) & 0x00000001)
1651
1652
#ifndef __ASSEMBLY__
1653
1663
struct
ALT_NOC_FW_DDR_L3_SCR_GLOB_s
1664
{
1665
uint32_t
error_response
: 1;
1666
uint32_t : 31;
1667
};
1668
1670
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_GLOB_s
ALT_NOC_FW_DDR_L3_SCR_GLOB_t
;
1671
#endif
/* __ASSEMBLY__ */
1672
1674
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_RESET 0x00000000
1675
1676
#define ALT_NOC_FW_DDR_L3_SCR_GLOB_OFST 0x2c
1677
1678
#ifndef __ASSEMBLY__
1679
1689
struct
ALT_NOC_FW_DDR_L3_SCR_s
1690
{
1691
volatile
ALT_NOC_FW_DDR_L3_SCR_EN_t
enable
;
1692
volatile
ALT_NOC_FW_DDR_L3_SCR_EN_SET_t
enable_set
;
1693
volatile
ALT_NOC_FW_DDR_L3_SCR_EN_CLR_t
enable_clear
;
1694
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG0ADDR_t
hpsregion0addr
;
1695
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG1ADDR_t
hpsregion1addr
;
1696
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG2ADDR_t
hpsregion2addr
;
1697
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG3ADDR_t
hpsregion3addr
;
1698
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t
hpsregion4addr
;
1699
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG5ADDR_t
hpsregion5addr
;
1700
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG6ADDR_t
hpsregion6addr
;
1701
volatile
ALT_NOC_FW_DDR_L3_SCR_HPSREG7ADDR_t
hpsregion7addr
;
1702
volatile
ALT_NOC_FW_DDR_L3_SCR_GLOB_t
global
;
1703
volatile
uint32_t
_pad_0x30_0x100
[52];
1704
};
1705
1707
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_s
ALT_NOC_FW_DDR_L3_SCR_t
;
1709
struct
ALT_NOC_FW_DDR_L3_SCR_raw_s
1710
{
1711
volatile
uint32_t
enable
;
1712
volatile
uint32_t
enable_set
;
1713
volatile
uint32_t
enable_clear
;
1714
volatile
uint32_t
hpsregion0addr
;
1715
volatile
uint32_t
hpsregion1addr
;
1716
volatile
uint32_t
hpsregion2addr
;
1717
volatile
uint32_t
hpsregion3addr
;
1718
volatile
uint32_t
hpsregion4addr
;
1719
volatile
uint32_t
hpsregion5addr
;
1720
volatile
uint32_t
hpsregion6addr
;
1721
volatile
uint32_t
hpsregion7addr
;
1722
volatile
uint32_t
global
;
1723
volatile
uint32_t
_pad_0x30_0x100
[52];
1724
};
1725
1727
typedef
volatile
struct
ALT_NOC_FW_DDR_L3_SCR_raw_s
ALT_NOC_FW_DDR_L3_SCR_raw_t
;
1728
#endif
/* __ASSEMBLY__ */
1729
1731
#ifdef __cplusplus
1732
}
1733
#endif
/* __cplusplus */
1734
#endif
/* __ALT_SOCAL_NOC_FW_DDR_L3_SCR_H__ */
1735
include
soc_a10
socal
alt_noc_fw_ddr_l3_scr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2