Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 11 (AHB or AXI Status Register) - AHB_or_AXI_Status

Description

This register provides the active status of the AXI interface's read and write channels. This register is useful for debugging purposes. In addition, this register is valid only in the Channel 0 DMA when multiple channels are present in the AV mode.

Register Layout

Bits Access Reset Description
[0] R 0x0 AXI Master Write Channel Status
[1] R 0x0 AXI Master Read Channel Status
[31:2] ??? 0x0 UNDEFINED

Field : AXI Master Write Channel Status - axwhsts

When high, it indicates that AXI Master's write channel is active and transferring data

Field Access Macros:

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB   0
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB   0
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH   1
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET   0x0
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : AXI Master Read Channel Status - axirdsts

When high, it indicates that AXI Master's read channel is active and transferring data.

Field Access Macros:

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB   1
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB   1
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH   1
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK   0x00000002
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET   0x0
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET(value)   (((value) << 1) & 0x00000002)
 

Data Structures

struct  ALT_EMAC_DMA_AHB_OR_AXI_STAT_s
 

Macros

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST   0x2c
 
#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_AHB_OR_AXI_STAT_s 
ALT_EMAC_DMA_AHB_OR_AXI_STAT_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_AHB_OR_AXI_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_AHB_OR_AXI_STAT.

Data Fields
const uint32_t axwhsts: 1 AXI Master Write Channel Status
const uint32_t axirdsts: 1 AXI Master Read Channel Status
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_RESET   0x0

The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS field value from a register.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXWHSTS register field value suitable for setting the register.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_RESET   0x0

The reset value of the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS field value from a register.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_DMA_AHB_OR_AXI_STAT_AXIRDSTS register field value suitable for setting the register.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST   0x2c

The byte offset of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register from the beginning of the component.

#define ALT_EMAC_DMA_AHB_OR_AXI_STAT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AHB_OR_AXI_STAT_OFST))

The address of the ALT_EMAC_DMA_AHB_OR_AXI_STAT register.

Typedef Documentation