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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The Operation Mode register establishes the Transmit and Receive operating modes and commands. This register should be the last CSR to be written as part of the DMA initialization.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | ??? | 0x0 | UNDEFINED |
[1] | RW | 0x0 | Start or Stop Receive |
[2] | RW | 0x0 | Operate on Second Frame |
[4:3] | RW | 0x0 | Receive Threshold Control |
[5] | ??? | 0x0 | UNDEFINED |
[6] | RW | 0x0 | Forward Undersized Good Frames |
[7] | RW | 0x0 | Forward Error Frames |
[8] | RW | 0x0 | Enable HW Flow Control |
[10:9] | RW | 0x0 | Threshold for Activating Flow Control (in half-duplex and full-duplex) |
[12:11] | RW | 0x0 | Threshold for Deactivating Flow Control (in half-duplex and full-duplex) |
[13] | RW | 0x0 | Start or Stop Transmission Command |
[16:14] | RW | 0x0 | Transmit Threshold Control |
[19:17] | ??? | 0x0 | UNDEFINED |
[20] | RW | 0x0 | Flush Transmit FIFO |
[21] | RW | 0x0 | Transmit Store and Forward |
[23:22] | ??? | 0x0 | UNDEFINED |
[24] | RW | 0x0 | Disable Flushing of Received Frames |
[25] | RW | 0x0 | Receive Store and Forward |
[26] | RW | 0x0 | Disable Dropping of TCP/IP Checksum Error Frames |
[31:27] | ??? | 0x0 | UNDEFINED |
Field : Start or Stop Receive - sr | ||||||||||
When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable. When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_LSB 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_MSB 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_SET_MSK 0x00000002 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_SR_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Operate on Second Frame - osf | ||||||||||
When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_LSB 2 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_MSB 2 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK 0x00000004 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_OSF_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : Receive Threshold Control - rtc | ||||||||||||||||
These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are transferred automatically. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 0x1 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 0x2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 0x3 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_LSB 3 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_MSB 4 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_WIDTH 2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK 0x00000018 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK 0xffffffe7 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_RESET 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_GET(value) (((value) & 0x00000018) >> 3) | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RTC_SET(value) (((value) << 3) & 0x00000018) | |||||||||||||||
Field : Forward Undersized Good Frames - fuf | ||||||||||
When set, the Rx FIFO forwards Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC. When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_LSB 6 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_MSB 6 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK 0x00000040 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FUF_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : Forward Error Frames - fef | ||||||||||
When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped. When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is written, then a partial frame may be forwarded to the DMA. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_LSB 7 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_MSB 7 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK 0x00000080 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FEF_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : Enable HW Flow Control - efc | ||||||||||
When this bit is set, the flow control signal operation based on the fill-level of Rx FIFO is enabled. When reset, the flow control operation is disabled. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_LSB 8 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_MSB 8 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK 0x00000100 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_EFC_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : Threshold for Activating Flow Control (in half-duplex and full-duplex) - rfa | ||||||||||||||||
These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated. These values only apply to the Rx FIFO when the EFC bit is set high. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K 0x1 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K 0x2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K 0x3 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_LSB 9 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_MSB 10 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_WIDTH 2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK 0x00000600 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK 0xfffff9ff | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_RESET 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_GET(value) (((value) & 0x00000600) >> 9) | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFA_SET(value) (((value) << 9) & 0x00000600) | |||||||||||||||
Field : Threshold for Deactivating Flow Control (in half-duplex and full-duplex) - rfd | ||||||||||||||||
These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation. The de-assertion is effective only after flow control is asserted. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K 0x1 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K 0x2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K 0x3 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_LSB 11 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_MSB 12 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_WIDTH 2 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK 0x00001800 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK 0xffffe7ff | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_RESET 0x0 | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_GET(value) (((value) & 0x00001800) >> 11) | |||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RFD_SET(value) (((value) << 11) & 0x00001800) | |||||||||||||||
Field : Start or Stop Transmission Command - st | ||||||||||
When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable. When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_LSB 13 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_MSB 13 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_SET_MSK 0x00002000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK 0xffffdfff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_GET(value) (((value) & 0x00002000) >> 13) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_ST_SET(value) (((value) << 13) & 0x00002000) | |||||||||
Field : Transmit Threshold Control - ttc | ||||||||||||||||||||||||||||
These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 0x0 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 0x1 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 0x2 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 0x3 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 0x4 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 0x5 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 0x6 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 0x7 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_LSB 14 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_MSB 16 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_WIDTH 3 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK 0x0001c000 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK 0xfffe3fff | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_GET(value) (((value) & 0x0001c000) >> 14) | |||||||||||||||||||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TTC_SET(value) (((value) << 14) & 0x0001c000) | |||||||||||||||||||||||||||
Field : Flush Transmit FIFO - ftf | ||||||||||
When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is completed. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission. Note: The flush operation is complete only when the Tx FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. To complete this flush operation, the PHY transmit clock is required to be active. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_LSB 20 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_MSB 20 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK 0x00100000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK 0xffefffff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_GET(value) (((value) & 0x00100000) >> 20) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_FTF_SET(value) (((value) << 20) & 0x00100000) | |||||||||
Field : Transmit Store and Forward - tsf | ||||||||||
When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are ignored. This bit should be changed only when the transmission is stopped. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_LSB 21 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_MSB 21 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK 0x00200000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK 0xffdfffff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_GET(value) (((value) & 0x00200000) >> 21) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_TSF_SET(value) (((value) << 21) & 0x00200000) | |||||||||
Field : Disable Flushing of Received Frames - dff | ||||||||||
When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_LSB 24 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_MSB 24 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK 0x01000000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK 0xfeffffff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_GET(value) (((value) & 0x01000000) >> 24) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DFF_SET(value) (((value) << 24) & 0x01000000) | |||||||||
Field : Receive Store and Forward - rsf | ||||||||||
When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_LSB 25 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_MSB 25 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK 0x02000000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK 0xfdffffff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_GET(value) (((value) & 0x02000000) >> 25) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_RSF_SET(value) (((value) << 25) & 0x02000000) | |||||||||
Field : Disable Dropping of TCP/IP Checksum Error Frames - dt | ||||||||||
When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_LSB 26 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_MSB 26 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_SET_MSK 0x04000000 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK 0xfbffffff | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_GET(value) (((value) & 0x04000000) >> 26) | |||||||||
#define | ALT_EMAC_DMA_OP_MOD_DT_SET(value) (((value) << 26) & 0x04000000) | |||||||||
Data Structures | |
struct | ALT_EMAC_DMA_OP_MOD_s |
Macros | |
#define | ALT_EMAC_DMA_OP_MOD_OFST 0x18 |
#define | ALT_EMAC_DMA_OP_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_DMA_OP_MOD_s | ALT_EMAC_DMA_OP_MOD_t |
struct ALT_EMAC_DMA_OP_MOD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_DMA_OP_MOD.
Data Fields | ||
---|---|---|
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | sr: 1 | Start or Stop Receive |
uint32_t | osf: 1 | Operate on Second Frame |
uint32_t | rtc: 2 | Receive Threshold Control |
uint32_t | __pad1__: 1 | UNDEFINED |
uint32_t | fuf: 1 | Forward Undersized Good Frames |
uint32_t | fef: 1 | Forward Error Frames |
uint32_t | efc: 1 | Enable HW Flow Control |
uint32_t | rfa: 2 | Threshold for Activating Flow Control (in half-duplex and full-duplex) |
uint32_t | rfd: 2 | Threshold for Deactivating Flow Control (in half-duplex and full-duplex) |
uint32_t | st: 1 | Start or Stop Transmission Command |
uint32_t | ttc: 3 | Transmit Threshold Control |
uint32_t | __pad2__: 3 | UNDEFINED |
uint32_t | ftf: 1 | Flush Transmit FIFO |
uint32_t | tsf: 1 | Transmit Store and Forward |
uint32_t | __pad3__: 2 | UNDEFINED |
uint32_t | dff: 1 | Disable Flushing of Received Frames |
uint32_t | rsf: 1 | Receive Store and Forward |
uint32_t | dt: 1 | Disable Dropping of TCP/IP Checksum Error Frames |
uint32_t | __pad4__: 5 | UNDEFINED |
#define ALT_EMAC_DMA_OP_MOD_SR_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
Rx DMA operation is stopped
#define ALT_EMAC_DMA_OP_MOD_SR_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR
Rx DMA operation is started
#define ALT_EMAC_DMA_OP_MOD_SR_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field.
#define ALT_EMAC_DMA_OP_MOD_SR_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field.
#define ALT_EMAC_DMA_OP_MOD_SR_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field.
#define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value.
#define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value.
#define ALT_EMAC_DMA_OP_MOD_SR_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field.
#define ALT_EMAC_DMA_OP_MOD_SR_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register.
#define ALT_EMAC_DMA_OP_MOD_SR_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
DMA Does Not Process second frame
#define ALT_EMAC_DMA_OP_MOD_OSF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF
DMA Processes second frame
#define ALT_EMAC_DMA_OP_MOD_OSF_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field.
#define ALT_EMAC_DMA_OP_MOD_OSF_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field.
#define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field.
#define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value.
#define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value.
#define ALT_EMAC_DMA_OP_MOD_OSF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field.
#define ALT_EMAC_DMA_OP_MOD_OSF_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_OSF_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
MTL Rcv Fifo threshold level 64
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
MTL Rcv Fifo threshold level 32
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 0x2 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
MTL Rcv Fifo threshold level 96
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 0x3 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC
MTL Rcv Fifo threshold level 128
#define ALT_EMAC_DMA_OP_MOD_RTC_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field.
#define ALT_EMAC_DMA_OP_MOD_RTC_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field.
#define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH 2 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field.
#define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK 0x00000018 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value.
#define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK 0xffffffe7 |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value.
#define ALT_EMAC_DMA_OP_MOD_RTC_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field.
#define ALT_EMAC_DMA_OP_MOD_RTC_GET | ( | value | ) | (((value) & 0x00000018) >> 3) |
Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register.
#define ALT_EMAC_DMA_OP_MOD_RTC_SET | ( | value | ) | (((value) << 3) & 0x00000018) |
Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
Drops Frames less than 64Bytes
#define ALT_EMAC_DMA_OP_MOD_FUF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF
Forward Frames with no errors
#define ALT_EMAC_DMA_OP_MOD_FUF_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field.
#define ALT_EMAC_DMA_OP_MOD_FUF_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field.
#define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field.
#define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK 0x00000040 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value.
#define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value.
#define ALT_EMAC_DMA_OP_MOD_FUF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field.
#define ALT_EMAC_DMA_OP_MOD_FUF_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_FUF_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
Drops Frames with error status
#define ALT_EMAC_DMA_OP_MOD_FEF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF
Forward all Frames(except runt)
#define ALT_EMAC_DMA_OP_MOD_FEF_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field.
#define ALT_EMAC_DMA_OP_MOD_FEF_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field.
#define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field.
#define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value.
#define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value.
#define ALT_EMAC_DMA_OP_MOD_FEF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field.
#define ALT_EMAC_DMA_OP_MOD_FEF_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_FEF_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
Rx FIFO Fill Level Disabled
#define ALT_EMAC_DMA_OP_MOD_EFC_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC
Rx FIFO Fill Level Enabled Ctrl
#define ALT_EMAC_DMA_OP_MOD_EFC_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field.
#define ALT_EMAC_DMA_OP_MOD_EFC_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field.
#define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field.
#define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value.
#define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value.
#define ALT_EMAC_DMA_OP_MOD_EFC_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field.
#define ALT_EMAC_DMA_OP_MOD_EFC_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register.
#define ALT_EMAC_DMA_OP_MOD_EFC_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
Full minus 1 KB
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
Full minus 2 KB
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K 0x2 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
Full minus 3 KB
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K 0x3 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA
Full minus 4 KB
#define ALT_EMAC_DMA_OP_MOD_RFA_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field.
#define ALT_EMAC_DMA_OP_MOD_RFA_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field.
#define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH 2 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field.
#define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK 0x00000600 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value.
#define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK 0xfffff9ff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value.
#define ALT_EMAC_DMA_OP_MOD_RFA_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field.
#define ALT_EMAC_DMA_OP_MOD_RFA_GET | ( | value | ) | (((value) & 0x00000600) >> 9) |
Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register.
#define ALT_EMAC_DMA_OP_MOD_RFA_SET | ( | value | ) | (((value) << 9) & 0x00000600) |
Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
Full minus 1 KB
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
Full minus 2 KB
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K 0x2 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
Full minus 3 KB
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K 0x3 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD
Full minus 4 KB
#define ALT_EMAC_DMA_OP_MOD_RFD_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field.
#define ALT_EMAC_DMA_OP_MOD_RFD_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field.
#define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH 2 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field.
#define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK 0x00001800 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value.
#define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK 0xffffe7ff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value.
#define ALT_EMAC_DMA_OP_MOD_RFD_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field.
#define ALT_EMAC_DMA_OP_MOD_RFD_GET | ( | value | ) | (((value) & 0x00001800) >> 11) |
Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register.
#define ALT_EMAC_DMA_OP_MOD_RFD_SET | ( | value | ) | (((value) << 11) & 0x00001800) |
Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_ST_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
Transmission Stopped State
#define ALT_EMAC_DMA_OP_MOD_ST_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST
Transmission in Run State
#define ALT_EMAC_DMA_OP_MOD_ST_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field.
#define ALT_EMAC_DMA_OP_MOD_ST_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field.
#define ALT_EMAC_DMA_OP_MOD_ST_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field.
#define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value.
#define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value.
#define ALT_EMAC_DMA_OP_MOD_ST_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field.
#define ALT_EMAC_DMA_OP_MOD_ST_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register.
#define ALT_EMAC_DMA_OP_MOD_ST_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 64
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 128
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 0x2 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 192
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 0x3 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 256
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 0x4 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 40
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 0x5 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 32
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 0x6 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 24
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 0x7 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC
MTL Transmit FIFO Threshold 16
#define ALT_EMAC_DMA_OP_MOD_TTC_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field.
#define ALT_EMAC_DMA_OP_MOD_TTC_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field.
#define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH 3 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field.
#define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK 0x0001c000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value.
#define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK 0xfffe3fff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value.
#define ALT_EMAC_DMA_OP_MOD_TTC_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field.
#define ALT_EMAC_DMA_OP_MOD_TTC_GET | ( | value | ) | (((value) & 0x0001c000) >> 14) |
Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register.
#define ALT_EMAC_DMA_OP_MOD_TTC_SET | ( | value | ) | (((value) << 14) & 0x0001c000) |
Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
Tx FIFO Data not Flushed
#define ALT_EMAC_DMA_OP_MOD_FTF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF
TX FIFO Data Flushed
#define ALT_EMAC_DMA_OP_MOD_FTF_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field.
#define ALT_EMAC_DMA_OP_MOD_FTF_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field.
#define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field.
#define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK 0x00100000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value.
#define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK 0xffefffff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value.
#define ALT_EMAC_DMA_OP_MOD_FTF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field.
#define ALT_EMAC_DMA_OP_MOD_FTF_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_FTF_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
Tx Does not Start with Full Frame
#define ALT_EMAC_DMA_OP_MOD_TSF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF
Tx Start with Full Frame
#define ALT_EMAC_DMA_OP_MOD_TSF_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field.
#define ALT_EMAC_DMA_OP_MOD_TSF_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field.
#define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field.
#define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK 0x00200000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value.
#define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value.
#define ALT_EMAC_DMA_OP_MOD_TSF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field.
#define ALT_EMAC_DMA_OP_MOD_TSF_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_TSF_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
Rx DMA Flushed
#define ALT_EMAC_DMA_OP_MOD_DFF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF
Rx DMA not Flushed
#define ALT_EMAC_DMA_OP_MOD_DFF_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field.
#define ALT_EMAC_DMA_OP_MOD_DFF_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field.
#define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field.
#define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value.
#define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value.
#define ALT_EMAC_DMA_OP_MOD_DFF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field.
#define ALT_EMAC_DMA_OP_MOD_DFF_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_DFF_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
Rx Fifo cut-through mode
#define ALT_EMAC_DMA_OP_MOD_RSF_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF
Read Rx FIFO only after complete frame
#define ALT_EMAC_DMA_OP_MOD_RSF_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field.
#define ALT_EMAC_DMA_OP_MOD_RSF_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field.
#define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field.
#define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value.
#define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value.
#define ALT_EMAC_DMA_OP_MOD_RSF_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field.
#define ALT_EMAC_DMA_OP_MOD_RSF_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register.
#define ALT_EMAC_DMA_OP_MOD_RSF_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_DT_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
All Error Frames Dropped
#define ALT_EMAC_DMA_OP_MOD_DT_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT
MAC does not drop frame with errors
#define ALT_EMAC_DMA_OP_MOD_DT_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field.
#define ALT_EMAC_DMA_OP_MOD_DT_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field.
#define ALT_EMAC_DMA_OP_MOD_DT_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field.
#define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK 0x04000000 |
The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value.
#define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value.
#define ALT_EMAC_DMA_OP_MOD_DT_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field.
#define ALT_EMAC_DMA_OP_MOD_DT_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register.
#define ALT_EMAC_DMA_OP_MOD_DT_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register.
#define ALT_EMAC_DMA_OP_MOD_OFST 0x18 |
The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component.
#define ALT_EMAC_DMA_OP_MOD_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST)) |
The address of the ALT_EMAC_DMA_OP_MOD register.
typedef struct ALT_EMAC_DMA_OP_MOD_s ALT_EMAC_DMA_OP_MOD_t |
The typedef declaration for register ALT_EMAC_DMA_OP_MOD.