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alt_i2c.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_I2C_H__
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#define __ALT_SOCAL_I2C_H__
37
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
47
121
#define ALT_I2C_CON_MST_MOD_E_DIS 0x0
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#define ALT_I2C_CON_MST_MOD_E_EN 0x1
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#define ALT_I2C_CON_MST_MOD_LSB 0
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#define ALT_I2C_CON_MST_MOD_MSB 0
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#define ALT_I2C_CON_MST_MOD_WIDTH 1
135
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#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
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#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
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#define ALT_I2C_CON_MST_MOD_RESET 0x1
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#define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_I2C_CON_SPEED_E_STANDARD 0x1
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#define ALT_I2C_CON_SPEED_E_FAST 0x2
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#define ALT_I2C_CON_SPEED_LSB 1
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#define ALT_I2C_CON_SPEED_MSB 2
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#define ALT_I2C_CON_SPEED_WIDTH 2
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#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
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#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
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#define ALT_I2C_CON_SPEED_RESET 0x2
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#define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
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#define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
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#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
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#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
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#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
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#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
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#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
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#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
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#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
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#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
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#define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
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#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
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#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
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#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
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#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
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#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
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#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
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#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
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#define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
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#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
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#define ALT_I2C_CON_IC_RESTART_EN_LSB 5
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#define ALT_I2C_CON_IC_RESTART_EN_MSB 5
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#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
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#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
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#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
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422
#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
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#define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
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426
#define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
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#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
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#define ALT_I2C_CON_IC_SLV_DIS_LSB 6
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#define ALT_I2C_CON_IC_SLV_DIS_MSB 6
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#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
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#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
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#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
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#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
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#define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_I2C_CON_STOP_DET_IFADDRED_LSB 7
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#define ALT_I2C_CON_STOP_DET_IFADDRED_MSB 7
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#define ALT_I2C_CON_STOP_DET_IFADDRED_WIDTH 1
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#define ALT_I2C_CON_STOP_DET_IFADDRED_SET_MSK 0x00000080
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#define ALT_I2C_CON_STOP_DET_IFADDRED_CLR_MSK 0xffffff7f
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#define ALT_I2C_CON_STOP_DET_IFADDRED_RESET 0x0
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#define ALT_I2C_CON_STOP_DET_IFADDRED_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_I2C_CON_STOP_DET_IFADDRED_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_I2C_CON_TX_EMPTY_CTL_LSB 8
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#define ALT_I2C_CON_TX_EMPTY_CTL_MSB 8
561
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#define ALT_I2C_CON_TX_EMPTY_CTL_WIDTH 1
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#define ALT_I2C_CON_TX_EMPTY_CTL_SET_MSK 0x00000100
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#define ALT_I2C_CON_TX_EMPTY_CTL_CLR_MSK 0xfffffeff
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#define ALT_I2C_CON_TX_EMPTY_CTL_RESET 0x0
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#define ALT_I2C_CON_TX_EMPTY_CTL_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_I2C_CON_TX_EMPTY_CTL_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_LSB 9
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_MSB 9
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_WIDTH 1
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET_MSK 0x00000200
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_CLR_MSK 0xfffffdff
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_RESET 0x0
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_GET(value) (((value) & 0x00000200) >> 9)
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#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET(value) (((value) << 9) & 0x00000200)
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_LSB 10
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_MSB 31
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_WIDTH 22
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET_MSK 0xfffffc00
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_CLR_MSK 0x000003ff
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_RESET 0x0
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_GET(value) (((value) & 0xfffffc00) >> 10)
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#define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET(value) (((value) << 10) & 0xfffffc00)
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#ifndef __ASSEMBLY__
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struct
ALT_I2C_CON_s
651
{
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uint32_t
master_mode
: 1;
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uint32_t
speed
: 2;
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uint32_t
ic_10bitaddr_slave
: 1;
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const
uint32_t
ic_10bitaddr_master
: 1;
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uint32_t
ic_restart_en
: 1;
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uint32_t
ic_slave_disable
: 1;
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uint32_t
stop_det_ifaddressed
: 1;
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uint32_t
tx_empty_ctrl
: 1;
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uint32_t
rx_fifo_full_hld_ctrl
: 1;
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const
uint32_t
rsvd_ic_con_31to10
: 22;
662
};
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665
typedef
volatile
struct
ALT_I2C_CON_s
ALT_I2C_CON_t
;
666
#endif
/* __ASSEMBLY__ */
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#define ALT_I2C_CON_RESET 0x0000007d
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#define ALT_I2C_CON_OFST 0x0
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#define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
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#define ALT_I2C_TAR_IC_TAR_LSB 0
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#define ALT_I2C_TAR_IC_TAR_MSB 9
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#define ALT_I2C_TAR_IC_TAR_WIDTH 10
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#define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
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#define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
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#define ALT_I2C_TAR_IC_TAR_RESET 0x55
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#define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
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#define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
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#define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
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#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
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#define ALT_I2C_TAR_GC_OR_START_LSB 10
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#define ALT_I2C_TAR_GC_OR_START_MSB 10
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#define ALT_I2C_TAR_GC_OR_START_WIDTH 1
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#define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
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#define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
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#define ALT_I2C_TAR_GC_OR_START_RESET 0x0
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#define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
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#define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
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#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
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#define ALT_I2C_TAR_SPECIAL_LSB 11
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#define ALT_I2C_TAR_SPECIAL_MSB 11
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#define ALT_I2C_TAR_SPECIAL_WIDTH 1
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#define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
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#define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
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#define ALT_I2C_TAR_SPECIAL_RESET 0x0
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#define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
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#define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
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#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
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#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
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#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
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#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
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#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
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#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
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#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
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#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
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#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
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#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
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#ifndef __ASSEMBLY__
952
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struct
ALT_I2C_TAR_s
963
{
964
uint32_t
ic_tar
: 10;
965
uint32_t
gc_or_start
: 1;
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uint32_t
special
: 1;
967
uint32_t
ic_10bitaddr_master
: 1;
968
uint32_t : 19;
969
};
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972
typedef
volatile
struct
ALT_I2C_TAR_s
ALT_I2C_TAR_t
;
973
#endif
/* __ASSEMBLY__ */
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#define ALT_I2C_TAR_RESET 0x00001055
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#define ALT_I2C_TAR_OFST 0x4
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#define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
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#define ALT_I2C_SAR_IC_SAR_LSB 0
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1034
#define ALT_I2C_SAR_IC_SAR_MSB 9
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#define ALT_I2C_SAR_IC_SAR_WIDTH 10
1037
1038
#define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
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#define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
1041
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#define ALT_I2C_SAR_IC_SAR_RESET 0x55
1043
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#define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
1045
1046
#define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
1047
1048
#ifndef __ASSEMBLY__
1049
1059
struct
ALT_I2C_SAR_s
1060
{
1061
uint32_t
ic_sar
: 10;
1062
uint32_t : 22;
1063
};
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1066
typedef
volatile
struct
ALT_I2C_SAR_s
ALT_I2C_SAR_t
;
1067
#endif
/* __ASSEMBLY__ */
1068
1070
#define ALT_I2C_SAR_RESET 0x00000055
1071
1072
#define ALT_I2C_SAR_OFST 0x8
1073
1074
#define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
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#define ALT_I2C_DATA_CMD_DAT_LSB 0
1138
1139
#define ALT_I2C_DATA_CMD_DAT_MSB 7
1140
1141
#define ALT_I2C_DATA_CMD_DAT_WIDTH 8
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1143
#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
1144
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#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
1146
1147
#define ALT_I2C_DATA_CMD_DAT_RESET 0x0
1148
1149
#define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
1150
1151
#define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
1152
1218
#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
1219
1224
#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
1225
1227
#define ALT_I2C_DATA_CMD_CMD_LSB 8
1228
1229
#define ALT_I2C_DATA_CMD_CMD_MSB 8
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1231
#define ALT_I2C_DATA_CMD_CMD_WIDTH 1
1232
1233
#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
1234
1235
#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
1236
1237
#define ALT_I2C_DATA_CMD_CMD_RESET 0x0
1238
1239
#define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
1240
1241
#define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
1242
1274
#define ALT_I2C_DATA_CMD_STOP_LSB 9
1275
1276
#define ALT_I2C_DATA_CMD_STOP_MSB 9
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1278
#define ALT_I2C_DATA_CMD_STOP_WIDTH 1
1279
1280
#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
1281
1282
#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
1283
1284
#define ALT_I2C_DATA_CMD_STOP_RESET 0x0
1285
1286
#define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
1287
1288
#define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
1289
1318
#define ALT_I2C_DATA_CMD_RESTART_LSB 10
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1320
#define ALT_I2C_DATA_CMD_RESTART_MSB 10
1321
1322
#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
1323
1324
#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
1325
1326
#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
1327
1328
#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
1329
1330
#define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
1331
1332
#define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
1333
1334
#ifndef __ASSEMBLY__
1335
1345
struct
ALT_I2C_DATA_CMD_s
1346
{
1347
uint32_t
dat
: 8;
1348
uint32_t
cmd
: 1;
1349
uint32_t
stop
: 1;
1350
uint32_t
restart
: 1;
1351
uint32_t : 21;
1352
};
1353
1355
typedef
volatile
struct
ALT_I2C_DATA_CMD_s
ALT_I2C_DATA_CMD_t
;
1356
#endif
/* __ASSEMBLY__ */
1357
1359
#define ALT_I2C_DATA_CMD_RESET 0x00000000
1360
1361
#define ALT_I2C_DATA_CMD_OFST 0x10
1362
1363
#define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
1364
1425
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
1426
1427
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
1428
1429
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
1430
1431
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
1432
1433
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
1434
1435
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
1436
1437
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1438
1439
#define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1440
1441
#ifndef __ASSEMBLY__
1442
1452
struct
ALT_I2C_SS_SCL_HCNT_s
1453
{
1454
uint32_t
ic_ss_scl_hcnt
: 16;
1455
uint32_t : 16;
1456
};
1457
1459
typedef
volatile
struct
ALT_I2C_SS_SCL_HCNT_s
ALT_I2C_SS_SCL_HCNT_t
;
1460
#endif
/* __ASSEMBLY__ */
1461
1463
#define ALT_I2C_SS_SCL_HCNT_RESET 0x00000190
1464
1465
#define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1466
1467
#define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1468
1523
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1524
1525
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1526
1527
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1528
1529
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1530
1531
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1532
1533
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1534
1535
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1536
1537
#define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1538
1539
#ifndef __ASSEMBLY__
1540
1550
struct
ALT_I2C_SS_SCL_LCNT_s
1551
{
1552
uint32_t
ic_ss_scl_lcnt
: 16;
1553
uint32_t : 16;
1554
};
1555
1557
typedef
volatile
struct
ALT_I2C_SS_SCL_LCNT_s
ALT_I2C_SS_SCL_LCNT_t
;
1558
#endif
/* __ASSEMBLY__ */
1559
1561
#define ALT_I2C_SS_SCL_LCNT_RESET 0x000001d6
1562
1563
#define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1564
1565
#define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1566
1626
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1627
1628
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1629
1630
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1631
1632
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1633
1634
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1635
1636
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1637
1638
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1639
1640
#define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1641
1642
#ifndef __ASSEMBLY__
1643
1653
struct
ALT_I2C_FS_SCL_HCNT_s
1654
{
1655
uint32_t
ic_fs_scl_hcnt
: 16;
1656
uint32_t : 16;
1657
};
1658
1660
typedef
volatile
struct
ALT_I2C_FS_SCL_HCNT_s
ALT_I2C_FS_SCL_HCNT_t
;
1661
#endif
/* __ASSEMBLY__ */
1662
1664
#define ALT_I2C_FS_SCL_HCNT_RESET 0x0000003c
1665
1666
#define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1667
1668
#define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1669
1732
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1733
1734
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1735
1736
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1737
1738
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1739
1740
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1741
1742
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1743
1744
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1745
1746
#define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1747
1748
#ifndef __ASSEMBLY__
1749
1759
struct
ALT_I2C_FS_SCL_LCNT_s
1760
{
1761
uint32_t
ic_fs_scl_lcnt
: 16;
1762
uint32_t : 16;
1763
};
1764
1766
typedef
volatile
struct
ALT_I2C_FS_SCL_LCNT_s
ALT_I2C_FS_SCL_LCNT_t
;
1767
#endif
/* __ASSEMBLY__ */
1768
1770
#define ALT_I2C_FS_SCL_LCNT_RESET 0x00000082
1771
1772
#define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1773
1774
#define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1775
1833
#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1834
1835
#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1836
1837
#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1838
1839
#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1840
1841
#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1842
1843
#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1844
1845
#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1846
1847
#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1848
1875
#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1876
1877
#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1878
1879
#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1880
1881
#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1882
1883
#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1884
1885
#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1886
1887
#define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1888
1889
#define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1890
1912
#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1913
1914
#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1915
1916
#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1917
1918
#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1919
1920
#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1921
1922
#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1923
1924
#define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1925
1926
#define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1927
1947
#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1948
1949
#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1950
1951
#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1952
1953
#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1954
1955
#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1956
1957
#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1958
1959
#define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1960
1961
#define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1962
2000
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
2001
2002
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
2003
2004
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
2005
2006
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
2007
2008
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
2009
2010
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
2011
2012
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2013
2014
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2015
2040
#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
2041
2042
#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
2043
2044
#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
2045
2046
#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
2047
2048
#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
2049
2050
#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
2051
2052
#define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2053
2054
#define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2055
2087
#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
2088
2089
#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
2090
2091
#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
2092
2093
#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
2094
2095
#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
2096
2097
#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
2098
2099
#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2100
2101
#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2102
2120
#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
2121
2122
#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
2123
2124
#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
2125
2126
#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
2127
2128
#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
2129
2130
#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
2131
2132
#define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2133
2134
#define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2135
2164
#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
2165
2166
#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
2167
2168
#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
2169
2170
#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
2171
2172
#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
2173
2174
#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
2175
2176
#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2177
2178
#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2179
2220
#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
2221
2222
#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
2223
2224
#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
2225
2226
#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
2227
2228
#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
2229
2230
#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
2231
2232
#define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2233
2234
#define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2235
2251
#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
2252
2253
#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
2254
2255
#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
2256
2257
#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
2258
2259
#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
2260
2261
#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
2262
2263
#define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2264
2265
#define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
2266
2284
#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
2285
2286
#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
2287
2288
#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
2289
2290
#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
2291
2292
#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
2293
2294
#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
2295
2296
#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2297
2298
#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2299
2314
#define ALT_I2C_INTR_STAT_R_RESTART_DET_LSB 12
2315
2316
#define ALT_I2C_INTR_STAT_R_RESTART_DET_MSB 12
2317
2318
#define ALT_I2C_INTR_STAT_R_RESTART_DET_WIDTH 1
2319
2320
#define ALT_I2C_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000
2321
2322
#define ALT_I2C_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff
2323
2324
#define ALT_I2C_INTR_STAT_R_RESTART_DET_RESET 0x0
2325
2326
#define ALT_I2C_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2327
2328
#define ALT_I2C_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2329
2343
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_LSB 13
2344
2345
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_MSB 13
2346
2347
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_WIDTH 1
2348
2349
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET_MSK 0x00002000
2350
2351
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_CLR_MSK 0xffffdfff
2352
2353
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_RESET 0x0
2354
2355
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2356
2357
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2358
2359
#ifndef __ASSEMBLY__
2360
2370
struct
ALT_I2C_INTR_STAT_s
2371
{
2372
const
uint32_t
r_rx_under
: 1;
2373
const
uint32_t
r_rx_over
: 1;
2374
const
uint32_t
r_rx_full
: 1;
2375
const
uint32_t
r_tx_over
: 1;
2376
const
uint32_t
r_tx_empty
: 1;
2377
const
uint32_t
r_rd_req
: 1;
2378
const
uint32_t
r_tx_abrt
: 1;
2379
const
uint32_t
r_rx_done
: 1;
2380
const
uint32_t
r_activity
: 1;
2381
const
uint32_t
r_stop_det
: 1;
2382
const
uint32_t
r_start_det
: 1;
2383
const
uint32_t
r_gen_call
: 1;
2384
const
uint32_t
r_restart_det
: 1;
2385
const
uint32_t
r_master_on_hold
: 1;
2386
uint32_t : 18;
2387
};
2388
2390
typedef
volatile
struct
ALT_I2C_INTR_STAT_s
ALT_I2C_INTR_STAT_t
;
2391
#endif
/* __ASSEMBLY__ */
2392
2394
#define ALT_I2C_INTR_STAT_RESET 0x00000000
2395
2396
#define ALT_I2C_INTR_STAT_OFST 0x2c
2397
2398
#define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
2399
2454
#define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
2455
2456
#define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
2457
2458
#define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
2459
2460
#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
2461
2462
#define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
2463
2464
#define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
2465
2466
#define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2467
2468
#define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2469
2481
#define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
2482
2483
#define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
2484
2485
#define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
2486
2487
#define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
2488
2489
#define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
2490
2491
#define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
2492
2493
#define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2494
2495
#define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2496
2508
#define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
2509
2510
#define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
2511
2512
#define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
2513
2514
#define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
2515
2516
#define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
2517
2518
#define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
2519
2520
#define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2521
2522
#define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2523
2535
#define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
2536
2537
#define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
2538
2539
#define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
2540
2541
#define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
2542
2543
#define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
2544
2545
#define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
2546
2547
#define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2548
2549
#define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2550
2562
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
2563
2564
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
2565
2566
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
2567
2568
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
2569
2570
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
2571
2572
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
2573
2574
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2575
2576
#define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2577
2589
#define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
2590
2591
#define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
2592
2593
#define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
2594
2595
#define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
2596
2597
#define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
2598
2599
#define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
2600
2601
#define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2602
2603
#define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2604
2616
#define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
2617
2618
#define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
2619
2620
#define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
2621
2622
#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
2623
2624
#define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
2625
2626
#define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
2627
2628
#define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2629
2630
#define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2631
2643
#define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
2644
2645
#define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
2646
2647
#define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
2648
2649
#define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
2650
2651
#define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
2652
2653
#define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
2654
2655
#define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2656
2657
#define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2658
2670
#define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
2671
2672
#define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
2673
2674
#define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
2675
2676
#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
2677
2678
#define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
2679
2680
#define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
2681
2682
#define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2683
2684
#define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2685
2697
#define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
2698
2699
#define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
2700
2701
#define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
2702
2703
#define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
2704
2705
#define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
2706
2707
#define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
2708
2709
#define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2710
2711
#define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2712
2724
#define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
2725
2726
#define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
2727
2728
#define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
2729
2730
#define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
2731
2732
#define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
2733
2734
#define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2735
2736
#define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2737
2738
#define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2739
2751
#define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2752
2753
#define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2754
2755
#define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2756
2757
#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2758
2759
#define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2760
2761
#define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2762
2763
#define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2764
2765
#define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2766
2778
#define ALT_I2C_INTR_MSK_M_RESTART_DET_LSB 12
2779
2780
#define ALT_I2C_INTR_MSK_M_RESTART_DET_MSB 12
2781
2782
#define ALT_I2C_INTR_MSK_M_RESTART_DET_WIDTH 1
2783
2784
#define ALT_I2C_INTR_MSK_M_RESTART_DET_SET_MSK 0x00001000
2785
2786
#define ALT_I2C_INTR_MSK_M_RESTART_DET_CLR_MSK 0xffffefff
2787
2788
#define ALT_I2C_INTR_MSK_M_RESTART_DET_RESET 0x0
2789
2790
#define ALT_I2C_INTR_MSK_M_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
2791
2792
#define ALT_I2C_INTR_MSK_M_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
2793
2805
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_LSB 13
2806
2807
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_MSB 13
2808
2809
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_WIDTH 1
2810
2811
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET_MSK 0x00002000
2812
2813
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_CLR_MSK 0xffffdfff
2814
2815
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_RESET 0x0
2816
2817
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
2818
2819
#define ALT_I2C_INTR_MSK_M_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
2820
2821
#ifndef __ASSEMBLY__
2822
2832
struct
ALT_I2C_INTR_MSK_s
2833
{
2834
uint32_t
m_rx_under
: 1;
2835
uint32_t
m_rx_over
: 1;
2836
uint32_t
m_rx_full
: 1;
2837
uint32_t
m_tx_over
: 1;
2838
uint32_t
m_tx_empty
: 1;
2839
uint32_t
m_rd_req
: 1;
2840
uint32_t
m_tx_abrt
: 1;
2841
uint32_t
m_rx_done
: 1;
2842
uint32_t
m_activity
: 1;
2843
uint32_t
m_stop_det
: 1;
2844
uint32_t
m_start_det
: 1;
2845
uint32_t
m_gen_call
: 1;
2846
uint32_t
m_restart_det
: 1;
2847
uint32_t
m_master_on_hold
: 1;
2848
uint32_t : 18;
2849
};
2850
2852
typedef
volatile
struct
ALT_I2C_INTR_MSK_s
ALT_I2C_INTR_MSK_t
;
2853
#endif
/* __ASSEMBLY__ */
2854
2856
#define ALT_I2C_INTR_MSK_RESET 0x000008ff
2857
2858
#define ALT_I2C_INTR_MSK_OFST 0x30
2859
2860
#define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2861
2915
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2916
2917
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2918
2919
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2920
2921
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2922
2923
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2924
2925
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2926
2927
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2928
2929
#define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2930
2957
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2958
2959
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2960
2961
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2962
2963
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2964
2965
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2966
2967
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2968
2969
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2970
2971
#define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2972
2994
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2995
2996
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2997
2998
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
2999
3000
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
3001
3002
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
3003
3004
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
3005
3006
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
3007
3008
#define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
3009
3029
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
3030
3031
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
3032
3033
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
3034
3035
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
3036
3037
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
3038
3039
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
3040
3041
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
3042
3043
#define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
3044
3084
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
3085
3086
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
3087
3088
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
3089
3090
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
3091
3092
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
3093
3094
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
3095
3096
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
3097
3098
#define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
3099
3124
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
3125
3126
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
3127
3128
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
3129
3130
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
3131
3132
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
3133
3134
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
3135
3136
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
3137
3138
#define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
3139
3171
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
3172
3173
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
3174
3175
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
3176
3177
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
3178
3179
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
3180
3181
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
3182
3183
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
3184
3185
#define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
3186
3204
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
3205
3206
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
3207
3208
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
3209
3210
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
3211
3212
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
3213
3214
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
3215
3216
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
3217
3218
#define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
3219
3248
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
3249
3250
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
3251
3252
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
3253
3254
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
3255
3256
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
3257
3258
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
3259
3260
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
3261
3262
#define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
3263
3303
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
3304
3305
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
3306
3307
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
3308
3309
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
3310
3311
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
3312
3313
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
3314
3315
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
3316
3317
#define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
3318
3334
#define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
3335
3336
#define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
3337
3338
#define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
3339
3340
#define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
3341
3342
#define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
3343
3344
#define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
3345
3346
#define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
3347
3348
#define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
3349
3367
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
3368
3369
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
3370
3371
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
3372
3373
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
3374
3375
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
3376
3377
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
3378
3379
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
3380
3381
#define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
3382
3406
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_LSB 12
3407
3408
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_MSB 12
3409
3410
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_WIDTH 1
3411
3412
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET_MSK 0x00001000
3413
3414
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_CLR_MSK 0xffffefff
3415
3416
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_RESET 0x0
3417
3418
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12)
3419
3420
#define ALT_I2C_RAW_INTR_STAT_RESTART_DET_SET(value) (((value) << 12) & 0x00001000)
3421
3435
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_LSB 13
3436
3437
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_MSB 13
3438
3439
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_WIDTH 1
3440
3441
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET_MSK 0x00002000
3442
3443
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_CLR_MSK 0xffffdfff
3444
3445
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_RESET 0x0
3446
3447
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13)
3448
3449
#define ALT_I2C_RAW_INTR_STAT_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000)
3450
3451
#ifndef __ASSEMBLY__
3452
3462
struct
ALT_I2C_RAW_INTR_STAT_s
3463
{
3464
const
uint32_t
rx_under
: 1;
3465
const
uint32_t
rx_over
: 1;
3466
const
uint32_t
rx_full
: 1;
3467
const
uint32_t
tx_over
: 1;
3468
const
uint32_t
tx_empty
: 1;
3469
const
uint32_t
rd_req
: 1;
3470
const
uint32_t
tx_abrt
: 1;
3471
const
uint32_t
rx_done
: 1;
3472
const
uint32_t
activity
: 1;
3473
const
uint32_t
stop_det
: 1;
3474
const
uint32_t
start_det
: 1;
3475
const
uint32_t
gen_call
: 1;
3476
const
uint32_t
restart_det
: 1;
3477
const
uint32_t
master_on_hold
: 1;
3478
uint32_t : 18;
3479
};
3480
3482
typedef
volatile
struct
ALT_I2C_RAW_INTR_STAT_s
ALT_I2C_RAW_INTR_STAT_t
;
3483
#endif
/* __ASSEMBLY__ */
3484
3486
#define ALT_I2C_RAW_INTR_STAT_RESET 0x00000000
3487
3488
#define ALT_I2C_RAW_INTR_STAT_OFST 0x34
3489
3490
#define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
3491
3538
#define ALT_I2C_RX_TL_RX_TL_LSB 0
3539
3540
#define ALT_I2C_RX_TL_RX_TL_MSB 7
3541
3542
#define ALT_I2C_RX_TL_RX_TL_WIDTH 8
3543
3544
#define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
3545
3546
#define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
3547
3548
#define ALT_I2C_RX_TL_RX_TL_RESET 0x0
3549
3550
#define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3551
3552
#define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
3553
3554
#ifndef __ASSEMBLY__
3555
3565
struct
ALT_I2C_RX_TL_s
3566
{
3567
uint32_t
rx_tl
: 8;
3568
uint32_t : 24;
3569
};
3570
3572
typedef
volatile
struct
ALT_I2C_RX_TL_s
ALT_I2C_RX_TL_t
;
3573
#endif
/* __ASSEMBLY__ */
3574
3576
#define ALT_I2C_RX_TL_RESET 0x00000000
3577
3578
#define ALT_I2C_RX_TL_OFST 0x38
3579
3580
#define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
3581
3628
#define ALT_I2C_TX_TL_TX_TL_LSB 0
3629
3630
#define ALT_I2C_TX_TL_TX_TL_MSB 7
3631
3632
#define ALT_I2C_TX_TL_TX_TL_WIDTH 8
3633
3634
#define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
3635
3636
#define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
3637
3638
#define ALT_I2C_TX_TL_TX_TL_RESET 0x0
3639
3640
#define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
3641
3642
#define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
3643
3644
#ifndef __ASSEMBLY__
3645
3655
struct
ALT_I2C_TX_TL_s
3656
{
3657
uint32_t
tx_tl
: 8;
3658
uint32_t : 24;
3659
};
3660
3662
typedef
volatile
struct
ALT_I2C_TX_TL_s
ALT_I2C_TX_TL_t
;
3663
#endif
/* __ASSEMBLY__ */
3664
3666
#define ALT_I2C_TX_TL_RESET 0x00000000
3667
3668
#define ALT_I2C_TX_TL_OFST 0x3c
3669
3670
#define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
3671
3710
#define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
3711
3712
#define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
3713
3714
#define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
3715
3716
#define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
3717
3718
#define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
3719
3720
#define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
3721
3722
#define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
3723
3724
#define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
3725
3726
#ifndef __ASSEMBLY__
3727
3737
struct
ALT_I2C_CLR_INTR_s
3738
{
3739
const
uint32_t
clr_intr
: 1;
3740
uint32_t : 31;
3741
};
3742
3744
typedef
volatile
struct
ALT_I2C_CLR_INTR_s
ALT_I2C_CLR_INTR_t
;
3745
#endif
/* __ASSEMBLY__ */
3746
3748
#define ALT_I2C_CLR_INTR_RESET 0x00000000
3749
3750
#define ALT_I2C_CLR_INTR_OFST 0x40
3751
3752
#define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
3753
3786
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
3787
3788
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
3789
3790
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
3791
3792
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
3793
3794
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
3795
3796
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
3797
3798
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
3799
3800
#define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
3801
3802
#ifndef __ASSEMBLY__
3803
3813
struct
ALT_I2C_CLR_RX_UNDER_s
3814
{
3815
const
uint32_t
clr_rx_under
: 1;
3816
uint32_t : 31;
3817
};
3818
3820
typedef
volatile
struct
ALT_I2C_CLR_RX_UNDER_s
ALT_I2C_CLR_RX_UNDER_t
;
3821
#endif
/* __ASSEMBLY__ */
3822
3824
#define ALT_I2C_CLR_RX_UNDER_RESET 0x00000000
3825
3826
#define ALT_I2C_CLR_RX_UNDER_OFST 0x44
3827
3828
#define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
3829
3862
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
3863
3864
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
3865
3866
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
3867
3868
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
3869
3870
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
3871
3872
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
3873
3874
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3875
3876
#define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
3877
3878
#ifndef __ASSEMBLY__
3879
3889
struct
ALT_I2C_CLR_RX_OVER_s
3890
{
3891
const
uint32_t
clr_rx_over
: 1;
3892
uint32_t : 31;
3893
};
3894
3896
typedef
volatile
struct
ALT_I2C_CLR_RX_OVER_s
ALT_I2C_CLR_RX_OVER_t
;
3897
#endif
/* __ASSEMBLY__ */
3898
3900
#define ALT_I2C_CLR_RX_OVER_RESET 0x00000000
3901
3902
#define ALT_I2C_CLR_RX_OVER_OFST 0x48
3903
3904
#define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
3905
3938
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
3939
3940
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
3941
3942
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
3943
3944
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
3945
3946
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
3947
3948
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
3949
3950
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
3951
3952
#define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
3953
3954
#ifndef __ASSEMBLY__
3955
3965
struct
ALT_I2C_CLR_TX_OVER_s
3966
{
3967
const
uint32_t
clr_tx_over
: 1;
3968
uint32_t : 31;
3969
};
3970
3972
typedef
volatile
struct
ALT_I2C_CLR_TX_OVER_s
ALT_I2C_CLR_TX_OVER_t
;
3973
#endif
/* __ASSEMBLY__ */
3974
3976
#define ALT_I2C_CLR_TX_OVER_RESET 0x00000000
3977
3978
#define ALT_I2C_CLR_TX_OVER_OFST 0x4c
3979
3980
#define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
3981
4014
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
4015
4016
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
4017
4018
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
4019
4020
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
4021
4022
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
4023
4024
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
4025
4026
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
4027
4028
#define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
4029
4030
#ifndef __ASSEMBLY__
4031
4041
struct
ALT_I2C_CLR_RD_REQ_s
4042
{
4043
const
uint32_t
clr_rd_req
: 1;
4044
uint32_t : 31;
4045
};
4046
4048
typedef
volatile
struct
ALT_I2C_CLR_RD_REQ_s
ALT_I2C_CLR_RD_REQ_t
;
4049
#endif
/* __ASSEMBLY__ */
4050
4052
#define ALT_I2C_CLR_RD_REQ_RESET 0x00000000
4053
4054
#define ALT_I2C_CLR_RD_REQ_OFST 0x50
4055
4056
#define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
4057
4100
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
4101
4102
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
4103
4104
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
4105
4106
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
4107
4108
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
4109
4110
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
4111
4112
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
4113
4114
#define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
4115
4116
#ifndef __ASSEMBLY__
4117
4127
struct
ALT_I2C_CLR_TX_ABRT_s
4128
{
4129
const
uint32_t
clr_tx_abort
: 1;
4130
uint32_t : 31;
4131
};
4132
4134
typedef
volatile
struct
ALT_I2C_CLR_TX_ABRT_s
ALT_I2C_CLR_TX_ABRT_t
;
4135
#endif
/* __ASSEMBLY__ */
4136
4138
#define ALT_I2C_CLR_TX_ABRT_RESET 0x00000000
4139
4140
#define ALT_I2C_CLR_TX_ABRT_OFST 0x54
4141
4142
#define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
4143
4176
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
4177
4178
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
4179
4180
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
4181
4182
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
4183
4184
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
4185
4186
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
4187
4188
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
4189
4190
#define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
4191
4192
#ifndef __ASSEMBLY__
4193
4203
struct
ALT_I2C_CLR_RX_DONE_s
4204
{
4205
const
uint32_t
clr_rx_done
: 1;
4206
uint32_t : 31;
4207
};
4208
4210
typedef
volatile
struct
ALT_I2C_CLR_RX_DONE_s
ALT_I2C_CLR_RX_DONE_t
;
4211
#endif
/* __ASSEMBLY__ */
4212
4214
#define ALT_I2C_CLR_RX_DONE_RESET 0x00000000
4215
4216
#define ALT_I2C_CLR_RX_DONE_OFST 0x58
4217
4218
#define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
4219
4264
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
4265
4266
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
4267
4268
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
4269
4270
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
4271
4272
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
4273
4274
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
4275
4276
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4277
4278
#define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4279
4280
#ifndef __ASSEMBLY__
4281
4291
struct
ALT_I2C_CLR_ACTIVITY_s
4292
{
4293
const
uint32_t
clr_activity
: 1;
4294
uint32_t : 31;
4295
};
4296
4298
typedef
volatile
struct
ALT_I2C_CLR_ACTIVITY_s
ALT_I2C_CLR_ACTIVITY_t
;
4299
#endif
/* __ASSEMBLY__ */
4300
4302
#define ALT_I2C_CLR_ACTIVITY_RESET 0x00000000
4303
4304
#define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
4305
4306
#define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
4307
4340
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
4341
4342
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
4343
4344
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
4345
4346
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
4347
4348
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
4349
4350
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
4351
4352
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
4353
4354
#define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
4355
4356
#ifndef __ASSEMBLY__
4357
4367
struct
ALT_I2C_CLR_STOP_DET_s
4368
{
4369
const
uint32_t
clr_stop_det
: 1;
4370
uint32_t : 31;
4371
};
4372
4374
typedef
volatile
struct
ALT_I2C_CLR_STOP_DET_s
ALT_I2C_CLR_STOP_DET_t
;
4375
#endif
/* __ASSEMBLY__ */
4376
4378
#define ALT_I2C_CLR_STOP_DET_RESET 0x00000000
4379
4380
#define ALT_I2C_CLR_STOP_DET_OFST 0x60
4381
4382
#define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
4383
4416
#define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
4417
4418
#define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
4419
4420
#define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
4421
4422
#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
4423
4424
#define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
4425
4426
#define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
4427
4428
#define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
4429
4430
#define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
4431
4432
#ifndef __ASSEMBLY__
4433
4443
struct
ALT_I2C_CLR_START_DET_s
4444
{
4445
const
uint32_t
clr_start_det
: 1;
4446
uint32_t : 31;
4447
};
4448
4450
typedef
volatile
struct
ALT_I2C_CLR_START_DET_s
ALT_I2C_CLR_START_DET_t
;
4451
#endif
/* __ASSEMBLY__ */
4452
4454
#define ALT_I2C_CLR_START_DET_RESET 0x00000000
4455
4456
#define ALT_I2C_CLR_START_DET_OFST 0x64
4457
4458
#define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
4459
4492
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
4493
4494
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
4495
4496
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
4497
4498
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
4499
4500
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
4501
4502
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
4503
4504
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
4505
4506
#define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
4507
4508
#ifndef __ASSEMBLY__
4509
4519
struct
ALT_I2C_CLR_GEN_CALL_s
4520
{
4521
const
uint32_t
clr_gen_call
: 1;
4522
uint32_t : 31;
4523
};
4524
4526
typedef
volatile
struct
ALT_I2C_CLR_GEN_CALL_s
ALT_I2C_CLR_GEN_CALL_t
;
4527
#endif
/* __ASSEMBLY__ */
4528
4530
#define ALT_I2C_CLR_GEN_CALL_RESET 0x00000000
4531
4532
#define ALT_I2C_CLR_GEN_CALL_OFST 0x68
4533
4534
#define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
4535
4616
#define ALT_I2C_EN_EN_E_DIS 0x0
4617
4622
#define ALT_I2C_EN_EN_E_EN 0x1
4623
4625
#define ALT_I2C_EN_EN_LSB 0
4626
4627
#define ALT_I2C_EN_EN_MSB 0
4628
4629
#define ALT_I2C_EN_EN_WIDTH 1
4630
4631
#define ALT_I2C_EN_EN_SET_MSK 0x00000001
4632
4633
#define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
4634
4635
#define ALT_I2C_EN_EN_RESET 0x0
4636
4637
#define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
4638
4639
#define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
4640
4673
#define ALT_I2C_EN_TXABT_LSB 1
4674
4675
#define ALT_I2C_EN_TXABT_MSB 1
4676
4677
#define ALT_I2C_EN_TXABT_WIDTH 1
4678
4679
#define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
4680
4681
#define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
4682
4683
#define ALT_I2C_EN_TXABT_RESET 0x0
4684
4685
#define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
4686
4687
#define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
4688
4689
#ifndef __ASSEMBLY__
4690
4700
struct
ALT_I2C_EN_s
4701
{
4702
uint32_t
enable
: 1;
4703
uint32_t
txabort
: 1;
4704
uint32_t : 30;
4705
};
4706
4708
typedef
volatile
struct
ALT_I2C_EN_s
ALT_I2C_EN_t
;
4709
#endif
/* __ASSEMBLY__ */
4710
4712
#define ALT_I2C_EN_RESET 0x00000000
4713
4714
#define ALT_I2C_EN_OFST 0x6c
4715
4716
#define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
4717
4776
#define ALT_I2C_STAT_ACTIVITY_LSB 0
4777
4778
#define ALT_I2C_STAT_ACTIVITY_MSB 0
4779
4780
#define ALT_I2C_STAT_ACTIVITY_WIDTH 1
4781
4782
#define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
4783
4784
#define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
4785
4786
#define ALT_I2C_STAT_ACTIVITY_RESET 0x0
4787
4788
#define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
4789
4790
#define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
4791
4822
#define ALT_I2C_STAT_TFNF_E_FULL 0x0
4823
4828
#define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
4829
4831
#define ALT_I2C_STAT_TFNF_LSB 1
4832
4833
#define ALT_I2C_STAT_TFNF_MSB 1
4834
4835
#define ALT_I2C_STAT_TFNF_WIDTH 1
4836
4837
#define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
4838
4839
#define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
4840
4841
#define ALT_I2C_STAT_TFNF_RESET 0x1
4842
4843
#define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
4844
4845
#define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
4846
4879
#define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
4880
4885
#define ALT_I2C_STAT_TFE_E_EMPTY 0x1
4886
4888
#define ALT_I2C_STAT_TFE_LSB 2
4889
4890
#define ALT_I2C_STAT_TFE_MSB 2
4891
4892
#define ALT_I2C_STAT_TFE_WIDTH 1
4893
4894
#define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
4895
4896
#define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
4897
4898
#define ALT_I2C_STAT_TFE_RESET 0x1
4899
4900
#define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
4901
4902
#define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
4903
4934
#define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
4935
4940
#define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
4941
4943
#define ALT_I2C_STAT_RFNE_LSB 3
4944
4945
#define ALT_I2C_STAT_RFNE_MSB 3
4946
4947
#define ALT_I2C_STAT_RFNE_WIDTH 1
4948
4949
#define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
4950
4951
#define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
4952
4953
#define ALT_I2C_STAT_RFNE_RESET 0x0
4954
4955
#define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
4956
4957
#define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
4958
4991
#define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
4992
4997
#define ALT_I2C_STAT_RFF_E_FULL 0x1
4998
5000
#define ALT_I2C_STAT_RFF_LSB 4
5001
5002
#define ALT_I2C_STAT_RFF_MSB 4
5003
5004
#define ALT_I2C_STAT_RFF_WIDTH 1
5005
5006
#define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
5007
5008
#define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
5009
5010
#define ALT_I2C_STAT_RFF_RESET 0x0
5011
5012
#define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
5013
5014
#define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
5015
5058
#define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
5059
5064
#define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
5065
5067
#define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
5068
5069
#define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
5070
5071
#define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
5072
5073
#define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
5074
5075
#define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
5076
5077
#define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
5078
5079
#define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
5080
5081
#define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
5082
5119
#define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
5120
5125
#define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
5126
5128
#define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
5129
5130
#define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
5131
5132
#define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
5133
5134
#define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
5135
5136
#define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
5137
5138
#define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
5139
5140
#define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
5141
5142
#define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
5143
5144
#ifndef __ASSEMBLY__
5145
5155
struct
ALT_I2C_STAT_s
5156
{
5157
const
uint32_t
activity
: 1;
5158
const
uint32_t
tfnf
: 1;
5159
const
uint32_t
tfe
: 1;
5160
const
uint32_t
rfne
: 1;
5161
const
uint32_t
rff
: 1;
5162
const
uint32_t
mst_activity
: 1;
5163
const
uint32_t
slv_activity
: 1;
5164
uint32_t : 25;
5165
};
5166
5168
typedef
volatile
struct
ALT_I2C_STAT_s
ALT_I2C_STAT_t
;
5169
#endif
/* __ASSEMBLY__ */
5170
5172
#define ALT_I2C_STAT_RESET 0x00000006
5173
5174
#define ALT_I2C_STAT_OFST 0x70
5175
5176
#define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
5177
5232
#define ALT_I2C_TXFLR_TXFLR_LSB 0
5233
5234
#define ALT_I2C_TXFLR_TXFLR_MSB 6
5235
5236
#define ALT_I2C_TXFLR_TXFLR_WIDTH 7
5237
5238
#define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
5239
5240
#define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
5241
5242
#define ALT_I2C_TXFLR_TXFLR_RESET 0x0
5243
5244
#define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5245
5246
#define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
5247
5248
#ifndef __ASSEMBLY__
5249
5259
struct
ALT_I2C_TXFLR_s
5260
{
5261
const
uint32_t
txflr
: 7;
5262
uint32_t : 25;
5263
};
5264
5266
typedef
volatile
struct
ALT_I2C_TXFLR_s
ALT_I2C_TXFLR_t
;
5267
#endif
/* __ASSEMBLY__ */
5268
5270
#define ALT_I2C_TXFLR_RESET 0x00000000
5271
5272
#define ALT_I2C_TXFLR_OFST 0x74
5273
5274
#define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
5275
5328
#define ALT_I2C_RXFLR_RXFLR_LSB 0
5329
5330
#define ALT_I2C_RXFLR_RXFLR_MSB 6
5331
5332
#define ALT_I2C_RXFLR_RXFLR_WIDTH 7
5333
5334
#define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
5335
5336
#define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
5337
5338
#define ALT_I2C_RXFLR_RXFLR_RESET 0x0
5339
5340
#define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
5341
5342
#define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
5343
5344
#ifndef __ASSEMBLY__
5345
5355
struct
ALT_I2C_RXFLR_s
5356
{
5357
const
uint32_t
rxflr
: 7;
5358
uint32_t : 25;
5359
};
5360
5362
typedef
volatile
struct
ALT_I2C_RXFLR_s
ALT_I2C_RXFLR_t
;
5363
#endif
/* __ASSEMBLY__ */
5364
5366
#define ALT_I2C_RXFLR_RESET 0x00000000
5367
5368
#define ALT_I2C_RXFLR_OFST 0x78
5369
5370
#define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
5371
5421
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_LSB 0
5422
5423
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_MSB 15
5424
5425
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_WIDTH 16
5426
5427
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET_MSK 0x0000ffff
5428
5429
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_CLR_MSK 0xffff0000
5430
5431
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_RESET 0x1
5432
5433
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
5434
5435
#define ALT_I2C_SDA_HOLD_IC_SDA_TX_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
5436
5450
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_LSB 16
5451
5452
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_MSB 23
5453
5454
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_WIDTH 8
5455
5456
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET_MSK 0x00ff0000
5457
5458
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_CLR_MSK 0xff00ffff
5459
5460
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_RESET 0x0
5461
5462
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_GET(value) (((value) & 0x00ff0000) >> 16)
5463
5464
#define ALT_I2C_SDA_HOLD_IC_SDA_RX_HOLD_SET(value) (((value) << 16) & 0x00ff0000)
5465
5466
#ifndef __ASSEMBLY__
5467
5477
struct
ALT_I2C_SDA_HOLD_s
5478
{
5479
uint32_t
ic_sda_tx_hold
: 16;
5480
uint32_t
ic_sda_rx_hold
: 8;
5481
uint32_t : 8;
5482
};
5483
5485
typedef
volatile
struct
ALT_I2C_SDA_HOLD_s
ALT_I2C_SDA_HOLD_t
;
5486
#endif
/* __ASSEMBLY__ */
5487
5489
#define ALT_I2C_SDA_HOLD_RESET 0x00000001
5490
5491
#define ALT_I2C_SDA_HOLD_OFST 0x7c
5492
5493
#define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
5494
5574
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
5575
5576
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
5577
5578
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
5579
5580
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
5581
5582
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
5583
5584
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
5585
5586
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
5587
5588
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
5589
5609
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
5610
5611
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
5612
5613
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
5614
5615
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
5616
5617
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
5618
5619
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
5620
5621
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
5622
5623
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
5624
5644
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
5645
5646
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
5647
5648
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
5649
5650
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
5651
5652
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
5653
5654
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
5655
5656
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
5657
5658
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
5659
5683
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
5684
5685
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
5686
5687
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
5688
5689
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
5690
5691
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
5692
5693
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
5694
5695
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
5696
5697
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
5698
5716
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
5717
5718
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
5719
5720
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
5721
5722
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
5723
5724
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
5725
5726
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
5727
5728
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
5729
5730
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
5731
5753
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
5754
5755
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
5756
5757
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
5758
5759
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
5760
5761
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
5762
5763
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
5764
5765
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
5766
5767
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
5768
5786
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
5787
5788
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
5789
5790
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
5791
5792
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
5793
5794
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
5795
5796
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
5797
5798
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
5799
5800
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
5801
5817
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
5818
5819
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
5820
5821
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
5822
5823
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
5824
5825
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
5826
5827
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
5828
5829
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
5830
5831
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
5832
5856
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
5857
5858
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
5859
5860
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
5861
5862
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
5863
5864
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
5865
5866
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
5867
5868
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
5869
5870
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
5871
5913
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
5914
5915
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
5916
5917
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
5918
5919
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
5920
5921
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
5922
5923
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
5924
5925
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
5926
5927
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
5928
5948
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
5949
5950
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
5951
5952
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
5953
5954
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
5955
5956
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
5957
5958
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
5959
5960
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
5961
5962
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
5963
5981
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
5982
5983
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
5984
5985
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
5986
5987
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
5988
5989
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
5990
5991
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
5992
5993
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
5994
5995
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
5996
6018
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
6019
6020
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
6021
6022
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
6023
6024
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
6025
6026
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
6027
6028
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
6029
6030
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
6031
6032
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
6033
6053
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
6054
6055
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
6056
6057
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
6058
6059
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
6060
6061
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
6062
6063
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
6064
6065
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
6066
6067
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
6068
6106
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
6107
6108
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
6109
6110
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
6111
6112
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
6113
6114
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
6115
6116
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
6117
6118
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
6119
6120
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
6121
6143
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
6144
6145
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
6146
6147
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
6148
6149
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
6150
6151
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
6152
6153
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
6154
6155
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
6156
6157
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
6158
6174
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_LSB 16
6175
6176
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_MSB 16
6177
6178
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_WIDTH 1
6179
6180
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET_MSK 0x00010000
6181
6182
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_CLR_MSK 0xfffeffff
6183
6184
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_RESET 0x0
6185
6186
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_GET(value) (((value) & 0x00010000) >> 16)
6187
6188
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET(value) (((value) << 16) & 0x00010000)
6189
6201
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_LSB 17
6202
6203
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_MSB 22
6204
6205
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_WIDTH 6
6206
6207
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET_MSK 0x007e0000
6208
6209
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_CLR_MSK 0xff81ffff
6210
6211
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_RESET 0x0
6212
6213
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_GET(value) (((value) & 0x007e0000) >> 17)
6214
6215
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET(value) (((value) << 17) & 0x007e0000)
6216
6234
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_LSB 23
6235
6236
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_MSB 31
6237
6238
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_WIDTH 9
6239
6240
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET_MSK 0xff800000
6241
6242
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_CLR_MSK 0x007fffff
6243
6244
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_RESET 0x0
6245
6246
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_GET(value) (((value) & 0xff800000) >> 23)
6247
6248
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET(value) (((value) << 23) & 0xff800000)
6249
6250
#ifndef __ASSEMBLY__
6251
6261
struct
ALT_I2C_TX_ABRT_SRC_s
6262
{
6263
const
uint32_t
abrt_7b_addr_noack
: 1;
6264
const
uint32_t
abrt_10addr1_noack
: 1;
6265
const
uint32_t
abrt_10addr2_noack
: 1;
6266
const
uint32_t
abrt_txdata_noack
: 1;
6267
const
uint32_t
abrt_gcall_noack
: 1;
6268
const
uint32_t
abrt_gcall_read
: 1;
6269
const
uint32_t
abrt_hs_ackdet
: 1;
6270
const
uint32_t
abrt_sbyte_ackdet
: 1;
6271
const
uint32_t
abrt_hs_norstrt
: 1;
6272
const
uint32_t
abrt_sbyte_norstrt
: 1;
6273
const
uint32_t
abrt_10b_rd_norstrt
: 1;
6274
const
uint32_t
abrt_master_dis
: 1;
6275
const
uint32_t
arb_lost
: 1;
6276
const
uint32_t
abrt_slvflush_txfifo
: 1;
6277
const
uint32_t
abrt_slv_arblost
: 1;
6278
const
uint32_t
abrt_slvrd_intx
: 1;
6279
const
uint32_t
abrt_user_abrt
: 1;
6280
const
uint32_t
rsvd_ic_tx_abrt_source_22to17
: 6;
6281
const
uint32_t
tx_flush_cnt
: 9;
6282
};
6283
6285
typedef
volatile
struct
ALT_I2C_TX_ABRT_SRC_s
ALT_I2C_TX_ABRT_SRC_t
;
6286
#endif
/* __ASSEMBLY__ */
6287
6289
#define ALT_I2C_TX_ABRT_SRC_RESET 0x00000000
6290
6291
#define ALT_I2C_TX_ABRT_SRC_OFST 0x80
6292
6293
#define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
6294
6368
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
6369
6374
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
6375
6377
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
6378
6379
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
6380
6381
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
6382
6383
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
6384
6385
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
6386
6387
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
6388
6389
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
6390
6391
#define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
6392
6393
#ifndef __ASSEMBLY__
6394
6404
struct
ALT_I2C_SLV_DATA_NACK_ONLY_s
6405
{
6406
uint32_t
nack
: 1;
6407
uint32_t : 31;
6408
};
6409
6411
typedef
volatile
struct
ALT_I2C_SLV_DATA_NACK_ONLY_s
ALT_I2C_SLV_DATA_NACK_ONLY_t
;
6412
#endif
/* __ASSEMBLY__ */
6413
6415
#define ALT_I2C_SLV_DATA_NACK_ONLY_RESET 0x00000000
6416
6417
#define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
6418
6419
#define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
6420
6487
#define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
6488
6493
#define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
6494
6496
#define ALT_I2C_DMA_CR_RDMAE_LSB 0
6497
6498
#define ALT_I2C_DMA_CR_RDMAE_MSB 0
6499
6500
#define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
6501
6502
#define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
6503
6504
#define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
6505
6506
#define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
6507
6508
#define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
6509
6510
#define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
6511
6542
#define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
6543
6548
#define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
6549
6551
#define ALT_I2C_DMA_CR_TDMAE_LSB 1
6552
6553
#define ALT_I2C_DMA_CR_TDMAE_MSB 1
6554
6555
#define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
6556
6557
#define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
6558
6559
#define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
6560
6561
#define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
6562
6563
#define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
6564
6565
#define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
6566
6576
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_LSB 2
6577
6578
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_MSB 31
6579
6580
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_WIDTH 30
6581
6582
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET_MSK 0xfffffffc
6583
6584
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_CLR_MSK 0x00000003
6585
6586
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_RESET 0x0
6587
6588
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_GET(value) (((value) & 0xfffffffc) >> 2)
6589
6590
#define ALT_I2C_DMA_CR_RSVD_IC_DMA_CR_31TO2_SET(value) (((value) << 2) & 0xfffffffc)
6591
6592
#ifndef __ASSEMBLY__
6593
6603
struct
ALT_I2C_DMA_CR_s
6604
{
6605
uint32_t
rdmae
: 1;
6606
uint32_t
tdmae
: 1;
6607
const
uint32_t
rsvd_ic_dma_cr_31to2
: 30;
6608
};
6609
6611
typedef
volatile
struct
ALT_I2C_DMA_CR_s
ALT_I2C_DMA_CR_t
;
6612
#endif
/* __ASSEMBLY__ */
6613
6615
#define ALT_I2C_DMA_CR_RESET 0x00000000
6616
6617
#define ALT_I2C_DMA_CR_OFST 0x88
6618
6619
#define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
6620
6675
#define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
6676
6677
#define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
6678
6679
#define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
6680
6681
#define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
6682
6683
#define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
6684
6685
#define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
6686
6687
#define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
6688
6689
#define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
6690
6691
#ifndef __ASSEMBLY__
6692
6702
struct
ALT_I2C_DMA_TDLR_s
6703
{
6704
uint32_t
dmatdl
: 6;
6705
uint32_t : 26;
6706
};
6707
6709
typedef
volatile
struct
ALT_I2C_DMA_TDLR_s
ALT_I2C_DMA_TDLR_t
;
6710
#endif
/* __ASSEMBLY__ */
6711
6713
#define ALT_I2C_DMA_TDLR_RESET 0x00000000
6714
6715
#define ALT_I2C_DMA_TDLR_OFST 0x8c
6716
6717
#define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
6718
6775
#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
6776
6777
#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
6778
6779
#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
6780
6781
#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
6782
6783
#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
6784
6785
#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
6786
6787
#define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
6788
6789
#define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
6790
6791
#ifndef __ASSEMBLY__
6792
6802
struct
ALT_I2C_DMA_RDLR_s
6803
{
6804
uint32_t
dmardl
: 6;
6805
uint32_t : 26;
6806
};
6807
6809
typedef
volatile
struct
ALT_I2C_DMA_RDLR_s
ALT_I2C_DMA_RDLR_t
;
6810
#endif
/* __ASSEMBLY__ */
6811
6813
#define ALT_I2C_DMA_RDLR_RESET 0x00000000
6814
6815
#define ALT_I2C_DMA_RDLR_OFST 0x90
6816
6817
#define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
6818
6869
#define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
6870
6871
#define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
6872
6873
#define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
6874
6875
#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
6876
6877
#define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
6878
6879
#define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
6880
6881
#define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
6882
6883
#define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
6884
6885
#ifndef __ASSEMBLY__
6886
6896
struct
ALT_I2C_SDA_SETUP_s
6897
{
6898
uint32_t
sda_setup
: 8;
6899
uint32_t : 24;
6900
};
6901
6903
typedef
volatile
struct
ALT_I2C_SDA_SETUP_s
ALT_I2C_SDA_SETUP_t
;
6904
#endif
/* __ASSEMBLY__ */
6905
6907
#define ALT_I2C_SDA_SETUP_RESET 0x00000064
6908
6909
#define ALT_I2C_SDA_SETUP_OFST 0x94
6910
6911
#define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
6912
6972
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
6973
6978
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
6979
6981
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
6982
6983
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
6984
6985
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
6986
6987
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
6988
6989
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
6990
6991
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
6992
6993
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
6994
6995
#define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
6996
7006
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_LSB 1
7007
7008
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_MSB 31
7009
7010
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_WIDTH 31
7011
7012
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET_MSK 0xfffffffe
7013
7014
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_CLR_MSK 0x00000001
7015
7016
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_RESET 0x0
7017
7018
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_GET(value) (((value) & 0xfffffffe) >> 1)
7019
7020
#define ALT_I2C_ACK_GENERAL_CALL_RSVD_IC_ACK_GEN_31TO1_SET(value) (((value) << 1) & 0xfffffffe)
7021
7022
#ifndef __ASSEMBLY__
7023
7033
struct
ALT_I2C_ACK_GENERAL_CALL_s
7034
{
7035
uint32_t
ack_gen_call
: 1;
7036
const
uint32_t
rsvd_ic_ack_gen_31to1
: 31;
7037
};
7038
7040
typedef
volatile
struct
ALT_I2C_ACK_GENERAL_CALL_s
ALT_I2C_ACK_GENERAL_CALL_t
;
7041
#endif
/* __ASSEMBLY__ */
7042
7044
#define ALT_I2C_ACK_GENERAL_CALL_RESET 0x00000001
7045
7046
#define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
7047
7048
#define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
7049
7124
#define ALT_I2C_EN_STAT_IC_EN_LSB 0
7125
7126
#define ALT_I2C_EN_STAT_IC_EN_MSB 0
7127
7128
#define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
7129
7130
#define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
7131
7132
#define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
7133
7134
#define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
7135
7136
#define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
7137
7138
#define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
7139
7195
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
7196
7197
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
7198
7199
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
7200
7201
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
7202
7203
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
7204
7205
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
7206
7207
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
7208
7209
#define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
7210
7252
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
7253
7254
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
7255
7256
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
7257
7258
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
7259
7260
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
7261
7262
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
7263
7264
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
7265
7266
#define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
7267
7268
#ifndef __ASSEMBLY__
7269
7279
struct
ALT_I2C_EN_STAT_s
7280
{
7281
const
uint32_t
ic_en
: 1;
7282
const
uint32_t
slv_disabled_while_busy
: 1;
7283
const
uint32_t
slv_rx_data_lost
: 1;
7284
uint32_t : 29;
7285
};
7286
7288
typedef
volatile
struct
ALT_I2C_EN_STAT_s
ALT_I2C_EN_STAT_t
;
7289
#endif
/* __ASSEMBLY__ */
7290
7292
#define ALT_I2C_EN_STAT_RESET 0x00000000
7293
7294
#define ALT_I2C_EN_STAT_OFST 0x9c
7295
7296
#define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
7297
7357
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_LSB 0
7358
7359
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_MSB 7
7360
7361
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_WIDTH 8
7362
7363
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET_MSK 0x000000ff
7364
7365
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_CLR_MSK 0xffffff00
7366
7367
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_RESET 0x2
7368
7369
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
7370
7371
#define ALT_I2C_FS_SPKLEN_IC_FS_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
7372
7373
#ifndef __ASSEMBLY__
7374
7384
struct
ALT_I2C_FS_SPKLEN_s
7385
{
7386
uint32_t
ic_fs_spklen
: 8;
7387
uint32_t : 24;
7388
};
7389
7391
typedef
volatile
struct
ALT_I2C_FS_SPKLEN_s
ALT_I2C_FS_SPKLEN_t
;
7392
#endif
/* __ASSEMBLY__ */
7393
7395
#define ALT_I2C_FS_SPKLEN_RESET 0x00000002
7396
7397
#define ALT_I2C_FS_SPKLEN_OFST 0xa0
7398
7399
#define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
7400
7433
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_LSB 0
7434
7435
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_MSB 0
7436
7437
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_WIDTH 1
7438
7439
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET_MSK 0x00000001
7440
7441
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_CLR_MSK 0xfffffffe
7442
7443
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_RESET 0x0
7444
7445
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_GET(value) (((value) & 0x00000001) >> 0)
7446
7447
#define ALT_I2C_CLR_RESTART_DET_CLR_RESTART_DET_SET(value) (((value) << 0) & 0x00000001)
7448
7449
#ifndef __ASSEMBLY__
7450
7460
struct
ALT_I2C_CLR_RESTART_DET_s
7461
{
7462
const
uint32_t
clr_restart_det
: 1;
7463
uint32_t : 31;
7464
};
7465
7467
typedef
volatile
struct
ALT_I2C_CLR_RESTART_DET_s
ALT_I2C_CLR_RESTART_DET_t
;
7468
#endif
/* __ASSEMBLY__ */
7469
7471
#define ALT_I2C_CLR_RESTART_DET_RESET 0x00000000
7472
7473
#define ALT_I2C_CLR_RESTART_DET_OFST 0xa8
7474
7475
#define ALT_I2C_CLR_RESTART_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RESTART_DET_OFST))
7476
7542
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
7543
7545
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
7546
7547
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
7548
7549
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
7550
7551
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
7552
7553
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
7554
7555
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
7556
7557
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
7558
7559
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
7560
7592
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
7593
7595
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
7596
7597
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
7598
7599
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
7600
7601
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
7602
7603
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
7604
7605
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
7606
7607
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
7608
7609
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
7610
7638
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
7639
7641
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
7642
7643
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
7644
7645
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
7646
7647
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
7648
7649
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
7650
7651
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
7652
7653
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
7654
7655
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
7656
7684
#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
7685
7687
#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
7688
7689
#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
7690
7691
#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
7692
7693
#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
7694
7695
#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
7696
7697
#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
7698
7699
#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
7700
7701
#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
7702
7730
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
7731
7733
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
7734
7735
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
7736
7737
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
7738
7739
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
7740
7741
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
7742
7743
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
7744
7745
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
7746
7747
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
7748
7786
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
7787
7789
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
7790
7791
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
7792
7793
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
7794
7795
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
7796
7797
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
7798
7799
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
7800
7801
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
7802
7803
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
7804
7838
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
7839
7841
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
7842
7843
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
7844
7845
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
7846
7847
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
7848
7849
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
7850
7851
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
7852
7853
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
7854
7855
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
7856
7890
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
7891
7893
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
7894
7895
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
7896
7897
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
7898
7899
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
7900
7901
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
7902
7903
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
7904
7905
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
7906
7907
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
7908
7909
#ifndef __ASSEMBLY__
7910
7920
struct
ALT_I2C_COMP_PARAM_1_s
7921
{
7922
const
uint32_t
apb_data_width
: 2;
7923
const
uint32_t
max_speed_mode
: 2;
7924
const
uint32_t
hc_count_values
: 1;
7925
const
uint32_t
intr_io
: 1;
7926
const
uint32_t
has_dma
: 1;
7927
const
uint32_t
add_encoded_params
: 1;
7928
const
uint32_t
rx_buffer_depth
: 8;
7929
const
uint32_t
tx_buffer_depth
: 8;
7930
uint32_t : 8;
7931
};
7932
7934
typedef
volatile
struct
ALT_I2C_COMP_PARAM_1_s
ALT_I2C_COMP_PARAM_1_t
;
7935
#endif
/* __ASSEMBLY__ */
7936
7938
#define ALT_I2C_COMP_PARAM_1_RESET 0x003f3fea
7939
7940
#define ALT_I2C_COMP_PARAM_1_OFST 0xf4
7941
7942
#define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
7943
7985
#define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_21A 0x3132312a
7986
7988
#define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
7989
7990
#define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
7991
7992
#define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
7993
7994
#define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
7995
7996
#define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
7997
7998
#define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132312a
7999
8000
#define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
8001
8002
#define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
8003
8004
#ifndef __ASSEMBLY__
8005
8015
struct
ALT_I2C_COMP_VER_s
8016
{
8017
const
uint32_t
ic_comp_version
: 32;
8018
};
8019
8021
typedef
volatile
struct
ALT_I2C_COMP_VER_s
ALT_I2C_COMP_VER_t
;
8022
#endif
/* __ASSEMBLY__ */
8023
8025
#define ALT_I2C_COMP_VER_RESET 0x3132312a
8026
8027
#define ALT_I2C_COMP_VER_OFST 0xf8
8028
8029
#define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
8030
8066
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
8067
8068
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
8069
8070
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
8071
8072
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
8073
8074
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
8075
8076
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
8077
8078
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
8079
8080
#define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
8081
8082
#ifndef __ASSEMBLY__
8083
8093
struct
ALT_I2C_COMP_TYPE_s
8094
{
8095
const
uint32_t
ic_comp_type
: 32;
8096
};
8097
8099
typedef
volatile
struct
ALT_I2C_COMP_TYPE_s
ALT_I2C_COMP_TYPE_t
;
8100
#endif
/* __ASSEMBLY__ */
8101
8103
#define ALT_I2C_COMP_TYPE_RESET 0x44570140
8104
8105
#define ALT_I2C_COMP_TYPE_OFST 0xfc
8106
8107
#define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
8108
8109
#ifndef __ASSEMBLY__
8110
8120
struct
ALT_I2C_s
8121
{
8122
volatile
ALT_I2C_CON_t
ic_con
;
8123
volatile
ALT_I2C_TAR_t
ic_tar
;
8124
volatile
ALT_I2C_SAR_t
ic_sar
;
8125
volatile
uint32_t
_pad_0xc_0xf
;
8126
volatile
ALT_I2C_DATA_CMD_t
ic_data_cmd
;
8127
volatile
ALT_I2C_SS_SCL_HCNT_t
ic_ss_scl_hcnt
;
8128
volatile
ALT_I2C_SS_SCL_LCNT_t
ic_ss_scl_lcnt
;
8129
volatile
ALT_I2C_FS_SCL_HCNT_t
ic_fs_scl_hcnt
;
8130
volatile
ALT_I2C_FS_SCL_LCNT_t
ic_fs_scl_lcnt
;
8131
volatile
uint32_t
_pad_0x24_0x2b
[2];
8132
volatile
ALT_I2C_INTR_STAT_t
ic_intr_stat
;
8133
volatile
ALT_I2C_INTR_MSK_t
ic_intr_mask
;
8134
volatile
ALT_I2C_RAW_INTR_STAT_t
ic_raw_intr_stat
;
8135
volatile
ALT_I2C_RX_TL_t
ic_rx_tl
;
8136
volatile
ALT_I2C_TX_TL_t
ic_tx_tl
;
8137
volatile
ALT_I2C_CLR_INTR_t
ic_clr_intr
;
8138
volatile
ALT_I2C_CLR_RX_UNDER_t
ic_clr_rx_under
;
8139
volatile
ALT_I2C_CLR_RX_OVER_t
ic_clr_rx_over
;
8140
volatile
ALT_I2C_CLR_TX_OVER_t
ic_clr_tx_over
;
8141
volatile
ALT_I2C_CLR_RD_REQ_t
ic_clr_rd_req
;
8142
volatile
ALT_I2C_CLR_TX_ABRT_t
ic_clr_tx_abrt
;
8143
volatile
ALT_I2C_CLR_RX_DONE_t
ic_clr_rx_done
;
8144
volatile
ALT_I2C_CLR_ACTIVITY_t
ic_clr_activity
;
8145
volatile
ALT_I2C_CLR_STOP_DET_t
ic_clr_stop_det
;
8146
volatile
ALT_I2C_CLR_START_DET_t
ic_clr_start_det
;
8147
volatile
ALT_I2C_CLR_GEN_CALL_t
ic_clr_gen_call
;
8148
volatile
ALT_I2C_EN_t
ic_enable
;
8149
volatile
ALT_I2C_STAT_t
ic_status
;
8150
volatile
ALT_I2C_TXFLR_t
ic_txflr
;
8151
volatile
ALT_I2C_RXFLR_t
ic_rxflr
;
8152
volatile
ALT_I2C_SDA_HOLD_t
ic_sda_hold
;
8153
volatile
ALT_I2C_TX_ABRT_SRC_t
ic_tx_abrt_source
;
8154
volatile
ALT_I2C_SLV_DATA_NACK_ONLY_t
ic_slv_data_nack_only
;
8155
volatile
ALT_I2C_DMA_CR_t
ic_dma_cr
;
8156
volatile
ALT_I2C_DMA_TDLR_t
ic_dma_tdlr
;
8157
volatile
ALT_I2C_DMA_RDLR_t
ic_dma_rdlr
;
8158
volatile
ALT_I2C_SDA_SETUP_t
ic_sda_setup
;
8159
volatile
ALT_I2C_ACK_GENERAL_CALL_t
ic_ack_general_call
;
8160
volatile
ALT_I2C_EN_STAT_t
ic_enable_status
;
8161
volatile
ALT_I2C_FS_SPKLEN_t
ic_fs_spklen
;
8162
volatile
uint32_t
_pad_0xa4_0xa7
;
8163
volatile
ALT_I2C_CLR_RESTART_DET_t
ic_clr_restart_det
;
8164
volatile
uint32_t
_pad_0xac_0xf3
[18];
8165
volatile
ALT_I2C_COMP_PARAM_1_t
ic_comp_param_1
;
8166
volatile
ALT_I2C_COMP_VER_t
ic_comp_version
;
8167
volatile
ALT_I2C_COMP_TYPE_t
ic_comp_type
;
8168
};
8169
8171
typedef
volatile
struct
ALT_I2C_s
ALT_I2C_t
;
8173
struct
ALT_I2C_raw_s
8174
{
8175
volatile
uint32_t
ic_con
;
8176
volatile
uint32_t
ic_tar
;
8177
volatile
uint32_t
ic_sar
;
8178
volatile
uint32_t
_pad_0xc_0xf
;
8179
volatile
uint32_t
ic_data_cmd
;
8180
volatile
uint32_t
ic_ss_scl_hcnt
;
8181
volatile
uint32_t
ic_ss_scl_lcnt
;
8182
volatile
uint32_t
ic_fs_scl_hcnt
;
8183
volatile
uint32_t
ic_fs_scl_lcnt
;
8184
volatile
uint32_t
_pad_0x24_0x2b
[2];
8185
volatile
uint32_t
ic_intr_stat
;
8186
volatile
uint32_t
ic_intr_mask
;
8187
volatile
uint32_t
ic_raw_intr_stat
;
8188
volatile
uint32_t
ic_rx_tl
;
8189
volatile
uint32_t
ic_tx_tl
;
8190
volatile
uint32_t
ic_clr_intr
;
8191
volatile
uint32_t
ic_clr_rx_under
;
8192
volatile
uint32_t
ic_clr_rx_over
;
8193
volatile
uint32_t
ic_clr_tx_over
;
8194
volatile
uint32_t
ic_clr_rd_req
;
8195
volatile
uint32_t
ic_clr_tx_abrt
;
8196
volatile
uint32_t
ic_clr_rx_done
;
8197
volatile
uint32_t
ic_clr_activity
;
8198
volatile
uint32_t
ic_clr_stop_det
;
8199
volatile
uint32_t
ic_clr_start_det
;
8200
volatile
uint32_t
ic_clr_gen_call
;
8201
volatile
uint32_t
ic_enable
;
8202
volatile
uint32_t
ic_status
;
8203
volatile
uint32_t
ic_txflr
;
8204
volatile
uint32_t
ic_rxflr
;
8205
volatile
uint32_t
ic_sda_hold
;
8206
volatile
uint32_t
ic_tx_abrt_source
;
8207
volatile
uint32_t
ic_slv_data_nack_only
;
8208
volatile
uint32_t
ic_dma_cr
;
8209
volatile
uint32_t
ic_dma_tdlr
;
8210
volatile
uint32_t
ic_dma_rdlr
;
8211
volatile
uint32_t
ic_sda_setup
;
8212
volatile
uint32_t
ic_ack_general_call
;
8213
volatile
uint32_t
ic_enable_status
;
8214
volatile
uint32_t
ic_fs_spklen
;
8215
volatile
uint32_t
_pad_0xa4_0xa7
;
8216
volatile
uint32_t
ic_clr_restart_det
;
8217
volatile
uint32_t
_pad_0xac_0xf3
[18];
8218
volatile
uint32_t
ic_comp_param_1
;
8219
volatile
uint32_t
ic_comp_version
;
8220
volatile
uint32_t
ic_comp_type
;
8221
};
8222
8224
typedef
volatile
struct
ALT_I2C_raw_s
ALT_I2C_raw_t
;
8225
#endif
/* __ASSEMBLY__ */
8226
8228
#ifdef __cplusplus
8229
}
8230
#endif
/* __cplusplus */
8231
#endif
/* __ALT_SOCAL_I2C_H__ */
8232
include
soc_a10
socal
alt_i2c.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2