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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT |
[3:2] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT |
[6:4] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP |
[7] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM |
[9:8] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT |
[11:10] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT |
[14:12] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP |
[15] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM |
[17:16] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT |
[19:18] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT |
[22:20] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP |
[23] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM |
[25:24] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT |
[27:26] | RW | 0x2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT |
[30:28] | RW | 0x4 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP |
[31] | RW | 0x0 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM |
Field : nandecc_wct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_LSB 0 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_MSB 1 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET_MSK 0x00000003 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_CLR_MSK 0xfffffffc |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_GET(value) (((value) & 0x00000003) >> 0) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET(value) (((value) << 0) & 0x00000003) |
Field : nandecc_rct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_LSB 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_MSB 3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET_MSK 0x0000000c |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_CLR_MSK 0xfffffff3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_GET(value) (((value) & 0x0000000c) >> 2) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET(value) (((value) << 2) & 0x0000000c) |
Field : nandecc_kp | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_LSB 4 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_MSB 6 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_WIDTH 3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET_MSK 0x00000070 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_CLR_MSK 0xffffff8f |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_RESET 0x4 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_GET(value) (((value) & 0x00000070) >> 4) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET(value) (((value) << 4) & 0x00000070) |
Field : nandecc_tm | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_LSB 7 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_MSB 7 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_WIDTH 1 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET_MSK 0x00000080 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_CLR_MSK 0xffffff7f |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_RESET 0x0 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET(value) (((value) << 7) & 0x00000080) |
Field : nandwr_wct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_LSB 8 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_MSB 9 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET_MSK 0x00000300 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_CLR_MSK 0xfffffcff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_GET(value) (((value) & 0x00000300) >> 8) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET(value) (((value) << 8) & 0x00000300) |
Field : nandwr_rct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_LSB 10 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_MSB 11 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET_MSK 0x00000c00 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_CLR_MSK 0xfffff3ff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_GET(value) (((value) & 0x00000c00) >> 10) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET(value) (((value) << 10) & 0x00000c00) |
Field : nandwr_kp | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_LSB 12 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_MSB 14 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_WIDTH 3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET_MSK 0x00007000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_CLR_MSK 0xffff8fff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_RESET 0x4 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_GET(value) (((value) & 0x00007000) >> 12) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET(value) (((value) << 12) & 0x00007000) |
Field : nandwr_tm | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_LSB 15 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_MSB 15 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_WIDTH 1 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET_MSK 0x00008000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_CLR_MSK 0xffff7fff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_RESET 0x0 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET(value) (((value) << 15) & 0x00008000) |
Field : nandrd_wct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_LSB 16 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_MSB 17 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET_MSK 0x00030000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_CLR_MSK 0xfffcffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_GET(value) (((value) & 0x00030000) >> 16) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET(value) (((value) << 16) & 0x00030000) |
Field : nandrd_rct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_LSB 18 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_MSB 19 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET_MSK 0x000c0000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_CLR_MSK 0xfff3ffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_GET(value) (((value) & 0x000c0000) >> 18) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET(value) (((value) << 18) & 0x000c0000) |
Field : nandrd_kp | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_LSB 20 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_MSB 22 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_WIDTH 3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET_MSK 0x00700000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_CLR_MSK 0xff8fffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_RESET 0x4 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_GET(value) (((value) & 0x00700000) >> 20) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET(value) (((value) << 20) & 0x00700000) |
Field : nandrd_tm | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_LSB 23 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_MSB 23 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_WIDTH 1 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET_MSK 0x00800000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_CLR_MSK 0xff7fffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_RESET 0x0 |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET(value) (((value) << 23) & 0x00800000) |
Field : sdmmc_wct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_LSB 24 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_MSB 25 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET_MSK 0x03000000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_CLR_MSK 0xfcffffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_GET(value) (((value) & 0x03000000) >> 24) |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET(value) (((value) << 24) & 0x03000000) |
Field : sdmmc_rct | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_LSB 26 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_MSB 27 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_WIDTH 2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET_MSK 0x0c000000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_CLR_MSK 0xf3ffffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_RESET 0x2 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_GET(value) (((value) & 0x0c000000) >> 26) |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET(value) (((value) << 26) & 0x0c000000) |
Field : sdmmc_kp | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_LSB 28 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_MSB 30 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_WIDTH 3 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET_MSK 0x70000000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_CLR_MSK 0x8fffffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_RESET 0x4 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_GET(value) (((value) & 0x70000000) >> 28) |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET(value) (((value) << 28) & 0x70000000) |
Field : sdmmc_tm | |
Field Access Macros: | |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_LSB 31 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_MSB 31 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_WIDTH 1 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET_MSK 0x80000000 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_CLR_MSK 0x7fffffff |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_RESET 0x0 |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_SYSMGR_TSMC_TSEL_2_s |
Macros | |
#define | ALT_SYSMGR_TSMC_TSEL_2_RESET 0x4a4a4a4a |
#define | ALT_SYSMGR_TSMC_TSEL_2_OFST 0x108 |
Typedefs | |
typedef struct ALT_SYSMGR_TSMC_TSEL_2_s | ALT_SYSMGR_TSMC_TSEL_2_t |
struct ALT_SYSMGR_TSMC_TSEL_2_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_TSMC_TSEL_2.
Data Fields | ||
---|---|---|
uint32_t | nandecc_wct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT |
uint32_t | nandecc_rct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT |
uint32_t | nandecc_kp: 3 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP |
uint32_t | nandecc_tm: 1 | ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM |
uint32_t | nandwr_wct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT |
uint32_t | nandwr_rct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT |
uint32_t | nandwr_kp: 3 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP |
uint32_t | nandwr_tm: 1 | ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM |
uint32_t | nandrd_wct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT |
uint32_t | nandrd_rct: 2 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT |
uint32_t | nandrd_kp: 3 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP |
uint32_t | nandrd_tm: 1 | ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM |
uint32_t | sdmmc_wct: 2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT |
uint32_t | sdmmc_rct: 2 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT |
uint32_t | sdmmc_kp: 3 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP |
uint32_t | sdmmc_tm: 1 | ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM |
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET_MSK 0x00000003 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET_MSK 0x0000000c |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_WIDTH 3 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET_MSK 0x00000070 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_CLR_MSK 0xffffff8f |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_RESET 0x4 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_GET | ( | value | ) | (((value) & 0x00000070) >> 4) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET | ( | value | ) | (((value) << 4) & 0x00000070) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_WIDTH 1 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET_MSK 0x00000080 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_RESET 0x0 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET_MSK 0x00000300 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET_MSK 0x00000c00 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_CLR_MSK 0xfffff3ff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_GET | ( | value | ) | (((value) & 0x00000c00) >> 10) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET | ( | value | ) | (((value) << 10) & 0x00000c00) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_WIDTH 3 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET_MSK 0x00007000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_CLR_MSK 0xffff8fff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_RESET 0x4 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_GET | ( | value | ) | (((value) & 0x00007000) >> 12) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET | ( | value | ) | (((value) << 12) & 0x00007000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_WIDTH 1 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET_MSK 0x00008000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_RESET 0x0 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET_MSK 0x00030000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET_MSK 0x000c0000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_CLR_MSK 0xfff3ffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_GET | ( | value | ) | (((value) & 0x000c0000) >> 18) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET | ( | value | ) | (((value) << 18) & 0x000c0000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_WIDTH 3 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET_MSK 0x00700000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_CLR_MSK 0xff8fffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_RESET 0x4 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_GET | ( | value | ) | (((value) & 0x00700000) >> 20) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET | ( | value | ) | (((value) << 20) & 0x00700000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_WIDTH 1 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET_MSK 0x00800000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_RESET 0x0 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET_MSK 0x03000000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_CLR_MSK 0xfcffffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_GET | ( | value | ) | (((value) & 0x03000000) >> 24) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET | ( | value | ) | (((value) << 24) & 0x03000000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_WIDTH 2 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET_MSK 0x0c000000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_CLR_MSK 0xf3ffffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_RESET 0x2 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_GET | ( | value | ) | (((value) & 0x0c000000) >> 26) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET | ( | value | ) | (((value) << 26) & 0x0c000000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_WIDTH 3 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET_MSK 0x70000000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_CLR_MSK 0x8fffffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_RESET 0x4 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_GET | ( | value | ) | (((value) & 0x70000000) >> 28) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET | ( | value | ) | (((value) << 28) & 0x70000000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_WIDTH 1 |
The width in bits of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET_MSK 0x80000000 |
The mask used to set the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_RESET 0x0 |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM field value from a register.
#define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM register field value suitable for setting the register.
#define ALT_SYSMGR_TSMC_TSEL_2_RESET 0x4a4a4a4a |
The reset value of the ALT_SYSMGR_TSMC_TSEL_2 register.
#define ALT_SYSMGR_TSMC_TSEL_2_OFST 0x108 |
The byte offset of the ALT_SYSMGR_TSMC_TSEL_2 register from the beginning of the component.
typedef struct ALT_SYSMGR_TSMC_TSEL_2_s ALT_SYSMGR_TSMC_TSEL_2_t |
The typedef declaration for register ALT_SYSMGR_TSMC_TSEL_2.