Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Boot Info Register - bootinfo

Description

Provides access to boot configuration information.

This is a read only register and a write should return error.

This register gets reset only on a cold reset.

Register Layout

Bits Access Reset Description
[0] R Unknown ALT_SYSMGR_BOOT_FPGA_BSEL_EN
[3:1] ??? Unknown UNDEFINED
[6:4] R Unknown ALT_SYSMGR_BOOT_FPGA_BSEL
[7] ??? Unknown UNDEFINED
[10:8] R Unknown ALT_SYSMGR_BOOT_PIN_BSEL
[11] ??? Unknown UNDEFINED
[14:12] R Unknown ALT_SYSMGR_BOOT_BSEL
[31:15] ??? Unknown UNDEFINED

Field : fpga_bsel_en

Specifies the value of the f2s_bsel_en. f2s_bsel_en is a signal from FPGA.

If 1, boot select value is equal to FPGA boot select signal (f2s_bsel).

If 0, boot select value is equal to the sampled value of HPS BSEL pins.

Value of f2s_bsel_en is overidden to 0x0 if FPGA is not in user mode (fpga_config_complete = 0)

Field Access Macros:

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_LSB   0
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_MSB   0
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_WIDTH   1
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET_MSK   0x00000001
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_RESET   0x0
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : fpga_bsel

The boot select field specifies the boot source. It is read by the Boot ROM code on a cold or warm reset to determine the boot source.

The boot select value is equal to the f2s_bsel signal from the FPGA if the f2s_bsel_en signal from the FPGA is 1 or equal to the sampled value of HPS BSEL pins if the f2s_bsel_en signal from the FPGA is 0 or the FPGA is not powered on or not in User Mode (fpga_config_complete = 0).

The HPS BSEL pins value are sampled upon deassertion of cold reset.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX | 0x0 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA | 0x1 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V | 0x2 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V | 0x3 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V | 0x6 | ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V | 0x7 |

Field Access Macros:

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX   0x0
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA   0x1
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V   0x2
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V   0x3
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V   0x6
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V   0x7
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_LSB   4
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_MSB   6
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_WIDTH   3
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_SET_MSK   0x00000070
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_CLR_MSK   0xffffff8f
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_GET(value)   (((value) & 0x00000070) >> 4)
 
#define ALT_SYSMGR_BOOT_FPGA_BSEL_SET(value)   (((value) << 4) & 0x00000070)
 

Field : pin_bsel

Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are sampled upon deassertion of cold reset.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX | 0x0 | ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA | 0x1 | ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V | 0x2 | ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V | 0x3 | ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V | 0x6 | ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V | 0x7 |

Field Access Macros:

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX   0x0
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA   0x1
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V   0x2
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V   0x3
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V   0x6
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V   0x7
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_LSB   8
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_MSB   10
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_WIDTH   3
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_SET_MSK   0x00000700
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_CLR_MSK   0xfffff8ff
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_GET(value)   (((value) & 0x00000700) >> 8)
 
#define ALT_SYSMGR_BOOT_PIN_BSEL_SET(value)   (((value) << 8) & 0x00000700)
 

Field : bsel

Multiplexed Value of Boot Select from pins and fpga

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_BOOT_BSEL_E_RSVDX | 0x0 | ALT_SYSMGR_BOOT_BSEL_E_FPGA | 0x1 | ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V | 0x2 | ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V | 0x3 | ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V | 0x4 | ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V | 0x5 | ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V | 0x6 | ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V | 0x7 |

Field Access Macros:

#define ALT_SYSMGR_BOOT_BSEL_E_RSVDX   0x0
 
#define ALT_SYSMGR_BOOT_BSEL_E_FPGA   0x1
 
#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V   0x2
 
#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V   0x3
 
#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4
 
#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5
 
#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V   0x6
 
#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V   0x7
 
#define ALT_SYSMGR_BOOT_BSEL_LSB   12
 
#define ALT_SYSMGR_BOOT_BSEL_MSB   14
 
#define ALT_SYSMGR_BOOT_BSEL_WIDTH   3
 
#define ALT_SYSMGR_BOOT_BSEL_SET_MSK   0x00007000
 
#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK   0xffff8fff
 
#define ALT_SYSMGR_BOOT_BSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_BSEL_GET(value)   (((value) & 0x00007000) >> 12)
 
#define ALT_SYSMGR_BOOT_BSEL_SET(value)   (((value) << 12) & 0x00007000)
 

Data Structures

struct  ALT_SYSMGR_BOOT_s
 

Macros

#define ALT_SYSMGR_BOOT_RESET   0x00000000
 
#define ALT_SYSMGR_BOOT_OFST   0xc
 

Typedefs

typedef struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t
 

Data Structure Documentation

struct ALT_SYSMGR_BOOT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_BOOT.

Data Fields
const uint32_t fpga_bsel_en: 1 ALT_SYSMGR_BOOT_FPGA_BSEL_EN
uint32_t __pad0__: 3 UNDEFINED
const uint32_t fpga_bsel: 3 ALT_SYSMGR_BOOT_FPGA_BSEL
uint32_t __pad1__: 1 UNDEFINED
const uint32_t pin_bsel: 3 ALT_SYSMGR_BOOT_PIN_BSEL
uint32_t __pad2__: 1 UNDEFINED
const uint32_t bsel: 3 ALT_SYSMGR_BOOT_BSEL
uint32_t __pad3__: 17 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_WIDTH   1

The width in bits of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_BOOT_FPGA_BSEL_EN field value from a register.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_BOOT_FPGA_BSEL_EN register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX   0x0

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA   0x1

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V   0x2

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V   0x3

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V   0x6

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V   0x7

Enumerated value for register field ALT_SYSMGR_BOOT_FPGA_BSEL

#define ALT_SYSMGR_BOOT_FPGA_BSEL_LSB   4

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_MSB   6

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_FPGA_BSEL register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_BOOT_FPGA_BSEL register field.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_SET_MSK   0x00000070

The mask used to set the ALT_SYSMGR_BOOT_FPGA_BSEL register field value.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_CLR_MSK   0xffffff8f

The mask used to clear the ALT_SYSMGR_BOOT_FPGA_BSEL register field value.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_FPGA_BSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_GET (   value)    (((value) & 0x00000070) >> 4)

Extracts the ALT_SYSMGR_BOOT_FPGA_BSEL field value from a register.

#define ALT_SYSMGR_BOOT_FPGA_BSEL_SET (   value)    (((value) << 4) & 0x00000070)

Produces a ALT_SYSMGR_BOOT_FPGA_BSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX   0x0

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA   0x1

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V   0x2

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V   0x3

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V   0x6

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V   0x7

Enumerated value for register field ALT_SYSMGR_BOOT_PIN_BSEL

#define ALT_SYSMGR_BOOT_PIN_BSEL_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PIN_BSEL register field.

#define ALT_SYSMGR_BOOT_PIN_BSEL_MSB   10

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PIN_BSEL register field.

#define ALT_SYSMGR_BOOT_PIN_BSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_BOOT_PIN_BSEL register field.

#define ALT_SYSMGR_BOOT_PIN_BSEL_SET_MSK   0x00000700

The mask used to set the ALT_SYSMGR_BOOT_PIN_BSEL register field value.

#define ALT_SYSMGR_BOOT_PIN_BSEL_CLR_MSK   0xfffff8ff

The mask used to clear the ALT_SYSMGR_BOOT_PIN_BSEL register field value.

#define ALT_SYSMGR_BOOT_PIN_BSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_PIN_BSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_PIN_BSEL_GET (   value)    (((value) & 0x00000700) >> 8)

Extracts the ALT_SYSMGR_BOOT_PIN_BSEL field value from a register.

#define ALT_SYSMGR_BOOT_PIN_BSEL_SET (   value)    (((value) << 8) & 0x00000700)

Produces a ALT_SYSMGR_BOOT_PIN_BSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_BSEL_E_RSVDX   0x0

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_FPGA   0x1

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V   0x2

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V   0x3

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V   0x6

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V   0x7

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

#define ALT_SYSMGR_BOOT_BSEL_LSB   12

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_MSB   14

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_SET_MSK   0x00007000

The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value.

#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK   0xffff8fff

The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value.

#define ALT_SYSMGR_BOOT_BSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_BSEL_GET (   value)    (((value) & 0x00007000) >> 12)

Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register.

#define ALT_SYSMGR_BOOT_BSEL_SET (   value)    (((value) << 12) & 0x00007000)

Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_RESET   0x00000000

The reset value of the ALT_SYSMGR_BOOT register.

#define ALT_SYSMGR_BOOT_OFST   0xc

The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_BOOT.