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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Device Control IN Endpoint 15 Control Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[10:0] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_MPS |
[14:11] | ??? | 0x0 | UNDEFINED |
[15] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_USBACTEP |
[16] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_DPID |
[17] | R | 0x0 | ALT_USB_DEV_DIEPCTL15_NAKSTS |
[19:18] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_EPTYPE |
[20] | ??? | 0x0 | UNDEFINED |
[21] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_STALL |
[25:22] | RW | 0x0 | ALT_USB_DEV_DIEPCTL15_TXFNUM |
[26] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_CNAK |
[27] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SNAK |
[28] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD0PID |
[29] | W | 0x0 | ALT_USB_DEV_DIEPCTL15_SETD1PID |
[30] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPDIS |
[31] | R-W once | 0x0 | ALT_USB_DEV_DIEPCTL15_EPENA |
Field : mps | |
Maximum Packet Size (MPS) The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes. Field Access Macros: | |
#define | ALT_USB_DEV_DIEPCTL15_MPS_LSB 0 |
#define | ALT_USB_DEV_DIEPCTL15_MPS_MSB 10 |
#define | ALT_USB_DEV_DIEPCTL15_MPS_WIDTH 11 |
#define | ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK 0x000007ff |
#define | ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK 0xfffff800 |
#define | ALT_USB_DEV_DIEPCTL15_MPS_RESET 0x0 |
#define | ALT_USB_DEV_DIEPCTL15_MPS_GET(value) (((value) & 0x000007ff) >> 0) |
#define | ALT_USB_DEV_DIEPCTL15_MPS_SET(value) (((value) << 0) & 0x000007ff) |
Field : usbactep | ||||||||||
USB Active Endpoint (USBActEP) Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB 15 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB 15 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK 0x00008000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK 0xffff7fff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_GET(value) (((value) & 0x00008000) >> 15) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_USBACTEP_SET(value) (((value) << 15) & 0x00008000) | |||||||||
Field : dpid | ||||||||||
Endpoint Data PID (DPID) Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. 1'b0: DATA0 1'b1: DATA1 This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. 1'b0 RO Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather DMA mode: Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro) frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register. 1'b0: Even (micro)frame 1'b1: Odd (micro)frame When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_LSB 16 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_MSB 16 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK 0x00010000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK 0xfffeffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_GET(value) (((value) & 0x00010000) >> 16) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_DPID_SET(value) (((value) << 16) & 0x00010000) | |||||||||
Field : naksts | ||||||||||||||||
NAK Status (NAKSts) Indicates the following: 1'b0: The core is transmitting non-NAK handshakes based on the FIFO status. 1'b1: The core is transmitting NAK handshakes on this endpoint. When either the application or the core sets this bit: The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet. For non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO. For isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK 0x0 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK 0x1 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB 17 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB 17 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH 1 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK 0x00020000 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK 0xfffdffff | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET 0x0 | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_GET(value) (((value) & 0x00020000) >> 17) | |||||||||||||||
#define | ALT_USB_DEV_DIEPCTL15_NAKSTS_SET(value) (((value) << 17) & 0x00020000) | |||||||||||||||
Field : stall | ||||||||||
STALL Handshake (Stall) Applies to non-control, non-isochronous IN and OUT endpoints only. The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. 1'b0 R_W Applies to control endpoints only. The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_LSB 21 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_MSB 21 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK 0x00200000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK 0xffdfffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_GET(value) (((value) & 0x00200000) >> 21) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_STALL_SET(value) (((value) << 21) & 0x00200000) | |||||||||
Field : txfnum | |
TxFIFO Number (TxFNum) Shared FIFO Operation non-periodic endpoints must set this bit to zero. Periodic endpoints must map this to the corresponding Periodic TxFIFO number. 4'h0: Non-Periodic TxFIFO Others: Specified Periodic TxFIFO.number Note: An interrupt IN endpoint can be configured as a non-periodic endpoint for applications such as mass storage. The core treats an IN endpoint as a non- periodic endpoint if the TxFNum field is set to 0. Otherwise, a separate periodic FIFO must be allocated for an interrupt IN endpoint, and the number of this FIFO must be programmed into the TxFNum field. Configuring an interrupt IN endpoint as a non-periodic endpoint saves the extra periodic FIFO area. Dedicated FIFO Operationthese bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints. Field Access Macros: | |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB 22 |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB 25 |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH 4 |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK 0x03c00000 |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK 0xfc3fffff |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET 0x0 |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_GET(value) (((value) & 0x03c00000) >> 22) |
#define | ALT_USB_DEV_DIEPCTL15_TXFNUM_SET(value) (((value) << 22) & 0x03c00000) |
Field : cnak | ||||||||||
Clear NAK (CNAK) A write to this bit clears the NAK bit For the endpoint. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_LSB 26 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_MSB 26 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK 0x04000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK 0xfbffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_GET(value) (((value) & 0x04000000) >> 26) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_CNAK_SET(value) (((value) << 26) & 0x04000000) | |||||||||
Field : snak | ||||||||||
Set NAK (SNAK) A write to this bit sets the NAK bit For the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit For an endpoint after a SETUP packet is received on that endpoint. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_LSB 27 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_MSB 27 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK 0x08000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK 0xf7ffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_GET(value) (((value) & 0x08000000) >> 27) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SNAK_SET(value) (((value) << 27) & 0x08000000) | |||||||||
Field : setd0pid | ||||||||||
Set DATA0 PID (SetD0PID) Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. 1'b0 WO In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB 28 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB 28 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK 0x10000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK 0xefffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_GET(value) (((value) & 0x10000000) >> 28) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD0PID_SET(value) (((value) << 28) & 0x10000000) | |||||||||
Field : setd1pid | ||||||||||
Set DATA1 PID (SetD1PID) Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro)frame. This field is not applicable for Scatter/Gather DMA mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB 29 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB 29 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK 0x20000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK 0xdfffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_GET(value) (((value) & 0x20000000) >> 29) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_SETD1PID_SET(value) (((value) << 29) & 0x20000000) | |||||||||
Field : epdis | ||||||||||
Endpoint Disable (EPDis) Applies to IN and OUT endpoints. The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_LSB 30 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_MSB 30 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK 0x40000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK 0xbfffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_GET(value) (((value) & 0x40000000) >> 30) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPDIS_SET(value) (((value) << 30) & 0x40000000) | |||||||||
Field : epena | ||||||||||
Endpoint Enable (EPEna) Applies to IN and OUT endpoints. When Scatter/Gather DMA mode is enabled, For IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup. For OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup. When Scatter/Gather DMA mode is enabledsuch as for buffer-pointer based DMA mode:
endpoint.
memory to start receiving data from the USB.
endpoint: SETUP Phase Done Endpoint Disabled Transfer Completed Note: For control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT 0x1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_LSB 31 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_MSB 31 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH 1 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK 0x80000000 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK 0x7fffffff | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_RESET 0x0 | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_GET(value) (((value) & 0x80000000) >> 31) | |||||||||
#define | ALT_USB_DEV_DIEPCTL15_EPENA_SET(value) (((value) << 31) & 0x80000000) | |||||||||
Data Structures | |
struct | ALT_USB_DEV_DIEPCTL15_s |
Macros | |
#define | ALT_USB_DEV_DIEPCTL15_RESET 0x00000000 |
#define | ALT_USB_DEV_DIEPCTL15_OFST 0x2e0 |
#define | ALT_USB_DEV_DIEPCTL15_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST)) |
Typedefs | |
typedef struct ALT_USB_DEV_DIEPCTL15_s | ALT_USB_DEV_DIEPCTL15_t |
struct ALT_USB_DEV_DIEPCTL15_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_USB_DEV_DIEPCTL15.
Data Fields | ||
---|---|---|
uint32_t | mps: 11 | ALT_USB_DEV_DIEPCTL15_MPS |
uint32_t | __pad0__: 4 | UNDEFINED |
uint32_t | usbactep: 1 | ALT_USB_DEV_DIEPCTL15_USBACTEP |
const uint32_t | dpid: 1 | ALT_USB_DEV_DIEPCTL15_DPID |
const uint32_t | naksts: 1 | ALT_USB_DEV_DIEPCTL15_NAKSTS |
uint32_t | eptype: 2 | ALT_USB_DEV_DIEPCTL15_EPTYPE |
uint32_t | __pad1__: 1 | UNDEFINED |
uint32_t | stall: 1 | ALT_USB_DEV_DIEPCTL15_STALL |
uint32_t | txfnum: 4 | ALT_USB_DEV_DIEPCTL15_TXFNUM |
uint32_t | cnak: 1 | ALT_USB_DEV_DIEPCTL15_CNAK |
uint32_t | snak: 1 | ALT_USB_DEV_DIEPCTL15_SNAK |
uint32_t | setd0pid: 1 | ALT_USB_DEV_DIEPCTL15_SETD0PID |
uint32_t | setd1pid: 1 | ALT_USB_DEV_DIEPCTL15_SETD1PID |
uint32_t | epdis: 1 | ALT_USB_DEV_DIEPCTL15_EPDIS |
uint32_t | epena: 1 | ALT_USB_DEV_DIEPCTL15_EPENA |
#define ALT_USB_DEV_DIEPCTL15_MPS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field.
#define ALT_USB_DEV_DIEPCTL15_MPS_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_MPS register field.
#define ALT_USB_DEV_DIEPCTL15_MPS_WIDTH 11 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_MPS register field.
#define ALT_USB_DEV_DIEPCTL15_MPS_SET_MSK 0x000007ff |
The mask used to set the ALT_USB_DEV_DIEPCTL15_MPS register field value.
#define ALT_USB_DEV_DIEPCTL15_MPS_CLR_MSK 0xfffff800 |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_MPS register field value.
#define ALT_USB_DEV_DIEPCTL15_MPS_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_MPS register field.
#define ALT_USB_DEV_DIEPCTL15_MPS_GET | ( | value | ) | (((value) & 0x000007ff) >> 0) |
Extracts the ALT_USB_DEV_DIEPCTL15_MPS field value from a register.
#define ALT_USB_DEV_DIEPCTL15_MPS_SET | ( | value | ) | (((value) << 0) & 0x000007ff) |
Produces a ALT_USB_DEV_DIEPCTL15_MPS register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_DISD 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
Not Active
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_E_END 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_USBACTEP
USB Active Endpoint
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET_MSK 0x00008000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_USBACTEP register field value.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_USBACTEP register field.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_USB_DEV_DIEPCTL15_USBACTEP field value from a register.
#define ALT_USB_DEV_DIEPCTL15_USBACTEP_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_USB_DEV_DIEPCTL15_USBACTEP register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_DPID_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
Endpoint Data PID not active
#define ALT_USB_DEV_DIEPCTL15_DPID_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_DPID
Endpoint Data PID active
#define ALT_USB_DEV_DIEPCTL15_DPID_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field.
#define ALT_USB_DEV_DIEPCTL15_DPID_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_DPID register field.
#define ALT_USB_DEV_DIEPCTL15_DPID_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_DPID register field.
#define ALT_USB_DEV_DIEPCTL15_DPID_SET_MSK 0x00010000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_DPID register field value.
#define ALT_USB_DEV_DIEPCTL15_DPID_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_DPID register field value.
#define ALT_USB_DEV_DIEPCTL15_DPID_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_DPID register field.
#define ALT_USB_DEV_DIEPCTL15_DPID_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_USB_DEV_DIEPCTL15_DPID field value from a register.
#define ALT_USB_DEV_DIEPCTL15_DPID_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_USB_DEV_DIEPCTL15_DPID register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NONNAK 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
The core is transmitting non-NAK handshakes based on the FIFO status
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_E_NAK 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_NAKSTS
The core is transmitting NAK handshakes on this endpoint
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET_MSK 0x00020000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_NAKSTS register field value.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_NAKSTS register field.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_USB_DEV_DIEPCTL15_NAKSTS field value from a register.
#define ALT_USB_DEV_DIEPCTL15_NAKSTS_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_USB_DEV_DIEPCTL15_NAKSTS register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_CTL 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
Control
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_ISOCHRONOUS 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
Isochronous
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_BULK 0x2 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
Bulk
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_E_INTERRUP 0x3 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPTYPE
Interrupt
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_WIDTH 2 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET_MSK 0x000c0000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_CLR_MSK 0xfff3ffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPTYPE register field value.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_EPTYPE register field.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_GET | ( | value | ) | (((value) & 0x000c0000) >> 18) |
Extracts the ALT_USB_DEV_DIEPCTL15_EPTYPE field value from a register.
#define ALT_USB_DEV_DIEPCTL15_EPTYPE_SET | ( | value | ) | (((value) << 18) & 0x000c0000) |
Produces a ALT_USB_DEV_DIEPCTL15_EPTYPE register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_STALL_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
STALL All Tokens not active
#define ALT_USB_DEV_DIEPCTL15_STALL_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_STALL
STALL All Tokens active
#define ALT_USB_DEV_DIEPCTL15_STALL_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field.
#define ALT_USB_DEV_DIEPCTL15_STALL_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_STALL register field.
#define ALT_USB_DEV_DIEPCTL15_STALL_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_STALL register field.
#define ALT_USB_DEV_DIEPCTL15_STALL_SET_MSK 0x00200000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_STALL register field value.
#define ALT_USB_DEV_DIEPCTL15_STALL_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_STALL register field value.
#define ALT_USB_DEV_DIEPCTL15_STALL_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_STALL register field.
#define ALT_USB_DEV_DIEPCTL15_STALL_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_USB_DEV_DIEPCTL15_STALL field value from a register.
#define ALT_USB_DEV_DIEPCTL15_STALL_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_USB_DEV_DIEPCTL15_STALL register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_WIDTH 4 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET_MSK 0x03c00000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_CLR_MSK 0xfc3fffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_TXFNUM register field value.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_TXFNUM register field.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_GET | ( | value | ) | (((value) & 0x03c00000) >> 22) |
Extracts the ALT_USB_DEV_DIEPCTL15_TXFNUM field value from a register.
#define ALT_USB_DEV_DIEPCTL15_TXFNUM_SET | ( | value | ) | (((value) << 22) & 0x03c00000) |
Produces a ALT_USB_DEV_DIEPCTL15_TXFNUM register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
No Clear NAK
#define ALT_USB_DEV_DIEPCTL15_CNAK_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_CNAK
Clear NAK
#define ALT_USB_DEV_DIEPCTL15_CNAK_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field.
#define ALT_USB_DEV_DIEPCTL15_CNAK_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_CNAK register field.
#define ALT_USB_DEV_DIEPCTL15_CNAK_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_CNAK register field.
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET_MSK 0x04000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_CNAK register field value.
#define ALT_USB_DEV_DIEPCTL15_CNAK_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_CNAK register field value.
#define ALT_USB_DEV_DIEPCTL15_CNAK_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_CNAK register field.
#define ALT_USB_DEV_DIEPCTL15_CNAK_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_USB_DEV_DIEPCTL15_CNAK field value from a register.
#define ALT_USB_DEV_DIEPCTL15_CNAK_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_USB_DEV_DIEPCTL15_CNAK register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
No Set NAK
#define ALT_USB_DEV_DIEPCTL15_SNAK_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SNAK
Set NAK
#define ALT_USB_DEV_DIEPCTL15_SNAK_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field.
#define ALT_USB_DEV_DIEPCTL15_SNAK_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SNAK register field.
#define ALT_USB_DEV_DIEPCTL15_SNAK_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_SNAK register field.
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET_MSK 0x08000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_SNAK register field value.
#define ALT_USB_DEV_DIEPCTL15_SNAK_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_SNAK register field value.
#define ALT_USB_DEV_DIEPCTL15_SNAK_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_SNAK register field.
#define ALT_USB_DEV_DIEPCTL15_SNAK_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_USB_DEV_DIEPCTL15_SNAK field value from a register.
#define ALT_USB_DEV_DIEPCTL15_SNAK_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_USB_DEV_DIEPCTL15_SNAK register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_DISD 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
Disables Set DATA0 PID
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_E_END 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD0PID
Endpoint Data PID to DATA0)
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET_MSK 0x10000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_CLR_MSK 0xefffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD0PID register field value.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_SETD0PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_USB_DEV_DIEPCTL15_SETD0PID field value from a register.
#define ALT_USB_DEV_DIEPCTL15_SETD0PID_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_USB_DEV_DIEPCTL15_SETD0PID register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_DISD 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
Disables Set DATA1 PID
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_E_END 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_SETD1PID
Enables Set DATA1 PID
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET_MSK 0x20000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_CLR_MSK 0xdfffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_SETD1PID register field value.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_SETD1PID register field.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_GET | ( | value | ) | (((value) & 0x20000000) >> 29) |
Extracts the ALT_USB_DEV_DIEPCTL15_SETD1PID field value from a register.
#define ALT_USB_DEV_DIEPCTL15_SETD1PID_SET | ( | value | ) | (((value) << 29) & 0x20000000) |
Produces a ALT_USB_DEV_DIEPCTL15_SETD1PID register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
No Endpoint Disable
#define ALT_USB_DEV_DIEPCTL15_EPDIS_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPDIS
Endpoint Disable
#define ALT_USB_DEV_DIEPCTL15_EPDIS_LSB 30 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPDIS register field.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_EPDIS register field.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET_MSK 0x40000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_EPDIS register field value.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_CLR_MSK 0xbfffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPDIS register field value.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_EPDIS register field.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_GET | ( | value | ) | (((value) & 0x40000000) >> 30) |
Extracts the ALT_USB_DEV_DIEPCTL15_EPDIS field value from a register.
#define ALT_USB_DEV_DIEPCTL15_EPDIS_SET | ( | value | ) | (((value) << 30) & 0x40000000) |
Produces a ALT_USB_DEV_DIEPCTL15_EPDIS register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_INACT 0x0 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
Endpoint Enable inactive
#define ALT_USB_DEV_DIEPCTL15_EPENA_E_ACT 0x1 |
Enumerated value for register field ALT_USB_DEV_DIEPCTL15_EPENA
Endpoint Enable active
#define ALT_USB_DEV_DIEPCTL15_EPENA_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field.
#define ALT_USB_DEV_DIEPCTL15_EPENA_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL15_EPENA register field.
#define ALT_USB_DEV_DIEPCTL15_EPENA_WIDTH 1 |
The width in bits of the ALT_USB_DEV_DIEPCTL15_EPENA register field.
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET_MSK 0x80000000 |
The mask used to set the ALT_USB_DEV_DIEPCTL15_EPENA register field value.
#define ALT_USB_DEV_DIEPCTL15_EPENA_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_USB_DEV_DIEPCTL15_EPENA register field value.
#define ALT_USB_DEV_DIEPCTL15_EPENA_RESET 0x0 |
The reset value of the ALT_USB_DEV_DIEPCTL15_EPENA register field.
#define ALT_USB_DEV_DIEPCTL15_EPENA_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_USB_DEV_DIEPCTL15_EPENA field value from a register.
#define ALT_USB_DEV_DIEPCTL15_EPENA_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_USB_DEV_DIEPCTL15_EPENA register field value suitable for setting the register.
#define ALT_USB_DEV_DIEPCTL15_RESET 0x00000000 |
The reset value of the ALT_USB_DEV_DIEPCTL15 register.
#define ALT_USB_DEV_DIEPCTL15_OFST 0x2e0 |
The byte offset of the ALT_USB_DEV_DIEPCTL15 register from the beginning of the component.
#define ALT_USB_DEV_DIEPCTL15_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL15_OFST)) |
The address of the ALT_USB_DEV_DIEPCTL15 register.
typedef struct ALT_USB_DEV_DIEPCTL15_s ALT_USB_DEV_DIEPCTL15_t |
The typedef declaration for register ALT_USB_DEV_DIEPCTL15.