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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock dividers for debug clocks derived from the Main PLL
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x0 | Debug AT Clock Divider |
[3:2] | RW | 0x1 | Debug Clock Divider |
[31:4] | ??? | 0x0 | UNDEFINED |
Field : Debug Clock Divider - dbgclk | ||||||||||
The dbg_clk is divided down from the dbg_at_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET(value) (((value) & 0x0000000c) >> 2) | |||||||||
#define | ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET(value) (((value) << 2) & 0x0000000c) | |||||||||
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_DBGDIV_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_DBGDIV_s | ALT_CLKMGR_MAINPLL_DBGDIV_t |
struct ALT_CLKMGR_MAINPLL_DBGDIV_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_DBGDIV.
Data Fields | ||
---|---|---|
uint32_t | dbgatclk: 2 | Debug AT Clock Divider |
uint32_t | dbgclk: 2 | Debug Clock Divider |
uint32_t | __pad0__: 28 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
Divide by 1
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
Divide by 2
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK
Divide by 4
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET_MSK 0x00000003 |
The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGATCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
Divide by 2
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK
Divide by 4
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET_MSK 0x0000000c |
The mask used to set the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_CLKMGR_MAINPLL_DBGDIV_DBGCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_DBGDIV_OFST 0x28 |
The byte offset of the ALT_CLKMGR_MAINPLL_DBGDIV register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_DBGDIV_s ALT_CLKMGR_MAINPLL_DBGDIV_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_DBGDIV.