Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
Main Page
Address Space
Data Structures
Files
File List
All
Data Structures
Variables
Typedefs
Groups
alt_ecc_nandw.h
1
/***********************************************************************************
2
* *
3
* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4
* *
5
* Redistribution and use in source and binary forms, with or without *
6
* modification, are permitted provided that the following conditions are met: *
7
* *
8
* 1. Redistributions of source code must retain the above copyright notice, *
9
* this list of conditions and the following disclaimer. *
10
* *
11
* 2. Redistributions in binary form must reproduce the above copyright notice, *
12
* this list of conditions and the following disclaimer in the documentation *
13
* and/or other materials provided with the distribution. *
14
* *
15
* 3. Neither the name of the copyright holder nor the names of its contributors *
16
* may be used to endorse or promote products derived from this software without *
17
* specific prior written permission. *
18
* *
19
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29
* POSSIBILITY OF SUCH DAMAGE. *
30
* *
31
***********************************************************************************/
32
35
#ifndef __ALT_SOCAL_ECC_NANDW_H__
36
#define __ALT_SOCAL_ECC_NANDW_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
43
#else
/* __cplusplus */
44
#include <stdint.h>
45
#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
47
74
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_LSB 0
75
76
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_MSB 15
77
78
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_WIDTH 16
79
80
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81
82
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83
84
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_RESET 0x0
85
86
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87
88
#define ALT_ECC_NANDW_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89
90
#ifndef __ASSEMBLY__
91
101
struct
ALT_ECC_NANDW_IP_REV_ID_s
102
{
103
const
uint32_t
SIREV
: 16;
104
uint32_t : 16;
105
};
106
108
typedef
volatile
struct
ALT_ECC_NANDW_IP_REV_ID_s
ALT_ECC_NANDW_IP_REV_ID_t
;
109
#endif
/* __ASSEMBLY__ */
110
112
#define ALT_ECC_NANDW_IP_REV_ID_RESET 0x00000000
113
114
#define ALT_ECC_NANDW_IP_REV_ID_OFST 0x0
115
142
#define ALT_ECC_NANDW_CTL_ECC_EN_LSB 0
143
144
#define ALT_ECC_NANDW_CTL_ECC_EN_MSB 0
145
146
#define ALT_ECC_NANDW_CTL_ECC_EN_WIDTH 1
147
148
#define ALT_ECC_NANDW_CTL_ECC_EN_SET_MSK 0x00000001
149
150
#define ALT_ECC_NANDW_CTL_ECC_EN_CLR_MSK 0xfffffffe
151
152
#define ALT_ECC_NANDW_CTL_ECC_EN_RESET 0x0
153
154
#define ALT_ECC_NANDW_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
155
156
#define ALT_ECC_NANDW_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
157
167
#define ALT_ECC_NANDW_CTL_CNT_RSTA_LSB 8
168
169
#define ALT_ECC_NANDW_CTL_CNT_RSTA_MSB 8
170
171
#define ALT_ECC_NANDW_CTL_CNT_RSTA_WIDTH 1
172
173
#define ALT_ECC_NANDW_CTL_CNT_RSTA_SET_MSK 0x00000100
174
175
#define ALT_ECC_NANDW_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
176
177
#define ALT_ECC_NANDW_CTL_CNT_RSTA_RESET 0x0
178
179
#define ALT_ECC_NANDW_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
180
181
#define ALT_ECC_NANDW_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
182
192
#define ALT_ECC_NANDW_CTL_INITA_LSB 16
193
194
#define ALT_ECC_NANDW_CTL_INITA_MSB 16
195
196
#define ALT_ECC_NANDW_CTL_INITA_WIDTH 1
197
198
#define ALT_ECC_NANDW_CTL_INITA_SET_MSK 0x00010000
199
200
#define ALT_ECC_NANDW_CTL_INITA_CLR_MSK 0xfffeffff
201
202
#define ALT_ECC_NANDW_CTL_INITA_RESET 0x0
203
204
#define ALT_ECC_NANDW_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
205
206
#define ALT_ECC_NANDW_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
207
208
#ifndef __ASSEMBLY__
209
219
struct
ALT_ECC_NANDW_CTL_s
220
{
221
uint32_t
ECC_EN
: 1;
222
uint32_t : 7;
223
uint32_t
CNT_RSTA
: 1;
224
uint32_t : 7;
225
uint32_t
INITA
: 1;
226
uint32_t : 15;
227
};
228
230
typedef
volatile
struct
ALT_ECC_NANDW_CTL_s
ALT_ECC_NANDW_CTL_t
;
231
#endif
/* __ASSEMBLY__ */
232
234
#define ALT_ECC_NANDW_CTL_RESET 0x00000000
235
236
#define ALT_ECC_NANDW_CTL_OFST 0x8
237
261
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_LSB 0
262
263
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_MSB 0
264
265
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_WIDTH 1
266
267
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
268
269
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
270
271
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_RESET 0x0
272
273
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
274
275
#define ALT_ECC_NANDW_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
276
277
#ifndef __ASSEMBLY__
278
288
struct
ALT_ECC_NANDW_INITSTAT_s
289
{
290
uint32_t
INITCOMPLETEA
: 1;
291
uint32_t : 31;
292
};
293
295
typedef
volatile
struct
ALT_ECC_NANDW_INITSTAT_s
ALT_ECC_NANDW_INITSTAT_t
;
296
#endif
/* __ASSEMBLY__ */
297
299
#define ALT_ECC_NANDW_INITSTAT_RESET 0x00000000
300
301
#define ALT_ECC_NANDW_INITSTAT_OFST 0xc
302
325
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_LSB 0
326
327
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_MSB 0
328
329
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_WIDTH 1
330
331
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
332
333
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
334
335
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_RESET 0x0
336
337
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
338
339
#define ALT_ECC_NANDW_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
340
341
#ifndef __ASSEMBLY__
342
352
struct
ALT_ECC_NANDW_ERRINTEN_s
353
{
354
uint32_t
SERRINTEN
: 1;
355
uint32_t : 31;
356
};
357
359
typedef
volatile
struct
ALT_ECC_NANDW_ERRINTEN_s
ALT_ECC_NANDW_ERRINTEN_t
;
360
#endif
/* __ASSEMBLY__ */
361
363
#define ALT_ECC_NANDW_ERRINTEN_RESET 0x00000000
364
365
#define ALT_ECC_NANDW_ERRINTEN_OFST 0x10
366
389
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_LSB 0
390
391
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_MSB 0
392
393
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_WIDTH 1
394
395
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_SET_MSK 0x00000001
396
397
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
398
399
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_RESET 0x0
400
401
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
402
403
#define ALT_ECC_NANDW_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
404
405
#ifndef __ASSEMBLY__
406
416
struct
ALT_ECC_NANDW_ERRINTENS_s
417
{
418
uint32_t
SERRINTS
: 1;
419
uint32_t : 31;
420
};
421
423
typedef
volatile
struct
ALT_ECC_NANDW_ERRINTENS_s
ALT_ECC_NANDW_ERRINTENS_t
;
424
#endif
/* __ASSEMBLY__ */
425
427
#define ALT_ECC_NANDW_ERRINTENS_RESET 0x00000000
428
429
#define ALT_ECC_NANDW_ERRINTENS_OFST 0x14
430
460
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_LSB 0
461
462
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_MSB 0
463
464
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_WIDTH 1
465
466
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_SET_MSK 0x00000001
467
468
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
469
470
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_RESET 0x0
471
472
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
473
474
#define ALT_ECC_NANDW_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
475
476
#ifndef __ASSEMBLY__
477
487
struct
ALT_ECC_NANDW_ERRINTENR_s
488
{
489
uint32_t
SERRINTR
: 1;
490
uint32_t : 31;
491
};
492
494
typedef
volatile
struct
ALT_ECC_NANDW_ERRINTENR_s
ALT_ECC_NANDW_ERRINTENR_t
;
495
#endif
/* __ASSEMBLY__ */
496
498
#define ALT_ECC_NANDW_ERRINTENR_RESET 0x00000000
499
500
#define ALT_ECC_NANDW_ERRINTENR_OFST 0x18
501
528
#define ALT_ECC_NANDW_INTMOD_INTMOD_LSB 0
529
530
#define ALT_ECC_NANDW_INTMOD_INTMOD_MSB 0
531
532
#define ALT_ECC_NANDW_INTMOD_INTMOD_WIDTH 1
533
534
#define ALT_ECC_NANDW_INTMOD_INTMOD_SET_MSK 0x00000001
535
536
#define ALT_ECC_NANDW_INTMOD_INTMOD_CLR_MSK 0xfffffffe
537
538
#define ALT_ECC_NANDW_INTMOD_INTMOD_RESET 0x0
539
540
#define ALT_ECC_NANDW_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
541
542
#define ALT_ECC_NANDW_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
543
553
#define ALT_ECC_NANDW_INTMOD_INTONOVF_LSB 8
554
555
#define ALT_ECC_NANDW_INTMOD_INTONOVF_MSB 8
556
557
#define ALT_ECC_NANDW_INTMOD_INTONOVF_WIDTH 1
558
559
#define ALT_ECC_NANDW_INTMOD_INTONOVF_SET_MSK 0x00000100
560
561
#define ALT_ECC_NANDW_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
562
563
#define ALT_ECC_NANDW_INTMOD_INTONOVF_RESET 0x0
564
565
#define ALT_ECC_NANDW_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
566
567
#define ALT_ECC_NANDW_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
568
578
#define ALT_ECC_NANDW_INTMOD_INTONCMP_LSB 16
579
580
#define ALT_ECC_NANDW_INTMOD_INTONCMP_MSB 16
581
582
#define ALT_ECC_NANDW_INTMOD_INTONCMP_WIDTH 1
583
584
#define ALT_ECC_NANDW_INTMOD_INTONCMP_SET_MSK 0x00010000
585
586
#define ALT_ECC_NANDW_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
587
588
#define ALT_ECC_NANDW_INTMOD_INTONCMP_RESET 0x0
589
590
#define ALT_ECC_NANDW_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
591
592
#define ALT_ECC_NANDW_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
593
594
#ifndef __ASSEMBLY__
595
605
struct
ALT_ECC_NANDW_INTMOD_s
606
{
607
uint32_t
INTMODE
: 1;
608
uint32_t : 7;
609
uint32_t
INTONOVF
: 1;
610
uint32_t : 7;
611
uint32_t
INTONCMP
: 1;
612
uint32_t : 15;
613
};
614
616
typedef
volatile
struct
ALT_ECC_NANDW_INTMOD_s
ALT_ECC_NANDW_INTMOD_t
;
617
#endif
/* __ASSEMBLY__ */
618
620
#define ALT_ECC_NANDW_INTMOD_RESET 0x00000000
621
622
#define ALT_ECC_NANDW_INTMOD_OFST 0x1c
623
650
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_LSB 0
651
652
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_MSB 0
653
654
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_WIDTH 1
655
656
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_SET_MSK 0x00000001
657
658
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
659
660
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_RESET 0x0
661
662
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
663
664
#define ALT_ECC_NANDW_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
665
675
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_LSB 8
676
677
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_MSB 8
678
679
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_WIDTH 1
680
681
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_SET_MSK 0x00000100
682
683
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
684
685
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_RESET 0x0
686
687
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
688
689
#define ALT_ECC_NANDW_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
690
691
#ifndef __ASSEMBLY__
692
702
struct
ALT_ECC_NANDW_INTSTAT_s
703
{
704
uint32_t
SERRPENA
: 1;
705
uint32_t : 7;
706
uint32_t
DERRPENA
: 1;
707
uint32_t : 23;
708
};
709
711
typedef
volatile
struct
ALT_ECC_NANDW_INTSTAT_s
ALT_ECC_NANDW_INTSTAT_t
;
712
#endif
/* __ASSEMBLY__ */
713
715
#define ALT_ECC_NANDW_INTSTAT_RESET 0x00000000
716
717
#define ALT_ECC_NANDW_INTSTAT_OFST 0x20
718
743
#define ALT_ECC_NANDW_INTTEST_TSERRA_LSB 0
744
745
#define ALT_ECC_NANDW_INTTEST_TSERRA_MSB 0
746
747
#define ALT_ECC_NANDW_INTTEST_TSERRA_WIDTH 1
748
749
#define ALT_ECC_NANDW_INTTEST_TSERRA_SET_MSK 0x00000001
750
751
#define ALT_ECC_NANDW_INTTEST_TSERRA_CLR_MSK 0xfffffffe
752
753
#define ALT_ECC_NANDW_INTTEST_TSERRA_RESET 0x0
754
755
#define ALT_ECC_NANDW_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
756
757
#define ALT_ECC_NANDW_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
758
768
#define ALT_ECC_NANDW_INTTEST_TDERRA_LSB 8
769
770
#define ALT_ECC_NANDW_INTTEST_TDERRA_MSB 8
771
772
#define ALT_ECC_NANDW_INTTEST_TDERRA_WIDTH 1
773
774
#define ALT_ECC_NANDW_INTTEST_TDERRA_SET_MSK 0x00000100
775
776
#define ALT_ECC_NANDW_INTTEST_TDERRA_CLR_MSK 0xfffffeff
777
778
#define ALT_ECC_NANDW_INTTEST_TDERRA_RESET 0x0
779
780
#define ALT_ECC_NANDW_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
781
782
#define ALT_ECC_NANDW_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
783
784
#ifndef __ASSEMBLY__
785
795
struct
ALT_ECC_NANDW_INTTEST_s
796
{
797
uint32_t
TSERRA
: 1;
798
uint32_t : 7;
799
uint32_t
TDERRA
: 1;
800
uint32_t : 23;
801
};
802
804
typedef
volatile
struct
ALT_ECC_NANDW_INTTEST_s
ALT_ECC_NANDW_INTTEST_t
;
805
#endif
/* __ASSEMBLY__ */
806
808
#define ALT_ECC_NANDW_INTTEST_RESET 0x00000000
809
810
#define ALT_ECC_NANDW_INTTEST_OFST 0x24
811
834
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_LSB 0
835
836
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_MSB 0
837
838
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_WIDTH 1
839
840
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_SET_MSK 0x00000001
841
842
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
843
844
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_RESET 0x0
845
846
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
847
848
#define ALT_ECC_NANDW_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
849
850
#ifndef __ASSEMBLY__
851
861
struct
ALT_ECC_NANDW_MODSTAT_s
862
{
863
uint32_t
CMPFLGA
: 1;
864
uint32_t : 31;
865
};
866
868
typedef
volatile
struct
ALT_ECC_NANDW_MODSTAT_s
ALT_ECC_NANDW_MODSTAT_t
;
869
#endif
/* __ASSEMBLY__ */
870
872
#define ALT_ECC_NANDW_MODSTAT_RESET 0x00000000
873
874
#define ALT_ECC_NANDW_MODSTAT_OFST 0x28
875
899
#define ALT_ECC_NANDW_DERRADDRA_ADDR_LSB 0
900
901
#define ALT_ECC_NANDW_DERRADDRA_ADDR_MSB 6
902
903
#define ALT_ECC_NANDW_DERRADDRA_ADDR_WIDTH 7
904
905
#define ALT_ECC_NANDW_DERRADDRA_ADDR_SET_MSK 0x0000007f
906
907
#define ALT_ECC_NANDW_DERRADDRA_ADDR_CLR_MSK 0xffffff80
908
909
#define ALT_ECC_NANDW_DERRADDRA_ADDR_RESET 0x0
910
911
#define ALT_ECC_NANDW_DERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
912
913
#define ALT_ECC_NANDW_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
914
915
#ifndef __ASSEMBLY__
916
926
struct
ALT_ECC_NANDW_DERRADDRA_s
927
{
928
uint32_t
Address
: 7;
929
uint32_t : 25;
930
};
931
933
typedef
volatile
struct
ALT_ECC_NANDW_DERRADDRA_s
ALT_ECC_NANDW_DERRADDRA_t
;
934
#endif
/* __ASSEMBLY__ */
935
937
#define ALT_ECC_NANDW_DERRADDRA_RESET 0x00000000
938
939
#define ALT_ECC_NANDW_DERRADDRA_OFST 0x2c
940
964
#define ALT_ECC_NANDW_SERRADDRA_ADDR_LSB 0
965
966
#define ALT_ECC_NANDW_SERRADDRA_ADDR_MSB 6
967
968
#define ALT_ECC_NANDW_SERRADDRA_ADDR_WIDTH 7
969
970
#define ALT_ECC_NANDW_SERRADDRA_ADDR_SET_MSK 0x0000007f
971
972
#define ALT_ECC_NANDW_SERRADDRA_ADDR_CLR_MSK 0xffffff80
973
974
#define ALT_ECC_NANDW_SERRADDRA_ADDR_RESET 0x0
975
976
#define ALT_ECC_NANDW_SERRADDRA_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
977
978
#define ALT_ECC_NANDW_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x0000007f)
979
980
#ifndef __ASSEMBLY__
981
991
struct
ALT_ECC_NANDW_SERRADDRA_s
992
{
993
uint32_t
Address
: 7;
994
uint32_t : 25;
995
};
996
998
typedef
volatile
struct
ALT_ECC_NANDW_SERRADDRA_s
ALT_ECC_NANDW_SERRADDRA_t
;
999
#endif
/* __ASSEMBLY__ */
1000
1002
#define ALT_ECC_NANDW_SERRADDRA_RESET 0x00000000
1003
1004
#define ALT_ECC_NANDW_SERRADDRA_OFST 0x30
1005
1027
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_LSB 0
1028
1029
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_MSB 31
1030
1031
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_WIDTH 32
1032
1033
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1034
1035
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1036
1037
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_RESET 0x0
1038
1039
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1040
1041
#define ALT_ECC_NANDW_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1042
1043
#ifndef __ASSEMBLY__
1044
1054
struct
ALT_ECC_NANDW_SERRCNTREG_s
1055
{
1056
uint32_t
SERRCNT
: 32;
1057
};
1058
1060
typedef
volatile
struct
ALT_ECC_NANDW_SERRCNTREG_s
ALT_ECC_NANDW_SERRCNTREG_t
;
1061
#endif
/* __ASSEMBLY__ */
1062
1064
#define ALT_ECC_NANDW_SERRCNTREG_RESET 0x00000000
1065
1066
#define ALT_ECC_NANDW_SERRCNTREG_OFST 0x3c
1067
1091
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_LSB 0
1092
1093
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_MSB 6
1094
1095
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_WIDTH 7
1096
1097
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x0000007f
1098
1099
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffffff80
1100
1101
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1102
1103
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x0000007f) >> 0)
1104
1105
#define ALT_ECC_NANDW_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x0000007f)
1106
1107
#ifndef __ASSEMBLY__
1108
1118
struct
ALT_ECC_NANDW_ADDRBUS_s
1119
{
1120
uint32_t
ECC_AddrBUS
: 7;
1121
uint32_t : 25;
1122
};
1123
1125
typedef
volatile
struct
ALT_ECC_NANDW_ADDRBUS_s
ALT_ECC_NANDW_ADDRBUS_t
;
1126
#endif
/* __ASSEMBLY__ */
1127
1129
#define ALT_ECC_NANDW_ADDRBUS_RESET 0x00000000
1130
1131
#define ALT_ECC_NANDW_ADDRBUS_OFST 0x40
1132
1133
#define ALT_ECC_NANDW_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_ADDRBUS_OFST))
1134
1156
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_LSB 0
1157
1158
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_MSB 31
1159
1160
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1161
1162
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1163
1164
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1165
1166
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1167
1168
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1169
1170
#define ALT_ECC_NANDW_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1171
1172
#ifndef __ASSEMBLY__
1173
1183
struct
ALT_ECC_NANDW_RDATA0BUS_s
1184
{
1185
uint32_t
ECC_RDataBUS
: 32;
1186
};
1187
1189
typedef
volatile
struct
ALT_ECC_NANDW_RDATA0BUS_s
ALT_ECC_NANDW_RDATA0BUS_t
;
1190
#endif
/* __ASSEMBLY__ */
1191
1193
#define ALT_ECC_NANDW_RDATA0BUS_RESET 0x00000000
1194
1195
#define ALT_ECC_NANDW_RDATA0BUS_OFST 0x44
1196
1197
#define ALT_ECC_NANDW_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA0BUS_OFST))
1198
1220
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_LSB 0
1221
1222
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_MSB 31
1223
1224
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1225
1226
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1227
1228
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1229
1230
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1231
1232
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1233
1234
#define ALT_ECC_NANDW_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1235
1236
#ifndef __ASSEMBLY__
1237
1247
struct
ALT_ECC_NANDW_RDATA1BUS_s
1248
{
1249
uint32_t
ECC_RDataBUS
: 32;
1250
};
1251
1253
typedef
volatile
struct
ALT_ECC_NANDW_RDATA1BUS_s
ALT_ECC_NANDW_RDATA1BUS_t
;
1254
#endif
/* __ASSEMBLY__ */
1255
1257
#define ALT_ECC_NANDW_RDATA1BUS_RESET 0x00000000
1258
1259
#define ALT_ECC_NANDW_RDATA1BUS_OFST 0x48
1260
1261
#define ALT_ECC_NANDW_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA1BUS_OFST))
1262
1284
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_LSB 0
1285
1286
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_MSB 31
1287
1288
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1289
1290
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1291
1292
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1293
1294
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1295
1296
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1297
1298
#define ALT_ECC_NANDW_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1299
1300
#ifndef __ASSEMBLY__
1301
1311
struct
ALT_ECC_NANDW_RDATA2BUS_s
1312
{
1313
uint32_t
ECC_RDataBUS
: 32;
1314
};
1315
1317
typedef
volatile
struct
ALT_ECC_NANDW_RDATA2BUS_s
ALT_ECC_NANDW_RDATA2BUS_t
;
1318
#endif
/* __ASSEMBLY__ */
1319
1321
#define ALT_ECC_NANDW_RDATA2BUS_RESET 0x00000000
1322
1323
#define ALT_ECC_NANDW_RDATA2BUS_OFST 0x4c
1324
1325
#define ALT_ECC_NANDW_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA2BUS_OFST))
1326
1348
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_LSB 0
1349
1350
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_MSB 31
1351
1352
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1353
1354
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1355
1356
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1357
1358
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1359
1360
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1361
1362
#define ALT_ECC_NANDW_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1363
1364
#ifndef __ASSEMBLY__
1365
1375
struct
ALT_ECC_NANDW_RDATA3BUS_s
1376
{
1377
uint32_t
ECC_RDataBUS
: 32;
1378
};
1379
1381
typedef
volatile
struct
ALT_ECC_NANDW_RDATA3BUS_s
ALT_ECC_NANDW_RDATA3BUS_t
;
1382
#endif
/* __ASSEMBLY__ */
1383
1385
#define ALT_ECC_NANDW_RDATA3BUS_RESET 0x00000000
1386
1387
#define ALT_ECC_NANDW_RDATA3BUS_OFST 0x50
1388
1389
#define ALT_ECC_NANDW_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATA3BUS_OFST))
1390
1412
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_LSB 0
1413
1414
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_MSB 31
1415
1416
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1417
1418
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1419
1420
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1421
1422
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1423
1424
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1425
1426
#define ALT_ECC_NANDW_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1427
1428
#ifndef __ASSEMBLY__
1429
1439
struct
ALT_ECC_NANDW_WDATA0BUS_s
1440
{
1441
uint32_t
ECC_WDataBUS
: 32;
1442
};
1443
1445
typedef
volatile
struct
ALT_ECC_NANDW_WDATA0BUS_s
ALT_ECC_NANDW_WDATA0BUS_t
;
1446
#endif
/* __ASSEMBLY__ */
1447
1449
#define ALT_ECC_NANDW_WDATA0BUS_RESET 0x00000000
1450
1451
#define ALT_ECC_NANDW_WDATA0BUS_OFST 0x54
1452
1453
#define ALT_ECC_NANDW_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA0BUS_OFST))
1454
1476
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_LSB 0
1477
1478
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_MSB 31
1479
1480
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1481
1482
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1483
1484
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1485
1486
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1487
1488
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1489
1490
#define ALT_ECC_NANDW_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1491
1492
#ifndef __ASSEMBLY__
1493
1503
struct
ALT_ECC_NANDW_WDATA1BUS_s
1504
{
1505
uint32_t
ECC_WDataBUS
: 32;
1506
};
1507
1509
typedef
volatile
struct
ALT_ECC_NANDW_WDATA1BUS_s
ALT_ECC_NANDW_WDATA1BUS_t
;
1510
#endif
/* __ASSEMBLY__ */
1511
1513
#define ALT_ECC_NANDW_WDATA1BUS_RESET 0x00000000
1514
1515
#define ALT_ECC_NANDW_WDATA1BUS_OFST 0x58
1516
1517
#define ALT_ECC_NANDW_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA1BUS_OFST))
1518
1540
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_LSB 0
1541
1542
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_MSB 31
1543
1544
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1545
1546
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1547
1548
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1549
1550
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1551
1552
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1553
1554
#define ALT_ECC_NANDW_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1555
1556
#ifndef __ASSEMBLY__
1557
1567
struct
ALT_ECC_NANDW_WDATA2BUS_s
1568
{
1569
uint32_t
ECC_WDataBUS
: 32;
1570
};
1571
1573
typedef
volatile
struct
ALT_ECC_NANDW_WDATA2BUS_s
ALT_ECC_NANDW_WDATA2BUS_t
;
1574
#endif
/* __ASSEMBLY__ */
1575
1577
#define ALT_ECC_NANDW_WDATA2BUS_RESET 0x00000000
1578
1579
#define ALT_ECC_NANDW_WDATA2BUS_OFST 0x5c
1580
1581
#define ALT_ECC_NANDW_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA2BUS_OFST))
1582
1604
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_LSB 0
1605
1606
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_MSB 31
1607
1608
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1609
1610
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1611
1612
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1613
1614
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1615
1616
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1617
1618
#define ALT_ECC_NANDW_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1619
1620
#ifndef __ASSEMBLY__
1621
1631
struct
ALT_ECC_NANDW_WDATA3BUS_s
1632
{
1633
uint32_t
ECC_WDataBUS
: 32;
1634
};
1635
1637
typedef
volatile
struct
ALT_ECC_NANDW_WDATA3BUS_s
ALT_ECC_NANDW_WDATA3BUS_t
;
1638
#endif
/* __ASSEMBLY__ */
1639
1641
#define ALT_ECC_NANDW_WDATA3BUS_RESET 0x00000000
1642
1643
#define ALT_ECC_NANDW_WDATA3BUS_OFST 0x60
1644
1645
#define ALT_ECC_NANDW_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATA3BUS_OFST))
1646
1676
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1677
1678
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1679
1680
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1681
1682
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1683
1684
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1685
1686
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1687
1688
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1689
1690
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1691
1701
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1702
1703
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1704
1705
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1706
1707
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1708
1709
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1710
1711
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1712
1713
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1714
1715
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1716
1726
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1727
1728
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1729
1730
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1731
1732
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1733
1734
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1735
1736
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1737
1738
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1739
1740
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1741
1751
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1752
1753
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1754
1755
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1756
1757
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1758
1759
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1760
1761
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1762
1763
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1764
1765
#define ALT_ECC_NANDW_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1766
1767
#ifndef __ASSEMBLY__
1768
1778
struct
ALT_ECC_NANDW_RDATAECC0BUS_s
1779
{
1780
uint32_t
ECC_RDataecc0BUS
: 7;
1781
uint32_t : 1;
1782
uint32_t
ECC_RDataecc1BUS
: 7;
1783
uint32_t : 1;
1784
uint32_t
ECC_RDataecc2BUS
: 7;
1785
uint32_t : 1;
1786
uint32_t
ECC_RDataecc3BUS
: 7;
1787
uint32_t : 1;
1788
};
1789
1791
typedef
volatile
struct
ALT_ECC_NANDW_RDATAECC0BUS_s
ALT_ECC_NANDW_RDATAECC0BUS_t
;
1792
#endif
/* __ASSEMBLY__ */
1793
1795
#define ALT_ECC_NANDW_RDATAECC0BUS_RESET 0x00000000
1796
1797
#define ALT_ECC_NANDW_RDATAECC0BUS_OFST 0x64
1798
1799
#define ALT_ECC_NANDW_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATAECC0BUS_OFST))
1800
1830
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1831
1832
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1833
1834
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1835
1836
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1837
1838
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1839
1840
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1841
1842
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1843
1844
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1845
1855
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1856
1857
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1858
1859
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1860
1861
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1862
1863
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1864
1865
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1866
1867
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1868
1869
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1870
1880
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1881
1882
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1883
1884
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1885
1886
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1887
1888
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1889
1890
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1891
1892
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1893
1894
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1895
1905
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1906
1907
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1908
1909
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1910
1911
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1912
1913
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1914
1915
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1916
1917
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1918
1919
#define ALT_ECC_NANDW_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1920
1921
#ifndef __ASSEMBLY__
1922
1932
struct
ALT_ECC_NANDW_RDATAECC1BUS_s
1933
{
1934
uint32_t
ECC_RDataecc4BUS
: 7;
1935
uint32_t : 1;
1936
uint32_t
ECC_RDataecc5BUS
: 7;
1937
uint32_t : 1;
1938
uint32_t
ECC_RDataecc6BUS
: 7;
1939
uint32_t : 1;
1940
uint32_t
ECC_RDataecc7BUS
: 7;
1941
uint32_t : 1;
1942
};
1943
1945
typedef
volatile
struct
ALT_ECC_NANDW_RDATAECC1BUS_s
ALT_ECC_NANDW_RDATAECC1BUS_t
;
1946
#endif
/* __ASSEMBLY__ */
1947
1949
#define ALT_ECC_NANDW_RDATAECC1BUS_RESET 0x00000000
1950
1951
#define ALT_ECC_NANDW_RDATAECC1BUS_OFST 0x68
1952
1953
#define ALT_ECC_NANDW_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_RDATAECC1BUS_OFST))
1954
1984
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1985
1986
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1987
1988
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1989
1990
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1991
1992
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1993
1994
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1995
1996
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1997
1998
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1999
2009
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2010
2011
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2012
2013
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2014
2015
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2016
2017
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2018
2019
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2020
2021
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2022
2023
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2024
2034
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2035
2036
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2037
2038
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2039
2040
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2041
2042
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2043
2044
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2045
2046
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2047
2048
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2049
2059
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2060
2061
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2062
2063
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2064
2065
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2066
2067
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2068
2069
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2070
2071
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2072
2073
#define ALT_ECC_NANDW_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2074
2075
#ifndef __ASSEMBLY__
2076
2086
struct
ALT_ECC_NANDW_WDATAECC0BUS_s
2087
{
2088
uint32_t
ECC_WDataecc0BUS
: 7;
2089
uint32_t : 1;
2090
uint32_t
ECC_WDataecc1BUS
: 7;
2091
uint32_t : 1;
2092
uint32_t
ECC_WDataecc2BUS
: 7;
2093
uint32_t : 1;
2094
uint32_t
ECC_WDataecc3BUS
: 7;
2095
uint32_t : 1;
2096
};
2097
2099
typedef
volatile
struct
ALT_ECC_NANDW_WDATAECC0BUS_s
ALT_ECC_NANDW_WDATAECC0BUS_t
;
2100
#endif
/* __ASSEMBLY__ */
2101
2103
#define ALT_ECC_NANDW_WDATAECC0BUS_RESET 0x00000000
2104
2105
#define ALT_ECC_NANDW_WDATAECC0BUS_OFST 0x6c
2106
2107
#define ALT_ECC_NANDW_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATAECC0BUS_OFST))
2108
2138
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2139
2140
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2141
2142
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2143
2144
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2145
2146
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2147
2148
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2149
2150
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2151
2152
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2153
2163
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2164
2165
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2166
2167
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2168
2169
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2170
2171
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2172
2173
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2174
2175
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2176
2177
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2178
2188
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2189
2190
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2191
2192
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2193
2194
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2195
2196
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2197
2198
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2199
2200
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2201
2202
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2203
2213
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2214
2215
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2216
2217
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2218
2219
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2220
2221
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2222
2223
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2224
2225
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2226
2227
#define ALT_ECC_NANDW_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2228
2229
#ifndef __ASSEMBLY__
2230
2240
struct
ALT_ECC_NANDW_WDATAECC1BUS_s
2241
{
2242
uint32_t
ECC_WDataecc4BUS
: 7;
2243
uint32_t : 1;
2244
uint32_t
ECC_WDataecc5BUS
: 7;
2245
uint32_t : 1;
2246
uint32_t
ECC_WDataecc6BUS
: 7;
2247
uint32_t : 1;
2248
uint32_t
ECC_WDataecc7BUS
: 7;
2249
uint32_t : 1;
2250
};
2251
2253
typedef
volatile
struct
ALT_ECC_NANDW_WDATAECC1BUS_s
ALT_ECC_NANDW_WDATAECC1BUS_t
;
2254
#endif
/* __ASSEMBLY__ */
2255
2257
#define ALT_ECC_NANDW_WDATAECC1BUS_RESET 0x00000000
2258
2259
#define ALT_ECC_NANDW_WDATAECC1BUS_OFST 0x70
2260
2261
#define ALT_ECC_NANDW_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDATAECC1BUS_OFST))
2262
2285
#define ALT_ECC_NANDW_DBYTECTL_DBEN_LSB 0
2286
2287
#define ALT_ECC_NANDW_DBYTECTL_DBEN_MSB 0
2288
2289
#define ALT_ECC_NANDW_DBYTECTL_DBEN_WIDTH 1
2290
2291
#define ALT_ECC_NANDW_DBYTECTL_DBEN_SET_MSK 0x00000001
2292
2293
#define ALT_ECC_NANDW_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2294
2295
#define ALT_ECC_NANDW_DBYTECTL_DBEN_RESET 0x0
2296
2297
#define ALT_ECC_NANDW_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2298
2299
#define ALT_ECC_NANDW_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2300
2301
#ifndef __ASSEMBLY__
2302
2312
struct
ALT_ECC_NANDW_DBYTECTL_s
2313
{
2314
uint32_t
DBEN
: 1;
2315
uint32_t : 31;
2316
};
2317
2319
typedef
volatile
struct
ALT_ECC_NANDW_DBYTECTL_s
ALT_ECC_NANDW_DBYTECTL_t
;
2320
#endif
/* __ASSEMBLY__ */
2321
2323
#define ALT_ECC_NANDW_DBYTECTL_RESET 0x00000000
2324
2325
#define ALT_ECC_NANDW_DBYTECTL_OFST 0x74
2326
2327
#define ALT_ECC_NANDW_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_DBYTECTL_OFST))
2328
2359
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_LSB 0
2360
2361
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_MSB 0
2362
2363
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_WIDTH 1
2364
2365
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_SET_MSK 0x00000001
2366
2367
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2368
2369
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_RESET 0x0
2370
2371
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2372
2373
#define ALT_ECC_NANDW_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2374
2384
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_LSB 1
2385
2386
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_MSB 1
2387
2388
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_WIDTH 1
2389
2390
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_SET_MSK 0x00000002
2391
2392
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2393
2394
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_RESET 0x0
2395
2396
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2397
2398
#define ALT_ECC_NANDW_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2399
2409
#define ALT_ECC_NANDW_ACCCTL_RDWR_LSB 8
2410
2411
#define ALT_ECC_NANDW_ACCCTL_RDWR_MSB 8
2412
2413
#define ALT_ECC_NANDW_ACCCTL_RDWR_WIDTH 1
2414
2415
#define ALT_ECC_NANDW_ACCCTL_RDWR_SET_MSK 0x00000100
2416
2417
#define ALT_ECC_NANDW_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2418
2419
#define ALT_ECC_NANDW_ACCCTL_RDWR_RESET 0x0
2420
2421
#define ALT_ECC_NANDW_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2422
2423
#define ALT_ECC_NANDW_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2424
2425
#ifndef __ASSEMBLY__
2426
2436
struct
ALT_ECC_NANDW_ACCCTL_s
2437
{
2438
uint32_t
DATAOVR
: 1;
2439
uint32_t
ECCOVR
: 1;
2440
uint32_t : 6;
2441
uint32_t
RDWR
: 1;
2442
uint32_t : 23;
2443
};
2444
2446
typedef
volatile
struct
ALT_ECC_NANDW_ACCCTL_s
ALT_ECC_NANDW_ACCCTL_t
;
2447
#endif
/* __ASSEMBLY__ */
2448
2450
#define ALT_ECC_NANDW_ACCCTL_RESET 0x00000000
2451
2452
#define ALT_ECC_NANDW_ACCCTL_OFST 0x78
2453
2454
#define ALT_ECC_NANDW_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_ACCCTL_OFST))
2455
2479
#define ALT_ECC_NANDW_STARTACC_ENBUSA_LSB 16
2480
2481
#define ALT_ECC_NANDW_STARTACC_ENBUSA_MSB 16
2482
2483
#define ALT_ECC_NANDW_STARTACC_ENBUSA_WIDTH 1
2484
2485
#define ALT_ECC_NANDW_STARTACC_ENBUSA_SET_MSK 0x00010000
2486
2487
#define ALT_ECC_NANDW_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2488
2489
#define ALT_ECC_NANDW_STARTACC_ENBUSA_RESET 0x0
2490
2491
#define ALT_ECC_NANDW_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2492
2493
#define ALT_ECC_NANDW_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2494
2495
#ifndef __ASSEMBLY__
2496
2506
struct
ALT_ECC_NANDW_STARTACC_s
2507
{
2508
uint32_t : 16;
2509
uint32_t
ENBUSA
: 1;
2510
uint32_t : 15;
2511
};
2512
2514
typedef
volatile
struct
ALT_ECC_NANDW_STARTACC_s
ALT_ECC_NANDW_STARTACC_t
;
2515
#endif
/* __ASSEMBLY__ */
2516
2518
#define ALT_ECC_NANDW_STARTACC_RESET 0x00000000
2519
2520
#define ALT_ECC_NANDW_STARTACC_OFST 0x7c
2521
2522
#define ALT_ECC_NANDW_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_STARTACC_OFST))
2523
2546
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_LSB 0
2547
2548
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_MSB 0
2549
2550
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_WIDTH 1
2551
2552
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2553
2554
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2555
2556
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_RESET 0x0
2557
2558
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2559
2560
#define ALT_ECC_NANDW_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2561
2562
#ifndef __ASSEMBLY__
2563
2573
struct
ALT_ECC_NANDW_WDCTL_s
2574
{
2575
uint32_t
WDEN_RAM
: 1;
2576
uint32_t : 31;
2577
};
2578
2580
typedef
volatile
struct
ALT_ECC_NANDW_WDCTL_s
ALT_ECC_NANDW_WDCTL_t
;
2581
#endif
/* __ASSEMBLY__ */
2582
2584
#define ALT_ECC_NANDW_WDCTL_RESET 0x00000000
2585
2586
#define ALT_ECC_NANDW_WDCTL_OFST 0x80
2587
2588
#define ALT_ECC_NANDW_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_NANDW_WDCTL_OFST))
2589
2617
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_LSB 0
2618
2619
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_MSB 6
2620
2621
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_WIDTH 7
2622
2623
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_SET_MSK 0x0000007f
2624
2625
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_CLR_MSK 0xffffff80
2626
2627
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_RESET 0x0
2628
2629
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_GET(value) (((value) & 0x0000007f) >> 0)
2630
2631
#define ALT_ECC_NANDW_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x0000007f)
2632
2643
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_LSB 31
2644
2645
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_MSB 31
2646
2647
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_WIDTH 1
2648
2649
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_SET_MSK 0x80000000
2650
2651
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2652
2653
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_RESET 0x0
2654
2655
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2656
2657
#define ALT_ECC_NANDW_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2658
2659
#ifndef __ASSEMBLY__
2660
2670
struct
ALT_ECC_NANDW_SERRLKUPA0_s
2671
{
2672
const
uint32_t
Address
: 7;
2673
uint32_t : 24;
2674
uint32_t
VALID
: 1;
2675
};
2676
2678
typedef
volatile
struct
ALT_ECC_NANDW_SERRLKUPA0_s
ALT_ECC_NANDW_SERRLKUPA0_t
;
2679
#endif
/* __ASSEMBLY__ */
2680
2682
#define ALT_ECC_NANDW_SERRLKUPA0_RESET 0x00000000
2683
2684
#define ALT_ECC_NANDW_SERRLKUPA0_OFST 0x90
2685
2686
#ifndef __ASSEMBLY__
2687
2697
struct
ALT_ECC_NANDW_s
2698
{
2699
volatile
ALT_ECC_NANDW_IP_REV_ID_t
IP_REV_ID
;
2700
volatile
uint32_t
_pad_0x4_0x7
;
2701
volatile
ALT_ECC_NANDW_CTL_t
CTRL
;
2702
volatile
ALT_ECC_NANDW_INITSTAT_t
INITSTAT
;
2703
volatile
ALT_ECC_NANDW_ERRINTEN_t
ERRINTEN
;
2704
volatile
ALT_ECC_NANDW_ERRINTENS_t
ERRINTENS
;
2705
volatile
ALT_ECC_NANDW_ERRINTENR_t
ERRINTENR
;
2706
volatile
ALT_ECC_NANDW_INTMOD_t
INTMODE
;
2707
volatile
ALT_ECC_NANDW_INTSTAT_t
INTSTAT
;
2708
volatile
ALT_ECC_NANDW_INTTEST_t
INTTEST
;
2709
volatile
ALT_ECC_NANDW_MODSTAT_t
MODSTAT
;
2710
volatile
ALT_ECC_NANDW_DERRADDRA_t
DERRADDRA
;
2711
volatile
ALT_ECC_NANDW_SERRADDRA_t
SERRADDRA
;
2712
volatile
uint32_t
_pad_0x34_0x3b
[2];
2713
volatile
ALT_ECC_NANDW_SERRCNTREG_t
SERRCNTREG
;
2714
volatile
ALT_ECC_NANDW_ADDRBUS_t
ECC_Addrbus
;
2715
volatile
ALT_ECC_NANDW_RDATA0BUS_t
ECC_RData0bus
;
2716
volatile
ALT_ECC_NANDW_RDATA1BUS_t
ECC_RData1bus
;
2717
volatile
ALT_ECC_NANDW_RDATA2BUS_t
ECC_RData2bus
;
2718
volatile
ALT_ECC_NANDW_RDATA3BUS_t
ECC_RData3bus
;
2719
volatile
ALT_ECC_NANDW_WDATA0BUS_t
ECC_WData0bus
;
2720
volatile
ALT_ECC_NANDW_WDATA1BUS_t
ECC_WData1bus
;
2721
volatile
ALT_ECC_NANDW_WDATA2BUS_t
ECC_WData2bus
;
2722
volatile
ALT_ECC_NANDW_WDATA3BUS_t
ECC_WData3bus
;
2723
volatile
ALT_ECC_NANDW_RDATAECC0BUS_t
ECC_RDataecc0bus
;
2724
volatile
ALT_ECC_NANDW_RDATAECC1BUS_t
ECC_RDataecc1bus
;
2725
volatile
ALT_ECC_NANDW_WDATAECC0BUS_t
ECC_WDataecc0bus
;
2726
volatile
ALT_ECC_NANDW_WDATAECC1BUS_t
ECC_WDataecc1bus
;
2727
volatile
ALT_ECC_NANDW_DBYTECTL_t
ECC_dbytectrl
;
2728
volatile
ALT_ECC_NANDW_ACCCTL_t
ECC_accctrl
;
2729
volatile
ALT_ECC_NANDW_STARTACC_t
ECC_startacc
;
2730
volatile
ALT_ECC_NANDW_WDCTL_t
ECC_wdctrl
;
2731
volatile
uint32_t
_pad_0x84_0x8f
[3];
2732
volatile
ALT_ECC_NANDW_SERRLKUPA0_t
SERRLKUPA0
;
2733
volatile
uint32_t
_pad_0x94_0x400
[219];
2734
};
2735
2737
typedef
volatile
struct
ALT_ECC_NANDW_s
ALT_ECC_NANDW_t
;
2739
struct
ALT_ECC_NANDW_raw_s
2740
{
2741
volatile
uint32_t
IP_REV_ID
;
2742
volatile
uint32_t
_pad_0x4_0x7
;
2743
volatile
uint32_t
CTRL
;
2744
volatile
uint32_t
INITSTAT
;
2745
volatile
uint32_t
ERRINTEN
;
2746
volatile
uint32_t
ERRINTENS
;
2747
volatile
uint32_t
ERRINTENR
;
2748
volatile
uint32_t
INTMODE
;
2749
volatile
uint32_t
INTSTAT
;
2750
volatile
uint32_t
INTTEST
;
2751
volatile
uint32_t
MODSTAT
;
2752
volatile
uint32_t
DERRADDRA
;
2753
volatile
uint32_t
SERRADDRA
;
2754
volatile
uint32_t
_pad_0x34_0x3b
[2];
2755
volatile
uint32_t
SERRCNTREG
;
2756
volatile
uint32_t
ECC_Addrbus
;
2757
volatile
uint32_t
ECC_RData0bus
;
2758
volatile
uint32_t
ECC_RData1bus
;
2759
volatile
uint32_t
ECC_RData2bus
;
2760
volatile
uint32_t
ECC_RData3bus
;
2761
volatile
uint32_t
ECC_WData0bus
;
2762
volatile
uint32_t
ECC_WData1bus
;
2763
volatile
uint32_t
ECC_WData2bus
;
2764
volatile
uint32_t
ECC_WData3bus
;
2765
volatile
uint32_t
ECC_RDataecc0bus
;
2766
volatile
uint32_t
ECC_RDataecc1bus
;
2767
volatile
uint32_t
ECC_WDataecc0bus
;
2768
volatile
uint32_t
ECC_WDataecc1bus
;
2769
volatile
uint32_t
ECC_dbytectrl
;
2770
volatile
uint32_t
ECC_accctrl
;
2771
volatile
uint32_t
ECC_startacc
;
2772
volatile
uint32_t
ECC_wdctrl
;
2773
volatile
uint32_t
_pad_0x84_0x8f
[3];
2774
volatile
uint32_t
SERRLKUPA0
;
2775
volatile
uint32_t
_pad_0x94_0x400
[219];
2776
};
2777
2779
typedef
volatile
struct
ALT_ECC_NANDW_raw_s
ALT_ECC_NANDW_raw_t
;
2780
#endif
/* __ASSEMBLY__ */
2781
2783
#ifdef __cplusplus
2784
}
2785
#endif
/* __cplusplus */
2786
#endif
/* __ALT_SOCAL_ECC_NANDW_H__ */
2787
include
soc_a10
socal
alt_ecc_nandw.h
Generated on Tue Sep 8 2015 13:32:55 for Altera SoCAL by
1.8.2