Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Interrupt Status Register - isr

Description

This register reports the status of the SPI Master interrupts after they have been masked.

Register Layout

Bits Access Reset Description
[0] R 0x0 Transmit FIFO Empty Interrupt Status
[1] R 0x0 Transmit FIFO Overflow Interrupt Status
[2] R 0x0 Receive FIFO Underflow Interrupt Status
[3] R 0x0 Receive FIFO Overflow Interrupt Status
[4] R 0x0 Receive FIFO Full Interrupt Status
[5] R 0x0 Multi-Master Contention Interrupt Status
[31:6] ??? 0x0 UNDEFINED

Field : Transmit FIFO Empty Interrupt Status - txeis

Empty status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_TXEIS_E_INACT 0x0 spi_txe_intr interrupt is not active after
: masking
ALT_SPIM_ISR_TXEIS_E_ACT 0x1 spi_txe_intr interrupt is active after masking

Field Access Macros:

#define ALT_SPIM_ISR_TXEIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_TXEIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_TXEIS_LSB   0
 
#define ALT_SPIM_ISR_TXEIS_MSB   0
 
#define ALT_SPIM_ISR_TXEIS_WIDTH   1
 
#define ALT_SPIM_ISR_TXEIS_SET_MSK   0x00000001
 
#define ALT_SPIM_ISR_TXEIS_CLR_MSK   0xfffffffe
 
#define ALT_SPIM_ISR_TXEIS_RESET   0x0
 
#define ALT_SPIM_ISR_TXEIS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SPIM_ISR_TXEIS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit FIFO Overflow Interrupt Status - txois

Overflow Status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_TXOIS_E_INACT 0x0 spi_txo_intr interrupt is not active after
: masking
ALT_SPIM_ISR_TXOIS_E_ACT 0x1 spi_txo_intr interrupt is active after masking

Field Access Macros:

#define ALT_SPIM_ISR_TXOIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_TXOIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_TXOIS_LSB   1
 
#define ALT_SPIM_ISR_TXOIS_MSB   1
 
#define ALT_SPIM_ISR_TXOIS_WIDTH   1
 
#define ALT_SPIM_ISR_TXOIS_SET_MSK   0x00000002
 
#define ALT_SPIM_ISR_TXOIS_CLR_MSK   0xfffffffd
 
#define ALT_SPIM_ISR_TXOIS_RESET   0x0
 
#define ALT_SPIM_ISR_TXOIS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SPIM_ISR_TXOIS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Receive FIFO Underflow Interrupt Status - rxuis

Underflow Status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_RXUIS_E_INACT 0x0 spi_rxu_intr interrupt is not active after
: masking
ALT_SPIM_ISR_RXUIS_E_ACT 0x1 spi_rxu_intr interrupt is active after masking

Field Access Macros:

#define ALT_SPIM_ISR_RXUIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_RXUIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_RXUIS_LSB   2
 
#define ALT_SPIM_ISR_RXUIS_MSB   2
 
#define ALT_SPIM_ISR_RXUIS_WIDTH   1
 
#define ALT_SPIM_ISR_RXUIS_SET_MSK   0x00000004
 
#define ALT_SPIM_ISR_RXUIS_CLR_MSK   0xfffffffb
 
#define ALT_SPIM_ISR_RXUIS_RESET   0x0
 
#define ALT_SPIM_ISR_RXUIS_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SPIM_ISR_RXUIS_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Receive FIFO Overflow Interrupt Status - rxois

Overflow Status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_RXOIS_E_INACT 0x0 spi_rxo_intr interrupt is not active after
: masking
ALT_SPIM_ISR_RXOIS_E_ACT 0x1 spi_rxo_intr interrupt is active after masking

Field Access Macros:

#define ALT_SPIM_ISR_RXOIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_RXOIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_RXOIS_LSB   3
 
#define ALT_SPIM_ISR_RXOIS_MSB   3
 
#define ALT_SPIM_ISR_RXOIS_WIDTH   1
 
#define ALT_SPIM_ISR_RXOIS_SET_MSK   0x00000008
 
#define ALT_SPIM_ISR_RXOIS_CLR_MSK   0xfffffff7
 
#define ALT_SPIM_ISR_RXOIS_RESET   0x0
 
#define ALT_SPIM_ISR_RXOIS_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SPIM_ISR_RXOIS_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Receive FIFO Full Interrupt Status - rxfis

Full Status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_RXFIS_E_INACT 0x0 spi_rxf_intr interrupt is not active after
: masking
ALT_SPIM_ISR_RXFIS_E_ACT 0x1 spi_rxf_intr interrupt is full after masking

Field Access Macros:

#define ALT_SPIM_ISR_RXFIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_RXFIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_RXFIS_LSB   4
 
#define ALT_SPIM_ISR_RXFIS_MSB   4
 
#define ALT_SPIM_ISR_RXFIS_WIDTH   1
 
#define ALT_SPIM_ISR_RXFIS_SET_MSK   0x00000010
 
#define ALT_SPIM_ISR_RXFIS_CLR_MSK   0xffffffef
 
#define ALT_SPIM_ISR_RXFIS_RESET   0x0
 
#define ALT_SPIM_ISR_RXFIS_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SPIM_ISR_RXFIS_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Multi-Master Contention Interrupt Status - mstis

Multi-master contention status.

Field Enumeration Values:

Enum Value Description
ALT_SPIM_ISR_MSTIS_E_INACT 0x0 0 = ssi_mst_intr interrupt not active after
: masking
ALT_SPIM_ISR_MSTIS_E_ACT 0x1 1 = ssi_mst_intr interrupt is active after
: masking

Field Access Macros:

#define ALT_SPIM_ISR_MSTIS_E_INACT   0x0
 
#define ALT_SPIM_ISR_MSTIS_E_ACT   0x1
 
#define ALT_SPIM_ISR_MSTIS_LSB   5
 
#define ALT_SPIM_ISR_MSTIS_MSB   5
 
#define ALT_SPIM_ISR_MSTIS_WIDTH   1
 
#define ALT_SPIM_ISR_MSTIS_SET_MSK   0x00000020
 
#define ALT_SPIM_ISR_MSTIS_CLR_MSK   0xffffffdf
 
#define ALT_SPIM_ISR_MSTIS_RESET   0x0
 
#define ALT_SPIM_ISR_MSTIS_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SPIM_ISR_MSTIS_SET(value)   (((value) << 5) & 0x00000020)
 

Data Structures

struct  ALT_SPIM_ISR_s
 

Macros

#define ALT_SPIM_ISR_OFST   0x30
 
#define ALT_SPIM_ISR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
 

Typedefs

typedef struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t
 

Data Structure Documentation

struct ALT_SPIM_ISR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SPIM_ISR.

Data Fields
const uint32_t txeis: 1 Transmit FIFO Empty Interrupt Status
const uint32_t txois: 1 Transmit FIFO Overflow Interrupt Status
const uint32_t rxuis: 1 Receive FIFO Underflow Interrupt Status
const uint32_t rxois: 1 Receive FIFO Overflow Interrupt Status
const uint32_t rxfis: 1 Receive FIFO Full Interrupt Status
const uint32_t mstis: 1 Multi-Master Contention Interrupt Status
uint32_t __pad0__: 26 UNDEFINED

Macro Definitions

#define ALT_SPIM_ISR_TXEIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_TXEIS

spi_txe_intr interrupt is not active after masking

#define ALT_SPIM_ISR_TXEIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_TXEIS

spi_txe_intr interrupt is active after masking

#define ALT_SPIM_ISR_TXEIS_LSB   0

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXEIS register field.

#define ALT_SPIM_ISR_TXEIS_MSB   0

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXEIS register field.

#define ALT_SPIM_ISR_TXEIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_TXEIS register field.

#define ALT_SPIM_ISR_TXEIS_SET_MSK   0x00000001

The mask used to set the ALT_SPIM_ISR_TXEIS register field value.

#define ALT_SPIM_ISR_TXEIS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SPIM_ISR_TXEIS register field value.

#define ALT_SPIM_ISR_TXEIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_TXEIS register field.

#define ALT_SPIM_ISR_TXEIS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SPIM_ISR_TXEIS field value from a register.

#define ALT_SPIM_ISR_TXEIS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SPIM_ISR_TXEIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_TXOIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_TXOIS

spi_txo_intr interrupt is not active after masking

#define ALT_SPIM_ISR_TXOIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_TXOIS

spi_txo_intr interrupt is active after masking

#define ALT_SPIM_ISR_TXOIS_LSB   1

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_TXOIS register field.

#define ALT_SPIM_ISR_TXOIS_MSB   1

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_TXOIS register field.

#define ALT_SPIM_ISR_TXOIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_TXOIS register field.

#define ALT_SPIM_ISR_TXOIS_SET_MSK   0x00000002

The mask used to set the ALT_SPIM_ISR_TXOIS register field value.

#define ALT_SPIM_ISR_TXOIS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SPIM_ISR_TXOIS register field value.

#define ALT_SPIM_ISR_TXOIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_TXOIS register field.

#define ALT_SPIM_ISR_TXOIS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SPIM_ISR_TXOIS field value from a register.

#define ALT_SPIM_ISR_TXOIS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SPIM_ISR_TXOIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_RXUIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_RXUIS

spi_rxu_intr interrupt is not active after masking

#define ALT_SPIM_ISR_RXUIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_RXUIS

spi_rxu_intr interrupt is active after masking

#define ALT_SPIM_ISR_RXUIS_LSB   2

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXUIS register field.

#define ALT_SPIM_ISR_RXUIS_MSB   2

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXUIS register field.

#define ALT_SPIM_ISR_RXUIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_RXUIS register field.

#define ALT_SPIM_ISR_RXUIS_SET_MSK   0x00000004

The mask used to set the ALT_SPIM_ISR_RXUIS register field value.

#define ALT_SPIM_ISR_RXUIS_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SPIM_ISR_RXUIS register field value.

#define ALT_SPIM_ISR_RXUIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_RXUIS register field.

#define ALT_SPIM_ISR_RXUIS_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SPIM_ISR_RXUIS field value from a register.

#define ALT_SPIM_ISR_RXUIS_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SPIM_ISR_RXUIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_RXOIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_RXOIS

spi_rxo_intr interrupt is not active after masking

#define ALT_SPIM_ISR_RXOIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_RXOIS

spi_rxo_intr interrupt is active after masking

#define ALT_SPIM_ISR_RXOIS_LSB   3

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXOIS register field.

#define ALT_SPIM_ISR_RXOIS_MSB   3

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXOIS register field.

#define ALT_SPIM_ISR_RXOIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_RXOIS register field.

#define ALT_SPIM_ISR_RXOIS_SET_MSK   0x00000008

The mask used to set the ALT_SPIM_ISR_RXOIS register field value.

#define ALT_SPIM_ISR_RXOIS_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SPIM_ISR_RXOIS register field value.

#define ALT_SPIM_ISR_RXOIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_RXOIS register field.

#define ALT_SPIM_ISR_RXOIS_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SPIM_ISR_RXOIS field value from a register.

#define ALT_SPIM_ISR_RXOIS_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SPIM_ISR_RXOIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_RXFIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_RXFIS

spi_rxf_intr interrupt is not active after masking

#define ALT_SPIM_ISR_RXFIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_RXFIS

spi_rxf_intr interrupt is full after masking

#define ALT_SPIM_ISR_RXFIS_LSB   4

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_RXFIS register field.

#define ALT_SPIM_ISR_RXFIS_MSB   4

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_RXFIS register field.

#define ALT_SPIM_ISR_RXFIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_RXFIS register field.

#define ALT_SPIM_ISR_RXFIS_SET_MSK   0x00000010

The mask used to set the ALT_SPIM_ISR_RXFIS register field value.

#define ALT_SPIM_ISR_RXFIS_CLR_MSK   0xffffffef

The mask used to clear the ALT_SPIM_ISR_RXFIS register field value.

#define ALT_SPIM_ISR_RXFIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_RXFIS register field.

#define ALT_SPIM_ISR_RXFIS_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SPIM_ISR_RXFIS field value from a register.

#define ALT_SPIM_ISR_RXFIS_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SPIM_ISR_RXFIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_MSTIS_E_INACT   0x0

Enumerated value for register field ALT_SPIM_ISR_MSTIS

0 = ssi_mst_intr interrupt not active after masking

#define ALT_SPIM_ISR_MSTIS_E_ACT   0x1

Enumerated value for register field ALT_SPIM_ISR_MSTIS

1 = ssi_mst_intr interrupt is active after masking

#define ALT_SPIM_ISR_MSTIS_LSB   5

The Least Significant Bit (LSB) position of the ALT_SPIM_ISR_MSTIS register field.

#define ALT_SPIM_ISR_MSTIS_MSB   5

The Most Significant Bit (MSB) position of the ALT_SPIM_ISR_MSTIS register field.

#define ALT_SPIM_ISR_MSTIS_WIDTH   1

The width in bits of the ALT_SPIM_ISR_MSTIS register field.

#define ALT_SPIM_ISR_MSTIS_SET_MSK   0x00000020

The mask used to set the ALT_SPIM_ISR_MSTIS register field value.

#define ALT_SPIM_ISR_MSTIS_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SPIM_ISR_MSTIS register field value.

#define ALT_SPIM_ISR_MSTIS_RESET   0x0

The reset value of the ALT_SPIM_ISR_MSTIS register field.

#define ALT_SPIM_ISR_MSTIS_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SPIM_ISR_MSTIS field value from a register.

#define ALT_SPIM_ISR_MSTIS_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SPIM_ISR_MSTIS register field value suitable for setting the register.

#define ALT_SPIM_ISR_OFST   0x30

The byte offset of the ALT_SPIM_ISR register from the beginning of the component.

#define ALT_SPIM_ISR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))

The address of the ALT_SPIM_ISR register.

Typedef Documentation

The typedef declaration for register ALT_SPIM_ISR.