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alt_sdmmc.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALTERA_ALT_SDMMC_H__
36
#define __ALTERA_ALT_SDMMC_H__
37
38
#ifdef __cplusplus
39
extern
"C"
40
{
41
#endif
/* __cplusplus */
42
107
#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
108
113
#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
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116
#define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
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#define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
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#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
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#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
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#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
125
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#define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
127
128
#define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
129
130
#define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
131
153
#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
154
159
#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
160
162
#define ALT_SDMMC_CTL_FIFO_RST_LSB 1
163
164
#define ALT_SDMMC_CTL_FIFO_RST_MSB 1
165
166
#define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
167
168
#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
169
170
#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
171
172
#define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
173
174
#define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
175
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#define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
199
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#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
205
207
#define ALT_SDMMC_CTL_DMA_RST_LSB 2
208
209
#define ALT_SDMMC_CTL_DMA_RST_MSB 2
210
211
#define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
212
213
#define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
214
215
#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
216
217
#define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
218
219
#define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
220
221
#define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
222
244
#define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
245
250
#define ALT_SDMMC_CTL_INT_EN_E_END 0x1
251
253
#define ALT_SDMMC_CTL_INT_EN_LSB 4
254
255
#define ALT_SDMMC_CTL_INT_EN_MSB 4
256
257
#define ALT_SDMMC_CTL_INT_EN_WIDTH 1
258
259
#define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
260
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#define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
262
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#define ALT_SDMMC_CTL_INT_EN_RESET 0x0
264
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#define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
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289
#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
290
295
#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
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298
#define ALT_SDMMC_CTL_RD_WAIT_LSB 6
299
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#define ALT_SDMMC_CTL_RD_WAIT_MSB 6
301
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#define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
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#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
305
306
#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
307
308
#define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
309
310
#define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
311
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#define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
313
338
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
339
344
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
345
347
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
348
349
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
350
351
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
352
353
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
354
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#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
356
357
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
358
359
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
360
361
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
362
386
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
387
392
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
393
395
#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
396
397
#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
398
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#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
400
401
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
402
403
#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
404
405
#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
406
407
#define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
408
409
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
410
440
#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
441
446
#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
447
449
#define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
450
451
#define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
452
453
#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
454
455
#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
456
457
#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
458
459
#define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
460
461
#define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
462
463
#define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
464
490
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
491
496
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
497
499
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
500
501
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
502
503
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
504
505
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
506
507
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
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509
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
510
511
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
512
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#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
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544
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
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555
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
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#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
562
584
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
594
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
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#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
608
609
#ifndef __ASSEMBLY__
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620
struct
ALT_SDMMC_CTL_s
621
{
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uint32_t
controller_reset
: 1;
623
uint32_t
fifo_reset
: 1;
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uint32_t
dma_reset
: 1;
625
uint32_t : 1;
626
uint32_t
int_enable
: 1;
627
uint32_t : 1;
628
uint32_t
read_wait
: 1;
629
uint32_t
send_irq_response
: 1;
630
uint32_t
abort_read_data
: 1;
631
uint32_t
send_ccsd
: 1;
632
uint32_t
send_auto_stop_ccsd
: 1;
633
uint32_t
ceata_device_interrupt_status
: 1;
634
uint32_t : 13;
635
uint32_t
use_internal_dmac
: 1;
636
uint32_t : 6;
637
};
638
640
typedef
volatile
struct
ALT_SDMMC_CTL_s
ALT_SDMMC_CTL_t
;
641
#endif
/* __ASSEMBLY__ */
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#define ALT_SDMMC_CTL_OFST 0x0
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682
#define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
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688
#define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
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#define ALT_SDMMC_PWREN_POWER_EN_LSB 0
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#define ALT_SDMMC_PWREN_POWER_EN_MSB 0
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#define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
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#define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
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#define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
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#define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
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#define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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struct
ALT_SDMMC_PWREN_s
719
{
720
uint32_t
power_enable
: 1;
721
uint32_t : 31;
722
};
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typedef
volatile
struct
ALT_SDMMC_PWREN_s
ALT_SDMMC_PWREN_t
;
726
#endif
/* __ASSEMBLY__ */
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#define ALT_SDMMC_PWREN_OFST 0x4
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
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#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
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#ifndef __ASSEMBLY__
772
782
struct
ALT_SDMMC_CLKDIV_s
783
{
784
uint32_t
clk_divider0
: 8;
785
uint32_t : 24;
786
};
787
789
typedef
volatile
struct
ALT_SDMMC_CLKDIV_s
ALT_SDMMC_CLKDIV_t
;
790
#endif
/* __ASSEMBLY__ */
791
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#define ALT_SDMMC_CLKDIV_OFST 0x8
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#define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
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#define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
833
834
#define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 1
835
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#define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 2
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#define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0x00000003
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#define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0xfffffffc
841
842
#define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
843
844
#define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0x00000003) >> 0)
845
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#define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0x00000003)
847
848
#ifndef __ASSEMBLY__
849
859
struct
ALT_SDMMC_CLKSRC_s
860
{
861
uint32_t
clk_source
: 2;
862
uint32_t : 30;
863
};
864
866
typedef
volatile
struct
ALT_SDMMC_CLKSRC_s
ALT_SDMMC_CLKSRC_t
;
867
#endif
/* __ASSEMBLY__ */
868
870
#define ALT_SDMMC_CLKSRC_OFST 0xc
871
907
#define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
908
913
#define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
914
916
#define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
917
918
#define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
919
920
#define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
921
922
#define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
923
924
#define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
925
926
#define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
927
928
#define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
929
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#define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
931
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#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
955
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#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
961
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#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
964
965
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
966
967
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
968
969
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
970
971
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
972
973
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
974
975
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
976
977
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
978
979
#ifndef __ASSEMBLY__
980
990
struct
ALT_SDMMC_CLKENA_s
991
{
992
uint32_t
cclk_enable
: 1;
993
uint32_t : 15;
994
uint32_t
cclk_low_power
: 1;
995
uint32_t : 15;
996
};
997
999
typedef
volatile
struct
ALT_SDMMC_CLKENA_s
ALT_SDMMC_CLKENA_t
;
1000
#endif
/* __ASSEMBLY__ */
1001
1003
#define ALT_SDMMC_CLKENA_OFST 0x10
1004
1027
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1028
1029
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1030
1031
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1032
1033
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1034
1035
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1036
1037
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1038
1039
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1040
1041
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1042
1054
#define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1055
1056
#define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1057
1058
#define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1059
1060
#define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1061
1062
#define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1063
1064
#define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1065
1066
#define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1067
1068
#define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1069
1070
#ifndef __ASSEMBLY__
1071
1081
struct
ALT_SDMMC_TMOUT_s
1082
{
1083
uint32_t
response_timeout
: 8;
1084
uint32_t
data_timeout
: 24;
1085
};
1086
1088
typedef
volatile
struct
ALT_SDMMC_TMOUT_s
ALT_SDMMC_TMOUT_t
;
1089
#endif
/* __ASSEMBLY__ */
1090
1092
#define ALT_SDMMC_TMOUT_OFST 0x14
1093
1129
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1130
1135
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1136
1138
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1139
1140
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1141
1142
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1143
1144
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1145
1146
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1147
1148
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1149
1150
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1151
1152
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1153
1175
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1176
1181
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1182
1184
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1185
1186
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1187
1188
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1189
1190
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1191
1192
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1193
1194
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1195
1196
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1197
1198
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1199
1200
#ifndef __ASSEMBLY__
1201
1211
struct
ALT_SDMMC_CTYPE_s
1212
{
1213
uint32_t
card_width2
: 1;
1214
uint32_t : 15;
1215
uint32_t
card_width1
: 1;
1216
uint32_t : 15;
1217
};
1218
1220
typedef
volatile
struct
ALT_SDMMC_CTYPE_s
ALT_SDMMC_CTYPE_t
;
1221
#endif
/* __ASSEMBLY__ */
1222
1224
#define ALT_SDMMC_CTYPE_OFST 0x18
1225
1248
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1249
1250
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1251
1252
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1253
1254
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1255
1256
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1257
1258
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1259
1260
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1261
1262
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1263
1264
#ifndef __ASSEMBLY__
1265
1275
struct
ALT_SDMMC_BLKSIZ_s
1276
{
1277
uint32_t
block_size
: 16;
1278
uint32_t : 16;
1279
};
1280
1282
typedef
volatile
struct
ALT_SDMMC_BLKSIZ_s
ALT_SDMMC_BLKSIZ_t
;
1283
#endif
/* __ASSEMBLY__ */
1284
1286
#define ALT_SDMMC_BLKSIZ_OFST 0x1c
1287
1318
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1319
1320
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1321
1322
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1323
1324
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1325
1326
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1327
1328
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1329
1330
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1331
1332
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1333
1334
#ifndef __ASSEMBLY__
1335
1345
struct
ALT_SDMMC_BYTCNT_s
1346
{
1347
uint32_t
byte_count
: 32;
1348
};
1349
1351
typedef
volatile
struct
ALT_SDMMC_BYTCNT_s
ALT_SDMMC_BYTCNT_t
;
1352
#endif
/* __ASSEMBLY__ */
1353
1355
#define ALT_SDMMC_BYTCNT_OFST 0x20
1356
1407
#define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1408
1413
#define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1414
1416
#define ALT_SDMMC_INTMSK_CD_LSB 0
1417
1418
#define ALT_SDMMC_INTMSK_CD_MSB 0
1419
1420
#define ALT_SDMMC_INTMSK_CD_WIDTH 1
1421
1422
#define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1423
1424
#define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1425
1426
#define ALT_SDMMC_INTMSK_CD_RESET 0x0
1427
1428
#define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1429
1430
#define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1431
1453
#define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1454
1459
#define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1460
1462
#define ALT_SDMMC_INTMSK_RE_LSB 1
1463
1464
#define ALT_SDMMC_INTMSK_RE_MSB 1
1465
1466
#define ALT_SDMMC_INTMSK_RE_WIDTH 1
1467
1468
#define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1469
1470
#define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1471
1472
#define ALT_SDMMC_INTMSK_RE_RESET 0x0
1473
1474
#define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1475
1476
#define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1477
1499
#define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1500
1505
#define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1506
1508
#define ALT_SDMMC_INTMSK_CMD_LSB 2
1509
1510
#define ALT_SDMMC_INTMSK_CMD_MSB 2
1511
1512
#define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1513
1514
#define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1515
1516
#define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1517
1518
#define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1519
1520
#define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1521
1522
#define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1523
1545
#define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1546
1551
#define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1552
1554
#define ALT_SDMMC_INTMSK_DTO_LSB 3
1555
1556
#define ALT_SDMMC_INTMSK_DTO_MSB 3
1557
1558
#define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1559
1560
#define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1561
1562
#define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1563
1564
#define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1565
1566
#define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1567
1568
#define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1569
1591
#define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1592
1597
#define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1598
1600
#define ALT_SDMMC_INTMSK_TXDR_LSB 4
1601
1602
#define ALT_SDMMC_INTMSK_TXDR_MSB 4
1603
1604
#define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1605
1606
#define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1607
1608
#define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1609
1610
#define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1611
1612
#define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1613
1614
#define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1615
1637
#define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1638
1643
#define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1644
1646
#define ALT_SDMMC_INTMSK_RXDR_LSB 5
1647
1648
#define ALT_SDMMC_INTMSK_RXDR_MSB 5
1649
1650
#define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1651
1652
#define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1653
1654
#define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1655
1656
#define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1657
1658
#define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1659
1660
#define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1661
1683
#define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
1684
1689
#define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
1690
1692
#define ALT_SDMMC_INTMSK_RCRC_LSB 6
1693
1694
#define ALT_SDMMC_INTMSK_RCRC_MSB 6
1695
1696
#define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
1697
1698
#define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
1699
1700
#define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
1701
1702
#define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
1703
1704
#define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
1705
1706
#define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
1707
1729
#define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
1730
1735
#define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
1736
1738
#define ALT_SDMMC_INTMSK_DCRC_LSB 7
1739
1740
#define ALT_SDMMC_INTMSK_DCRC_MSB 7
1741
1742
#define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
1743
1744
#define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
1745
1746
#define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
1747
1748
#define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
1749
1750
#define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
1751
1752
#define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
1753
1775
#define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
1776
1781
#define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
1782
1784
#define ALT_SDMMC_INTMSK_RTO_LSB 8
1785
1786
#define ALT_SDMMC_INTMSK_RTO_MSB 8
1787
1788
#define ALT_SDMMC_INTMSK_RTO_WIDTH 1
1789
1790
#define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
1791
1792
#define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
1793
1794
#define ALT_SDMMC_INTMSK_RTO_RESET 0x0
1795
1796
#define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
1797
1798
#define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
1799
1821
#define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
1822
1827
#define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
1828
1830
#define ALT_SDMMC_INTMSK_DRT_LSB 9
1831
1832
#define ALT_SDMMC_INTMSK_DRT_MSB 9
1833
1834
#define ALT_SDMMC_INTMSK_DRT_WIDTH 1
1835
1836
#define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
1837
1838
#define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
1839
1840
#define ALT_SDMMC_INTMSK_DRT_RESET 0x0
1841
1842
#define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
1843
1844
#define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
1845
1867
#define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
1868
1873
#define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
1874
1876
#define ALT_SDMMC_INTMSK_HTO_LSB 10
1877
1878
#define ALT_SDMMC_INTMSK_HTO_MSB 10
1879
1880
#define ALT_SDMMC_INTMSK_HTO_WIDTH 1
1881
1882
#define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
1883
1884
#define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
1885
1886
#define ALT_SDMMC_INTMSK_HTO_RESET 0x0
1887
1888
#define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
1889
1890
#define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
1891
1913
#define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
1914
1919
#define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
1920
1922
#define ALT_SDMMC_INTMSK_FRUN_LSB 11
1923
1924
#define ALT_SDMMC_INTMSK_FRUN_MSB 11
1925
1926
#define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
1927
1928
#define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
1929
1930
#define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
1931
1932
#define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
1933
1934
#define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
1935
1936
#define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
1937
1959
#define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
1960
1965
#define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
1966
1968
#define ALT_SDMMC_INTMSK_HLE_LSB 12
1969
1970
#define ALT_SDMMC_INTMSK_HLE_MSB 12
1971
1972
#define ALT_SDMMC_INTMSK_HLE_WIDTH 1
1973
1974
#define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
1975
1976
#define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
1977
1978
#define ALT_SDMMC_INTMSK_HLE_RESET 0x0
1979
1980
#define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
1981
1982
#define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
1983
2005
#define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2006
2011
#define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2012
2014
#define ALT_SDMMC_INTMSK_SBE_LSB 13
2015
2016
#define ALT_SDMMC_INTMSK_SBE_MSB 13
2017
2018
#define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2019
2020
#define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2021
2022
#define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2023
2024
#define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2025
2026
#define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2027
2028
#define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2029
2051
#define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2052
2057
#define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2058
2060
#define ALT_SDMMC_INTMSK_ACD_LSB 14
2061
2062
#define ALT_SDMMC_INTMSK_ACD_MSB 14
2063
2064
#define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2065
2066
#define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2067
2068
#define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2069
2070
#define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2071
2072
#define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2073
2074
#define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2075
2097
#define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2098
2103
#define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2104
2106
#define ALT_SDMMC_INTMSK_EBE_LSB 15
2107
2108
#define ALT_SDMMC_INTMSK_EBE_MSB 15
2109
2110
#define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2111
2112
#define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2113
2114
#define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2115
2116
#define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2117
2118
#define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2119
2120
#define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2121
2143
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2144
2149
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2150
2152
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2153
2154
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 16
2155
2156
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 1
2157
2158
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0x00010000
2159
2160
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0xfffeffff
2161
2162
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2163
2164
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0x00010000) >> 16)
2165
2166
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0x00010000)
2167
2168
#ifndef __ASSEMBLY__
2169
2179
struct
ALT_SDMMC_INTMSK_s
2180
{
2181
uint32_t
cd
: 1;
2182
uint32_t
re
: 1;
2183
uint32_t
cmd
: 1;
2184
uint32_t
dto
: 1;
2185
uint32_t
txdr
: 1;
2186
uint32_t
rxdr
: 1;
2187
uint32_t
rcrc
: 1;
2188
uint32_t
dcrc
: 1;
2189
uint32_t
rto
: 1;
2190
uint32_t
drt
: 1;
2191
uint32_t
hto
: 1;
2192
uint32_t
frun
: 1;
2193
uint32_t
hle
: 1;
2194
uint32_t
sbe
: 1;
2195
uint32_t
acd
: 1;
2196
uint32_t
ebe
: 1;
2197
uint32_t
sdio_int_mask
: 1;
2198
uint32_t : 15;
2199
};
2200
2202
typedef
volatile
struct
ALT_SDMMC_INTMSK_s
ALT_SDMMC_INTMSK_t
;
2203
#endif
/* __ASSEMBLY__ */
2204
2206
#define ALT_SDMMC_INTMSK_OFST 0x24
2207
2229
#define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2230
2231
#define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2232
2233
#define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2234
2235
#define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2236
2237
#define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2238
2239
#define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2240
2241
#define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2242
2243
#define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2244
2245
#ifndef __ASSEMBLY__
2246
2256
struct
ALT_SDMMC_CMDARG_s
2257
{
2258
uint32_t
cmd_arg
: 32;
2259
};
2260
2262
typedef
volatile
struct
ALT_SDMMC_CMDARG_s
ALT_SDMMC_CMDARG_t
;
2263
#endif
/* __ASSEMBLY__ */
2264
2266
#define ALT_SDMMC_CMDARG_OFST 0x28
2267
2311
#define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2312
2313
#define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2314
2315
#define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2316
2317
#define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2318
2319
#define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2320
2321
#define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2322
2323
#define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2324
2325
#define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2326
2347
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x0
2348
2353
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x1
2354
2356
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2357
2358
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2359
2360
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2361
2362
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2363
2364
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2365
2366
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2367
2368
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2369
2370
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2371
2392
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2393
2398
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2399
2401
#define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2402
2403
#define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2404
2405
#define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2406
2407
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2408
2409
#define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2410
2411
#define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2412
2413
#define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2414
2415
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2416
2438
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2439
2444
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2445
2447
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2448
2449
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2450
2451
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2452
2453
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2454
2455
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2456
2457
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2458
2459
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2460
2461
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2462
2483
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2484
2489
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2490
2492
#define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2493
2494
#define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2495
2496
#define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2497
2498
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2499
2500
#define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2501
2502
#define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2503
2504
#define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2505
2506
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2507
2528
#define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2529
2534
#define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2535
2537
#define ALT_SDMMC_CMD_RD_WR_LSB 10
2538
2539
#define ALT_SDMMC_CMD_RD_WR_MSB 10
2540
2541
#define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2542
2543
#define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2544
2545
#define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2546
2547
#define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2548
2549
#define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2550
2551
#define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2552
2573
#define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2574
2579
#define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2580
2582
#define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2583
2584
#define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2585
2586
#define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2587
2588
#define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2589
2590
#define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2591
2592
#define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2593
2594
#define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2595
2596
#define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2597
2627
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2628
2633
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2634
2636
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2637
2638
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2639
2640
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2641
2642
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2643
2644
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2645
2646
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2647
2648
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2649
2650
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
2651
2674
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
2675
2680
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
2681
2683
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
2684
2685
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
2686
2687
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
2688
2689
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
2690
2691
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
2692
2693
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
2694
2695
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
2696
2697
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
2698
2728
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
2729
2734
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
2735
2737
#define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
2738
2739
#define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
2740
2741
#define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
2742
2743
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
2744
2745
#define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
2746
2747
#define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
2748
2749
#define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
2750
2751
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
2752
2779
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
2780
2785
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
2786
2788
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
2789
2790
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
2791
2792
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
2793
2794
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
2795
2796
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
2797
2798
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
2799
2800
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
2801
2802
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
2803
2813
#define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
2814
2815
#define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
2816
2817
#define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
2818
2819
#define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
2820
2821
#define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
2822
2823
#define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
2824
2825
#define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
2826
2827
#define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
2828
2859
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
2860
2865
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
2866
2868
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
2869
2870
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
2871
2872
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
2873
2874
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
2875
2876
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
2877
2878
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
2879
2880
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
2881
2882
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
2883
2910
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
2911
2916
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
2917
2919
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
2920
2921
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
2922
2923
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
2924
2925
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
2926
2927
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
2928
2929
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
2930
2931
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
2932
2933
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
2934
2963
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
2964
2970
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
2971
2973
#define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
2974
2975
#define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
2976
2977
#define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
2978
2979
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
2980
2981
#define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
2982
2983
#define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
2984
2985
#define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
2986
2987
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
2988
3011
#define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3012
3017
#define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3018
3020
#define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3021
3022
#define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3023
3024
#define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3025
3026
#define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3027
3028
#define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3029
3030
#define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3031
3032
#define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3033
3034
#define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3035
3057
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3058
3063
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3064
3066
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3067
3068
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3069
3070
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3071
3072
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3073
3074
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3075
3076
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3077
3078
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3079
3080
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3081
3103
#define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3104
3109
#define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3110
3112
#define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3113
3114
#define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3115
3116
#define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3117
3118
#define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3119
3120
#define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3121
3122
#define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3123
3124
#define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3125
3126
#define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3127
3148
#define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3149
3154
#define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3155
3157
#define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3158
3159
#define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3160
3161
#define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3162
3163
#define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3164
3165
#define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3166
3167
#define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3168
3169
#define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3170
3171
#define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3172
3193
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3194
3199
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3200
3202
#define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3203
3204
#define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3205
3206
#define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3207
3208
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3209
3210
#define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3211
3212
#define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3213
3214
#define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3215
3216
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3217
3247
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3248
3253
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3254
3256
#define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3257
3258
#define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3259
3260
#define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3261
3262
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3263
3264
#define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3265
3266
#define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3267
3268
#define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3269
3270
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3271
3296
#define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3297
3302
#define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3303
3305
#define ALT_SDMMC_CMD_START_CMD_LSB 31
3306
3307
#define ALT_SDMMC_CMD_START_CMD_MSB 31
3308
3309
#define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3310
3311
#define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3312
3313
#define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3314
3315
#define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3316
3317
#define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3318
3319
#define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3320
3321
#ifndef __ASSEMBLY__
3322
3332
struct
ALT_SDMMC_CMD_s
3333
{
3334
uint32_t
cmd_index
: 6;
3335
uint32_t
response_expect
: 1;
3336
uint32_t
response_length
: 1;
3337
uint32_t
check_response_crc
: 1;
3338
uint32_t
data_expected
: 1;
3339
uint32_t
read_write
: 1;
3340
uint32_t
transfer_mode
: 1;
3341
uint32_t
send_auto_stop
: 1;
3342
uint32_t
wait_prvdata_complete
: 1;
3343
uint32_t
stop_abort_cmd
: 1;
3344
uint32_t
send_initialization
: 1;
3345
uint32_t
card_number
: 5;
3346
uint32_t
update_clock_registers_only
: 1;
3347
uint32_t
read_ceata_device
: 1;
3348
uint32_t
ccs_expected
: 1;
3349
uint32_t
enable_boot
: 1;
3350
uint32_t
expect_boot_ack
: 1;
3351
uint32_t
disable_boot
: 1;
3352
uint32_t
boot_mode
: 1;
3353
uint32_t
volt_switch
: 1;
3354
uint32_t
use_hold_reg
: 1;
3355
uint32_t : 1;
3356
uint32_t
start_cmd
: 1;
3357
};
3358
3360
typedef
volatile
struct
ALT_SDMMC_CMD_s
ALT_SDMMC_CMD_t
;
3361
#endif
/* __ASSEMBLY__ */
3362
3364
#define ALT_SDMMC_CMD_OFST 0x2c
3365
3387
#define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3388
3389
#define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3390
3391
#define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3392
3393
#define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3394
3395
#define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3396
3397
#define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3398
3399
#define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3400
3401
#define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3402
3403
#ifndef __ASSEMBLY__
3404
3414
struct
ALT_SDMMC_RESP0_s
3415
{
3416
const
uint32_t
response0
: 32;
3417
};
3418
3420
typedef
volatile
struct
ALT_SDMMC_RESP0_s
ALT_SDMMC_RESP0_t
;
3421
#endif
/* __ASSEMBLY__ */
3422
3424
#define ALT_SDMMC_RESP0_OFST 0x30
3425
3448
#define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3449
3450
#define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3451
3452
#define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3453
3454
#define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3455
3456
#define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3457
3458
#define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3459
3460
#define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3461
3462
#define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3463
3464
#ifndef __ASSEMBLY__
3465
3475
struct
ALT_SDMMC_RESP1_s
3476
{
3477
const
uint32_t
response1
: 32;
3478
};
3479
3481
typedef
volatile
struct
ALT_SDMMC_RESP1_s
ALT_SDMMC_RESP1_t
;
3482
#endif
/* __ASSEMBLY__ */
3483
3485
#define ALT_SDMMC_RESP1_OFST 0x34
3486
3506
#define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3507
3508
#define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3509
3510
#define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3511
3512
#define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3513
3514
#define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3515
3516
#define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3517
3518
#define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3519
3520
#define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3521
3522
#ifndef __ASSEMBLY__
3523
3533
struct
ALT_SDMMC_RESP2_s
3534
{
3535
const
uint32_t
response2
: 32;
3536
};
3537
3539
typedef
volatile
struct
ALT_SDMMC_RESP2_s
ALT_SDMMC_RESP2_t
;
3540
#endif
/* __ASSEMBLY__ */
3541
3543
#define ALT_SDMMC_RESP2_OFST 0x38
3544
3564
#define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
3565
3566
#define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
3567
3568
#define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
3569
3570
#define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
3571
3572
#define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
3573
3574
#define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
3575
3576
#define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
3577
3578
#define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
3579
3580
#ifndef __ASSEMBLY__
3581
3591
struct
ALT_SDMMC_RESP3_s
3592
{
3593
const
uint32_t
response3
: 32;
3594
};
3595
3597
typedef
volatile
struct
ALT_SDMMC_RESP3_s
ALT_SDMMC_RESP3_t
;
3598
#endif
/* __ASSEMBLY__ */
3599
3601
#define ALT_SDMMC_RESP3_OFST 0x3c
3602
3652
#define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
3653
3658
#define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
3659
3661
#define ALT_SDMMC_MINTSTS_CD_LSB 0
3662
3663
#define ALT_SDMMC_MINTSTS_CD_MSB 0
3664
3665
#define ALT_SDMMC_MINTSTS_CD_WIDTH 1
3666
3667
#define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
3668
3669
#define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
3670
3671
#define ALT_SDMMC_MINTSTS_CD_RESET 0x0
3672
3673
#define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
3674
3675
#define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
3676
3697
#define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
3698
3703
#define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
3704
3706
#define ALT_SDMMC_MINTSTS_RESP_LSB 1
3707
3708
#define ALT_SDMMC_MINTSTS_RESP_MSB 1
3709
3710
#define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
3711
3712
#define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
3713
3714
#define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
3715
3716
#define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
3717
3718
#define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
3719
3720
#define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
3721
3742
#define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
3743
3748
#define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
3749
3751
#define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
3752
3753
#define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
3754
3755
#define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
3756
3757
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
3758
3759
#define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
3760
3761
#define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
3762
3763
#define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
3764
3765
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
3766
3787
#define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
3788
3793
#define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
3794
3796
#define ALT_SDMMC_MINTSTS_DT_LSB 3
3797
3798
#define ALT_SDMMC_MINTSTS_DT_MSB 3
3799
3800
#define ALT_SDMMC_MINTSTS_DT_WIDTH 1
3801
3802
#define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
3803
3804
#define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
3805
3806
#define ALT_SDMMC_MINTSTS_DT_RESET 0x0
3807
3808
#define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
3809
3810
#define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
3811
3832
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
3833
3838
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
3839
3841
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
3842
3843
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
3844
3845
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
3846
3847
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
3848
3849
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
3850
3851
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
3852
3853
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
3854
3855
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
3856
3877
#define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
3878
3883
#define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
3884
3886
#define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
3887
3888
#define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
3889
3890
#define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
3891
3892
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
3893
3894
#define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
3895
3896
#define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
3897
3898
#define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
3899
3900
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
3901
3922
#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
3923
3928
#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
3929
3931
#define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
3932
3933
#define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
3934
3935
#define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
3936
3937
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
3938
3939
#define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
3940
3941
#define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
3942
3943
#define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
3944
3945
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
3946
3967
#define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
3968
3973
#define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
3974
3976
#define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
3977
3978
#define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
3979
3980
#define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
3981
3982
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
3983
3984
#define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
3985
3986
#define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
3987
3988
#define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
3989
3990
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
3991
4012
#define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4013
4018
#define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4019
4021
#define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4022
4023
#define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4024
4025
#define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4026
4027
#define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4028
4029
#define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4030
4031
#define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4032
4033
#define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4034
4035
#define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4036
4057
#define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4058
4063
#define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4064
4066
#define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4067
4068
#define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4069
4070
#define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4071
4072
#define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4073
4074
#define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4075
4076
#define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4077
4078
#define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4079
4080
#define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4081
4102
#define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4103
4108
#define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4109
4111
#define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4112
4113
#define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4114
4115
#define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4116
4117
#define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4118
4119
#define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4120
4121
#define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4122
4123
#define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4124
4125
#define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4126
4147
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4148
4153
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4154
4156
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4157
4158
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4159
4160
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4161
4162
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4163
4164
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4165
4166
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4167
4168
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4169
4170
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4171
4192
#define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4193
4198
#define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4199
4201
#define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4202
4203
#define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4204
4205
#define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4206
4207
#define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4208
4209
#define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4210
4211
#define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4212
4213
#define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4214
4215
#define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4216
4237
#define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4238
4243
#define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4244
4246
#define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4247
4248
#define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4249
4250
#define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4251
4252
#define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4253
4254
#define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4255
4256
#define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4257
4258
#define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4259
4260
#define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4261
4282
#define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4283
4288
#define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4289
4291
#define ALT_SDMMC_MINTSTS_ACD_LSB 14
4292
4293
#define ALT_SDMMC_MINTSTS_ACD_MSB 14
4294
4295
#define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4296
4297
#define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4298
4299
#define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4300
4301
#define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4302
4303
#define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4304
4305
#define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4306
4327
#define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4328
4333
#define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4334
4336
#define ALT_SDMMC_MINTSTS_EBE_LSB 15
4337
4338
#define ALT_SDMMC_MINTSTS_EBE_MSB 15
4339
4340
#define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4341
4342
#define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4343
4344
#define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4345
4346
#define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4347
4348
#define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4349
4350
#define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4351
4375
#define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4376
4381
#define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4382
4384
#define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4385
4386
#define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 16
4387
4388
#define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 1
4389
4390
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0x00010000
4391
4392
#define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
4393
4394
#define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4395
4396
#define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
4397
4398
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
4399
4400
#ifndef __ASSEMBLY__
4401
4411
struct
ALT_SDMMC_MINTSTS_s
4412
{
4413
const
uint32_t
cd
: 1;
4414
const
uint32_t
resp
: 1;
4415
const
uint32_t
cmd_done
: 1;
4416
const
uint32_t
dt
: 1;
4417
const
uint32_t
dttxfifodr
: 1;
4418
const
uint32_t
rxfifodr
: 1;
4419
const
uint32_t
respcrcerr
: 1;
4420
const
uint32_t
datacrcerr
: 1;
4421
const
uint32_t
respto
: 1;
4422
const
uint32_t
datardto
: 1;
4423
const
uint32_t
dshto
: 1;
4424
const
uint32_t
fifoovunerr
: 1;
4425
const
uint32_t
hlwerr
: 1;
4426
const
uint32_t
strerr
: 1;
4427
const
uint32_t
acd
: 1;
4428
const
uint32_t
ebe
: 1;
4429
const
uint32_t
sdio_interrupt
: 1;
4430
uint32_t : 15;
4431
};
4432
4434
typedef
volatile
struct
ALT_SDMMC_MINTSTS_s
ALT_SDMMC_MINTSTS_t
;
4435
#endif
/* __ASSEMBLY__ */
4436
4438
#define ALT_SDMMC_MINTSTS_OFST 0x40
4439
4490
#define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4491
4496
#define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4497
4499
#define ALT_SDMMC_RINTSTS_CD_LSB 0
4500
4501
#define ALT_SDMMC_RINTSTS_CD_MSB 0
4502
4503
#define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4504
4505
#define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4506
4507
#define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4508
4509
#define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4510
4511
#define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4512
4513
#define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4514
4536
#define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4537
4542
#define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4543
4545
#define ALT_SDMMC_RINTSTS_RE_LSB 1
4546
4547
#define ALT_SDMMC_RINTSTS_RE_MSB 1
4548
4549
#define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4550
4551
#define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4552
4553
#define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4554
4555
#define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4556
4557
#define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
4558
4559
#define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
4560
4582
#define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
4583
4588
#define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
4589
4591
#define ALT_SDMMC_RINTSTS_CMD_LSB 2
4592
4593
#define ALT_SDMMC_RINTSTS_CMD_MSB 2
4594
4595
#define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
4596
4597
#define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
4598
4599
#define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
4600
4601
#define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
4602
4603
#define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
4604
4605
#define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
4606
4628
#define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
4629
4634
#define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
4635
4637
#define ALT_SDMMC_RINTSTS_DTO_LSB 3
4638
4639
#define ALT_SDMMC_RINTSTS_DTO_MSB 3
4640
4641
#define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
4642
4643
#define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
4644
4645
#define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
4646
4647
#define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
4648
4649
#define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
4650
4651
#define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
4652
4674
#define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
4675
4680
#define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
4681
4683
#define ALT_SDMMC_RINTSTS_TXDR_LSB 4
4684
4685
#define ALT_SDMMC_RINTSTS_TXDR_MSB 4
4686
4687
#define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
4688
4689
#define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
4690
4691
#define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
4692
4693
#define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
4694
4695
#define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
4696
4697
#define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
4698
4720
#define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
4721
4726
#define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
4727
4729
#define ALT_SDMMC_RINTSTS_RXDR_LSB 5
4730
4731
#define ALT_SDMMC_RINTSTS_RXDR_MSB 5
4732
4733
#define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
4734
4735
#define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
4736
4737
#define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
4738
4739
#define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
4740
4741
#define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
4742
4743
#define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
4744
4766
#define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
4767
4772
#define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
4773
4775
#define ALT_SDMMC_RINTSTS_RCRC_LSB 6
4776
4777
#define ALT_SDMMC_RINTSTS_RCRC_MSB 6
4778
4779
#define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
4780
4781
#define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
4782
4783
#define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
4784
4785
#define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
4786
4787
#define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
4788
4789
#define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
4790
4812
#define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
4813
4818
#define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
4819
4821
#define ALT_SDMMC_RINTSTS_DCRC_LSB 7
4822
4823
#define ALT_SDMMC_RINTSTS_DCRC_MSB 7
4824
4825
#define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
4826
4827
#define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
4828
4829
#define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
4830
4831
#define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
4832
4833
#define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
4834
4835
#define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
4836
4859
#define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
4860
4865
#define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
4866
4868
#define ALT_SDMMC_RINTSTS_BAR_LSB 8
4869
4870
#define ALT_SDMMC_RINTSTS_BAR_MSB 8
4871
4872
#define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
4873
4874
#define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
4875
4876
#define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
4877
4878
#define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
4879
4880
#define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
4881
4882
#define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
4883
4906
#define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
4907
4912
#define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
4913
4915
#define ALT_SDMMC_RINTSTS_BDS_LSB 9
4916
4917
#define ALT_SDMMC_RINTSTS_BDS_MSB 9
4918
4919
#define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
4920
4921
#define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
4922
4923
#define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
4924
4925
#define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
4926
4927
#define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
4928
4929
#define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
4930
4954
#define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
4955
4960
#define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
4961
4963
#define ALT_SDMMC_RINTSTS_HTO_LSB 10
4964
4965
#define ALT_SDMMC_RINTSTS_HTO_MSB 10
4966
4967
#define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
4968
4969
#define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
4970
4971
#define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
4972
4973
#define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
4974
4975
#define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
4976
4977
#define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
4978
5000
#define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5001
5006
#define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5007
5009
#define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5010
5011
#define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5012
5013
#define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5014
5015
#define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5016
5017
#define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5018
5019
#define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5020
5021
#define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5022
5023
#define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5024
5046
#define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5047
5052
#define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5053
5055
#define ALT_SDMMC_RINTSTS_HLE_LSB 12
5056
5057
#define ALT_SDMMC_RINTSTS_HLE_MSB 12
5058
5059
#define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5060
5061
#define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5062
5063
#define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5064
5065
#define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5066
5067
#define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5068
5069
#define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5070
5092
#define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5093
5098
#define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5099
5101
#define ALT_SDMMC_RINTSTS_SBE_LSB 13
5102
5103
#define ALT_SDMMC_RINTSTS_SBE_MSB 13
5104
5105
#define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5106
5107
#define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5108
5109
#define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5110
5111
#define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5112
5113
#define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5114
5115
#define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5116
5138
#define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5139
5144
#define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5145
5147
#define ALT_SDMMC_RINTSTS_ACD_LSB 14
5148
5149
#define ALT_SDMMC_RINTSTS_ACD_MSB 14
5150
5151
#define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5152
5153
#define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5154
5155
#define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5156
5157
#define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5158
5159
#define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5160
5161
#define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5162
5184
#define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5185
5190
#define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5191
5193
#define ALT_SDMMC_RINTSTS_EBE_LSB 15
5194
5195
#define ALT_SDMMC_RINTSTS_EBE_MSB 15
5196
5197
#define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5198
5199
#define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5200
5201
#define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5202
5203
#define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5204
5205
#define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5206
5207
#define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5208
5229
#define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5230
5235
#define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5236
5238
#define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5239
5240
#define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 16
5241
5242
#define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 1
5243
5244
#define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0x00010000
5245
5246
#define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0xfffeffff
5247
5248
#define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5249
5250
#define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0x00010000) >> 16)
5251
5252
#define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0x00010000)
5253
5254
#ifndef __ASSEMBLY__
5255
5265
struct
ALT_SDMMC_RINTSTS_s
5266
{
5267
uint32_t
cd
: 1;
5268
uint32_t
re
: 1;
5269
uint32_t
cmd
: 1;
5270
uint32_t
dto
: 1;
5271
uint32_t
txdr
: 1;
5272
uint32_t
rxdr
: 1;
5273
uint32_t
rcrc
: 1;
5274
uint32_t
dcrc
: 1;
5275
uint32_t
bar
: 1;
5276
uint32_t
bds
: 1;
5277
uint32_t
hto
: 1;
5278
uint32_t
frun
: 1;
5279
uint32_t
hle
: 1;
5280
uint32_t
sbe
: 1;
5281
uint32_t
acd
: 1;
5282
uint32_t
ebe
: 1;
5283
uint32_t
sdio_interrupt
: 1;
5284
uint32_t : 15;
5285
};
5286
5288
typedef
volatile
struct
ALT_SDMMC_RINTSTS_s
ALT_SDMMC_RINTSTS_t
;
5289
#endif
/* __ASSEMBLY__ */
5290
5292
#define ALT_SDMMC_RINTSTS_OFST 0x44
5293
5337
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5338
5343
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5344
5346
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5347
5348
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5349
5350
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5351
5352
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5353
5354
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5355
5356
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5357
5358
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5359
5360
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5361
5383
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5384
5389
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5390
5392
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5393
5394
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5395
5396
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5397
5398
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5399
5400
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5401
5402
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5403
5404
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5405
5406
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5407
5428
#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5429
5434
#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5435
5437
#define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5438
5439
#define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5440
5441
#define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5442
5443
#define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5444
5445
#define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5446
5447
#define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5448
5449
#define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5450
5451
#define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5452
5473
#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x0
5474
5479
#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x1
5480
5482
#define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5483
5484
#define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5485
5486
#define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5487
5488
#define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5489
5490
#define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5491
5492
#define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5493
5494
#define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5495
5496
#define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
5497
5532
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
5533
5538
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
5539
5544
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
5545
5550
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
5551
5556
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
5557
5562
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
5563
5568
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
5569
5574
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
5575
5580
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
5581
5586
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
5587
5592
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
5593
5598
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
5599
5604
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
5605
5610
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
5611
5616
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
5617
5622
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
5623
5625
#define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
5626
5627
#define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
5628
5629
#define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
5630
5631
#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
5632
5633
#define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
5634
5635
#define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
5636
5637
#define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
5638
5639
#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
5640
5662
#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
5663
5668
#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
5669
5671
#define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
5672
5673
#define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
5674
5675
#define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
5676
5677
#define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
5678
5679
#define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
5680
5681
#define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
5682
5683
#define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
5684
5685
#define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
5686
5708
#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
5709
5714
#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
5715
5717
#define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
5718
5719
#define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
5720
5721
#define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
5722
5723
#define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
5724
5725
#define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
5726
5727
#define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
5728
5729
#define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
5730
5731
#define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
5732
5753
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
5754
5759
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
5760
5762
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
5763
5764
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
5765
5766
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
5767
5768
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
5769
5770
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
5771
5772
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
5773
5774
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
5775
5776
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
5777
5787
#define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
5788
5789
#define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
5790
5791
#define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
5792
5793
#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
5794
5795
#define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
5796
5797
#define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
5798
5799
#define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
5800
5801
#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
5802
5812
#define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
5813
5814
#define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
5815
5816
#define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
5817
5818
#define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
5819
5820
#define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
5821
5822
#define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
5823
5824
#define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
5825
5826
#define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
5827
5828
#ifndef __ASSEMBLY__
5829
5839
struct
ALT_SDMMC_STAT_s
5840
{
5841
const
uint32_t
fifo_rx_watermark
: 1;
5842
const
uint32_t
fifo_tx_watermark
: 1;
5843
const
uint32_t
fifo_empty
: 1;
5844
const
uint32_t
fifo_full
: 1;
5845
const
uint32_t
command_fsm_states
: 4;
5846
const
uint32_t
data_3_status
: 1;
5847
const
uint32_t
data_busy
: 1;
5848
const
uint32_t
data_state_mc_busy
: 1;
5849
const
uint32_t
response_index
: 6;
5850
const
uint32_t
fifo_count
: 13;
5851
uint32_t : 2;
5852
};
5853
5855
typedef
volatile
struct
ALT_SDMMC_STAT_s
ALT_SDMMC_STAT_t
;
5856
#endif
/* __ASSEMBLY__ */
5857
5859
#define ALT_SDMMC_STAT_OFST 0x48
5860
5900
#define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
5901
5902
#define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
5903
5904
#define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
5905
5906
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
5907
5908
#define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
5909
5910
#define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
5911
5912
#define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
5913
5914
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
5915
5945
#define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
5946
5947
#define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
5948
5949
#define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
5950
5951
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
5952
5953
#define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
5954
5955
#define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
5956
5957
#define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
5958
5959
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
5960
5991
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
5992
5997
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
5998
6003
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6004
6009
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6010
6015
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6016
6021
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6022
6027
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6028
6030
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6031
6032
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6033
6034
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6035
6036
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6037
6038
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6039
6040
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6041
6042
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6043
6044
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6045
6046
#ifndef __ASSEMBLY__
6047
6057
struct
ALT_SDMMC_FIFOTH_s
6058
{
6059
uint32_t
tx_wmark
: 12;
6060
uint32_t : 4;
6061
uint32_t
rx_wmark
: 12;
6062
uint32_t
dw_dma_multiple_transaction_size
: 3;
6063
uint32_t : 1;
6064
};
6065
6067
typedef
volatile
struct
ALT_SDMMC_FIFOTH_s
ALT_SDMMC_FIFOTH_t
;
6068
#endif
/* __ASSEMBLY__ */
6069
6071
#define ALT_SDMMC_FIFOTH_OFST 0x4c
6072
6106
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6107
6112
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6113
6115
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6116
6117
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6118
6119
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6120
6121
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6122
6123
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6124
6125
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6126
6127
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6128
6129
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6130
6131
#ifndef __ASSEMBLY__
6132
6142
struct
ALT_SDMMC_CDETECT_s
6143
{
6144
const
uint32_t
card_detect_n
: 1;
6145
uint32_t : 31;
6146
};
6147
6149
typedef
volatile
struct
ALT_SDMMC_CDETECT_s
ALT_SDMMC_CDETECT_t
;
6150
#endif
/* __ASSEMBLY__ */
6151
6153
#define ALT_SDMMC_CDETECT_OFST 0x50
6154
6188
#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6189
6194
#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6195
6197
#define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6198
6199
#define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6200
6201
#define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6202
6203
#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6204
6205
#define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6206
6207
#define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6208
6209
#define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6210
6211
#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6212
6213
#ifndef __ASSEMBLY__
6214
6224
struct
ALT_SDMMC_WRTPRT_s
6225
{
6226
const
uint32_t
write_protect
: 1;
6227
uint32_t : 31;
6228
};
6229
6231
typedef
volatile
struct
ALT_SDMMC_WRTPRT_s
ALT_SDMMC_WRTPRT_t
;
6232
#endif
/* __ASSEMBLY__ */
6233
6235
#define ALT_SDMMC_WRTPRT_OFST 0x54
6236
6256
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
6257
6258
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
6259
6260
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
6261
6262
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
6263
6264
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
6265
6266
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
6267
6268
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6269
6270
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6271
6272
#ifndef __ASSEMBLY__
6273
6283
struct
ALT_SDMMC_TCBCNT_s
6284
{
6285
const
uint32_t
trans_card_byte_count
: 32;
6286
};
6287
6289
typedef
volatile
struct
ALT_SDMMC_TCBCNT_s
ALT_SDMMC_TCBCNT_t
;
6290
#endif
/* __ASSEMBLY__ */
6291
6293
#define ALT_SDMMC_TCBCNT_OFST 0x5c
6294
6318
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
6319
6320
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
6321
6322
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
6323
6324
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
6325
6326
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
6327
6328
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
6329
6330
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
6331
6332
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
6333
6334
#ifndef __ASSEMBLY__
6335
6345
struct
ALT_SDMMC_TBBCNT_s
6346
{
6347
const
uint32_t
trans_fifo_byte_count
: 32;
6348
};
6349
6351
typedef
volatile
struct
ALT_SDMMC_TBBCNT_s
ALT_SDMMC_TBBCNT_t
;
6352
#endif
/* __ASSEMBLY__ */
6353
6355
#define ALT_SDMMC_TBBCNT_OFST 0x60
6356
6378
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
6379
6380
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
6381
6382
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
6383
6384
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
6385
6386
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
6387
6388
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
6389
6390
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
6391
6392
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
6393
6394
#ifndef __ASSEMBLY__
6395
6405
struct
ALT_SDMMC_DEBNCE_s
6406
{
6407
uint32_t
debounce_count
: 24;
6408
uint32_t : 8;
6409
};
6410
6412
typedef
volatile
struct
ALT_SDMMC_DEBNCE_s
ALT_SDMMC_DEBNCE_t
;
6413
#endif
/* __ASSEMBLY__ */
6414
6416
#define ALT_SDMMC_DEBNCE_OFST 0x64
6417
6437
#define ALT_SDMMC_USRID_USR_ID_LSB 0
6438
6439
#define ALT_SDMMC_USRID_USR_ID_MSB 31
6440
6441
#define ALT_SDMMC_USRID_USR_ID_WIDTH 32
6442
6443
#define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
6444
6445
#define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
6446
6447
#define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
6448
6449
#define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
6450
6451
#define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
6452
6453
#ifndef __ASSEMBLY__
6454
6464
struct
ALT_SDMMC_USRID_s
6465
{
6466
uint32_t
usr_id
: 32;
6467
};
6468
6470
typedef
volatile
struct
ALT_SDMMC_USRID_s
ALT_SDMMC_USRID_t
;
6471
#endif
/* __ASSEMBLY__ */
6472
6474
#define ALT_SDMMC_USRID_OFST 0x68
6475
6495
#define ALT_SDMMC_VERID_VER_ID_LSB 0
6496
6497
#define ALT_SDMMC_VERID_VER_ID_MSB 31
6498
6499
#define ALT_SDMMC_VERID_VER_ID_WIDTH 32
6500
6501
#define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
6502
6503
#define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
6504
6505
#define ALT_SDMMC_VERID_VER_ID_RESET 0x5342240a
6506
6507
#define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
6508
6509
#define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
6510
6511
#ifndef __ASSEMBLY__
6512
6522
struct
ALT_SDMMC_VERID_s
6523
{
6524
const
uint32_t
ver_id
: 32;
6525
};
6526
6528
typedef
volatile
struct
ALT_SDMMC_VERID_s
ALT_SDMMC_VERID_t
;
6529
#endif
/* __ASSEMBLY__ */
6530
6532
#define ALT_SDMMC_VERID_OFST 0x6c
6533
6578
#define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
6579
6581
#define ALT_SDMMC_HCON_CT_LSB 0
6582
6583
#define ALT_SDMMC_HCON_CT_MSB 0
6584
6585
#define ALT_SDMMC_HCON_CT_WIDTH 1
6586
6587
#define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
6588
6589
#define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
6590
6591
#define ALT_SDMMC_HCON_CT_RESET 0x1
6592
6593
#define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
6594
6595
#define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
6596
6616
#define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
6617
6619
#define ALT_SDMMC_HCON_NC_LSB 1
6620
6621
#define ALT_SDMMC_HCON_NC_MSB 5
6622
6623
#define ALT_SDMMC_HCON_NC_WIDTH 5
6624
6625
#define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
6626
6627
#define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
6628
6629
#define ALT_SDMMC_HCON_NC_RESET 0x0
6630
6631
#define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
6632
6633
#define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
6634
6654
#define ALT_SDMMC_HCON_HBUS_E_APB 0x0
6655
6657
#define ALT_SDMMC_HCON_HBUS_LSB 6
6658
6659
#define ALT_SDMMC_HCON_HBUS_MSB 6
6660
6661
#define ALT_SDMMC_HCON_HBUS_WIDTH 1
6662
6663
#define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
6664
6665
#define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
6666
6667
#define ALT_SDMMC_HCON_HBUS_RESET 0x0
6668
6669
#define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
6670
6671
#define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
6672
6692
#define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
6693
6695
#define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
6696
6697
#define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
6698
6699
#define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
6700
6701
#define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
6702
6703
#define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
6704
6705
#define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
6706
6707
#define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
6708
6709
#define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
6710
6730
#define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
6731
6733
#define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
6734
6735
#define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
6736
6737
#define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
6738
6739
#define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
6740
6741
#define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
6742
6743
#define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
6744
6745
#define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
6746
6747
#define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
6748
6769
#define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
6770
6772
#define ALT_SDMMC_HCON_DMAINTF_LSB 16
6773
6774
#define ALT_SDMMC_HCON_DMAINTF_MSB 17
6775
6776
#define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
6777
6778
#define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
6779
6780
#define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
6781
6782
#define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
6783
6784
#define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
6785
6786
#define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
6787
6808
#define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
6809
6811
#define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
6812
6813
#define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
6814
6815
#define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
6816
6817
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
6818
6819
#define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
6820
6821
#define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
6822
6823
#define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
6824
6825
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
6826
6846
#define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
6847
6849
#define ALT_SDMMC_HCON_RIOS_LSB 21
6850
6851
#define ALT_SDMMC_HCON_RIOS_MSB 21
6852
6853
#define ALT_SDMMC_HCON_RIOS_WIDTH 1
6854
6855
#define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
6856
6857
#define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
6858
6859
#define ALT_SDMMC_HCON_RIOS_RESET 0x0
6860
6861
#define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
6862
6863
#define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
6864
6884
#define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
6885
6887
#define ALT_SDMMC_HCON_IHR_LSB 22
6888
6889
#define ALT_SDMMC_HCON_IHR_MSB 22
6890
6891
#define ALT_SDMMC_HCON_IHR_WIDTH 1
6892
6893
#define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
6894
6895
#define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
6896
6897
#define ALT_SDMMC_HCON_IHR_RESET 0x1
6898
6899
#define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
6900
6901
#define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
6902
6922
#define ALT_SDMMC_HCON_SCFP_E_SET 0x1
6923
6925
#define ALT_SDMMC_HCON_SCFP_LSB 23
6926
6927
#define ALT_SDMMC_HCON_SCFP_MSB 23
6928
6929
#define ALT_SDMMC_HCON_SCFP_WIDTH 1
6930
6931
#define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
6932
6933
#define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
6934
6935
#define ALT_SDMMC_HCON_SCFP_RESET 0x1
6936
6937
#define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
6938
6939
#define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
6940
6960
#define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
6961
6963
#define ALT_SDMMC_HCON_NCD_LSB 24
6964
6965
#define ALT_SDMMC_HCON_NCD_MSB 25
6966
6967
#define ALT_SDMMC_HCON_NCD_WIDTH 2
6968
6969
#define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
6970
6971
#define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
6972
6973
#define ALT_SDMMC_HCON_NCD_RESET 0x0
6974
6975
#define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
6976
6977
#define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
6978
6998
#define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
6999
7001
#define ALT_SDMMC_HCON_ARO_LSB 26
7002
7003
#define ALT_SDMMC_HCON_ARO_MSB 26
7004
7005
#define ALT_SDMMC_HCON_ARO_WIDTH 1
7006
7007
#define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7008
7009
#define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7010
7011
#define ALT_SDMMC_HCON_ARO_RESET 0x0
7012
7013
#define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7014
7015
#define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7016
7017
#ifndef __ASSEMBLY__
7018
7028
struct
ALT_SDMMC_HCON_s
7029
{
7030
const
uint32_t
ct
: 1;
7031
const
uint32_t
nc
: 5;
7032
const
uint32_t
hbus
: 1;
7033
const
uint32_t
hdatawidth
: 3;
7034
const
uint32_t
haddrwidth
: 6;
7035
const
uint32_t
dmaintf
: 2;
7036
const
uint32_t
dmadatawidth
: 3;
7037
const
uint32_t
rios
: 1;
7038
const
uint32_t
ihr
: 1;
7039
const
uint32_t
scfp
: 1;
7040
const
uint32_t
ncd
: 2;
7041
const
uint32_t
aro
: 1;
7042
uint32_t : 5;
7043
};
7044
7046
typedef
volatile
struct
ALT_SDMMC_HCON_s
ALT_SDMMC_HCON_t
;
7047
#endif
/* __ASSEMBLY__ */
7048
7050
#define ALT_SDMMC_HCON_OFST 0x70
7051
7091
#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7092
7097
#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7098
7100
#define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7101
7102
#define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 0
7103
7104
#define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 1
7105
7106
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x00000001
7107
7108
#define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xfffffffe
7109
7110
#define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7111
7112
#define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x00000001) >> 0)
7113
7114
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x00000001)
7115
7136
#define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7137
7142
#define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7143
7145
#define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7146
7147
#define ALT_SDMMC_UHS_REG_DDR_REG_MSB 16
7148
7149
#define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 1
7150
7151
#define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0x00010000
7152
7153
#define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0xfffeffff
7154
7155
#define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7156
7157
#define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0x00010000) >> 16)
7158
7159
#define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0x00010000)
7160
7161
#ifndef __ASSEMBLY__
7162
7172
struct
ALT_SDMMC_UHS_REG_s
7173
{
7174
uint32_t
volt_reg
: 1;
7175
uint32_t : 15;
7176
uint32_t
ddr_reg
: 1;
7177
uint32_t : 15;
7178
};
7179
7181
typedef
volatile
struct
ALT_SDMMC_UHS_REG_s
ALT_SDMMC_UHS_REG_t
;
7182
#endif
/* __ASSEMBLY__ */
7183
7185
#define ALT_SDMMC_UHS_REG_OFST 0x74
7186
7219
#define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
7220
7225
#define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
7226
7228
#define ALT_SDMMC_RST_N_CARD_RST_LSB 0
7229
7230
#define ALT_SDMMC_RST_N_CARD_RST_MSB 0
7231
7232
#define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
7233
7234
#define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
7235
7236
#define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
7237
7238
#define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
7239
7240
#define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
7241
7242
#define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
7243
7244
#ifndef __ASSEMBLY__
7245
7255
struct
ALT_SDMMC_RST_N_s
7256
{
7257
uint32_t
card_reset
: 1;
7258
uint32_t : 31;
7259
};
7260
7262
typedef
volatile
struct
ALT_SDMMC_RST_N_s
ALT_SDMMC_RST_N_t
;
7263
#endif
/* __ASSEMBLY__ */
7264
7266
#define ALT_SDMMC_RST_N_OFST 0x78
7267
7306
#define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
7307
7312
#define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
7313
7315
#define ALT_SDMMC_BMOD_SWR_LSB 0
7316
7317
#define ALT_SDMMC_BMOD_SWR_MSB 0
7318
7319
#define ALT_SDMMC_BMOD_SWR_WIDTH 1
7320
7321
#define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
7322
7323
#define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
7324
7325
#define ALT_SDMMC_BMOD_SWR_RESET 0x0
7326
7327
#define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
7328
7329
#define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
7330
7353
#define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
7354
7359
#define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
7360
7362
#define ALT_SDMMC_BMOD_FB_LSB 1
7363
7364
#define ALT_SDMMC_BMOD_FB_MSB 1
7365
7366
#define ALT_SDMMC_BMOD_FB_WIDTH 1
7367
7368
#define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
7369
7370
#define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
7371
7372
#define ALT_SDMMC_BMOD_FB_RESET 0x0
7373
7374
#define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
7375
7376
#define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
7377
7388
#define ALT_SDMMC_BMOD_DSL_LSB 2
7389
7390
#define ALT_SDMMC_BMOD_DSL_MSB 6
7391
7392
#define ALT_SDMMC_BMOD_DSL_WIDTH 5
7393
7394
#define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
7395
7396
#define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
7397
7398
#define ALT_SDMMC_BMOD_DSL_RESET 0x0
7399
7400
#define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
7401
7402
#define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
7403
7424
#define ALT_SDMMC_BMOD_DE_E_END 0x1
7425
7430
#define ALT_SDMMC_BMOD_DE_E_DISD 0x0
7431
7433
#define ALT_SDMMC_BMOD_DE_LSB 7
7434
7435
#define ALT_SDMMC_BMOD_DE_MSB 7
7436
7437
#define ALT_SDMMC_BMOD_DE_WIDTH 1
7438
7439
#define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
7440
7441
#define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
7442
7443
#define ALT_SDMMC_BMOD_DE_RESET 0x0
7444
7445
#define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
7446
7447
#define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
7448
7479
#define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
7480
7485
#define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
7486
7491
#define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
7492
7497
#define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
7498
7503
#define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
7504
7509
#define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
7510
7515
#define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
7516
7521
#define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
7522
7524
#define ALT_SDMMC_BMOD_PBL_LSB 8
7525
7526
#define ALT_SDMMC_BMOD_PBL_MSB 10
7527
7528
#define ALT_SDMMC_BMOD_PBL_WIDTH 3
7529
7530
#define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
7531
7532
#define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
7533
7534
#define ALT_SDMMC_BMOD_PBL_RESET 0x0
7535
7536
#define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
7537
7538
#define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
7539
7540
#ifndef __ASSEMBLY__
7541
7551
struct
ALT_SDMMC_BMOD_s
7552
{
7553
uint32_t
swr
: 1;
7554
uint32_t
fb
: 1;
7555
uint32_t
dsl
: 5;
7556
uint32_t
de
: 1;
7557
const
uint32_t
pbl
: 3;
7558
uint32_t : 21;
7559
};
7560
7562
typedef
volatile
struct
ALT_SDMMC_BMOD_s
ALT_SDMMC_BMOD_t
;
7563
#endif
/* __ASSEMBLY__ */
7564
7566
#define ALT_SDMMC_BMOD_OFST 0x80
7567
7591
#define ALT_SDMMC_PLDMND_PD_LSB 0
7592
7593
#define ALT_SDMMC_PLDMND_PD_MSB 31
7594
7595
#define ALT_SDMMC_PLDMND_PD_WIDTH 32
7596
7597
#define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
7598
7599
#define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
7600
7601
#define ALT_SDMMC_PLDMND_PD_RESET 0x0
7602
7603
#define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
7604
7605
#define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
7606
7607
#ifndef __ASSEMBLY__
7608
7618
struct
ALT_SDMMC_PLDMND_s
7619
{
7620
uint32_t
pd
: 32;
7621
};
7622
7624
typedef
volatile
struct
ALT_SDMMC_PLDMND_s
ALT_SDMMC_PLDMND_t
;
7625
#endif
/* __ASSEMBLY__ */
7626
7628
#define ALT_SDMMC_PLDMND_OFST 0x84
7629
7653
#define ALT_SDMMC_DBADDR_SDL_LSB 2
7654
7655
#define ALT_SDMMC_DBADDR_SDL_MSB 31
7656
7657
#define ALT_SDMMC_DBADDR_SDL_WIDTH 30
7658
7659
#define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xfffffffc
7660
7661
#define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000003
7662
7663
#define ALT_SDMMC_DBADDR_SDL_RESET 0x0
7664
7665
#define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xfffffffc) >> 2)
7666
7667
#define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 2) & 0xfffffffc)
7668
7669
#ifndef __ASSEMBLY__
7670
7680
struct
ALT_SDMMC_DBADDR_s
7681
{
7682
uint32_t : 2;
7683
uint32_t
sdl
: 30;
7684
};
7685
7687
typedef
volatile
struct
ALT_SDMMC_DBADDR_s
ALT_SDMMC_DBADDR_t
;
7688
#endif
/* __ASSEMBLY__ */
7689
7691
#define ALT_SDMMC_DBADDR_OFST 0x88
7692
7736
#define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
7737
7742
#define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
7743
7745
#define ALT_SDMMC_IDSTS_TI_LSB 0
7746
7747
#define ALT_SDMMC_IDSTS_TI_MSB 0
7748
7749
#define ALT_SDMMC_IDSTS_TI_WIDTH 1
7750
7751
#define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
7752
7753
#define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
7754
7755
#define ALT_SDMMC_IDSTS_TI_RESET 0x0
7756
7757
#define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
7758
7759
#define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
7760
7781
#define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
7782
7787
#define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
7788
7790
#define ALT_SDMMC_IDSTS_RI_LSB 1
7791
7792
#define ALT_SDMMC_IDSTS_RI_MSB 1
7793
7794
#define ALT_SDMMC_IDSTS_RI_WIDTH 1
7795
7796
#define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
7797
7798
#define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
7799
7800
#define ALT_SDMMC_IDSTS_RI_RESET 0x0
7801
7802
#define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
7803
7804
#define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
7805
7827
#define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
7828
7833
#define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
7834
7836
#define ALT_SDMMC_IDSTS_FBE_LSB 2
7837
7838
#define ALT_SDMMC_IDSTS_FBE_MSB 2
7839
7840
#define ALT_SDMMC_IDSTS_FBE_WIDTH 1
7841
7842
#define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
7843
7844
#define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
7845
7846
#define ALT_SDMMC_IDSTS_FBE_RESET 0x0
7847
7848
#define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
7849
7850
#define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
7851
7875
#define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
7876
7881
#define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
7882
7884
#define ALT_SDMMC_IDSTS_DU_LSB 4
7885
7886
#define ALT_SDMMC_IDSTS_DU_MSB 4
7887
7888
#define ALT_SDMMC_IDSTS_DU_WIDTH 1
7889
7890
#define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
7891
7892
#define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
7893
7894
#define ALT_SDMMC_IDSTS_DU_RESET 0x0
7895
7896
#define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
7897
7898
#define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
7899
7935
#define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
7936
7941
#define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
7942
7944
#define ALT_SDMMC_IDSTS_CES_LSB 5
7945
7946
#define ALT_SDMMC_IDSTS_CES_MSB 5
7947
7948
#define ALT_SDMMC_IDSTS_CES_WIDTH 1
7949
7950
#define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
7951
7952
#define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
7953
7954
#define ALT_SDMMC_IDSTS_CES_RESET 0x0
7955
7956
#define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
7957
7958
#define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
7959
7987
#define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
7988
7993
#define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
7994
7996
#define ALT_SDMMC_IDSTS_NIS_LSB 8
7997
7998
#define ALT_SDMMC_IDSTS_NIS_MSB 8
7999
8000
#define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8001
8002
#define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8003
8004
#define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8005
8006
#define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8007
8008
#define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8009
8010
#define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8011
8041
#define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8042
8047
#define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8048
8050
#define ALT_SDMMC_IDSTS_AIS_LSB 9
8051
8052
#define ALT_SDMMC_IDSTS_AIS_MSB 9
8053
8054
#define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8055
8056
#define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8057
8058
#define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8059
8060
#define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8061
8062
#define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8063
8064
#define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
8065
8087
#define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
8088
8093
#define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
8094
8096
#define ALT_SDMMC_IDSTS_EB_LSB 10
8097
8098
#define ALT_SDMMC_IDSTS_EB_MSB 12
8099
8100
#define ALT_SDMMC_IDSTS_EB_WIDTH 3
8101
8102
#define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
8103
8104
#define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
8105
8106
#define ALT_SDMMC_IDSTS_EB_RESET 0x0
8107
8108
#define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
8109
8110
#define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
8111
8139
#define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
8140
8145
#define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
8146
8151
#define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
8152
8157
#define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
8158
8163
#define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
8164
8169
#define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
8170
8175
#define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
8176
8181
#define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
8182
8187
#define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
8188
8190
#define ALT_SDMMC_IDSTS_FSM_LSB 13
8191
8192
#define ALT_SDMMC_IDSTS_FSM_MSB 16
8193
8194
#define ALT_SDMMC_IDSTS_FSM_WIDTH 4
8195
8196
#define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
8197
8198
#define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
8199
8200
#define ALT_SDMMC_IDSTS_FSM_RESET 0x0
8201
8202
#define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
8203
8204
#define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
8205
8206
#ifndef __ASSEMBLY__
8207
8217
struct
ALT_SDMMC_IDSTS_s
8218
{
8219
uint32_t
ti
: 1;
8220
uint32_t
ri
: 1;
8221
uint32_t
fbe
: 1;
8222
uint32_t : 1;
8223
uint32_t
du
: 1;
8224
uint32_t
ces
: 1;
8225
uint32_t : 2;
8226
uint32_t
nis
: 1;
8227
uint32_t
ais
: 1;
8228
const
uint32_t
eb
: 3;
8229
const
uint32_t
fsm
: 4;
8230
uint32_t : 15;
8231
};
8232
8234
typedef
volatile
struct
ALT_SDMMC_IDSTS_s
ALT_SDMMC_IDSTS_t
;
8235
#endif
/* __ASSEMBLY__ */
8236
8238
#define ALT_SDMMC_IDSTS_OFST 0x8c
8239
8282
#define ALT_SDMMC_IDINTEN_TI_E_END 0x1
8283
8288
#define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
8289
8291
#define ALT_SDMMC_IDINTEN_TI_LSB 0
8292
8293
#define ALT_SDMMC_IDINTEN_TI_MSB 0
8294
8295
#define ALT_SDMMC_IDINTEN_TI_WIDTH 1
8296
8297
#define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
8298
8299
#define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
8300
8301
#define ALT_SDMMC_IDINTEN_TI_RESET 0x0
8302
8303
#define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
8304
8305
#define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
8306
8328
#define ALT_SDMMC_IDINTEN_RI_E_END 0x1
8329
8334
#define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
8335
8337
#define ALT_SDMMC_IDINTEN_RI_LSB 1
8338
8339
#define ALT_SDMMC_IDINTEN_RI_MSB 1
8340
8341
#define ALT_SDMMC_IDINTEN_RI_WIDTH 1
8342
8343
#define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
8344
8345
#define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
8346
8347
#define ALT_SDMMC_IDINTEN_RI_RESET 0x0
8348
8349
#define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
8350
8351
#define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
8352
8374
#define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
8375
8380
#define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
8381
8383
#define ALT_SDMMC_IDINTEN_FBE_LSB 2
8384
8385
#define ALT_SDMMC_IDINTEN_FBE_MSB 2
8386
8387
#define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
8388
8389
#define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
8390
8391
#define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
8392
8393
#define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
8394
8395
#define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
8396
8397
#define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
8398
8420
#define ALT_SDMMC_IDINTEN_DU_E_END 0x1
8421
8426
#define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
8427
8429
#define ALT_SDMMC_IDINTEN_DU_LSB 4
8430
8431
#define ALT_SDMMC_IDINTEN_DU_MSB 4
8432
8433
#define ALT_SDMMC_IDINTEN_DU_WIDTH 1
8434
8435
#define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
8436
8437
#define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
8438
8439
#define ALT_SDMMC_IDINTEN_DU_RESET 0x0
8440
8441
#define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
8442
8443
#define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
8444
8465
#define ALT_SDMMC_IDINTEN_CES_E_END 0x1
8466
8471
#define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
8472
8474
#define ALT_SDMMC_IDINTEN_CES_LSB 5
8475
8476
#define ALT_SDMMC_IDINTEN_CES_MSB 5
8477
8478
#define ALT_SDMMC_IDINTEN_CES_WIDTH 1
8479
8480
#define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
8481
8482
#define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
8483
8484
#define ALT_SDMMC_IDINTEN_CES_RESET 0x0
8485
8486
#define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
8487
8488
#define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
8489
8510
#define ALT_SDMMC_IDINTEN_NI_E_END 0x1
8511
8516
#define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
8517
8519
#define ALT_SDMMC_IDINTEN_NI_LSB 8
8520
8521
#define ALT_SDMMC_IDINTEN_NI_MSB 8
8522
8523
#define ALT_SDMMC_IDINTEN_NI_WIDTH 1
8524
8525
#define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
8526
8527
#define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
8528
8529
#define ALT_SDMMC_IDINTEN_NI_RESET 0x0
8530
8531
#define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
8532
8533
#define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
8534
8561
#define ALT_SDMMC_IDINTEN_AI_E_END 0x1
8562
8567
#define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
8568
8570
#define ALT_SDMMC_IDINTEN_AI_LSB 9
8571
8572
#define ALT_SDMMC_IDINTEN_AI_MSB 9
8573
8574
#define ALT_SDMMC_IDINTEN_AI_WIDTH 1
8575
8576
#define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
8577
8578
#define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
8579
8580
#define ALT_SDMMC_IDINTEN_AI_RESET 0x0
8581
8582
#define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
8583
8584
#define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
8585
8586
#ifndef __ASSEMBLY__
8587
8597
struct
ALT_SDMMC_IDINTEN_s
8598
{
8599
uint32_t
ti
: 1;
8600
uint32_t
ri
: 1;
8601
uint32_t
fbe
: 1;
8602
uint32_t : 1;
8603
uint32_t
du
: 1;
8604
uint32_t
ces
: 1;
8605
uint32_t : 2;
8606
uint32_t
ni
: 1;
8607
uint32_t
ai
: 1;
8608
uint32_t : 22;
8609
};
8610
8612
typedef
volatile
struct
ALT_SDMMC_IDINTEN_s
ALT_SDMMC_IDINTEN_t
;
8613
#endif
/* __ASSEMBLY__ */
8614
8616
#define ALT_SDMMC_IDINTEN_OFST 0x90
8617
8640
#define ALT_SDMMC_DSCADDR_HDA_LSB 0
8641
8642
#define ALT_SDMMC_DSCADDR_HDA_MSB 31
8643
8644
#define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
8645
8646
#define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
8647
8648
#define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
8649
8650
#define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
8651
8652
#define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
8653
8654
#define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
8655
8656
#ifndef __ASSEMBLY__
8657
8667
struct
ALT_SDMMC_DSCADDR_s
8668
{
8669
const
uint32_t
hda
: 32;
8670
};
8671
8673
typedef
volatile
struct
ALT_SDMMC_DSCADDR_s
ALT_SDMMC_DSCADDR_t
;
8674
#endif
/* __ASSEMBLY__ */
8675
8677
#define ALT_SDMMC_DSCADDR_OFST 0x94
8678
8701
#define ALT_SDMMC_BUFADDR_HBA_LSB 0
8702
8703
#define ALT_SDMMC_BUFADDR_HBA_MSB 31
8704
8705
#define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
8706
8707
#define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
8708
8709
#define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
8710
8711
#define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
8712
8713
#define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
8714
8715
#define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
8716
8717
#ifndef __ASSEMBLY__
8718
8728
struct
ALT_SDMMC_BUFADDR_s
8729
{
8730
const
uint32_t
hba
: 32;
8731
};
8732
8734
typedef
volatile
struct
ALT_SDMMC_BUFADDR_s
ALT_SDMMC_BUFADDR_t
;
8735
#endif
/* __ASSEMBLY__ */
8736
8738
#define ALT_SDMMC_BUFADDR_OFST 0x98
8739
8776
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
8777
8782
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
8783
8785
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
8786
8787
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
8788
8789
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
8790
8791
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
8792
8793
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
8794
8795
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
8796
8797
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
8798
8799
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
8800
8810
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
8811
8812
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 27
8813
8814
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 12
8815
8816
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x0fff0000
8817
8818
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xf000ffff
8819
8820
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
8821
8822
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x0fff0000) >> 16)
8823
8824
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x0fff0000)
8825
8826
#ifndef __ASSEMBLY__
8827
8837
struct
ALT_SDMMC_CARDTHRCTL_s
8838
{
8839
uint32_t
cardrdthren
: 1;
8840
uint32_t : 15;
8841
uint32_t
cardrdthreshold
: 12;
8842
uint32_t : 4;
8843
};
8844
8846
typedef
volatile
struct
ALT_SDMMC_CARDTHRCTL_s
ALT_SDMMC_CARDTHRCTL_t
;
8847
#endif
/* __ASSEMBLY__ */
8848
8850
#define ALT_SDMMC_CARDTHRCTL_OFST 0x100
8851
8885
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
8886
8891
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
8892
8894
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
8895
8896
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
8897
8898
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
8899
8900
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
8901
8902
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
8903
8904
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
8905
8906
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
8907
8908
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
8909
8910
#ifndef __ASSEMBLY__
8911
8921
struct
ALT_SDMMC_BACK_END_POWER_R_s
8922
{
8923
uint32_t
back_end_power
: 16;
8924
uint32_t : 16;
8925
};
8926
8928
typedef
volatile
struct
ALT_SDMMC_BACK_END_POWER_R_s
ALT_SDMMC_BACK_END_POWER_R_t
;
8929
#endif
/* __ASSEMBLY__ */
8930
8932
#define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
8933
8957
#define ALT_SDMMC_DATA_VALUE_LSB 0
8958
8959
#define ALT_SDMMC_DATA_VALUE_MSB 31
8960
8961
#define ALT_SDMMC_DATA_VALUE_WIDTH 32
8962
8963
#define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
8964
8965
#define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
8966
8967
#define ALT_SDMMC_DATA_VALUE_RESET 0x0
8968
8969
#define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
8970
8971
#define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
8972
8973
#ifndef __ASSEMBLY__
8974
8984
struct
ALT_SDMMC_DATA_s
8985
{
8986
uint32_t
value
: 32;
8987
};
8988
8990
typedef
volatile
struct
ALT_SDMMC_DATA_s
ALT_SDMMC_DATA_t
;
8991
#endif
/* __ASSEMBLY__ */
8992
8994
#define ALT_SDMMC_DATA_OFST 0x200
8995
8996
#ifndef __ASSEMBLY__
8997
9007
struct
ALT_SDMMC_s
9008
{
9009
volatile
ALT_SDMMC_CTL_t
ctrl
;
9010
volatile
ALT_SDMMC_PWREN_t
pwren
;
9011
volatile
ALT_SDMMC_CLKDIV_t
clkdiv
;
9012
volatile
ALT_SDMMC_CLKSRC_t
clksrc
;
9013
volatile
ALT_SDMMC_CLKENA_t
clkena
;
9014
volatile
ALT_SDMMC_TMOUT_t
tmout
;
9015
volatile
ALT_SDMMC_CTYPE_t
ctype
;
9016
volatile
ALT_SDMMC_BLKSIZ_t
blksiz
;
9017
volatile
ALT_SDMMC_BYTCNT_t
bytcnt
;
9018
volatile
ALT_SDMMC_INTMSK_t
intmask
;
9019
volatile
ALT_SDMMC_CMDARG_t
cmdarg
;
9020
volatile
ALT_SDMMC_CMD_t
cmd
;
9021
volatile
ALT_SDMMC_RESP0_t
resp0
;
9022
volatile
ALT_SDMMC_RESP1_t
resp1
;
9023
volatile
ALT_SDMMC_RESP2_t
resp2
;
9024
volatile
ALT_SDMMC_RESP3_t
resp3
;
9025
volatile
ALT_SDMMC_MINTSTS_t
mintsts
;
9026
volatile
ALT_SDMMC_RINTSTS_t
rintsts
;
9027
volatile
ALT_SDMMC_STAT_t
status
;
9028
volatile
ALT_SDMMC_FIFOTH_t
fifoth
;
9029
volatile
ALT_SDMMC_CDETECT_t
cdetect
;
9030
volatile
ALT_SDMMC_WRTPRT_t
wrtprt
;
9031
volatile
uint32_t
_pad_0x58_0x5b
;
9032
volatile
ALT_SDMMC_TCBCNT_t
tcbcnt
;
9033
volatile
ALT_SDMMC_TBBCNT_t
tbbcnt
;
9034
volatile
ALT_SDMMC_DEBNCE_t
debnce
;
9035
volatile
ALT_SDMMC_USRID_t
usrid
;
9036
volatile
ALT_SDMMC_VERID_t
verid
;
9037
volatile
ALT_SDMMC_HCON_t
hcon
;
9038
volatile
ALT_SDMMC_UHS_REG_t
uhs_reg
;
9039
volatile
ALT_SDMMC_RST_N_t
rst_n
;
9040
volatile
uint32_t
_pad_0x7c_0x7f
;
9041
volatile
ALT_SDMMC_BMOD_t
bmod
;
9042
volatile
ALT_SDMMC_PLDMND_t
pldmnd
;
9043
volatile
ALT_SDMMC_DBADDR_t
dbaddr
;
9044
volatile
ALT_SDMMC_IDSTS_t
idsts
;
9045
volatile
ALT_SDMMC_IDINTEN_t
idinten
;
9046
volatile
ALT_SDMMC_DSCADDR_t
dscaddr
;
9047
volatile
ALT_SDMMC_BUFADDR_t
bufaddr
;
9048
volatile
uint32_t
_pad_0x9c_0xff
[25];
9049
volatile
ALT_SDMMC_CARDTHRCTL_t
cardthrctl
;
9050
volatile
ALT_SDMMC_BACK_END_POWER_R_t
back_end_power_r
;
9051
volatile
uint32_t
_pad_0x108_0x1ff
[62];
9052
volatile
ALT_SDMMC_DATA_t
data
;
9053
volatile
uint32_t
_pad_0x204_0x400
[127];
9054
};
9055
9057
typedef
volatile
struct
ALT_SDMMC_s
ALT_SDMMC_t
;
9059
struct
ALT_SDMMC_raw_s
9060
{
9061
volatile
uint32_t
ctrl
;
9062
volatile
uint32_t
pwren
;
9063
volatile
uint32_t
clkdiv
;
9064
volatile
uint32_t
clksrc
;
9065
volatile
uint32_t
clkena
;
9066
volatile
uint32_t
tmout
;
9067
volatile
uint32_t
ctype
;
9068
volatile
uint32_t
blksiz
;
9069
volatile
uint32_t
bytcnt
;
9070
volatile
uint32_t
intmask
;
9071
volatile
uint32_t
cmdarg
;
9072
volatile
uint32_t
cmd
;
9073
volatile
uint32_t
resp0
;
9074
volatile
uint32_t
resp1
;
9075
volatile
uint32_t
resp2
;
9076
volatile
uint32_t
resp3
;
9077
volatile
uint32_t
mintsts
;
9078
volatile
uint32_t
rintsts
;
9079
volatile
uint32_t
status
;
9080
volatile
uint32_t
fifoth
;
9081
volatile
uint32_t
cdetect
;
9082
volatile
uint32_t
wrtprt
;
9083
volatile
uint32_t
_pad_0x58_0x5b
;
9084
volatile
uint32_t
tcbcnt
;
9085
volatile
uint32_t
tbbcnt
;
9086
volatile
uint32_t
debnce
;
9087
volatile
uint32_t
usrid
;
9088
volatile
uint32_t
verid
;
9089
volatile
uint32_t
hcon
;
9090
volatile
uint32_t
uhs_reg
;
9091
volatile
uint32_t
rst_n
;
9092
volatile
uint32_t
_pad_0x7c_0x7f
;
9093
volatile
uint32_t
bmod
;
9094
volatile
uint32_t
pldmnd
;
9095
volatile
uint32_t
dbaddr
;
9096
volatile
uint32_t
idsts
;
9097
volatile
uint32_t
idinten
;
9098
volatile
uint32_t
dscaddr
;
9099
volatile
uint32_t
bufaddr
;
9100
volatile
uint32_t
_pad_0x9c_0xff
[25];
9101
volatile
uint32_t
cardthrctl
;
9102
volatile
uint32_t
back_end_power_r
;
9103
volatile
uint32_t
_pad_0x108_0x1ff
[62];
9104
volatile
uint32_t
data
;
9105
volatile
uint32_t
_pad_0x204_0x400
[127];
9106
};
9107
9109
typedef
volatile
struct
ALT_SDMMC_raw_s
ALT_SDMMC_raw_t
;
9110
#endif
/* __ASSEMBLY__ */
9111
9113
#ifdef __cplusplus
9114
}
9115
#endif
/* __cplusplus */
9116
#endif
/* __ALTERA_ALT_SDMMC_H__ */
9117
include
soc_cv_av
socal
alt_sdmmc.h
Generated on Tue Sep 8 2015 13:28:44 for Altera SoCAL by
1.8.2