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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Counter Restart Register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | W | 0x0 | ALT_L4WD_CRR_WDT_CRR |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : wdt_crr | |||||||
This register is used to restart the WDT counter. As a safety feature to prevent accidental restarts, the value 0x76 must be written. A restart also clears the WDT interrupt. Reading this register returns zero. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_CRR_WDT_CRR_E_KICK 0x76 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_LSB 0 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_MSB 7 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_WIDTH 8 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_SET_MSK 0x000000ff | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_CLR_MSK 0xffffff00 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_RESET 0x0 | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_GET(value) (((value) & 0x000000ff) >> 0) | ||||||
#define | ALT_L4WD_CRR_WDT_CRR_SET(value) (((value) << 0) & 0x000000ff) | ||||||
Data Structures | |
struct | ALT_L4WD_CRR_s |
Macros | |
#define | ALT_L4WD_CRR_RESET 0x00000000 |
#define | ALT_L4WD_CRR_OFST 0xc |
#define | ALT_L4WD_CRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CRR_OFST)) |
Typedefs | |
typedef struct ALT_L4WD_CRR_s | ALT_L4WD_CRR_t |
struct ALT_L4WD_CRR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_L4WD_CRR.
Data Fields | ||
---|---|---|
uint32_t | wdt_crr: 8 | ALT_L4WD_CRR_WDT_CRR |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_L4WD_CRR_WDT_CRR_E_KICK 0x76 |
Enumerated value for register field ALT_L4WD_CRR_WDT_CRR
Value to write to restart watchdog timer
#define ALT_L4WD_CRR_WDT_CRR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_L4WD_CRR_WDT_CRR register field.
#define ALT_L4WD_CRR_WDT_CRR_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_L4WD_CRR_WDT_CRR register field.
#define ALT_L4WD_CRR_WDT_CRR_WIDTH 8 |
The width in bits of the ALT_L4WD_CRR_WDT_CRR register field.
#define ALT_L4WD_CRR_WDT_CRR_SET_MSK 0x000000ff |
The mask used to set the ALT_L4WD_CRR_WDT_CRR register field value.
#define ALT_L4WD_CRR_WDT_CRR_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_L4WD_CRR_WDT_CRR register field value.
#define ALT_L4WD_CRR_WDT_CRR_RESET 0x0 |
The reset value of the ALT_L4WD_CRR_WDT_CRR register field.
#define ALT_L4WD_CRR_WDT_CRR_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_L4WD_CRR_WDT_CRR field value from a register.
#define ALT_L4WD_CRR_WDT_CRR_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_L4WD_CRR_WDT_CRR register field value suitable for setting the register.
#define ALT_L4WD_CRR_RESET 0x00000000 |
The reset value of the ALT_L4WD_CRR register.
#define ALT_L4WD_CRR_OFST 0xc |
The byte offset of the ALT_L4WD_CRR register from the beginning of the component.
#define ALT_L4WD_CRR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CRR_OFST)) |
The address of the ALT_L4WD_CRR register.
typedef struct ALT_L4WD_CRR_s ALT_L4WD_CRR_t |
The typedef declaration for register ALT_L4WD_CRR.