Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 MP Peripherals Security - l4mp

Description

Controls security settings for L4 MP peripherals.

Register Layout

Bits Access Reset Description
[0] W 0x0 FPGA Manager Register Security
[1] W 0x0 DAP Security
[2] W 0x0 QSPI Registers Security
[3] W 0x0 SDMMC Security
[4] W 0x0 EMAC 0 Security
[5] W 0x0 EMAC 1 Security
[6] W 0x0 ACP ID Mapper Security
[7] W 0x0 GPIO 0 Security
[8] W 0x0 GPIO 1 Security
[9] W 0x0 GPIO 2 Security
[31:10] ??? 0x0 UNDEFINED

Field : FPGA Manager Register Security - fpgamgrregs

Controls whether secure or non-secure masters can access the FPGA Manager Register slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_FPGAMGR_LSB   0
 
#define ALT_L3_SEC_L4MP_FPGAMGR_MSB   0
 
#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH   1
 
#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK   0x00000001
 
#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK   0xfffffffe
 
#define ALT_L3_SEC_L4MP_FPGAMGR_RESET   0x0
 
#define ALT_L3_SEC_L4MP_FPGAMGR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L3_SEC_L4MP_FPGAMGR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : DAP Security - dap

Controls whether secure or non-secure masters can access the DAP slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_DAP_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_DAP_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_DAP_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_DAP_LSB   1
 
#define ALT_L3_SEC_L4MP_DAP_MSB   1
 
#define ALT_L3_SEC_L4MP_DAP_WIDTH   1
 
#define ALT_L3_SEC_L4MP_DAP_SET_MSK   0x00000002
 
#define ALT_L3_SEC_L4MP_DAP_CLR_MSK   0xfffffffd
 
#define ALT_L3_SEC_L4MP_DAP_RESET   0x0
 
#define ALT_L3_SEC_L4MP_DAP_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L3_SEC_L4MP_DAP_SET(value)   (((value) << 1) & 0x00000002)
 

Field : QSPI Registers Security - qspiregs

Controls whether secure or non-secure masters can access the QSPI Registers slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_QSPI_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_QSPI_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_QSPI_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_QSPI_LSB   2
 
#define ALT_L3_SEC_L4MP_QSPI_MSB   2
 
#define ALT_L3_SEC_L4MP_QSPI_WIDTH   1
 
#define ALT_L3_SEC_L4MP_QSPI_SET_MSK   0x00000004
 
#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK   0xfffffffb
 
#define ALT_L3_SEC_L4MP_QSPI_RESET   0x0
 
#define ALT_L3_SEC_L4MP_QSPI_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_L3_SEC_L4MP_QSPI_SET(value)   (((value) << 2) & 0x00000004)
 

Field : SDMMC Security - sdmmc

Controls whether secure or non-secure masters can access the SDMMC slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_SDMMC_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_SDMMC_LSB   3
 
#define ALT_L3_SEC_L4MP_SDMMC_MSB   3
 
#define ALT_L3_SEC_L4MP_SDMMC_WIDTH   1
 
#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK   0x00000008
 
#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK   0xfffffff7
 
#define ALT_L3_SEC_L4MP_SDMMC_RESET   0x0
 
#define ALT_L3_SEC_L4MP_SDMMC_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_L3_SEC_L4MP_SDMMC_SET(value)   (((value) << 3) & 0x00000008)
 

Field : EMAC 0 Security - emac0

Controls whether secure or non-secure masters can access the EMAC 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_EMAC0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_EMAC0_LSB   4
 
#define ALT_L3_SEC_L4MP_EMAC0_MSB   4
 
#define ALT_L3_SEC_L4MP_EMAC0_WIDTH   1
 
#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK   0x00000010
 
#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK   0xffffffef
 
#define ALT_L3_SEC_L4MP_EMAC0_RESET   0x0
 
#define ALT_L3_SEC_L4MP_EMAC0_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_L3_SEC_L4MP_EMAC0_SET(value)   (((value) << 4) & 0x00000010)
 

Field : EMAC 1 Security - emac1

Controls whether secure or non-secure masters can access the EMAC 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_EMAC1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_EMAC1_LSB   5
 
#define ALT_L3_SEC_L4MP_EMAC1_MSB   5
 
#define ALT_L3_SEC_L4MP_EMAC1_WIDTH   1
 
#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK   0x00000020
 
#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK   0xffffffdf
 
#define ALT_L3_SEC_L4MP_EMAC1_RESET   0x0
 
#define ALT_L3_SEC_L4MP_EMAC1_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_L3_SEC_L4MP_EMAC1_SET(value)   (((value) << 5) & 0x00000020)
 

Field : ACP ID Mapper Security - acpidmap

Controls whether secure or non-secure masters can access the ACP ID Mapper slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB   6
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB   6
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH   1
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK   0x00000040
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK   0xffffffbf
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET   0x0
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_L3_SEC_L4MP_ACPIDMAP_SET(value)   (((value) << 6) & 0x00000040)
 

Field : GPIO 0 Security - gpio0

Controls whether secure or non-secure masters can access the GPIO 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_GPIO0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_GPIO0_LSB   7
 
#define ALT_L3_SEC_L4MP_GPIO0_MSB   7
 
#define ALT_L3_SEC_L4MP_GPIO0_WIDTH   1
 
#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK   0x00000080
 
#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK   0xffffff7f
 
#define ALT_L3_SEC_L4MP_GPIO0_RESET   0x0
 
#define ALT_L3_SEC_L4MP_GPIO0_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_L3_SEC_L4MP_GPIO0_SET(value)   (((value) << 7) & 0x00000080)
 

Field : GPIO 1 Security - gpio1

Controls whether secure or non-secure masters can access the GPIO 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_GPIO1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_GPIO1_LSB   8
 
#define ALT_L3_SEC_L4MP_GPIO1_MSB   8
 
#define ALT_L3_SEC_L4MP_GPIO1_WIDTH   1
 
#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK   0x00000100
 
#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK   0xfffffeff
 
#define ALT_L3_SEC_L4MP_GPIO1_RESET   0x0
 
#define ALT_L3_SEC_L4MP_GPIO1_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_L3_SEC_L4MP_GPIO1_SET(value)   (((value) << 8) & 0x00000100)
 

Field : GPIO 2 Security - gpio2

Controls whether secure or non-secure masters can access the GPIO 2 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4MP_GPIO2_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE   0x0
 
#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4MP_GPIO2_LSB   9
 
#define ALT_L3_SEC_L4MP_GPIO2_MSB   9
 
#define ALT_L3_SEC_L4MP_GPIO2_WIDTH   1
 
#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK   0x00000200
 
#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK   0xfffffdff
 
#define ALT_L3_SEC_L4MP_GPIO2_RESET   0x0
 
#define ALT_L3_SEC_L4MP_GPIO2_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_L3_SEC_L4MP_GPIO2_SET(value)   (((value) << 9) & 0x00000200)
 

Data Structures

struct  ALT_L3_SEC_L4MP_s
 

Macros

#define ALT_L3_SEC_L4MP_OFST   0x8
 

Typedefs

typedef struct ALT_L3_SEC_L4MP_s ALT_L3_SEC_L4MP_t
 

Data Structure Documentation

struct ALT_L3_SEC_L4MP_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L3_SEC_L4MP.

Data Fields
uint32_t fpgamgrregs: 1 FPGA Manager Register Security
uint32_t dap: 1 DAP Security
uint32_t qspiregs: 1 QSPI Registers Security
uint32_t sdmmc: 1 SDMMC Security
uint32_t emac0: 1 EMAC 0 Security
uint32_t emac1: 1 EMAC 1 Security
uint32_t acpidmap: 1 ACP ID Mapper Security
uint32_t gpio0: 1 GPIO 0 Security
uint32_t gpio1: 1 GPIO 1 Security
uint32_t gpio2: 1 GPIO 2 Security
uint32_t __pad0__: 22 UNDEFINED

Macro Definitions

#define ALT_L3_SEC_L4MP_FPGAMGR_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_FPGAMGR_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_FPGAMGR

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_FPGAMGR_LSB   0

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field.

#define ALT_L3_SEC_L4MP_FPGAMGR_MSB   0

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_FPGAMGR register field.

#define ALT_L3_SEC_L4MP_FPGAMGR_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_FPGAMGR register field.

#define ALT_L3_SEC_L4MP_FPGAMGR_SET_MSK   0x00000001

The mask used to set the ALT_L3_SEC_L4MP_FPGAMGR register field value.

#define ALT_L3_SEC_L4MP_FPGAMGR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L3_SEC_L4MP_FPGAMGR register field value.

#define ALT_L3_SEC_L4MP_FPGAMGR_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_FPGAMGR register field.

#define ALT_L3_SEC_L4MP_FPGAMGR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L3_SEC_L4MP_FPGAMGR field value from a register.

#define ALT_L3_SEC_L4MP_FPGAMGR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L3_SEC_L4MP_FPGAMGR register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_DAP_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_DAP

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_DAP_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_DAP

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_DAP_LSB   1

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_DAP register field.

#define ALT_L3_SEC_L4MP_DAP_MSB   1

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_DAP register field.

#define ALT_L3_SEC_L4MP_DAP_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_DAP register field.

#define ALT_L3_SEC_L4MP_DAP_SET_MSK   0x00000002

The mask used to set the ALT_L3_SEC_L4MP_DAP register field value.

#define ALT_L3_SEC_L4MP_DAP_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L3_SEC_L4MP_DAP register field value.

#define ALT_L3_SEC_L4MP_DAP_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_DAP register field.

#define ALT_L3_SEC_L4MP_DAP_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L3_SEC_L4MP_DAP field value from a register.

#define ALT_L3_SEC_L4MP_DAP_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L3_SEC_L4MP_DAP register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_QSPI_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_QSPI

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_QSPI_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_QSPI

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_QSPI_LSB   2

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_QSPI register field.

#define ALT_L3_SEC_L4MP_QSPI_MSB   2

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_QSPI register field.

#define ALT_L3_SEC_L4MP_QSPI_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_QSPI register field.

#define ALT_L3_SEC_L4MP_QSPI_SET_MSK   0x00000004

The mask used to set the ALT_L3_SEC_L4MP_QSPI register field value.

#define ALT_L3_SEC_L4MP_QSPI_CLR_MSK   0xfffffffb

The mask used to clear the ALT_L3_SEC_L4MP_QSPI register field value.

#define ALT_L3_SEC_L4MP_QSPI_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_QSPI register field.

#define ALT_L3_SEC_L4MP_QSPI_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_L3_SEC_L4MP_QSPI field value from a register.

#define ALT_L3_SEC_L4MP_QSPI_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_L3_SEC_L4MP_QSPI register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_SDMMC_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_SDMMC_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_SDMMC

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_SDMMC_LSB   3

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_SDMMC register field.

#define ALT_L3_SEC_L4MP_SDMMC_MSB   3

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_SDMMC register field.

#define ALT_L3_SEC_L4MP_SDMMC_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_SDMMC register field.

#define ALT_L3_SEC_L4MP_SDMMC_SET_MSK   0x00000008

The mask used to set the ALT_L3_SEC_L4MP_SDMMC register field value.

#define ALT_L3_SEC_L4MP_SDMMC_CLR_MSK   0xfffffff7

The mask used to clear the ALT_L3_SEC_L4MP_SDMMC register field value.

#define ALT_L3_SEC_L4MP_SDMMC_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_SDMMC register field.

#define ALT_L3_SEC_L4MP_SDMMC_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_L3_SEC_L4MP_SDMMC field value from a register.

#define ALT_L3_SEC_L4MP_SDMMC_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_L3_SEC_L4MP_SDMMC register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_EMAC0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_EMAC0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_EMAC0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_EMAC0_LSB   4

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field.

#define ALT_L3_SEC_L4MP_EMAC0_MSB   4

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC0 register field.

#define ALT_L3_SEC_L4MP_EMAC0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_EMAC0 register field.

#define ALT_L3_SEC_L4MP_EMAC0_SET_MSK   0x00000010

The mask used to set the ALT_L3_SEC_L4MP_EMAC0 register field value.

#define ALT_L3_SEC_L4MP_EMAC0_CLR_MSK   0xffffffef

The mask used to clear the ALT_L3_SEC_L4MP_EMAC0 register field value.

#define ALT_L3_SEC_L4MP_EMAC0_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_EMAC0 register field.

#define ALT_L3_SEC_L4MP_EMAC0_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_L3_SEC_L4MP_EMAC0 field value from a register.

#define ALT_L3_SEC_L4MP_EMAC0_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_L3_SEC_L4MP_EMAC0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_EMAC1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_EMAC1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_EMAC1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_EMAC1_LSB   5

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field.

#define ALT_L3_SEC_L4MP_EMAC1_MSB   5

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_EMAC1 register field.

#define ALT_L3_SEC_L4MP_EMAC1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_EMAC1 register field.

#define ALT_L3_SEC_L4MP_EMAC1_SET_MSK   0x00000020

The mask used to set the ALT_L3_SEC_L4MP_EMAC1 register field value.

#define ALT_L3_SEC_L4MP_EMAC1_CLR_MSK   0xffffffdf

The mask used to clear the ALT_L3_SEC_L4MP_EMAC1 register field value.

#define ALT_L3_SEC_L4MP_EMAC1_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_EMAC1 register field.

#define ALT_L3_SEC_L4MP_EMAC1_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_L3_SEC_L4MP_EMAC1 field value from a register.

#define ALT_L3_SEC_L4MP_EMAC1_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_L3_SEC_L4MP_EMAC1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_ACPIDMAP_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_ACPIDMAP_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_ACPIDMAP

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_ACPIDMAP_LSB   6

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field.

#define ALT_L3_SEC_L4MP_ACPIDMAP_MSB   6

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_ACPIDMAP register field.

#define ALT_L3_SEC_L4MP_ACPIDMAP_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_ACPIDMAP register field.

#define ALT_L3_SEC_L4MP_ACPIDMAP_SET_MSK   0x00000040

The mask used to set the ALT_L3_SEC_L4MP_ACPIDMAP register field value.

#define ALT_L3_SEC_L4MP_ACPIDMAP_CLR_MSK   0xffffffbf

The mask used to clear the ALT_L3_SEC_L4MP_ACPIDMAP register field value.

#define ALT_L3_SEC_L4MP_ACPIDMAP_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_ACPIDMAP register field.

#define ALT_L3_SEC_L4MP_ACPIDMAP_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_L3_SEC_L4MP_ACPIDMAP field value from a register.

#define ALT_L3_SEC_L4MP_ACPIDMAP_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_L3_SEC_L4MP_ACPIDMAP register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_GPIO0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_GPIO0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_GPIO0_LSB   7

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field.

#define ALT_L3_SEC_L4MP_GPIO0_MSB   7

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO0 register field.

#define ALT_L3_SEC_L4MP_GPIO0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_GPIO0 register field.

#define ALT_L3_SEC_L4MP_GPIO0_SET_MSK   0x00000080

The mask used to set the ALT_L3_SEC_L4MP_GPIO0 register field value.

#define ALT_L3_SEC_L4MP_GPIO0_CLR_MSK   0xffffff7f

The mask used to clear the ALT_L3_SEC_L4MP_GPIO0 register field value.

#define ALT_L3_SEC_L4MP_GPIO0_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_GPIO0 register field.

#define ALT_L3_SEC_L4MP_GPIO0_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_L3_SEC_L4MP_GPIO0 field value from a register.

#define ALT_L3_SEC_L4MP_GPIO0_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_L3_SEC_L4MP_GPIO0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_GPIO1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_GPIO1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_GPIO1_LSB   8

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field.

#define ALT_L3_SEC_L4MP_GPIO1_MSB   8

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO1 register field.

#define ALT_L3_SEC_L4MP_GPIO1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_GPIO1 register field.

#define ALT_L3_SEC_L4MP_GPIO1_SET_MSK   0x00000100

The mask used to set the ALT_L3_SEC_L4MP_GPIO1 register field value.

#define ALT_L3_SEC_L4MP_GPIO1_CLR_MSK   0xfffffeff

The mask used to clear the ALT_L3_SEC_L4MP_GPIO1 register field value.

#define ALT_L3_SEC_L4MP_GPIO1_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_GPIO1 register field.

#define ALT_L3_SEC_L4MP_GPIO1_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_L3_SEC_L4MP_GPIO1 field value from a register.

#define ALT_L3_SEC_L4MP_GPIO1_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_L3_SEC_L4MP_GPIO1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_GPIO2_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4MP_GPIO2_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4MP_GPIO2

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4MP_GPIO2_LSB   9

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field.

#define ALT_L3_SEC_L4MP_GPIO2_MSB   9

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4MP_GPIO2 register field.

#define ALT_L3_SEC_L4MP_GPIO2_WIDTH   1

The width in bits of the ALT_L3_SEC_L4MP_GPIO2 register field.

#define ALT_L3_SEC_L4MP_GPIO2_SET_MSK   0x00000200

The mask used to set the ALT_L3_SEC_L4MP_GPIO2 register field value.

#define ALT_L3_SEC_L4MP_GPIO2_CLR_MSK   0xfffffdff

The mask used to clear the ALT_L3_SEC_L4MP_GPIO2 register field value.

#define ALT_L3_SEC_L4MP_GPIO2_RESET   0x0

The reset value of the ALT_L3_SEC_L4MP_GPIO2 register field.

#define ALT_L3_SEC_L4MP_GPIO2_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_L3_SEC_L4MP_GPIO2 field value from a register.

#define ALT_L3_SEC_L4MP_GPIO2_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_L3_SEC_L4MP_GPIO2 register field value suitable for setting the register.

#define ALT_L3_SEC_L4MP_OFST   0x8

The byte offset of the ALT_L3_SEC_L4MP register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_L3_SEC_L4MP.