Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 Watchdog Debug Register - wddbg

Description

Controls the behavior of the L4 watchdogs when the CPUs are in debug mode. These control registers are used to drive the pause input signal of the L4 watchdogs. Note that the watchdogs built into the MPU automatically are paused when their associated CPU enters debug mode. Only reset by a cold reset.

Register Layout

Bits Access Reset Description
[1:0] RW 0x3 Debug Mode
[3:2] RW 0x3 Debug Mode
[31:4] ??? 0x0 UNDEFINED

Field : Debug Mode - mode_0

Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0 Continue normal operation ignoring debug mode of
: CPUs
ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1 Pause normal operation only if CPU0 is in debug
: mode
ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2 Pause normal operation only if CPU1 is in debug
: mode
ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3 Pause normal operation if CPU0 or CPU1 is in
: debug mode

Field Access Macros:

#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE   0x0
 
#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0   0x1
 
#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1   0x2
 
#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER   0x3
 
#define ALT_SYSMGR_WDDBG_MOD_0_LSB   0
 
#define ALT_SYSMGR_WDDBG_MOD_0_MSB   1
 
#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH   2
 
#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK   0x00000003
 
#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK   0xfffffffc
 
#define ALT_SYSMGR_WDDBG_MOD_0_RESET   0x3
 
#define ALT_SYSMGR_WDDBG_MOD_0_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_SYSMGR_WDDBG_MOD_0_SET(value)   (((value) << 0) & 0x00000003)
 

Field : Debug Mode - mode_1

Controls behavior of L4 watchdog when CPUs in debug mode. Field array index matches L4 watchdog index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0 Continue normal operation ignoring debug mode of
: CPUs
ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1 Pause normal operation only if CPU0 is in debug
: mode
ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2 Pause normal operation only if CPU1 is in debug
: mode
ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3 Pause normal operation if CPU0 or CPU1 is in
: debug mode

Field Access Macros:

#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE   0x0
 
#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0   0x1
 
#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1   0x2
 
#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER   0x3
 
#define ALT_SYSMGR_WDDBG_MOD_1_LSB   2
 
#define ALT_SYSMGR_WDDBG_MOD_1_MSB   3
 
#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH   2
 
#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK   0x0000000c
 
#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK   0xfffffff3
 
#define ALT_SYSMGR_WDDBG_MOD_1_RESET   0x3
 
#define ALT_SYSMGR_WDDBG_MOD_1_GET(value)   (((value) & 0x0000000c) >> 2)
 
#define ALT_SYSMGR_WDDBG_MOD_1_SET(value)   (((value) << 2) & 0x0000000c)
 

Data Structures

struct  ALT_SYSMGR_WDDBG_s
 

Macros

#define ALT_SYSMGR_WDDBG_OFST   0x10
 

Typedefs

typedef struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t
 

Data Structure Documentation

struct ALT_SYSMGR_WDDBG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_WDDBG.

Data Fields
uint32_t mode_0: 2 Debug Mode
uint32_t mode_1: 2 Debug Mode
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE   0x0

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0

Continue normal operation ignoring debug mode of CPUs

#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0   0x1

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0

Pause normal operation only if CPU0 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1   0x2

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0

Pause normal operation only if CPU1 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER   0x3

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_0

Pause normal operation if CPU0 or CPU1 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_0_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field.

#define ALT_SYSMGR_WDDBG_MOD_0_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_0 register field.

#define ALT_SYSMGR_WDDBG_MOD_0_WIDTH   2

The width in bits of the ALT_SYSMGR_WDDBG_MOD_0 register field.

#define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK   0x00000003

The mask used to set the ALT_SYSMGR_WDDBG_MOD_0 register field value.

#define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK   0xfffffffc

The mask used to clear the ALT_SYSMGR_WDDBG_MOD_0 register field value.

#define ALT_SYSMGR_WDDBG_MOD_0_RESET   0x3

The reset value of the ALT_SYSMGR_WDDBG_MOD_0 register field.

#define ALT_SYSMGR_WDDBG_MOD_0_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_SYSMGR_WDDBG_MOD_0 field value from a register.

#define ALT_SYSMGR_WDDBG_MOD_0_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_SYSMGR_WDDBG_MOD_0 register field value suitable for setting the register.

#define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE   0x0

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1

Continue normal operation ignoring debug mode of CPUs

#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0   0x1

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1

Pause normal operation only if CPU0 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1   0x2

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1

Pause normal operation only if CPU1 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER   0x3

Enumerated value for register field ALT_SYSMGR_WDDBG_MOD_1

Pause normal operation if CPU0 or CPU1 is in debug mode

#define ALT_SYSMGR_WDDBG_MOD_1_LSB   2

The Least Significant Bit (LSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field.

#define ALT_SYSMGR_WDDBG_MOD_1_MSB   3

The Most Significant Bit (MSB) position of the ALT_SYSMGR_WDDBG_MOD_1 register field.

#define ALT_SYSMGR_WDDBG_MOD_1_WIDTH   2

The width in bits of the ALT_SYSMGR_WDDBG_MOD_1 register field.

#define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK   0x0000000c

The mask used to set the ALT_SYSMGR_WDDBG_MOD_1 register field value.

#define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK   0xfffffff3

The mask used to clear the ALT_SYSMGR_WDDBG_MOD_1 register field value.

#define ALT_SYSMGR_WDDBG_MOD_1_RESET   0x3

The reset value of the ALT_SYSMGR_WDDBG_MOD_1 register field.

#define ALT_SYSMGR_WDDBG_MOD_1_GET (   value)    (((value) & 0x0000000c) >> 2)

Extracts the ALT_SYSMGR_WDDBG_MOD_1 field value from a register.

#define ALT_SYSMGR_WDDBG_MOD_1_SET (   value)    (((value) << 2) & 0x0000000c)

Produces a ALT_SYSMGR_WDDBG_MOD_1 register field value suitable for setting the register.

#define ALT_SYSMGR_WDDBG_OFST   0x10

The byte offset of the ALT_SYSMGR_WDDBG register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_WDDBG.