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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Allows HPS to control FPGA configuration.
The NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields drive signals to the FPGA Control Block that are logically ORed into their respective pins. These signals are always driven independent of the value of EN. The polarity of the NCONFIGPULL, NSTATUSPULL, and CONFDONEPULL fields is inverted relative to their associated pins.
The MSEL (external pins), CDRATIO and CFGWDTH signals determine the mode of operation for Normal Configuration. For Partial Reconfiguration, CDRATIO is used to set the appropriate clock to data ratio, and CFGWDTH should always be set to 16-bit Passive Parallel.
AXICFGEN is used to enable transfer of configuration data by enabling or disabling DCLK during data transfers.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL |
[7:1] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA |
[15:9] | ??? | 0x1 | UNDEFINED |
[17:16] | RW | 0x0 | CD Ratio |
[23:18] | ??? | 0x0 | UNDEFINED |
[24] | RW | 0x0 | Configuration Data Width |
[31:25] | ??? | 0x0 | UNDEFINED |
Field : en_cfg_ctrl | |
If this bit is not enabled, the s2f_dclk as well as s2f_data will be always driven 0. This is to provide a mechanism by which HPS can take over the DCLK/DATA by first setting the nenable_dclk even while s2f_dclk and s2f_data from HPS is silent. Field Access Macros: | |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_LSB 0 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_MSB 0 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_WIDTH 1 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET_MSK 0x00000001 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_CLR_MSK 0xfffffffe |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_RESET 0x0 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET(value) (((value) << 0) & 0x00000001) |
Field : en_cfg_data | |
this is an unused software bit Field Access Macros: | |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_LSB 8 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_MSB 8 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_WIDTH 1 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_CLR_MSK 0xfffffeff |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_RESET 0x0 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET(value) (((value) << 8) & 0x00000100) |
Field : CD Ratio - cdratio | ||||||||||||||||
This field controls the Clock to Data Ratio (CDRATIO) for Normal Configuration and Partial Reconfiguration data transfer from the AXI Slave to the FPGA. For Normal Configuration, the value in this field must be set to be consistent to the implied CD ratio of the MSEL setting. For Partial Reconfiguration, the value in this field must be set to the same clock to data ratio in the options bits in the Normal Configuration file. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 0x0 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 0x1 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 0x2 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 0x3 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MSB 17 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_WIDTH 2 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_CLR_MSK 0xfffcffff | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_RESET 0x0 | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_GET(value) (((value) & 0x00030000) >> 16) | |||||||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET(value) (((value) << 16) & 0x00030000) | |||||||||||||||
Field : Configuration Data Width - cfgwidth | ||||||||||
This field determines the Configuration Passive Parallel data bus width when HPS configures the FPGA. Only 32-bit Passive Parallel or 16-bit Passive Parallel are supported. When HPS does Normal Configuration, configuration should use 32-bit Passive Parallel Mode. The external pins MSEL must be set appropriately for the configuration selected. For Partial Reconfiguration, 16-bit Passive Parallel must be used. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 0x0 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 0x1 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_LSB 24 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_MSB 24 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_WIDTH 1 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_CLR_MSK 0xfeffffff | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_RESET 0x0 | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_GET(value) (((value) & 0x01000000) >> 24) | |||||||||
#define | ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET(value) (((value) << 24) & 0x01000000) | |||||||||
Data Structures | |
struct | ALT_FPGAMGR_IMGCFG_CTL_02_s |
Macros | |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_RESET 0x00000200 |
#define | ALT_FPGAMGR_IMGCFG_CTL_02_OFST 0x78 |
Typedefs | |
typedef struct ALT_FPGAMGR_IMGCFG_CTL_02_s | ALT_FPGAMGR_IMGCFG_CTL_02_t |
struct ALT_FPGAMGR_IMGCFG_CTL_02_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_FPGAMGR_IMGCFG_CTL_02.
Data Fields | ||
---|---|---|
uint32_t | en_cfg_ctrl: 1 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL |
uint32_t | __pad0__: 7 | UNDEFINED |
uint32_t | en_cfg_data: 1 | ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA |
uint32_t | __pad1__: 7 | UNDEFINED |
uint32_t | cdratio: 2 | CD Ratio |
uint32_t | __pad2__: 6 | UNDEFINED |
uint32_t | cfgwidth: 1 | Configuration Data Width |
uint32_t | __pad3__: 7 | UNDEFINED |
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_WIDTH 1 |
The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET_MSK 0x00000001 |
The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_RESET 0x0 |
The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL field value from a register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTL register field value suitable for setting the register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_WIDTH 1 |
The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK 0x00000100 |
The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_RESET 0x0 |
The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA field value from a register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA register field value suitable for setting the register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X1 0x0 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
CDRATIO of 1
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X2 0x1 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
CDRATIO of 2
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X4 0x2 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
CDRATIO of 4
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_E_X8 0x3 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO
CDRATIO of 8
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_WIDTH 2 |
The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK 0x00030000 |
The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_RESET 0x0 |
The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO field value from a register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO register field value suitable for setting the register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX16 0x0 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH
16-bit Passive Parallel
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_E_PPX32 0x1 |
Enumerated value for register field ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH
32-bit Passive Parallel
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_WIDTH 1 |
The width in bits of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK 0x01000000 |
The mask used to set the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_RESET 0x0 |
The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH field value from a register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH register field value suitable for setting the register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_RESET 0x00000200 |
The reset value of the ALT_FPGAMGR_IMGCFG_CTL_02 register.
#define ALT_FPGAMGR_IMGCFG_CTL_02_OFST 0x78 |
The byte offset of the ALT_FPGAMGR_IMGCFG_CTL_02 register from the beginning of the component.
typedef struct ALT_FPGAMGR_IMGCFG_CTL_02_s ALT_FPGAMGR_IMGCFG_CTL_02_t |
The typedef declaration for register ALT_FPGAMGR_IMGCFG_CTL_02.