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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[4:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID |
[6:5] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD |
[9:7] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN |
[12:10] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN |
[15:13] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN |
[18:16] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN |
[21:19] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN |
[23:22] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET |
[25:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET |
[27:26] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET |
[29:28] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET |
[31:30] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET |
Field : cfg_tile_id | |
Tile ID Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_LSB 0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_MSB 4 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_WIDTH 5 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_GET(value) (((value) & 0x0000001f) >> 0) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET(value) (((value) << 0) & 0x0000001f) |
Field : cfg_pingpong_mode | |
Ping Pong mode: 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_LSB 5 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_MSB 6 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET_MSK 0x00000060 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_CLR_MSK 0xffffff9f |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_GET(value) (((value) & 0x00000060) >> 5) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET(value) (((value) << 5) & 0x00000060) |
Field : cfg_ctrl_slot_rotate_en | |
Cmd slot rotate enable: bit[0] controls write, 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_LSB 7 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_MSB 9 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET_MSK 0x00000380 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_GET(value) (((value) & 0x00000380) >> 7) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET(value) (((value) << 7) & 0x00000380) |
Field : cfg_dbc0_slot_rotate_en | |
DBC0 slot rotate enable: bit[0] controls write, 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET(value) (((value) & 0x00001c00) >> 10) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET(value) (((value) << 10) & 0x00001c00) |
Field : cfg_dbc1_slot_rotate_en | |
DBC1 slot rotate enable: bit[0] controls write, 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET(value) (((value) & 0x0000e000) >> 13) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET(value) (((value) << 13) & 0x0000e000) |
Field : cfg_dbc2_slot_rotate_en | |
DBC2 slot rotate enable: bit[0] controls write, 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET(value) (((value) & 0x00070000) >> 16) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET(value) (((value) << 16) & 0x00070000) |
Field : cfg_dbc3_slot_rotate_en | |
DBC3 slot rotate enable: bit[0] controls write, 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET(value) (((value) & 0x00380000) >> 19) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET(value) (((value) << 19) & 0x00380000) |
Field : cfg_ctrl_slot_offset | |
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_LSB 22 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_MSB 23 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET_MSK 0x00c00000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_CLR_MSK 0xff3fffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_GET(value) (((value) & 0x00c00000) >> 22) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET(value) (((value) << 22) & 0x00c00000) |
Field : cfg_dbc0_slot_offset | |
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_GET(value) (((value) & 0x03000000) >> 24) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET(value) (((value) << 24) & 0x03000000) |
Field : cfg_dbc1_slot_offset | |
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_GET(value) (((value) & 0x0c000000) >> 26) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET(value) (((value) << 26) & 0x0c000000) |
Field : cfg_dbc2_slot_offset | |
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_GET(value) (((value) & 0x30000000) >> 28) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET(value) (((value) << 28) & 0x30000000) |
Field : cfg_dbc3_slot_offset | |
Enables afi information to be offset by numbers of FR cycles. Affected afi signal is afi_rdata_en, afi_rdata_en_full, afi_wdata_valid, afi_dqs_burst, afi_mrnk_write and afi_mrnk_read. Set this to: - 2 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_GET(value) (((value) & 0xc0000000) >> 30) |
#define | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET(value) (((value) << 30) & 0xc0000000) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_CTLCFG4_s |
Macros | |
#define | ALT_IO48_HMC_MMR_CTLCFG4_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG4_OFST 0x38 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_CTLCFG4_s | ALT_IO48_HMC_MMR_CTLCFG4_t |
struct ALT_IO48_HMC_MMR_CTLCFG4_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG4.
Data Fields | ||
---|---|---|
uint32_t | cfg_tile_id: 5 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID |
uint32_t | cfg_pingpong_mode: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD |
uint32_t | cfg_ctrl_slot_rotate_en: 3 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN |
uint32_t | cfg_dbc0_slot_rotate_en: 3 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN |
uint32_t | cfg_dbc1_slot_rotate_en: 3 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN |
uint32_t | cfg_dbc2_slot_rotate_en: 3 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN |
uint32_t | cfg_dbc3_slot_rotate_en: 3 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN |
uint32_t | cfg_ctrl_slot_offset: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET |
uint32_t | cfg_dbc0_slot_offset: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET |
uint32_t | cfg_dbc1_slot_offset: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET |
uint32_t | cfg_dbc2_slot_offset: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET |
uint32_t | cfg_dbc3_slot_offset: 2 | ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET |
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_WIDTH 5 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET_MSK 0x0000001f |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_CLR_MSK 0xffffffe0 |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_GET | ( | value | ) | (((value) & 0x0000001f) >> 0) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID_SET | ( | value | ) | (((value) << 0) & 0x0000001f) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_TILE_ID register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET_MSK 0x00000060 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_CLR_MSK 0xffffff9f |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_GET | ( | value | ) | (((value) & 0x00000060) >> 5) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD_SET | ( | value | ) | (((value) << 5) & 0x00000060) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_PINGPONG_MOD register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET_MSK 0x00000380 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_CLR_MSK 0xfffffc7f |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_GET | ( | value | ) | (((value) & 0x00000380) >> 7) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN_SET | ( | value | ) | (((value) << 7) & 0x00000380) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_ROTATE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET_MSK 0x00001c00 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_CLR_MSK 0xffffe3ff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_GET | ( | value | ) | (((value) & 0x00001c00) >> 10) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN_SET | ( | value | ) | (((value) << 10) & 0x00001c00) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_ROTATE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET_MSK 0x0000e000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_CLR_MSK 0xffff1fff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_GET | ( | value | ) | (((value) & 0x0000e000) >> 13) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN_SET | ( | value | ) | (((value) << 13) & 0x0000e000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_ROTATE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET_MSK 0x00070000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_CLR_MSK 0xfff8ffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_GET | ( | value | ) | (((value) & 0x00070000) >> 16) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN_SET | ( | value | ) | (((value) << 16) & 0x00070000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_ROTATE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET_MSK 0x00380000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_CLR_MSK 0xffc7ffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_GET | ( | value | ) | (((value) & 0x00380000) >> 19) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN_SET | ( | value | ) | (((value) << 19) & 0x00380000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_ROTATE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET_MSK 0x00c00000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_CLR_MSK 0xff3fffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_GET | ( | value | ) | (((value) & 0x00c00000) >> 22) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET_SET | ( | value | ) | (((value) << 22) & 0x00c00000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_CTL_SLOT_OFFSET register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET_MSK 0x03000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_CLR_MSK 0xfcffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_GET | ( | value | ) | (((value) & 0x03000000) >> 24) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET_SET | ( | value | ) | (((value) << 24) & 0x03000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC0_SLOT_OFFSET register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET_MSK 0x0c000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_CLR_MSK 0xf3ffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_GET | ( | value | ) | (((value) & 0x0c000000) >> 26) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET_SET | ( | value | ) | (((value) << 26) & 0x0c000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC1_SLOT_OFFSET register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET_MSK 0x30000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_CLR_MSK 0xcfffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_GET | ( | value | ) | (((value) & 0x30000000) >> 28) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET_SET | ( | value | ) | (((value) << 28) & 0x30000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC2_SLOT_OFFSET register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_LSB 30 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_WIDTH 2 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET_MSK 0xc0000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_CLR_MSK 0x3fffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_GET | ( | value | ) | (((value) & 0xc0000000) >> 30) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET_SET | ( | value | ) | (((value) << 30) & 0xc0000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG4_CFG_DBC3_SLOT_OFFSET register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG4_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG4 register.
#define ALT_IO48_HMC_MMR_CTLCFG4_OFST 0x38 |
The byte offset of the ALT_IO48_HMC_MMR_CTLCFG4 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_CTLCFG4_s ALT_IO48_HMC_MMR_CTLCFG4_t |
The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG4.