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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock dividers for NoC Clocks.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x0 | L4 Main Clock Divider |
[7:2] | ??? | 0x0 | UNDEFINED |
[9:8] | RW | 0x1 | L4 MP Clock Divider |
[15:10] | ??? | 0x0 | UNDEFINED |
[17:16] | RW | 0x2 | L4 SP Clock Divider |
[23:18] | ??? | 0x0 | UNDEFINED |
[25:24] | RW | 0x0 | CoreSight Trace Clock Divider |
[27:26] | RW | 0x2 | CoreSight Trace Interface Clock Divider |
[28] | RW | 0x1 | CoreSight Debug Clock Divider |
[31:29] | ??? | 0x0 | UNDEFINED |
Field : L4 MP Clock Divider - l4mpclk | ||||||||||||||||
The external l4_mp_clk divider is specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 0x0 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 0x1 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 0x3 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_MSB 9 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_WIDTH 2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET_MSK 0x00000300 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_CLR_MSK 0xfffffcff | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_RESET 0x1 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_GET(value) (((value) & 0x00000300) >> 8) | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET(value) (((value) << 8) & 0x00000300) | |||||||||||||||
Field : L4 SP Clock Divider - l4spclk | ||||||||||||||||
The external l4_sp_clk divider is specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 0x0 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 0x1 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 0x3 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_MSB 17 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_WIDTH 2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET_MSK 0x00030000 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_CLR_MSK 0xfffcffff | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_RESET 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_GET(value) (((value) & 0x00030000) >> 16) | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET(value) (((value) << 16) & 0x00030000) | |||||||||||||||
Field : CoreSight Trace Clock Divider - csatclk | ||||||||||||||||
The external cs_at_clk divider is specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 0x0 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 0x1 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 0x3 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_MSB 25 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_WIDTH 2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET_MSK 0x03000000 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_CLR_MSK 0xfcffffff | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_RESET 0x0 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_GET(value) (((value) & 0x03000000) >> 24) | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET(value) (((value) << 24) & 0x03000000) | |||||||||||||||
Field : CoreSight Trace Interface Clock Divider - cstraceclk | ||||||||||||||||
The external cs_trace_clk divider is specified in this field. The cs_trace_clk is used by the actual trace interface to the debugger. This divider is cascaded after the cs_at_clk external divider. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 0x0 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 0x1 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 0x3 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_MSB 27 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_WIDTH 2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET_MSK 0x0c000000 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_CLR_MSK 0xf3ffffff | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_RESET 0x2 | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_GET(value) (((value) & 0x0c000000) >> 26) | |||||||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET(value) (((value) << 26) & 0x0c000000) | |||||||||||||||
Field : CoreSight Debug Clock Divider - cspdbgclk | ||||||||||
The external cs_pdbg_clk divider is specified in this field. This divider is cascaded after the cs_at_clk external divider. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 0x0 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_MSB 28 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_WIDTH 1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET_MSK 0x10000000 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_CLR_MSK 0xefffffff | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_RESET 0x1 | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_GET(value) (((value) & 0x10000000) >> 28) | |||||||||
#define | ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET(value) (((value) << 28) & 0x10000000) | |||||||||
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_NOCDIV_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_NOCDIV_RESET 0x18020100 |
#define | ALT_CLKMGR_MAINPLL_NOCDIV_OFST 0x68 |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_NOCDIV_s | ALT_CLKMGR_MAINPLL_NOCDIV_t |
struct ALT_CLKMGR_MAINPLL_NOCDIV_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_NOCDIV.
Data Fields | ||
---|---|---|
uint32_t | l4mainclk: 2 | L4 Main Clock Divider |
uint32_t | __pad0__: 6 | UNDEFINED |
uint32_t | l4mpclk: 2 | L4 MP Clock Divider |
uint32_t | __pad1__: 6 | UNDEFINED |
uint32_t | l4spclk: 2 | L4 SP Clock Divider |
uint32_t | __pad2__: 6 | UNDEFINED |
uint32_t | csatclk: 2 | CoreSight Trace Clock Divider |
uint32_t | cstraceclk: 2 | CoreSight Trace Interface Clock Divider |
uint32_t | cspdbgclk: 1 | CoreSight Debug Clock Divider |
uint32_t | __pad3__: 3 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET_MSK 0x00000003 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET_MSK 0x00000300 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET_MSK 0x00030000 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_RESET 0x2 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET_MSK 0x03000000 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_CLR_MSK 0xfcffffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_GET | ( | value | ) | (((value) & 0x03000000) >> 24) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET | ( | value | ) | (((value) << 24) & 0x03000000) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
Divide By 2
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK
Divide By 8
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET_MSK 0x0c000000 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_CLR_MSK 0xf3ffffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_RESET 0x2 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_GET | ( | value | ) | (((value) & 0x0c000000) >> 26) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET | ( | value | ) | (((value) << 26) & 0x0c000000) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
Divide By 1
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK
Divide By 4
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET_MSK 0x10000000 |
The mask used to set the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_CLR_MSK 0xefffffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK field value from a register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_RESET 0x18020100 |
The reset value of the ALT_CLKMGR_MAINPLL_NOCDIV register.
#define ALT_CLKMGR_MAINPLL_NOCDIV_OFST 0x68 |
The byte offset of the ALT_CLKMGR_MAINPLL_NOCDIV register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_NOCDIV_s ALT_CLKMGR_MAINPLL_NOCDIV_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_NOCDIV.