Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Remap - remap

Description

The L3 interconnect has separate address maps for the various L3 Masters. Generally, the addresses are the same for most masters. However, the sparse interconnect of the L3 switch causes some masters to have holes in their memory maps. The remap bits are not mutually exclusive. Each bit can be set independently and in combinations. Priority for the bits is determined by the bit offset: lower offset bits take precedence over higher offset bits.

Register Layout

Bits Access Reset Description
[0] W 0x0 MPU at 0x0
[1] W 0x0 Non-MPU at 0x0
[2] ??? 0x0 UNDEFINED
[3] W 0x0 HPS2FPGA AXI Bridge Visibility
[4] W 0x0 LWHPS2FPGA AXI Bridge Visibility
[31:5] ??? 0x0 UNDEFINED

Field : MPU at 0x0 - mpuzero

Controls whether address 0x0 for the MPU L3 master is mapped to the Boot ROM or On-chip RAM. This field only has an effect on the MPU L3 master.

Field Enumeration Values:

Enum Value Description
ALT_L3_REMAP_MPUZERO_E_BOOTROM 0x0 Maps the Boot ROM to address 0x0 for the MPU L3
: master. Note that the Boot ROM is also always
: mapped to address 0xfffd_0000 for the MPU L3
: master independent of this field's value.
ALT_L3_REMAP_MPUZERO_E_OCRAM 0x1 Maps the On-chip RAM to address 0x0 for the MPU
: L3 master. Note that the On-chip RAM is also
: always mapped to address 0xffff_0000 for the MPU
: L3 master independent of this field's value.

Field Access Macros:

#define ALT_L3_REMAP_MPUZERO_E_BOOTROM   0x0
 
#define ALT_L3_REMAP_MPUZERO_E_OCRAM   0x1
 
#define ALT_L3_REMAP_MPUZERO_LSB   0
 
#define ALT_L3_REMAP_MPUZERO_MSB   0
 
#define ALT_L3_REMAP_MPUZERO_WIDTH   1
 
#define ALT_L3_REMAP_MPUZERO_SET_MSK   0x00000001
 
#define ALT_L3_REMAP_MPUZERO_CLR_MSK   0xfffffffe
 
#define ALT_L3_REMAP_MPUZERO_RESET   0x0
 
#define ALT_L3_REMAP_MPUZERO_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L3_REMAP_MPUZERO_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Non-MPU at 0x0 - nonmpuzero

Controls whether address 0x0 for the non-MPU L3 masters is mapped to the SDRAM or On-chip RAM. This field only has an effect on the non-MPU L3 masters. The non-MPU L3 masters are the DMA controllers (standalone and those built-in to peripherals), the FPGA2HPS AXI Bridge, and the DAP.

Field Enumeration Values:

Enum Value Description
ALT_L3_REMAP_NONMPUZERO_E_SDRAM 0x0 Maps the SDRAM to address 0x0 for the non-MPU L3
: masters.
ALT_L3_REMAP_NONMPUZERO_E_OCRAM 0x1 Maps the On-chip RAM to address 0x0 for the non-
: MPU L3 masters. Note that the On-chip RAM is
: also always mapped to address 0xffff_0000 for
: the non-MPU L3 masters independent of this
: field's value.

Field Access Macros:

#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM   0x0
 
#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM   0x1
 
#define ALT_L3_REMAP_NONMPUZERO_LSB   1
 
#define ALT_L3_REMAP_NONMPUZERO_MSB   1
 
#define ALT_L3_REMAP_NONMPUZERO_WIDTH   1
 
#define ALT_L3_REMAP_NONMPUZERO_SET_MSK   0x00000002
 
#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK   0xfffffffd
 
#define ALT_L3_REMAP_NONMPUZERO_RESET   0x0
 
#define ALT_L3_REMAP_NONMPUZERO_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L3_REMAP_NONMPUZERO_SET(value)   (((value) << 1) & 0x00000002)
 

Field : HPS2FPGA AXI Bridge Visibility - hps2fpga

Controls whether the HPS2FPGA AXI Bridge is visible to L3 masters or not.

Field Enumeration Values:

Enum Value Description
ALT_L3_REMAP_H2F_E_INVISIBLE 0x0 The HPS2FPGA AXI Bridge is not visible to L3
: masters. Accesses to the associated address
: range return an AXI decode error to the master.
ALT_L3_REMAP_H2F_E_VISIBLE 0x1 The HPS2FPGA AXI Bridge is visible to L3
: masters.

Field Access Macros:

#define ALT_L3_REMAP_H2F_E_INVISIBLE   0x0
 
#define ALT_L3_REMAP_H2F_E_VISIBLE   0x1
 
#define ALT_L3_REMAP_H2F_LSB   3
 
#define ALT_L3_REMAP_H2F_MSB   3
 
#define ALT_L3_REMAP_H2F_WIDTH   1
 
#define ALT_L3_REMAP_H2F_SET_MSK   0x00000008
 
#define ALT_L3_REMAP_H2F_CLR_MSK   0xfffffff7
 
#define ALT_L3_REMAP_H2F_RESET   0x0
 
#define ALT_L3_REMAP_H2F_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_L3_REMAP_H2F_SET(value)   (((value) << 3) & 0x00000008)
 

Field : LWHPS2FPGA AXI Bridge Visibility - lwhps2fpga

Controls whether the Lightweight HPS2FPGA AXI Bridge is visible to L3 masters or not.

Field Enumeration Values:

Enum Value Description
ALT_L3_REMAP_LWH2F_E_INVISIBLE 0x0 The LWHPS2FPGA AXI Bridge is not visible to L3
: masters. Accesses to the associated address
: range return an AXI decode error to the master.
ALT_L3_REMAP_LWH2F_E_VISIBLE 0x1 The LWHPS2FPGA AXI Bridge is visible to L3
: masters.

Field Access Macros:

#define ALT_L3_REMAP_LWH2F_E_INVISIBLE   0x0
 
#define ALT_L3_REMAP_LWH2F_E_VISIBLE   0x1
 
#define ALT_L3_REMAP_LWH2F_LSB   4
 
#define ALT_L3_REMAP_LWH2F_MSB   4
 
#define ALT_L3_REMAP_LWH2F_WIDTH   1
 
#define ALT_L3_REMAP_LWH2F_SET_MSK   0x00000010
 
#define ALT_L3_REMAP_LWH2F_CLR_MSK   0xffffffef
 
#define ALT_L3_REMAP_LWH2F_RESET   0x0
 
#define ALT_L3_REMAP_LWH2F_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_L3_REMAP_LWH2F_SET(value)   (((value) << 4) & 0x00000010)
 

Data Structures

struct  ALT_L3_REMAP_s
 

Macros

#define ALT_L3_REMAP_OFST   0x0
 

Typedefs

typedef struct ALT_L3_REMAP_s ALT_L3_REMAP_t
 

Data Structure Documentation

struct ALT_L3_REMAP_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L3_REMAP.

Data Fields
uint32_t mpuzero: 1 MPU at 0x0
uint32_t nonmpuzero: 1 Non-MPU at 0x0
uint32_t __pad0__: 1 UNDEFINED
uint32_t hps2fpga: 1 HPS2FPGA AXI Bridge Visibility
uint32_t lwhps2fpga: 1 LWHPS2FPGA AXI Bridge Visibility
uint32_t __pad1__: 27 UNDEFINED

Macro Definitions

#define ALT_L3_REMAP_MPUZERO_E_BOOTROM   0x0

Enumerated value for register field ALT_L3_REMAP_MPUZERO

Maps the Boot ROM to address 0x0 for the MPU L3 master. Note that the Boot ROM is also always mapped to address 0xfffd_0000 for the MPU L3 master independent of this field's value.

#define ALT_L3_REMAP_MPUZERO_E_OCRAM   0x1

Enumerated value for register field ALT_L3_REMAP_MPUZERO

Maps the On-chip RAM to address 0x0 for the MPU L3 master. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the MPU L3 master independent of this field's value.

#define ALT_L3_REMAP_MPUZERO_LSB   0

The Least Significant Bit (LSB) position of the ALT_L3_REMAP_MPUZERO register field.

#define ALT_L3_REMAP_MPUZERO_MSB   0

The Most Significant Bit (MSB) position of the ALT_L3_REMAP_MPUZERO register field.

#define ALT_L3_REMAP_MPUZERO_WIDTH   1

The width in bits of the ALT_L3_REMAP_MPUZERO register field.

#define ALT_L3_REMAP_MPUZERO_SET_MSK   0x00000001

The mask used to set the ALT_L3_REMAP_MPUZERO register field value.

#define ALT_L3_REMAP_MPUZERO_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L3_REMAP_MPUZERO register field value.

#define ALT_L3_REMAP_MPUZERO_RESET   0x0

The reset value of the ALT_L3_REMAP_MPUZERO register field.

#define ALT_L3_REMAP_MPUZERO_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L3_REMAP_MPUZERO field value from a register.

#define ALT_L3_REMAP_MPUZERO_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L3_REMAP_MPUZERO register field value suitable for setting the register.

#define ALT_L3_REMAP_NONMPUZERO_E_SDRAM   0x0

Enumerated value for register field ALT_L3_REMAP_NONMPUZERO

Maps the SDRAM to address 0x0 for the non-MPU L3 masters.

#define ALT_L3_REMAP_NONMPUZERO_E_OCRAM   0x1

Enumerated value for register field ALT_L3_REMAP_NONMPUZERO

Maps the On-chip RAM to address 0x0 for the non-MPU L3 masters. Note that the On-chip RAM is also always mapped to address 0xffff_0000 for the non-MPU L3 masters independent of this field's value.

#define ALT_L3_REMAP_NONMPUZERO_LSB   1

The Least Significant Bit (LSB) position of the ALT_L3_REMAP_NONMPUZERO register field.

#define ALT_L3_REMAP_NONMPUZERO_MSB   1

The Most Significant Bit (MSB) position of the ALT_L3_REMAP_NONMPUZERO register field.

#define ALT_L3_REMAP_NONMPUZERO_WIDTH   1

The width in bits of the ALT_L3_REMAP_NONMPUZERO register field.

#define ALT_L3_REMAP_NONMPUZERO_SET_MSK   0x00000002

The mask used to set the ALT_L3_REMAP_NONMPUZERO register field value.

#define ALT_L3_REMAP_NONMPUZERO_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L3_REMAP_NONMPUZERO register field value.

#define ALT_L3_REMAP_NONMPUZERO_RESET   0x0

The reset value of the ALT_L3_REMAP_NONMPUZERO register field.

#define ALT_L3_REMAP_NONMPUZERO_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L3_REMAP_NONMPUZERO field value from a register.

#define ALT_L3_REMAP_NONMPUZERO_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L3_REMAP_NONMPUZERO register field value suitable for setting the register.

#define ALT_L3_REMAP_H2F_E_INVISIBLE   0x0

Enumerated value for register field ALT_L3_REMAP_H2F

The HPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.

#define ALT_L3_REMAP_H2F_E_VISIBLE   0x1

Enumerated value for register field ALT_L3_REMAP_H2F

The HPS2FPGA AXI Bridge is visible to L3 masters.

#define ALT_L3_REMAP_H2F_LSB   3

The Least Significant Bit (LSB) position of the ALT_L3_REMAP_H2F register field.

#define ALT_L3_REMAP_H2F_MSB   3

The Most Significant Bit (MSB) position of the ALT_L3_REMAP_H2F register field.

#define ALT_L3_REMAP_H2F_WIDTH   1

The width in bits of the ALT_L3_REMAP_H2F register field.

#define ALT_L3_REMAP_H2F_SET_MSK   0x00000008

The mask used to set the ALT_L3_REMAP_H2F register field value.

#define ALT_L3_REMAP_H2F_CLR_MSK   0xfffffff7

The mask used to clear the ALT_L3_REMAP_H2F register field value.

#define ALT_L3_REMAP_H2F_RESET   0x0

The reset value of the ALT_L3_REMAP_H2F register field.

#define ALT_L3_REMAP_H2F_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_L3_REMAP_H2F field value from a register.

#define ALT_L3_REMAP_H2F_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_L3_REMAP_H2F register field value suitable for setting the register.

#define ALT_L3_REMAP_LWH2F_E_INVISIBLE   0x0

Enumerated value for register field ALT_L3_REMAP_LWH2F

The LWHPS2FPGA AXI Bridge is not visible to L3 masters. Accesses to the associated address range return an AXI decode error to the master.

#define ALT_L3_REMAP_LWH2F_E_VISIBLE   0x1

Enumerated value for register field ALT_L3_REMAP_LWH2F

The LWHPS2FPGA AXI Bridge is visible to L3 masters.

#define ALT_L3_REMAP_LWH2F_LSB   4

The Least Significant Bit (LSB) position of the ALT_L3_REMAP_LWH2F register field.

#define ALT_L3_REMAP_LWH2F_MSB   4

The Most Significant Bit (MSB) position of the ALT_L3_REMAP_LWH2F register field.

#define ALT_L3_REMAP_LWH2F_WIDTH   1

The width in bits of the ALT_L3_REMAP_LWH2F register field.

#define ALT_L3_REMAP_LWH2F_SET_MSK   0x00000010

The mask used to set the ALT_L3_REMAP_LWH2F register field value.

#define ALT_L3_REMAP_LWH2F_CLR_MSK   0xffffffef

The mask used to clear the ALT_L3_REMAP_LWH2F register field value.

#define ALT_L3_REMAP_LWH2F_RESET   0x0

The reset value of the ALT_L3_REMAP_LWH2F register field.

#define ALT_L3_REMAP_LWH2F_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_L3_REMAP_LWH2F field value from a register.

#define ALT_L3_REMAP_LWH2F_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_L3_REMAP_LWH2F register field value suitable for setting the register.

#define ALT_L3_REMAP_OFST   0x0

The byte offset of the ALT_L3_REMAP register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_L3_REMAP.