Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Register 472 (PPS0 Interval Register) - gmacgrp_pps0_interval

Description

The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0]).

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 PPS0 Output Signal Interval

Field : PPS0 Output Signal Interval - ppsint

These bits store the interval between the rising edges of PPS0 signal output in terms of units of sub-second increment value.

You need to program one value less than the required interval. For example, if the PTP reference clock is 50 MHz (period of 20ns), and desired interval between rising edges of PPS0 signal output is 100ns (that is, five units of sub-second increment value), then you should program value 4 (5 -1) in this register.

Field Access Macros:

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB   0
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB   31
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH   32
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK   0xffffffff
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK   0x00000000
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET   0x0
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_EMAC_GMAC_PPS0_INTERVAL_s
 

Macros

#define ALT_EMAC_GMAC_PPS0_INTERVAL_RESET   0x00000000
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST   0x760
 
#define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_PPS0_INTERVAL_s 
ALT_EMAC_GMAC_PPS0_INTERVAL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_PPS0_INTERVAL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL.

Data Fields
uint32_t ppsint: 32 PPS0 Output Signal Interval

Macro Definitions

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_WIDTH   32

The width in bits of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET_MSK   0xffffffff

The mask used to set the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_CLR_MSK   0x00000000

The mask used to clear the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT field value from a register.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_EMAC_GMAC_PPS0_INTERVAL_PPSINT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_PPS0_INTERVAL register.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_OFST   0x760

The byte offset of the ALT_EMAC_GMAC_PPS0_INTERVAL register from the beginning of the component.

#define ALT_EMAC_GMAC_PPS0_INTERVAL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS0_INTERVAL_OFST))

The address of the ALT_EMAC_GMAC_PPS0_INTERVAL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_PPS0_INTERVAL.