Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : sbcfg6

Description

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL
[23:16] RW 0x0 ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST
[31:24] RW 0x0 ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID

Field : cfg_period_dqstrk_interval

Inverval between two controller controlled periodic DQS tracking

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB   0
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB   15
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH   16
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : cfg_t_param_dqstrk_to_valid_last

DQS Tracking Rd to Valid timing for the last Rank

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB   16
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB   23
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH   8
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK   0x00ff0000
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK   0xff00ffff
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET(value)   (((value) & 0x00ff0000) >> 16)
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET(value)   (((value) << 16) & 0x00ff0000)
 

Field : cfg_t_param_dqstrk_to_valid

DQS Tracking Rd to Valid timing for Ranks other than the Last

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB   24
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB   31
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH   8
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK   0xff000000
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK   0x00ffffff
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET(value)   (((value) & 0xff000000) >> 24)
 
#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET(value)   (((value) << 24) & 0xff000000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_SBCFG6_s
 

Macros

#define ALT_IO48_HMC_MMR_SBCFG6_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_SBCFG6_OFST   0x74
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_SBCFG6_s 
ALT_IO48_HMC_MMR_SBCFG6_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_SBCFG6_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_SBCFG6.

Data Fields
uint32_t cfg_period_dqstrk_interval: 16 ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL
uint32_t cfg_t_param_dqstrk_to_valid_last: 8 ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST
uint32_t cfg_t_param_dqstrk_to_valid: 8 ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID

Macro Definitions

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET_MSK   0x0000ffff

The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_CLR_MSK   0xffff0000

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_PERIOD_DQSTRK_INTERVAL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_MSB   23

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_WIDTH   8

The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET_MSK   0x00ff0000

The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_CLR_MSK   0xff00ffff

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_GET (   value)    (((value) & 0x00ff0000) >> 16)

Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST_SET (   value)    (((value) << 16) & 0x00ff0000)

Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LAST register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_LSB   24

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_WIDTH   8

The width in bits of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET_MSK   0xff000000

The mask used to set the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_CLR_MSK   0x00ffffff

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_GET (   value)    (((value) & 0xff000000) >> 24)

Extracts the ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID_SET (   value)    (((value) << 24) & 0xff000000)

Produces a ALT_IO48_HMC_MMR_SBCFG6_CFG_T_PARAM_DQSTRK_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG6_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_SBCFG6 register.

#define ALT_IO48_HMC_MMR_SBCFG6_OFST   0x74

The byte offset of the ALT_IO48_HMC_MMR_SBCFG6 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG6.