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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register controls which ODT pin is asserted during reads or writes. Bits [1:0] control which ODT pin is asserted during to accesses to chip select 0, bits [3:2] which ODT pin is asserted during accesses to chip select 1. For example, a value of "1001" will cause ODT[0] to be asserted for accesses to CS[0], and ODT[1] to be asserted for access to CS[1] pin. Set this to "0001" if there is only one chip select available.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[3:0] | RW | Unknown | Write ODT Control |
[7:4] | RW | Unknown | Read ODT Control |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : Write ODT Control - cfg_write_odt_chip | |
This register controls which ODT pin is asserted during writes. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0) |
#define | ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f) |
Field : Read ODT Control - cfg_read_odt_chip | |
This register controls which ODT pin is asserted during reads. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4) |
#define | ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0) |
Data Structures | |
struct | ALT_SDR_CTL_DRAMODT_s |
Macros | |
#define | ALT_SDR_CTL_DRAMODT_OFST 0x18 |
Typedefs | |
typedef struct ALT_SDR_CTL_DRAMODT_s | ALT_SDR_CTL_DRAMODT_t |
struct ALT_SDR_CTL_DRAMODT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_DRAMODT.
Data Fields | ||
---|---|---|
uint32_t | cfg_write_odt_chip: 4 | Write ODT Control |
uint32_t | cfg_read_odt_chip: 4 | Read ODT Control |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f |
The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0 |
The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET | ( | value | ) | (((value) & 0x0000000f) >> 0) |
Extracts the ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP field value from a register.
#define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET | ( | value | ) | (((value) << 0) & 0x0000000f) |
Produces a ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0 |
The mask used to set the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f |
The mask used to clear the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET | ( | value | ) | (((value) & 0x000000f0) >> 4) |
Extracts the ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP field value from a register.
#define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET | ( | value | ) | (((value) << 4) & 0x000000f0) |
Produces a ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMODT_OFST 0x18 |
The byte offset of the ALT_SDR_CTL_DRAMODT register from the beginning of the component.
typedef struct ALT_SDR_CTL_DRAMODT_s ALT_SDR_CTL_DRAMODT_t |
The typedef declaration for register ALT_SDR_CTL_DRAMODT.