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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains settings that control Couner 5 clock generated from the Peripheral PLL VCO clock.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[10:0] | RW | 0x0 | Counter |
[15:11] | ??? | 0x0 | UNDEFINED |
[18:16] | RW | 0x0 | ALT_CLKMGR_PERPLL_CNTR5CLK_SRC |
[31:19] | ??? | 0x0 | UNDEFINED |
Field : Counter - cnt | |
Divides the VCO frequency by the value+1 in this field. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x0 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0) |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff) |
Data Structures | |
struct | ALT_CLKMGR_PERPLL_CNTR5CLK_s |
Macros | |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000000 |
#define | ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x34 |
Typedefs | |
typedef struct ALT_CLKMGR_PERPLL_CNTR5CLK_s | ALT_CLKMGR_PERPLL_CNTR5CLK_t |
struct ALT_CLKMGR_PERPLL_CNTR5CLK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK.
Data Fields | ||
---|---|---|
uint32_t | cnt: 11 | Counter |
uint32_t | __pad0__: 5 | UNDEFINED |
uint32_t | src: 3 | ALT_CLKMGR_PERPLL_CNTR5CLK_SRC |
uint32_t | __pad1__: 13 | UNDEFINED |
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11 |
The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff |
The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800 |
The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET | ( | value | ) | (((value) & 0x000007ff) >> 0) |
Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_CNT field value from a register.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET | ( | value | ) | (((value) << 0) & 0x000007ff) |
Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_CNT register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 0x2 |
Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC 0x3 |
Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA 0x4 |
Enumerated value for register field ALT_CLKMGR_PERPLL_CNTR5CLK_SRC
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_WIDTH 3 |
The width in bits of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET_MSK 0x00070000 |
The mask used to set the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_CLR_MSK 0xfff8ffff |
The mask used to clear the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_GET | ( | value | ) | (((value) & 0x00070000) >> 16) |
Extracts the ALT_CLKMGR_PERPLL_CNTR5CLK_SRC field value from a register.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET | ( | value | ) | (((value) << 16) & 0x00070000) |
Produces a ALT_CLKMGR_PERPLL_CNTR5CLK_SRC register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000000 |
The reset value of the ALT_CLKMGR_PERPLL_CNTR5CLK register.
#define ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x34 |
The byte offset of the ALT_CLKMGR_PERPLL_CNTR5CLK register from the beginning of the component.
typedef struct ALT_CLKMGR_PERPLL_CNTR5CLK_s ALT_CLKMGR_PERPLL_CNTR5CLK_t |
The typedef declaration for register ALT_CLKMGR_PERPLL_CNTR5CLK.