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alt_l2_p310.h
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36 
37 /*
38  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/alt_l2_p310.h#1 $
39  */
40 
41 #ifndef __ALT_L2_P310_H__
42 #define __ALT_L2_P310_H__
43 
44 #include <stdbool.h>
45 #include "socal/hps.h"
46 
47 #ifdef __cplusplus
48 extern "C"
49 {
50 #endif /* __cplusplus */
51 
52 /******************************************************************************/
53 // ARM Level 2 Cache Controller L2C-310 Register Interface
54 // These definitions should match the values given in DDI0246H_l2c310_r3p3_trm.pdf
55 // provided by ARM
56 
57 
58 // Cache ID Register
59 // The Cache ID Registers is a read only register
60 // Bits Field Description
61 // :-------|:--------------------------|:-----------------------------------------
62 // [31:24] | Implementer | ID of IP provider. Should be 0x41 (ARM)
63 // [23:16] | Reserved | SBZ/RAZ
64 // [15:10] | Cache ID |
65 // [9:6] | Part Number |
66 // [5:0] | RTL release |
67 // Cache ID Register Address
68 
69 #define ALT_L2_CACHE_ID_OFST 0x000
70 #define ALT_L2_CACHE_ID_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
71 // Cache ID Register - Implementer Mask
72 #define ALT_L2_CACHE_ID_IMPLEMENTER_MASK 0xFF000000
73 // Cache ID Register - Cache ID Mask
74 #define ALT_L2_CACHE_ID_CACHE_ID_MASK 0x0000FC00
75 // Cache ID Register - Part Number Mask
76 #define ALT_L2_CACHE_ID_PART_NUMBER_MASK 0x000003C0
77 // Cache ID Register - RTL Relase Mask
78 #define ALT_L2_CACHE_ID_RTL_RELEASE_MASK 0x0000003F
79 
80 #define ALT_L2_CACHE_TYPE_OFST 0x004
81 #define ALT_L2_CACHE_TYPE_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ID_OFST)
82 
83 // The Cache Control Register is a read and write register
84 // Bits Field Description
85 // :-------|:--------------------------|:-----------------------------------------
86 // [31:1] | Reservered | SBZ/RAZ
87 // [0] | L2 Cache Enable |
88 
89 // Cache Control Register Address
90 #define ALT_L2_CACHE_REG1_CNTRL_OFST 0x100
91 #define ALT_L2_CACHE_REG1_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_CNTRL_OFST)
92 // Cache Control Register - Enable
93 #define ALT_L2_CACHE_REG1_CNTRL_DISABLE 0x0
94 #define ALT_L2_CACHE_REG1_CNTRL_ENABLE 0x1
95 #define ALT_L2_CACHE_REG1_CNTRL_ENABLE_MASK 0x1
96 
97 // Aux Cache Control Register
98 // The Aux Cache Control Register is a read and write register
99 // Bits Field Description
100 // :-------|:--------------------------|:-----------------------------------------
101 // [31] | Reservered | SBZ/RAZ
102 // [30] | Early BRESP Enabled |
103 // [29] | Inst Prefetch Enable |
104 // [28] | Data Prefetch Enable |
105 // [27] | N/S Int Access Cntrl |
106 // [26] | N/S Lockdown Enable |
107 // [25] | Cache Replacement Policy |
108 // [24:23] | Force Write Allocate |
109 // [22] | Shared Attr Override En |
110 // [21] | Parity Enable |
111 // [20] | Event Monitor Bus Enable |
112 // [19:17] | Way Size |
113 // [16] | Associativity |
114 // [15:14] | Reserved |
115 // [13] | Shared Attribute Inv En |
116 // [12] | Exclusive Cache Config |
117 // [11] | Store Buffer Dev Limit En |
118 // [10] | High Priority for SO En |
119 // [9:1] | Reserved |
120 // [0] | Full Line of Zero En |
121 
122 // Aux Cache Control Register Address
123 #define ALT_L2_CACHE_REG1_AUX_CNTRL_OFST 0x104
124 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_AUX_CNTRL_OFST)
125 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_EN_MASK 0x40000000
126 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_ENABLE 0x40000000
127 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EARLY_BRESP_DISABLE 0
128 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_EN_MASK 0x20000000
129 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_ENABLE 0x20000000
130 #define ALT_L2_CACHE_REG1_AUX_CNTRL_INST_PREFETCH_DISABLE 0
131 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_EN_MASK 0x10000000
132 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_ENABLE 0x10000000
133 #define ALT_L2_CACHE_REG1_AUX_CNTRL_DATA_PREFETCH_DISABLE 0
134 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_MASK 0x08000000
135 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_ENABLE 0x08000000
136 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_INT_ACC_CNTRL_DISABLE 0
137 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_EN_MASK 0x04000000
138 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_ENABLE 0x04000000
139 #define ALT_L2_CACHE_REG1_AUX_CNTRL_NS_LOCKDOWN_DISABLE 0
140 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_MASK 0x02000000
141 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RANDOM 0
142 #define ALT_L2_CACHE_REG1_AUX_CNTRL_CACHE_REPL_POL_RR 0x02000000
143 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_MASK 0x01800000
144 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_AWCACHE 0
145 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA0 0x00800000
146 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_WA1 0x01000000
147 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FORCE_WRITE_ALLOC_00 0x01800000
148 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_EN_MASK 0x00400000
149 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_ENABLE 0x00400000
150 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHARED_ATTR_OVERRIDE_DISABLE 0
151 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_EN_MASK 0x00200000
152 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_ENABLE 0x00200000
153 #define ALT_L2_CACHE_REG1_AUX_CNTRL_PARITY_DISABLE 0
154 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_EN_MASK 0x00100000
155 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_ENABLE 0x00100000
156 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EVENT_MNTR_BUS_DISABLE 0
157 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_MASK 0x000E0000
158 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_16KB 0x00020000
159 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_32KB 0x00040000
160 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_64KB 0x00060000
161 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_128KB 0x00080000
162 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_256B 0x000A0000
163 #define ALT_L2_CACHE_REG1_AUX_CNTRL_WAY_SIZE_512KB 0x000C0000
164 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_MASK 0x00010000
165 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_8WAY 0
166 #define ALT_L2_CACHE_REG1_AUX_CNTRL_ASSOCIATIVITY_16WAY 0x00010000
167 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_EN_MASK 0x00002000
168 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_ENABLE 0x00002000
169 #define ALT_L2_CACHE_REG1_AUX_CNTRL_SHAR_ATTR_INV_DISABLE 0
170 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_MASK 0x00001000
171 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_ENABLE 0x00001000
172 #define ALT_L2_CACHE_REG1_AUX_CNTRL_EXCL_CACHE_CFG_DISABLE 0
173 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_EN_MASK 0x00000800
174 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_ENABLE 0x00000800
175 #define ALT_L2_CACHE_REG1_AUX_CNTRL_STOR_BUFF_DEV_LIM_DISABLE 0
176 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_EN_MASK 0x00000400
177 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_ENABLE 0x00000400
178 #define ALT_L2_CACHE_REG1_AUX_CNTRL_H_PRI_SO_DEV_RD_DISABLE 0
179 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_EN_MASK 0x1
180 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_ENABLE 0x1
181 #define ALT_L2_CACHE_REG1_AUX_CNTRL_FULL_LINE_0_DISABLE 0
182 
183 // Tag and Data RAM Latency Control Register
184 // The Tag and Data RAM Latency Control Register is a read and write register
185 // Bits Field Description
186 // :-------|:--------------------------|:-----------------------------------------
187 // [31:11] | Reservered | SBZ/RAZ
188 // [10:8] | RAM Write Access Latency |
189 // [7] | Reserved |
190 // [10:8] | RAM Read Access Latency |
191 // [3] | Reserved |
192 // [2:0] | RAM Setup Latency |
193 
194 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST 0x108
195 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_OFST)
196 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_MASK 0x00000700
197 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_1 0x00000000
198 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_2 0x00000100
199 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_3 0x00000200
200 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_4 0x00000300
201 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_5 0x00000400
202 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_6 0x00000500
203 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_7 0x00000600
204 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_8 0x00000700
205 
206 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_MASK 0x00000070
207 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_1 0x00000000
208 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_2 0x00000010
209 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_3 0x00000020
210 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_4 0x00000030
211 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_5 0x00000040
212 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_6 0x00000050
213 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_7 0x00000060
214 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_8 0x00000070
215 
216 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_MASK 0x00000007
217 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_1 0x00000000
218 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_2 0x00000001
219 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_3 0x00000002
220 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_4 0x00000003
221 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_5 0x00000004
222 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_6 0x00000005
223 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_7 0x00000006
224 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_8 0x00000007
225 
226 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_WRITE_LATENCY_LSB 8
227 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_READ_LATENCY_LSB 4
228 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_SETUP_LATENCY_LSB 0
229 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_1 0x00000000
230 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_2 0x00000001
231 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_3 0x00000002
232 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_4 0x00000003
233 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_5 0x00000004
234 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_6 0x00000005
235 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_7 0x00000006
236 #define ALT_L2_CACHE_REG1_TAG_RAM_CNTRL_LATENCY_8 0x00000007
237 
238 #define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST 0x10C
239 #define ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_DATA_RAM_CNTRL_OFST)
240 
241 // Event Counter Control Register
242 // Bits Field Description
243 // :-------|:--------------------------|:-----------------------------------------
244 // [31:3] | Reservered | SBZ/RAZ
245 // [2:1] | Counter Reset |
246 // [0] | Event Counter Enable |
247 
248 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_OFST 0x200
249 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT_CNTRL_OFST)
250 
251 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_MASK 0x00000006
252 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_0 0x00000002
253 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_RESET_1 0x00000004
254 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_EN_MASK 1
255 // Enable Counter
256 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_ENABLE 1
257 #define ALT_L2_CACHE_REG2_EV_CNT_CNTRL_DISABLE 0
258 
259 
260 // Event Counter Configuration Registers
261 // Bits Field Description
262 // :-------|:--------------------------|:-----------------------------------------
263 // [31:6] | Reservered | SBZ/RAZ
264 // [5:2] | Counter Event Source |
265 // [1:0] | Event Counter Interupt En |
266 
267 // Event Counter Configuration Register Addresses
268 #define ALT_L2_CACHE_REG2_EV_CNT1_CFG_OFST 0x204
269 #define ALT_L2_CACHE_REG2_EV_CNT1_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT1_CFG_OFST)
270 #define ALT_L2_CACHE_REG2_EV_CNT0_CFG_OFST 0x208
271 #define ALT_L2_CACHE_REG2_EV_CNT0_CFG_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG1_EV_CNT0_CFG_OFST)
272 
273 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_MASK 0x0000003C
274 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DISABLE 0x00000000
275 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_CO 0x00000004
276 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRHIT 0x00000008
277 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DRREQ 0x0000000C
278 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWHIT 0x00000010
279 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWREQ 0x00000014
280 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_DWTREQ 0x00000018
281 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRHIT 0x0000001C
282 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IRREQ 0x00000020
283 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_WA 0x00000024
284 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_IPFALLOC 0x00000028
285 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFHIT 0x0000002C
286 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFALLOC 0x00000030
287 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRRCVD 0x00000034
288 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_SRCONF 0x00000038
289 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_SRC_EPFRCVD 0x0000003C
290 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_MASK 0x3
291 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_DISABLED 0
292 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_INC 0x00000001
293 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_ENABLE_OF 0x00000002
294 #define ALT_L2_CACHE_REG2_EV_CNT_CFG_INT_GEN_DIS 0x00000003
295 
296 
297 // Event Counter Registers
298 #define ALT_L2_CACHE_REG2_EV_CNT1_OFST 0x20C
299 #define ALT_L2_CACHE_REG2_EV_CNT1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT1_OFST)
300 #define ALT_L2_CACHE_REG2_EV_CNT0_OFST 0x210
301 #define ALT_L2_CACHE_REG2_EV_CNT0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_EV_CNT0_OFST)
302 
303 // Interrupt Registers. The following defines are used for the next several registers
304 // Bits Field Description
305 // :-------|:--------------------------|:-----------------------------------------
306 // [31:9] | Reservered | SBZ/RAZ
307 // [8] | DECERR |
308 // [7] | SLVERR |
309 // [6] | ERRRD |
310 // [5] | ERRRT |
311 // [4] | ERRWD |
312 // [3] | ERRWT |
313 // [2] | PARRD |
314 // [1] | PARRT |
315 // [0] | ECNTR |
316 
317 #define ALT_L2_CACHE_REG2_INT_DECERR 0x100
318 #define ALT_L2_CACHE_REG2_INT_SLVERR 0x080
319 #define ALT_L2_CACHE_REG2_INT_ERRRD 0x040
320 #define ALT_L2_CACHE_REG2_INT_ERRRT 0x020
321 #define ALT_L2_CACHE_REG2_INT_ERRWD 0x010
322 #define ALT_L2_CACHE_REG2_INT_ERRWT 0x008
323 #define ALT_L2_CACHE_REG2_INT_PARRD 0x004
324 #define ALT_L2_CACHE_REG2_INT_PARRT 0x002
325 #define ALT_L2_CACHE_REG2_INT_ECNTR 0x001
326 
327 // Interrupt Enable Mask Register
328 // See "Interrupt Registers" above
329 #define ALT_L2_CACHE_REG2_INT_MASK_OFST 0x214
330 #define ALT_L2_CACHE_REG2_INT_MASK_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_OFST)
331 
332 // Interrupt Status Register (Should be RAW_STATUS & INT_MASK
333 // See "Interrupt Registers" above
334 #define ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST 0x218
335 #define ALT_L2_CACHE_REG2_INT_MASK_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_MASK_STATUS_OFST)
336 
337 // Interrupt Raw Status Register (Excludes Masks)
338 // See "Interrupt Registers" above
339 #define ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST 0x21C
340 #define ALT_L2_CACHE_REG2_INT_RAW_STATUS_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_RAW_STATUS_OFST)
341 
342 // Interrupt Clear Status Register
343 // See "Interrupt Registers" above
344 #define ALT_L2_CACHE_REG2_INT_CLEAR_OFST 0x220
345 #define ALT_L2_CACHE_REG2_INT_CLEAR_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG2_INT_CLEAR_OFST)
346 
347 // PA Format
348 // Bits Field Description
349 // :-------|:--------------------------|:-----------------------------------------
350 // [31:12] | Tag |
351 // [11:5] | Index |
352 // [4:1] | Reserved |
353 // [0] | Complete |
354 
355 // Index or Way Format
356 // Bits Field Description
357 // :-------|:--------------------------|:-----------------------------------------
358 // [31:28] | Way |
359 // [27:12] | Reserved |
360 // [11:5] | Index |
361 // [4:1] | Reserved |
362 // [0] | Complete |
363 
364 // Way Format
365 // Bits Field Description
366 // :-------|:--------------------------|:-----------------------------------------
367 // [31:16] | Reserved |
368 // [15:0] | Way Bits |
369 
370 // Cache Sync Register
371 // Bits Field Description
372 // :-------|:--------------------------|:-----------------------------------------
373 // [31:1] | Reserved |
374 // [0] | Complete |
375 #define ALT_L2_CACHE_REG7_CACHE_SYNC_OFST 0x730
376 #define ALT_L2_CACHE_REG7_CACHE_SYNC_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CACHE_SYNC_OFST)
377 
378 // Invalidate Line by Physical Address
379 // See the "PA Format" above for description of the fields of this register
380 #define ALT_L2_CACHE_REG7_INV_PA_OFST 0x770
381 #define ALT_L2_CACHE_REG7_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_PA_OFST)
382 
383 // Invalidate Line by Way
384 // See the "Way Format" above for description of the fields of this register
385 #define ALT_L2_CACHE_REG7_INV_WAY_OFST 0x77C
386 #define ALT_L2_CACHE_REG7_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_INV_WAY_OFST)
387 
388 // Clean Line by Physical Address
389 // See the "PA Format" above for description of the fields of this register
390 #define ALT_L2_CACHE_REG7_CLEAN_PA_OFST 0x7B0
391 #define ALT_L2_CACHE_REG7_CLEAN_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_PA_OFST)
392 
393 // Clean Line by Set/Way
394 // See the "Index or Way Format" above for a description of the fields of this register
395 #define ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST 0x7B8
396 #define ALT_L2_CACHE_REG7_CLEAN_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INDEX_OFST)
397 
398 // Invalidate Line by Way
399 // See the "Way Format" above for description of the fields of this register
400 #define ALT_L2_CACHE_REG7_CLEAN_WAY_OFST 0x7BC
401 #define ALT_L2_CACHE_REG7_CLEAN_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_WAY_OFST)
402 
403 // Clean and Invalidate Line by Physical Address
404 // See the "PA Format" above for description of the fields of this register
405 #define ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST 0x7F0
406 #define ALT_L2_CACHE_REG7_CLEAN_INV_PA_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_PA_OFST)
407 
408 // Clean and Invalidate Line by Set/Way
409 // See the "Index or Way Format" above for a description of the fields of this register
410 #define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST 0x7F8
411 #define ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_INDEX_OFST)
412 
413 // Invalidate Line by Way
414 // See the "Way Format" above for description of the fields of this register
415 #define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST 0x7FC
416 #define ALT_L2_CACHE_REG7_CLEAN_INV_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG7_CLEAN_INV_WAY_OFST)
417 
418 // Lockdown Registers
419 // The format for each of these lockdown registers is the same
420 // Bits Field Description
421 // :-------|:--------------------------|:-----------------------------------------
422 // [31:16] | Reserved |
423 // [15:0] | Way Bits |
424 
425 
426 #define ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X) (0x900 + (X)*0x10)
427 #define ALT_L2_CACHE_REG9_D_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN_OFST(X))
428 
429 #define ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X) (0x904 + (X)*0x10)
430 #define ALT_L2_CACHE_REG9_I_LOCKDOWN_ADDR(X) (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN_OFST(X))
431 
432 #define ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST 0x900
433 #define ALT_L2_CACHE_REG9_D_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN0_OFST)
434 
435 #define ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST 0x904
436 #define ALT_L2_CACHE_REG9_I_LOCKDOWN0_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN0_OFST)
437 
438 #define ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST 0x908
439 #define ALT_L2_CACHE_REG9_D_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN1_OFST)
440 
441 #define ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST 0x90C
442 #define ALT_L2_CACHE_REG9_I_LOCKDOWN1_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN1_OFST)
443 
444 #define ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST 0x910
445 #define ALT_L2_CACHE_REG9_D_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN2_OFST)
446 
447 #define ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST 0x914
448 #define ALT_L2_CACHE_REG9_I_LOCKDOWN2_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN2_OFST)
449 
450 #define ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST 0x918
451 #define ALT_L2_CACHE_REG9_D_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN3_OFST)
452 
453 #define ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST 0x91C
454 #define ALT_L2_CACHE_REG9_I_LOCKDOWN3_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN3_OFST)
455 
456 #define ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST 0x920
457 #define ALT_L2_CACHE_REG9_D_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN4_OFST)
458 
459 #define ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST 0x924
460 #define ALT_L2_CACHE_REG9_I_LOCKDOWN4_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN4_OFST)
461 
462 #define ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST 0x928
463 #define ALT_L2_CACHE_REG9_D_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN5_OFST)
464 
465 #define ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST 0x92C
466 #define ALT_L2_CACHE_REG9_I_LOCKDOWN5_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN5_OFST)
467 
468 #define ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST 0x930
469 #define ALT_L2_CACHE_REG9_D_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN6_OFST)
470 
471 #define ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST 0x934
472 #define ALT_L2_CACHE_REG9_I_LOCKDOWN6_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN6_OFST)
473 
474 #define ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST 0x938
475 #define ALT_L2_CACHE_REG9_D_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_D_LOCKDOWN7_OFST)
476 
477 #define ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST 0x93C
478 #define ALT_L2_CACHE_REG9_I_LOCKDOWN7_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_I_LOCKDOWN7_OFST)
479 
480 // Lockdown by Line Enable
481 // Bits Field Description
482 // :-------|:--------------------------|:-----------------------------------------
483 // [31:1] | Reserved |
484 // [0] | Enable |
485 
486 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST 0x950
487 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_LOCK_LINE_EN_OFST)
488 #define ALT_L2_CACHE_REG9_LOCK_LINE_EN_MASK 0x00000001
489 #define ALT_L2_CACHE_REG9_LOCK_LINE_ENABLE 0x00000001
490 #define ALT_L2_CACHE_REG9_LOCK_LINE_DISABLE 0
491 
492 #define ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST 0x954
493 #define ALT_L2_CACHE_REG9_UNLOCK_WAY_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_REG9_UNLOCK_WAY_OFST)
494 
495 // Address Filtering Start Register
496 // The Address Filtering Start Register is a read and write register.
497 // Bits Field Description
498 // :-------|:--------------------------|:-----------------------------------------
499 // [31:20] | address_filtering_start | Address filtering start address for
500 // | | bits [31:20] of the filtering address.
501 // [19:1] | Reserved | SBZ/RAZ
502 // [0] | address_filtering_enable | 0 - address filtering disabled
503 // | | 1 - address filtering enabled.
504 
505 // Address Filtering Start Register Address
506 #define ALT_L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
507 #define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ADDR_FILTERING_START_OFST)
508 // Address Filtering Start Register - Start Value Mask
509 #define ALT_L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
510 // Address Filtering Start Register - Reset Start Address Value (1 MB)
511 #define ALT_L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
512 // Address Filtering Start Register - Enable Flag Mask
513 #define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
514 // Address Filtering Start Register - Reset Enable Flag Value (Enabled)
515 #define ALT_L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
516 
517 // Address Filtering End Register
518 // The Address Filtering End Register is a read and write register.
519 // Bits Field Description
520 // :-------|:--------------------------|:-----------------------------------------
521 // [31:20] | address_filtering_end | Address filtering end address for bits
522 // | | [31:20] of the filtering address.
523 // [19:0] | Reserved | SBZ/RAZ
524 
525 // Address Filtering End Register Address
526 #define ALT_L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
527 #define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + ALT_L2_CACHE_ADDR_FILTERING_END_OFST)
528 // Address Filtering End Register - End Value Mask
529 #define ALT_L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
530 // Address Filtering End Register - Reset End Address Value (3 GiB)
531 #define ALT_L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
532 
533 #ifdef __cplusplus
534 }
535 #endif /* __cplusplus */
536 #endif /* __ALT_L2_P310_H__ */