Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_spim.h
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32 
35 #ifndef __ALT_SOCAL_SPIM_H__
36 #define __ALT_SOCAL_SPIM_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
121 #define ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT 0x3
122 
127 #define ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT 0x4
128 
133 #define ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT 0x5
134 
139 #define ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT 0x6
140 
145 #define ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT 0x7
146 
151 #define ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT 0x8
152 
157 #define ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT 0x9
158 
163 #define ALT_SPIM_CTLR0_DFS_E_WIDTH11BIT 0xa
164 
169 #define ALT_SPIM_CTLR0_DFS_E_WIDTH12BIT 0xb
170 
175 #define ALT_SPIM_CTLR0_DFS_E_WIDTH13BIT 0xc
176 
181 #define ALT_SPIM_CTLR0_DFS_E_WIDTH14BIT 0xd
182 
187 #define ALT_SPIM_CTLR0_DFS_E_WIDTH15BIT 0xe
188 
193 #define ALT_SPIM_CTLR0_DFS_E_WIDTH16BIT 0xf
194 
196 #define ALT_SPIM_CTLR0_DFS_LSB 0
197 
198 #define ALT_SPIM_CTLR0_DFS_MSB 3
199 
200 #define ALT_SPIM_CTLR0_DFS_WIDTH 4
201 
202 #define ALT_SPIM_CTLR0_DFS_SET_MSK 0x0000000f
203 
204 #define ALT_SPIM_CTLR0_DFS_CLR_MSK 0xfffffff0
205 
206 #define ALT_SPIM_CTLR0_DFS_RESET 0x7
207 
208 #define ALT_SPIM_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
209 
210 #define ALT_SPIM_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
211 
243 #define ALT_SPIM_CTLR0_FRF_E_MOTSPI 0x0
244 
249 #define ALT_SPIM_CTLR0_FRF_E_TISSP 0x1
250 
255 #define ALT_SPIM_CTLR0_FRF_E_NATMW 0x2
256 
258 #define ALT_SPIM_CTLR0_FRF_LSB 4
259 
260 #define ALT_SPIM_CTLR0_FRF_MSB 5
261 
262 #define ALT_SPIM_CTLR0_FRF_WIDTH 2
263 
264 #define ALT_SPIM_CTLR0_FRF_SET_MSK 0x00000030
265 
266 #define ALT_SPIM_CTLR0_FRF_CLR_MSK 0xffffffcf
267 
268 #define ALT_SPIM_CTLR0_FRF_RESET 0x0
269 
270 #define ALT_SPIM_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
271 
272 #define ALT_SPIM_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
273 
310 #define ALT_SPIM_CTLR0_SCPH_E_MIDBIT 0x0
311 
316 #define ALT_SPIM_CTLR0_SCPH_E_STARTBIT 0x1
317 
319 #define ALT_SPIM_CTLR0_SCPH_LSB 6
320 
321 #define ALT_SPIM_CTLR0_SCPH_MSB 6
322 
323 #define ALT_SPIM_CTLR0_SCPH_WIDTH 1
324 
325 #define ALT_SPIM_CTLR0_SCPH_SET_MSK 0x00000040
326 
327 #define ALT_SPIM_CTLR0_SCPH_CLR_MSK 0xffffffbf
328 
329 #define ALT_SPIM_CTLR0_SCPH_RESET 0x0
330 
331 #define ALT_SPIM_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
332 
333 #define ALT_SPIM_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
334 
365 #define ALT_SPIM_CTLR0_SCPOL_E_INACTLOW 0x0
366 
371 #define ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH 0x1
372 
374 #define ALT_SPIM_CTLR0_SCPOL_LSB 7
375 
376 #define ALT_SPIM_CTLR0_SCPOL_MSB 7
377 
378 #define ALT_SPIM_CTLR0_SCPOL_WIDTH 1
379 
380 #define ALT_SPIM_CTLR0_SCPOL_SET_MSK 0x00000080
381 
382 #define ALT_SPIM_CTLR0_SCPOL_CLR_MSK 0xffffff7f
383 
384 #define ALT_SPIM_CTLR0_SCPOL_RESET 0x0
385 
386 #define ALT_SPIM_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
387 
388 #define ALT_SPIM_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
389 
442 #define ALT_SPIM_CTLR0_TMOD_E_TXRX 0x0
443 
448 #define ALT_SPIM_CTLR0_TMOD_E_TXONLY 0x1
449 
454 #define ALT_SPIM_CTLR0_TMOD_E_RXONLY 0x2
455 
460 #define ALT_SPIM_CTLR0_TMOD_E_EERD 0x3
461 
463 #define ALT_SPIM_CTLR0_TMOD_LSB 8
464 
465 #define ALT_SPIM_CTLR0_TMOD_MSB 9
466 
467 #define ALT_SPIM_CTLR0_TMOD_WIDTH 2
468 
469 #define ALT_SPIM_CTLR0_TMOD_SET_MSK 0x00000300
470 
471 #define ALT_SPIM_CTLR0_TMOD_CLR_MSK 0xfffffcff
472 
473 #define ALT_SPIM_CTLR0_TMOD_RESET 0x0
474 
475 #define ALT_SPIM_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
476 
477 #define ALT_SPIM_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
478 
507 #define ALT_SPIM_CTLR0_SRL_E_NORMMOD 0x0
508 
513 #define ALT_SPIM_CTLR0_SRL_E_TESTMOD 0x1
514 
516 #define ALT_SPIM_CTLR0_SRL_LSB 11
517 
518 #define ALT_SPIM_CTLR0_SRL_MSB 11
519 
520 #define ALT_SPIM_CTLR0_SRL_WIDTH 1
521 
522 #define ALT_SPIM_CTLR0_SRL_SET_MSK 0x00000800
523 
524 #define ALT_SPIM_CTLR0_SRL_CLR_MSK 0xfffff7ff
525 
526 #define ALT_SPIM_CTLR0_SRL_RESET 0x0
527 
528 #define ALT_SPIM_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
529 
530 #define ALT_SPIM_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
531 
568 #define ALT_SPIM_CTLR0_CFS_E_SIZE1BIT 0x0
569 
574 #define ALT_SPIM_CTLR0_CFS_E_SIZE2BIT 0x1
575 
580 #define ALT_SPIM_CTLR0_CFS_E_SIZE3BIT 0x2
581 
586 #define ALT_SPIM_CTLR0_CFS_E_SIZE4BIT 0x3
587 
592 #define ALT_SPIM_CTLR0_CFS_E_SIZE5BIT 0x4
593 
598 #define ALT_SPIM_CTLR0_CFS_E_SIZE6BIT 0x05
599 
604 #define ALT_SPIM_CTLR0_CFS_E_SIZE7BIT 0x6
605 
610 #define ALT_SPIM_CTLR0_CFS_E_SIZE8BIT 0x7
611 
616 #define ALT_SPIM_CTLR0_CFS_E_SIZE9BIT 0x8
617 
622 #define ALT_SPIM_CTLR0_CFS_E_SIZE10BIT 0x9
623 
628 #define ALT_SPIM_CTLR0_CFS_E_SIZE11BIT 0xa
629 
634 #define ALT_SPIM_CTLR0_CFS_E_SIZE12BIT 0xb
635 
640 #define ALT_SPIM_CTLR0_CFS_E_SIZE13BIT 0xc
641 
646 #define ALT_SPIM_CTLR0_CFS_E_SIZE14BIT 0xd
647 
652 #define ALT_SPIM_CTLR0_CFS_E_SIZE15BIT 0xe
653 
658 #define ALT_SPIM_CTLR0_CFS_E_SIZE16BIT 0xf
659 
661 #define ALT_SPIM_CTLR0_CFS_LSB 12
662 
663 #define ALT_SPIM_CTLR0_CFS_MSB 15
664 
665 #define ALT_SPIM_CTLR0_CFS_WIDTH 4
666 
667 #define ALT_SPIM_CTLR0_CFS_SET_MSK 0x0000f000
668 
669 #define ALT_SPIM_CTLR0_CFS_CLR_MSK 0xffff0fff
670 
671 #define ALT_SPIM_CTLR0_CFS_RESET 0x0
672 
673 #define ALT_SPIM_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
674 
675 #define ALT_SPIM_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
676 
677 #ifndef __ASSEMBLY__
678 
689 {
690  uint32_t dfs : 4;
691  uint32_t frf : 2;
692  uint32_t scph : 1;
693  uint32_t scpol : 1;
694  uint32_t tmod : 2;
695  uint32_t : 1;
696  uint32_t srl : 1;
697  uint32_t cfs : 4;
698  uint32_t : 16;
699 };
700 
702 typedef volatile struct ALT_SPIM_CTLR0_s ALT_SPIM_CTLR0_t;
703 #endif /* __ASSEMBLY__ */
704 
706 #define ALT_SPIM_CTLR0_RESET 0x00000007
707 
708 #define ALT_SPIM_CTLR0_OFST 0x0
709 
710 #define ALT_SPIM_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR0_OFST))
711 
765 #define ALT_SPIM_CTLR1_NDF_LSB 0
766 
767 #define ALT_SPIM_CTLR1_NDF_MSB 15
768 
769 #define ALT_SPIM_CTLR1_NDF_WIDTH 16
770 
771 #define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff
772 
773 #define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000
774 
775 #define ALT_SPIM_CTLR1_NDF_RESET 0x0
776 
777 #define ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
778 
779 #define ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
780 
781 #ifndef __ASSEMBLY__
782 
793 {
794  uint32_t ndf : 16;
795  uint32_t : 16;
796 };
797 
799 typedef volatile struct ALT_SPIM_CTLR1_s ALT_SPIM_CTLR1_t;
800 #endif /* __ASSEMBLY__ */
801 
803 #define ALT_SPIM_CTLR1_RESET 0x00000000
804 
805 #define ALT_SPIM_CTLR1_OFST 0x4
806 
807 #define ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST))
808 
854 #define ALT_SPIM_SPIENR_SPI_EN_E_DISD 0x0
855 
860 #define ALT_SPIM_SPIENR_SPI_EN_E_END 0x1
861 
863 #define ALT_SPIM_SPIENR_SPI_EN_LSB 0
864 
865 #define ALT_SPIM_SPIENR_SPI_EN_MSB 0
866 
867 #define ALT_SPIM_SPIENR_SPI_EN_WIDTH 1
868 
869 #define ALT_SPIM_SPIENR_SPI_EN_SET_MSK 0x00000001
870 
871 #define ALT_SPIM_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
872 
873 #define ALT_SPIM_SPIENR_SPI_EN_RESET 0x0
874 
875 #define ALT_SPIM_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
876 
877 #define ALT_SPIM_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
878 
879 #ifndef __ASSEMBLY__
880 
891 {
892  uint32_t spi_en : 1;
893  uint32_t : 31;
894 };
895 
897 typedef volatile struct ALT_SPIM_SPIENR_s ALT_SPIM_SPIENR_t;
898 #endif /* __ASSEMBLY__ */
899 
901 #define ALT_SPIM_SPIENR_RESET 0x00000000
902 
903 #define ALT_SPIM_SPIENR_OFST 0x8
904 
905 #define ALT_SPIM_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPIENR_OFST))
906 
964 #define ALT_SPIM_MWCR_MWMOD_E_NONSEQ 0x0
965 
970 #define ALT_SPIM_MWCR_MWMOD_E_SEQ 0x1
971 
973 #define ALT_SPIM_MWCR_MWMOD_LSB 0
974 
975 #define ALT_SPIM_MWCR_MWMOD_MSB 0
976 
977 #define ALT_SPIM_MWCR_MWMOD_WIDTH 1
978 
979 #define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
980 
981 #define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
982 
983 #define ALT_SPIM_MWCR_MWMOD_RESET 0x0
984 
985 #define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
986 
987 #define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
988 
1019 #define ALT_SPIM_MWCR_MDD_E_RXMOD 0x0
1020 
1025 #define ALT_SPIM_MWCR_MDD_E_TXMOD 0x1
1026 
1028 #define ALT_SPIM_MWCR_MDD_LSB 1
1029 
1030 #define ALT_SPIM_MWCR_MDD_MSB 1
1031 
1032 #define ALT_SPIM_MWCR_MDD_WIDTH 1
1033 
1034 #define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
1035 
1036 #define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
1037 
1038 #define ALT_SPIM_MWCR_MDD_RESET 0x0
1039 
1040 #define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
1041 
1042 #define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
1043 
1080 #define ALT_SPIM_MWCR_MHS_E_DISD 0x0
1081 
1086 #define ALT_SPIM_MWCR_MHS_E_END 0x1
1087 
1089 #define ALT_SPIM_MWCR_MHS_LSB 2
1090 
1091 #define ALT_SPIM_MWCR_MHS_MSB 2
1092 
1093 #define ALT_SPIM_MWCR_MHS_WIDTH 1
1094 
1095 #define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
1096 
1097 #define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
1098 
1099 #define ALT_SPIM_MWCR_MHS_RESET 0x0
1100 
1101 #define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
1102 
1103 #define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
1104 
1105 #ifndef __ASSEMBLY__
1106 
1117 {
1118  uint32_t mwmod : 1;
1119  uint32_t mdd : 1;
1120  uint32_t mhs : 1;
1121  uint32_t : 29;
1122 };
1123 
1125 typedef volatile struct ALT_SPIM_MWCR_s ALT_SPIM_MWCR_t;
1126 #endif /* __ASSEMBLY__ */
1127 
1129 #define ALT_SPIM_MWCR_RESET 0x00000000
1130 
1131 #define ALT_SPIM_MWCR_OFST 0xc
1132 
1133 #define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
1134 
1204 #define ALT_SPIM_SER_SER_E_NOTSELECTED 0x0
1205 
1210 #define ALT_SPIM_SER_SER_E_SELECTED 0x1
1211 
1213 #define ALT_SPIM_SER_SER_LSB 0
1214 
1215 #define ALT_SPIM_SER_SER_MSB 3
1216 
1217 #define ALT_SPIM_SER_SER_WIDTH 4
1218 
1219 #define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
1220 
1221 #define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
1222 
1223 #define ALT_SPIM_SER_SER_RESET 0x0
1224 
1225 #define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
1226 
1227 #define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
1228 
1229 #ifndef __ASSEMBLY__
1230 
1241 {
1242  uint32_t ser : 4;
1243  uint32_t : 28;
1244 };
1245 
1247 typedef volatile struct ALT_SPIM_SER_s ALT_SPIM_SER_t;
1248 #endif /* __ASSEMBLY__ */
1249 
1251 #define ALT_SPIM_SER_RESET 0x00000000
1252 
1253 #define ALT_SPIM_SER_OFST 0x10
1254 
1255 #define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
1256 
1311 #define ALT_SPIM_BAUDR_SCKDV_LSB 0
1312 
1313 #define ALT_SPIM_BAUDR_SCKDV_MSB 15
1314 
1315 #define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
1316 
1317 #define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
1318 
1319 #define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
1320 
1321 #define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
1322 
1323 #define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
1324 
1325 #define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
1326 
1327 #ifndef __ASSEMBLY__
1328 
1339 {
1340  uint32_t sckdv : 16;
1341  uint32_t : 16;
1342 };
1343 
1345 typedef volatile struct ALT_SPIM_BAUDR_s ALT_SPIM_BAUDR_t;
1346 #endif /* __ASSEMBLY__ */
1347 
1349 #define ALT_SPIM_BAUDR_RESET 0x00000000
1350 
1351 #define ALT_SPIM_BAUDR_OFST 0x14
1352 
1353 #define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
1354 
1395 #define ALT_SPIM_TXFTLR_TFT_LSB 0
1396 
1397 #define ALT_SPIM_TXFTLR_TFT_MSB 7
1398 
1399 #define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1400 
1401 #define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1402 
1403 #define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1404 
1405 #define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1406 
1407 #define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1408 
1409 #define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1410 
1411 #ifndef __ASSEMBLY__
1412 
1423 {
1424  uint32_t tft : 8;
1425  uint32_t : 24;
1426 };
1427 
1429 typedef volatile struct ALT_SPIM_TXFTLR_s ALT_SPIM_TXFTLR_t;
1430 #endif /* __ASSEMBLY__ */
1431 
1433 #define ALT_SPIM_TXFTLR_RESET 0x00000000
1434 
1435 #define ALT_SPIM_TXFTLR_OFST 0x18
1436 
1437 #define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
1438 
1479 #define ALT_SPIM_RXFTLR_RFT_LSB 0
1480 
1481 #define ALT_SPIM_RXFTLR_RFT_MSB 7
1482 
1483 #define ALT_SPIM_RXFTLR_RFT_WIDTH 8
1484 
1485 #define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
1486 
1487 #define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
1488 
1489 #define ALT_SPIM_RXFTLR_RFT_RESET 0x0
1490 
1491 #define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1492 
1493 #define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1494 
1495 #ifndef __ASSEMBLY__
1496 
1507 {
1508  uint32_t rft : 8;
1509  uint32_t : 24;
1510 };
1511 
1513 typedef volatile struct ALT_SPIM_RXFTLR_s ALT_SPIM_RXFTLR_t;
1514 #endif /* __ASSEMBLY__ */
1515 
1517 #define ALT_SPIM_RXFTLR_RESET 0x00000000
1518 
1519 #define ALT_SPIM_RXFTLR_OFST 0x1c
1520 
1521 #define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
1522 
1547 #define ALT_SPIM_TXFLR_TXTFL_LSB 0
1548 
1549 #define ALT_SPIM_TXFLR_TXTFL_MSB 8
1550 
1551 #define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
1552 
1553 #define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
1554 
1555 #define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1556 
1557 #define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
1558 
1559 #define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1560 
1561 #define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1562 
1563 #ifndef __ASSEMBLY__
1564 
1575 {
1576  const uint32_t txtfl : 9;
1577  uint32_t : 23;
1578 };
1579 
1581 typedef volatile struct ALT_SPIM_TXFLR_s ALT_SPIM_TXFLR_t;
1582 #endif /* __ASSEMBLY__ */
1583 
1585 #define ALT_SPIM_TXFLR_RESET 0x00000000
1586 
1587 #define ALT_SPIM_TXFLR_OFST 0x20
1588 
1589 #define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
1590 
1615 #define ALT_SPIM_RXFLR_RXTFL_LSB 0
1616 
1617 #define ALT_SPIM_RXFLR_RXTFL_MSB 8
1618 
1619 #define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
1620 
1621 #define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
1622 
1623 #define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1624 
1625 #define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
1626 
1627 #define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1628 
1629 #define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1630 
1631 #ifndef __ASSEMBLY__
1632 
1643 {
1644  const uint32_t rxtfl : 9;
1645  uint32_t : 23;
1646 };
1647 
1649 typedef volatile struct ALT_SPIM_RXFLR_s ALT_SPIM_RXFLR_t;
1650 #endif /* __ASSEMBLY__ */
1651 
1653 #define ALT_SPIM_RXFLR_RESET 0x00000000
1654 
1655 #define ALT_SPIM_RXFLR_OFST 0x24
1656 
1657 #define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
1658 
1700 #define ALT_SPIM_SR_BUSY_E_INACT 0x0
1701 
1706 #define ALT_SPIM_SR_BUSY_E_ACT 0x1
1707 
1709 #define ALT_SPIM_SR_BUSY_LSB 0
1710 
1711 #define ALT_SPIM_SR_BUSY_MSB 0
1712 
1713 #define ALT_SPIM_SR_BUSY_WIDTH 1
1714 
1715 #define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
1716 
1717 #define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
1718 
1719 #define ALT_SPIM_SR_BUSY_RESET 0x0
1720 
1721 #define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1722 
1723 #define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1724 
1745 #define ALT_SPIM_SR_TFNF_E_FULL 0x0
1746 
1751 #define ALT_SPIM_SR_TFNF_E_NOTFULL 0x1
1752 
1754 #define ALT_SPIM_SR_TFNF_LSB 1
1755 
1756 #define ALT_SPIM_SR_TFNF_MSB 1
1757 
1758 #define ALT_SPIM_SR_TFNF_WIDTH 1
1759 
1760 #define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
1761 
1762 #define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
1763 
1764 #define ALT_SPIM_SR_TFNF_RESET 0x1
1765 
1766 #define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1767 
1768 #define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1769 
1790 #define ALT_SPIM_SR_TFE_E_NOTEMPTY 0x0
1791 
1796 #define ALT_SPIM_SR_TFE_E_EMPTY 0x1
1797 
1799 #define ALT_SPIM_SR_TFE_LSB 2
1800 
1801 #define ALT_SPIM_SR_TFE_MSB 2
1802 
1803 #define ALT_SPIM_SR_TFE_WIDTH 1
1804 
1805 #define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
1806 
1807 #define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
1808 
1809 #define ALT_SPIM_SR_TFE_RESET 0x1
1810 
1811 #define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1812 
1813 #define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1814 
1835 #define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
1836 
1841 #define ALT_SPIM_SR_RFNE_E_NOTEMPTY 0x1
1842 
1844 #define ALT_SPIM_SR_RFNE_LSB 3
1845 
1846 #define ALT_SPIM_SR_RFNE_MSB 3
1847 
1848 #define ALT_SPIM_SR_RFNE_WIDTH 1
1849 
1850 #define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
1851 
1852 #define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
1853 
1854 #define ALT_SPIM_SR_RFNE_RESET 0x0
1855 
1856 #define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1857 
1858 #define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1859 
1880 #define ALT_SPIM_SR_RFF_E_NOTFULL 0x0
1881 
1886 #define ALT_SPIM_SR_RFF_E_FULL 0x1
1887 
1889 #define ALT_SPIM_SR_RFF_LSB 4
1890 
1891 #define ALT_SPIM_SR_RFF_MSB 4
1892 
1893 #define ALT_SPIM_SR_RFF_WIDTH 1
1894 
1895 #define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
1896 
1897 #define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
1898 
1899 #define ALT_SPIM_SR_RFF_RESET 0x0
1900 
1901 #define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1902 
1903 #define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1904 
1933 #define ALT_SPIM_SR_DCOL_E_NOERROR 0x0
1934 
1939 #define ALT_SPIM_SR_DCOL_E_ERROR 0x1
1940 
1942 #define ALT_SPIM_SR_DCOL_LSB 6
1943 
1944 #define ALT_SPIM_SR_DCOL_MSB 6
1945 
1946 #define ALT_SPIM_SR_DCOL_WIDTH 1
1947 
1948 #define ALT_SPIM_SR_DCOL_SET_MSK 0x00000040
1949 
1950 #define ALT_SPIM_SR_DCOL_CLR_MSK 0xffffffbf
1951 
1952 #define ALT_SPIM_SR_DCOL_RESET 0x0
1953 
1954 #define ALT_SPIM_SR_DCOL_GET(value) (((value) & 0x00000040) >> 6)
1955 
1956 #define ALT_SPIM_SR_DCOL_SET(value) (((value) << 6) & 0x00000040)
1957 
1958 #ifndef __ASSEMBLY__
1959 
1970 {
1971  const uint32_t busy : 1;
1972  const uint32_t tfnf : 1;
1973  const uint32_t tfe : 1;
1974  const uint32_t rfne : 1;
1975  const uint32_t rff : 1;
1976  uint32_t : 1;
1977  const uint32_t dcol : 1;
1978  uint32_t : 25;
1979 };
1980 
1982 typedef volatile struct ALT_SPIM_SR_s ALT_SPIM_SR_t;
1983 #endif /* __ASSEMBLY__ */
1984 
1986 #define ALT_SPIM_SR_RESET 0x00000006
1987 
1988 #define ALT_SPIM_SR_OFST 0x28
1989 
1990 #define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
1991 
2034 #define ALT_SPIM_IMR_TXEIM_E_MSKED 0x0
2035 
2040 #define ALT_SPIM_IMR_TXEIM_E_END 0x1
2041 
2043 #define ALT_SPIM_IMR_TXEIM_LSB 0
2044 
2045 #define ALT_SPIM_IMR_TXEIM_MSB 0
2046 
2047 #define ALT_SPIM_IMR_TXEIM_WIDTH 1
2048 
2049 #define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
2050 
2051 #define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
2052 
2053 #define ALT_SPIM_IMR_TXEIM_RESET 0x1
2054 
2055 #define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
2056 
2057 #define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
2058 
2083 #define ALT_SPIM_IMR_TXOIM_E_MSKED 0x0
2084 
2089 #define ALT_SPIM_IMR_TXOIM_E_END 0x1
2090 
2092 #define ALT_SPIM_IMR_TXOIM_LSB 1
2093 
2094 #define ALT_SPIM_IMR_TXOIM_MSB 1
2095 
2096 #define ALT_SPIM_IMR_TXOIM_WIDTH 1
2097 
2098 #define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
2099 
2100 #define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
2101 
2102 #define ALT_SPIM_IMR_TXOIM_RESET 0x1
2103 
2104 #define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
2105 
2106 #define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
2107 
2132 #define ALT_SPIM_IMR_RXUIM_E_MSKED 0x0
2133 
2138 #define ALT_SPIM_IMR_RXUIM_E_END 0x1
2139 
2141 #define ALT_SPIM_IMR_RXUIM_LSB 2
2142 
2143 #define ALT_SPIM_IMR_RXUIM_MSB 2
2144 
2145 #define ALT_SPIM_IMR_RXUIM_WIDTH 1
2146 
2147 #define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
2148 
2149 #define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
2150 
2151 #define ALT_SPIM_IMR_RXUIM_RESET 0x1
2152 
2153 #define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
2154 
2155 #define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
2156 
2181 #define ALT_SPIM_IMR_RXOIM_E_MSKED 0x0
2182 
2187 #define ALT_SPIM_IMR_RXOIM_E_END 0x1
2188 
2190 #define ALT_SPIM_IMR_RXOIM_LSB 3
2191 
2192 #define ALT_SPIM_IMR_RXOIM_MSB 3
2193 
2194 #define ALT_SPIM_IMR_RXOIM_WIDTH 1
2195 
2196 #define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
2197 
2198 #define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
2199 
2200 #define ALT_SPIM_IMR_RXOIM_RESET 0x1
2201 
2202 #define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
2203 
2204 #define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
2205 
2230 #define ALT_SPIM_IMR_RXFIM_E_MSKED 0x0
2231 
2236 #define ALT_SPIM_IMR_RXFIM_E_END 0x1
2237 
2239 #define ALT_SPIM_IMR_RXFIM_LSB 4
2240 
2241 #define ALT_SPIM_IMR_RXFIM_MSB 4
2242 
2243 #define ALT_SPIM_IMR_RXFIM_WIDTH 1
2244 
2245 #define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
2246 
2247 #define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
2248 
2249 #define ALT_SPIM_IMR_RXFIM_RESET 0x1
2250 
2251 #define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
2252 
2253 #define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
2254 
2270 #define ALT_SPIM_IMR_MSTIM_LSB 5
2271 
2272 #define ALT_SPIM_IMR_MSTIM_MSB 5
2273 
2274 #define ALT_SPIM_IMR_MSTIM_WIDTH 1
2275 
2276 #define ALT_SPIM_IMR_MSTIM_SET_MSK 0x00000020
2277 
2278 #define ALT_SPIM_IMR_MSTIM_CLR_MSK 0xffffffdf
2279 
2280 #define ALT_SPIM_IMR_MSTIM_RESET 0x1
2281 
2282 #define ALT_SPIM_IMR_MSTIM_GET(value) (((value) & 0x00000020) >> 5)
2283 
2284 #define ALT_SPIM_IMR_MSTIM_SET(value) (((value) << 5) & 0x00000020)
2285 
2286 #ifndef __ASSEMBLY__
2287 
2298 {
2299  uint32_t txeim : 1;
2300  uint32_t txoim : 1;
2301  uint32_t rxuim : 1;
2302  uint32_t rxoim : 1;
2303  uint32_t rxfim : 1;
2304  uint32_t mstim : 1;
2305  uint32_t : 26;
2306 };
2307 
2309 typedef volatile struct ALT_SPIM_IMR_s ALT_SPIM_IMR_t;
2310 #endif /* __ASSEMBLY__ */
2311 
2313 #define ALT_SPIM_IMR_RESET 0x0000003f
2314 
2315 #define ALT_SPIM_IMR_OFST 0x2c
2316 
2317 #define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
2318 
2362 #define ALT_SPIM_ISR_TXEIS_E_INACT 0x0
2363 
2368 #define ALT_SPIM_ISR_TXEIS_E_ACT 0x1
2369 
2371 #define ALT_SPIM_ISR_TXEIS_LSB 0
2372 
2373 #define ALT_SPIM_ISR_TXEIS_MSB 0
2374 
2375 #define ALT_SPIM_ISR_TXEIS_WIDTH 1
2376 
2377 #define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
2378 
2379 #define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
2380 
2381 #define ALT_SPIM_ISR_TXEIS_RESET 0x0
2382 
2383 #define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
2384 
2385 #define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
2386 
2412 #define ALT_SPIM_ISR_TXOIS_E_INACT 0x0
2413 
2418 #define ALT_SPIM_ISR_TXOIS_E_ACT 0x1
2419 
2421 #define ALT_SPIM_ISR_TXOIS_LSB 1
2422 
2423 #define ALT_SPIM_ISR_TXOIS_MSB 1
2424 
2425 #define ALT_SPIM_ISR_TXOIS_WIDTH 1
2426 
2427 #define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
2428 
2429 #define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
2430 
2431 #define ALT_SPIM_ISR_TXOIS_RESET 0x0
2432 
2433 #define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
2434 
2435 #define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
2436 
2462 #define ALT_SPIM_ISR_RXUIS_E_INACT 0x0
2463 
2468 #define ALT_SPIM_ISR_RXUIS_E_ACT 0x1
2469 
2471 #define ALT_SPIM_ISR_RXUIS_LSB 2
2472 
2473 #define ALT_SPIM_ISR_RXUIS_MSB 2
2474 
2475 #define ALT_SPIM_ISR_RXUIS_WIDTH 1
2476 
2477 #define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
2478 
2479 #define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
2480 
2481 #define ALT_SPIM_ISR_RXUIS_RESET 0x0
2482 
2483 #define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
2484 
2485 #define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
2486 
2512 #define ALT_SPIM_ISR_RXOIS_E_INACT 0x0
2513 
2518 #define ALT_SPIM_ISR_RXOIS_E_ACT 0x1
2519 
2521 #define ALT_SPIM_ISR_RXOIS_LSB 3
2522 
2523 #define ALT_SPIM_ISR_RXOIS_MSB 3
2524 
2525 #define ALT_SPIM_ISR_RXOIS_WIDTH 1
2526 
2527 #define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
2528 
2529 #define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
2530 
2531 #define ALT_SPIM_ISR_RXOIS_RESET 0x0
2532 
2533 #define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2534 
2535 #define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2536 
2562 #define ALT_SPIM_ISR_RXFIS_E_INACT 0x0
2563 
2568 #define ALT_SPIM_ISR_RXFIS_E_ACT 0x1
2569 
2571 #define ALT_SPIM_ISR_RXFIS_LSB 4
2572 
2573 #define ALT_SPIM_ISR_RXFIS_MSB 4
2574 
2575 #define ALT_SPIM_ISR_RXFIS_WIDTH 1
2576 
2577 #define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
2578 
2579 #define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
2580 
2581 #define ALT_SPIM_ISR_RXFIS_RESET 0x0
2582 
2583 #define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2584 
2585 #define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2586 
2615 #define ALT_SPIM_ISR_MSTIS_E_INACT 0x0
2616 
2621 #define ALT_SPIM_ISR_MSTIS_E_ACT 0x1
2622 
2624 #define ALT_SPIM_ISR_MSTIS_LSB 5
2625 
2626 #define ALT_SPIM_ISR_MSTIS_MSB 5
2627 
2628 #define ALT_SPIM_ISR_MSTIS_WIDTH 1
2629 
2630 #define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
2631 
2632 #define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
2633 
2634 #define ALT_SPIM_ISR_MSTIS_RESET 0x0
2635 
2636 #define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2637 
2638 #define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2639 
2640 #ifndef __ASSEMBLY__
2641 
2652 {
2653  const uint32_t txeis : 1;
2654  const uint32_t txois : 1;
2655  const uint32_t rxuis : 1;
2656  const uint32_t rxois : 1;
2657  const uint32_t rxfis : 1;
2658  const uint32_t mstis : 1;
2659  uint32_t : 26;
2660 };
2661 
2663 typedef volatile struct ALT_SPIM_ISR_s ALT_SPIM_ISR_t;
2664 #endif /* __ASSEMBLY__ */
2665 
2667 #define ALT_SPIM_ISR_RESET 0x00000000
2668 
2669 #define ALT_SPIM_ISR_OFST 0x30
2670 
2671 #define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
2672 
2716 #define ALT_SPIM_RISR_TXEIR_E_INACT 0x0
2717 
2722 #define ALT_SPIM_RISR_TXEIR_E_ACT 0x1
2723 
2725 #define ALT_SPIM_RISR_TXEIR_LSB 0
2726 
2727 #define ALT_SPIM_RISR_TXEIR_MSB 0
2728 
2729 #define ALT_SPIM_RISR_TXEIR_WIDTH 1
2730 
2731 #define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
2732 
2733 #define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
2734 
2735 #define ALT_SPIM_RISR_TXEIR_RESET 0x0
2736 
2737 #define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2738 
2739 #define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2740 
2766 #define ALT_SPIM_RISR_TXOIR_E_INACT 0x0
2767 
2772 #define ALT_SPIM_RISR_TXOIR_E_ACT 0x1
2773 
2775 #define ALT_SPIM_RISR_TXOIR_LSB 1
2776 
2777 #define ALT_SPIM_RISR_TXOIR_MSB 1
2778 
2779 #define ALT_SPIM_RISR_TXOIR_WIDTH 1
2780 
2781 #define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
2782 
2783 #define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
2784 
2785 #define ALT_SPIM_RISR_TXOIR_RESET 0x0
2786 
2787 #define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2788 
2789 #define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2790 
2817 #define ALT_SPIM_RISR_RXUIR_E_INACT 0x0
2818 
2823 #define ALT_SPIM_RISR_RXUIR_E_ACT 0x1
2824 
2826 #define ALT_SPIM_RISR_RXUIR_LSB 2
2827 
2828 #define ALT_SPIM_RISR_RXUIR_MSB 2
2829 
2830 #define ALT_SPIM_RISR_RXUIR_WIDTH 1
2831 
2832 #define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
2833 
2834 #define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
2835 
2836 #define ALT_SPIM_RISR_RXUIR_RESET 0x0
2837 
2838 #define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2839 
2840 #define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2841 
2867 #define ALT_SPIM_RISR_RXOIR_E_INACTOVE 0x0
2868 
2873 #define ALT_SPIM_RISR_RXOIR_E_ACT 0x1
2874 
2876 #define ALT_SPIM_RISR_RXOIR_LSB 3
2877 
2878 #define ALT_SPIM_RISR_RXOIR_MSB 3
2879 
2880 #define ALT_SPIM_RISR_RXOIR_WIDTH 1
2881 
2882 #define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
2883 
2884 #define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
2885 
2886 #define ALT_SPIM_RISR_RXOIR_RESET 0x0
2887 
2888 #define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2889 
2890 #define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2891 
2918 #define ALT_SPIM_RISR_RXFIR_E_INACT 0x0
2919 
2924 #define ALT_SPIM_RISR_RXFIR_E_ACT 0x1
2925 
2927 #define ALT_SPIM_RISR_RXFIR_LSB 4
2928 
2929 #define ALT_SPIM_RISR_RXFIR_MSB 4
2930 
2931 #define ALT_SPIM_RISR_RXFIR_WIDTH 1
2932 
2933 #define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
2934 
2935 #define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
2936 
2937 #define ALT_SPIM_RISR_RXFIR_RESET 0x0
2938 
2939 #define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2940 
2941 #define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2942 
2960 #define ALT_SPIM_RISR_MSTIR_LSB 5
2961 
2962 #define ALT_SPIM_RISR_MSTIR_MSB 5
2963 
2964 #define ALT_SPIM_RISR_MSTIR_WIDTH 1
2965 
2966 #define ALT_SPIM_RISR_MSTIR_SET_MSK 0x00000020
2967 
2968 #define ALT_SPIM_RISR_MSTIR_CLR_MSK 0xffffffdf
2969 
2970 #define ALT_SPIM_RISR_MSTIR_RESET 0x0
2971 
2972 #define ALT_SPIM_RISR_MSTIR_GET(value) (((value) & 0x00000020) >> 5)
2973 
2974 #define ALT_SPIM_RISR_MSTIR_SET(value) (((value) << 5) & 0x00000020)
2975 
2976 #ifndef __ASSEMBLY__
2977 
2988 {
2989  const uint32_t txeir : 1;
2990  const uint32_t txoir : 1;
2991  const uint32_t rxuir : 1;
2992  const uint32_t rxoir : 1;
2993  const uint32_t rxfir : 1;
2994  const uint32_t mstir : 1;
2995  uint32_t : 26;
2996 };
2997 
2999 typedef volatile struct ALT_SPIM_RISR_s ALT_SPIM_RISR_t;
3000 #endif /* __ASSEMBLY__ */
3001 
3003 #define ALT_SPIM_RISR_RESET 0x00000000
3004 
3005 #define ALT_SPIM_RISR_OFST 0x34
3006 
3007 #define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
3008 
3035 #define ALT_SPIM_TXOICR_TXOICR_LSB 0
3036 
3037 #define ALT_SPIM_TXOICR_TXOICR_MSB 0
3038 
3039 #define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
3040 
3041 #define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
3042 
3043 #define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
3044 
3045 #define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
3046 
3047 #define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
3048 
3049 #define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
3050 
3051 #ifndef __ASSEMBLY__
3052 
3063 {
3064  const uint32_t txoicr : 1;
3065  uint32_t : 31;
3066 };
3067 
3069 typedef volatile struct ALT_SPIM_TXOICR_s ALT_SPIM_TXOICR_t;
3070 #endif /* __ASSEMBLY__ */
3071 
3073 #define ALT_SPIM_TXOICR_RESET 0x00000000
3074 
3075 #define ALT_SPIM_TXOICR_OFST 0x38
3076 
3077 #define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
3078 
3105 #define ALT_SPIM_RXOICR_RXOICR_LSB 0
3106 
3107 #define ALT_SPIM_RXOICR_RXOICR_MSB 0
3108 
3109 #define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
3110 
3111 #define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
3112 
3113 #define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
3114 
3115 #define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
3116 
3117 #define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
3118 
3119 #define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
3120 
3121 #ifndef __ASSEMBLY__
3122 
3133 {
3134  const uint32_t rxoicr : 1;
3135  uint32_t : 31;
3136 };
3137 
3139 typedef volatile struct ALT_SPIM_RXOICR_s ALT_SPIM_RXOICR_t;
3140 #endif /* __ASSEMBLY__ */
3141 
3143 #define ALT_SPIM_RXOICR_RESET 0x00000000
3144 
3145 #define ALT_SPIM_RXOICR_OFST 0x3c
3146 
3147 #define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
3148 
3175 #define ALT_SPIM_RXUICR_RXUICR_LSB 0
3176 
3177 #define ALT_SPIM_RXUICR_RXUICR_MSB 0
3178 
3179 #define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
3180 
3181 #define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
3182 
3183 #define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
3184 
3185 #define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
3186 
3187 #define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
3188 
3189 #define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
3190 
3191 #ifndef __ASSEMBLY__
3192 
3203 {
3204  const uint32_t rxuicr : 1;
3205  uint32_t : 31;
3206 };
3207 
3209 typedef volatile struct ALT_SPIM_RXUICR_s ALT_SPIM_RXUICR_t;
3210 #endif /* __ASSEMBLY__ */
3211 
3213 #define ALT_SPIM_RXUICR_RESET 0x00000000
3214 
3215 #define ALT_SPIM_RXUICR_OFST 0x40
3216 
3217 #define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
3218 
3245 #define ALT_SPIM_MSTICR_MSTICR_LSB 0
3246 
3247 #define ALT_SPIM_MSTICR_MSTICR_MSB 0
3248 
3249 #define ALT_SPIM_MSTICR_MSTICR_WIDTH 1
3250 
3251 #define ALT_SPIM_MSTICR_MSTICR_SET_MSK 0x00000001
3252 
3253 #define ALT_SPIM_MSTICR_MSTICR_CLR_MSK 0xfffffffe
3254 
3255 #define ALT_SPIM_MSTICR_MSTICR_RESET 0x0
3256 
3257 #define ALT_SPIM_MSTICR_MSTICR_GET(value) (((value) & 0x00000001) >> 0)
3258 
3259 #define ALT_SPIM_MSTICR_MSTICR_SET(value) (((value) << 0) & 0x00000001)
3260 
3261 #ifndef __ASSEMBLY__
3262 
3273 {
3274  const uint32_t msticr : 1;
3275  uint32_t : 31;
3276 };
3277 
3279 typedef volatile struct ALT_SPIM_MSTICR_s ALT_SPIM_MSTICR_t;
3280 #endif /* __ASSEMBLY__ */
3281 
3283 #define ALT_SPIM_MSTICR_RESET 0x00000000
3284 
3285 #define ALT_SPIM_MSTICR_OFST 0x44
3286 
3287 #define ALT_SPIM_MSTICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MSTICR_OFST))
3288 
3317 #define ALT_SPIM_ICR_ICR_LSB 0
3318 
3319 #define ALT_SPIM_ICR_ICR_MSB 0
3320 
3321 #define ALT_SPIM_ICR_ICR_WIDTH 1
3322 
3323 #define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
3324 
3325 #define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
3326 
3327 #define ALT_SPIM_ICR_ICR_RESET 0x0
3328 
3329 #define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
3330 
3331 #define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
3332 
3333 #ifndef __ASSEMBLY__
3334 
3345 {
3346  const uint32_t icr : 1;
3347  uint32_t : 31;
3348 };
3349 
3351 typedef volatile struct ALT_SPIM_ICR_s ALT_SPIM_ICR_t;
3352 #endif /* __ASSEMBLY__ */
3353 
3355 #define ALT_SPIM_ICR_RESET 0x00000000
3356 
3357 #define ALT_SPIM_ICR_OFST 0x48
3358 
3359 #define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
3360 
3413 #define ALT_SPIM_DMACR_RDMAE_E_DISD 0x0
3414 
3419 #define ALT_SPIM_DMACR_RDMAE_E_END 0x1
3420 
3422 #define ALT_SPIM_DMACR_RDMAE_LSB 0
3423 
3424 #define ALT_SPIM_DMACR_RDMAE_MSB 0
3425 
3426 #define ALT_SPIM_DMACR_RDMAE_WIDTH 1
3427 
3428 #define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
3429 
3430 #define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
3431 
3432 #define ALT_SPIM_DMACR_RDMAE_RESET 0x0
3433 
3434 #define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
3435 
3436 #define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
3437 
3464 #define ALT_SPIM_DMACR_TDMAE_E_DISD 0x0
3465 
3470 #define ALT_SPIM_DMACR_TDMAE_E_END 0x1
3471 
3473 #define ALT_SPIM_DMACR_TDMAE_LSB 1
3474 
3475 #define ALT_SPIM_DMACR_TDMAE_MSB 1
3476 
3477 #define ALT_SPIM_DMACR_TDMAE_WIDTH 1
3478 
3479 #define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
3480 
3481 #define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
3482 
3483 #define ALT_SPIM_DMACR_TDMAE_RESET 0x0
3484 
3485 #define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
3486 
3487 #define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
3488 
3489 #ifndef __ASSEMBLY__
3490 
3501 {
3502  uint32_t rdmae : 1;
3503  uint32_t tdmae : 1;
3504  uint32_t : 30;
3505 };
3506 
3508 typedef volatile struct ALT_SPIM_DMACR_s ALT_SPIM_DMACR_t;
3509 #endif /* __ASSEMBLY__ */
3510 
3512 #define ALT_SPIM_DMACR_RESET 0x00000000
3513 
3514 #define ALT_SPIM_DMACR_OFST 0x4c
3515 
3516 #define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
3517 
3558 #define ALT_SPIM_DMATDLR_DMATDL_LSB 0
3559 
3560 #define ALT_SPIM_DMATDLR_DMATDL_MSB 7
3561 
3562 #define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
3563 
3564 #define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
3565 
3566 #define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
3567 
3568 #define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
3569 
3570 #define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
3571 
3572 #define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
3573 
3574 #ifndef __ASSEMBLY__
3575 
3586 {
3587  uint32_t dmatdl : 8;
3588  uint32_t : 24;
3589 };
3590 
3592 typedef volatile struct ALT_SPIM_DMATDLR_s ALT_SPIM_DMATDLR_t;
3593 #endif /* __ASSEMBLY__ */
3594 
3596 #define ALT_SPIM_DMATDLR_RESET 0x00000000
3597 
3598 #define ALT_SPIM_DMATDLR_OFST 0x50
3599 
3600 #define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
3601 
3640 #define ALT_SPIM_DMARDLR_DMARDL_LSB 0
3641 
3642 #define ALT_SPIM_DMARDLR_DMARDL_MSB 7
3643 
3644 #define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
3645 
3646 #define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
3647 
3648 #define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
3649 
3650 #define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
3651 
3652 #define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
3653 
3654 #define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
3655 
3656 #ifndef __ASSEMBLY__
3657 
3668 {
3669  uint32_t dmardl : 8;
3670  uint32_t : 24;
3671 };
3672 
3674 typedef volatile struct ALT_SPIM_DMARDLR_s ALT_SPIM_DMARDLR_t;
3675 #endif /* __ASSEMBLY__ */
3676 
3678 #define ALT_SPIM_DMARDLR_RESET 0x00000000
3679 
3680 #define ALT_SPIM_DMARDLR_OFST 0x54
3681 
3682 #define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
3683 
3709 #define ALT_SPIM_IDR_IDR_LSB 0
3710 
3711 #define ALT_SPIM_IDR_IDR_MSB 31
3712 
3713 #define ALT_SPIM_IDR_IDR_WIDTH 32
3714 
3715 #define ALT_SPIM_IDR_IDR_SET_MSK 0xffffffff
3716 
3717 #define ALT_SPIM_IDR_IDR_CLR_MSK 0x00000000
3718 
3719 #define ALT_SPIM_IDR_IDR_RESET 0x5510000
3720 
3721 #define ALT_SPIM_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
3722 
3723 #define ALT_SPIM_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
3724 
3725 #ifndef __ASSEMBLY__
3726 
3737 {
3738  const uint32_t idr : 32;
3739 };
3740 
3742 typedef volatile struct ALT_SPIM_IDR_s ALT_SPIM_IDR_t;
3743 #endif /* __ASSEMBLY__ */
3744 
3746 #define ALT_SPIM_IDR_RESET 0x05510000
3747 
3748 #define ALT_SPIM_IDR_OFST 0x58
3749 
3750 #define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
3751 
3774 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_LSB 0
3775 
3776 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_MSB 31
3777 
3778 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3779 
3780 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3781 
3782 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3783 
3784 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_RESET 0x3332322a
3785 
3786 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3787 
3788 #define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3789 
3790 #ifndef __ASSEMBLY__
3791 
3802 {
3803  uint32_t spi_version_id : 32;
3804 };
3805 
3808 #endif /* __ASSEMBLY__ */
3809 
3811 #define ALT_SPIM_SPI_VER_ID_RESET 0x3332322a
3812 
3813 #define ALT_SPIM_SPI_VER_ID_OFST 0x5c
3814 
3815 #define ALT_SPIM_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPI_VER_ID_OFST))
3816 
3855 #define ALT_SPIM_DR_DR_LSB 0
3856 
3857 #define ALT_SPIM_DR_DR_MSB 15
3858 
3859 #define ALT_SPIM_DR_DR_WIDTH 16
3860 
3861 #define ALT_SPIM_DR_DR_SET_MSK 0x0000ffff
3862 
3863 #define ALT_SPIM_DR_DR_CLR_MSK 0xffff0000
3864 
3865 #define ALT_SPIM_DR_DR_RESET 0x0
3866 
3867 #define ALT_SPIM_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3868 
3869 #define ALT_SPIM_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3870 
3871 #ifndef __ASSEMBLY__
3872 
3883 {
3884  uint32_t dr : 16;
3885  uint32_t : 16;
3886 };
3887 
3889 typedef volatile struct ALT_SPIM_DR_s ALT_SPIM_DR_t;
3890 #endif /* __ASSEMBLY__ */
3891 
3893 #define ALT_SPIM_DR_RESET 0x00000000
3894 
3895 #define ALT_SPIM_DR_OFST 0x60
3896 
3897 #define ALT_SPIM_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR_OFST))
3898 
3947 #define ALT_SPIM_RX_SMPL_DLY_RSD_LSB 0
3948 
3949 #define ALT_SPIM_RX_SMPL_DLY_RSD_MSB 7
3950 
3951 #define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH 8
3952 
3953 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK 0x000000ff
3954 
3955 #define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK 0xffffff00
3956 
3957 #define ALT_SPIM_RX_SMPL_DLY_RSD_RESET 0x0
3958 
3959 #define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value) (((value) & 0x000000ff) >> 0)
3960 
3961 #define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value) (((value) << 0) & 0x000000ff)
3962 
3963 #ifndef __ASSEMBLY__
3964 
3975 {
3976  uint32_t rsd : 8;
3977  uint32_t : 24;
3978 };
3979 
3982 #endif /* __ASSEMBLY__ */
3983 
3985 #define ALT_SPIM_RX_SMPL_DLY_RESET 0x00000000
3986 
3987 #define ALT_SPIM_RX_SMPL_DLY_OFST 0xf0
3988 
3989 #define ALT_SPIM_RX_SMPL_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))
3990 
4012 #define ALT_SPIM_RSVD_0_FLD_LSB 0
4013 
4014 #define ALT_SPIM_RSVD_0_FLD_MSB 31
4015 
4016 #define ALT_SPIM_RSVD_0_FLD_WIDTH 32
4017 
4018 #define ALT_SPIM_RSVD_0_FLD_SET_MSK 0xffffffff
4019 
4020 #define ALT_SPIM_RSVD_0_FLD_CLR_MSK 0x00000000
4021 
4022 #define ALT_SPIM_RSVD_0_FLD_RESET 0x0
4023 
4024 #define ALT_SPIM_RSVD_0_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4025 
4026 #define ALT_SPIM_RSVD_0_FLD_SET(value) (((value) << 0) & 0xffffffff)
4027 
4028 #ifndef __ASSEMBLY__
4029 
4040 {
4041  uint32_t fld : 32;
4042 };
4043 
4045 typedef volatile struct ALT_SPIM_RSVD_0_s ALT_SPIM_RSVD_0_t;
4046 #endif /* __ASSEMBLY__ */
4047 
4049 #define ALT_SPIM_RSVD_0_RESET 0x00000000
4050 
4051 #define ALT_SPIM_RSVD_0_OFST 0xf4
4052 
4053 #define ALT_SPIM_RSVD_0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_0_OFST))
4054 
4076 #define ALT_SPIM_RSVD_1_FLD_LSB 0
4077 
4078 #define ALT_SPIM_RSVD_1_FLD_MSB 31
4079 
4080 #define ALT_SPIM_RSVD_1_FLD_WIDTH 32
4081 
4082 #define ALT_SPIM_RSVD_1_FLD_SET_MSK 0xffffffff
4083 
4084 #define ALT_SPIM_RSVD_1_FLD_CLR_MSK 0x00000000
4085 
4086 #define ALT_SPIM_RSVD_1_FLD_RESET 0x0
4087 
4088 #define ALT_SPIM_RSVD_1_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4089 
4090 #define ALT_SPIM_RSVD_1_FLD_SET(value) (((value) << 0) & 0xffffffff)
4091 
4092 #ifndef __ASSEMBLY__
4093 
4104 {
4105  uint32_t fld : 32;
4106 };
4107 
4109 typedef volatile struct ALT_SPIM_RSVD_1_s ALT_SPIM_RSVD_1_t;
4110 #endif /* __ASSEMBLY__ */
4111 
4113 #define ALT_SPIM_RSVD_1_RESET 0x00000000
4114 
4115 #define ALT_SPIM_RSVD_1_OFST 0xf8
4116 
4117 #define ALT_SPIM_RSVD_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_1_OFST))
4118 
4140 #define ALT_SPIM_RSVD_2_FLD_LSB 0
4141 
4142 #define ALT_SPIM_RSVD_2_FLD_MSB 31
4143 
4144 #define ALT_SPIM_RSVD_2_FLD_WIDTH 32
4145 
4146 #define ALT_SPIM_RSVD_2_FLD_SET_MSK 0xffffffff
4147 
4148 #define ALT_SPIM_RSVD_2_FLD_CLR_MSK 0x00000000
4149 
4150 #define ALT_SPIM_RSVD_2_FLD_RESET 0x0
4151 
4152 #define ALT_SPIM_RSVD_2_FLD_GET(value) (((value) & 0xffffffff) >> 0)
4153 
4154 #define ALT_SPIM_RSVD_2_FLD_SET(value) (((value) << 0) & 0xffffffff)
4155 
4156 #ifndef __ASSEMBLY__
4157 
4168 {
4169  uint32_t fld : 32;
4170 };
4171 
4173 typedef volatile struct ALT_SPIM_RSVD_2_s ALT_SPIM_RSVD_2_t;
4174 #endif /* __ASSEMBLY__ */
4175 
4177 #define ALT_SPIM_RSVD_2_RESET 0x00000000
4178 
4179 #define ALT_SPIM_RSVD_2_OFST 0xfc
4180 
4181 #define ALT_SPIM_RSVD_2_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RSVD_2_OFST))
4182 
4183 #ifndef __ASSEMBLY__
4184 
4195 {
4200  volatile ALT_SPIM_SER_t ser;
4206  volatile ALT_SPIM_SR_t sr;
4207  volatile ALT_SPIM_IMR_t imr;
4208  volatile ALT_SPIM_ISR_t isr;
4214  volatile ALT_SPIM_ICR_t icr;
4218  volatile ALT_SPIM_IDR_t idr;
4220  volatile ALT_SPIM_DR_t dr;
4221  volatile uint32_t _pad_0x64_0xef[35];
4226 };
4227 
4229 typedef volatile struct ALT_SPIM_s ALT_SPIM_t;
4232 {
4233  volatile uint32_t ctrlr0;
4234  volatile uint32_t ctrlr1;
4235  volatile uint32_t spienr;
4236  volatile uint32_t mwcr;
4237  volatile uint32_t ser;
4238  volatile uint32_t baudr;
4239  volatile uint32_t txftlr;
4240  volatile uint32_t rxftlr;
4241  volatile uint32_t txflr;
4242  volatile uint32_t rxflr;
4243  volatile uint32_t sr;
4244  volatile uint32_t imr;
4245  volatile uint32_t isr;
4246  volatile uint32_t risr;
4247  volatile uint32_t txoicr;
4248  volatile uint32_t rxoicr;
4249  volatile uint32_t rxuicr;
4250  volatile uint32_t msticr;
4251  volatile uint32_t icr;
4252  volatile uint32_t dmacr;
4253  volatile uint32_t dmatdlr;
4254  volatile uint32_t dmardlr;
4255  volatile uint32_t idr;
4256  volatile uint32_t spi_version_id;
4257  volatile uint32_t dr;
4258  volatile uint32_t _pad_0x64_0xef[35];
4259  volatile uint32_t rx_sample_dly;
4260  volatile uint32_t rsvd_0;
4261  volatile uint32_t rsvd_1;
4262  volatile uint32_t rsvd_2;
4263 };
4264 
4266 typedef volatile struct ALT_SPIM_raw_s ALT_SPIM_raw_t;
4267 #endif /* __ASSEMBLY__ */
4268 
4270 #ifdef __cplusplus
4271 }
4272 #endif /* __cplusplus */
4273 #endif /* __ALT_SOCAL_SPIM_H__ */
4274