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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Control register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_SDMMC_CTL_CTLLER_RST |
[1] | RW | 0x0 | ALT_SDMMC_CTL_FIFO_RST |
[2] | RW | 0x0 | ALT_SDMMC_CTL_DMA_RST |
[3] | ??? | 0x0 | UNDEFINED |
[4] | RW | 0x0 | ALT_SDMMC_CTL_INT_EN |
[5] | RW | 0x0 | ALT_SDMMC_CTL_DMA_EN |
[6] | RW | 0x0 | ALT_SDMMC_CTL_RD_WAIT |
[7] | RW | 0x0 | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE |
[8] | RW | 0x0 | ALT_SDMMC_CTL_ABT_RD_DATA |
[9] | RW | 0x0 | ALT_SDMMC_CTL_SEND_CCSD |
[10] | RW | 0x0 | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD |
[11] | RW | 0x0 | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT |
[15:12] | ??? | 0x0 | UNDEFINED |
[19:16] | RW | 0x0 | ALT_SDMMC_CTL_CARD_VOLTAGE_A |
[23:20] | RW | 0x0 | ALT_SDMMC_CTL_CARD_VOLTAGE_B |
[24] | RW | 0x0 | ALT_SDMMC_CTL_EN_OD_PULLUP |
[25] | RW | 0x0 | ALT_SDMMC_CTL_USE_INTERNAL_DMAC |
[31:26] | ??? | 0x0 | UNDEFINED |
Field : controller_reset | ||||||||||
0-No change 1-Reset DWC_mobile_storage controller To reset controller, firmware should set bit to 1. This bit is auto-cleared after two AHB and two cclk_in clock cycles. This resets:
Does not affect any registers or DMA interface, or FIFO or host interrupts Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_LSB 0 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_MSB 0 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : fifo_reset | ||||||||||
0-No change 1-Reset to data FIFO To reset FIFO pointers To reset FIFO, firmware should set bit to 1. This bit is auto-cleared after completion of reset operation. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_LSB 1 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_MSB 1 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : dma_reset | ||||||||||
0-No change 1-Reset internal DMA interface control logic To reset DMA interface, firmware should set bit to 1. This bit is auto-cleared after two AHB clocks. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_LSB 2 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_MSB 2 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : int_enable | ||||||||||
Global interrupt enable/disable bit: 0-Disable interrupts 1-Enable interrupts The int port is 1 only when this bit is 1 and one or more unmasked interrupts are set. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_INT_EN_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_E_END 0x1 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_LSB 4 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_MSB 4 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : dma_enable | |
0-Disable DMA transfer mode 1-Enable DMA transfer mode Valid only if DWC_mobile_storage configured for External DMA interface. Field Access Macros: | |
#define | ALT_SDMMC_CTL_DMA_EN_LSB 5 |
#define | ALT_SDMMC_CTL_DMA_EN_MSB 5 |
#define | ALT_SDMMC_CTL_DMA_EN_WIDTH 1 |
#define | ALT_SDMMC_CTL_DMA_EN_SET_MSK 0x00000020 |
#define | ALT_SDMMC_CTL_DMA_EN_CLR_MSK 0xffffffdf |
#define | ALT_SDMMC_CTL_DMA_EN_RESET 0x0 |
#define | ALT_SDMMC_CTL_DMA_EN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_SDMMC_CTL_DMA_EN_SET(value) (((value) << 5) & 0x00000020) |
Field : read_wait | ||||||||||
0-Clear read wait 1-Assert read wait For sending read-wait to SDIO cards. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_LSB 6 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_MSB 6 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : send_irq_response | ||||||||||
0-No Change in this 1-Send auto IRQ response Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40, and DWC_mobile_storage waits for interrupt response from MMC card(s). In meantime, if host wants DWC_mobile_storage to exit waiting for interrupt state, it can set this bit, at which time DWC_mobile_storage command state-machine sends CMD40 response on bus and returns to idle state. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : abort_read_data | ||||||||||
0-No change 1-After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs,software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data statemachine resets to idle. Used in SDIO card suspend sequence. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : send_ccsd | |||||||||||||
0-Clear this bit if DWC_mobile_storage does not reset the bit 1-Send Command Completion Signal Disable (CCSD) to CE-ATA device Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_LSB 9 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_MSB 9 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0 | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9) | ||||||||||||
#define | ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200) | ||||||||||||
Field : send_auto_stop_ccsd | ||||||||||
0-Clear bit if DWC_mobile_storage does not reset the bit 1-Send internally generated STOP after sending CCSD to CE-ATA device Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10) | |||||||||
#define | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400) | |||||||||
Field : ceata_device_interrupt_status | ||||||||||
0-Interrupts not enabled in CE-ATA device 1-Interrupts are enabled in CE-ATA device Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11) | |||||||||
#define | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800) | |||||||||
Field : card_voltage_a | |
Card regulator-A voltage setting; output to card_volt_a port. Optional feature; ports can be used as general-purpose outputs Field Access Macros: | |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_LSB 16 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_MSB 19 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_WIDTH 4 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET_MSK 0x000f0000 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_RESET 0x0 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16) |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000) |
Field : card_voltage_b | |
Card regulator-B voltage setting; output to card_volt_b port. Optional feature; ports can be used as general-purpose outputs Field Access Macros: | |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_LSB 20 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_MSB 23 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_WIDTH 4 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET_MSK 0x00f00000 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_RESET 0x0 |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20) |
#define | ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000) |
Field : enable_od_pullup | |
External open-drain pullup 0-Disable 1-Enable Inverted value of this bit is output to ccmd_od_pullup_en_n port. When bit is set, command output always driven in open-drive mode; that is, DWC_mobile_storage drives either 0 or high impedance, and does not drive hard 1. Field Access Macros: | |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_LSB 24 |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_MSB 24 |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_WIDTH 1 |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_SET_MSK 0x01000000 |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_CLR_MSK 0xfeffffff |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_RESET 0x0 |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_SDMMC_CTL_EN_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000) |
Field : use_internal_dmac | |||||||||||||
Present only for the Internal DMAC configuration; else, it is reserved. 0-The host performs data transfers through the slave interface 1-Internal DMAC used for data transfer Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0 | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25) | ||||||||||||
#define | ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000) | ||||||||||||
Data Structures | |
struct | ALT_SDMMC_CTL_s |
Macros | |
#define | ALT_SDMMC_CTL_RESET 0x00000000 |
#define | ALT_SDMMC_CTL_OFST 0x0 |
Typedefs | |
typedef struct ALT_SDMMC_CTL_s | ALT_SDMMC_CTL_t |
struct ALT_SDMMC_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_CTL.
Data Fields | ||
---|---|---|
uint32_t | controller_reset: 1 | ALT_SDMMC_CTL_CTLLER_RST |
uint32_t | fifo_reset: 1 | ALT_SDMMC_CTL_FIFO_RST |
uint32_t | dma_reset: 1 | ALT_SDMMC_CTL_DMA_RST |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | int_enable: 1 | ALT_SDMMC_CTL_INT_EN |
uint32_t | dma_enable: 1 | ALT_SDMMC_CTL_DMA_EN |
uint32_t | read_wait: 1 | ALT_SDMMC_CTL_RD_WAIT |
uint32_t | send_irq_response: 1 | ALT_SDMMC_CTL_SEND_IRQ_RESPONSE |
uint32_t | abort_read_data: 1 | ALT_SDMMC_CTL_ABT_RD_DATA |
uint32_t | send_ccsd: 1 | ALT_SDMMC_CTL_SEND_CCSD |
uint32_t | send_auto_stop_ccsd: 1 | ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD |
uint32_t | ceata_device_interrupt_status: 1 | ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT |
uint32_t | __pad1__: 4 | UNDEFINED |
uint32_t | card_voltage_a: 4 | ALT_SDMMC_CTL_CARD_VOLTAGE_A |
uint32_t | card_voltage_b: 4 | ALT_SDMMC_CTL_CARD_VOLTAGE_B |
uint32_t | enable_od_pullup: 1 | ALT_SDMMC_CTL_EN_OD_PULLUP |
uint32_t | use_internal_dmac: 1 | ALT_SDMMC_CTL_USE_INTERNAL_DMAC |
uint32_t | __pad2__: 6 | UNDEFINED |
#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
No change -default
#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST
Reset SD/MMC controller
#define ALT_SDMMC_CTL_CTLLER_RST_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field.
#define ALT_SDMMC_CTL_CTLLER_RST_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field.
#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_CTLLER_RST register field.
#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001 |
The mask used to set the ALT_SDMMC_CTL_CTLLER_RST register field value.
#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDMMC_CTL_CTLLER_RST register field value.
#define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_CTLLER_RST register field.
#define ALT_SDMMC_CTL_CTLLER_RST_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDMMC_CTL_CTLLER_RST field value from a register.
#define ALT_SDMMC_CTL_CTLLER_RST_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDMMC_CTL_CTLLER_RST register field value suitable for setting the register.
#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
No change
#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST
Reset to data FIFO To reset FIFO pointers
#define ALT_SDMMC_CTL_FIFO_RST_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_FIFO_RST register field.
#define ALT_SDMMC_CTL_FIFO_RST_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_FIFO_RST register field.
#define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_FIFO_RST register field.
#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002 |
The mask used to set the ALT_SDMMC_CTL_FIFO_RST register field value.
#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SDMMC_CTL_FIFO_RST register field value.
#define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_FIFO_RST register field.
#define ALT_SDMMC_CTL_FIFO_RST_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SDMMC_CTL_FIFO_RST field value from a register.
#define ALT_SDMMC_CTL_FIFO_RST_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SDMMC_CTL_FIFO_RST register field value suitable for setting the register.
#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
No change
#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_DMA_RST
Reset internal DMA interface control logic
#define ALT_SDMMC_CTL_DMA_RST_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_RST register field.
#define ALT_SDMMC_CTL_DMA_RST_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_RST register field.
#define ALT_SDMMC_CTL_DMA_RST_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_DMA_RST register field.
#define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004 |
The mask used to set the ALT_SDMMC_CTL_DMA_RST register field value.
#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SDMMC_CTL_DMA_RST register field value.
#define ALT_SDMMC_CTL_DMA_RST_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_DMA_RST register field.
#define ALT_SDMMC_CTL_DMA_RST_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SDMMC_CTL_DMA_RST field value from a register.
#define ALT_SDMMC_CTL_DMA_RST_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SDMMC_CTL_DMA_RST register field value suitable for setting the register.
#define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_INT_EN
Disable Interrupts
#define ALT_SDMMC_CTL_INT_EN_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_INT_EN
Enable interrupts
#define ALT_SDMMC_CTL_INT_EN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_INT_EN register field.
#define ALT_SDMMC_CTL_INT_EN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_INT_EN register field.
#define ALT_SDMMC_CTL_INT_EN_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_INT_EN register field.
#define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010 |
The mask used to set the ALT_SDMMC_CTL_INT_EN register field value.
#define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SDMMC_CTL_INT_EN register field value.
#define ALT_SDMMC_CTL_INT_EN_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_INT_EN register field.
#define ALT_SDMMC_CTL_INT_EN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SDMMC_CTL_INT_EN field value from a register.
#define ALT_SDMMC_CTL_INT_EN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SDMMC_CTL_INT_EN register field value suitable for setting the register.
#define ALT_SDMMC_CTL_DMA_EN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_EN register field.
#define ALT_SDMMC_CTL_DMA_EN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_EN register field.
#define ALT_SDMMC_CTL_DMA_EN_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_DMA_EN register field.
#define ALT_SDMMC_CTL_DMA_EN_SET_MSK 0x00000020 |
The mask used to set the ALT_SDMMC_CTL_DMA_EN register field value.
#define ALT_SDMMC_CTL_DMA_EN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_SDMMC_CTL_DMA_EN register field value.
#define ALT_SDMMC_CTL_DMA_EN_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_DMA_EN register field.
#define ALT_SDMMC_CTL_DMA_EN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_SDMMC_CTL_DMA_EN field value from a register.
#define ALT_SDMMC_CTL_DMA_EN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_SDMMC_CTL_DMA_EN register field value suitable for setting the register.
#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
Read Wait
#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT
Assert Read Wait
#define ALT_SDMMC_CTL_RD_WAIT_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_RD_WAIT register field.
#define ALT_SDMMC_CTL_RD_WAIT_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_RD_WAIT register field.
#define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_RD_WAIT register field.
#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040 |
The mask used to set the ALT_SDMMC_CTL_RD_WAIT register field value.
#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_SDMMC_CTL_RD_WAIT register field value.
#define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_RD_WAIT register field.
#define ALT_SDMMC_CTL_RD_WAIT_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_SDMMC_CTL_RD_WAIT field value from a register.
#define ALT_SDMMC_CTL_RD_WAIT_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_SDMMC_CTL_RD_WAIT register field value suitable for setting the register.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
No change
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE
Send auto IRQ response
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080 |
The mask used to set the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE field value from a register.
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value suitable for setting the register.
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
No change
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA
Abort Read
#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field.
#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field.
#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_ABT_RD_DATA register field.
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100 |
The mask used to set the ALT_SDMMC_CTL_ABT_RD_DATA register field value.
#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SDMMC_CTL_ABT_RD_DATA register field value.
#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_ABT_RD_DATA register field.
#define ALT_SDMMC_CTL_ABT_RD_DATA_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SDMMC_CTL_ABT_RD_DATA field value from a register.
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SDMMC_CTL_ABT_RD_DATA register field value suitable for setting the register.
#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
Clear bit if SD/MMC does not reset the bit
#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD
Send Command Completion Signal Disable (CCSD) to CE-ATA device
#define ALT_SDMMC_CTL_SEND_CCSD_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field.
#define ALT_SDMMC_CTL_SEND_CCSD_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field.
#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_SEND_CCSD register field.
#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200 |
The mask used to set the ALT_SDMMC_CTL_SEND_CCSD register field value.
#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_SDMMC_CTL_SEND_CCSD register field value.
#define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_SEND_CCSD register field.
#define ALT_SDMMC_CTL_SEND_CCSD_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_SDMMC_CTL_SEND_CCSD field value from a register.
#define ALT_SDMMC_CTL_SEND_CCSD_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_SDMMC_CTL_SEND_CCSD register field value suitable for setting the register.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
Clear bit if SD/MMC does not reset the bit
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD
Send internally generated STOP.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400 |
The mask used to set the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD field value from a register.
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
Interrupts not enabled in CE-ATA device
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT
Interrupts are enabled in CE-ATA device
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800 |
The mask used to set the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT field value from a register.
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value suitable for setting the register.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_WIDTH 4 |
The width in bits of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET_MSK 0x000f0000 |
The mask used to set the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff |
The mask used to clear the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_CARD_VOLTAGE_A register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_GET | ( | value | ) | (((value) & 0x000f0000) >> 16) |
Extracts the ALT_SDMMC_CTL_CARD_VOLTAGE_A field value from a register.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET | ( | value | ) | (((value) << 16) & 0x000f0000) |
Produces a ALT_SDMMC_CTL_CARD_VOLTAGE_A register field value suitable for setting the register.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_WIDTH 4 |
The width in bits of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET_MSK 0x00f00000 |
The mask used to set the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff |
The mask used to clear the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_CARD_VOLTAGE_B register field.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_GET | ( | value | ) | (((value) & 0x00f00000) >> 20) |
Extracts the ALT_SDMMC_CTL_CARD_VOLTAGE_B field value from a register.
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET | ( | value | ) | (((value) << 20) & 0x00f00000) |
Produces a ALT_SDMMC_CTL_CARD_VOLTAGE_B register field value suitable for setting the register.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_EN_OD_PULLUP register field.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_EN_OD_PULLUP register field.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_EN_OD_PULLUP register field.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_SET_MSK 0x01000000 |
The mask used to set the ALT_SDMMC_CTL_EN_OD_PULLUP register field value.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_SDMMC_CTL_EN_OD_PULLUP register field value.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_EN_OD_PULLUP register field.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_SDMMC_CTL_EN_OD_PULLUP field value from a register.
#define ALT_SDMMC_CTL_EN_OD_PULLUP_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_SDMMC_CTL_EN_OD_PULLUP register field value suitable for setting the register.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
The host performs data transfers thru slave interface
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC
Internal DMAC used for data transfer
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1 |
The width in bits of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000 |
The mask used to set the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0 |
The reset value of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_SDMMC_CTL_USE_INTERNAL_DMAC field value from a register.
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value suitable for setting the register.
#define ALT_SDMMC_CTL_RESET 0x00000000 |
The reset value of the ALT_SDMMC_CTL register.
#define ALT_SDMMC_CTL_OFST 0x0 |
The byte offset of the ALT_SDMMC_CTL register from the beginning of the component.
typedef struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t |
The typedef declaration for register ALT_SDMMC_CTL.