Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECCCTRL1

Description

ECC control 1.

This bit is used to set the initialize the memory and ecc to a known value

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN
[7:1] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST
[15:9] ??? 0x0 UNDEFINED
[16] RW 0x0 ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST
[31:17] ??? 0x0 UNDEFINED

Field : ECC_EN

Enable for the ECC detection and correction logic.

1'b0:ECC block is disabled. Default value after reset.

1'b1: ECC block is enabled. Every RAM access will verify the data and generate any necessary error requests.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_LSB   0
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_MSB   0
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET_MSK   0x00000001
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_CLR_MSK   0xfffffffe
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : CNT_RST

Reset of internal counter.

1'b0: No effect on internal counter. Dafault value after reset

1'b1: Reset the internal counter to zero

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_LSB   8
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_MSB   8
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET_MSK   0x00000100
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_CLR_MSK   0xfffffeff
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET(value)   (((value) << 8) & 0x00000100)
 

Field : AUTOWB_CNT_RST

Reset the autoWB internal counter to zero.

1'b0 : No effect on autoWB internal counter. Default value after reset

1'b1 : Reset the autoWB internal counter to zero

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_LSB   16
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_MSB   16
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET_MSK   0x00010000
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_CLR_MSK   0xfffeffff
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET(value)   (((value) << 16) & 0x00010000)
 

Data Structures

struct  ALT_ECC_HMC_OCP_ECCCTL1_s
 

Macros

#define ALT_ECC_HMC_OCP_ECCCTL1_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_ECCCTL1_OFST   0x100
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_ECCCTL1_s 
ALT_ECC_HMC_OCP_ECCCTL1_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_ECCCTL1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_ECCCTL1.

Data Fields
uint32_t ECC_EN: 1 ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN
uint32_t __pad0__: 7 UNDEFINED
uint32_t CNT_RST: 1 ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST
uint32_t __pad1__: 7 UNDEFINED
uint32_t AUTOWB_CNT_RST: 1 ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST
uint32_t __pad2__: 15 UNDEFINED

Macro Definitions

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET_MSK   0x00000001

The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN field value from a register.

#define ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_HMC_OCP_ECCCTL1_ECC_EN register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_MSB   8

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET_MSK   0x00000100

The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_CLR_MSK   0xfffffeff

The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST field value from a register.

#define ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_ECC_HMC_OCP_ECCCTL1_CNT_RST register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_LSB   16

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_MSB   16

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET_MSK   0x00010000

The mask used to set the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_CLR_MSK   0xfffeffff

The mask used to clear the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST field value from a register.

#define ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_ECC_HMC_OCP_ECCCTL1_AUTOWB_CNT_RST register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECCCTL1_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_ECCCTL1 register.

#define ALT_ECC_HMC_OCP_ECCCTL1_OFST   0x100

The byte offset of the ALT_ECC_HMC_OCP_ECCCTL1 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_ECC_HMC_OCP_ECCCTL1.