308 #define ALT_MMU_SUPERSECTION_SIZE (1UL << 24)
313 #define ALT_MMU_SECTION_SIZE (1UL << 20)
318 #define ALT_MMU_LARGE_PAGE_SIZE (1UL << 16)
323 #define ALT_MMU_SMALL_PAGE_SIZE (1UL << 12)
329 #define ALT_MMU_TTB1_SIZE 16384
335 #define ALT_MMU_TTB2_SIZE 1024
367 #define ALT_MMU_TTB1_TYPE_MASK 0x00000003
368 #define ALT_MMU_TTB1_TYPE_GET(desc) (((desc) & ALT_MMU_TTB1_TYPE_MASK) >> 0)
369 #define ALT_MMU_TTB1_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB1_TYPE_MASK)
378 #define ALT_MMU_TTB1_PAGE_TBL_NS_MASK 0x00000008
379 #define ALT_MMU_TTB1_PAGE_TBL_NS_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) >> 3)
380 #define ALT_MMU_TTB1_PAGE_TBL_NS_SET(val) (((val) << 3) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK)
390 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK 0x000001e0
391 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) >> 5)
392 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK)
399 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK 0xfffffc00
400 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) >> 10)
401 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(val) (((val) << 10) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK)
411 #define ALT_MMU_TTB1_SECTION_B_MASK 0x00000004
412 #define ALT_MMU_TTB1_SECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_B_MASK) >> 2)
413 #define ALT_MMU_TTB1_SECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SECTION_B_MASK)
423 #define ALT_MMU_TTB1_SECTION_C_MASK 0x00000008
424 #define ALT_MMU_TTB1_SECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_C_MASK) >> 3)
425 #define ALT_MMU_TTB1_SECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SECTION_C_MASK)
435 #define ALT_MMU_TTB1_SECTION_XN_MASK 0x00000010
436 #define ALT_MMU_TTB1_SECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_XN_MASK) >> 4)
437 #define ALT_MMU_TTB1_SECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SECTION_XN_MASK)
446 #define ALT_MMU_TTB1_SECTION_DOMAIN_MASK 0x000001e0
447 #define ALT_MMU_TTB1_SECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) >> 5)
448 #define ALT_MMU_TTB1_SECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK)
457 #define ALT_MMU_TTB1_SECTION_AP_MASK 0x00008c00
458 #define ALT_MMU_TTB1_SECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
459 #define ALT_MMU_TTB1_SECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
469 #define ALT_MMU_TTB1_SECTION_TEX_MASK 0x00007000
470 #define ALT_MMU_TTB1_SECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_TEX_MASK) >> 12)
471 #define ALT_MMU_TTB1_SECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SECTION_TEX_MASK)
480 #define ALT_MMU_TTB1_SECTION_S_MASK 0x00010000
481 #define ALT_MMU_TTB1_SECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_S_MASK) >> 16)
482 #define ALT_MMU_TTB1_SECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SECTION_S_MASK)
491 #define ALT_MMU_TTB1_SECTION_NG_MASK 0x00020000
492 #define ALT_MMU_TTB1_SECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NG_MASK) >> 17)
493 #define ALT_MMU_TTB1_SECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SECTION_NG_MASK)
503 #define ALT_MMU_TTB1_SECTION_NS_MASK 0x00080000
504 #define ALT_MMU_TTB1_SECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NS_MASK) >> 19)
505 #define ALT_MMU_TTB1_SECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SECTION_NS_MASK)
512 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK 0xfff00000
513 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) >> 20)
514 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(val) (((val) << 20) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK)
524 #define ALT_MMU_TTB1_SUPERSECTION_B_MASK 0x00000004
525 #define ALT_MMU_TTB1_SUPERSECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) >> 2)
526 #define ALT_MMU_TTB1_SUPERSECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SUPERSECTION_B_MASK)
536 #define ALT_MMU_TTB1_SUPERSECTION_C_MASK 0x00000008
537 #define ALT_MMU_TTB1_SUPERSECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) >> 3)
538 #define ALT_MMU_TTB1_SUPERSECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SUPERSECTION_C_MASK)
548 #define ALT_MMU_TTB1_SUPERSECTION_XN_MASK 0x00000010
549 #define ALT_MMU_TTB1_SUPERSECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) >> 4)
550 #define ALT_MMU_TTB1_SUPERSECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK)
559 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK 0x000001e0
560 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) >> 5)
561 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK)
570 #define ALT_MMU_TTB1_SUPERSECTION_AP_MASK 0x00008c00
571 #define ALT_MMU_TTB1_SUPERSECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
572 #define ALT_MMU_TTB1_SUPERSECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
582 #define ALT_MMU_TTB1_SUPERSECTION_TEX_MASK 0x00007000
583 #define ALT_MMU_TTB1_SUPERSECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) >> 12)
584 #define ALT_MMU_TTB1_SUPERSECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK)
593 #define ALT_MMU_TTB1_SUPERSECTION_S_MASK 0x00010000
594 #define ALT_MMU_TTB1_SUPERSECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) >> 16)
595 #define ALT_MMU_TTB1_SUPERSECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SUPERSECTION_S_MASK)
604 #define ALT_MMU_TTB1_SUPERSECTION_NG_MASK 0x00020000
605 #define ALT_MMU_TTB1_SUPERSECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) >> 17)
606 #define ALT_MMU_TTB1_SUPERSECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK)
616 #define ALT_MMU_TTB1_SUPERSECTION_NS_MASK 0x00080000
617 #define ALT_MMU_TTB1_SUPERSECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) >> 19)
618 #define ALT_MMU_TTB1_SUPERSECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK)
624 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK 0xff000000
625 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) >> 24)
626 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(val) (((val) << 24) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK)
659 #define ALT_MMU_TTB2_TYPE_MASK 0x00000003
660 #define ALT_MMU_TTB2_TYPE_GET(desc) (((desc) & ALT_MMU_TTB2_TYPE_MASK) >> 0)
661 #define ALT_MMU_TTB2_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB2_TYPE_MASK)
670 #define ALT_MMU_TTB2_LARGE_PAGE_B_MASK 0x00000004
671 #define ALT_MMU_TTB2_LARGE_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) >> 2)
672 #define ALT_MMU_TTB2_LARGE_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK)
682 #define ALT_MMU_TTB2_LARGE_PAGE_C_MASK 0x00000008
683 #define ALT_MMU_TTB2_LARGE_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) >> 3)
684 #define ALT_MMU_TTB2_LARGE_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK)
693 #define ALT_MMU_TTB2_LARGE_PAGE_AP_MASK 0x00000230
694 #define ALT_MMU_TTB2_LARGE_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
695 #define ALT_MMU_TTB2_LARGE_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
704 #define ALT_MMU_TTB2_LARGE_PAGE_S_MASK 0x00000400
705 #define ALT_MMU_TTB2_LARGE_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) >> 10)
706 #define ALT_MMU_TTB2_LARGE_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK)
715 #define ALT_MMU_TTB2_LARGE_PAGE_NG_MASK 0x00000800
716 #define ALT_MMU_TTB2_LARGE_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) >> 11)
717 #define ALT_MMU_TTB2_LARGE_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK)
727 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK 0x00007000
728 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) >> 12)
729 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK)
739 #define ALT_MMU_TTB2_LARGE_PAGE_XN_MASK 0x00008000
740 #define ALT_MMU_TTB2_LARGE_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) >> 15)
741 #define ALT_MMU_TTB2_LARGE_PAGE_XN_SET(val) (((val) << 15) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK)
748 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK 0xffff0000
749 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) >> 16)
750 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(val) (((val) << 16) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK)
760 #define ALT_MMU_TTB2_SMALL_PAGE_XN_MASK 0x00000001
761 #define ALT_MMU_TTB2_SMALL_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) >> 0)
762 #define ALT_MMU_TTB2_SMALL_PAGE_XN_SET(val) (((val) << 0) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK)
772 #define ALT_MMU_TTB2_SMALL_PAGE_B_MASK 0x00000004
773 #define ALT_MMU_TTB2_SMALL_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) >> 2)
774 #define ALT_MMU_TTB2_SMALL_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK)
784 #define ALT_MMU_TTB2_SMALL_PAGE_C_MASK 0x00000008
785 #define ALT_MMU_TTB2_SMALL_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) >> 3)
786 #define ALT_MMU_TTB2_SMALL_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK)
795 #define ALT_MMU_TTB2_SMALL_PAGE_AP_MASK 0x00000230
796 #define ALT_MMU_TTB2_SMALL_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
797 #define ALT_MMU_TTB2_SMALL_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
807 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK 0x000001c0
808 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) >> 6)
809 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(val) (((val) << 6) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK)
818 #define ALT_MMU_TTB2_SMALL_PAGE_S_MASK 0x00000400
819 #define ALT_MMU_TTB2_SMALL_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) >> 10)
820 #define ALT_MMU_TTB2_SMALL_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK)
829 #define ALT_MMU_TTB2_SMALL_PAGE_NG_MASK 0x00000800
830 #define ALT_MMU_TTB2_SMALL_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) >> 11)
831 #define ALT_MMU_TTB2_SMALL_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK)
838 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK 0xfffff000
839 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) >> 12)
840 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(val) (((val) << 12) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK)
1216 const uint32_t desc);
1256 const uint32_t desc);
1375 const bool enable_ttbr1_walk,
1376 const uint32_t base_addr_width);
1395 const size_t num_elem);
1547 typedef void* (*alt_mmu_ttb_alloc_t)(
const size_t size,
void * context);
1572 const size_t num_mem_regions);
1613 const size_t num_mem_regions,
1615 void * ttb_alloc_context);
1687 uintptr_t
alt_mmu_va_to_pa(
const void * va, uint32_t * seglength, uint32_t * dfsr);