Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Memory Protection Rule Read-Write Register - protrulerdwr

Description

This register is used to perform read and write operations to the internal protection table.

Register Layout

Bits Access Reset Description
[4:0] RW Unknown Rule Offset
[5] RW Unknown Rule Write
[6] RW Unknown Rule Read
[31:7] ??? 0x0 UNDEFINED

Field : Rule Offset - ruleoffset

This field defines which of the 20 rules in the protection table you want to read or write.

Field Access Macros:

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB   0
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB   4
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH   5
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK   0x0000001f
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK   0xffffffe0
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET   0x0
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value)   (((value) & 0x0000001f) >> 0)
 
#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value)   (((value) << 0) & 0x0000001f)
 

Field : Rule Write - writerule

Write to this bit to have the memory_prot_data register to the table at the offset specified by port_offset. Bit automatically clears after a single cycle and the write operation is complete.

Field Access Macros:

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB   5
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB   5
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH   1
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK   0x00000020
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK   0xffffffdf
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET   0x0
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Rule Read - readrule

Write to this bit to have the memory_prot_data register loaded with the value from the internal protection table at offset. Table value will be loaded before a rdy is returned so read data from the register will be correct for any follow- on reads to the memory_prot_data register.

Field Access Macros:

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB   6
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB   6
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH   1
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK   0x00000040
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK   0xffffffbf
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET   0x0
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value)   (((value) << 6) & 0x00000040)
 

Data Structures

struct  ALT_SDR_CTL_PROTRULERDWR_s
 

Macros

#define ALT_SDR_CTL_PROTRULERDWR_OFST   0x9c
 

Typedefs

typedef struct
ALT_SDR_CTL_PROTRULERDWR_s 
ALT_SDR_CTL_PROTRULERDWR_t
 

Data Structure Documentation

struct ALT_SDR_CTL_PROTRULERDWR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDR_CTL_PROTRULERDWR.

Data Fields
uint32_t ruleoffset: 5 Rule Offset
uint32_t writerule: 1 Rule Write
uint32_t readrule: 1 Rule Read
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB   4

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH   5

The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK   0x0000001f

The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK   0xffffffe0

The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET   0x0

The reset value of the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field is UNKNOWN.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET (   value)    (((value) & 0x0000001f) >> 0)

Extracts the ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET field value from a register.

#define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET (   value)    (((value) << 0) & 0x0000001f)

Produces a ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET register field value suitable for setting the register.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB   5

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB   5

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH   1

The width in bits of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK   0x00000020

The mask used to set the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET   0x0

The reset value of the ALT_SDR_CTL_PROTRULERDWR_WRRULE register field is UNKNOWN.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SDR_CTL_PROTRULERDWR_WRRULE field value from a register.

#define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SDR_CTL_PROTRULERDWR_WRRULE register field value suitable for setting the register.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB   6

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB   6

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH   1

The width in bits of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK   0x00000040

The mask used to set the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET   0x0

The reset value of the ALT_SDR_CTL_PROTRULERDWR_RDRULE register field is UNKNOWN.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SDR_CTL_PROTRULERDWR_RDRULE field value from a register.

#define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SDR_CTL_PROTRULERDWR_RDRULE register field value suitable for setting the register.

#define ALT_SDR_CTL_PROTRULERDWR_OFST   0x9c

The byte offset of the ALT_SDR_CTL_PROTRULERDWR register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDR_CTL_PROTRULERDWR.