Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECC_WDataecc0bus

Description

The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.

Register Layout

Bits Access Reset Description
[4:0] RW 0x0 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS
[7:5] ??? 0x0 UNDEFINED
[12:8] RW 0x0 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS
[15:13] ??? 0x0 UNDEFINED
[20:16] RW 0x0 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS
[23:21] ??? 0x0 UNDEFINED
[28:24] RW 0x0 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS
[31:29] ??? 0x0 UNDEFINED

Field : ECC_WDataecc0BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB   0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB   4
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH   5
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK   0x0000001f
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK   0xffffffe0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET   0x0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value)   (((value) & 0x0000001f) >> 0)
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value)   (((value) << 0) & 0x0000001f)
 

Field : ECC_WDataecc1BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB   8
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB   12
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH   5
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK   0x00001f00
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK   0xffffe0ff
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET   0x0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value)   (((value) & 0x00001f00) >> 8)
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value)   (((value) << 8) & 0x00001f00)
 

Field : ECC_WDataecc2BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB   16
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB   20
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH   5
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK   0x001f0000
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK   0xffe0ffff
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET   0x0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value)   (((value) & 0x001f0000) >> 16)
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value)   (((value) << 16) & 0x001f0000)
 

Field : ECC_WDataecc3BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB   24
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB   28
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH   5
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK   0x1f000000
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK   0xe0ffffff
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET   0x0
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value)   (((value) & 0x1f000000) >> 24)
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value)   (((value) << 24) & 0x1f000000)
 

Data Structures

struct  ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s
 

Macros

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_RESET   0x00000000
 
#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_OFST   0x6c
 

Typedefs

typedef struct
ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s 
ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_t
 

Data Structure Documentation

struct ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS.

Data Fields
uint32_t ECC_WDataecc0BUS: 5 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS
uint32_t __pad0__: 3 UNDEFINED
uint32_t ECC_WDataecc1BUS: 5 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS
uint32_t __pad1__: 3 UNDEFINED
uint32_t ECC_WDataecc2BUS: 5 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS
uint32_t __pad2__: 3 UNDEFINED
uint32_t ECC_WDataecc3BUS: 5 ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS
uint32_t __pad3__: 3 UNDEFINED

Macro Definitions

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB   4

The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH   5

The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK   0x0000001f

The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK   0xffffffe0

The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET   0x0

The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET (   value)    (((value) & 0x0000001f) >> 0)

Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS field value from a register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET (   value)    (((value) << 0) & 0x0000001f)

Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS register field value suitable for setting the register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB   12

The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH   5

The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK   0x00001f00

The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK   0xffffe0ff

The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET   0x0

The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET (   value)    (((value) & 0x00001f00) >> 8)

Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS field value from a register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET (   value)    (((value) << 8) & 0x00001f00)

Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS register field value suitable for setting the register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB   16

The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB   20

The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH   5

The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK   0x001f0000

The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK   0xffe0ffff

The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET   0x0

The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET (   value)    (((value) & 0x001f0000) >> 16)

Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS field value from a register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET (   value)    (((value) << 16) & 0x001f0000)

Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS register field value suitable for setting the register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB   24

The Least Significant Bit (LSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB   28

The Most Significant Bit (MSB) position of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH   5

The width in bits of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK   0x1f000000

The mask used to set the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK   0xe0ffffff

The mask used to clear the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET   0x0

The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET (   value)    (((value) & 0x1f000000) >> 24)

Extracts the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS field value from a register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET (   value)    (((value) << 24) & 0x1f000000)

Produces a ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS register field value suitable for setting the register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_RESET   0x00000000

The reset value of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS register.

#define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_OFST   0x6c

The byte offset of the ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS register from the beginning of the component.

Typedef Documentation