Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ctrl

Description

Sets various operating condiitions.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Controller Reset
[1] RW 0x0 FIFO Reset
[2] RW 0x0 Dma Reset
[3] ??? 0x0 UNDEFINED
[4] RW 0x0 Int Enable
[5] ??? 0x0 UNDEFINED
[6] RW 0x0 Read Wait
[7] RW 0x0 Send Irq Response
[8] RW 0x0 Abort Read Data
[9] RW 0x0 Send CCSD
[10] RW 0x0 Send Auto Stop CCSD
[11] RW 0x0 Ceata Device Interrupt Status
[24:12] ??? 0x0 UNDEFINED
[25] RW 0x0 Use Internal DMAC
[31:26] ??? 0x0 UNDEFINED

Field : Controller Reset - controller_reset

This bit resets the controller. This bit is auto-cleared after two l4_mp_clk and two sdmmc_clk clock cycles. This resets:

  • BIU/CIU interface
  • CIU and state machines
  • abort_read_data, send_irq_response, and read_wait bits of control register
  • start_cmd bit of command register

Does not affect any registers, DMA interface, FIFO or host interrupts.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0 No change -default
ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1 Reset SD/MMC controller

Field Access Macros:

#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE   0x0
 
#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE   0x1
 
#define ALT_SDMMC_CTL_CTLLER_RST_LSB   0
 
#define ALT_SDMMC_CTL_CTLLER_RST_MSB   0
 
#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH   1
 
#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK   0x00000001
 
#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK   0xfffffffe
 
#define ALT_SDMMC_CTL_CTLLER_RST_RESET   0x0
 
#define ALT_SDMMC_CTL_CTLLER_RST_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SDMMC_CTL_CTLLER_RST_SET(value)   (((value) << 0) & 0x00000001)
 

Field : FIFO Reset - fifo_reset

This bit resets the FIFO. This bit is auto-cleared after completion of reset operation.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0 No change
ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1 Reset to data FIFO To reset FIFO pointers

Field Access Macros:

#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE   0x0
 
#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE   0x1
 
#define ALT_SDMMC_CTL_FIFO_RST_LSB   1
 
#define ALT_SDMMC_CTL_FIFO_RST_MSB   1
 
#define ALT_SDMMC_CTL_FIFO_RST_WIDTH   1
 
#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK   0x00000002
 
#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK   0xfffffffd
 
#define ALT_SDMMC_CTL_FIFO_RST_RESET   0x0
 
#define ALT_SDMMC_CTL_FIFO_RST_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SDMMC_CTL_FIFO_RST_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Dma Reset - dma_reset

This bit resets the DMA interface control logic

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0 No change
ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1 Reset internal DMA interface control logic

Field Access Macros:

#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE   0x0
 
#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE   0x1
 
#define ALT_SDMMC_CTL_DMA_RST_LSB   2
 
#define ALT_SDMMC_CTL_DMA_RST_MSB   2
 
#define ALT_SDMMC_CTL_DMA_RST_WIDTH   1
 
#define ALT_SDMMC_CTL_DMA_RST_SET_MSK   0x00000004
 
#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK   0xfffffffb
 
#define ALT_SDMMC_CTL_DMA_RST_RESET   0x0
 
#define ALT_SDMMC_CTL_DMA_RST_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SDMMC_CTL_DMA_RST_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Int Enable - int_enable

This bit enables and disable interrupts if one or more unmasked interrupts are set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_INT_EN_E_DISD 0x0 Disable Interrupts
ALT_SDMMC_CTL_INT_EN_E_END 0x1 Enable interrupts

Field Access Macros:

#define ALT_SDMMC_CTL_INT_EN_E_DISD   0x0
 
#define ALT_SDMMC_CTL_INT_EN_E_END   0x1
 
#define ALT_SDMMC_CTL_INT_EN_LSB   4
 
#define ALT_SDMMC_CTL_INT_EN_MSB   4
 
#define ALT_SDMMC_CTL_INT_EN_WIDTH   1
 
#define ALT_SDMMC_CTL_INT_EN_SET_MSK   0x00000010
 
#define ALT_SDMMC_CTL_INT_EN_CLR_MSK   0xffffffef
 
#define ALT_SDMMC_CTL_INT_EN_RESET   0x0
 
#define ALT_SDMMC_CTL_INT_EN_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SDMMC_CTL_INT_EN_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Read Wait - read_wait

For sending read-wait to SDIO cards.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0 Read Wait
ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1 Assert Read Wait

Field Access Macros:

#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT   0x0
 
#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT   0x1
 
#define ALT_SDMMC_CTL_RD_WAIT_LSB   6
 
#define ALT_SDMMC_CTL_RD_WAIT_MSB   6
 
#define ALT_SDMMC_CTL_RD_WAIT_WIDTH   1
 
#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK   0x00000040
 
#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK   0xffffffbf
 
#define ALT_SDMMC_CTL_RD_WAIT_RESET   0x0
 
#define ALT_SDMMC_CTL_RD_WAIT_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SDMMC_CTL_RD_WAIT_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Send Irq Response - send_irq_response

Bit automatically clears once response is sent. To wait for MMC card interrupts, host issues CMD40, and SD/MMC waits for interrupt response from MMC card(s). In meantime, if host wants SD/MMC to exit waiting for interrupt state, it can set this bit, at which time SD/MMC command state-machine sends CMD40 response on bus and returns to idle state.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0 No change
ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1 Send auto IRQ response

Field Access Macros:

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE   0x0
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE   0x1
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB   7
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB   7
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH   1
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK   0x00000080
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK   0xffffff7f
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET   0x0
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Abort Read Data - abort_read_data

After suspend command is issued during read-transfer, software polls card to find when suspend happened. Once suspend occurs software sets bit to reset data state-machine, which is waiting for next block of data. Bit automatically clears once data statemachine resets to idle. Used in SDIO card suspend sequence.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0 No change
ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1 Abort Read

Field Access Macros:

#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE   0x0
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE   0x1
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB   8
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB   8
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH   1
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK   0x00000100
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK   0xfffffeff
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET   0x0
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Send CCSD - send_ccsd

When set, SD/MMC sends CCSD to CE-ATA device. Software sets this bit only if current command is expecting CCS (that is, RW_BLK) and interrupts are enabled in CE-ATA device. Once the CCSD pattern is sent to device, SD/MMC automatically clears send_ccsd bit. It also sets Command Done (CD) bit in RINTSTS register and generates interrupt to host if Command Done interrupt is not masked.

NOTE: Once send_ccsd bit is set, it takes two card clock cycles to drive the CCSD on the CMD line. Due to this, during the boundary conditions it may happen that CCSD is sent to the CE-ATA device, even if the device signalled CCS.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0 Clear bit if SD/MMC does not reset the bit
ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1 Send Command Completion Signal Disable (CCSD) to
: CE-ATA device

Field Access Macros:

#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT   0x0
 
#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT   0x1
 
#define ALT_SDMMC_CTL_SEND_CCSD_LSB   9
 
#define ALT_SDMMC_CTL_SEND_CCSD_MSB   9
 
#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH   1
 
#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK   0x00000200
 
#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK   0xfffffdff
 
#define ALT_SDMMC_CTL_SEND_CCSD_RESET   0x0
 
#define ALT_SDMMC_CTL_SEND_CCSD_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SDMMC_CTL_SEND_CCSD_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Send Auto Stop CCSD - send_auto_stop_ccsd

Always set send_auto_stop_ccsd and send_ccsd bits together; send_auto_stop_ccsd should not be set independent of send_ccsd. When set, SD/MMC automatically sends internally generated STOP command (CMD12) to CE-ATA device. After sending internally-generated STOP command, Auto Command Done (ACD) bit in RINTSTS is set and generates interrupt to host if Auto CommandDone interrupt is not masked. After sending the CCSD, SD/MMC automatically clears send_auto_stop_ccsd bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0 Clear bit if SD/MMC does not reset the bit
ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1 Send internally generated STOP.

Field Access Macros:

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT   0x0
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT   0x1
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB   10
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB   10
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH   1
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK   0x00000400
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK   0xfffffbff
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET   0x0
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Ceata Device Interrupt Status - ceata_device_interrupt_status

Software should appropriately write to this bit after power-on reset or any other reset to CE-ATA device. After reset, usually CE-ATA device interrupt is disabled (nIEN = 1). If the host enables CE-ATA device interrupt, then software should set this bit.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0 Interrupts not enabled in CE-ATA device
ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1 Interrupts are enabled in CE-ATA device

Field Access Macros:

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD   0x0
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END   0x1
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB   11
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB   11
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH   1
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK   0x00000800
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK   0xfffff7ff
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET   0x0
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Use Internal DMAC - use_internal_dmac

Enable and Disable Internal DMA transfers.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0 The host performs data transfers thru slave
: interface
ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1 Internal DMAC used for data transfer

Field Access Macros:

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD   0x0
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END   0x1
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB   25
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB   25
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH   1
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK   0x02000000
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK   0xfdffffff
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET   0x0
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value)   (((value) << 25) & 0x02000000)
 

Data Structures

struct  ALT_SDMMC_CTL_s
 

Macros

#define ALT_SDMMC_CTL_OFST   0x0
 

Typedefs

typedef struct ALT_SDMMC_CTL_s ALT_SDMMC_CTL_t
 

Data Structure Documentation

struct ALT_SDMMC_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_CTL.

Data Fields
uint32_t controller_reset: 1 Controller Reset
uint32_t fifo_reset: 1 FIFO Reset
uint32_t dma_reset: 1 Dma Reset
uint32_t __pad0__: 1 UNDEFINED
uint32_t int_enable: 1 Int Enable
uint32_t __pad1__: 1 UNDEFINED
uint32_t read_wait: 1 Read Wait
uint32_t send_irq_response: 1 Send Irq Response
uint32_t abort_read_data: 1 Abort Read Data
uint32_t send_ccsd: 1 Send CCSD
uint32_t send_auto_stop_ccsd: 1 Send Auto Stop CCSD
uint32_t ceata_device_interrupt_status: 1 Ceata Device Interrupt Status
uint32_t __pad2__: 13 UNDEFINED
uint32_t use_internal_dmac: 1 Use Internal DMAC
uint32_t __pad3__: 6 UNDEFINED

Macro Definitions

#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE   0x0

Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST

No change -default

#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE   0x1

Enumerated value for register field ALT_SDMMC_CTL_CTLLER_RST

Reset SD/MMC controller

#define ALT_SDMMC_CTL_CTLLER_RST_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field.

#define ALT_SDMMC_CTL_CTLLER_RST_MSB   0

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CTLLER_RST register field.

#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_CTLLER_RST register field.

#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK   0x00000001

The mask used to set the ALT_SDMMC_CTL_CTLLER_RST register field value.

#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SDMMC_CTL_CTLLER_RST register field value.

#define ALT_SDMMC_CTL_CTLLER_RST_RESET   0x0

The reset value of the ALT_SDMMC_CTL_CTLLER_RST register field.

#define ALT_SDMMC_CTL_CTLLER_RST_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SDMMC_CTL_CTLLER_RST field value from a register.

#define ALT_SDMMC_CTL_CTLLER_RST_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SDMMC_CTL_CTLLER_RST register field value suitable for setting the register.

#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE   0x0

Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST

No change

#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE   0x1

Enumerated value for register field ALT_SDMMC_CTL_FIFO_RST

Reset to data FIFO To reset FIFO pointers

#define ALT_SDMMC_CTL_FIFO_RST_LSB   1

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_FIFO_RST register field.

#define ALT_SDMMC_CTL_FIFO_RST_MSB   1

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_FIFO_RST register field.

#define ALT_SDMMC_CTL_FIFO_RST_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_FIFO_RST register field.

#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK   0x00000002

The mask used to set the ALT_SDMMC_CTL_FIFO_RST register field value.

#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SDMMC_CTL_FIFO_RST register field value.

#define ALT_SDMMC_CTL_FIFO_RST_RESET   0x0

The reset value of the ALT_SDMMC_CTL_FIFO_RST register field.

#define ALT_SDMMC_CTL_FIFO_RST_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SDMMC_CTL_FIFO_RST field value from a register.

#define ALT_SDMMC_CTL_FIFO_RST_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SDMMC_CTL_FIFO_RST register field value suitable for setting the register.

#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE   0x0

Enumerated value for register field ALT_SDMMC_CTL_DMA_RST

No change

#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE   0x1

Enumerated value for register field ALT_SDMMC_CTL_DMA_RST

Reset internal DMA interface control logic

#define ALT_SDMMC_CTL_DMA_RST_LSB   2

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_DMA_RST register field.

#define ALT_SDMMC_CTL_DMA_RST_MSB   2

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_DMA_RST register field.

#define ALT_SDMMC_CTL_DMA_RST_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_DMA_RST register field.

#define ALT_SDMMC_CTL_DMA_RST_SET_MSK   0x00000004

The mask used to set the ALT_SDMMC_CTL_DMA_RST register field value.

#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SDMMC_CTL_DMA_RST register field value.

#define ALT_SDMMC_CTL_DMA_RST_RESET   0x0

The reset value of the ALT_SDMMC_CTL_DMA_RST register field.

#define ALT_SDMMC_CTL_DMA_RST_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SDMMC_CTL_DMA_RST field value from a register.

#define ALT_SDMMC_CTL_DMA_RST_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SDMMC_CTL_DMA_RST register field value suitable for setting the register.

#define ALT_SDMMC_CTL_INT_EN_E_DISD   0x0

Enumerated value for register field ALT_SDMMC_CTL_INT_EN

Disable Interrupts

#define ALT_SDMMC_CTL_INT_EN_E_END   0x1

Enumerated value for register field ALT_SDMMC_CTL_INT_EN

Enable interrupts

#define ALT_SDMMC_CTL_INT_EN_LSB   4

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_INT_EN register field.

#define ALT_SDMMC_CTL_INT_EN_MSB   4

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_INT_EN register field.

#define ALT_SDMMC_CTL_INT_EN_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_INT_EN register field.

#define ALT_SDMMC_CTL_INT_EN_SET_MSK   0x00000010

The mask used to set the ALT_SDMMC_CTL_INT_EN register field value.

#define ALT_SDMMC_CTL_INT_EN_CLR_MSK   0xffffffef

The mask used to clear the ALT_SDMMC_CTL_INT_EN register field value.

#define ALT_SDMMC_CTL_INT_EN_RESET   0x0

The reset value of the ALT_SDMMC_CTL_INT_EN register field.

#define ALT_SDMMC_CTL_INT_EN_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SDMMC_CTL_INT_EN field value from a register.

#define ALT_SDMMC_CTL_INT_EN_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SDMMC_CTL_INT_EN register field value suitable for setting the register.

#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT   0x0

Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT

Read Wait

#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT   0x1

Enumerated value for register field ALT_SDMMC_CTL_RD_WAIT

Assert Read Wait

#define ALT_SDMMC_CTL_RD_WAIT_LSB   6

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_RD_WAIT register field.

#define ALT_SDMMC_CTL_RD_WAIT_MSB   6

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_RD_WAIT register field.

#define ALT_SDMMC_CTL_RD_WAIT_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_RD_WAIT register field.

#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK   0x00000040

The mask used to set the ALT_SDMMC_CTL_RD_WAIT register field value.

#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SDMMC_CTL_RD_WAIT register field value.

#define ALT_SDMMC_CTL_RD_WAIT_RESET   0x0

The reset value of the ALT_SDMMC_CTL_RD_WAIT register field.

#define ALT_SDMMC_CTL_RD_WAIT_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SDMMC_CTL_RD_WAIT field value from a register.

#define ALT_SDMMC_CTL_RD_WAIT_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SDMMC_CTL_RD_WAIT register field value suitable for setting the register.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE   0x0

Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE

No change

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE   0x1

Enumerated value for register field ALT_SDMMC_CTL_SEND_IRQ_RESPONSE

Send auto IRQ response

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB   7

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK   0x00000080

The mask used to set the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET   0x0

The reset value of the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SDMMC_CTL_SEND_IRQ_RESPONSE field value from a register.

#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SDMMC_CTL_SEND_IRQ_RESPONSE register field value suitable for setting the register.

#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE   0x0

Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA

No change

#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE   0x1

Enumerated value for register field ALT_SDMMC_CTL_ABT_RD_DATA

Abort Read

#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field.

#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB   8

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_ABT_RD_DATA register field.

#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_ABT_RD_DATA register field.

#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK   0x00000100

The mask used to set the ALT_SDMMC_CTL_ABT_RD_DATA register field value.

#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SDMMC_CTL_ABT_RD_DATA register field value.

#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET   0x0

The reset value of the ALT_SDMMC_CTL_ABT_RD_DATA register field.

#define ALT_SDMMC_CTL_ABT_RD_DATA_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SDMMC_CTL_ABT_RD_DATA field value from a register.

#define ALT_SDMMC_CTL_ABT_RD_DATA_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SDMMC_CTL_ABT_RD_DATA register field value suitable for setting the register.

#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT   0x0

Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD

Clear bit if SD/MMC does not reset the bit

#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT   0x1

Enumerated value for register field ALT_SDMMC_CTL_SEND_CCSD

Send Command Completion Signal Disable (CCSD) to CE-ATA device

#define ALT_SDMMC_CTL_SEND_CCSD_LSB   9

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field.

#define ALT_SDMMC_CTL_SEND_CCSD_MSB   9

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_CCSD register field.

#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_SEND_CCSD register field.

#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK   0x00000200

The mask used to set the ALT_SDMMC_CTL_SEND_CCSD register field value.

#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SDMMC_CTL_SEND_CCSD register field value.

#define ALT_SDMMC_CTL_SEND_CCSD_RESET   0x0

The reset value of the ALT_SDMMC_CTL_SEND_CCSD register field.

#define ALT_SDMMC_CTL_SEND_CCSD_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SDMMC_CTL_SEND_CCSD field value from a register.

#define ALT_SDMMC_CTL_SEND_CCSD_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SDMMC_CTL_SEND_CCSD register field value suitable for setting the register.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT   0x0

Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD

Clear bit if SD/MMC does not reset the bit

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT   0x1

Enumerated value for register field ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD

Send internally generated STOP.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB   10

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB   10

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK   0x00000400

The mask used to set the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET   0x0

The reset value of the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD field value from a register.

#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD register field value suitable for setting the register.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD   0x0

Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT

Interrupts not enabled in CE-ATA device

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END   0x1

Enumerated value for register field ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT

Interrupts are enabled in CE-ATA device

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB   11

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB   11

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK   0x00000800

The mask used to set the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET   0x0

The reset value of the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT field value from a register.

#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT register field value suitable for setting the register.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD   0x0

Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC

The host performs data transfers thru slave interface

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END   0x1

Enumerated value for register field ALT_SDMMC_CTL_USE_INTERNAL_DMAC

Internal DMAC used for data transfer

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB   25

The Least Significant Bit (LSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB   25

The Most Significant Bit (MSB) position of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH   1

The width in bits of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK   0x02000000

The mask used to set the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK   0xfdffffff

The mask used to clear the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET   0x0

The reset value of the ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_SDMMC_CTL_USE_INTERNAL_DMAC field value from a register.

#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_SDMMC_CTL_USE_INTERNAL_DMAC register field value suitable for setting the register.

#define ALT_SDMMC_CTL_OFST   0x0

The byte offset of the ALT_SDMMC_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_CTL.