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Altera HWLIB
16.0
The Altera HW Manager API Reference Manual
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#include "hwlib.h"
#include "socal/alt_clkmgr.h"
Go to the source code of this file.
Contains the definition of an opaque data structure that contains raw configuration information for a clock group.
Typedefs | |
typedef enum ALT_CLK_GRP_e | ALT_CLK_GRP_t |
typedef struct ALT_CLK_GROUP_RAW_CFG_s | ALT_CLK_GROUP_RAW_CFG_t |
Enumerations | |
enum | ALT_CLK_GRP_e { ALT_MAIN_PLL_CLK_GRP, ALT_PERIPH_PLL_CLK_GRP, ALT_SDRAM_PLL_CLK_GRP } |
struct ALT_CLK_GROUP_RAW_CFG_s |
This type definition defines an opaque data structure for holding the configuration settings for a complete clock group.
Data Fields | ||
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uint32_t | verid | SoC FPGA version identifier. This field encapsulates the silicon identifier and version information associated with this clock group configuration. It is used to assert that this clock group configuration is valid for this device. |
uint32_t | siliid2 | Reserved register - reserved for future device IDs or capability flags. |
ALT_CLK_GRP_t | clkgrpsel | Clock group union discriminator. |
union ALT_CLK_GROUP_RAW_CFG_u | clkgrp |
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u |
This union holds the register values for configuration of the set of possible clock groups on the SoC FPGA. The clkgrpsel discriminator identifies the valid clock group union data member.
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.mainpllgrp |
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.perpllgrp |
union ALT_CLK_GROUP_RAW_CFG_s::ALT_CLK_GROUP_RAW_CFG_u.sdrpllgrp |
typedef enum ALT_CLK_GRP_e ALT_CLK_GRP_t |
This type definition enumerates the clock groups
typedef struct ALT_CLK_GROUP_RAW_CFG_s ALT_CLK_GROUP_RAW_CFG_t |
This type definition defines an opaque data structure for holding the configuration settings for a complete clock group.
enum ALT_CLK_GRP_e |