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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Write One to Set corresonding fields in Enable Register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | emac0_clk Enable |
[1] | RW | 0x1 | emac1_clk_clk Enable |
[2] | RW | 0x1 | emac2_clk Enable |
[3] | RW | 0x1 | emac_ptp_clk Enable |
[4] | RW | 0x1 | gpio_db_clk Enable |
[5] | RW | 0x1 | SDMMC Clock Enable |
[6] | RW | 0x1 | s2f_user1_clk Enable |
[7] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x1 | USB Clock Enable |
[9] | RW | 0x1 | SPIM Clock Enable |
[10] | RW | 0x1 | NAND Clock Enable |
[11] | RW | 0x1 | QSPI Clock Enable |
[31:12] | ??? | 0x0 | UNDEFINED |
Field : emac0_clk Enable - emac0en | |
Enables clock emac0_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET(value) (((value) << 0) & 0x00000001) |
Field : emac1_clk_clk Enable - emac1en | |
Enables clock emac1_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET(value) (((value) << 1) & 0x00000002) |
Field : emac2_clk Enable - emac2en | |
Enables clock emac2_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET(value) (((value) << 2) & 0x00000004) |
Field : emac_ptp_clk Enable - emacptpen | |
Enables clock emac_ptp_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008) |
Field : gpio_db_clk Enable - gpiodben | |
Enables clock gpio_db_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4 |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4 |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010 |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET(value) (((value) << 4) & 0x00000010) |
Field : SDMMC Clock Enable - sdmmcclken | |
Enables SDMMC peripheral clock. This enable goes outside of the Clock Manger to the SDMMC directly. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5 |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5 |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020 |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020) |
Field : s2f_user1_clk Enable - s2fuser1clken | |
Enables clock s2f_user1_clk output Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6 |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6 |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040 |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040) |
Field : USB Clock Enable - usbclken | |
Enables USB peripheral clock. This enable goes outside of the Clock Manger to the USB directly. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8 |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8 |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100 |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET(value) (((value) << 8) & 0x00000100) |
Field : SPIM Clock Enable - spimclken | |
Enables SPI Master peripheral clock. This enable goes outside of the Clock Manger to the SPIM directly. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9 |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9 |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200 |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200) |
Field : NAND Clock Enable - nandclken | |
Enables NAND peripheral clock. This enable goes outside of the Clock Manger to the NAND directly. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10 |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10 |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400 |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400) |
Field : QSPI Clock Enable - qspiclken | |
Enables QSPI peripheral clock. This enable goes outside of the Clock Manger to the QSPI directly. Field Access Macros: | |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_LSB 11 |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_MSB 11 |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_WIDTH 1 |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET_MSK 0x00000800 |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_CLR_MSK 0xfffff7ff |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_RESET 0x1 |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800) |
Data Structures | |
struct | ALT_CLKMGR_PERPLL_ENS_s |
Macros | |
#define | ALT_CLKMGR_PERPLL_ENS_RESET 0x00000f7f |
#define | ALT_CLKMGR_PERPLL_ENS_OFST 0xc |
Typedefs | |
typedef struct ALT_CLKMGR_PERPLL_ENS_s | ALT_CLKMGR_PERPLL_ENS_t |
struct ALT_CLKMGR_PERPLL_ENS_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_PERPLL_ENS.
Data Fields | ||
---|---|---|
uint32_t | emac0en: 1 | emac0_clk Enable |
uint32_t | emac1en: 1 | emac1_clk_clk Enable |
uint32_t | emac2en: 1 | emac2_clk Enable |
uint32_t | emacptpen: 1 | emac_ptp_clk Enable |
uint32_t | gpiodben: 1 | gpio_db_clk Enable |
uint32_t | sdmmcclken: 1 | SDMMC Clock Enable |
uint32_t | s2fuser1clken: 1 | s2f_user1_clk Enable |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | usbclken: 1 | USB Clock Enable |
uint32_t | spimclken: 1 | SPIM Clock Enable |
uint32_t | nandclken: 1 | NAND Clock Enable |
uint32_t | qspiclken: 1 | QSPI Clock Enable |
uint32_t | __pad1__: 20 | UNDEFINED |
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC0EN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_PERPLL_ENS_EMAC0EN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC1EN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_PERPLL_ENS_EMAC1EN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_PERPLL_ENS_EMAC2EN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_PERPLL_ENS_EMAC2EN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_CLKMGR_PERPLL_ENS_EMACPTPEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_CLKMGR_PERPLL_ENS_EMACPTPEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_CLKMGR_PERPLL_ENS_GPIODBEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_CLKMGR_PERPLL_ENS_GPIODBEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_CLKMGR_PERPLL_ENS_USBCLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_CLKMGR_PERPLL_ENS_USBCLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_CLKMGR_PERPLL_ENS_NANDCLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_CLKMGR_PERPLL_ENS_NANDCLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET_MSK 0x00000800 |
The mask used to set the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_CLKMGR_PERPLL_ENS_QSPICLKEN field value from a register.
#define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_CLKMGR_PERPLL_ENS_QSPICLKEN register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_ENS_RESET 0x00000f7f |
The reset value of the ALT_CLKMGR_PERPLL_ENS register.
#define ALT_CLKMGR_PERPLL_ENS_OFST 0xc |
The byte offset of the ALT_CLKMGR_PERPLL_ENS register from the beginning of the component.
typedef struct ALT_CLKMGR_PERPLL_ENS_s ALT_CLKMGR_PERPLL_ENS_t |
The typedef declaration for register ALT_CLKMGR_PERPLL_ENS.