Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : uhs_reg

Description

UHS-1 Register

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_SDMMC_UHS_REG_VOLT_REG
[31:16] RW 0x0 ALT_SDMMC_UHS_REG_DDR_REG

Field : volt_reg

High Voltage mode. Determines the voltage fed to the buffers by an

external voltage regulator.

0 Buffers supplied with 3.3V Vdd

1 Buffers supplied with 1.8V Vdd

These bits function as the output of the host controller and are fed to an external voltage regulator. The voltage regulator must switch the voltage of the buffers of a particular card to either 3.3V or 1.8V, depending on the

value programmed in the register.

VOLT_REG[0] should be set to 1’b1 for card number 0 in order to make it

operate for 1.8V.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0 Buffers supplied with 3.3V Vdd
ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1 Buffers supplied with 1.8V Vdd

Field Access Macros:

#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V   0x0
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V   0x1
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_LSB   0
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_MSB   15
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH   16
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK   0x0000ffff
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK   0xffff0000
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : ddr_reg

DDR mode. These bits indicate DDR mode of operation to the core for the data transfer.

0 Non-DDR mode

1 DDR mode

UHS_REG [16] should be set for card number 0, UHS_REG [17] for card number 1 and so on.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0 Non-DDR mode
ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1 DDR mode

Field Access Macros:

#define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR   0x0
 
#define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR   0x1
 
#define ALT_SDMMC_UHS_REG_DDR_REG_LSB   16
 
#define ALT_SDMMC_UHS_REG_DDR_REG_MSB   31
 
#define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH   16
 
#define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK   0xffff0000
 
#define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK   0x0000ffff
 
#define ALT_SDMMC_UHS_REG_DDR_REG_RESET   0x0
 
#define ALT_SDMMC_UHS_REG_DDR_REG_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_SDMMC_UHS_REG_DDR_REG_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_SDMMC_UHS_REG_s
 

Macros

#define ALT_SDMMC_UHS_REG_RESET   0x00000000
 
#define ALT_SDMMC_UHS_REG_OFST   0x74
 

Typedefs

typedef struct ALT_SDMMC_UHS_REG_s ALT_SDMMC_UHS_REG_t
 

Data Structure Documentation

struct ALT_SDMMC_UHS_REG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_UHS_REG.

Data Fields
uint32_t volt_reg: 16 ALT_SDMMC_UHS_REG_VOLT_REG
uint32_t ddr_reg: 16 ALT_SDMMC_UHS_REG_DDR_REG

Macro Definitions

#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V   0x0

Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG

Buffers supplied with 3.3V Vdd

#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V   0x1

Enumerated value for register field ALT_SDMMC_UHS_REG_VOLT_REG

Buffers supplied with 1.8V Vdd

#define ALT_SDMMC_UHS_REG_VOLT_REG_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_VOLT_REG_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH   16

The width in bits of the ALT_SDMMC_UHS_REG_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK   0x0000ffff

The mask used to set the ALT_SDMMC_UHS_REG_VOLT_REG register field value.

#define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK   0xffff0000

The mask used to clear the ALT_SDMMC_UHS_REG_VOLT_REG register field value.

#define ALT_SDMMC_UHS_REG_VOLT_REG_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_VOLT_REG register field.

#define ALT_SDMMC_UHS_REG_VOLT_REG_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_SDMMC_UHS_REG_VOLT_REG field value from a register.

#define ALT_SDMMC_UHS_REG_VOLT_REG_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_SDMMC_UHS_REG_VOLT_REG register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR   0x0

Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG

Non-DDR mode

#define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR   0x1

Enumerated value for register field ALT_SDMMC_UHS_REG_DDR_REG

DDR mode

#define ALT_SDMMC_UHS_REG_DDR_REG_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field.

#define ALT_SDMMC_UHS_REG_DDR_REG_MSB   31

The Most Significant Bit (MSB) position of the ALT_SDMMC_UHS_REG_DDR_REG register field.

#define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH   16

The width in bits of the ALT_SDMMC_UHS_REG_DDR_REG register field.

#define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK   0xffff0000

The mask used to set the ALT_SDMMC_UHS_REG_DDR_REG register field value.

#define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK   0x0000ffff

The mask used to clear the ALT_SDMMC_UHS_REG_DDR_REG register field value.

#define ALT_SDMMC_UHS_REG_DDR_REG_RESET   0x0

The reset value of the ALT_SDMMC_UHS_REG_DDR_REG register field.

#define ALT_SDMMC_UHS_REG_DDR_REG_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_SDMMC_UHS_REG_DDR_REG field value from a register.

#define ALT_SDMMC_UHS_REG_DDR_REG_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_SDMMC_UHS_REG_DDR_REG register field value suitable for setting the register.

#define ALT_SDMMC_UHS_REG_RESET   0x00000000

The reset value of the ALT_SDMMC_UHS_REG register.

#define ALT_SDMMC_UHS_REG_OFST   0x74

The byte offset of the ALT_SDMMC_UHS_REG register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_UHS_REG.