Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Voltage Level Configuration Register - configuration_dedicated_io_bank

Description

This register is used to control the voltage select for all dedicated IO.

Register Layout

Bits Access Reset Description
[1:0] RW 0x0 Voltage select
[7:2] R 0x0 ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2
[9:8] RW 0x0 Voltage select
[31:10] R 0x0 ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10

Field : Voltage select - VOLTAGE_SEL_PERI_IO

Configuration bits for voltage select. This only affects peripheral IO (exclude CLK and RST IO).

00 : 3.0V operation

01 : 1.8V operation

10 : 2.5V operation

11 : RSVD

Field Access Macros:

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_LSB   0
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_MSB   1
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_WIDTH   2
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET_MSK   0x00000003
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_CLR_MSK   0xfffffffc
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_RESET   0x0
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET(value)   (((value) << 0) & 0x00000003)
 

Field : Reserved_7to2

Reserved

Field Access Macros:

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_LSB   2
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_MSB   7
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_WIDTH   6
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET_MSK   0x000000fc
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_CLR_MSK   0xffffff03
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_RESET   0x0
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_GET(value)   (((value) & 0x000000fc) >> 2)
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET(value)   (((value) << 2) & 0x000000fc)
 

Field : Voltage select - VOLTAGE_SEL_CLKRST_IO

Configuration bits for voltage select. This only affects CLK and RST IO.

00 : 3.0V operation

01 : 1.8V operation

10 : 2.5V operation

11 : RSVD

Field Access Macros:

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_LSB   8
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_MSB   9
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_WIDTH   2
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET_MSK   0x00000300
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_CLR_MSK   0xfffffcff
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_RESET   0x0
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_GET(value)   (((value) & 0x00000300) >> 8)
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET(value)   (((value) << 8) & 0x00000300)
 

Field : Reserved_31to10

Reserved

Field Access Macros:

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_LSB   10
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_MSB   31
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_WIDTH   22
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET_MSK   0xfffffc00
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_CLR_MSK   0x000003ff
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_RESET   0x0
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_GET(value)   (((value) & 0xfffffc00) >> 10)
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET(value)   (((value) << 10) & 0xfffffc00)
 

Data Structures

struct  ALT_PINMUX_DCTD_IO_CFG_BANK_s
 

Macros

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RESET   0x00000000
 
#define ALT_PINMUX_DCTD_IO_CFG_BANK_OFST   0x100
 

Typedefs

typedef struct
ALT_PINMUX_DCTD_IO_CFG_BANK_s 
ALT_PINMUX_DCTD_IO_CFG_BANK_t
 

Data Structure Documentation

struct ALT_PINMUX_DCTD_IO_CFG_BANK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_BANK.

Data Fields
uint32_t VOLTAGE_SEL_PERI_IO: 2 Voltage select
const uint32_t Reserved_7to2: 6 ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2
uint32_t VOLTAGE_SEL_CLKRST_IO: 2 Voltage select
const uint32_t Reserved_31to10: 22 ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10

Macro Definitions

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_LSB   0

The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_MSB   1

The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_WIDTH   2

The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET_MSK   0x00000003

The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_CLR_MSK   0xfffffffc

The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_RESET   0x0

The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO field value from a register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_PERI_IO register field value suitable for setting the register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_LSB   2

The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_MSB   7

The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_WIDTH   6

The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET_MSK   0x000000fc

The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_CLR_MSK   0xffffff03

The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_RESET   0x0

The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_GET (   value)    (((value) & 0x000000fc) >> 2)

Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 field value from a register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2_SET (   value)    (((value) << 2) & 0x000000fc)

Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_7TO2 register field value suitable for setting the register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_LSB   8

The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_MSB   9

The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_WIDTH   2

The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET_MSK   0x00000300

The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_CLR_MSK   0xfffffcff

The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_RESET   0x0

The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_GET (   value)    (((value) & 0x00000300) >> 8)

Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO field value from a register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO_SET (   value)    (((value) << 8) & 0x00000300)

Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_VOLTAGE_SEL_CLKRST_IO register field value suitable for setting the register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_LSB   10

The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_MSB   31

The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_WIDTH   22

The width in bits of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET_MSK   0xfffffc00

The mask used to set the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_CLR_MSK   0x000003ff

The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_RESET   0x0

The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_GET (   value)    (((value) & 0xfffffc00) >> 10)

Extracts the ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 field value from a register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10_SET (   value)    (((value) << 10) & 0xfffffc00)

Produces a ALT_PINMUX_DCTD_IO_CFG_BANK_RSVD_31TO10 register field value suitable for setting the register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_RESET   0x00000000

The reset value of the ALT_PINMUX_DCTD_IO_CFG_BANK register.

#define ALT_PINMUX_DCTD_IO_CFG_BANK_OFST   0x100

The byte offset of the ALT_PINMUX_DCTD_IO_CFG_BANK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_BANK.