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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The control bits of the IF1/2 Command Register specify the transfer direction and select which portions of the Message Object should be transferred. A message transfer is started as soon as the CPU has written the message number to the low byte of the Command Request Register and IFxCMR.AutoInc is zero. With this write operation, the IFxCMR.Busy bit is automatically set to 1 to notify the CPU that a transfer is in progress. After a wait time of 2 to 8 HOST_CLK periods, the transfer between theInterface Register and the Message RAM has been completed and the IFxCMR.Busy bit is cleared to 0. The upper limit of the wait time occurs when the message transfer coincides with a CAN message transmission, acceptance filtering, or message storage. If the CPU writes to both Command Registers consecutively (requests a second transfer while another transfer is already in progress), the second transfer starts when the first one is completed. Note: While Busy bit of IF1/2 Command Register is one, IF1/2 Register Set is write protected.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x1 | Message Number |
[12:8] | ??? | 0x0 | UNDEFINED |
[13] | RW | 0x0 | Automatic Increment of Message Object Number |
[14] | RW | 0x0 | Activation of DMA feature for subsequent internal IFx Register Set |
[15] | R | 0x0 | Busy Flag |
[16] | RW | 0x0 | Access Data Bytes 4-7 |
[17] | RW | 0x0 | Access Data Bytes 0-3 |
[18] | RW | 0x0 | Access Transmission Request Bit and NewDat Bit |
[19] | RW | 0x0 | Clear Interrupt Pending Bit |
[20] | RW | 0x0 | Access Control Bits |
[21] | RW | 0x0 | Access Arbitration Bits |
[22] | RW | 0x0 | Access Mask Bits |
[23] | RW | 0x0 | Write / Read Transfer |
[28:24] | ??? | 0x0 | UNDEFINED |
[29] | RW | 0x0 | Clear the AutoInc bit without starting a transfer |
[31:30] | ??? | 0x0 | UNDEFINED |
Field : Message Number - MONum | |
0x01-0x80 Valid Message Number, the Message Object in the Message RAM is selected for data transfer (up to 128 MsgObj). 0x00 Not a valid Message Number, interpreted as 0x80. 0x81-0xFF Not a valid Message Number, interpreted as 0x01-0x7F. Note: When an invalid Message Number is written to IFxCMR.MONum which is higher than the last Message Object number, a modulo addressing will occur.When e.g. accessing Message Object 33 in a CAN module with 32 Message Objects only, the Message Object 1 will be accessed instead. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_LSB 0 |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_MSB 7 |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_WIDTH 8 |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_SET_MSK 0x000000ff |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_CLR_MSK 0xffffff00 |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_RESET 0x1 |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_CAN_MSGIF_IF1CMR_MONUM_SET(value) (((value) << 0) & 0x000000ff) |
Field : Automatic Increment of Message Object Number - AutoInc | ||||||||||
Automatic Increment of Message Object Number The behavior of the Message Object Number increment depends on the Transfer Direction, IFxCMR.WR1RD0.
Always after successful transfer the Busy Bit will be reset. In combination with DMAactive the port CAN_IFxDMA is set, too. Note: If the direction is configured as Read a write access to Data-Byte 7 will not start any transfer, as well as if the direction is configured as Write a read access to Data-Byte 7 will not start any transfer. At transfer direction Read each read of Data-Byte 7 will start a transfer until IFxCMR.AutoInc is reset. To aware of resetting a NewDat bit of the following message object, the application has to reset IFxCMR.AutoInc before reading the Data-Byte 7 of the last message object which will be read. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_DISD 0x0 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_END 0x1 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_LSB 13 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_MSB 13 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_WIDTH 1 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET_MSK 0x00002000 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_CLR_MSK 0xffffdfff | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_RESET 0x0 | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_GET(value) (((value) & 0x00002000) >> 13) | |||||||||
#define | ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET(value) (((value) << 13) & 0x00002000) | |||||||||
Field : Activation of DMA feature for subsequent internal IFx Register Set - DMAactive | |||||||||||||||||||||||||||||||||||||||||||||||||
Activation of DMA feature for subsequent internal IFx Register Set Field Enumeration Values:
Field Access Macros: | |||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_E_PASSIVE 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_E_INITIATED 0x1 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_LSB 14 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_MSB 14 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_WIDTH 1 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_SET_MSK 0x00004000 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_CLR_MSK 0xffffbfff | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_RESET 0x0 | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_GET(value) (((value) & 0x00004000) >> 14) | ||||||||||||||||||||||||||||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_DMAACT_SET(value) (((value) << 14) & 0x00004000) | ||||||||||||||||||||||||||||||||||||||||||||||||
Field : Busy Flag - Busy | ||||||||||||||||
Busy Flag Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_E_DONE 0x0 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_E_WRITING 0x1 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_LSB 15 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_MSB 15 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_WIDTH 1 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_SET_MSK 0x00008000 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_CLR_MSK 0xffff7fff | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_RESET 0x0 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_GET(value) (((value) & 0x00008000) >> 15) | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_BUSY_SET(value) (((value) << 15) & 0x00008000) | |||||||||||||||
Field : Access Data Bytes 4-7 - DataB | |
Write Direction: 0= Data Bytes 4-7 unchanged. 1= transfer Data Bytes 4-7 to Message Object. Read Direction: 0= Data Bytes 4-7 unchanged. 1= transfer Data Bytes 4-7 to IFxDB. Note: The speed of the message transfer does not depend on how many bytes are transferred. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_LSB 16 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_MSB 16 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_SET_MSK 0x00010000 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_CLR_MSK 0xfffeffff |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_CAN_MSGIF_IF1CMR_DATAB_SET(value) (((value) << 16) & 0x00010000) |
Field : Access Data Bytes 0-3 - DataA | |
Write Direction: 0= Data Bytes 0-3 unchanged. 1= transfer Data Bytes 0-3 to Message Object. Read Direction: 0= Data Bytes 0-3 unchanged. 1= transfer Data Bytes 0-3 to IFxDA. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_LSB 17 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_MSB 17 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_SET_MSK 0x00020000 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_CLR_MSK 0xfffdffff |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_CAN_MSGIF_IF1CMR_DATAA_SET(value) (((value) << 17) & 0x00020000) |
Field : Access Transmission Request Bit and NewDat Bit - TxRqstNewDat | |
Write Direction: 0= TxRqst and NewDat bit will be handled according IFxMCTR.NewDat bit and IFxMCTR.TxRqst bit. 1= set TxRqst and NewDat in Message Object to one Note: If a CAN transmission is requested by setting IFxCMR.TxRqst/NewDat, the TxRqst and NewDat bits in the Message Object will be set to one independently of the values in IFxMCTR. Read Direction: 0= NewDat bit remains unchanged. 1= clear NewDat bit in the Message Object. Note: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat. The values of these bits transferred to the IFxMCTR always reflect the status before resetting them. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_LSB 18 |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_MSB 18 |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET_MSK 0x00040000 |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_CLR_MSK 0xfffbffff |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET(value) (((value) << 18) & 0x00040000) |
Field : Clear Interrupt Pending Bit - ClrIntPnd | |
Write Direction: Has no influence to Message Object at write transfer. Note: When writing to a Message Object, this bit is ignored and copying of IntPnd flag from IFx Control Register to Message RAM could only be controlled by IFxMTR.IntPnd bit. Read Direction: 0= IntPnd bit remains unchanged. 1= clear IntPnd bit in the Message Object. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_LSB 19 |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_MSB 19 |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET_MSK 0x00080000 |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_CLR_MSK 0xfff7ffff |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET(value) (((value) << 19) & 0x00080000) |
Field : Access Control Bits - Control | |
Write Direction: 0= Control Bits unchanged. 1= transfer Control Bits to Message Object. Note: If IFxCMR.TxRqst/NewDat bit is set, bits IFxMCTR.TxRqst and IFxMCTR.NewDat will be ignored. Read Direction: 0= Control Bits unchanged. 1= transfer Control Bits to IFxMCTR Register. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_LSB 20 |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_MSB 20 |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_SET_MSK 0x00100000 |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_CLR_MSK 0xffefffff |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_CAN_MSGIF_IF1CMR_CTL_SET(value) (((value) << 20) & 0x00100000) |
Field : Access Arbitration Bits - Arb | |
Write Direction: 0= Arbitration bits unchanged. 1= transfer Identifier + Dir + Xtd + MsgVal to Message Object. Read Direction: 0= Arbitration bits unchanged. 1= transfer Identifier + Dir + Xtd + MsgVal to IFxARB Register. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_LSB 21 |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_MSB 21 |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_SET_MSK 0x00200000 |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_CLR_MSK 0xffdfffff |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_CAN_MSGIF_IF1CMR_ARB_SET(value) (((value) << 21) & 0x00200000) |
Field : Access Mask Bits - Mask | |
Write Direction: 0= Mask bits unchanged. 1= transfer Identifier Mask + MDir + MXtd to Message Object. Read Direction: 0= Mask bits unchanged. 1= transfer Identifier Mask + MDir + MXtd to IFxMSK Register. Field Access Macros: | |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_LSB 22 |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_MSB 22 |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_WIDTH 1 |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_SET_MSK 0x00400000 |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_CLR_MSK 0xffbfffff |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_RESET 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_CAN_MSGIF_IF1CMR_MSK_SET(value) (((value) << 22) & 0x00400000) |
Field : Write / Read Transfer - WR1RD0 | ||||||||||||||||||||||
Write / Read Transfer Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_RD 0x0 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_WR 0x1 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_LSB 23 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_MSB 23 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_WIDTH 1 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET_MSK 0x00800000 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_CLR_MSK 0xff7fffff | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_RESET 0x0 | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_GET(value) (((value) & 0x00800000) >> 23) | |||||||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET(value) (((value) << 23) & 0x00800000) | |||||||||||||||||||||
Field : Clear the AutoInc bit without starting a transfer - ClrAutoInc | ||||||||||||||||
Clear the AutoInc bit without starting a transfer Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_NOCLR 0x0 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_CLR 0x1 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_LSB 29 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_MSB 29 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_WIDTH 1 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET_MSK 0x20000000 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_CLR_MSK 0xdfffffff | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_RESET 0x0 | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_GET(value) (((value) & 0x20000000) >> 29) | |||||||||||||||
#define | ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET(value) (((value) << 29) & 0x20000000) | |||||||||||||||
Data Structures | |
struct | ALT_CAN_MSGIF_IF1CMR_s |
Macros | |
#define | ALT_CAN_MSGIF_IF1CMR_OFST 0x0 |
#define | ALT_CAN_MSGIF_IF1CMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1CMR_OFST)) |
Typedefs | |
typedef struct ALT_CAN_MSGIF_IF1CMR_s | ALT_CAN_MSGIF_IF1CMR_t |
struct ALT_CAN_MSGIF_IF1CMR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CAN_MSGIF_IF1CMR.
Data Fields | ||
---|---|---|
uint32_t | MONum: 8 | Message Number |
uint32_t | __pad0__: 5 | UNDEFINED |
uint32_t | AutoInc: 1 | Automatic Increment of Message Object Number |
uint32_t | DMAactive: 1 | Activation of DMA feature for subsequent internal IFx Register Set |
const uint32_t | Busy: 1 | Busy Flag |
uint32_t | DataB: 1 | Access Data Bytes 4-7 |
uint32_t | DataA: 1 | Access Data Bytes 0-3 |
uint32_t | TxRqstNewDat: 1 | Access Transmission Request Bit and NewDat Bit |
uint32_t | ClrIntPnd: 1 | Clear Interrupt Pending Bit |
uint32_t | Control: 1 | Access Control Bits |
uint32_t | Arb: 1 | Access Arbitration Bits |
uint32_t | Mask: 1 | Access Mask Bits |
uint32_t | WR1RD0: 1 | Write / Read Transfer |
uint32_t | __pad1__: 5 | UNDEFINED |
uint32_t | ClrAutoInc: 1 | Clear the AutoInc bit without starting a transfer |
uint32_t | __pad2__: 2 | UNDEFINED |
#define ALT_CAN_MSGIF_IF1CMR_MONUM_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_MONUM register field.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_MONUM register field.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_WIDTH 8 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_MONUM register field.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_SET_MSK 0x000000ff |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_MONUM register field value.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_MONUM register field value.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_RESET 0x1 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_MONUM register field.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_CAN_MSGIF_IF1CMR_MONUM field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_MONUM_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_CAN_MSGIF_IF1CMR_MONUM register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_DISD 0x0 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_AUTOINC
AutoIncrement of Message Object Number disabled.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_E_END 0x1 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_AUTOINC
AutoIncrement of Message Object Number enabled.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET_MSK 0x00002000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_AUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_CAN_MSGIF_IF1CMR_AUTOINC field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_AUTOINC_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_CAN_MSGIF_IF1CMR_AUTOINC register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_E_PASSIVE 0x0 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_DMAACT
DMA line leaves passive, independent of IFx activities.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_E_INITIATED 0x1 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_DMAACT
By writing to the Command Request Register, an internal transfer of Message Object Data between RAM and IFx will be initiated. When this transfer is complete and DMAactive bit was set, the CAN_IFxDMA line gets active. The DMAactive bit and port CAN_IFxDMA are staying active until first read or write access to one of the IFx registers. If AutoInc is set DMAactive will be left active, otherwise the bit is reset.
Note: Due to auto reset feature of DMAactive bit if AutoInc is inactive, this bit has to be set for each subsequent DMA cycle separately. DMA line has to be enabled in CAN Control Register.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_SET_MSK 0x00004000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_DMAACT register field value.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DMAACT register field value.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_DMAACT register field.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_CAN_MSGIF_IF1CMR_DMAACT field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_DMAACT_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_CAN_MSGIF_IF1CMR_DMAACT register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_E_DONE 0x0 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_BUSY
Set to zero when read/write action has finished.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_E_WRITING 0x1 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_BUSY
Set to one when writing to the IFxCMR.MONum. While bit is one, IFx Register Set is write protected.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_BUSY register field.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_BUSY register field.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_BUSY register field.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_SET_MSK 0x00008000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_BUSY register field value.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_BUSY register field value.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_BUSY register field.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_CAN_MSGIF_IF1CMR_BUSY field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_BUSY_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_CAN_MSGIF_IF1CMR_BUSY register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAB register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAB register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_DATAB register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_SET_MSK 0x00010000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_DATAB register field value.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DATAB register field value.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_DATAB register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_CAN_MSGIF_IF1CMR_DATAB field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_DATAB_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_CAN_MSGIF_IF1CMR_DATAB register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAA register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_DATAA register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_DATAA register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_SET_MSK 0x00020000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_DATAA register field value.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_DATAA register field value.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_DATAA register field.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_CAN_MSGIF_IF1CMR_DATAA field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_DATAA_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_CAN_MSGIF_IF1CMR_DATAA register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET_MSK 0x00040000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_CAN_MSGIF_IF1CMR_TXRQSTNEWDAT register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET_MSK 0x00080000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_CAN_MSGIF_IF1CMR_CLRINTPND field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_CLRINTPND_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_CAN_MSGIF_IF1CMR_CLRINTPND register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_CTL_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CTL register field.
#define ALT_CAN_MSGIF_IF1CMR_CTL_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CTL register field.
#define ALT_CAN_MSGIF_IF1CMR_CTL_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_CTL register field.
#define ALT_CAN_MSGIF_IF1CMR_CTL_SET_MSK 0x00100000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_CTL register field value.
#define ALT_CAN_MSGIF_IF1CMR_CTL_CLR_MSK 0xffefffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CTL register field value.
#define ALT_CAN_MSGIF_IF1CMR_CTL_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_CTL register field.
#define ALT_CAN_MSGIF_IF1CMR_CTL_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_CAN_MSGIF_IF1CMR_CTL field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_CTL_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_CAN_MSGIF_IF1CMR_CTL register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_ARB_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_ARB register field.
#define ALT_CAN_MSGIF_IF1CMR_ARB_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_ARB register field.
#define ALT_CAN_MSGIF_IF1CMR_ARB_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_ARB register field.
#define ALT_CAN_MSGIF_IF1CMR_ARB_SET_MSK 0x00200000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_ARB register field value.
#define ALT_CAN_MSGIF_IF1CMR_ARB_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_ARB register field value.
#define ALT_CAN_MSGIF_IF1CMR_ARB_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_ARB register field.
#define ALT_CAN_MSGIF_IF1CMR_ARB_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_CAN_MSGIF_IF1CMR_ARB field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_ARB_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_CAN_MSGIF_IF1CMR_ARB register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_MSK_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_MSK register field.
#define ALT_CAN_MSGIF_IF1CMR_MSK_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_MSK register field.
#define ALT_CAN_MSGIF_IF1CMR_MSK_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_MSK register field.
#define ALT_CAN_MSGIF_IF1CMR_MSK_SET_MSK 0x00400000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_MSK register field value.
#define ALT_CAN_MSGIF_IF1CMR_MSK_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_MSK register field value.
#define ALT_CAN_MSGIF_IF1CMR_MSK_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_MSK register field.
#define ALT_CAN_MSGIF_IF1CMR_MSK_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_CAN_MSGIF_IF1CMR_MSK field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_MSK_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_CAN_MSGIF_IF1CMR_MSK register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_RD 0x0 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_WR1RD0
Transfer data from the Message Object addressed by IFxCMR.MONum into the selected IFx Message Buffer Registers.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_E_WR 0x1 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_WR1RD0
Transfer data from the selected IFx Message Buffer Registers to the Message Object addressed by IFxCMR.MONum.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET_MSK 0x00800000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_CAN_MSGIF_IF1CMR_WR1RD0 field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_WR1RD0_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_CAN_MSGIF_IF1CMR_WR1RD0 register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_NOCLR 0x0 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC
Has no effect to the other Bits of this Register.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_E_CLR 0x1 |
Enumerated value for register field ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC
Clear the AutoInc bit without starting a transfer, all other bits will be ignored.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_WIDTH 1 |
The width in bits of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET_MSK 0x20000000 |
The mask used to set the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_CLR_MSK 0xdfffffff |
The mask used to clear the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_RESET 0x0 |
The reset value of the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_GET | ( | value | ) | (((value) & 0x20000000) >> 29) |
Extracts the ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC field value from a register.
#define ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC_SET | ( | value | ) | (((value) << 29) & 0x20000000) |
Produces a ALT_CAN_MSGIF_IF1CMR_CLRAUTOINC register field value suitable for setting the register.
#define ALT_CAN_MSGIF_IF1CMR_OFST 0x0 |
The byte offset of the ALT_CAN_MSGIF_IF1CMR register from the beginning of the component.
#define ALT_CAN_MSGIF_IF1CMR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_CAN_MSGIF_IF1CMR_OFST)) |
The address of the ALT_CAN_MSGIF_IF1CMR register.
typedef struct ALT_CAN_MSGIF_IF1CMR_s ALT_CAN_MSGIF_IF1CMR_t |
The typedef declaration for register ALT_CAN_MSGIF_IF1CMR.