Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Device Control IN Endpoint 5 Control Register - diepctl5

Description

Endpoint_number: 5

Register Layout

Bits Access Reset Description
[10:0] RW 0x0 Maximum Packet Size
[14:11] ??? 0x0 UNDEFINED
[15] RW 0x0 USB Active Endpoint
[16] R 0x0 Endpoint Data PID
[17] R 0x0 NAK Status
[19:18] RW 0x0 Endpoint Type
[20] ??? 0x0 UNDEFINED
[21] R 0x0 STALL Handshake
[25:22] RW 0x0 TxFIFO Number
[26] W 0x0 Clear NAK
[27] W 0x0 Set NAK
[28] W 0x0 Set DATA0 PID
[29] W 0x0 Set DATA1 PID
[30] R 0x0 Endpoint Disable
[31] R 0x0 Endpoint Enable

Field : Maximum Packet Size - mps

Applies to IN and OUT endpoints. The application must program this field with the maximum packet size for the current logical endpoint. This value is in bytes.

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_MPS_LSB   0
 
#define ALT_USB_DEV_DIEPCTL5_MPS_MSB   10
 
#define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH   11
 
#define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK   0x000007ff
 
#define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK   0xfffff800
 
#define ALT_USB_DEV_DIEPCTL5_MPS_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_MPS_GET(value)   (((value) & 0x000007ff) >> 0)
 
#define ALT_USB_DEV_DIEPCTL5_MPS_SET(value)   (((value) << 0) & 0x000007ff)
 

Field : USB Active Endpoint - usbactep

Indicates whether this endpoint is active in the current configuration and interface. The core clears this bit for all endpoints (other than EP 0) after detecting a USB reset. After receiving the SetConfiguration and SetInterface commands, the application must program endpoint registers accordingly and set this bit.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD 0x0 Not Active
ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END 0x1 USB Active Endpoint

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD   0x0
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END   0x1
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB   15
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB   15
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK   0x00008000
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK   0xffff7fff
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Endpoint Data PID - dpid

Applies to interrupt/bulk IN and OUT endpoints only. Contains the PID of the packet to be received or transmitted on this endpoint. The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated. The applications use the SetD1PID and SetD0PID fields of this register to program either DATA0 or DATA1 PID. 0: DATA0 1: DATA1This field is applicable both for Scatter/Gather DMA mode and non- Scatter/Gather DMA mode. Even/Odd (Micro)Frame (EO_FrNum) In non-Scatter/Gather DMA mode:

Applies to isochronous IN and OUT endpoints only. Indicates the (micro)frame number in which the core transmits/receives isochronous data for this endpoint. The application must program the even/odd (micro) frame number in which it intends to transmit/receive isochronous data for this endpoint using the SetEvnFr and SetOddFr fields in this register.

0: Even (micro)frame

1: Odd (micro)frame

When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is provided in the transmit descriptor structure. The frame in which data is received is updated in receive descriptor structure.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_DPID_E_INACT 0x0 Endpoint Data PID not active
ALT_USB_DEV_DIEPCTL5_DPID_E_ACT 0x1 Endpoint Data PID active

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_DPID_LSB   16
 
#define ALT_USB_DEV_DIEPCTL5_DPID_MSB   16
 
#define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK   0x00010000
 
#define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK   0xfffeffff
 
#define ALT_USB_DEV_DIEPCTL5_DPID_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_DPID_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_USB_DEV_DIEPCTL5_DPID_SET(value)   (((value) << 16) & 0x00010000)
 

Field : NAK Status - naksts

When either the application or the core sets this bit:

  • The core stops receiving any data on an OUT endpoint, even if there is space in the RxFIFO to accommodate the incoming packet.
  • for non-isochronous IN endpoints: The core stops transmitting any data on an IN endpoint, even if there data is available in the TxFIFO.
  • for isochronous IN endpoints: The core sends out a zero-length data packet, even if there data is available in the TxFIFO.

Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK 0x0 The core is transmitting non-NAK handshakes
: based on the FIFO status
ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK 0x1 The core is transmitting NAK handshakes on this
: endpoint

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK   0x0
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK   0x1
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB   17
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB   17
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK   0x00020000
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK   0xfffdffff
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET(value)   (((value) << 17) & 0x00020000)
 

Field : Endpoint Type - eptype

This is the transfer type supported by this logical endpoint.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL 0x0 Control
ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS 0x1 Isochronous
ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK 0x2 Bulk
ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP 0x3 Interrupt

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS   0x1
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK   0x2
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP   0x3
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB   18
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB   19
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH   2
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK   0x000c0000
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK   0xfff3ffff
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET(value)   (((value) & 0x000c0000) >> 18)
 
#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET(value)   (((value) << 18) & 0x000c0000)
 

Field : STALL Handshake - stall

Applies to non-control, non-isochronous IN and OUT endpoints only. The application sets this bit to stall all tokens from the USB host to this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Only the application can clear this bit, never the core. Applies to control endpoints only. The application can only set this bit, and the core clears it, when a SETUP token is received for this endpoint. If a NAK bit, Global Non-periodic IN NAK, or Global OUT NAK is set along with this bit, the STALL bit takes priority. Irrespective of this bit's setting, the core always responds to SETUP data packets with an ACK handshake.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_STALL_E_INACT 0x0 STALL All Tokens not active
ALT_USB_DEV_DIEPCTL5_STALL_E_ACT 0x1 STALL All Tokens active

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_STALL_LSB   21
 
#define ALT_USB_DEV_DIEPCTL5_STALL_MSB   21
 
#define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK   0x00200000
 
#define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK   0xffdfffff
 
#define ALT_USB_DEV_DIEPCTL5_STALL_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_STALL_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_USB_DEV_DIEPCTL5_STALL_SET(value)   (((value) << 21) & 0x00200000)
 

Field : TxFIFO Number - txfnum

Shared FIFO Operation-non-periodic endpoints must set this bit to zero. Periodic endpoints must map this to the corresponding Periodic TxFIFO number.

4'h0: Non-Periodic TxFIFO

Others: Specified Periodic TxFIFO.number

An interrupt IN endpoint can be configured as a non-periodic endpoint for applications such as mass storage. The core treats an IN endpoint as a non- periodic endpoint if the TxFNum field is set to 0. Configuring an interrupt IN endpoint as a non-periodic endpoint saves the extra periodic FIFO area. Dedicated FIFO Operation-these bits specify the FIFO number associated with this endpoint. Each active IN endpoint must be programmed to a separate FIFO number. This field is valid only for IN endpoints.

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB   22
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB   25
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH   4
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK   0x03c00000
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK   0xfc3fffff
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET(value)   (((value) & 0x03c00000) >> 22)
 
#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET(value)   (((value) << 22) & 0x03c00000)
 

Field : Clear NAK - cnak

A write to this bit clears the NAK bit for the endpoint.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT 0x0 No Clear NAK
ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT 0x1 Clear NAK

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_LSB   26
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_MSB   26
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK   0x04000000
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK   0xfbffffff
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_USB_DEV_DIEPCTL5_CNAK_SET(value)   (((value) << 26) & 0x04000000)
 

Field : Set NAK - snak

A write to this bit sets the NAK bit for the endpoint. Using this bit, the application can control the transmission of NAK handshakes on an endpoint. The core can also Set this bit for an endpoint after a SETUP packet is received on that endpoint.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT 0x0 No Set NAK
ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT 0x1 Set NAK

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_LSB   27
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_MSB   27
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK   0x08000000
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK   0xf7ffffff
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_USB_DEV_DIEPCTL5_SNAK_SET(value)   (((value) << 27) & 0x08000000)
 

Field : Set DATA0 PID - setd0pid

Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA0. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode. In non-Scatter/Gather DMA mode: Set Even (micro)frame (SetEvenFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to even (micro) frame. When Scatter/Gather DMA mode is enabled, this field is reserved. The frame number in which to send data is in the transmit descriptor structure. The frame in which to receive data is updated in receive descriptor structure.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD 0x0 Disables Set DATA0 PID
ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END 0x1 Endpoint Data PID to DATA0)

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END   0x1
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB   28
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB   28
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK   0x10000000
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK   0xefffffff
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET(value)   (((value) & 0x10000000) >> 28)
 
#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET(value)   (((value) << 28) & 0x10000000)
 

Field : Set DATA1 PID - setd1pid

Applies to interrupt/bulk IN and OUT endpoints only. Writing to this field sets the Endpoint Data PID (DPID) field in this register to DATA1. This field is applicable both for Scatter/Gather DMA mode and non-Scatter/Gather DMA mode.

Set Odd (micro)frame (SetOddFr) Applies to isochronous IN and OUT endpoints only. Writing to this field sets the Even/Odd (micro)frame (EO_FrNum) field to odd (micro)frame.This field is not applicable for Scatter/Gather DMA mode.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD 0x0 Disables Set DATA1 PID
ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END 0x1 Enables Set DATA1 PID

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END   0x1
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB   29
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB   29
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK   0x20000000
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK   0xdfffffff
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET(value)   (((value) & 0x20000000) >> 29)
 
#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET(value)   (((value) << 29) & 0x20000000)
 

Field : Endpoint Disable - epdis

Applies to IN and OUT endpoints. The application sets this bit to stop transmitting/receiving data on an endpoint, even before the transfer for that endpoint is complete. The application must wait for the Endpoint Disabled interrupt before treating the endpoint as disabled. The core clears this bit before setting the Endpoint Disabled interrupt. The application must set this bit only if Endpoint Enable is already set for this endpoint.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT 0x0 No Endpoint Disable
ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT 0x1 Endpoint Disable

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB   30
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB   30
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK   0x40000000
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK   0xbfffffff
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET(value)   (((value) << 30) & 0x40000000)
 

Field : Endpoint Enable - epena

Applies to IN and OUT endpoints.

  • When Scatter/Gather DMA mode is enabled,
  • for IN endpoints this bit indicates that the descriptor structure and data buffer with data ready to transmit is setup.
  • for OUT endpoint it indicates that the descriptor structure and data buffer to receive data is setup.
  • When Scatter/Gather DMA mode is enabled such as for buffer-pointer based DMA mode:
  • for IN endpoints, this bit indicates that data is ready to be transmitted on the endpoint.
  • for OUT endpoints, this bit indicates that the application has allocated the memory to start receiving data from the USB.
  • The core clears this bit before setting any of the following interrupts on this endpoint:
  • SETUP Phase Done
  • Endpoint Disabled
  • Transfer Completed

for control endpoints in DMA mode, this bit must be set to be able to transfer SETUP data packets in memory.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT 0x0 Endpoint Enable inactive
ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT 0x1 Endpoint Enable active

Field Access Macros:

#define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT   0x1
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_LSB   31
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_MSB   31
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH   1
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK   0x80000000
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK   0x7fffffff
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_RESET   0x0
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_USB_DEV_DIEPCTL5_EPENA_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_USB_DEV_DIEPCTL5_s
 

Macros

#define ALT_USB_DEV_DIEPCTL5_OFST   0x1a0
 
#define ALT_USB_DEV_DIEPCTL5_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST))
 

Typedefs

typedef struct
ALT_USB_DEV_DIEPCTL5_s 
ALT_USB_DEV_DIEPCTL5_t
 

Data Structure Documentation

struct ALT_USB_DEV_DIEPCTL5_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_USB_DEV_DIEPCTL5.

Data Fields
uint32_t mps: 11 Maximum Packet Size
uint32_t __pad0__: 4 UNDEFINED
uint32_t usbactep: 1 USB Active Endpoint
const uint32_t dpid: 1 Endpoint Data PID
const uint32_t naksts: 1 NAK Status
uint32_t eptype: 2 Endpoint Type
uint32_t __pad1__: 1 UNDEFINED
const uint32_t stall: 1 STALL Handshake
uint32_t txfnum: 4 TxFIFO Number
uint32_t cnak: 1 Clear NAK
uint32_t snak: 1 Set NAK
uint32_t setd0pid: 1 Set DATA0 PID
uint32_t setd1pid: 1 Set DATA1 PID
const uint32_t epdis: 1 Endpoint Disable
const uint32_t epena: 1 Endpoint Enable

Macro Definitions

#define ALT_USB_DEV_DIEPCTL5_MPS_LSB   0

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field.

#define ALT_USB_DEV_DIEPCTL5_MPS_MSB   10

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_MPS register field.

#define ALT_USB_DEV_DIEPCTL5_MPS_WIDTH   11

The width in bits of the ALT_USB_DEV_DIEPCTL5_MPS register field.

#define ALT_USB_DEV_DIEPCTL5_MPS_SET_MSK   0x000007ff

The mask used to set the ALT_USB_DEV_DIEPCTL5_MPS register field value.

#define ALT_USB_DEV_DIEPCTL5_MPS_CLR_MSK   0xfffff800

The mask used to clear the ALT_USB_DEV_DIEPCTL5_MPS register field value.

#define ALT_USB_DEV_DIEPCTL5_MPS_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_MPS register field.

#define ALT_USB_DEV_DIEPCTL5_MPS_GET (   value)    (((value) & 0x000007ff) >> 0)

Extracts the ALT_USB_DEV_DIEPCTL5_MPS field value from a register.

#define ALT_USB_DEV_DIEPCTL5_MPS_SET (   value)    (((value) << 0) & 0x000007ff)

Produces a ALT_USB_DEV_DIEPCTL5_MPS register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP

Not Active

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_USBACTEP

USB Active Endpoint

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_LSB   15

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_MSB   15

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET_MSK   0x00008000

The mask used to set the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_CLR_MSK   0xffff7fff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_USBACTEP register field value.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_USBACTEP register field.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_USB_DEV_DIEPCTL5_USBACTEP field value from a register.

#define ALT_USB_DEV_DIEPCTL5_USBACTEP_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_USB_DEV_DIEPCTL5_USBACTEP register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_DPID_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID

Endpoint Data PID not active

#define ALT_USB_DEV_DIEPCTL5_DPID_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_DPID

Endpoint Data PID active

#define ALT_USB_DEV_DIEPCTL5_DPID_LSB   16

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field.

#define ALT_USB_DEV_DIEPCTL5_DPID_MSB   16

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_DPID register field.

#define ALT_USB_DEV_DIEPCTL5_DPID_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_DPID register field.

#define ALT_USB_DEV_DIEPCTL5_DPID_SET_MSK   0x00010000

The mask used to set the ALT_USB_DEV_DIEPCTL5_DPID register field value.

#define ALT_USB_DEV_DIEPCTL5_DPID_CLR_MSK   0xfffeffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_DPID register field value.

#define ALT_USB_DEV_DIEPCTL5_DPID_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_DPID register field.

#define ALT_USB_DEV_DIEPCTL5_DPID_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_USB_DEV_DIEPCTL5_DPID field value from a register.

#define ALT_USB_DEV_DIEPCTL5_DPID_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_USB_DEV_DIEPCTL5_DPID register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NONNAK   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS

The core is transmitting non-NAK handshakes based on the FIFO status

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_E_NAK   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_NAKSTS

The core is transmitting NAK handshakes on this endpoint

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_LSB   17

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_MSB   17

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET_MSK   0x00020000

The mask used to set the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_CLR_MSK   0xfffdffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_NAKSTS register field value.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_NAKSTS register field.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_USB_DEV_DIEPCTL5_NAKSTS field value from a register.

#define ALT_USB_DEV_DIEPCTL5_NAKSTS_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_USB_DEV_DIEPCTL5_NAKSTS register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_CTL   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE

Control

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_ISOCHRONOUS   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE

Isochronous

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_BULK   0x2

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE

Bulk

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_E_INTERRUP   0x3

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPTYPE

Interrupt

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_LSB   18

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_MSB   19

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_WIDTH   2

The width in bits of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET_MSK   0x000c0000

The mask used to set the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_CLR_MSK   0xfff3ffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPTYPE register field value.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_EPTYPE register field.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_GET (   value)    (((value) & 0x000c0000) >> 18)

Extracts the ALT_USB_DEV_DIEPCTL5_EPTYPE field value from a register.

#define ALT_USB_DEV_DIEPCTL5_EPTYPE_SET (   value)    (((value) << 18) & 0x000c0000)

Produces a ALT_USB_DEV_DIEPCTL5_EPTYPE register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_STALL_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL

STALL All Tokens not active

#define ALT_USB_DEV_DIEPCTL5_STALL_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_STALL

STALL All Tokens active

#define ALT_USB_DEV_DIEPCTL5_STALL_LSB   21

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field.

#define ALT_USB_DEV_DIEPCTL5_STALL_MSB   21

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_STALL register field.

#define ALT_USB_DEV_DIEPCTL5_STALL_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_STALL register field.

#define ALT_USB_DEV_DIEPCTL5_STALL_SET_MSK   0x00200000

The mask used to set the ALT_USB_DEV_DIEPCTL5_STALL register field value.

#define ALT_USB_DEV_DIEPCTL5_STALL_CLR_MSK   0xffdfffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_STALL register field value.

#define ALT_USB_DEV_DIEPCTL5_STALL_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_STALL register field.

#define ALT_USB_DEV_DIEPCTL5_STALL_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_USB_DEV_DIEPCTL5_STALL field value from a register.

#define ALT_USB_DEV_DIEPCTL5_STALL_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_USB_DEV_DIEPCTL5_STALL register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_LSB   22

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_MSB   25

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_WIDTH   4

The width in bits of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET_MSK   0x03c00000

The mask used to set the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_CLR_MSK   0xfc3fffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_TXFNUM register field value.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_TXFNUM register field.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_GET (   value)    (((value) & 0x03c00000) >> 22)

Extracts the ALT_USB_DEV_DIEPCTL5_TXFNUM field value from a register.

#define ALT_USB_DEV_DIEPCTL5_TXFNUM_SET (   value)    (((value) << 22) & 0x03c00000)

Produces a ALT_USB_DEV_DIEPCTL5_TXFNUM register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_CNAK_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK

No Clear NAK

#define ALT_USB_DEV_DIEPCTL5_CNAK_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_CNAK

Clear NAK

#define ALT_USB_DEV_DIEPCTL5_CNAK_LSB   26

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field.

#define ALT_USB_DEV_DIEPCTL5_CNAK_MSB   26

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_CNAK register field.

#define ALT_USB_DEV_DIEPCTL5_CNAK_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_CNAK register field.

#define ALT_USB_DEV_DIEPCTL5_CNAK_SET_MSK   0x04000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_CNAK register field value.

#define ALT_USB_DEV_DIEPCTL5_CNAK_CLR_MSK   0xfbffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_CNAK register field value.

#define ALT_USB_DEV_DIEPCTL5_CNAK_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_CNAK register field.

#define ALT_USB_DEV_DIEPCTL5_CNAK_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_USB_DEV_DIEPCTL5_CNAK field value from a register.

#define ALT_USB_DEV_DIEPCTL5_CNAK_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_USB_DEV_DIEPCTL5_CNAK register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_SNAK_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK

No Set NAK

#define ALT_USB_DEV_DIEPCTL5_SNAK_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SNAK

Set NAK

#define ALT_USB_DEV_DIEPCTL5_SNAK_LSB   27

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field.

#define ALT_USB_DEV_DIEPCTL5_SNAK_MSB   27

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SNAK register field.

#define ALT_USB_DEV_DIEPCTL5_SNAK_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_SNAK register field.

#define ALT_USB_DEV_DIEPCTL5_SNAK_SET_MSK   0x08000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_SNAK register field value.

#define ALT_USB_DEV_DIEPCTL5_SNAK_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_SNAK register field value.

#define ALT_USB_DEV_DIEPCTL5_SNAK_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_SNAK register field.

#define ALT_USB_DEV_DIEPCTL5_SNAK_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_USB_DEV_DIEPCTL5_SNAK field value from a register.

#define ALT_USB_DEV_DIEPCTL5_SNAK_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_USB_DEV_DIEPCTL5_SNAK register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID

Disables Set DATA0 PID

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD0PID

Endpoint Data PID to DATA0)

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_LSB   28

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_MSB   28

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET_MSK   0x10000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_CLR_MSK   0xefffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD0PID register field value.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_SETD0PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_GET (   value)    (((value) & 0x10000000) >> 28)

Extracts the ALT_USB_DEV_DIEPCTL5_SETD0PID field value from a register.

#define ALT_USB_DEV_DIEPCTL5_SETD0PID_SET (   value)    (((value) << 28) & 0x10000000)

Produces a ALT_USB_DEV_DIEPCTL5_SETD0PID register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID

Disables Set DATA1 PID

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_SETD1PID

Enables Set DATA1 PID

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_LSB   29

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_MSB   29

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET_MSK   0x20000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_CLR_MSK   0xdfffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_SETD1PID register field value.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_SETD1PID register field.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_GET (   value)    (((value) & 0x20000000) >> 29)

Extracts the ALT_USB_DEV_DIEPCTL5_SETD1PID field value from a register.

#define ALT_USB_DEV_DIEPCTL5_SETD1PID_SET (   value)    (((value) << 29) & 0x20000000)

Produces a ALT_USB_DEV_DIEPCTL5_SETD1PID register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS

No Endpoint Disable

#define ALT_USB_DEV_DIEPCTL5_EPDIS_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPDIS

Endpoint Disable

#define ALT_USB_DEV_DIEPCTL5_EPDIS_LSB   30

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_MSB   30

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPDIS register field.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_EPDIS register field.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET_MSK   0x40000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_EPDIS register field value.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_CLR_MSK   0xbfffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPDIS register field value.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_EPDIS register field.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_USB_DEV_DIEPCTL5_EPDIS field value from a register.

#define ALT_USB_DEV_DIEPCTL5_EPDIS_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_USB_DEV_DIEPCTL5_EPDIS register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_EPENA_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA

Endpoint Enable inactive

#define ALT_USB_DEV_DIEPCTL5_EPENA_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DIEPCTL5_EPENA

Endpoint Enable active

#define ALT_USB_DEV_DIEPCTL5_EPENA_LSB   31

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field.

#define ALT_USB_DEV_DIEPCTL5_EPENA_MSB   31

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DIEPCTL5_EPENA register field.

#define ALT_USB_DEV_DIEPCTL5_EPENA_WIDTH   1

The width in bits of the ALT_USB_DEV_DIEPCTL5_EPENA register field.

#define ALT_USB_DEV_DIEPCTL5_EPENA_SET_MSK   0x80000000

The mask used to set the ALT_USB_DEV_DIEPCTL5_EPENA register field value.

#define ALT_USB_DEV_DIEPCTL5_EPENA_CLR_MSK   0x7fffffff

The mask used to clear the ALT_USB_DEV_DIEPCTL5_EPENA register field value.

#define ALT_USB_DEV_DIEPCTL5_EPENA_RESET   0x0

The reset value of the ALT_USB_DEV_DIEPCTL5_EPENA register field.

#define ALT_USB_DEV_DIEPCTL5_EPENA_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_USB_DEV_DIEPCTL5_EPENA field value from a register.

#define ALT_USB_DEV_DIEPCTL5_EPENA_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_USB_DEV_DIEPCTL5_EPENA register field value suitable for setting the register.

#define ALT_USB_DEV_DIEPCTL5_OFST   0x1a0

The byte offset of the ALT_USB_DEV_DIEPCTL5 register from the beginning of the component.

#define ALT_USB_DEV_DIEPCTL5_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DIEPCTL5_OFST))

The address of the ALT_USB_DEV_DIEPCTL5 register.

Typedef Documentation

The typedef declaration for register ALT_USB_DEV_DIEPCTL5.