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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 256 (Layer 3 and Layer 4 Control Register 0)
This register controls the operations of the filter 0 of Layer 3 and Layer 4. This register is reserved if the Layer 3 and Layer 4 Filtering feature is not selected during core configuration.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 |
[1] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 |
[2] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 |
[3] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 |
[4] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 |
[5] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 |
[10:6] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 |
[15:11] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 |
[16] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 |
[17] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 |
[18] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 |
[19] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 |
[20] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 |
[21] | RW | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 |
[31:22] | R | 0x0 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 |
Field : l3pen0 | |
Layer 3 Protocol Enable When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames. The Layer 3 matching is done only when either L3SAM0 or L3DAM0 bit is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB 0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB 0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET(value) (((value) << 0) & 0x00000001) |
Field : reserved_1 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_LSB 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_MSB 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET(value) (((value) << 1) & 0x00000002) |
Field : l3sam0 | |
Layer 3 IP SA Match Enable When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 4 (L3DAM0) because either IPv6 SA or DA can be checked for filtering. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB 2 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB 2 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK 0x00000004 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK 0xfffffffb |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET(value) (((value) << 2) & 0x00000004) |
Field : l3saim0 | |
Layer 3 IP SA Inverse Match Enable When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 2 (L3SAM0) is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB 3 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB 3 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET(value) (((value) << 3) & 0x00000008) |
Field : l3dam0 | |
Layer 3 IP DA Match Enable When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When Bit 0 (L3PEN0) is set, you should set either this bit or Bit 2 (L3SAM0) because either IPv6 DA or SA can be checked for filtering. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB 4 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB 4 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK 0x00000010 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK 0xffffffef |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET(value) (((value) << 4) & 0x00000010) |
Field : l3daim0 | |
Layer 3 IP DA Inverse Match Enable When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid and applicable only when Bit 4 (L3DAM0) is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB 5 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB 5 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK 0x00000020 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK 0xffffffdf |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET(value) (((value) << 5) & 0x00000020) |
Field : l3hsbm0 | |
Layer 3 IP SA Higher Bits Match IPv4 Frames: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field:
IPv6 Frames: This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames. This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB 6 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB 10 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH 5 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK 0x000007c0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK 0xfffff83f |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET(value) (((value) & 0x000007c0) >> 6) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET(value) (((value) << 6) & 0x000007c0) |
Field : l3hdbm0 | |
Layer 3 IP DA Higher Bits Match IPv4 Frames: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field:
IPv6 Frames: Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM0, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM0[1:0] and L3HSBM0 bits:
This field is valid and applicable only if L3DAM0 or L3SAM0 is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB 11 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB 15 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH 5 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK 0x0000f800 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK 0xffff07ff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET(value) (((value) & 0x0000f800) >> 11) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET(value) (((value) << 11) & 0x0000f800) |
Field : l4pen0 | |
Layer 4 Protocol Enable When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching. The Layer 4 matching is done only when either L4SPM0 or L4DPM0 bit is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB 16 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB 16 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET(value) (((value) << 16) & 0x00010000) |
Field : reserved_17 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_LSB 17 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_MSB 17 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET_MSK 0x00020000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_CLR_MSK 0xfffdffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET(value) (((value) << 17) & 0x00020000) |
Field : l4spm0 | |
Layer 4 Source Port Match Enable When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB 18 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB 18 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK 0x00040000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK 0xfffbffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET(value) (((value) << 18) & 0x00040000) |
Field : l4spim0 | |
Layer 4 Source Port Inverse Match Enable When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 18 (L4SPM0) is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB 19 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB 19 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK 0x00080000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK 0xfff7ffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET(value) (((value) << 19) & 0x00080000) |
Field : l4dpm0 | |
Layer 4 Destination Port Match Enable When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB 20 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB 20 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK 0x00100000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK 0xffefffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET(value) (((value) << 20) & 0x00100000) |
Field : l4dpim0 | |
Layer 4 Destination Port Inverse Match Enable When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching. This bit is valid and applicable only when Bit 20 (L4DPM0) is set high. Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB 21 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB 21 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH 1 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK 0x00200000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK 0xffdfffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET(value) (((value) << 21) & 0x00200000) |
Field : reserved_31_22 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_LSB 22 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_MSB 31 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_WIDTH 10 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET_MSK 0xffc00000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_CLR_MSK 0x003fffff |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_RESET 0x0 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_GET(value) (((value) & 0xffc00000) >> 22) |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET(value) (((value) << 22) & 0xffc00000) |
Data Structures | |
struct | ALT_EMAC_GMAC_L3_L4_CTL0_s |
Macros | |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_OFST 0x400 |
#define | ALT_EMAC_GMAC_L3_L4_CTL0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_L3_L4_CTL0_s | ALT_EMAC_GMAC_L3_L4_CTL0_t |
struct ALT_EMAC_GMAC_L3_L4_CTL0_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL0.
Data Fields | ||
---|---|---|
uint32_t | l3pen0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 |
const uint32_t | reserved_1: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 |
uint32_t | l3sam0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 |
uint32_t | l3saim0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 |
uint32_t | l3dam0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 |
uint32_t | l3daim0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 |
uint32_t | l3hsbm0: 5 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 |
uint32_t | l3hdbm0: 5 | ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 |
uint32_t | l4pen0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 |
const uint32_t | reserved_17: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 |
uint32_t | l4spm0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 |
uint32_t | l4spim0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 |
uint32_t | l4dpm0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 |
uint32_t | l4dpim0: 1 | ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 |
const uint32_t | reserved_31_22: 10 | ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 |
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3PEN0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_1 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3SAIM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3DAIM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_WIDTH 5 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET_MSK 0x000007c0 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_CLR_MSK 0xfffff83f |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_GET | ( | value | ) | (((value) & 0x000007c0) >> 6) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0_SET | ( | value | ) | (((value) << 6) & 0x000007c0) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HSBM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_WIDTH 5 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET_MSK 0x0000f800 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_CLR_MSK 0xffff07ff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_GET | ( | value | ) | (((value) & 0x0000f800) >> 11) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0_SET | ( | value | ) | (((value) << 11) & 0x0000f800) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L3HDBM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4PEN0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET_MSK 0x00020000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_17 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4SPIM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET_MSK 0x00100000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_CLR_MSK 0xffefffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET_MSK 0x00200000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_L4DPIM0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_WIDTH 10 |
The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET_MSK 0xffc00000 |
The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_CLR_MSK 0x003fffff |
The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_GET | ( | value | ) | (((value) & 0xffc00000) >> 22) |
Extracts the ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 field value from a register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22_SET | ( | value | ) | (((value) << 22) & 0xffc00000) |
Produces a ALT_EMAC_GMAC_L3_L4_CTL0_RSVD_31_22 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_L3_L4_CTL0 register.
#define ALT_EMAC_GMAC_L3_L4_CTL0_OFST 0x400 |
The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL0 register from the beginning of the component.
#define ALT_EMAC_GMAC_L3_L4_CTL0_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL0_OFST)) |
The address of the ALT_EMAC_GMAC_L3_L4_CTL0 register.
typedef struct ALT_EMAC_GMAC_L3_L4_CTL0_s ALT_EMAC_GMAC_L3_L4_CTL0_t |
The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL0.