Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : acc_clks

Description

Timing parameter from read enable going low to capture read data

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_NAND_CFG_ACC_CLKS_VALUE
[31:4] ??? 0x0 UNDEFINED

Field : value

Signifies the number of bus interface nand_mp_clk clock cycles, controller should wait from read enable going low to sending out a strobe of nand_mp_clk for capturing of incoming data.

Field Access Macros:

#define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB   0
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB   3
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH   4
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK   0x0000000f
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK   0xfffffff0
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET   0x0
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value)   (((value) << 0) & 0x0000000f)
 

Data Structures

struct  ALT_NAND_CFG_ACC_CLKS_s
 

Macros

#define ALT_NAND_CFG_ACC_CLKS_OFST   0x130
 

Typedefs

typedef struct
ALT_NAND_CFG_ACC_CLKS_s 
ALT_NAND_CFG_ACC_CLKS_t
 

Data Structure Documentation

struct ALT_NAND_CFG_ACC_CLKS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_ACC_CLKS.

Data Fields
uint32_t value: 4 ALT_NAND_CFG_ACC_CLKS_VALUE
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB   3

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_ACC_CLKS_VALUE register field.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH   4

The width in bits of the ALT_NAND_CFG_ACC_CLKS_VALUE register field.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK   0x0000000f

The mask used to set the ALT_NAND_CFG_ACC_CLKS_VALUE register field value.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK   0xfffffff0

The mask used to clear the ALT_NAND_CFG_ACC_CLKS_VALUE register field value.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET   0x0

The reset value of the ALT_NAND_CFG_ACC_CLKS_VALUE register field.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_NAND_CFG_ACC_CLKS_VALUE field value from a register.

#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_NAND_CFG_ACC_CLKS_VALUE register field value suitable for setting the register.

#define ALT_NAND_CFG_ACC_CLKS_OFST   0x130

The byte offset of the ALT_NAND_CFG_ACC_CLKS register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_CFG_ACC_CLKS.