Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : flash_burst_length

Description

Register Layout

Bits Access Reset Description
[1:0] RW 0x1 ALT_NAND_DMA_FLSH_BURST_LEN_VALUE
[3:2] ??? Unknown UNDEFINED
[4] RW 0x0 ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST
[7:5] ??? Unknown UNDEFINED
[31:8] RW 0x0 ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE

Field : value

Sets the burst used by data dma for transferring data to/from flash device.

This burst length is different and is larger than the burst length on the

host bus so that larger amount of data can be transferred to/from device,

descreasing controller data transfer overhead in the process.

00 - 64 bytes, 01 - 128 bytes, 10 - 256 bytes, 11 - 512 bytes.

The host burst size multiplied by the number of outstanding requests on the

host side should be greater than equal to this value. If not, the device side

burst length will be equal to host side burst length.

Field Access Macros:

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB   0
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB   1
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH   2
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK   0x00000003
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK   0xfffffffc
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET   0x1
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value)   (((value) << 0) & 0x00000003)
 

Field : continous_burst

When this bit is set, the Data DMA will burst the entire page from/to the

flash device. Please make sure that the host system can provide/sink data

at a fast pace to avoid unnecessary pausing of data on the device interface.

Field Access Macros:

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB   4
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB   4
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH   1
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK   0x00000010
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK   0xffffffef
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET   0x0
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value)   (((value) << 4) & 0x00000010)
 

Field : polling_sync_counter_value

Number of cycles CMDDMA channel has to wait before polling the SYNC Pointer again.

If this counter value is 0, no polling is done.

Field Access Macros:

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_LSB   8
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_MSB   31
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_WIDTH   24
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET_MSK   0xffffff00
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_CLR_MSK   0x000000ff
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_RESET   0x0
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_GET(value)   (((value) & 0xffffff00) >> 8)
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET(value)   (((value) << 8) & 0xffffff00)
 

Data Structures

struct  ALT_NAND_DMA_FLSH_BURST_LEN_s
 

Macros

#define ALT_NAND_DMA_FLSH_BURST_LEN_RESET   0x00000001
 
#define ALT_NAND_DMA_FLSH_BURST_LEN_OFST   0x70
 

Typedefs

typedef struct
ALT_NAND_DMA_FLSH_BURST_LEN_s 
ALT_NAND_DMA_FLSH_BURST_LEN_t
 

Data Structure Documentation

struct ALT_NAND_DMA_FLSH_BURST_LEN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_DMA_FLSH_BURST_LEN.

Data Fields
uint32_t value: 2 ALT_NAND_DMA_FLSH_BURST_LEN_VALUE
uint32_t __pad0__: 2 UNDEFINED
uint32_t continous_burst: 1 ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST
uint32_t __pad1__: 3 UNDEFINED
uint32_t polling_sync_counter_value: 24 ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE

Macro Definitions

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB   1

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH   2

The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK   0x00000003

The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK   0xfffffffc

The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET   0x1

The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_VALUE field value from a register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_NAND_DMA_FLSH_BURST_LEN_VALUE register field value suitable for setting the register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB   4

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB   4

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH   1

The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK   0x00000010

The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK   0xffffffef

The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET   0x0

The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST field value from a register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST register field value suitable for setting the register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_LSB   8

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_MSB   31

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_WIDTH   24

The width in bits of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET_MSK   0xffffff00

The mask used to set the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_CLR_MSK   0x000000ff

The mask used to clear the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_RESET   0x0

The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_GET (   value)    (((value) & 0xffffff00) >> 8)

Extracts the ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE field value from a register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET (   value)    (((value) << 8) & 0xffffff00)

Produces a ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE register field value suitable for setting the register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_RESET   0x00000001

The reset value of the ALT_NAND_DMA_FLSH_BURST_LEN register.

#define ALT_NAND_DMA_FLSH_BURST_LEN_OFST   0x70

The byte offset of the ALT_NAND_DMA_FLSH_BURST_LEN register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_DMA_FLSH_BURST_LEN.