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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Reports settings of various GPIO configuration parameters
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | R | 0x2 | APB DATA WIDTH |
[3:2] | R | 0x0 | NUM PORTS |
[4] | R | 0x1 | PORT A SINGLE CTL |
[5] | R | 0x1 | PORT B SINGLE CTL |
[6] | R | 0x1 | PORT C SINGLE CTL |
[7] | R | 0x1 | PORT D SINGLE CTL |
[8] | R | 0x0 | HW PORTA |
[11:9] | ??? | 0x0 | UNDEFINED |
[12] | R | 0x1 | Port A Interrupt Field |
[13] | R | 0x1 | Debounce Field |
[14] | R | 0x1 | Encoded GPIO Parameters Available |
[15] | R | 0x1 | ID Field |
[20:16] | R | 0x1f | Encoded ID Width Field |
[31:21] | ??? | 0x0 | UNDEFINED |
Field : APB DATA WIDTH - apb_data_width | |||||||
Fixed to support an ABP data bus width of 32-bits. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0) | ||||||
#define | ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003) | ||||||
Field : NUM PORTS - num_ports | |||||||
The value of this register is fixed at one port (Port A). Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_GET(value) (((value) & 0x0000000c) >> 2) | ||||||
#define | ALT_GPIO_CFG_REG1_NUM_PORTS_SET(value) (((value) << 2) & 0x0000000c) | ||||||
Field : PORT A SINGLE CTL - porta_single_ctl | |||||||
Indicates the mode of operation of Port A to be software controlled only. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET(value) (((value) & 0x00000010) >> 4) | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET(value) (((value) << 4) & 0x00000010) | ||||||
Field : PORT B SINGLE CTL - portb_single_ctl | |||||||
Indicates the mode of operation of Port B to be software controlled only. Ignored because there is no Port B in the GPIO. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET(value) (((value) & 0x00000020) >> 5) | ||||||
#define | ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET(value) (((value) << 5) & 0x00000020) | ||||||
Field : PORT C SINGLE CTL - portc_single_ctl | |||||||
Indicates the mode of operation of Port C to be software controlled only. Ignored because there is no Port C in the GPIO. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET(value) (((value) & 0x00000040) >> 6) | ||||||
#define | ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET(value) (((value) << 6) & 0x00000040) | ||||||
Field : PORT D SINGLE CTL - portd_single_ctl | |||||||
Indicates the mode of operation of Port D to be software controlled only. Ignored because there is no Port D in the GPIO. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET(value) (((value) & 0x00000080) >> 7) | ||||||
#define | ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET(value) (((value) << 7) & 0x00000080) | ||||||
Field : HW PORTA - hw_porta | |||||||
The value is fixed to enable Port A configuration to be controlled by software only. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_GET(value) (((value) & 0x00000100) >> 8) | ||||||
#define | ALT_GPIO_CFG_REG1_HW_PORTA_SET(value) (((value) << 8) & 0x00000100) | ||||||
Field : Port A Interrupt Field - porta_intr | |||||||
The value of this field is fixed to allow interrupts on Port A. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_GET(value) (((value) & 0x00001000) >> 12) | ||||||
#define | ALT_GPIO_CFG_REG1_PORTA_INTR_SET(value) (((value) << 12) & 0x00001000) | ||||||
Field : Debounce Field - debounce | |||||||
The value of this field is fixed to allow debouncing of the Port A signals. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_GET(value) (((value) & 0x00002000) >> 13) | ||||||
#define | ALT_GPIO_CFG_REG1_DEBOUNCE_SET(value) (((value) << 13) & 0x00002000) | ||||||
Field : Encoded GPIO Parameters Available - add_encoded_params | |||||||
Fixed to allow the indentification of the Designware IP component. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00004000) >> 14) | ||||||
#define | ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET(value) (((value) << 14) & 0x00004000) | ||||||
Field : ID Field - gpio_id | |||||||
Provides an ID code value Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_GET(value) (((value) & 0x00008000) >> 15) | ||||||
#define | ALT_GPIO_CFG_REG1_GPIO_ID_SET(value) (((value) << 15) & 0x00008000) | ||||||
Field : Encoded ID Width Field - encoded_id_width | |||||||
This value is fixed at 32 bits. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET(value) (((value) & 0x001f0000) >> 16) | ||||||
#define | ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET(value) (((value) << 16) & 0x001f0000) | ||||||
Data Structures | |
struct | ALT_GPIO_CFG_REG1_s |
Macros | |
#define | ALT_GPIO_CFG_REG1_OFST 0x74 |
#define | ALT_GPIO_CFG_REG1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) |
Typedefs | |
typedef struct ALT_GPIO_CFG_REG1_s | ALT_GPIO_CFG_REG1_t |
struct ALT_GPIO_CFG_REG1_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_GPIO_CFG_REG1.
Data Fields | ||
---|---|---|
const uint32_t | apb_data_width: 2 | APB DATA WIDTH |
const uint32_t | num_ports: 2 | NUM PORTS |
const uint32_t | porta_single_ctl: 1 | PORT A SINGLE CTL |
const uint32_t | portb_single_ctl: 1 | PORT B SINGLE CTL |
const uint32_t | portc_single_ctl: 1 | PORT C SINGLE CTL |
const uint32_t | portd_single_ctl: 1 | PORT D SINGLE CTL |
const uint32_t | hw_porta: 1 | HW PORTA |
uint32_t | __pad0__: 3 | UNDEFINED |
const uint32_t | porta_intr: 1 | Port A Interrupt Field |
const uint32_t | debounce: 1 | Debounce Field |
const uint32_t | add_encoded_params: 1 | Encoded GPIO Parameters Available |
const uint32_t | gpio_id: 1 | ID Field |
const uint32_t | encoded_id_width: 5 | Encoded ID Width Field |
uint32_t | __pad1__: 11 | UNDEFINED |
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 |
Enumerated value for register field ALT_GPIO_CFG_REG1_APB_DATA_WIDTH
APB Data Width = 32-bits
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_WIDTH 2 |
The width in bits of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET_MSK 0x00000003 |
The mask used to set the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_RESET 0x2 |
The reset value of the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_GPIO_CFG_REG1_APB_DATA_WIDTH field value from a register.
#define ALT_GPIO_CFG_REG1_APB_DATA_WIDTH_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_GPIO_CFG_REG1_APB_DATA_WIDTH register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_E_ONEPORTA 0x0 |
Enumerated value for register field ALT_GPIO_CFG_REG1_NUM_PORTS
Number of GPIO Ports = 1
#define ALT_GPIO_CFG_REG1_NUM_PORTS_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_NUM_PORTS register field.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_WIDTH 2 |
The width in bits of the ALT_GPIO_CFG_REG1_NUM_PORTS register field.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET_MSK 0x0000000c |
The mask used to set the ALT_GPIO_CFG_REG1_NUM_PORTS register field value.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_GPIO_CFG_REG1_NUM_PORTS register field value.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_RESET 0x0 |
The reset value of the ALT_GPIO_CFG_REG1_NUM_PORTS register field.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_GPIO_CFG_REG1_NUM_PORTS field value from a register.
#define ALT_GPIO_CFG_REG1_NUM_PORTS_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_GPIO_CFG_REG1_NUM_PORTS register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_E_SOFTCTLONLY 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL
Software Enabled Individual Port Control
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET_MSK 0x00000010 |
The mask used to set the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_CLR_MSK 0xffffffef |
The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL field value from a register.
#define ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_GPIO_CFG_REG1_PORTA_SINGLE_CTL register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_E_SOFTCTLONLY 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL
Software Enabled Individual Port Control
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET_MSK 0x00000020 |
The mask used to set the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL field value from a register.
#define ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_GPIO_CFG_REG1_PORTB_SINGLE_CTL register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_E_SOFTCTLONLY 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL
Software Enabled Individual Port Control
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET_MSK 0x00000040 |
The mask used to set the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL field value from a register.
#define ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_GPIO_CFG_REG1_PORTC_SINGLE_CTL register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_E_SOFTCTLONLY 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL
Software Enabled Individual Port Control
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET_MSK 0x00000080 |
The mask used to set the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL field value from a register.
#define ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_GPIO_CFG_REG1_PORTD_SINGLE_CTL register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_HW_PORTA_E_PORTANOHARD 0x0 |
Enumerated value for register field ALT_GPIO_CFG_REG1_HW_PORTA
Software Configuration Control Enabled
#define ALT_GPIO_CFG_REG1_HW_PORTA_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field.
#define ALT_GPIO_CFG_REG1_HW_PORTA_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_HW_PORTA register field.
#define ALT_GPIO_CFG_REG1_HW_PORTA_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_HW_PORTA register field.
#define ALT_GPIO_CFG_REG1_HW_PORTA_SET_MSK 0x00000100 |
The mask used to set the ALT_GPIO_CFG_REG1_HW_PORTA register field value.
#define ALT_GPIO_CFG_REG1_HW_PORTA_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_GPIO_CFG_REG1_HW_PORTA register field value.
#define ALT_GPIO_CFG_REG1_HW_PORTA_RESET 0x0 |
The reset value of the ALT_GPIO_CFG_REG1_HW_PORTA register field.
#define ALT_GPIO_CFG_REG1_HW_PORTA_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_GPIO_CFG_REG1_HW_PORTA field value from a register.
#define ALT_GPIO_CFG_REG1_HW_PORTA_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_GPIO_CFG_REG1_HW_PORTA register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_E_PORTAINTERR 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_PORTA_INTR
Port A Interrupts Enabled
#define ALT_GPIO_CFG_REG1_PORTA_INTR_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_PORTA_INTR register field.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_PORTA_INTR register field.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET_MSK 0x00001000 |
The mask used to set the ALT_GPIO_CFG_REG1_PORTA_INTR register field value.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_CLR_MSK 0xffffefff |
The mask used to clear the ALT_GPIO_CFG_REG1_PORTA_INTR register field value.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_PORTA_INTR register field.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_GPIO_CFG_REG1_PORTA_INTR field value from a register.
#define ALT_GPIO_CFG_REG1_PORTA_INTR_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_GPIO_CFG_REG1_PORTA_INTR register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_E_DEBOUNCEA 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_DEBOUNCE
Debounce is Enabled
#define ALT_GPIO_CFG_REG1_DEBOUNCE_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_DEBOUNCE register field.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_DEBOUNCE register field.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET_MSK 0x00002000 |
The mask used to set the ALT_GPIO_CFG_REG1_DEBOUNCE register field value.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_GPIO_CFG_REG1_DEBOUNCE register field value.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_DEBOUNCE register field.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_GPIO_CFG_REG1_DEBOUNCE field value from a register.
#define ALT_GPIO_CFG_REG1_DEBOUNCE_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_GPIO_CFG_REG1_DEBOUNCE register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS
Enable IP indentification
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET_MSK 0x00004000 |
The mask used to set the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS field value from a register.
#define ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_GPIO_CFG_REG1_ADD_ENC_PARAMS register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_GPIO_ID_E_IDCODE 0x1 |
Enumerated value for register field ALT_GPIO_CFG_REG1_GPIO_ID
GPIO ID Code
#define ALT_GPIO_CFG_REG1_GPIO_ID_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field.
#define ALT_GPIO_CFG_REG1_GPIO_ID_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_GPIO_ID register field.
#define ALT_GPIO_CFG_REG1_GPIO_ID_WIDTH 1 |
The width in bits of the ALT_GPIO_CFG_REG1_GPIO_ID register field.
#define ALT_GPIO_CFG_REG1_GPIO_ID_SET_MSK 0x00008000 |
The mask used to set the ALT_GPIO_CFG_REG1_GPIO_ID register field value.
#define ALT_GPIO_CFG_REG1_GPIO_ID_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_GPIO_CFG_REG1_GPIO_ID register field value.
#define ALT_GPIO_CFG_REG1_GPIO_ID_RESET 0x1 |
The reset value of the ALT_GPIO_CFG_REG1_GPIO_ID register field.
#define ALT_GPIO_CFG_REG1_GPIO_ID_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_GPIO_CFG_REG1_GPIO_ID field value from a register.
#define ALT_GPIO_CFG_REG1_GPIO_ID_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_GPIO_CFG_REG1_GPIO_ID register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_E_ENCIDWIDTH 0x1f |
Enumerated value for register field ALT_GPIO_CFG_REG1_ENC_ID_WIDTH
Width of ID Field
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_WIDTH 5 |
The width in bits of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET_MSK 0x001f0000 |
The mask used to set the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_CLR_MSK 0xffe0ffff |
The mask used to clear the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_RESET 0x1f |
The reset value of the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_GET | ( | value | ) | (((value) & 0x001f0000) >> 16) |
Extracts the ALT_GPIO_CFG_REG1_ENC_ID_WIDTH field value from a register.
#define ALT_GPIO_CFG_REG1_ENC_ID_WIDTH_SET | ( | value | ) | (((value) << 16) & 0x001f0000) |
Produces a ALT_GPIO_CFG_REG1_ENC_ID_WIDTH register field value suitable for setting the register.
#define ALT_GPIO_CFG_REG1_OFST 0x74 |
The byte offset of the ALT_GPIO_CFG_REG1 register from the beginning of the component.
#define ALT_GPIO_CFG_REG1_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG1_OFST)) |
The address of the ALT_GPIO_CFG_REG1 register.
typedef struct ALT_GPIO_CFG_REG1_s ALT_GPIO_CFG_REG1_t |
The typedef declaration for register ALT_GPIO_CFG_REG1.