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alt_noc_mpu_ddr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_MPU_DDR_H__
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#define __ALT_SOCAL_NOC_MPU_DDR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_MSB 7
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_WIDTH 8
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET_MSK 0x000000ff
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_CLR_MSK 0xffffff00
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_RESET 0x6
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_LSB 8
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_MSB 31
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_WIDTH 24
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET_MSK 0xffffff00
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_CLR_MSK 0x000000ff
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_RESET 0xfa9ecc
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_COREID_s
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{
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const
uint32_t
CORETYPEID
: 8;
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const
uint32_t
CORECHECKSUM
: 24;
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};
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typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_COREID_s
ALT_NOC_MPU_DDR_T_PRB_COREID_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_RESET 0xfa9ecc06
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#define ALT_NOC_MPU_DDR_T_PRB_COREID_OFST 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_MSB 7
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_WIDTH 8
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET_MSK 0x000000ff
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_CLR_MSK 0xffffff00
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_LSB 8
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_MSB 31
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_WIDTH 24
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET_MSK 0xffffff00
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_CLR_MSK 0x000000ff
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_RESET 0x129ff
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_REVID_s
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{
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const
uint32_t
USERID
: 8;
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const
uint32_t
FLEXNOCID
: 24;
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};
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typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_REVID_s
ALT_NOC_MPU_DDR_T_PRB_REVID_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_RESET 0x0129ff00
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#define ALT_NOC_MPU_DDR_T_PRB_REVID_OFST 0x4
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_MSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET_MSK 0x00000001
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_CLR_MSK 0xfffffffe
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ERREN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_LSB 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_MSB 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET_MSK 0x00000002
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_CLR_MSK 0xfffffffd
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_TRACEEN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_LSB 2
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_MSB 2
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET_MSK 0x00000004
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_CLR_MSK 0xfffffffb
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_PAYLDEN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_LSB 3
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_MSB 3
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET_MSK 0x00000008
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_CLR_MSK 0xfffffff7
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATEN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_LSB 4
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_MSB 4
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET_MSK 0x00000010
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_CLR_MSK 0xffffffef
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_ALARMEN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_LSB 5
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_MSB 5
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET_MSK 0x00000020
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_CLR_MSK 0xffffffdf
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_STATCONDDUMP_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_LSB 6
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_MSB 6
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET_MSK 0x00000040
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_CLR_MSK 0xffffffbf
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_INTRUSIVEMOD_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_LSB 7
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_MSB 7
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET_MSK 0x00000080
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_CLR_MSK 0xffffff7f
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_FILTBYTEALWAYSCHAINABLEEN_SET(value) (((value) << 7) & 0x00000080)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s
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{
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uint32_t
ERREN
: 1;
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uint32_t
TRACEEN
: 1;
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uint32_t
PAYLOADEN
: 1;
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uint32_t
STATEN
: 1;
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uint32_t
ALARMEN
: 1;
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uint32_t
STATCONDDUMP
: 1;
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uint32_t
INTRUSIVEMODE
: 1;
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uint32_t
FILTBYTEALWAYSCHAINABLEEN
: 1;
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uint32_t : 24;
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};
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typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_MAINCTL_s
ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_RESET 0x00000000
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#define ALT_NOC_MPU_DDR_T_PRB_MAINCTL_OFST 0x8
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_MSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET_MSK 0x00000001
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_CLR_MSK 0xfffffffe
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_LSB 1
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_MSB 1
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_WIDTH 1
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET_MSK 0x00000002
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_CLR_MSK 0xfffffffd
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET(value) (((value) << 1) & 0x00000002)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s
572
{
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uint32_t
GLOBALEN
: 1;
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const
uint32_t
ACTIVE
: 1;
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uint32_t : 30;
576
};
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typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_RESET 0x00000000
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#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_OFST 0xc
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_MSB 15
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_WIDTH 16
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET_MSK 0x0000ffff
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_CLR_MSK 0xffff0000
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_FLTLUT_SET(value) (((value) << 0) & 0x0000ffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s
640
{
641
uint32_t
FILTERLUT
: 16;
642
uint32_t : 16;
643
};
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typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTLUT_s
ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t
;
647
#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_RESET 0x00000000
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#define ALT_NOC_MPU_DDR_T_PRB_FLTLUT_OFST 0x14
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_MSB 4
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_WIDTH 5
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET_MSK 0x0000001f
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_CLR_MSK 0xffffffe0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_GET(value) (((value) & 0x0000001f) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_TRACEALARMEN_SET(value) (((value) << 0) & 0x0000001f)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s
708
{
709
uint32_t
TRACEALARMEN
: 5;
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uint32_t : 27;
711
};
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714
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_s
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t
;
715
#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_RESET 0x00000000
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_OFST 0x18
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_LSB 0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_MSB 4
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_WIDTH 5
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET_MSK 0x0000001f
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_CLR_MSK 0xffffffe0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_RESET 0x0
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_GET(value) (((value) & 0x0000001f) >> 0)
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#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_TRACEALARMSTAT_SET(value) (((value) << 0) & 0x0000001f)
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#ifndef __ASSEMBLY__
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774
struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s
775
{
776
const
uint32_t
TRACEALARMSTATUS
: 5;
777
uint32_t : 27;
778
};
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781
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_s
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t
;
782
#endif
/* __ASSEMBLY__ */
783
785
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_RESET 0x00000000
786
787
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_OFST 0x1c
788
813
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_LSB 0
814
815
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_MSB 4
816
817
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5
818
819
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f
820
821
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0
822
823
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0
824
825
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0)
826
827
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f)
828
829
#ifndef __ASSEMBLY__
830
840
struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s
841
{
842
uint32_t
TRACEALARMCLR
: 5;
843
uint32_t : 27;
844
};
845
847
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t
;
848
#endif
/* __ASSEMBLY__ */
849
851
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_RESET 0x00000000
852
853
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_OFST 0x20
854
883
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_LSB 0
884
885
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_MSB 4
886
887
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_WIDTH 5
888
889
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET_MSK 0x0000001f
890
891
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_CLR_MSK 0xffffffe0
892
893
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_RESET 0x0
894
895
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_GET(value) (((value) & 0x0000001f) >> 0)
896
897
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_STATPERIOD_SET(value) (((value) << 0) & 0x0000001f)
898
899
#ifndef __ASSEMBLY__
900
910
struct
ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s
911
{
912
uint32_t
STATPERIOD
: 5;
913
uint32_t : 27;
914
};
915
917
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_s
ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t
;
918
#endif
/* __ASSEMBLY__ */
919
921
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_RESET 0x00000000
922
923
#define ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_OFST 0x24
924
949
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_LSB 0
950
951
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_MSB 0
952
953
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_WIDTH 1
954
955
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET_MSK 0x00000001
956
957
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_CLR_MSK 0xfffffffe
958
959
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_RESET 0x0
960
961
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_GET(value) (((value) & 0x00000001) >> 0)
962
963
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_STATGO_SET(value) (((value) << 0) & 0x00000001)
964
965
#ifndef __ASSEMBLY__
966
976
struct
ALT_NOC_MPU_DDR_T_PRB_STATGO_s
977
{
978
uint32_t
STATGO
: 1;
979
uint32_t : 31;
980
};
981
983
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATGO_s
ALT_NOC_MPU_DDR_T_PRB_STATGO_t
;
984
#endif
/* __ASSEMBLY__ */
985
987
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_RESET 0x00000000
988
989
#define ALT_NOC_MPU_DDR_T_PRB_STATGO_OFST 0x28
990
1014
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_LSB 0
1015
1016
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_MSB 31
1017
1018
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_WIDTH 32
1019
1020
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET_MSK 0xffffffff
1021
1022
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_CLR_MSK 0x00000000
1023
1024
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_RESET 0x0
1025
1026
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_GET(value) (((value) & 0xffffffff) >> 0)
1027
1028
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_STATALARMMIN_SET(value) (((value) << 0) & 0xffffffff)
1029
1030
#ifndef __ASSEMBLY__
1031
1041
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s
1042
{
1043
uint32_t
STATALARMMIN
: 32;
1044
};
1045
1047
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_s
ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t
;
1048
#endif
/* __ASSEMBLY__ */
1049
1051
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_RESET 0x00000000
1052
1053
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_OFST 0x2c
1054
1078
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_LSB 0
1079
1080
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_MSB 31
1081
1082
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_WIDTH 32
1083
1084
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET_MSK 0xffffffff
1085
1086
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_CLR_MSK 0x00000000
1087
1088
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_RESET 0x0
1089
1090
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_GET(value) (((value) & 0xffffffff) >> 0)
1091
1092
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_STATALARMMAX_SET(value) (((value) << 0) & 0xffffffff)
1093
1094
#ifndef __ASSEMBLY__
1095
1105
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s
1106
{
1107
uint32_t
STATALARMMAX
: 32;
1108
};
1109
1111
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_s
ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t
;
1112
#endif
/* __ASSEMBLY__ */
1113
1115
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_RESET 0x00000000
1116
1117
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_OFST 0x30
1118
1144
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_LSB 0
1145
1146
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_MSB 0
1147
1148
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_WIDTH 1
1149
1150
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET_MSK 0x00000001
1151
1152
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_CLR_MSK 0xfffffffe
1153
1154
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_RESET 0x0
1155
1156
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_GET(value) (((value) & 0x00000001) >> 0)
1157
1158
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_STATALARMSTAT_SET(value) (((value) << 0) & 0x00000001)
1159
1160
#ifndef __ASSEMBLY__
1161
1171
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s
1172
{
1173
const
uint32_t
STATALARMSTATUS
: 1;
1174
uint32_t : 31;
1175
};
1176
1178
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_s
ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t
;
1179
#endif
/* __ASSEMBLY__ */
1180
1182
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_RESET 0x00000000
1183
1184
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_OFST 0x34
1185
1210
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_LSB 0
1211
1212
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_MSB 0
1213
1214
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_WIDTH 1
1215
1216
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET_MSK 0x00000001
1217
1218
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_CLR_MSK 0xfffffffe
1219
1220
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_RESET 0x0
1221
1222
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_GET(value) (((value) & 0x00000001) >> 0)
1223
1224
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_STATALARMCLR_SET(value) (((value) << 0) & 0x00000001)
1225
1226
#ifndef __ASSEMBLY__
1227
1237
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s
1238
{
1239
uint32_t
STATALARMCLR
: 1;
1240
uint32_t : 31;
1241
};
1242
1244
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_s
ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t
;
1245
#endif
/* __ASSEMBLY__ */
1246
1248
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_RESET 0x00000000
1249
1250
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_OFST 0x38
1251
1274
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_LSB 0
1275
1276
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_MSB 0
1277
1278
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_WIDTH 1
1279
1280
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET_MSK 0x00000001
1281
1282
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_CLR_MSK 0xfffffffe
1283
1284
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_RESET 0x1
1285
1286
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_GET(value) (((value) & 0x00000001) >> 0)
1287
1288
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_STATALARMEN_SET(value) (((value) << 0) & 0x00000001)
1289
1290
#ifndef __ASSEMBLY__
1291
1301
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s
1302
{
1303
uint32_t
STATALARMEN
: 1;
1304
uint32_t : 31;
1305
};
1306
1308
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_s
ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t
;
1309
#endif
/* __ASSEMBLY__ */
1310
1312
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_RESET 0x00000001
1313
1314
#define ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_OFST 0x3c
1315
1338
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_LSB 0
1339
1340
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_MSB 18
1341
1342
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_WIDTH 19
1343
1344
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET_MSK 0x0007ffff
1345
1346
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_CLR_MSK 0xfff80000
1347
1348
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_RESET 0x0
1349
1350
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
1351
1352
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_FLTS_0_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
1353
1354
#ifndef __ASSEMBLY__
1355
1365
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s
1366
{
1367
uint32_t
FILTERS_0_ROUTEIDBASE
: 19;
1368
uint32_t : 13;
1369
};
1370
1372
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t
;
1373
#endif
/* __ASSEMBLY__ */
1374
1376
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_RESET 0x00000000
1377
1378
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_OFST 0x44
1379
1403
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_LSB 0
1404
1405
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_MSB 18
1406
1407
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_WIDTH 19
1408
1409
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET_MSK 0x0007ffff
1410
1411
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_CLR_MSK 0xfff80000
1412
1413
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_RESET 0x0
1414
1415
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
1416
1417
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_FLTS_0_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
1418
1419
#ifndef __ASSEMBLY__
1420
1430
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s
1431
{
1432
uint32_t
FILTERS_0_ROUTEIDMASK
: 19;
1433
uint32_t : 13;
1434
};
1435
1437
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t
;
1438
#endif
/* __ASSEMBLY__ */
1439
1441
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_RESET 0x00000000
1442
1443
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_OFST 0x48
1444
1465
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_LSB 0
1466
1467
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_MSB 31
1468
1469
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_WIDTH 32
1470
1471
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET_MSK 0xffffffff
1472
1473
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_CLR_MSK 0x00000000
1474
1475
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_RESET 0x0
1476
1477
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
1478
1479
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_FLTS_0_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
1480
1481
#ifndef __ASSEMBLY__
1482
1492
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s
1493
{
1494
uint32_t
FILTERS_0_ADDRBASE_LOW
: 32;
1495
};
1496
1498
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t
;
1499
#endif
/* __ASSEMBLY__ */
1500
1502
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_RESET 0x00000000
1503
1504
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_OFST 0x4c
1505
1531
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_LSB 0
1532
1533
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_MSB 5
1534
1535
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_WIDTH 6
1536
1537
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET_MSK 0x0000003f
1538
1539
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_CLR_MSK 0xffffffc0
1540
1541
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_RESET 0x0
1542
1543
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
1544
1545
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_FLTS_0_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
1546
1547
#ifndef __ASSEMBLY__
1548
1558
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s
1559
{
1560
uint32_t
FILTERS_0_WINDOWSIZE
: 6;
1561
uint32_t : 26;
1562
};
1563
1565
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t
;
1566
#endif
/* __ASSEMBLY__ */
1567
1569
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_RESET 0x00000000
1570
1571
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_OFST 0x54
1572
1594
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_LSB 0
1595
1596
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_MSB 2
1597
1598
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_WIDTH 3
1599
1600
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET_MSK 0x00000007
1601
1602
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_CLR_MSK 0xfffffff8
1603
1604
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_RESET 0x0
1605
1606
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
1607
1608
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_FLTS_0_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
1609
1610
#ifndef __ASSEMBLY__
1611
1621
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s
1622
{
1623
uint32_t
FILTERS_0_SECURITYBASE
: 3;
1624
uint32_t : 29;
1625
};
1626
1628
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t
;
1629
#endif
/* __ASSEMBLY__ */
1630
1632
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_RESET 0x00000000
1633
1634
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_OFST 0x58
1635
1659
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_LSB 0
1660
1661
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_MSB 2
1662
1663
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_WIDTH 3
1664
1665
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET_MSK 0x00000007
1666
1667
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_CLR_MSK 0xfffffff8
1668
1669
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_RESET 0x0
1670
1671
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
1672
1673
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_FLTS_0_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
1674
1675
#ifndef __ASSEMBLY__
1676
1686
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s
1687
{
1688
uint32_t
FILTERS_0_SECURITYMASK
: 3;
1689
uint32_t : 29;
1690
};
1691
1693
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t
;
1694
#endif
/* __ASSEMBLY__ */
1695
1697
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_RESET 0x00000000
1698
1699
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_OFST 0x5c
1700
1727
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_LSB 0
1728
1729
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_MSB 0
1730
1731
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_WIDTH 1
1732
1733
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET_MSK 0x00000001
1734
1735
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_CLR_MSK 0xfffffffe
1736
1737
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_RESET 0x0
1738
1739
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
1740
1741
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
1742
1752
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_LSB 1
1753
1754
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_MSB 1
1755
1756
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_WIDTH 1
1757
1758
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET_MSK 0x00000002
1759
1760
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_CLR_MSK 0xfffffffd
1761
1762
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_RESET 0x0
1763
1764
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
1765
1766
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
1767
1777
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_LSB 2
1778
1779
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_MSB 2
1780
1781
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_WIDTH 1
1782
1783
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET_MSK 0x00000004
1784
1785
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
1786
1787
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_RESET 0x0
1788
1789
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
1790
1791
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
1792
1802
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_LSB 3
1803
1804
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_MSB 3
1805
1806
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_WIDTH 1
1807
1808
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET_MSK 0x00000008
1809
1810
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_CLR_MSK 0xfffffff7
1811
1812
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_RESET 0x0
1813
1814
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
1815
1816
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
1817
1818
#ifndef __ASSEMBLY__
1819
1829
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s
1830
{
1831
uint32_t
RDEN
: 1;
1832
uint32_t
WREN
: 1;
1833
uint32_t
LOCKEN
: 1;
1834
uint32_t
URGEN
: 1;
1835
uint32_t : 28;
1836
};
1837
1839
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t
;
1840
#endif
/* __ASSEMBLY__ */
1841
1843
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_RESET 0x00000000
1844
1845
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_OFST 0x60
1846
1871
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_LSB 0
1872
1873
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_MSB 0
1874
1875
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_WIDTH 1
1876
1877
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET_MSK 0x00000001
1878
1879
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_CLR_MSK 0xfffffffe
1880
1881
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_RESET 0x0
1882
1883
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
1884
1885
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
1886
1896
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_LSB 1
1897
1898
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_MSB 1
1899
1900
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_WIDTH 1
1901
1902
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET_MSK 0x00000002
1903
1904
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_CLR_MSK 0xfffffffd
1905
1906
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_RESET 0x0
1907
1908
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
1909
1910
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
1911
1912
#ifndef __ASSEMBLY__
1913
1923
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s
1924
{
1925
uint32_t
REQEN
: 1;
1926
uint32_t
RSPEN
: 1;
1927
uint32_t : 30;
1928
};
1929
1931
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t
;
1932
#endif
/* __ASSEMBLY__ */
1933
1935
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_RESET 0x00000000
1936
1937
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_OFST 0x64
1938
1961
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_LSB 0
1962
1963
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_MSB 3
1964
1965
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_WIDTH 4
1966
1967
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET_MSK 0x0000000f
1968
1969
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_CLR_MSK 0xfffffff0
1970
1971
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_RESET 0x0
1972
1973
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_GET(value) (((value) & 0x0000000f) >> 0)
1974
1975
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_FLTS_0_LEN_SET(value) (((value) << 0) & 0x0000000f)
1976
1977
#ifndef __ASSEMBLY__
1978
1988
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s
1989
{
1990
uint32_t
FILTERS_0_LENGTH
: 4;
1991
uint32_t : 28;
1992
};
1993
1995
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t
;
1996
#endif
/* __ASSEMBLY__ */
1997
1999
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_RESET 0x00000000
2000
2001
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_OFST 0x68
2002
2026
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_LSB 0
2027
2028
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_MSB 1
2029
2030
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_WIDTH 2
2031
2032
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET_MSK 0x00000003
2033
2034
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_CLR_MSK 0xfffffffc
2035
2036
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_RESET 0x0
2037
2038
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2039
2040
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_FLTS_0_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2041
2042
#ifndef __ASSEMBLY__
2043
2053
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s
2054
{
2055
uint32_t
FILTERS_0_URGENCY
: 2;
2056
uint32_t : 30;
2057
};
2058
2060
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t
;
2061
#endif
/* __ASSEMBLY__ */
2062
2064
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_RESET 0x00000000
2065
2066
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_OFST 0x6c
2067
2090
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_LSB 0
2091
2092
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_MSB 18
2093
2094
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_WIDTH 19
2095
2096
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET_MSK 0x0007ffff
2097
2098
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_CLR_MSK 0xfff80000
2099
2100
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_RESET 0x0
2101
2102
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2103
2104
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_FLTS_1_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2105
2106
#ifndef __ASSEMBLY__
2107
2117
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s
2118
{
2119
uint32_t
FILTERS_1_ROUTEIDBASE
: 19;
2120
uint32_t : 13;
2121
};
2122
2124
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t
;
2125
#endif
/* __ASSEMBLY__ */
2126
2128
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_RESET 0x00000000
2129
2130
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_OFST 0x80
2131
2155
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_LSB 0
2156
2157
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_MSB 18
2158
2159
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_WIDTH 19
2160
2161
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET_MSK 0x0007ffff
2162
2163
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_CLR_MSK 0xfff80000
2164
2165
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_RESET 0x0
2166
2167
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2168
2169
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_FLTS_1_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2170
2171
#ifndef __ASSEMBLY__
2172
2182
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s
2183
{
2184
uint32_t
FILTERS_1_ROUTEIDMASK
: 19;
2185
uint32_t : 13;
2186
};
2187
2189
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t
;
2190
#endif
/* __ASSEMBLY__ */
2191
2193
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_RESET 0x00000000
2194
2195
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_OFST 0x84
2196
2217
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_LSB 0
2218
2219
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_MSB 31
2220
2221
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_WIDTH 32
2222
2223
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET_MSK 0xffffffff
2224
2225
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_CLR_MSK 0x00000000
2226
2227
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_RESET 0x0
2228
2229
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2230
2231
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_FLTS_1_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2232
2233
#ifndef __ASSEMBLY__
2234
2244
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s
2245
{
2246
uint32_t
FILTERS_1_ADDRBASE_LOW
: 32;
2247
};
2248
2250
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t
;
2251
#endif
/* __ASSEMBLY__ */
2252
2254
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_RESET 0x00000000
2255
2256
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_OFST 0x88
2257
2283
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_LSB 0
2284
2285
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_MSB 5
2286
2287
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_WIDTH 6
2288
2289
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET_MSK 0x0000003f
2290
2291
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_CLR_MSK 0xffffffc0
2292
2293
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_RESET 0x0
2294
2295
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
2296
2297
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_FLTS_1_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
2298
2299
#ifndef __ASSEMBLY__
2300
2310
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s
2311
{
2312
uint32_t
FILTERS_1_WINDOWSIZE
: 6;
2313
uint32_t : 26;
2314
};
2315
2317
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t
;
2318
#endif
/* __ASSEMBLY__ */
2319
2321
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_RESET 0x00000000
2322
2323
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_OFST 0x90
2324
2346
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_LSB 0
2347
2348
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_MSB 2
2349
2350
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_WIDTH 3
2351
2352
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET_MSK 0x00000007
2353
2354
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_CLR_MSK 0xfffffff8
2355
2356
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_RESET 0x0
2357
2358
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
2359
2360
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_FLTS_1_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
2361
2362
#ifndef __ASSEMBLY__
2363
2373
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s
2374
{
2375
uint32_t
FILTERS_1_SECURITYBASE
: 3;
2376
uint32_t : 29;
2377
};
2378
2380
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t
;
2381
#endif
/* __ASSEMBLY__ */
2382
2384
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_RESET 0x00000000
2385
2386
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_OFST 0x94
2387
2411
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_LSB 0
2412
2413
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_MSB 2
2414
2415
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_WIDTH 3
2416
2417
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET_MSK 0x00000007
2418
2419
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_CLR_MSK 0xfffffff8
2420
2421
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_RESET 0x0
2422
2423
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
2424
2425
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_FLTS_1_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
2426
2427
#ifndef __ASSEMBLY__
2428
2438
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s
2439
{
2440
uint32_t
FILTERS_1_SECURITYMASK
: 3;
2441
uint32_t : 29;
2442
};
2443
2445
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t
;
2446
#endif
/* __ASSEMBLY__ */
2447
2449
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_RESET 0x00000000
2450
2451
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_OFST 0x98
2452
2479
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_LSB 0
2480
2481
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_MSB 0
2482
2483
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_WIDTH 1
2484
2485
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET_MSK 0x00000001
2486
2487
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_CLR_MSK 0xfffffffe
2488
2489
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_RESET 0x0
2490
2491
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
2492
2493
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
2494
2504
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_LSB 1
2505
2506
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_MSB 1
2507
2508
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_WIDTH 1
2509
2510
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET_MSK 0x00000002
2511
2512
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_CLR_MSK 0xfffffffd
2513
2514
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_RESET 0x0
2515
2516
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
2517
2518
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
2519
2529
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_LSB 2
2530
2531
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_MSB 2
2532
2533
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_WIDTH 1
2534
2535
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET_MSK 0x00000004
2536
2537
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
2538
2539
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_RESET 0x0
2540
2541
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
2542
2543
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
2544
2554
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_LSB 3
2555
2556
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_MSB 3
2557
2558
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_WIDTH 1
2559
2560
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET_MSK 0x00000008
2561
2562
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_CLR_MSK 0xfffffff7
2563
2564
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_RESET 0x0
2565
2566
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
2567
2568
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
2569
2570
#ifndef __ASSEMBLY__
2571
2581
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s
2582
{
2583
uint32_t
RDEN
: 1;
2584
uint32_t
WREN
: 1;
2585
uint32_t
LOCKEN
: 1;
2586
uint32_t
URGEN
: 1;
2587
uint32_t : 28;
2588
};
2589
2591
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t
;
2592
#endif
/* __ASSEMBLY__ */
2593
2595
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_RESET 0x00000000
2596
2597
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_OFST 0x9c
2598
2623
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_LSB 0
2624
2625
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_MSB 0
2626
2627
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_WIDTH 1
2628
2629
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET_MSK 0x00000001
2630
2631
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_CLR_MSK 0xfffffffe
2632
2633
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_RESET 0x0
2634
2635
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
2636
2637
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
2638
2648
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_LSB 1
2649
2650
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_MSB 1
2651
2652
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_WIDTH 1
2653
2654
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET_MSK 0x00000002
2655
2656
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_CLR_MSK 0xfffffffd
2657
2658
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_RESET 0x0
2659
2660
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
2661
2662
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
2663
2664
#ifndef __ASSEMBLY__
2665
2675
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s
2676
{
2677
uint32_t
REQEN
: 1;
2678
uint32_t
RSPEN
: 1;
2679
uint32_t : 30;
2680
};
2681
2683
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t
;
2684
#endif
/* __ASSEMBLY__ */
2685
2687
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_RESET 0x00000000
2688
2689
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_OFST 0xa0
2690
2713
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_LSB 0
2714
2715
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_MSB 3
2716
2717
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_WIDTH 4
2718
2719
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET_MSK 0x0000000f
2720
2721
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_CLR_MSK 0xfffffff0
2722
2723
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_RESET 0x0
2724
2725
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_GET(value) (((value) & 0x0000000f) >> 0)
2726
2727
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_FLTS_1_LEN_SET(value) (((value) << 0) & 0x0000000f)
2728
2729
#ifndef __ASSEMBLY__
2730
2740
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s
2741
{
2742
uint32_t
FILTERS_1_LENGTH
: 4;
2743
uint32_t : 28;
2744
};
2745
2747
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t
;
2748
#endif
/* __ASSEMBLY__ */
2749
2751
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_RESET 0x00000000
2752
2753
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_OFST 0xa4
2754
2778
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_LSB 0
2779
2780
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_MSB 1
2781
2782
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_WIDTH 2
2783
2784
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET_MSK 0x00000003
2785
2786
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_CLR_MSK 0xfffffffc
2787
2788
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_RESET 0x0
2789
2790
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
2791
2792
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_FLTS_1_URGENCY_SET(value) (((value) << 0) & 0x00000003)
2793
2794
#ifndef __ASSEMBLY__
2795
2805
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s
2806
{
2807
uint32_t
FILTERS_1_URGENCY
: 2;
2808
uint32_t : 30;
2809
};
2810
2812
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t
;
2813
#endif
/* __ASSEMBLY__ */
2814
2816
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_RESET 0x00000000
2817
2818
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_OFST 0xa8
2819
2842
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_LSB 0
2843
2844
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_MSB 18
2845
2846
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_WIDTH 19
2847
2848
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET_MSK 0x0007ffff
2849
2850
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_CLR_MSK 0xfff80000
2851
2852
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_RESET 0x0
2853
2854
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
2855
2856
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_FLTS_2_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
2857
2858
#ifndef __ASSEMBLY__
2859
2869
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s
2870
{
2871
uint32_t
FILTERS_2_ROUTEIDBASE
: 19;
2872
uint32_t : 13;
2873
};
2874
2876
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t
;
2877
#endif
/* __ASSEMBLY__ */
2878
2880
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_RESET 0x00000000
2881
2882
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_OFST 0xbc
2883
2907
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_LSB 0
2908
2909
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_MSB 18
2910
2911
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_WIDTH 19
2912
2913
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET_MSK 0x0007ffff
2914
2915
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_CLR_MSK 0xfff80000
2916
2917
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_RESET 0x0
2918
2919
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
2920
2921
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_FLTS_2_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
2922
2923
#ifndef __ASSEMBLY__
2924
2934
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s
2935
{
2936
uint32_t
FILTERS_2_ROUTEIDMASK
: 19;
2937
uint32_t : 13;
2938
};
2939
2941
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t
;
2942
#endif
/* __ASSEMBLY__ */
2943
2945
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_RESET 0x00000000
2946
2947
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_OFST 0xc0
2948
2969
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_LSB 0
2970
2971
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_MSB 31
2972
2973
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_WIDTH 32
2974
2975
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET_MSK 0xffffffff
2976
2977
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_CLR_MSK 0x00000000
2978
2979
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_RESET 0x0
2980
2981
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
2982
2983
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_FLTS_2_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
2984
2985
#ifndef __ASSEMBLY__
2986
2996
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s
2997
{
2998
uint32_t
FILTERS_2_ADDRBASE_LOW
: 32;
2999
};
3000
3002
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t
;
3003
#endif
/* __ASSEMBLY__ */
3004
3006
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_RESET 0x00000000
3007
3008
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_OFST 0xc4
3009
3035
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_LSB 0
3036
3037
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_MSB 5
3038
3039
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_WIDTH 6
3040
3041
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET_MSK 0x0000003f
3042
3043
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_CLR_MSK 0xffffffc0
3044
3045
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_RESET 0x0
3046
3047
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3048
3049
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_FLTS_2_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3050
3051
#ifndef __ASSEMBLY__
3052
3062
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s
3063
{
3064
uint32_t
FILTERS_2_WINDOWSIZE
: 6;
3065
uint32_t : 26;
3066
};
3067
3069
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t
;
3070
#endif
/* __ASSEMBLY__ */
3071
3073
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_RESET 0x00000000
3074
3075
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_OFST 0xcc
3076
3098
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_LSB 0
3099
3100
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_MSB 2
3101
3102
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_WIDTH 3
3103
3104
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET_MSK 0x00000007
3105
3106
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_CLR_MSK 0xfffffff8
3107
3108
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_RESET 0x0
3109
3110
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3111
3112
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_FLTS_2_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3113
3114
#ifndef __ASSEMBLY__
3115
3125
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s
3126
{
3127
uint32_t
FILTERS_2_SECURITYBASE
: 3;
3128
uint32_t : 29;
3129
};
3130
3132
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t
;
3133
#endif
/* __ASSEMBLY__ */
3134
3136
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_RESET 0x00000000
3137
3138
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_OFST 0xd0
3139
3163
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_LSB 0
3164
3165
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_MSB 2
3166
3167
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_WIDTH 3
3168
3169
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET_MSK 0x00000007
3170
3171
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_CLR_MSK 0xfffffff8
3172
3173
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_RESET 0x0
3174
3175
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3176
3177
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_FLTS_2_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3178
3179
#ifndef __ASSEMBLY__
3180
3190
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s
3191
{
3192
uint32_t
FILTERS_2_SECURITYMASK
: 3;
3193
uint32_t : 29;
3194
};
3195
3197
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t
;
3198
#endif
/* __ASSEMBLY__ */
3199
3201
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_RESET 0x00000000
3202
3203
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_OFST 0xd4
3204
3231
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_LSB 0
3232
3233
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_MSB 0
3234
3235
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_WIDTH 1
3236
3237
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET_MSK 0x00000001
3238
3239
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_CLR_MSK 0xfffffffe
3240
3241
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_RESET 0x0
3242
3243
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3244
3245
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3246
3256
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_LSB 1
3257
3258
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_MSB 1
3259
3260
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_WIDTH 1
3261
3262
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET_MSK 0x00000002
3263
3264
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_CLR_MSK 0xfffffffd
3265
3266
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_RESET 0x0
3267
3268
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
3269
3270
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
3271
3281
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_LSB 2
3282
3283
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_MSB 2
3284
3285
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_WIDTH 1
3286
3287
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET_MSK 0x00000004
3288
3289
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
3290
3291
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_RESET 0x0
3292
3293
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
3294
3295
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
3296
3306
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_LSB 3
3307
3308
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_MSB 3
3309
3310
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_WIDTH 1
3311
3312
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET_MSK 0x00000008
3313
3314
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_CLR_MSK 0xfffffff7
3315
3316
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_RESET 0x0
3317
3318
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
3319
3320
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
3321
3322
#ifndef __ASSEMBLY__
3323
3333
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s
3334
{
3335
uint32_t
RDEN
: 1;
3336
uint32_t
WREN
: 1;
3337
uint32_t
LOCKEN
: 1;
3338
uint32_t
URGEN
: 1;
3339
uint32_t : 28;
3340
};
3341
3343
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t
;
3344
#endif
/* __ASSEMBLY__ */
3345
3347
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_RESET 0x00000000
3348
3349
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_OFST 0xd8
3350
3375
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_LSB 0
3376
3377
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_MSB 0
3378
3379
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_WIDTH 1
3380
3381
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET_MSK 0x00000001
3382
3383
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_CLR_MSK 0xfffffffe
3384
3385
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_RESET 0x0
3386
3387
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
3388
3389
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
3390
3400
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_LSB 1
3401
3402
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_MSB 1
3403
3404
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_WIDTH 1
3405
3406
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET_MSK 0x00000002
3407
3408
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_CLR_MSK 0xfffffffd
3409
3410
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_RESET 0x0
3411
3412
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
3413
3414
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
3415
3416
#ifndef __ASSEMBLY__
3417
3427
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s
3428
{
3429
uint32_t
REQEN
: 1;
3430
uint32_t
RSPEN
: 1;
3431
uint32_t : 30;
3432
};
3433
3435
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t
;
3436
#endif
/* __ASSEMBLY__ */
3437
3439
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_RESET 0x00000000
3440
3441
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_OFST 0xdc
3442
3465
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_LSB 0
3466
3467
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_MSB 3
3468
3469
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_WIDTH 4
3470
3471
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET_MSK 0x0000000f
3472
3473
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_CLR_MSK 0xfffffff0
3474
3475
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_RESET 0x0
3476
3477
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_GET(value) (((value) & 0x0000000f) >> 0)
3478
3479
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_FLTS_2_LEN_SET(value) (((value) << 0) & 0x0000000f)
3480
3481
#ifndef __ASSEMBLY__
3482
3492
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s
3493
{
3494
uint32_t
FILTERS_2_LENGTH
: 4;
3495
uint32_t : 28;
3496
};
3497
3499
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t
;
3500
#endif
/* __ASSEMBLY__ */
3501
3503
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_RESET 0x00000000
3504
3505
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_OFST 0xe0
3506
3530
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_LSB 0
3531
3532
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_MSB 1
3533
3534
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_WIDTH 2
3535
3536
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET_MSK 0x00000003
3537
3538
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_CLR_MSK 0xfffffffc
3539
3540
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_RESET 0x0
3541
3542
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
3543
3544
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_FLTS_2_URGENCY_SET(value) (((value) << 0) & 0x00000003)
3545
3546
#ifndef __ASSEMBLY__
3547
3557
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s
3558
{
3559
uint32_t
FILTERS_2_URGENCY
: 2;
3560
uint32_t : 30;
3561
};
3562
3564
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t
;
3565
#endif
/* __ASSEMBLY__ */
3566
3568
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_RESET 0x00000000
3569
3570
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_OFST 0xe4
3571
3594
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_LSB 0
3595
3596
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_MSB 18
3597
3598
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_WIDTH 19
3599
3600
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET_MSK 0x0007ffff
3601
3602
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_CLR_MSK 0xfff80000
3603
3604
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_RESET 0x0
3605
3606
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_GET(value) (((value) & 0x0007ffff) >> 0)
3607
3608
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_FLTS_3_ROUTEIDBASE_SET(value) (((value) << 0) & 0x0007ffff)
3609
3610
#ifndef __ASSEMBLY__
3611
3621
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s
3622
{
3623
uint32_t
FILTERS_3_ROUTEIDBASE
: 19;
3624
uint32_t : 13;
3625
};
3626
3628
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t
;
3629
#endif
/* __ASSEMBLY__ */
3630
3632
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_RESET 0x00000000
3633
3634
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_OFST 0xf8
3635
3659
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_LSB 0
3660
3661
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_MSB 18
3662
3663
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_WIDTH 19
3664
3665
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET_MSK 0x0007ffff
3666
3667
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_CLR_MSK 0xfff80000
3668
3669
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_RESET 0x0
3670
3671
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_GET(value) (((value) & 0x0007ffff) >> 0)
3672
3673
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_FLTS_3_ROUTEIDMSK_SET(value) (((value) << 0) & 0x0007ffff)
3674
3675
#ifndef __ASSEMBLY__
3676
3686
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s
3687
{
3688
uint32_t
FILTERS_3_ROUTEIDMASK
: 19;
3689
uint32_t : 13;
3690
};
3691
3693
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t
;
3694
#endif
/* __ASSEMBLY__ */
3695
3697
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_RESET 0x00000000
3698
3699
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_OFST 0xfc
3700
3721
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_LSB 0
3722
3723
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_MSB 31
3724
3725
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_WIDTH 32
3726
3727
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET_MSK 0xffffffff
3728
3729
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_CLR_MSK 0x00000000
3730
3731
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_RESET 0x0
3732
3733
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_GET(value) (((value) & 0xffffffff) >> 0)
3734
3735
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_FLTS_3_ADDRBASE_LOW_SET(value) (((value) << 0) & 0xffffffff)
3736
3737
#ifndef __ASSEMBLY__
3738
3748
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s
3749
{
3750
uint32_t
FILTERS_3_ADDRBASE_LOW
: 32;
3751
};
3752
3754
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t
;
3755
#endif
/* __ASSEMBLY__ */
3756
3758
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_RESET 0x00000000
3759
3760
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_OFST 0x100
3761
3787
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_LSB 0
3788
3789
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_MSB 5
3790
3791
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_WIDTH 6
3792
3793
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET_MSK 0x0000003f
3794
3795
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_CLR_MSK 0xffffffc0
3796
3797
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_RESET 0x0
3798
3799
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_GET(value) (((value) & 0x0000003f) >> 0)
3800
3801
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_FLTS_3_WINDOWSIZE_SET(value) (((value) << 0) & 0x0000003f)
3802
3803
#ifndef __ASSEMBLY__
3804
3814
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s
3815
{
3816
uint32_t
FILTERS_3_WINDOWSIZE
: 6;
3817
uint32_t : 26;
3818
};
3819
3821
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t
;
3822
#endif
/* __ASSEMBLY__ */
3823
3825
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_RESET 0x00000000
3826
3827
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_OFST 0x108
3828
3850
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_LSB 0
3851
3852
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_MSB 2
3853
3854
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_WIDTH 3
3855
3856
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET_MSK 0x00000007
3857
3858
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_CLR_MSK 0xfffffff8
3859
3860
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_RESET 0x0
3861
3862
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_GET(value) (((value) & 0x00000007) >> 0)
3863
3864
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_FLTS_3_SECURITYBASE_SET(value) (((value) << 0) & 0x00000007)
3865
3866
#ifndef __ASSEMBLY__
3867
3877
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s
3878
{
3879
uint32_t
FILTERS_3_SECURITYBASE
: 3;
3880
uint32_t : 29;
3881
};
3882
3884
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t
;
3885
#endif
/* __ASSEMBLY__ */
3886
3888
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_RESET 0x00000000
3889
3890
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_OFST 0x10c
3891
3915
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_LSB 0
3916
3917
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_MSB 2
3918
3919
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_WIDTH 3
3920
3921
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET_MSK 0x00000007
3922
3923
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_CLR_MSK 0xfffffff8
3924
3925
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_RESET 0x0
3926
3927
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_GET(value) (((value) & 0x00000007) >> 0)
3928
3929
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_FLTS_3_SECURITYMSK_SET(value) (((value) << 0) & 0x00000007)
3930
3931
#ifndef __ASSEMBLY__
3932
3942
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s
3943
{
3944
uint32_t
FILTERS_3_SECURITYMASK
: 3;
3945
uint32_t : 29;
3946
};
3947
3949
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t
;
3950
#endif
/* __ASSEMBLY__ */
3951
3953
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_RESET 0x00000000
3954
3955
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_OFST 0x110
3956
3983
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_LSB 0
3984
3985
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_MSB 0
3986
3987
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_WIDTH 1
3988
3989
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET_MSK 0x00000001
3990
3991
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_CLR_MSK 0xfffffffe
3992
3993
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_RESET 0x0
3994
3995
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_GET(value) (((value) & 0x00000001) >> 0)
3996
3997
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RDEN_SET(value) (((value) << 0) & 0x00000001)
3998
4008
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_LSB 1
4009
4010
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_MSB 1
4011
4012
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_WIDTH 1
4013
4014
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET_MSK 0x00000002
4015
4016
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_CLR_MSK 0xfffffffd
4017
4018
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_RESET 0x0
4019
4020
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_GET(value) (((value) & 0x00000002) >> 1)
4021
4022
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_WREN_SET(value) (((value) << 1) & 0x00000002)
4023
4033
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_LSB 2
4034
4035
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_MSB 2
4036
4037
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_WIDTH 1
4038
4039
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET_MSK 0x00000004
4040
4041
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_CLR_MSK 0xfffffffb
4042
4043
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_RESET 0x0
4044
4045
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_GET(value) (((value) & 0x00000004) >> 2)
4046
4047
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_LOCKEN_SET(value) (((value) << 2) & 0x00000004)
4048
4058
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_LSB 3
4059
4060
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_MSB 3
4061
4062
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_WIDTH 1
4063
4064
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET_MSK 0x00000008
4065
4066
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_CLR_MSK 0xfffffff7
4067
4068
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_RESET 0x0
4069
4070
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_GET(value) (((value) & 0x00000008) >> 3)
4071
4072
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_URGEN_SET(value) (((value) << 3) & 0x00000008)
4073
4074
#ifndef __ASSEMBLY__
4075
4085
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s
4086
{
4087
uint32_t
RDEN
: 1;
4088
uint32_t
WREN
: 1;
4089
uint32_t
LOCKEN
: 1;
4090
uint32_t
URGEN
: 1;
4091
uint32_t : 28;
4092
};
4093
4095
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t
;
4096
#endif
/* __ASSEMBLY__ */
4097
4099
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_RESET 0x00000000
4100
4101
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_OFST 0x114
4102
4127
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_LSB 0
4128
4129
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_MSB 0
4130
4131
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_WIDTH 1
4132
4133
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET_MSK 0x00000001
4134
4135
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_CLR_MSK 0xfffffffe
4136
4137
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_RESET 0x0
4138
4139
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_GET(value) (((value) & 0x00000001) >> 0)
4140
4141
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_REQEN_SET(value) (((value) << 0) & 0x00000001)
4142
4152
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_LSB 1
4153
4154
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_MSB 1
4155
4156
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_WIDTH 1
4157
4158
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET_MSK 0x00000002
4159
4160
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_CLR_MSK 0xfffffffd
4161
4162
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_RESET 0x0
4163
4164
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_GET(value) (((value) & 0x00000002) >> 1)
4165
4166
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RSPEN_SET(value) (((value) << 1) & 0x00000002)
4167
4168
#ifndef __ASSEMBLY__
4169
4179
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s
4180
{
4181
uint32_t
REQEN
: 1;
4182
uint32_t
RSPEN
: 1;
4183
uint32_t : 30;
4184
};
4185
4187
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t
;
4188
#endif
/* __ASSEMBLY__ */
4189
4191
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_RESET 0x00000000
4192
4193
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_OFST 0x118
4194
4217
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_LSB 0
4218
4219
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_MSB 3
4220
4221
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_WIDTH 4
4222
4223
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET_MSK 0x0000000f
4224
4225
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_CLR_MSK 0xfffffff0
4226
4227
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_RESET 0x0
4228
4229
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_GET(value) (((value) & 0x0000000f) >> 0)
4230
4231
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_FLTS_3_LEN_SET(value) (((value) << 0) & 0x0000000f)
4232
4233
#ifndef __ASSEMBLY__
4234
4244
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s
4245
{
4246
uint32_t
FILTERS_3_LENGTH
: 4;
4247
uint32_t : 28;
4248
};
4249
4251
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t
;
4252
#endif
/* __ASSEMBLY__ */
4253
4255
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_RESET 0x00000000
4256
4257
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_OFST 0x11c
4258
4282
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_LSB 0
4283
4284
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_MSB 1
4285
4286
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_WIDTH 2
4287
4288
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET_MSK 0x00000003
4289
4290
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_CLR_MSK 0xfffffffc
4291
4292
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_RESET 0x0
4293
4294
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_GET(value) (((value) & 0x00000003) >> 0)
4295
4296
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_FLTS_3_URGENCY_SET(value) (((value) << 0) & 0x00000003)
4297
4298
#ifndef __ASSEMBLY__
4299
4309
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s
4310
{
4311
uint32_t
FILTERS_3_URGENCY
: 2;
4312
uint32_t : 30;
4313
};
4314
4316
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_s
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t
;
4317
#endif
/* __ASSEMBLY__ */
4318
4320
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_RESET 0x00000000
4321
4322
#define ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_OFST 0x120
4323
4348
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_LSB 0
4349
4350
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_MSB 4
4351
4352
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_WIDTH 5
4353
4354
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET_MSK 0x0000001f
4355
4356
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_CLR_MSK 0xffffffe0
4357
4358
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_RESET 0x0
4359
4360
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4361
4362
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4363
4364
#ifndef __ASSEMBLY__
4365
4375
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s
4376
{
4377
uint32_t
INTEVENT
: 5;
4378
uint32_t : 27;
4379
};
4380
4382
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t
;
4383
#endif
/* __ASSEMBLY__ */
4384
4386
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_RESET 0x00000000
4387
4388
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_OFST 0x138
4389
4413
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_LSB 0
4414
4415
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_MSB 1
4416
4417
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_WIDTH 2
4418
4419
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET_MSK 0x00000003
4420
4421
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_CLR_MSK 0xfffffffc
4422
4423
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_RESET 0x0
4424
4425
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4426
4427
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_CNTRS_0_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4428
4429
#ifndef __ASSEMBLY__
4430
4440
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s
4441
{
4442
uint32_t
COUNTERS_0_ALARMMODE
: 2;
4443
uint32_t : 30;
4444
};
4445
4447
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t
;
4448
#endif
/* __ASSEMBLY__ */
4449
4451
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_RESET 0x00000000
4452
4453
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_OFST 0x13c
4454
4478
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0
4479
4480
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15
4481
4482
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16
4483
4484
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff
4485
4486
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000
4487
4488
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0
4489
4490
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4491
4492
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4493
4494
#ifndef __ASSEMBLY__
4495
4505
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s
4506
{
4507
const
uint32_t
COUNTERS_0_VAL
: 16;
4508
uint32_t : 16;
4509
};
4510
4512
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t
;
4513
#endif
/* __ASSEMBLY__ */
4514
4516
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_RESET 0x00000000
4517
4518
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_OFST 0x140
4519
4544
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_LSB 0
4545
4546
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_MSB 4
4547
4548
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_WIDTH 5
4549
4550
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET_MSK 0x0000001f
4551
4552
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_CLR_MSK 0xffffffe0
4553
4554
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_RESET 0x0
4555
4556
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_GET(value) (((value) & 0x0000001f) >> 0)
4557
4558
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_INTEVENT_SET(value) (((value) << 0) & 0x0000001f)
4559
4560
#ifndef __ASSEMBLY__
4561
4571
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s
4572
{
4573
uint32_t
INTEVENT
: 5;
4574
uint32_t : 27;
4575
};
4576
4578
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t
;
4579
#endif
/* __ASSEMBLY__ */
4580
4582
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_RESET 0x00000000
4583
4584
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_OFST 0x14c
4585
4609
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_LSB 0
4610
4611
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_MSB 1
4612
4613
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_WIDTH 2
4614
4615
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET_MSK 0x00000003
4616
4617
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_CLR_MSK 0xfffffffc
4618
4619
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_RESET 0x0
4620
4621
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_GET(value) (((value) & 0x00000003) >> 0)
4622
4623
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_CNTRS_1_ALARMMOD_SET(value) (((value) << 0) & 0x00000003)
4624
4625
#ifndef __ASSEMBLY__
4626
4636
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s
4637
{
4638
uint32_t
COUNTERS_1_ALARMMODE
: 2;
4639
uint32_t : 30;
4640
};
4641
4643
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t
;
4644
#endif
/* __ASSEMBLY__ */
4645
4647
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_RESET 0x00000000
4648
4649
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_OFST 0x150
4650
4674
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_LSB 0
4675
4676
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_MSB 15
4677
4678
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_WIDTH 16
4679
4680
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET_MSK 0x0000ffff
4681
4682
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_CLR_MSK 0xffff0000
4683
4684
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_RESET 0x0
4685
4686
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_GET(value) (((value) & 0x0000ffff) >> 0)
4687
4688
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_CNTRS_1_VAL_SET(value) (((value) << 0) & 0x0000ffff)
4689
4690
#ifndef __ASSEMBLY__
4691
4701
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s
4702
{
4703
const
uint32_t
COUNTERS_1_VAL
: 16;
4704
uint32_t : 16;
4705
};
4706
4708
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_s
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t
;
4709
#endif
/* __ASSEMBLY__ */
4710
4712
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_RESET 0x00000000
4713
4714
#define ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_OFST 0x154
4715
4716
#ifndef __ASSEMBLY__
4717
4727
struct
ALT_NOC_MPU_DDR_T_PRB_s
4728
{
4729
volatile
ALT_NOC_MPU_DDR_T_PRB_COREID_t
ddr_T_main_Probe_Id_CoreId
;
4730
volatile
ALT_NOC_MPU_DDR_T_PRB_REVID_t
ddr_T_main_Probe_Id_RevisionId
;
4731
volatile
ALT_NOC_MPU_DDR_T_PRB_MAINCTL_t
ddr_T_main_Probe_MainCtl
;
4732
volatile
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t
ddr_T_main_Probe_CfgCtl
;
4733
volatile
uint32_t
_pad_0x10_0x13
;
4734
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTLUT_t
ddr_T_main_Probe_FilterLut
;
4735
volatile
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMEN_t
ddr_T_main_Probe_TraceAlarmEn
;
4736
volatile
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMSTAT_t
ddr_T_main_Probe_TraceAlarmStatus
;
4737
volatile
ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t
ddr_T_main_Probe_TraceAlarmClr
;
4738
volatile
ALT_NOC_MPU_DDR_T_PRB_STATPERIOD_t
ddr_T_main_Probe_StatPeriod
;
4739
volatile
ALT_NOC_MPU_DDR_T_PRB_STATGO_t
ddr_T_main_Probe_StatGo
;
4740
volatile
ALT_NOC_MPU_DDR_T_PRB_STATALARMMIN_t
ddr_T_main_Probe_StatAlarmMin
;
4741
volatile
ALT_NOC_MPU_DDR_T_PRB_STATALARMMAX_t
ddr_T_main_Probe_StatAlarmMax
;
4742
volatile
ALT_NOC_MPU_DDR_T_PRB_STATALARMSTAT_t
ddr_T_main_Probe_StatAlarmStatus
;
4743
volatile
ALT_NOC_MPU_DDR_T_PRB_STATALARMCLR_t
ddr_T_main_Probe_StatAlarmClr
;
4744
volatile
ALT_NOC_MPU_DDR_T_PRB_STATALARMEN_t
ddr_T_main_Probe_StatAlarmEn
;
4745
volatile
uint32_t
_pad_0x40_0x43
;
4746
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDBASE_t
ddr_T_main_Probe_Filters_0_RouteIdBase
;
4747
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ROUTEIDMSK_t
ddr_T_main_Probe_Filters_0_RouteIdMask
;
4748
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_ADDRBASE_LOW_t
ddr_T_main_Probe_Filters_0_AddrBase_Low
;
4749
volatile
uint32_t
_pad_0x50_0x53
;
4750
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_WINDOWSIZE_t
ddr_T_main_Probe_Filters_0_WindowSize
;
4751
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYBASE_t
ddr_T_main_Probe_Filters_0_SecurityBase
;
4752
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_SECURITYMSK_t
ddr_T_main_Probe_Filters_0_SecurityMask
;
4753
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_OPCODE_t
ddr_T_main_Probe_Filters_0_Opcode
;
4754
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_STAT_t
ddr_T_main_Probe_Filters_0_Status
;
4755
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_LEN_t
ddr_T_main_Probe_Filters_0_Length
;
4756
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_0_URGENCY_t
ddr_T_main_Probe_Filters_0_Urgency
;
4757
volatile
uint32_t
_pad_0x70_0x7f
[4];
4758
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDBASE_t
ddr_T_main_Probe_Filters_1_RouteIdBase
;
4759
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ROUTEIDMSK_t
ddr_T_main_Probe_Filters_1_RouteIdMask
;
4760
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_ADDRBASE_LOW_t
ddr_T_main_Probe_Filters_1_AddrBase_Low
;
4761
volatile
uint32_t
_pad_0x8c_0x8f
;
4762
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_WINDOWSIZE_t
ddr_T_main_Probe_Filters_1_WindowSize
;
4763
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYBASE_t
ddr_T_main_Probe_Filters_1_SecurityBase
;
4764
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_SECURITYMSK_t
ddr_T_main_Probe_Filters_1_SecurityMask
;
4765
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_OPCODE_t
ddr_T_main_Probe_Filters_1_Opcode
;
4766
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_STAT_t
ddr_T_main_Probe_Filters_1_Status
;
4767
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_LEN_t
ddr_T_main_Probe_Filters_1_Length
;
4768
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_1_URGENCY_t
ddr_T_main_Probe_Filters_1_Urgency
;
4769
volatile
uint32_t
_pad_0xac_0xbb
[4];
4770
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDBASE_t
ddr_T_main_Probe_Filters_2_RouteIdBase
;
4771
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ROUTEIDMSK_t
ddr_T_main_Probe_Filters_2_RouteIdMask
;
4772
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_ADDRBASE_LOW_t
ddr_T_main_Probe_Filters_2_AddrBase_Low
;
4773
volatile
uint32_t
_pad_0xc8_0xcb
;
4774
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_WINDOWSIZE_t
ddr_T_main_Probe_Filters_2_WindowSize
;
4775
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYBASE_t
ddr_T_main_Probe_Filters_2_SecurityBase
;
4776
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_SECURITYMSK_t
ddr_T_main_Probe_Filters_2_SecurityMask
;
4777
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_OPCODE_t
ddr_T_main_Probe_Filters_2_Opcode
;
4778
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_STAT_t
ddr_T_main_Probe_Filters_2_Status
;
4779
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_LEN_t
ddr_T_main_Probe_Filters_2_Length
;
4780
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_2_URGENCY_t
ddr_T_main_Probe_Filters_2_Urgency
;
4781
volatile
uint32_t
_pad_0xe8_0xf7
[4];
4782
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDBASE_t
ddr_T_main_Probe_Filters_3_RouteIdBase
;
4783
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ROUTEIDMSK_t
ddr_T_main_Probe_Filters_3_RouteIdMask
;
4784
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_ADDRBASE_LOW_t
ddr_T_main_Probe_Filters_3_AddrBase_Low
;
4785
volatile
uint32_t
_pad_0x104_0x107
;
4786
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_WINDOWSIZE_t
ddr_T_main_Probe_Filters_3_WindowSize
;
4787
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYBASE_t
ddr_T_main_Probe_Filters_3_SecurityBase
;
4788
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_SECURITYMSK_t
ddr_T_main_Probe_Filters_3_SecurityMask
;
4789
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_OPCODE_t
ddr_T_main_Probe_Filters_3_Opcode
;
4790
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_STAT_t
ddr_T_main_Probe_Filters_3_Status
;
4791
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_LEN_t
ddr_T_main_Probe_Filters_3_Length
;
4792
volatile
ALT_NOC_MPU_DDR_T_PRB_FLTS_3_URGENCY_t
ddr_T_main_Probe_Filters_3_Urgency
;
4793
volatile
uint32_t
_pad_0x124_0x137
[5];
4794
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_SRC_t
ddr_T_main_Probe_Counters_0_Src
;
4795
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_ALARMMOD_t
ddr_T_main_Probe_Counters_0_AlarmMode
;
4796
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_0_VAL_t
ddr_T_main_Probe_Counters_0_Val
;
4797
volatile
uint32_t
_pad_0x144_0x14b
[2];
4798
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_SRC_t
ddr_T_main_Probe_Counters_1_Src
;
4799
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_ALARMMOD_t
ddr_T_main_Probe_Counters_1_AlarmMode
;
4800
volatile
ALT_NOC_MPU_DDR_T_PRB_CNTRS_1_VAL_t
ddr_T_main_Probe_Counters_1_Val
;
4801
volatile
uint32_t
_pad_0x158_0x400
[170];
4802
};
4803
4805
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_s
ALT_NOC_MPU_DDR_T_PRB_t
;
4807
struct
ALT_NOC_MPU_DDR_T_PRB_raw_s
4808
{
4809
volatile
uint32_t
ddr_T_main_Probe_Id_CoreId
;
4810
volatile
uint32_t
ddr_T_main_Probe_Id_RevisionId
;
4811
volatile
uint32_t
ddr_T_main_Probe_MainCtl
;
4812
volatile
uint32_t
ddr_T_main_Probe_CfgCtl
;
4813
volatile
uint32_t
_pad_0x10_0x13
;
4814
volatile
uint32_t
ddr_T_main_Probe_FilterLut
;
4815
volatile
uint32_t
ddr_T_main_Probe_TraceAlarmEn
;
4816
volatile
uint32_t
ddr_T_main_Probe_TraceAlarmStatus
;
4817
volatile
uint32_t
ddr_T_main_Probe_TraceAlarmClr
;
4818
volatile
uint32_t
ddr_T_main_Probe_StatPeriod
;
4819
volatile
uint32_t
ddr_T_main_Probe_StatGo
;
4820
volatile
uint32_t
ddr_T_main_Probe_StatAlarmMin
;
4821
volatile
uint32_t
ddr_T_main_Probe_StatAlarmMax
;
4822
volatile
uint32_t
ddr_T_main_Probe_StatAlarmStatus
;
4823
volatile
uint32_t
ddr_T_main_Probe_StatAlarmClr
;
4824
volatile
uint32_t
ddr_T_main_Probe_StatAlarmEn
;
4825
volatile
uint32_t
_pad_0x40_0x43
;
4826
volatile
uint32_t
ddr_T_main_Probe_Filters_0_RouteIdBase
;
4827
volatile
uint32_t
ddr_T_main_Probe_Filters_0_RouteIdMask
;
4828
volatile
uint32_t
ddr_T_main_Probe_Filters_0_AddrBase_Low
;
4829
volatile
uint32_t
_pad_0x50_0x53
;
4830
volatile
uint32_t
ddr_T_main_Probe_Filters_0_WindowSize
;
4831
volatile
uint32_t
ddr_T_main_Probe_Filters_0_SecurityBase
;
4832
volatile
uint32_t
ddr_T_main_Probe_Filters_0_SecurityMask
;
4833
volatile
uint32_t
ddr_T_main_Probe_Filters_0_Opcode
;
4834
volatile
uint32_t
ddr_T_main_Probe_Filters_0_Status
;
4835
volatile
uint32_t
ddr_T_main_Probe_Filters_0_Length
;
4836
volatile
uint32_t
ddr_T_main_Probe_Filters_0_Urgency
;
4837
volatile
uint32_t
_pad_0x70_0x7f
[4];
4838
volatile
uint32_t
ddr_T_main_Probe_Filters_1_RouteIdBase
;
4839
volatile
uint32_t
ddr_T_main_Probe_Filters_1_RouteIdMask
;
4840
volatile
uint32_t
ddr_T_main_Probe_Filters_1_AddrBase_Low
;
4841
volatile
uint32_t
_pad_0x8c_0x8f
;
4842
volatile
uint32_t
ddr_T_main_Probe_Filters_1_WindowSize
;
4843
volatile
uint32_t
ddr_T_main_Probe_Filters_1_SecurityBase
;
4844
volatile
uint32_t
ddr_T_main_Probe_Filters_1_SecurityMask
;
4845
volatile
uint32_t
ddr_T_main_Probe_Filters_1_Opcode
;
4846
volatile
uint32_t
ddr_T_main_Probe_Filters_1_Status
;
4847
volatile
uint32_t
ddr_T_main_Probe_Filters_1_Length
;
4848
volatile
uint32_t
ddr_T_main_Probe_Filters_1_Urgency
;
4849
volatile
uint32_t
_pad_0xac_0xbb
[4];
4850
volatile
uint32_t
ddr_T_main_Probe_Filters_2_RouteIdBase
;
4851
volatile
uint32_t
ddr_T_main_Probe_Filters_2_RouteIdMask
;
4852
volatile
uint32_t
ddr_T_main_Probe_Filters_2_AddrBase_Low
;
4853
volatile
uint32_t
_pad_0xc8_0xcb
;
4854
volatile
uint32_t
ddr_T_main_Probe_Filters_2_WindowSize
;
4855
volatile
uint32_t
ddr_T_main_Probe_Filters_2_SecurityBase
;
4856
volatile
uint32_t
ddr_T_main_Probe_Filters_2_SecurityMask
;
4857
volatile
uint32_t
ddr_T_main_Probe_Filters_2_Opcode
;
4858
volatile
uint32_t
ddr_T_main_Probe_Filters_2_Status
;
4859
volatile
uint32_t
ddr_T_main_Probe_Filters_2_Length
;
4860
volatile
uint32_t
ddr_T_main_Probe_Filters_2_Urgency
;
4861
volatile
uint32_t
_pad_0xe8_0xf7
[4];
4862
volatile
uint32_t
ddr_T_main_Probe_Filters_3_RouteIdBase
;
4863
volatile
uint32_t
ddr_T_main_Probe_Filters_3_RouteIdMask
;
4864
volatile
uint32_t
ddr_T_main_Probe_Filters_3_AddrBase_Low
;
4865
volatile
uint32_t
_pad_0x104_0x107
;
4866
volatile
uint32_t
ddr_T_main_Probe_Filters_3_WindowSize
;
4867
volatile
uint32_t
ddr_T_main_Probe_Filters_3_SecurityBase
;
4868
volatile
uint32_t
ddr_T_main_Probe_Filters_3_SecurityMask
;
4869
volatile
uint32_t
ddr_T_main_Probe_Filters_3_Opcode
;
4870
volatile
uint32_t
ddr_T_main_Probe_Filters_3_Status
;
4871
volatile
uint32_t
ddr_T_main_Probe_Filters_3_Length
;
4872
volatile
uint32_t
ddr_T_main_Probe_Filters_3_Urgency
;
4873
volatile
uint32_t
_pad_0x124_0x137
[5];
4874
volatile
uint32_t
ddr_T_main_Probe_Counters_0_Src
;
4875
volatile
uint32_t
ddr_T_main_Probe_Counters_0_AlarmMode
;
4876
volatile
uint32_t
ddr_T_main_Probe_Counters_0_Val
;
4877
volatile
uint32_t
_pad_0x144_0x14b
[2];
4878
volatile
uint32_t
ddr_T_main_Probe_Counters_1_Src
;
4879
volatile
uint32_t
ddr_T_main_Probe_Counters_1_AlarmMode
;
4880
volatile
uint32_t
ddr_T_main_Probe_Counters_1_Val
;
4881
volatile
uint32_t
_pad_0x158_0x400
[170];
4882
};
4883
4885
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_PRB_raw_s
ALT_NOC_MPU_DDR_T_PRB_raw_t
;
4886
#endif
/* __ASSEMBLY__ */
4887
4913
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_LSB 0
4914
4915
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_MSB 7
4916
4917
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_WIDTH 8
4918
4919
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET_MSK 0x000000ff
4920
4921
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_CLR_MSK 0xffffff00
4922
4923
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_RESET 0x2
4924
4925
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_GET(value) (((value) & 0x000000ff) >> 0)
4926
4927
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_TYPEID_SET(value) (((value) << 0) & 0x000000ff)
4928
4938
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_LSB 8
4939
4940
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_MSB 31
4941
4942
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_WIDTH 24
4943
4944
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET_MSK 0xffffff00
4945
4946
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_CLR_MSK 0x000000ff
4947
4948
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_RESET 0x7242e2
4949
4950
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_GET(value) (((value) & 0xffffff00) >> 8)
4951
4952
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_CHECKSUM_SET(value) (((value) << 8) & 0xffffff00)
4953
4954
#ifndef __ASSEMBLY__
4955
4965
struct
ALT_NOC_MPU_DDR_T_SCHED_COREID_s
4966
{
4967
const
uint32_t
CORETYPEID
: 8;
4968
const
uint32_t
CORECHECKSUM
: 24;
4969
};
4970
4972
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_COREID_s
ALT_NOC_MPU_DDR_T_SCHED_COREID_t
;
4973
#endif
/* __ASSEMBLY__ */
4974
4976
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_RESET 0x7242e202
4977
4978
#define ALT_NOC_MPU_DDR_T_SCHED_COREID_OFST 0x0
4979
5000
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_LSB 0
5001
5002
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_MSB 7
5003
5004
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_WIDTH 8
5005
5006
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET_MSK 0x000000ff
5007
5008
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_CLR_MSK 0xffffff00
5009
5010
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_RESET 0x0
5011
5012
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_GET(value) (((value) & 0x000000ff) >> 0)
5013
5014
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_UID_SET(value) (((value) << 0) & 0x000000ff)
5015
5026
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_LSB 8
5027
5028
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_MSB 31
5029
5030
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_WIDTH 24
5031
5032
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET_MSK 0xffffff00
5033
5034
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_CLR_MSK 0x000000ff
5035
5036
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_RESET 0x129ff
5037
5038
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_GET(value) (((value) & 0xffffff00) >> 8)
5039
5040
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_FLEXNOCID_SET(value) (((value) << 8) & 0xffffff00)
5041
5042
#ifndef __ASSEMBLY__
5043
5053
struct
ALT_NOC_MPU_DDR_T_SCHED_REVID_s
5054
{
5055
const
uint32_t
USERID
: 8;
5056
const
uint32_t
FLEXNOCID
: 24;
5057
};
5058
5060
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_REVID_s
ALT_NOC_MPU_DDR_T_SCHED_REVID_t
;
5061
#endif
/* __ASSEMBLY__ */
5062
5064
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_RESET 0x0129ff00
5065
5066
#define ALT_NOC_MPU_DDR_T_SCHED_REVID_OFST 0x4
5067
5127
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R12_B3_C10 0x00
5128
5133
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R13_B3_C10 0x01
5134
5139
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C10 0x02
5140
5145
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C10 0x03
5146
5151
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C10 0x04
5152
5157
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B3_C10 0x05
5158
5163
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B3_C11 0x06
5164
5169
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C11 0x07
5170
5175
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B3_C11 0x08
5176
5181
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B3_C12 0x09
5182
5187
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R14_B4_C10 0x0A
5188
5193
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R15_B4_C10 0x0B
5194
5199
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R16_B4_C10 0x0C
5200
5205
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_R17_B4_C10 0x0D
5206
5211
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R12_C10 0x0E
5212
5217
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R13_C10 0x0F
5218
5223
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C10 0x10
5224
5229
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C10 0x11
5230
5235
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C10 0x12
5236
5241
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R17_C10 0x13
5242
5247
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R14_C11 0x14
5248
5253
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C11 0x15
5254
5259
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R16_C11 0x16
5260
5265
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B3_R15_C12 0x17
5266
5271
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R14_C10 0x18
5272
5277
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R15_C10 0x19
5278
5283
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R16_C10 0x1A
5284
5289
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_E_B4_R17_C10 0x1B
5290
5292
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_LSB 0
5293
5294
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_MSB 4
5295
5296
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_WIDTH 5
5297
5298
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET_MSK 0x0000001f
5299
5300
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_CLR_MSK 0xffffffe0
5301
5302
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_RESET 0x0
5303
5304
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_GET(value) (((value) & 0x0000001f) >> 0)
5305
5306
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_DDRCONF_SET(value) (((value) << 0) & 0x0000001f)
5307
5308
#ifndef __ASSEMBLY__
5309
5319
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s
5320
{
5321
uint32_t
DDRCONF
: 5;
5322
uint32_t : 27;
5323
};
5324
5326
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_s
ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t
;
5327
#endif
/* __ASSEMBLY__ */
5328
5330
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_RESET 0x00000000
5331
5332
#define ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_OFST 0x8
5333
5362
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0
5363
5364
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_MSB 5
5365
5366
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_WIDTH 6
5367
5368
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f
5369
5370
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0
5371
5372
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_RESET 0x1c
5373
5374
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0)
5375
5376
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f)
5377
5388
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6
5389
5390
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_MSB 11
5391
5392
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_WIDTH 6
5393
5394
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0
5395
5396
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f
5397
5398
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_RESET 0x13
5399
5400
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6)
5401
5402
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0)
5403
5414
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12
5415
5416
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_MSB 17
5417
5418
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_WIDTH 6
5419
5420
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000
5421
5422
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff
5423
5424
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_RESET 0x21
5425
5426
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12)
5427
5428
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000)
5429
5440
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18
5441
5442
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_MSB 20
5443
5444
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_WIDTH 3
5445
5446
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000
5447
5448
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff
5449
5450
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_RESET 0x2
5451
5452
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18)
5453
5454
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000)
5455
5466
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21
5467
5468
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_MSB 25
5469
5470
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_WIDTH 5
5471
5472
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET_MSK 0x03e00000
5473
5474
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff
5475
5476
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_RESET 0x1
5477
5478
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21)
5479
5480
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000)
5481
5492
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26
5493
5494
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_MSB 30
5495
5496
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_WIDTH 5
5497
5498
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET_MSK 0x7c000000
5499
5500
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff
5501
5502
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_RESET 0xb
5503
5504
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26)
5505
5506
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000)
5507
5517
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31
5518
5519
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_MSB 31
5520
5521
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_WIDTH 1
5522
5523
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET_MSK 0x80000000
5524
5525
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff
5526
5527
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_RESET 0x1
5528
5529
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31)
5530
5531
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000)
5532
5533
#ifndef __ASSEMBLY__
5534
5544
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s
5545
{
5546
uint32_t
ACTTOACT
: 6;
5547
uint32_t
RDTOMISS
: 6;
5548
uint32_t
WRTOMISS
: 6;
5549
uint32_t
BURSTLEN
: 3;
5550
uint32_t
RDTOWR
: 5;
5551
uint32_t
WRTORD
: 5;
5552
uint32_t
BWRATIO
: 1;
5553
};
5554
5556
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t
;
5557
#endif
/* __ASSEMBLY__ */
5558
5560
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RESET 0xac2a14dc
5561
5562
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_OFST 0xc
5563
5588
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_LSB 0
5589
5590
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_MSB 0
5591
5592
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_WIDTH 1
5593
5594
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET_MSK 0x00000001
5595
5596
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_CLR_MSK 0xfffffffe
5597
5598
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_RESET 0x0
5599
5600
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_GET(value) (((value) & 0x00000001) >> 0)
5601
5602
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_AUTOPRECHARGE_SET(value) (((value) << 0) & 0x00000001)
5603
5613
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_LSB 1
5614
5615
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_MSB 1
5616
5617
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_WIDTH 1
5618
5619
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET_MSK 0x00000002
5620
5621
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_CLR_MSK 0xfffffffd
5622
5623
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_RESET 0x0
5624
5625
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_GET(value) (((value) & 0x00000002) >> 1)
5626
5627
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_BWRATIOEXTENDED_SET(value) (((value) << 1) & 0x00000002)
5628
5629
#ifndef __ASSEMBLY__
5630
5640
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s
5641
{
5642
uint32_t
AUTOPRECHARGE
: 1;
5643
uint32_t
BWRATIOEXTENDED
: 1;
5644
uint32_t : 30;
5645
};
5646
5648
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_s
ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t
;
5649
#endif
/* __ASSEMBLY__ */
5650
5652
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_RESET 0x00000000
5653
5654
#define ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_OFST 0x10
5655
5677
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_LSB 0
5678
5679
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_MSB 7
5680
5681
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_WIDTH 8
5682
5683
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET_MSK 0x000000ff
5684
5685
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_CLR_MSK 0xffffff00
5686
5687
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_RESET 0x13
5688
5689
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_GET(value) (((value) & 0x000000ff) >> 0)
5690
5691
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET(value) (((value) << 0) & 0x000000ff)
5692
5693
#ifndef __ASSEMBLY__
5694
5704
struct
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s
5705
{
5706
uint32_t
READLATENCY
: 8;
5707
uint32_t : 24;
5708
};
5709
5711
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t
;
5712
#endif
/* __ASSEMBLY__ */
5713
5715
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RESET 0x00000013
5716
5717
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_OFST 0x14
5718
5744
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB 0
5745
5746
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_MSB 3
5747
5748
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_WIDTH 4
5749
5750
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET_MSK 0x0000000f
5751
5752
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_CLR_MSK 0xfffffff0
5753
5754
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_RESET 0x2
5755
5756
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_GET(value) (((value) & 0x0000000f) >> 0)
5757
5758
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET(value) (((value) << 0) & 0x0000000f)
5759
5769
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB 4
5770
5771
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_MSB 9
5772
5773
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_WIDTH 6
5774
5775
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET_MSK 0x000003f0
5776
5777
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_CLR_MSK 0xfffffc0f
5778
5779
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_RESET 0xd
5780
5781
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_GET(value) (((value) & 0x000003f0) >> 4)
5782
5783
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET(value) (((value) << 4) & 0x000003f0)
5784
5794
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB 10
5795
5796
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_MSB 10
5797
5798
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_WIDTH 1
5799
5800
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET_MSK 0x00000400
5801
5802
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_CLR_MSK 0xfffffbff
5803
5804
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_RESET 0x1
5805
5806
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_GET(value) (((value) & 0x00000400) >> 10)
5807
5808
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET(value) (((value) << 10) & 0x00000400)
5809
5810
#ifndef __ASSEMBLY__
5811
5821
struct
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s
5822
{
5823
uint32_t
RRD
: 4;
5824
uint32_t
FAW
: 6;
5825
uint32_t
FAWBANK
: 1;
5826
uint32_t : 21;
5827
};
5828
5830
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t
;
5831
#endif
/* __ASSEMBLY__ */
5832
5834
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RESET 0x000004d2
5835
5836
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_OFST 0x38
5837
5864
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_LSB 0
5865
5866
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_MSB 1
5867
5868
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_WIDTH 2
5869
5870
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET_MSK 0x00000003
5871
5872
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_CLR_MSK 0xfffffffc
5873
5874
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_RESET 0x1
5875
5876
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_GET(value) (((value) & 0x00000003) >> 0)
5877
5878
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTORD_SET(value) (((value) << 0) & 0x00000003)
5879
5890
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_LSB 2
5891
5892
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_MSB 3
5893
5894
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_WIDTH 2
5895
5896
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET_MSK 0x0000000c
5897
5898
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_CLR_MSK 0xfffffff3
5899
5900
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_RESET 0x1
5901
5902
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_GET(value) (((value) & 0x0000000c) >> 2)
5903
5904
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSRDTOWR_SET(value) (((value) << 2) & 0x0000000c)
5905
5916
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_LSB 4
5917
5918
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_MSB 5
5919
5920
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_WIDTH 2
5921
5922
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET_MSK 0x00000030
5923
5924
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_CLR_MSK 0xffffffcf
5925
5926
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_RESET 0x1
5927
5928
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_GET(value) (((value) & 0x00000030) >> 4)
5929
5930
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_BUSWRTORD_SET(value) (((value) << 4) & 0x00000030)
5931
5932
#ifndef __ASSEMBLY__
5933
5943
struct
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s
5944
{
5945
uint32_t
BUSRDTORD
: 2;
5946
uint32_t
BUSRDTOWR
: 2;
5947
uint32_t
BUSWRTORD
: 2;
5948
uint32_t : 26;
5949
};
5950
5952
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_s
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t
;
5953
#endif
/* __ASSEMBLY__ */
5954
5956
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_RESET 0x00000015
5957
5958
#define ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_OFST 0x3c
5959
5960
#ifndef __ASSEMBLY__
5961
5971
struct
ALT_NOC_MPU_DDR_T_SCHED_s
5972
{
5973
volatile
ALT_NOC_MPU_DDR_T_SCHED_COREID_t
ddr_T_main_Scheduler_Id_CoreId
;
5974
volatile
ALT_NOC_MPU_DDR_T_SCHED_REVID_t
ddr_T_main_Scheduler_Id_RevisionId
;
5975
volatile
ALT_NOC_MPU_DDR_T_SCHED_DDRCONF_t
ddr_T_main_Scheduler_DdrConf
;
5976
volatile
ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t
ddr_T_main_Scheduler_DdrTiming
;
5977
volatile
ALT_NOC_MPU_DDR_T_SCHED_DDRMOD_t
ddr_T_main_Scheduler_DdrMode
;
5978
volatile
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t
ddr_T_main_Scheduler_ReadLatency
;
5979
volatile
uint32_t
_pad_0x18_0x37
[8];
5980
volatile
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t
ddr_T_main_Scheduler_Activate
;
5981
volatile
ALT_NOC_MPU_DDR_T_SCHED_DEVTODEV_t
ddr_T_main_Scheduler_DevToDev
;
5982
volatile
uint32_t
_pad_0x40_0x80
[16];
5983
};
5984
5986
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_s
ALT_NOC_MPU_DDR_T_SCHED_t
;
5988
struct
ALT_NOC_MPU_DDR_T_SCHED_raw_s
5989
{
5990
volatile
uint32_t
ddr_T_main_Scheduler_Id_CoreId
;
5991
volatile
uint32_t
ddr_T_main_Scheduler_Id_RevisionId
;
5992
volatile
uint32_t
ddr_T_main_Scheduler_DdrConf
;
5993
volatile
uint32_t
ddr_T_main_Scheduler_DdrTiming
;
5994
volatile
uint32_t
ddr_T_main_Scheduler_DdrMode
;
5995
volatile
uint32_t
ddr_T_main_Scheduler_ReadLatency
;
5996
volatile
uint32_t
_pad_0x18_0x37
[8];
5997
volatile
uint32_t
ddr_T_main_Scheduler_Activate
;
5998
volatile
uint32_t
ddr_T_main_Scheduler_DevToDev
;
5999
volatile
uint32_t
_pad_0x40_0x80
[16];
6000
};
6001
6003
typedef
volatile
struct
ALT_NOC_MPU_DDR_T_SCHED_raw_s
ALT_NOC_MPU_DDR_T_SCHED_raw_t
;
6004
#endif
/* __ASSEMBLY__ */
6005
6007
#ifdef __cplusplus
6008
}
6009
#endif
/* __cplusplus */
6010
#endif
/* __ALT_SOCAL_NOC_MPU_DDR_H__ */
6011
include
soc_a10
socal
alt_noc_mpu_ddr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2