This module defines the API for controlling and accessing devices through the HPS SD/MMC Controller.
This module provides programmatic access to the SD/MMC host controller functions for:
- control and status
- card/device interface configuration
- command processor interface
- internal DMA controller
- FIFO
The primary purpose of this API is to a provide a general purpose framework that can be used for writing software drivers that interact with a wide range of card and device types that may interface to HPS through the SD/MMC host controller.
Although the HPS SD/MMC Controller supports SD, SDIO, CE-ATA, and MMC card and device types, this driver only supports block read/write data transfers to SD storage devices.
Supported:
- Integrated DMA Controller (IDMAC)
- Host Bus: AHB (32-bit)
- SD/MMC controller may be used by FPGA
Unsupported:
- Dual Data Rate (DDR)
- More than one card
- SDR104, SDR50, and DDR5 timing modes
Clock Signals:
- l4_mp_clk - AHB/APB Clock, Frequency Range: 0-100MHz, Must be greater than or equal to 1/10 cclk_in
- sdmmc_clk - Card input clock. Both positive and negative edges are used, Frequency Range: 0-200MHz
- sdmmc_cclk_out - Card Clock. Output from internal clock dividers.
- sdmmc_fb_clk_in - Feedback version of cclk_out to compensate for external delays, Frequency Range: 0-50MHz
Interface Signals: SD/MMC Controller Interface I/O Pins
Signal Width Direction Description
sdmmc_cclk_out 1 Out Clock from controller to the card sdmmc_cmd 1 In/Out Card command sdmmc_pwren 1 Out External device power enable sdmmc_data 8 In/Out Card data
Interrupts:
- Three (3) interrupt outputs:
- sdmmc_int
- SDIO card interrupts
- End bit error(read)/no CRC(write)
- Auto command done
- Start bit error
- Hardware locked write error
- FIFO underrun/overrun error
- Data starvation by host timeout
- Data read timeout/boot data start
- Response Timeout/Boot ack received
- Data CRC error
- Response CRC error
- Receive FIFO data request
- Transmit FIFO data request
- Data transfer over
- Command done
- Response error
- sdmmc_sberr, single bit ECC error
- sdmmc_dberr, double bit ECC error
References:
- Altera, Cyclone V Device Handbook Volume 3: Hard Processor System Technical Reference Manual, SD/MMC Controller.
- Synopsys, DesignWare Cores Mobile Storage Host Databook, DWC_mobile_storage
Notes:
- To avoid glitches in the card clock outputs (cclk_out), the software should use the steps outlined in section 7.4 Phase Switching of the databook when changing the card clock frequency.
- In order to utilize ECC, follow the embedded RAM initialization procedure in section 8 Enabling ECC of the data book.
- The SD/MMC controller does not directly support voltage switching, card interrupts, or back-end power control of eSDIO card devices. However, you can connect these signals to general-purpose I/Os (GPIOs).
- The SD/MMC controller does not contain a reset output as part of the external card interface. To reset the flash card device, consider using a general purpose output pin.
Features:
- Block Read/Write support
- Internal DMA used for efficiency
- Command Engine Interface
- Internal DMA Interface
- Configuration and Status Interface
- Interrupt Status and Control Interface