Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 MP SP APB Clock Source - l4src

Description

Contains fields that select the clock source for L4 MP and SP APB interconnect

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[0] RW 0x0 l4_mp_clk Source
[1] RW 0x0 l4_sp_clk Source
[31:2] ??? 0x0 UNDEFINED

Field : l4_mp_clk Source - l4mp

Selects the source for l4_mp_clk

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL 0x0 main_clk
ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL 0x1 periph_base_clk

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL   0x0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL   0x1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB   0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB   0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK   0x00000001
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET   0x0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET(value)   (((value) << 0) & 0x00000001)
 

Field : l4_sp_clk Source - l4sp

Selects the source for l4_sp_clk

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL 0x0 main_clk
ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL 0x1 periph_base_clk

Field Access Macros:

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL   0x0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL   0x1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB   1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB   1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH   1
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK   0x00000002
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK   0xfffffffd
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET   0x0
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET(value)   (((value) << 1) & 0x00000002)
 

Data Structures

struct  ALT_CLKMGR_MAINPLL_L4SRC_s
 

Macros

#define ALT_CLKMGR_MAINPLL_L4SRC_OFST   0x30
 

Typedefs

typedef struct
ALT_CLKMGR_MAINPLL_L4SRC_s 
ALT_CLKMGR_MAINPLL_L4SRC_t
 

Data Structure Documentation

struct ALT_CLKMGR_MAINPLL_L4SRC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_MAINPLL_L4SRC.

Data Fields
uint32_t l4mp: 1 l4_mp_clk Source
uint32_t l4sp: 1 l4_sp_clk Source
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_MAINPLL   0x0

Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP

main_clk

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_E_PERIPHPLL   0x1

Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4MP

periph_base_clk

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_RESET   0x0

The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4MP field value from a register.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4MP_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4MP register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_MAINPLL   0x0

Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP

main_clk

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_E_PERIPHPLL   0x1

Enumerated value for register field ALT_CLKMGR_MAINPLL_L4SRC_L4SP

periph_base_clk

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_LSB   1

The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_MSB   1

The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_WIDTH   1

The width in bits of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET_MSK   0x00000002

The mask used to set the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_CLR_MSK   0xfffffffd

The mask used to clear the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_RESET   0x0

The reset value of the ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_CLKMGR_MAINPLL_L4SRC_L4SP field value from a register.

#define ALT_CLKMGR_MAINPLL_L4SRC_L4SP_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_CLKMGR_MAINPLL_L4SRC_L4SP register field value suitable for setting the register.

#define ALT_CLKMGR_MAINPLL_L4SRC_OFST   0x30

The byte offset of the ALT_CLKMGR_MAINPLL_L4SRC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_MAINPLL_L4SRC.