Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : sbcfg0

Description

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0
[31:16] RW 0x0 ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1

Field : cfg_rld3_refresh_seq0

Banks to Refresh for RLD3 in sequence 0. Must not be more than 4 banks

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB   0
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB   15
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH   16
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : cfg_rld3_refresh_seq1

Banks to Refresh for RLD3 in sequence 1. Must not be more than 4 banks

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB   16
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB   31
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH   16
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_SBCFG0_s
 

Macros

#define ALT_IO48_HMC_MMR_SBCFG0_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_SBCFG0_OFST   0x5c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_SBCFG0_s 
ALT_IO48_HMC_MMR_SBCFG0_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_SBCFG0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_SBCFG0.

Data Fields
uint32_t cfg_rld3_refresh_seq0: 16 ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0
uint32_t cfg_rld3_refresh_seq1: 16 ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1

Macro Definitions

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET_MSK   0x0000ffff

The mask used to set the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_CLR_MSK   0xffff0000

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ0 register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET_MSK   0xffff0000

The mask used to set the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_CLR_MSK   0x0000ffff

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_IO48_HMC_MMR_SBCFG0_CFG_RLD3_REFRESH_SEQ1 register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG0_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_SBCFG0 register.

#define ALT_IO48_HMC_MMR_SBCFG0_OFST   0x5c

The byte offset of the ALT_IO48_HMC_MMR_SBCFG0 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG0.