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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Device reset. Controller sends a RESET command to device.
Controller resets bit after sending command to device
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK0 |
[1] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK1 |
[2] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK2 |
[3] | RW | 0x0 | ALT_NAND_CFG_DEVICE_RST_BANK3 |
[31:4] | ??? | Unknown | UNDEFINED |
Field : bank0 | |
Issues reset to bank 0. Controller resets the bit after reset command is issued to device. Field Access Macros: | |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001) |
Field : bank1 | |
Issues reset to bank 1. Controller resets the bit after reset command is issued to device. Field Access Macros: | |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002) |
Field : bank2 | |
Issues reset to bank 2. Controller resets the bit after reset command is issued to device. Field Access Macros: | |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004) |
Field : bank3 | |
Issues reset to bank 3. Controller resets the bit after reset command is issued to device. Field Access Macros: | |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0 |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008) |
Data Structures | |
struct | ALT_NAND_CFG_DEVICE_RST_s |
Macros | |
#define | ALT_NAND_CFG_DEVICE_RST_RESET 0x00000000 |
#define | ALT_NAND_CFG_DEVICE_RST_OFST 0x0 |
Typedefs | |
typedef struct ALT_NAND_CFG_DEVICE_RST_s | ALT_NAND_CFG_DEVICE_RST_t |
struct ALT_NAND_CFG_DEVICE_RST_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_DEVICE_RST.
Data Fields | ||
---|---|---|
uint32_t | bank0: 1 | ALT_NAND_CFG_DEVICE_RST_BANK0 |
uint32_t | bank1: 1 | ALT_NAND_CFG_DEVICE_RST_BANK1 |
uint32_t | bank2: 1 | ALT_NAND_CFG_DEVICE_RST_BANK2 |
uint32_t | bank3: 1 | ALT_NAND_CFG_DEVICE_RST_BANK3 |
uint32_t | __pad0__: 28 | UNDEFINED |
#define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001 |
The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK0 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0 |
The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK0 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NAND_CFG_DEVICE_RST_BANK0 field value from a register.
#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NAND_CFG_DEVICE_RST_BANK0 register field value suitable for setting the register.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002 |
The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK1 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0 |
The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK1 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_NAND_CFG_DEVICE_RST_BANK1 field value from a register.
#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_NAND_CFG_DEVICE_RST_BANK1 register field value suitable for setting the register.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004 |
The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK2 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0 |
The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK2 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_NAND_CFG_DEVICE_RST_BANK2 field value from a register.
#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_NAND_CFG_DEVICE_RST_BANK2 register field value suitable for setting the register.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008 |
The mask used to set the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_NAND_CFG_DEVICE_RST_BANK3 register field value.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0 |
The reset value of the ALT_NAND_CFG_DEVICE_RST_BANK3 register field.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_NAND_CFG_DEVICE_RST_BANK3 field value from a register.
#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_NAND_CFG_DEVICE_RST_BANK3 register field value suitable for setting the register.
#define ALT_NAND_CFG_DEVICE_RST_RESET 0x00000000 |
The reset value of the ALT_NAND_CFG_DEVICE_RST register.
#define ALT_NAND_CFG_DEVICE_RST_OFST 0x0 |
The byte offset of the ALT_NAND_CFG_DEVICE_RST register from the beginning of the component.
typedef struct ALT_NAND_CFG_DEVICE_RST_s ALT_NAND_CFG_DEVICE_RST_t |
The typedef declaration for register ALT_NAND_CFG_DEVICE_RST.