Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L2 Data RAM ECC Enable Register - mpu_ctrl_l2_ecc

Description

This register is used to enable ECC on the L2 Data RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error.

Some fileds of this register are only reset by a cold reset (ignores warm reset).

Some fields are affected by both warm and cold reset.

Register Layout

Bits Access Reset Description
[0] RW 0x0 L2 Data RAM Error Correction and Detection Enable
[7:1] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN
[15:9] ??? 0x0 UNDEFINED
[16] RW 0x0 ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE
[31:17] ??? 0x0 UNDEFINED

Field : L2 Data RAM Error Correction and Detection Enable - ecc_en

Enable Single bit or Double bit error Detection and Single bit Error Correction for L2 Data RAM

Only reset by a cold reset (ignores warm reset).

Field Access Macros:

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_LSB   0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_MSB   0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_WIDTH   1
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET_MSK   0x00000001
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_RESET   0x0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : inj_en

Error injection enable. Write 1 here to enable error injection to MPU L2.

Please note that if ECC is not enabled by writing 1 to ecc_en bit there wont be any error injections.

This bit will get reset on a warm reset and cold reset.

Field Access Macros:

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_LSB   8
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_MSB   8
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_WIDTH   1
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET_MSK   0x00000100
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_CLR_MSK   0xfffffeff
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_RESET   0x0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : inj_type

MPU L2 ECC error injection type. This bit will get reset on a warm reset and cold reset.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT | 0x0 | ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT | 0x1 |

Field Access Macros:

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT   0x0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT   0x1
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_LSB   16
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_MSB   16
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_WIDTH   1
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET_MSK   0x00010000
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_CLR_MSK   0xfffeffff
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_RESET   0x0
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET(value)   (((value) << 16) & 0x00010000)
 

Data Structures

struct  ALT_SYSMGR_MPU_CTL_L2_ECC_s
 

Macros

#define ALT_SYSMGR_MPU_CTL_L2_ECC_RESET   0x00000000
 
#define ALT_SYSMGR_MPU_CTL_L2_ECC_OFST   0x10
 

Typedefs

typedef struct
ALT_SYSMGR_MPU_CTL_L2_ECC_s 
ALT_SYSMGR_MPU_CTL_L2_ECC_t
 

Data Structure Documentation

struct ALT_SYSMGR_MPU_CTL_L2_ECC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_MPU_CTL_L2_ECC.

Data Fields
uint32_t ecc_en: 1 L2 Data RAM Error Correction and Detection Enable
uint32_t __pad0__: 7 UNDEFINED
uint32_t inj_en: 1 ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN
uint32_t __pad1__: 7 UNDEFINED
uint32_t inj_type: 1 ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE
uint32_t __pad2__: 15 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN field value from a register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_MSB   8

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET_MSK   0x00000100

The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN field value from a register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT   0x0

Enumerated value for register field ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT   0x1

Enumerated value for register field ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_LSB   16

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_MSB   16

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET_MSK   0x00010000

The mask used to set the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_CLR_MSK   0xfffeffff

The mask used to clear the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE field value from a register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_RESET   0x00000000

The reset value of the ALT_SYSMGR_MPU_CTL_L2_ECC register.

#define ALT_SYSMGR_MPU_CTL_L2_ECC_OFST   0x10

The byte offset of the ALT_SYSMGR_MPU_CTL_L2_ECC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_MPU_CTL_L2_ECC.