Altera SoCAL  16.0
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alt_clkmgr.h
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32 
35 #ifndef __ALT_SOCAL_CLKMGR_H__
36 #define __ALT_SOCAL_CLKMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
87 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_LSB 0
88 
89 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_MSB 0
90 
91 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_WIDTH 1
92 
93 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK 0x00000001
94 
95 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_CLR_MSK 0xfffffffe
96 
97 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_RESET 0x1
98 
99 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_GET(value) (((value) & 0x00000001) >> 0)
100 
101 #define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET(value) (((value) << 0) & 0x00000001)
102 
116 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_LSB 8
117 
118 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_MSB 8
119 
120 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_WIDTH 1
121 
122 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET_MSK 0x00000100
123 
124 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_CLR_MSK 0xfffffeff
125 
126 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_RESET 0x0
127 
128 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_GET(value) (((value) & 0x00000100) >> 8)
129 
130 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET(value) (((value) << 8) & 0x00000100)
131 
146 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_LSB 9
147 
148 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_MSB 9
149 
150 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_WIDTH 1
151 
152 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET_MSK 0x00000200
153 
154 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_CLR_MSK 0xfffffdff
155 
156 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_RESET 0x0
157 
158 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_GET(value) (((value) & 0x00000200) >> 9)
159 
160 #define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET(value) (((value) << 9) & 0x00000200)
161 
162 #ifndef __ASSEMBLY__
163 
174 {
175  uint32_t bootmode : 1;
176  uint32_t : 7;
177  uint32_t swctrlbtclken : 1;
178  uint32_t swctrlbtclksel : 1;
179  uint32_t : 22;
180 };
181 
184 #endif /* __ASSEMBLY__ */
185 
187 #define ALT_CLKMGR_CLKMGR_CTL_RESET 0x00000003
188 
189 #define ALT_CLKMGR_CLKMGR_CTL_OFST 0x0
190 
222 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_LSB 0
223 
224 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_MSB 0
225 
226 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_WIDTH 1
227 
228 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK 0x00000001
229 
230 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
231 
232 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_RESET 0x0
233 
234 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
235 
236 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
237 
249 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_LSB 1
250 
251 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_MSB 1
252 
253 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_WIDTH 1
254 
255 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK 0x00000002
256 
257 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
258 
259 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_RESET 0x0
260 
261 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
262 
263 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
264 
275 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_LSB 2
276 
277 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_MSB 2
278 
279 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_WIDTH 1
280 
281 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK 0x00000004
282 
283 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_CLR_MSK 0xfffffffb
284 
285 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_RESET 0x0
286 
287 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
288 
289 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
290 
301 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_LSB 3
302 
303 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_MSB 3
304 
305 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_WIDTH 1
306 
307 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK 0x00000008
308 
309 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_CLR_MSK 0xfffffff7
310 
311 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_RESET 0x0
312 
313 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
314 
315 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
316 
328 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_LSB 8
329 
330 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_MSB 8
331 
332 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_WIDTH 1
333 
334 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK 0x00000100
335 
336 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
337 
338 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_RESET 0x0
339 
340 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
341 
342 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
343 
355 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_LSB 9
356 
357 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_MSB 9
358 
359 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_WIDTH 1
360 
361 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK 0x00000200
362 
363 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
364 
365 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_RESET 0x0
366 
367 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
368 
369 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
370 
381 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_LSB 10
382 
383 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_MSB 10
384 
385 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_WIDTH 1
386 
387 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK 0x00000400
388 
389 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
390 
391 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_RESET 0x0
392 
393 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
394 
395 #define ALT_CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
396 
408 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_LSB 11
409 
410 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_MSB 11
411 
412 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_WIDTH 1
413 
414 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK 0x00000800
415 
416 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
417 
418 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_RESET 0x0
419 
420 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
421 
422 #define ALT_CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
423 
424 #ifndef __ASSEMBLY__
425 
436 {
437  uint32_t mainpllachieved : 1;
438  uint32_t perpllachieved : 1;
439  uint32_t mainplllost : 1;
440  uint32_t perplllost : 1;
441  uint32_t : 4;
442  uint32_t mainpllrfslip : 1;
443  uint32_t perpllrfslip : 1;
444  uint32_t mainpllfbslip : 1;
445  uint32_t perpllfbslip : 1;
446  uint32_t : 20;
447 };
448 
451 #endif /* __ASSEMBLY__ */
452 
454 #define ALT_CLKMGR_CLKMGR_INTR_RESET 0x00000000
455 
456 #define ALT_CLKMGR_CLKMGR_INTR_OFST 0x4
457 
489 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_LSB 0
490 
491 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_MSB 0
492 
493 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_WIDTH 1
494 
495 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_SET_MSK 0x00000001
496 
497 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
498 
499 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_RESET 0x0
500 
501 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
502 
503 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
504 
516 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_LSB 1
517 
518 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_MSB 1
519 
520 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_WIDTH 1
521 
522 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_SET_MSK 0x00000002
523 
524 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_CLR_MSK 0xfffffffd
525 
526 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_RESET 0x0
527 
528 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
529 
530 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
531 
542 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_LSB 2
543 
544 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_MSB 2
545 
546 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_WIDTH 1
547 
548 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_SET_MSK 0x00000004
549 
550 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_CLR_MSK 0xfffffffb
551 
552 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_RESET 0x0
553 
554 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
555 
556 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
557 
568 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_LSB 3
569 
570 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_MSB 3
571 
572 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_WIDTH 1
573 
574 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_SET_MSK 0x00000008
575 
576 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_CLR_MSK 0xfffffff7
577 
578 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_RESET 0x0
579 
580 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
581 
582 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
583 
595 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_LSB 8
596 
597 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_MSB 8
598 
599 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_WIDTH 1
600 
601 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_SET_MSK 0x00000100
602 
603 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
604 
605 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_RESET 0x0
606 
607 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
608 
609 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
610 
622 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_LSB 9
623 
624 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_MSB 9
625 
626 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_WIDTH 1
627 
628 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_SET_MSK 0x00000200
629 
630 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_CLR_MSK 0xfffffdff
631 
632 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_RESET 0x0
633 
634 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
635 
636 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
637 
648 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_LSB 10
649 
650 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_MSB 10
651 
652 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_WIDTH 1
653 
654 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_SET_MSK 0x00000400
655 
656 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
657 
658 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_RESET 0x0
659 
660 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
661 
662 #define ALT_CLKMGR_CLKMGR_INTRS_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
663 
675 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_LSB 11
676 
677 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_MSB 11
678 
679 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_WIDTH 1
680 
681 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_SET_MSK 0x00000800
682 
683 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
684 
685 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_RESET 0x0
686 
687 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
688 
689 #define ALT_CLKMGR_CLKMGR_INTRS_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
690 
691 #ifndef __ASSEMBLY__
692 
703 {
704  uint32_t mainpllachieved : 1;
705  uint32_t perpllachieved : 1;
706  uint32_t mainplllost : 1;
707  uint32_t perplllost : 1;
708  uint32_t : 4;
709  uint32_t mainpllrfslip : 1;
710  uint32_t perpllrfslip : 1;
711  uint32_t mainpllfbslip : 1;
712  uint32_t perpllfbslip : 1;
713  uint32_t : 20;
714 };
715 
718 #endif /* __ASSEMBLY__ */
719 
721 #define ALT_CLKMGR_CLKMGR_INTRS_RESET 0x00000000
722 
723 #define ALT_CLKMGR_CLKMGR_INTRS_OFST 0x8
724 
756 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_LSB 0
757 
758 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_MSB 0
759 
760 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_WIDTH 1
761 
762 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_SET_MSK 0x00000001
763 
764 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
765 
766 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_RESET 0x0
767 
768 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
769 
770 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
771 
783 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_LSB 1
784 
785 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_MSB 1
786 
787 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_WIDTH 1
788 
789 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_SET_MSK 0x00000002
790 
791 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
792 
793 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_RESET 0x0
794 
795 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
796 
797 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
798 
809 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_LSB 2
810 
811 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_MSB 2
812 
813 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_WIDTH 1
814 
815 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_SET_MSK 0x00000004
816 
817 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_CLR_MSK 0xfffffffb
818 
819 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_RESET 0x0
820 
821 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
822 
823 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
824 
835 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_LSB 3
836 
837 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_MSB 3
838 
839 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_WIDTH 1
840 
841 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_SET_MSK 0x00000008
842 
843 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_CLR_MSK 0xfffffff7
844 
845 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_RESET 0x0
846 
847 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
848 
849 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
850 
862 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_LSB 8
863 
864 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_MSB 8
865 
866 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_WIDTH 1
867 
868 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_SET_MSK 0x00000100
869 
870 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
871 
872 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_RESET 0x0
873 
874 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
875 
876 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
877 
889 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_LSB 9
890 
891 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_MSB 9
892 
893 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_WIDTH 1
894 
895 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_SET_MSK 0x00000200
896 
897 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
898 
899 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_RESET 0x0
900 
901 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
902 
903 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
904 
915 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_LSB 10
916 
917 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_MSB 10
918 
919 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_WIDTH 1
920 
921 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_SET_MSK 0x00000400
922 
923 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
924 
925 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_RESET 0x0
926 
927 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
928 
929 #define ALT_CLKMGR_CLKMGR_INTRR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
930 
942 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_LSB 11
943 
944 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_MSB 11
945 
946 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_WIDTH 1
947 
948 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_SET_MSK 0x00000800
949 
950 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
951 
952 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_RESET 0x0
953 
954 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
955 
956 #define ALT_CLKMGR_CLKMGR_INTRR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
957 
958 #ifndef __ASSEMBLY__
959 
970 {
971  uint32_t mainpllachieved : 1;
972  uint32_t perpllachieved : 1;
973  uint32_t mainplllost : 1;
974  uint32_t perplllost : 1;
975  uint32_t : 4;
976  uint32_t mainpllrfslip : 1;
977  uint32_t perpllrfslip : 1;
978  uint32_t mainpllfbslip : 1;
979  uint32_t perpllfbslip : 1;
980  uint32_t : 20;
981 };
982 
985 #endif /* __ASSEMBLY__ */
986 
988 #define ALT_CLKMGR_CLKMGR_INTRR_RESET 0x00000000
989 
990 #define ALT_CLKMGR_CLKMGR_INTRR_OFST 0xc
991 
1024 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_LSB 0
1025 
1026 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_MSB 0
1027 
1028 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_WIDTH 1
1029 
1030 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_SET_MSK 0x00000001
1031 
1032 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1033 
1034 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_RESET 0x0
1035 
1036 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1037 
1038 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1039 
1051 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_LSB 1
1052 
1053 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_MSB 1
1054 
1055 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_WIDTH 1
1056 
1057 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_SET_MSK 0x00000002
1058 
1059 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1060 
1061 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_RESET 0x0
1062 
1063 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1064 
1065 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1066 
1078 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_LSB 2
1079 
1080 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_MSB 2
1081 
1082 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_WIDTH 1
1083 
1084 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_SET_MSK 0x00000004
1085 
1086 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_CLR_MSK 0xfffffffb
1087 
1088 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_RESET 0x0
1089 
1090 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1091 
1092 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1093 
1105 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_LSB 3
1106 
1107 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_MSB 3
1108 
1109 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_WIDTH 1
1110 
1111 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_SET_MSK 0x00000008
1112 
1113 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_CLR_MSK 0xfffffff7
1114 
1115 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_RESET 0x0
1116 
1117 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1118 
1119 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1120 
1132 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_LSB 8
1133 
1134 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_MSB 8
1135 
1136 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_WIDTH 1
1137 
1138 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_SET_MSK 0x00000100
1139 
1140 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1141 
1142 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_RESET 0x0
1143 
1144 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1145 
1146 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1147 
1159 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_LSB 9
1160 
1161 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_MSB 9
1162 
1163 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_WIDTH 1
1164 
1165 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_SET_MSK 0x00000200
1166 
1167 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1168 
1169 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_RESET 0x0
1170 
1171 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1172 
1173 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1174 
1186 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_LSB 10
1187 
1188 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_MSB 10
1189 
1190 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_WIDTH 1
1191 
1192 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_SET_MSK 0x00000400
1193 
1194 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1195 
1196 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_RESET 0x0
1197 
1198 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1199 
1200 #define ALT_CLKMGR_CLKMGR_INTREN_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1201 
1213 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_LSB 11
1214 
1215 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_MSB 11
1216 
1217 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_WIDTH 1
1218 
1219 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_SET_MSK 0x00000800
1220 
1221 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1222 
1223 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_RESET 0x0
1224 
1225 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1226 
1227 #define ALT_CLKMGR_CLKMGR_INTREN_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1228 
1229 #ifndef __ASSEMBLY__
1230 
1241 {
1242  uint32_t mainpllachieved : 1;
1243  uint32_t perpllachieved : 1;
1244  uint32_t mainplllost : 1;
1245  uint32_t perplllost : 1;
1246  uint32_t : 4;
1247  uint32_t mainpllrfslip : 1;
1248  uint32_t perpllrfslip : 1;
1249  uint32_t mainpllfbslip : 1;
1250  uint32_t perpllfbslip : 1;
1251  uint32_t : 20;
1252 };
1253 
1256 #endif /* __ASSEMBLY__ */
1257 
1259 #define ALT_CLKMGR_CLKMGR_INTREN_RESET 0x00000000
1260 
1261 #define ALT_CLKMGR_CLKMGR_INTREN_OFST 0x10
1262 
1295 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_LSB 0
1296 
1297 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_MSB 0
1298 
1299 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_WIDTH 1
1300 
1301 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_SET_MSK 0x00000001
1302 
1303 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1304 
1305 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_RESET 0x0
1306 
1307 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1308 
1309 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1310 
1322 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_LSB 1
1323 
1324 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_MSB 1
1325 
1326 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_WIDTH 1
1327 
1328 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_SET_MSK 0x00000002
1329 
1330 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1331 
1332 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_RESET 0x0
1333 
1334 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1335 
1336 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1337 
1349 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_LSB 2
1350 
1351 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_MSB 2
1352 
1353 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_WIDTH 1
1354 
1355 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_SET_MSK 0x00000004
1356 
1357 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_CLR_MSK 0xfffffffb
1358 
1359 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_RESET 0x0
1360 
1361 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1362 
1363 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1364 
1376 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_LSB 3
1377 
1378 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_MSB 3
1379 
1380 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_WIDTH 1
1381 
1382 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_SET_MSK 0x00000008
1383 
1384 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_CLR_MSK 0xfffffff7
1385 
1386 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_RESET 0x0
1387 
1388 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1389 
1390 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1391 
1403 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_LSB 8
1404 
1405 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_MSB 8
1406 
1407 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_WIDTH 1
1408 
1409 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_SET_MSK 0x00000100
1410 
1411 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1412 
1413 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_RESET 0x0
1414 
1415 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1416 
1417 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1418 
1430 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_LSB 9
1431 
1432 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_MSB 9
1433 
1434 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_WIDTH 1
1435 
1436 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_SET_MSK 0x00000200
1437 
1438 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1439 
1440 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_RESET 0x0
1441 
1442 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1443 
1444 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1445 
1457 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_LSB 10
1458 
1459 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_MSB 10
1460 
1461 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_WIDTH 1
1462 
1463 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_SET_MSK 0x00000400
1464 
1465 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1466 
1467 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_RESET 0x0
1468 
1469 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1470 
1471 #define ALT_CLKMGR_CLKMGR_INTRENS_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1472 
1484 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_LSB 11
1485 
1486 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_MSB 11
1487 
1488 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_WIDTH 1
1489 
1490 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_SET_MSK 0x00000800
1491 
1492 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1493 
1494 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_RESET 0x0
1495 
1496 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1497 
1498 #define ALT_CLKMGR_CLKMGR_INTRENS_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1499 
1500 #ifndef __ASSEMBLY__
1501 
1512 {
1513  uint32_t mainpllachieved : 1;
1514  uint32_t perpllachieved : 1;
1515  uint32_t mainplllost : 1;
1516  uint32_t perplllost : 1;
1517  uint32_t : 4;
1518  uint32_t mainpllrfslip : 1;
1519  uint32_t perpllrfslip : 1;
1520  uint32_t mainpllfbslip : 1;
1521  uint32_t perpllfbslip : 1;
1522  uint32_t : 20;
1523 };
1524 
1527 #endif /* __ASSEMBLY__ */
1528 
1530 #define ALT_CLKMGR_CLKMGR_INTRENS_RESET 0x00000000
1531 
1532 #define ALT_CLKMGR_CLKMGR_INTRENS_OFST 0x14
1533 
1566 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_LSB 0
1567 
1568 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_MSB 0
1569 
1570 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_WIDTH 1
1571 
1572 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_SET_MSK 0x00000001
1573 
1574 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_CLR_MSK 0xfffffffe
1575 
1576 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_RESET 0x0
1577 
1578 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_GET(value) (((value) & 0x00000001) >> 0)
1579 
1580 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLACHIEVED_SET(value) (((value) << 0) & 0x00000001)
1581 
1593 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_LSB 1
1594 
1595 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_MSB 1
1596 
1597 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_WIDTH 1
1598 
1599 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_SET_MSK 0x00000002
1600 
1601 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_CLR_MSK 0xfffffffd
1602 
1603 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_RESET 0x0
1604 
1605 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_GET(value) (((value) & 0x00000002) >> 1)
1606 
1607 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLACHIEVED_SET(value) (((value) << 1) & 0x00000002)
1608 
1620 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_LSB 2
1621 
1622 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_MSB 2
1623 
1624 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_WIDTH 1
1625 
1626 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_SET_MSK 0x00000004
1627 
1628 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_CLR_MSK 0xfffffffb
1629 
1630 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_RESET 0x0
1631 
1632 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_GET(value) (((value) & 0x00000004) >> 2)
1633 
1634 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLLOST_SET(value) (((value) << 2) & 0x00000004)
1635 
1647 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_LSB 3
1648 
1649 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_MSB 3
1650 
1651 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_WIDTH 1
1652 
1653 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_SET_MSK 0x00000008
1654 
1655 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_CLR_MSK 0xfffffff7
1656 
1657 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_RESET 0x0
1658 
1659 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_GET(value) (((value) & 0x00000008) >> 3)
1660 
1661 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLLOST_SET(value) (((value) << 3) & 0x00000008)
1662 
1674 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_LSB 8
1675 
1676 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_MSB 8
1677 
1678 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_WIDTH 1
1679 
1680 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_SET_MSK 0x00000100
1681 
1682 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_CLR_MSK 0xfffffeff
1683 
1684 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_RESET 0x0
1685 
1686 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_GET(value) (((value) & 0x00000100) >> 8)
1687 
1688 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLRFSLIP_SET(value) (((value) << 8) & 0x00000100)
1689 
1701 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_LSB 9
1702 
1703 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_MSB 9
1704 
1705 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_WIDTH 1
1706 
1707 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_SET_MSK 0x00000200
1708 
1709 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_CLR_MSK 0xfffffdff
1710 
1711 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_RESET 0x0
1712 
1713 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_GET(value) (((value) & 0x00000200) >> 9)
1714 
1715 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLRFSLIP_SET(value) (((value) << 9) & 0x00000200)
1716 
1728 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_LSB 10
1729 
1730 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_MSB 10
1731 
1732 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_WIDTH 1
1733 
1734 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_SET_MSK 0x00000400
1735 
1736 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_CLR_MSK 0xfffffbff
1737 
1738 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_RESET 0x0
1739 
1740 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_GET(value) (((value) & 0x00000400) >> 10)
1741 
1742 #define ALT_CLKMGR_CLKMGR_INTRENR_MAINPLLFBSLIP_SET(value) (((value) << 10) & 0x00000400)
1743 
1755 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_LSB 11
1756 
1757 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_MSB 11
1758 
1759 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_WIDTH 1
1760 
1761 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_SET_MSK 0x00000800
1762 
1763 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_CLR_MSK 0xfffff7ff
1764 
1765 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_RESET 0x0
1766 
1767 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_GET(value) (((value) & 0x00000800) >> 11)
1768 
1769 #define ALT_CLKMGR_CLKMGR_INTRENR_PERPLLFBSLIP_SET(value) (((value) << 11) & 0x00000800)
1770 
1771 #ifndef __ASSEMBLY__
1772 
1783 {
1784  uint32_t mainpllachieved : 1;
1785  uint32_t perpllachieved : 1;
1786  uint32_t mainplllost : 1;
1787  uint32_t perplllost : 1;
1788  uint32_t : 4;
1789  uint32_t mainpllrfslip : 1;
1790  uint32_t perpllrfslip : 1;
1791  uint32_t mainpllfbslip : 1;
1792  uint32_t perpllfbslip : 1;
1793  uint32_t : 20;
1794 };
1795 
1798 #endif /* __ASSEMBLY__ */
1799 
1801 #define ALT_CLKMGR_CLKMGR_INTRENR_RESET 0x00000000
1802 
1803 #define ALT_CLKMGR_CLKMGR_INTRENR_OFST 0x18
1804 
1854 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_E_IDLE 0x0
1855 
1860 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_E_BUSY 0x1
1861 
1863 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_LSB 0
1864 
1865 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_MSB 0
1866 
1867 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_WIDTH 1
1868 
1869 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_SET_MSK 0x00000001
1870 
1871 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_CLR_MSK 0xfffffffe
1872 
1873 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_RESET 0x0
1874 
1875 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1876 
1877 #define ALT_CLKMGR_CLKMGR_STAT_BUSY_SET(value) (((value) << 0) & 0x00000001)
1878 
1889 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_LSB 8
1890 
1891 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_MSB 8
1892 
1893 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_WIDTH 1
1894 
1895 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK 0x00000100
1896 
1897 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_CLR_MSK 0xfffffeff
1898 
1899 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_RESET 0x0
1900 
1901 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_GET(value) (((value) & 0x00000100) >> 8)
1902 
1903 #define ALT_CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET(value) (((value) << 8) & 0x00000100)
1904 
1915 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_LSB 9
1916 
1917 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_MSB 9
1918 
1919 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_WIDTH 1
1920 
1921 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK 0x00000200
1922 
1923 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_CLR_MSK 0xfffffdff
1924 
1925 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_RESET 0x0
1926 
1927 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_GET(value) (((value) & 0x00000200) >> 9)
1928 
1929 #define ALT_CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET(value) (((value) << 9) & 0x00000200)
1930 
1944 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_LSB 16
1945 
1946 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_MSB 16
1947 
1948 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_WIDTH 1
1949 
1950 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_SET_MSK 0x00010000
1951 
1952 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_CLR_MSK 0xfffeffff
1953 
1954 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_RESET 0x1
1955 
1956 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_GET(value) (((value) & 0x00010000) >> 16)
1957 
1958 #define ALT_CLKMGR_CLKMGR_STAT_BOOTMOD_SET(value) (((value) << 16) & 0x00010000)
1959 
1972 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_LSB 17
1973 
1974 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_MSB 17
1975 
1976 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_WIDTH 1
1977 
1978 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK 0x00020000
1979 
1980 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_CLR_MSK 0xfffdffff
1981 
1982 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_RESET 0x0
1983 
1984 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_GET(value) (((value) & 0x00020000) >> 17)
1985 
1986 #define ALT_CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET(value) (((value) << 17) & 0x00020000)
1987 
1988 #ifndef __ASSEMBLY__
1989 
2000 {
2001  const uint32_t busy : 1;
2002  uint32_t : 7;
2003  const uint32_t mainplllocked : 1;
2004  const uint32_t perplllocked : 1;
2005  uint32_t : 6;
2006  const uint32_t bootmode : 1;
2007  const uint32_t bootclksrc : 1;
2008  uint32_t : 14;
2009 };
2010 
2013 #endif /* __ASSEMBLY__ */
2014 
2016 #define ALT_CLKMGR_CLKMGR_STAT_RESET 0x00010000
2017 
2018 #define ALT_CLKMGR_CLKMGR_STAT_OFST 0x1c
2019 
2078 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_LSB 0
2079 
2080 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_MSB 3
2081 
2082 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_WIDTH 4
2083 
2084 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET_MSK 0x0000000f
2085 
2086 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_CLR_MSK 0xfffffff0
2087 
2088 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_RESET 0x8
2089 
2090 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_GET(value) (((value) & 0x0000000f) >> 0)
2091 
2092 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET(value) (((value) << 0) & 0x0000000f)
2093 
2126 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_LSB 8
2127 
2128 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_MSB 11
2129 
2130 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_WIDTH 4
2131 
2132 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET_MSK 0x00000f00
2133 
2134 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_CLR_MSK 0xfffff0ff
2135 
2136 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_RESET 0x8
2137 
2138 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_GET(value) (((value) & 0x00000f00) >> 8)
2139 
2140 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET(value) (((value) << 8) & 0x00000f00)
2141 
2177 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_LSB 16
2178 
2179 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_MSB 20
2180 
2181 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_WIDTH 5
2182 
2183 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET_MSK 0x001f0000
2184 
2185 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_CLR_MSK 0xffe0ffff
2186 
2187 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_RESET 0x10
2188 
2189 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_GET(value) (((value) & 0x001f0000) >> 16)
2190 
2191 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET(value) (((value) << 16) & 0x001f0000)
2192 
2193 #ifndef __ASSEMBLY__
2194 
2205 {
2206  uint32_t mainclksel : 4;
2207  uint32_t : 4;
2208  uint32_t periclksel : 4;
2209  uint32_t : 4;
2210  uint32_t debugclksel : 5;
2211  uint32_t : 11;
2212 };
2213 
2216 #endif /* __ASSEMBLY__ */
2217 
2219 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_RESET 0x00100808
2220 
2221 #define ALT_CLKMGR_CLKMGR_TESTIOCTL_OFST 0x20
2222 
2223 #ifndef __ASSEMBLY__
2224 
2235 {
2245  volatile uint32_t _pad_0x24_0x40[7];
2246 };
2247 
2252 {
2253  volatile uint32_t ctrl;
2254  volatile uint32_t intr;
2255  volatile uint32_t intrs;
2256  volatile uint32_t intrr;
2257  volatile uint32_t intren;
2258  volatile uint32_t intrens;
2259  volatile uint32_t intrenr;
2260  volatile uint32_t stat;
2261  volatile uint32_t testioctrl;
2262  volatile uint32_t _pad_0x24_0x40[7];
2263 };
2264 
2267 #endif /* __ASSEMBLY__ */
2268 
2305 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_LSB 0
2306 
2307 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_MSB 0
2308 
2309 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_WIDTH 1
2310 
2311 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
2312 
2313 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe
2314 
2315 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_RESET 0x1
2316 
2317 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
2318 
2319 #define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
2320 
2330 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_LSB 1
2331 
2332 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_MSB 1
2333 
2334 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_WIDTH 1
2335 
2336 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002
2337 
2338 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd
2339 
2340 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_RESET 0x1
2341 
2342 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_GET(value) (((value) & 0x00000002) >> 1)
2343 
2344 #define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET(value) (((value) << 1) & 0x00000002)
2345 
2355 #define ALT_CLKMGR_MAINPLL_VCO0_EN_LSB 2
2356 
2357 #define ALT_CLKMGR_MAINPLL_VCO0_EN_MSB 2
2358 
2359 #define ALT_CLKMGR_MAINPLL_VCO0_EN_WIDTH 1
2360 
2361 #define ALT_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004
2362 
2363 #define ALT_CLKMGR_MAINPLL_VCO0_EN_CLR_MSK 0xfffffffb
2364 
2365 #define ALT_CLKMGR_MAINPLL_VCO0_EN_RESET 0x0
2366 
2367 #define ALT_CLKMGR_MAINPLL_VCO0_EN_GET(value) (((value) & 0x00000004) >> 2)
2368 
2369 #define ALT_CLKMGR_MAINPLL_VCO0_EN_SET(value) (((value) << 2) & 0x00000004)
2370 
2387 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_LSB 3
2388 
2389 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_MSB 3
2390 
2391 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_WIDTH 1
2392 
2393 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
2394 
2395 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7
2396 
2397 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_RESET 0x0
2398 
2399 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_GET(value) (((value) & 0x00000008) >> 3)
2400 
2401 #define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET(value) (((value) << 3) & 0x00000008)
2402 
2424 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_LSB 4
2425 
2426 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_MSB 4
2427 
2428 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_WIDTH 1
2429 
2430 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
2431 
2432 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef
2433 
2434 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_RESET 0x0
2435 
2436 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_GET(value) (((value) & 0x00000010) >> 4)
2437 
2438 #define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET(value) (((value) << 4) & 0x00000010)
2439 
2449 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_LSB 5
2450 
2451 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_MSB 5
2452 
2453 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_WIDTH 1
2454 
2455 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET_MSK 0x00000020
2456 
2457 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf
2458 
2459 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_RESET 0x0
2460 
2461 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_GET(value) (((value) & 0x00000020) >> 5)
2462 
2463 #define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET(value) (((value) << 5) & 0x00000020)
2464 
2474 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_LSB 6
2475 
2476 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_MSB 6
2477 
2478 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_WIDTH 1
2479 
2480 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET_MSK 0x00000040
2481 
2482 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_CLR_MSK 0xffffffbf
2483 
2484 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_RESET 0x1
2485 
2486 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_GET(value) (((value) & 0x00000040) >> 6)
2487 
2488 #define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET(value) (((value) << 6) & 0x00000040)
2489 
2511 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_EOSC1 0x0
2512 
2517 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
2518 
2523 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_F2S 0x2
2524 
2526 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
2527 
2528 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_MSB 9
2529 
2530 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_WIDTH 2
2531 
2532 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET_MSK 0x00000300
2533 
2534 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_CLR_MSK 0xfffffcff
2535 
2536 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_RESET 0x0
2537 
2538 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_GET(value) (((value) & 0x00000300) >> 8)
2539 
2540 #define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET(value) (((value) << 8) & 0x00000300)
2541 
2551 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_LSB 16
2552 
2553 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_MSB 27
2554 
2555 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_WIDTH 12
2556 
2557 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET_MSK 0x0fff0000
2558 
2559 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff
2560 
2561 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_RESET 0x1
2562 
2563 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_GET(value) (((value) & 0x0fff0000) >> 16)
2564 
2565 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET(value) (((value) << 16) & 0x0fff0000)
2566 
2581 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_LSB 28
2582 
2583 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_MSB 28
2584 
2585 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_WIDTH 1
2586 
2587 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET_MSK 0x10000000
2588 
2589 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff
2590 
2591 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_RESET 0x0
2592 
2593 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_GET(value) (((value) & 0x10000000) >> 28)
2594 
2595 #define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET(value) (((value) << 28) & 0x10000000)
2596 
2597 #ifndef __ASSEMBLY__
2598 
2609 {
2610  uint32_t bgpwrdn : 1;
2611  uint32_t pwrdn : 1;
2612  uint32_t en : 1;
2613  uint32_t outresetall : 1;
2614  uint32_t regextsel : 1;
2615  uint32_t fasten : 1;
2616  uint32_t saten : 1;
2617  uint32_t : 1;
2618  uint32_t psrc : 2;
2619  uint32_t : 6;
2620  uint32_t bwadj : 12;
2621  uint32_t bwadjen : 1;
2622  uint32_t : 3;
2623 };
2624 
2627 #endif /* __ASSEMBLY__ */
2628 
2630 #define ALT_CLKMGR_MAINPLL_VCO0_RESET 0x00010043
2631 
2632 #define ALT_CLKMGR_MAINPLL_VCO0_OFST 0x0
2633 
2662 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_LSB 0
2663 
2664 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_MSB 12
2665 
2666 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_WIDTH 13
2667 
2668 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_SET_MSK 0x00001fff
2669 
2670 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_CLR_MSK 0xffffe000
2671 
2672 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_RESET 0x1
2673 
2674 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_GET(value) (((value) & 0x00001fff) >> 0)
2675 
2676 #define ALT_CLKMGR_MAINPLL_VCO1_NUMER_SET(value) (((value) << 0) & 0x00001fff)
2677 
2690 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
2691 
2692 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_MSB 21
2693 
2694 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_WIDTH 6
2695 
2696 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_SET_MSK 0x003f0000
2697 
2698 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_CLR_MSK 0xffc0ffff
2699 
2700 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_RESET 0x1
2701 
2702 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
2703 
2704 #define ALT_CLKMGR_MAINPLL_VCO1_DENOM_SET(value) (((value) << 16) & 0x003f0000)
2705 
2706 #ifndef __ASSEMBLY__
2707 
2718 {
2719  uint32_t numer : 13;
2720  uint32_t : 3;
2721  uint32_t denom : 6;
2722  uint32_t : 10;
2723 };
2724 
2727 #endif /* __ASSEMBLY__ */
2728 
2730 #define ALT_CLKMGR_MAINPLL_VCO1_RESET 0x00010001
2731 
2732 #define ALT_CLKMGR_MAINPLL_VCO1_OFST 0x4
2733 
2767 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_LSB 0
2768 
2769 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_MSB 0
2770 
2771 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_WIDTH 1
2772 
2773 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET_MSK 0x00000001
2774 
2775 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_CLR_MSK 0xfffffffe
2776 
2777 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_RESET 0x1
2778 
2779 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
2780 
2781 #define ALT_CLKMGR_MAINPLL_EN_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
2782 
2792 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_LSB 1
2793 
2794 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_MSB 1
2795 
2796 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_WIDTH 1
2797 
2798 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET_MSK 0x00000002
2799 
2800 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_CLR_MSK 0xfffffffd
2801 
2802 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_RESET 0x1
2803 
2804 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
2805 
2806 #define ALT_CLKMGR_MAINPLL_EN_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
2807 
2817 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_LSB 2
2818 
2819 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_MSB 2
2820 
2821 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_WIDTH 1
2822 
2823 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET_MSK 0x00000004
2824 
2825 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_CLR_MSK 0xfffffffb
2826 
2827 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_RESET 0x1
2828 
2829 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
2830 
2831 #define ALT_CLKMGR_MAINPLL_EN_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
2832 
2842 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_LSB 3
2843 
2844 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_MSB 3
2845 
2846 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_WIDTH 1
2847 
2848 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET_MSK 0x00000008
2849 
2850 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_CLR_MSK 0xfffffff7
2851 
2852 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_RESET 0x1
2853 
2854 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
2855 
2856 #define ALT_CLKMGR_MAINPLL_EN_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
2857 
2867 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_LSB 4
2868 
2869 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_MSB 4
2870 
2871 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_WIDTH 1
2872 
2873 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET_MSK 0x00000010
2874 
2875 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_CLR_MSK 0xffffffef
2876 
2877 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_RESET 0x1
2878 
2879 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
2880 
2881 #define ALT_CLKMGR_MAINPLL_EN_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
2882 
2892 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_LSB 5
2893 
2894 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_MSB 5
2895 
2896 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_WIDTH 1
2897 
2898 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_SET_MSK 0x00000020
2899 
2900 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_CLR_MSK 0xffffffdf
2901 
2902 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_RESET 0x1
2903 
2904 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
2905 
2906 #define ALT_CLKMGR_MAINPLL_EN_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
2907 
2917 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_LSB 6
2918 
2919 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_MSB 6
2920 
2921 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_WIDTH 1
2922 
2923 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK 0x00000040
2924 
2925 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
2926 
2927 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_RESET 0x1
2928 
2929 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
2930 
2931 #define ALT_CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
2932 
2942 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_LSB 7
2943 
2944 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_MSB 7
2945 
2946 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_WIDTH 1
2947 
2948 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK 0x00000080
2949 
2950 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
2951 
2952 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_RESET 0x1
2953 
2954 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
2955 
2956 #define ALT_CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
2957 
2958 #ifndef __ASSEMBLY__
2959 
2970 {
2971  uint32_t mpuclken : 1;
2972  uint32_t l4mainclken : 1;
2973  uint32_t l4mpclken : 1;
2974  uint32_t l4spclken : 1;
2975  uint32_t csclken : 1;
2976  uint32_t cstimerclken : 1;
2977  uint32_t s2fuser0clken : 1;
2978  uint32_t hmcpllrefclken : 1;
2979  uint32_t : 24;
2980 };
2981 
2984 #endif /* __ASSEMBLY__ */
2985 
2987 #define ALT_CLKMGR_MAINPLL_EN_RESET 0x000000ff
2988 
2989 #define ALT_CLKMGR_MAINPLL_EN_OFST 0x8
2990 
3020 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_LSB 0
3021 
3022 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_MSB 0
3023 
3024 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_WIDTH 1
3025 
3026 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET_MSK 0x00000001
3027 
3028 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_CLR_MSK 0xfffffffe
3029 
3030 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_RESET 0x1
3031 
3032 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
3033 
3034 #define ALT_CLKMGR_MAINPLL_ENS_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
3035 
3045 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_LSB 1
3046 
3047 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_MSB 1
3048 
3049 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_WIDTH 1
3050 
3051 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET_MSK 0x00000002
3052 
3053 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_CLR_MSK 0xfffffffd
3054 
3055 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_RESET 0x1
3056 
3057 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
3058 
3059 #define ALT_CLKMGR_MAINPLL_ENS_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
3060 
3070 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_LSB 2
3071 
3072 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_MSB 2
3073 
3074 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_WIDTH 1
3075 
3076 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET_MSK 0x00000004
3077 
3078 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_CLR_MSK 0xfffffffb
3079 
3080 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_RESET 0x1
3081 
3082 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
3083 
3084 #define ALT_CLKMGR_MAINPLL_ENS_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
3085 
3095 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_LSB 3
3096 
3097 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_MSB 3
3098 
3099 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_WIDTH 1
3100 
3101 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET_MSK 0x00000008
3102 
3103 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_CLR_MSK 0xfffffff7
3104 
3105 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_RESET 0x1
3106 
3107 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
3108 
3109 #define ALT_CLKMGR_MAINPLL_ENS_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
3110 
3120 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_LSB 4
3121 
3122 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_MSB 4
3123 
3124 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_WIDTH 1
3125 
3126 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET_MSK 0x00000010
3127 
3128 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_CLR_MSK 0xffffffef
3129 
3130 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_RESET 0x1
3131 
3132 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
3133 
3134 #define ALT_CLKMGR_MAINPLL_ENS_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
3135 
3145 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_LSB 5
3146 
3147 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_MSB 5
3148 
3149 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_WIDTH 1
3150 
3151 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_SET_MSK 0x00000020
3152 
3153 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_CLR_MSK 0xffffffdf
3154 
3155 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_RESET 0x1
3156 
3157 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
3158 
3159 #define ALT_CLKMGR_MAINPLL_ENS_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
3160 
3170 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_LSB 6
3171 
3172 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_MSB 6
3173 
3174 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_WIDTH 1
3175 
3176 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET_MSK 0x00000040
3177 
3178 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
3179 
3180 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_RESET 0x1
3181 
3182 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
3183 
3184 #define ALT_CLKMGR_MAINPLL_ENS_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
3185 
3195 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_LSB 7
3196 
3197 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_MSB 7
3198 
3199 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_WIDTH 1
3200 
3201 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_SET_MSK 0x00000080
3202 
3203 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
3204 
3205 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_RESET 0x1
3206 
3207 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
3208 
3209 #define ALT_CLKMGR_MAINPLL_ENS_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
3210 
3211 #ifndef __ASSEMBLY__
3212 
3223 {
3224  uint32_t mpuclken : 1;
3225  uint32_t l4mainclken : 1;
3226  uint32_t l4mpclken : 1;
3227  uint32_t l4spclken : 1;
3228  uint32_t csclken : 1;
3229  uint32_t cstimerclken : 1;
3230  uint32_t s2fuser0clken : 1;
3231  uint32_t hmcpllrefclken : 1;
3232  uint32_t : 24;
3233 };
3234 
3237 #endif /* __ASSEMBLY__ */
3238 
3240 #define ALT_CLKMGR_MAINPLL_ENS_RESET 0x000000ff
3241 
3242 #define ALT_CLKMGR_MAINPLL_ENS_OFST 0xc
3243 
3273 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_LSB 0
3274 
3275 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_MSB 0
3276 
3277 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_WIDTH 1
3278 
3279 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET_MSK 0x00000001
3280 
3281 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_CLR_MSK 0xfffffffe
3282 
3283 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_RESET 0x1
3284 
3285 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_GET(value) (((value) & 0x00000001) >> 0)
3286 
3287 #define ALT_CLKMGR_MAINPLL_ENR_MPUCLKEN_SET(value) (((value) << 0) & 0x00000001)
3288 
3298 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_LSB 1
3299 
3300 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_MSB 1
3301 
3302 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_WIDTH 1
3303 
3304 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET_MSK 0x00000002
3305 
3306 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_CLR_MSK 0xfffffffd
3307 
3308 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_RESET 0x1
3309 
3310 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_GET(value) (((value) & 0x00000002) >> 1)
3311 
3312 #define ALT_CLKMGR_MAINPLL_ENR_L4MAINCLKEN_SET(value) (((value) << 1) & 0x00000002)
3313 
3323 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_LSB 2
3324 
3325 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_MSB 2
3326 
3327 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_WIDTH 1
3328 
3329 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET_MSK 0x00000004
3330 
3331 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_CLR_MSK 0xfffffffb
3332 
3333 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_RESET 0x1
3334 
3335 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_GET(value) (((value) & 0x00000004) >> 2)
3336 
3337 #define ALT_CLKMGR_MAINPLL_ENR_L4MPCLKEN_SET(value) (((value) << 2) & 0x00000004)
3338 
3348 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_LSB 3
3349 
3350 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_MSB 3
3351 
3352 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_WIDTH 1
3353 
3354 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET_MSK 0x00000008
3355 
3356 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_CLR_MSK 0xfffffff7
3357 
3358 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_RESET 0x1
3359 
3360 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_GET(value) (((value) & 0x00000008) >> 3)
3361 
3362 #define ALT_CLKMGR_MAINPLL_ENR_L4SPCLKEN_SET(value) (((value) << 3) & 0x00000008)
3363 
3373 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_LSB 4
3374 
3375 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_MSB 4
3376 
3377 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_WIDTH 1
3378 
3379 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET_MSK 0x00000010
3380 
3381 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_CLR_MSK 0xffffffef
3382 
3383 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_RESET 0x1
3384 
3385 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_GET(value) (((value) & 0x00000010) >> 4)
3386 
3387 #define ALT_CLKMGR_MAINPLL_ENR_CSCLKEN_SET(value) (((value) << 4) & 0x00000010)
3388 
3398 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_LSB 5
3399 
3400 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_MSB 5
3401 
3402 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_WIDTH 1
3403 
3404 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET_MSK 0x00000020
3405 
3406 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_CLR_MSK 0xffffffdf
3407 
3408 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_RESET 0x1
3409 
3410 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_GET(value) (((value) & 0x00000020) >> 5)
3411 
3412 #define ALT_CLKMGR_MAINPLL_ENR_CSTMRCLKEN_SET(value) (((value) << 5) & 0x00000020)
3413 
3423 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_LSB 6
3424 
3425 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_MSB 6
3426 
3427 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_WIDTH 1
3428 
3429 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET_MSK 0x00000040
3430 
3431 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_CLR_MSK 0xffffffbf
3432 
3433 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_RESET 0x1
3434 
3435 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_GET(value) (((value) & 0x00000040) >> 6)
3436 
3437 #define ALT_CLKMGR_MAINPLL_ENR_S2FUSER0CLKEN_SET(value) (((value) << 6) & 0x00000040)
3438 
3448 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_LSB 7
3449 
3450 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_MSB 7
3451 
3452 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_WIDTH 1
3453 
3454 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET_MSK 0x00000080
3455 
3456 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_CLR_MSK 0xffffff7f
3457 
3458 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_RESET 0x1
3459 
3460 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_GET(value) (((value) & 0x00000080) >> 7)
3461 
3462 #define ALT_CLKMGR_MAINPLL_ENR_HMCPLLREFCLKEN_SET(value) (((value) << 7) & 0x00000080)
3463 
3464 #ifndef __ASSEMBLY__
3465 
3476 {
3477  uint32_t mpuclken : 1;
3478  uint32_t l4mainclken : 1;
3479  uint32_t l4mpclken : 1;
3480  uint32_t l4spclken : 1;
3481  uint32_t csclken : 1;
3482  uint32_t cstimerclken : 1;
3483  uint32_t s2fuser0clken : 1;
3484  uint32_t hmcpllrefclken : 1;
3485  uint32_t : 24;
3486 };
3487 
3490 #endif /* __ASSEMBLY__ */
3491 
3493 #define ALT_CLKMGR_MAINPLL_ENR_RESET 0x000000ff
3494 
3495 #define ALT_CLKMGR_MAINPLL_ENR_OFST 0x10
3496 
3528 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_LSB 0
3529 
3530 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_MSB 0
3531 
3532 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_WIDTH 1
3533 
3534 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET_MSK 0x00000001
3535 
3536 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_CLR_MSK 0xfffffffe
3537 
3538 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_RESET 0x1
3539 
3540 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3541 
3542 #define ALT_CLKMGR_MAINPLL_BYPASS_MPU_SET(value) (((value) << 0) & 0x00000001)
3543 
3553 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_LSB 1
3554 
3555 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_MSB 1
3556 
3557 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_WIDTH 1
3558 
3559 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET_MSK 0x00000002
3560 
3561 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_CLR_MSK 0xfffffffd
3562 
3563 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_RESET 0x1
3564 
3565 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_GET(value) (((value) & 0x00000002) >> 1)
3566 
3567 #define ALT_CLKMGR_MAINPLL_BYPASS_NOC_SET(value) (((value) << 1) & 0x00000002)
3568 
3578 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_LSB 2
3579 
3580 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_MSB 2
3581 
3582 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_WIDTH 1
3583 
3584 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET_MSK 0x00000004
3585 
3586 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_CLR_MSK 0xfffffffb
3587 
3588 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_RESET 0x1
3589 
3590 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
3591 
3592 #define ALT_CLKMGR_MAINPLL_BYPASS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
3593 
3603 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_LSB 3
3604 
3605 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_MSB 3
3606 
3607 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_WIDTH 1
3608 
3609 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_SET_MSK 0x00000008
3610 
3611 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_CLR_MSK 0xfffffff7
3612 
3613 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_RESET 0x1
3614 
3615 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
3616 
3617 #define ALT_CLKMGR_MAINPLL_BYPASS_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
3618 
3630 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_LSB 4
3631 
3632 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_MSB 4
3633 
3634 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_WIDTH 1
3635 
3636 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_SET_MSK 0x00000010
3637 
3638 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_CLR_MSK 0xffffffef
3639 
3640 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_RESET 0x1
3641 
3642 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_GET(value) (((value) & 0x00000010) >> 4)
3643 
3644 #define ALT_CLKMGR_MAINPLL_BYPASS_RFEN_SET(value) (((value) << 4) & 0x00000010)
3645 
3656 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_LSB 5
3657 
3658 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_MSB 5
3659 
3660 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_WIDTH 1
3661 
3662 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_SET_MSK 0x00000020
3663 
3664 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_CLR_MSK 0xffffffdf
3665 
3666 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_RESET 0x1
3667 
3668 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_GET(value) (((value) & 0x00000020) >> 5)
3669 
3670 #define ALT_CLKMGR_MAINPLL_BYPASS_FBEN_SET(value) (((value) << 5) & 0x00000020)
3671 
3672 #ifndef __ASSEMBLY__
3673 
3684 {
3685  uint32_t mpu : 1;
3686  uint32_t noc : 1;
3687  uint32_t s2fuser0 : 1;
3688  uint32_t hmcpllref : 1;
3689  uint32_t rfen : 1;
3690  uint32_t fben : 1;
3691  uint32_t : 26;
3692 };
3693 
3696 #endif /* __ASSEMBLY__ */
3697 
3699 #define ALT_CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
3700 
3701 #define ALT_CLKMGR_MAINPLL_BYPASS_OFST 0x14
3702 
3731 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_LSB 0
3732 
3733 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_MSB 0
3734 
3735 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_WIDTH 1
3736 
3737 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET_MSK 0x00000001
3738 
3739 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_CLR_MSK 0xfffffffe
3740 
3741 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_RESET 0x1
3742 
3743 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_GET(value) (((value) & 0x00000001) >> 0)
3744 
3745 #define ALT_CLKMGR_MAINPLL_BYPASSS_MPU_SET(value) (((value) << 0) & 0x00000001)
3746 
3757 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_LSB 1
3758 
3759 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_MSB 1
3760 
3761 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_WIDTH 1
3762 
3763 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET_MSK 0x00000002
3764 
3765 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_CLR_MSK 0xfffffffd
3766 
3767 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_RESET 0x1
3768 
3769 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_GET(value) (((value) & 0x00000002) >> 1)
3770 
3771 #define ALT_CLKMGR_MAINPLL_BYPASSS_NOC_SET(value) (((value) << 1) & 0x00000002)
3772 
3783 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_LSB 2
3784 
3785 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_MSB 2
3786 
3787 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_WIDTH 1
3788 
3789 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET_MSK 0x00000004
3790 
3791 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_CLR_MSK 0xfffffffb
3792 
3793 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_RESET 0x1
3794 
3795 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
3796 
3797 #define ALT_CLKMGR_MAINPLL_BYPASSS_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
3798 
3808 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_LSB 3
3809 
3810 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_MSB 3
3811 
3812 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_WIDTH 1
3813 
3814 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_SET_MSK 0x00000008
3815 
3816 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_CLR_MSK 0xfffffff7
3817 
3818 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_RESET 0x1
3819 
3820 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
3821 
3822 #define ALT_CLKMGR_MAINPLL_BYPASSS_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
3823 
3835 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_LSB 4
3836 
3837 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_MSB 4
3838 
3839 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_WIDTH 1
3840 
3841 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_SET_MSK 0x00000010
3842 
3843 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_CLR_MSK 0xffffffef
3844 
3845 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_RESET 0x1
3846 
3847 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_GET(value) (((value) & 0x00000010) >> 4)
3848 
3849 #define ALT_CLKMGR_MAINPLL_BYPASSS_RFEN_SET(value) (((value) << 4) & 0x00000010)
3850 
3861 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_LSB 5
3862 
3863 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_MSB 5
3864 
3865 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_WIDTH 1
3866 
3867 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_SET_MSK 0x00000020
3868 
3869 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_CLR_MSK 0xffffffdf
3870 
3871 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_RESET 0x1
3872 
3873 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_GET(value) (((value) & 0x00000020) >> 5)
3874 
3875 #define ALT_CLKMGR_MAINPLL_BYPASSS_FBEN_SET(value) (((value) << 5) & 0x00000020)
3876 
3877 #ifndef __ASSEMBLY__
3878 
3889 {
3890  uint32_t mpu : 1;
3891  uint32_t noc : 1;
3892  uint32_t s2fuser0 : 1;
3893  uint32_t hmcpllref : 1;
3894  uint32_t rfen : 1;
3895  uint32_t fben : 1;
3896  uint32_t : 26;
3897 };
3898 
3901 #endif /* __ASSEMBLY__ */
3902 
3904 #define ALT_CLKMGR_MAINPLL_BYPASSS_RESET 0x0000003f
3905 
3906 #define ALT_CLKMGR_MAINPLL_BYPASSS_OFST 0x18
3907 
3936 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_LSB 0
3937 
3938 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_MSB 0
3939 
3940 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_WIDTH 1
3941 
3942 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET_MSK 0x00000001
3943 
3944 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_CLR_MSK 0xfffffffe
3945 
3946 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_RESET 0x1
3947 
3948 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_GET(value) (((value) & 0x00000001) >> 0)
3949 
3950 #define ALT_CLKMGR_MAINPLL_BYPASSR_MPU_SET(value) (((value) << 0) & 0x00000001)
3951 
3962 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_LSB 1
3963 
3964 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_MSB 1
3965 
3966 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_WIDTH 1
3967 
3968 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET_MSK 0x00000002
3969 
3970 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_CLR_MSK 0xfffffffd
3971 
3972 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_RESET 0x1
3973 
3974 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_GET(value) (((value) & 0x00000002) >> 1)
3975 
3976 #define ALT_CLKMGR_MAINPLL_BYPASSR_NOC_SET(value) (((value) << 1) & 0x00000002)
3977 
3988 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_LSB 2
3989 
3990 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_MSB 2
3991 
3992 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_WIDTH 1
3993 
3994 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET_MSK 0x00000004
3995 
3996 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_CLR_MSK 0xfffffffb
3997 
3998 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_RESET 0x1
3999 
4000 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_GET(value) (((value) & 0x00000004) >> 2)
4001 
4002 #define ALT_CLKMGR_MAINPLL_BYPASSR_S2FUSER0_SET(value) (((value) << 2) & 0x00000004)
4003 
4013 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_LSB 3
4014 
4015 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_MSB 3
4016 
4017 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_WIDTH 1
4018 
4019 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET_MSK 0x00000008
4020 
4021 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_CLR_MSK 0xfffffff7
4022 
4023 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_RESET 0x1
4024 
4025 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_GET(value) (((value) & 0x00000008) >> 3)
4026 
4027 #define ALT_CLKMGR_MAINPLL_BYPASSR_HMCPLLREF_SET(value) (((value) << 3) & 0x00000008)
4028 
4040 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_LSB 4
4041 
4042 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_MSB 4
4043 
4044 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_WIDTH 1
4045 
4046 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET_MSK 0x00000010
4047 
4048 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_CLR_MSK 0xffffffef
4049 
4050 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_RESET 0x1
4051 
4052 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_GET(value) (((value) & 0x00000010) >> 4)
4053 
4054 #define ALT_CLKMGR_MAINPLL_BYPASSR_RFEN_SET(value) (((value) << 4) & 0x00000010)
4055 
4066 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_LSB 5
4067 
4068 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_MSB 5
4069 
4070 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_WIDTH 1
4071 
4072 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET_MSK 0x00000020
4073 
4074 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_CLR_MSK 0xffffffdf
4075 
4076 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_RESET 0x1
4077 
4078 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_GET(value) (((value) & 0x00000020) >> 5)
4079 
4080 #define ALT_CLKMGR_MAINPLL_BYPASSR_FBEN_SET(value) (((value) << 5) & 0x00000020)
4081 
4082 #ifndef __ASSEMBLY__
4083 
4094 {
4095  uint32_t mpu : 1;
4096  uint32_t noc : 1;
4097  uint32_t s2fuser0 : 1;
4098  uint32_t hmcpllref : 1;
4099  uint32_t rfen : 1;
4100  uint32_t fben : 1;
4101  uint32_t : 26;
4102 };
4103 
4106 #endif /* __ASSEMBLY__ */
4107 
4109 #define ALT_CLKMGR_MAINPLL_BYPASSR_RESET 0x0000003f
4110 
4111 #define ALT_CLKMGR_MAINPLL_BYPASSR_OFST 0x1c
4112 
4138 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_LSB 0
4139 
4140 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_MSB 10
4141 
4142 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_WIDTH 11
4143 
4144 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET_MSK 0x000007ff
4145 
4146 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_CLR_MSK 0xfffff800
4147 
4148 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_RESET 0x0
4149 
4150 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4151 
4152 #define ALT_CLKMGR_MAINPLL_MPUCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4153 
4177 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_MAIN 0x0
4178 
4182 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_PERI 0x1
4183 
4187 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_OSC1 0x2
4188 
4192 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_INTOSC 0x3
4193 
4197 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_E_FPGA 0x4
4198 
4200 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
4201 
4202 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_MSB 18
4203 
4204 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_WIDTH 3
4205 
4206 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET_MSK 0x00070000
4207 
4208 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_CLR_MSK 0xfff8ffff
4209 
4210 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_RESET 0x0
4211 
4212 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4213 
4214 #define ALT_CLKMGR_MAINPLL_MPUCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4215 
4216 #ifndef __ASSEMBLY__
4217 
4228 {
4229  uint32_t cnt : 11;
4230  uint32_t : 5;
4231  uint32_t src : 3;
4232  uint32_t : 13;
4233 };
4234 
4237 #endif /* __ASSEMBLY__ */
4238 
4240 #define ALT_CLKMGR_MAINPLL_MPUCLK_RESET 0x00000000
4241 
4242 #define ALT_CLKMGR_MAINPLL_MPUCLK_OFST 0x20
4243 
4269 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_LSB 0
4270 
4271 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_MSB 10
4272 
4273 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_WIDTH 11
4274 
4275 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET_MSK 0x000007ff
4276 
4277 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_CLR_MSK 0xfffff800
4278 
4279 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_RESET 0x0
4280 
4281 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4282 
4283 #define ALT_CLKMGR_MAINPLL_NOCCLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4284 
4308 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_MAIN 0x0
4309 
4313 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_PERI 0x1
4314 
4318 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_OSC1 0x2
4319 
4323 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_INTOSC 0x3
4324 
4328 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_E_FPGA 0x4
4329 
4331 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
4332 
4333 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_MSB 18
4334 
4335 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_WIDTH 3
4336 
4337 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET_MSK 0x00070000
4338 
4339 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_CLR_MSK 0xfff8ffff
4340 
4341 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_RESET 0x0
4342 
4343 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4344 
4345 #define ALT_CLKMGR_MAINPLL_NOCCLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4346 
4347 #ifndef __ASSEMBLY__
4348 
4359 {
4360  uint32_t cnt : 11;
4361  uint32_t : 5;
4362  uint32_t src : 3;
4363  uint32_t : 13;
4364 };
4365 
4368 #endif /* __ASSEMBLY__ */
4369 
4371 #define ALT_CLKMGR_MAINPLL_NOCCLK_RESET 0x00000000
4372 
4373 #define ALT_CLKMGR_MAINPLL_NOCCLK_OFST 0x24
4374 
4398 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_LSB 0
4399 
4400 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_MSB 10
4401 
4402 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_WIDTH 11
4403 
4404 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
4405 
4406 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
4407 
4408 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_RESET 0x0
4409 
4410 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4411 
4412 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4413 
4414 #ifndef __ASSEMBLY__
4415 
4426 {
4427  uint32_t cnt : 11;
4428  uint32_t : 21;
4429 };
4430 
4433 #endif /* __ASSEMBLY__ */
4434 
4436 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_RESET 0x00000000
4437 
4438 #define ALT_CLKMGR_MAINPLL_CNTR2CLK_OFST 0x28
4439 
4463 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_LSB 0
4464 
4465 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_MSB 10
4466 
4467 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_WIDTH 11
4468 
4469 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
4470 
4471 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
4472 
4473 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_RESET 0x0
4474 
4475 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4476 
4477 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4478 
4479 #ifndef __ASSEMBLY__
4480 
4491 {
4492  uint32_t cnt : 11;
4493  uint32_t : 21;
4494 };
4495 
4498 #endif /* __ASSEMBLY__ */
4499 
4501 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_RESET 0x00000000
4502 
4503 #define ALT_CLKMGR_MAINPLL_CNTR3CLK_OFST 0x2c
4504 
4528 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_LSB 0
4529 
4530 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_MSB 10
4531 
4532 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_WIDTH 11
4533 
4534 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
4535 
4536 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
4537 
4538 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_RESET 0x0
4539 
4540 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4541 
4542 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4543 
4544 #ifndef __ASSEMBLY__
4545 
4556 {
4557  uint32_t cnt : 11;
4558  uint32_t : 21;
4559 };
4560 
4563 #endif /* __ASSEMBLY__ */
4564 
4566 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_RESET 0x00000000
4567 
4568 #define ALT_CLKMGR_MAINPLL_CNTR4CLK_OFST 0x30
4569 
4593 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_LSB 0
4594 
4595 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_MSB 10
4596 
4597 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_WIDTH 11
4598 
4599 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
4600 
4601 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
4602 
4603 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_RESET 0x0
4604 
4605 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4606 
4607 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4608 
4609 #ifndef __ASSEMBLY__
4610 
4621 {
4622  uint32_t cnt : 11;
4623  uint32_t : 21;
4624 };
4625 
4628 #endif /* __ASSEMBLY__ */
4629 
4631 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_RESET 0x00000000
4632 
4633 #define ALT_CLKMGR_MAINPLL_CNTR5CLK_OFST 0x34
4634 
4658 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_LSB 0
4659 
4660 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_MSB 10
4661 
4662 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_WIDTH 11
4663 
4664 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
4665 
4666 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
4667 
4668 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_RESET 0x0
4669 
4670 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4671 
4672 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4673 
4674 #ifndef __ASSEMBLY__
4675 
4686 {
4687  uint32_t cnt : 11;
4688  uint32_t : 21;
4689 };
4690 
4693 #endif /* __ASSEMBLY__ */
4694 
4696 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_RESET 0x00000000
4697 
4698 #define ALT_CLKMGR_MAINPLL_CNTR6CLK_OFST 0x38
4699 
4725 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_LSB 0
4726 
4727 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_MSB 10
4728 
4729 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_WIDTH 11
4730 
4731 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
4732 
4733 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
4734 
4735 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_RESET 0x0
4736 
4737 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4738 
4739 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4740 
4764 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_MAIN 0x0
4765 
4769 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_PERI 0x1
4770 
4774 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_OSC1 0x2
4775 
4779 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_INTOSC 0x3
4780 
4784 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_E_FPGA 0x4
4785 
4787 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
4788 
4789 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_MSB 18
4790 
4791 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_WIDTH 3
4792 
4793 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET_MSK 0x00070000
4794 
4795 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_CLR_MSK 0xfff8ffff
4796 
4797 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_RESET 0x0
4798 
4799 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4800 
4801 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4802 
4803 #ifndef __ASSEMBLY__
4804 
4815 {
4816  uint32_t cnt : 11;
4817  uint32_t : 5;
4818  uint32_t src : 3;
4819  uint32_t : 13;
4820 };
4821 
4824 #endif /* __ASSEMBLY__ */
4825 
4827 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_RESET 0x00000000
4828 
4829 #define ALT_CLKMGR_MAINPLL_CNTR7CLK_OFST 0x3c
4830 
4854 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_LSB 0
4855 
4856 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_MSB 10
4857 
4858 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_WIDTH 11
4859 
4860 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
4861 
4862 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
4863 
4864 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_RESET 0x0
4865 
4866 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4867 
4868 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4869 
4870 #ifndef __ASSEMBLY__
4871 
4882 {
4883  uint32_t cnt : 11;
4884  uint32_t : 21;
4885 };
4886 
4889 #endif /* __ASSEMBLY__ */
4890 
4892 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_RESET 0x00000000
4893 
4894 #define ALT_CLKMGR_MAINPLL_CNTR8CLK_OFST 0x40
4895 
4921 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_LSB 0
4922 
4923 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_MSB 10
4924 
4925 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_WIDTH 11
4926 
4927 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
4928 
4929 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
4930 
4931 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_RESET 0x0
4932 
4933 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
4934 
4935 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
4936 
4960 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_MAIN 0x0
4961 
4965 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_PERI 0x1
4966 
4970 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_OSC1 0x2
4971 
4975 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_INTOSC 0x3
4976 
4980 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_E_FPGA 0x4
4981 
4983 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
4984 
4985 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_MSB 18
4986 
4987 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_WIDTH 3
4988 
4989 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_SET_MSK 0x00070000
4990 
4991 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_CLR_MSK 0xfff8ffff
4992 
4993 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_RESET 0x0
4994 
4995 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
4996 
4997 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
4998 
4999 #ifndef __ASSEMBLY__
5000 
5011 {
5012  uint32_t cnt : 11;
5013  uint32_t : 5;
5014  uint32_t src : 3;
5015  uint32_t : 13;
5016 };
5017 
5020 #endif /* __ASSEMBLY__ */
5021 
5023 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_RESET 0x00000000
5024 
5025 #define ALT_CLKMGR_MAINPLL_CNTR9CLK_OFST 0x44
5026 
5050 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_LSB 0
5051 
5052 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_MSB 10
5053 
5054 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_WIDTH 11
5055 
5056 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_SET_MSK 0x000007ff
5057 
5058 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_CLR_MSK 0xfffff800
5059 
5060 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_RESET 0x0
5061 
5062 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
5063 
5064 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
5065 
5066 #ifndef __ASSEMBLY__
5067 
5078 {
5079  uint32_t cnt : 11;
5080  uint32_t : 21;
5081 };
5082 
5085 #endif /* __ASSEMBLY__ */
5086 
5088 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_RESET 0x00000000
5089 
5090 #define ALT_CLKMGR_MAINPLL_CNTR15CLK_OFST 0x5c
5091 
5130 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_LSB 0
5131 
5132 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_MSB 15
5133 
5134 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_WIDTH 16
5135 
5136 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_SET_MSK 0x0000ffff
5137 
5138 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_CLR_MSK 0xffff0000
5139 
5140 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_RESET 0x0
5141 
5142 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_GET(value) (((value) & 0x0000ffff) >> 0)
5143 
5144 #define ALT_CLKMGR_MAINPLL_OUTRST_OUTRST_SET(value) (((value) << 0) & 0x0000ffff)
5145 
5146 #ifndef __ASSEMBLY__
5147 
5158 {
5159  uint32_t outreset : 16;
5160  uint32_t : 16;
5161 };
5162 
5165 #endif /* __ASSEMBLY__ */
5166 
5168 #define ALT_CLKMGR_MAINPLL_OUTRST_RESET 0x00000000
5169 
5170 #define ALT_CLKMGR_MAINPLL_OUTRST_OFST 0x60
5171 
5217 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE 0x0
5218 
5223 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD 0x1
5224 
5226 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_LSB 0
5227 
5228 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_MSB 15
5229 
5230 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_WIDTH 16
5231 
5232 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_SET_MSK 0x0000ffff
5233 
5234 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_CLR_MSK 0xffff0000
5235 
5236 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_RESET 0x0
5237 
5238 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_GET(value) (((value) & 0x0000ffff) >> 0)
5239 
5240 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000ffff)
5241 
5242 #ifndef __ASSEMBLY__
5243 
5254 {
5255  const uint32_t outresetack : 16;
5256  uint32_t : 16;
5257 };
5258 
5261 #endif /* __ASSEMBLY__ */
5262 
5264 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_RESET 0x00000000
5265 
5266 #define ALT_CLKMGR_MAINPLL_OUTRSTSTAT_OFST 0x64
5267 
5311 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV1 0x0
5312 
5317 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV2 0x1
5318 
5323 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV4 0x2
5324 
5329 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_E_DIV8 0x3
5330 
5332 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
5333 
5334 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_MSB 1
5335 
5336 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_WIDTH 2
5337 
5338 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET_MSK 0x00000003
5339 
5340 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_CLR_MSK 0xfffffffc
5341 
5342 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_RESET 0x0
5343 
5344 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_GET(value) (((value) & 0x00000003) >> 0)
5345 
5346 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_SET(value) (((value) << 0) & 0x00000003)
5347 
5370 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV1 0x0
5371 
5376 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV2 0x1
5377 
5382 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV4 0x2
5383 
5388 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_E_DIV8 0x3
5389 
5391 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
5392 
5393 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_MSB 9
5394 
5395 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_WIDTH 2
5396 
5397 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET_MSK 0x00000300
5398 
5399 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_CLR_MSK 0xfffffcff
5400 
5401 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_RESET 0x1
5402 
5403 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_GET(value) (((value) & 0x00000300) >> 8)
5404 
5405 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4MPCLK_SET(value) (((value) << 8) & 0x00000300)
5406 
5429 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV1 0x0
5430 
5435 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV2 0x1
5436 
5441 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV4 0x2
5442 
5447 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_E_DIV8 0x3
5448 
5450 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
5451 
5452 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_MSB 17
5453 
5454 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_WIDTH 2
5455 
5456 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET_MSK 0x00030000
5457 
5458 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_CLR_MSK 0xfffcffff
5459 
5460 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_RESET 0x2
5461 
5462 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_GET(value) (((value) & 0x00030000) >> 16)
5463 
5464 #define ALT_CLKMGR_MAINPLL_NOCDIV_L4SPCLK_SET(value) (((value) << 16) & 0x00030000)
5465 
5488 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV1 0x0
5489 
5494 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV2 0x1
5495 
5500 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV4 0x2
5501 
5506 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_E_DIV8 0x3
5507 
5509 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
5510 
5511 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_MSB 25
5512 
5513 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_WIDTH 2
5514 
5515 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET_MSK 0x03000000
5516 
5517 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_CLR_MSK 0xfcffffff
5518 
5519 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_RESET 0x0
5520 
5521 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_GET(value) (((value) & 0x03000000) >> 24)
5522 
5523 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSATCLK_SET(value) (((value) << 24) & 0x03000000)
5524 
5549 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV1 0x0
5550 
5555 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV2 0x1
5556 
5561 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV4 0x2
5562 
5567 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_E_DIV8 0x3
5568 
5570 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
5571 
5572 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_MSB 27
5573 
5574 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_WIDTH 2
5575 
5576 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET_MSK 0x0c000000
5577 
5578 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_CLR_MSK 0xf3ffffff
5579 
5580 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_RESET 0x2
5581 
5582 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_GET(value) (((value) & 0x0c000000) >> 26)
5583 
5584 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_SET(value) (((value) << 26) & 0x0c000000)
5585 
5607 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV1 0x0
5608 
5613 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_E_DIV4 0x1
5614 
5616 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
5617 
5618 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_MSB 28
5619 
5620 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_WIDTH 1
5621 
5622 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET_MSK 0x10000000
5623 
5624 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_CLR_MSK 0xefffffff
5625 
5626 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_RESET 0x1
5627 
5628 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_GET(value) (((value) & 0x10000000) >> 28)
5629 
5630 #define ALT_CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_SET(value) (((value) << 28) & 0x10000000)
5631 
5632 #ifndef __ASSEMBLY__
5633 
5644 {
5645  uint32_t l4mainclk : 2;
5646  uint32_t : 6;
5647  uint32_t l4mpclk : 2;
5648  uint32_t : 6;
5649  uint32_t l4spclk : 2;
5650  uint32_t : 6;
5651  uint32_t csatclk : 2;
5652  uint32_t cstraceclk : 2;
5653  uint32_t cspdbgclk : 1;
5654  uint32_t : 3;
5655 };
5656 
5659 #endif /* __ASSEMBLY__ */
5660 
5662 #define ALT_CLKMGR_MAINPLL_NOCDIV_RESET 0x18020100
5663 
5664 #define ALT_CLKMGR_MAINPLL_NOCDIV_OFST 0x68
5665 
5666 #ifndef __ASSEMBLY__
5667 
5678 {
5697  volatile uint32_t _pad_0x48_0x5b[5];
5702  volatile uint32_t _pad_0x6c_0x80[5];
5703 };
5704 
5709 {
5710  volatile uint32_t vco0;
5711  volatile uint32_t vco1;
5712  volatile uint32_t en;
5713  volatile uint32_t ens;
5714  volatile uint32_t enr;
5715  volatile uint32_t bypass;
5716  volatile uint32_t bypasss;
5717  volatile uint32_t bypassr;
5718  volatile uint32_t mpuclk;
5719  volatile uint32_t nocclk;
5720  volatile uint32_t cntr2clk;
5721  volatile uint32_t cntr3clk;
5722  volatile uint32_t cntr4clk;
5723  volatile uint32_t cntr5clk;
5724  volatile uint32_t cntr6clk;
5725  volatile uint32_t cntr7clk;
5726  volatile uint32_t cntr8clk;
5727  volatile uint32_t cntr9clk;
5728  volatile uint32_t _pad_0x48_0x5b[5];
5729  volatile uint32_t cntr15clk;
5730  volatile uint32_t outrst;
5731  volatile uint32_t outrststat;
5732  volatile uint32_t nocdiv;
5733  volatile uint32_t _pad_0x6c_0x80[5];
5734 };
5735 
5738 #endif /* __ASSEMBLY__ */
5739 
5779 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_LSB 0
5780 
5781 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_MSB 0
5782 
5783 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_WIDTH 1
5784 
5785 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK 0x00000001
5786 
5787 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe
5788 
5789 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_RESET 0x1
5790 
5791 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0)
5792 
5793 #define ALT_CLKMGR_PERPLL_VCO0_BGPWRDN_SET(value) (((value) << 0) & 0x00000001)
5794 
5804 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_LSB 1
5805 
5806 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_MSB 1
5807 
5808 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_WIDTH 1
5809 
5810 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK 0x00000002
5811 
5812 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd
5813 
5814 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_RESET 0x1
5815 
5816 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_GET(value) (((value) & 0x00000002) >> 1)
5817 
5818 #define ALT_CLKMGR_PERPLL_VCO0_PWRDN_SET(value) (((value) << 1) & 0x00000002)
5819 
5829 #define ALT_CLKMGR_PERPLL_VCO0_EN_LSB 2
5830 
5831 #define ALT_CLKMGR_PERPLL_VCO0_EN_MSB 2
5832 
5833 #define ALT_CLKMGR_PERPLL_VCO0_EN_WIDTH 1
5834 
5835 #define ALT_CLKMGR_PERPLL_VCO0_EN_SET_MSK 0x00000004
5836 
5837 #define ALT_CLKMGR_PERPLL_VCO0_EN_CLR_MSK 0xfffffffb
5838 
5839 #define ALT_CLKMGR_PERPLL_VCO0_EN_RESET 0x0
5840 
5841 #define ALT_CLKMGR_PERPLL_VCO0_EN_GET(value) (((value) & 0x00000004) >> 2)
5842 
5843 #define ALT_CLKMGR_PERPLL_VCO0_EN_SET(value) (((value) << 2) & 0x00000004)
5844 
5861 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_LSB 3
5862 
5863 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_MSB 3
5864 
5865 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_WIDTH 1
5866 
5867 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008
5868 
5869 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7
5870 
5871 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_RESET 0x0
5872 
5873 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_GET(value) (((value) & 0x00000008) >> 3)
5874 
5875 #define ALT_CLKMGR_PERPLL_VCO0_OUTRSTALL_SET(value) (((value) << 3) & 0x00000008)
5876 
5898 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_LSB 4
5899 
5900 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_MSB 4
5901 
5902 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_WIDTH 1
5903 
5904 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010
5905 
5906 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef
5907 
5908 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_RESET 0x0
5909 
5910 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_GET(value) (((value) & 0x00000010) >> 4)
5911 
5912 #define ALT_CLKMGR_PERPLL_VCO0_REGEXTSEL_SET(value) (((value) << 4) & 0x00000010)
5913 
5923 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_LSB 5
5924 
5925 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_MSB 5
5926 
5927 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_WIDTH 1
5928 
5929 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_SET_MSK 0x00000020
5930 
5931 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf
5932 
5933 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_RESET 0x0
5934 
5935 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_GET(value) (((value) & 0x00000020) >> 5)
5936 
5937 #define ALT_CLKMGR_PERPLL_VCO0_FASTEN_SET(value) (((value) << 5) & 0x00000020)
5938 
5948 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_LSB 6
5949 
5950 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_MSB 6
5951 
5952 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_WIDTH 1
5953 
5954 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_SET_MSK 0x00000040
5955 
5956 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_CLR_MSK 0xffffffbf
5957 
5958 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_RESET 0x1
5959 
5960 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_GET(value) (((value) & 0x00000040) >> 6)
5961 
5962 #define ALT_CLKMGR_PERPLL_VCO0_SATEN_SET(value) (((value) << 6) & 0x00000040)
5963 
5986 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_EOSC1 0x0
5987 
5992 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
5993 
5998 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_F2S 0x2
5999 
6004 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_E_MAIN 0x3
6005 
6007 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_LSB 8
6008 
6009 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_MSB 9
6010 
6011 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_WIDTH 2
6012 
6013 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_SET_MSK 0x00000300
6014 
6015 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_CLR_MSK 0xfffffcff
6016 
6017 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_RESET 0x0
6018 
6019 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_GET(value) (((value) & 0x00000300) >> 8)
6020 
6021 #define ALT_CLKMGR_PERPLL_VCO0_PSRC_SET(value) (((value) << 8) & 0x00000300)
6022 
6032 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_LSB 16
6033 
6034 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_MSB 27
6035 
6036 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_WIDTH 12
6037 
6038 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_SET_MSK 0x0fff0000
6039 
6040 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff
6041 
6042 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_RESET 0x1
6043 
6044 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_GET(value) (((value) & 0x0fff0000) >> 16)
6045 
6046 #define ALT_CLKMGR_PERPLL_VCO0_BWADJ_SET(value) (((value) << 16) & 0x0fff0000)
6047 
6062 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_LSB 28
6063 
6064 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_MSB 28
6065 
6066 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_WIDTH 1
6067 
6068 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_SET_MSK 0x10000000
6069 
6070 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff
6071 
6072 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_RESET 0x0
6073 
6074 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_GET(value) (((value) & 0x10000000) >> 28)
6075 
6076 #define ALT_CLKMGR_PERPLL_VCO0_BWADJEN_SET(value) (((value) << 28) & 0x10000000)
6077 
6078 #ifndef __ASSEMBLY__
6079 
6090 {
6091  uint32_t bgpwrdn : 1;
6092  uint32_t pwrdn : 1;
6093  uint32_t en : 1;
6094  uint32_t outresetall : 1;
6095  uint32_t regextsel : 1;
6096  uint32_t fasten : 1;
6097  uint32_t saten : 1;
6098  uint32_t : 1;
6099  uint32_t psrc : 2;
6100  uint32_t : 6;
6101  uint32_t bwadj : 12;
6102  uint32_t bwadjen : 1;
6103  uint32_t : 3;
6104 };
6105 
6108 #endif /* __ASSEMBLY__ */
6109 
6111 #define ALT_CLKMGR_PERPLL_VCO0_RESET 0x00010043
6112 
6113 #define ALT_CLKMGR_PERPLL_VCO0_OFST 0x0
6114 
6143 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_LSB 0
6144 
6145 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_MSB 12
6146 
6147 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_WIDTH 13
6148 
6149 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_SET_MSK 0x00001fff
6150 
6151 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_CLR_MSK 0xffffe000
6152 
6153 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_RESET 0x1
6154 
6155 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_GET(value) (((value) & 0x00001fff) >> 0)
6156 
6157 #define ALT_CLKMGR_PERPLL_VCO1_NUMER_SET(value) (((value) << 0) & 0x00001fff)
6158 
6171 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_LSB 16
6172 
6173 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_MSB 21
6174 
6175 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_WIDTH 6
6176 
6177 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_SET_MSK 0x003f0000
6178 
6179 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_CLR_MSK 0xffc0ffff
6180 
6181 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_RESET 0x1
6182 
6183 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_GET(value) (((value) & 0x003f0000) >> 16)
6184 
6185 #define ALT_CLKMGR_PERPLL_VCO1_DENOM_SET(value) (((value) << 16) & 0x003f0000)
6186 
6187 #ifndef __ASSEMBLY__
6188 
6199 {
6200  uint32_t numer : 13;
6201  uint32_t : 3;
6202  uint32_t denom : 6;
6203  uint32_t : 10;
6204 };
6205 
6208 #endif /* __ASSEMBLY__ */
6209 
6211 #define ALT_CLKMGR_PERPLL_VCO1_RESET 0x00010001
6212 
6213 #define ALT_CLKMGR_PERPLL_VCO1_OFST 0x4
6214 
6253 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_LSB 0
6254 
6255 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_MSB 0
6256 
6257 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_WIDTH 1
6258 
6259 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET_MSK 0x00000001
6260 
6261 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_CLR_MSK 0xfffffffe
6262 
6263 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_RESET 0x1
6264 
6265 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6266 
6267 #define ALT_CLKMGR_PERPLL_EN_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6268 
6278 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_LSB 1
6279 
6280 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_MSB 1
6281 
6282 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_WIDTH 1
6283 
6284 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET_MSK 0x00000002
6285 
6286 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_CLR_MSK 0xfffffffd
6287 
6288 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_RESET 0x1
6289 
6290 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6291 
6292 #define ALT_CLKMGR_PERPLL_EN_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6293 
6303 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_LSB 2
6304 
6305 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_MSB 2
6306 
6307 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_WIDTH 1
6308 
6309 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET_MSK 0x00000004
6310 
6311 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_CLR_MSK 0xfffffffb
6312 
6313 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_RESET 0x1
6314 
6315 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6316 
6317 #define ALT_CLKMGR_PERPLL_EN_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
6318 
6328 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_LSB 3
6329 
6330 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_MSB 3
6331 
6332 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_WIDTH 1
6333 
6334 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET_MSK 0x00000008
6335 
6336 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_CLR_MSK 0xfffffff7
6337 
6338 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_RESET 0x1
6339 
6340 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
6341 
6342 #define ALT_CLKMGR_PERPLL_EN_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
6343 
6353 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_LSB 4
6354 
6355 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_MSB 4
6356 
6357 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_WIDTH 1
6358 
6359 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET_MSK 0x00000010
6360 
6361 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_CLR_MSK 0xffffffef
6362 
6363 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_RESET 0x1
6364 
6365 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
6366 
6367 #define ALT_CLKMGR_PERPLL_EN_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
6368 
6379 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_LSB 5
6380 
6381 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_MSB 5
6382 
6383 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_WIDTH 1
6384 
6385 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET_MSK 0x00000020
6386 
6387 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_CLR_MSK 0xffffffdf
6388 
6389 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_RESET 0x1
6390 
6391 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
6392 
6393 #define ALT_CLKMGR_PERPLL_EN_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
6394 
6404 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_LSB 6
6405 
6406 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_MSB 6
6407 
6408 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_WIDTH 1
6409 
6410 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET_MSK 0x00000040
6411 
6412 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
6413 
6414 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_RESET 0x1
6415 
6416 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
6417 
6418 #define ALT_CLKMGR_PERPLL_EN_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
6419 
6430 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_LSB 8
6431 
6432 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_MSB 8
6433 
6434 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_WIDTH 1
6435 
6436 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET_MSK 0x00000100
6437 
6438 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_CLR_MSK 0xfffffeff
6439 
6440 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_RESET 0x1
6441 
6442 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
6443 
6444 #define ALT_CLKMGR_PERPLL_EN_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
6445 
6456 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_LSB 9
6457 
6458 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_MSB 9
6459 
6460 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_WIDTH 1
6461 
6462 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET_MSK 0x00000200
6463 
6464 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_CLR_MSK 0xfffffdff
6465 
6466 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_RESET 0x1
6467 
6468 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
6469 
6470 #define ALT_CLKMGR_PERPLL_EN_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
6471 
6482 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_LSB 10
6483 
6484 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_MSB 10
6485 
6486 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_WIDTH 1
6487 
6488 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET_MSK 0x00000400
6489 
6490 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_CLR_MSK 0xfffffbff
6491 
6492 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_RESET 0x1
6493 
6494 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
6495 
6496 #define ALT_CLKMGR_PERPLL_EN_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
6497 
6508 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_LSB 11
6509 
6510 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_MSB 11
6511 
6512 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_WIDTH 1
6513 
6514 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_SET_MSK 0x00000800
6515 
6516 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_CLR_MSK 0xfffff7ff
6517 
6518 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_RESET 0x1
6519 
6520 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
6521 
6522 #define ALT_CLKMGR_PERPLL_EN_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
6523 
6524 #ifndef __ASSEMBLY__
6525 
6536 {
6537  uint32_t emac0en : 1;
6538  uint32_t emac1en : 1;
6539  uint32_t emac2en : 1;
6540  uint32_t emacptpen : 1;
6541  uint32_t gpiodben : 1;
6542  uint32_t sdmmcclken : 1;
6543  uint32_t s2fuser1clken : 1;
6544  uint32_t : 1;
6545  uint32_t usbclken : 1;
6546  uint32_t spimclken : 1;
6547  uint32_t nandclken : 1;
6548  uint32_t qspiclken : 1;
6549  uint32_t : 20;
6550 };
6551 
6554 #endif /* __ASSEMBLY__ */
6555 
6557 #define ALT_CLKMGR_PERPLL_EN_RESET 0x00000f7f
6558 
6559 #define ALT_CLKMGR_PERPLL_EN_OFST 0x8
6560 
6594 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_LSB 0
6595 
6596 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_MSB 0
6597 
6598 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_WIDTH 1
6599 
6600 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET_MSK 0x00000001
6601 
6602 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_CLR_MSK 0xfffffffe
6603 
6604 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_RESET 0x1
6605 
6606 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6607 
6608 #define ALT_CLKMGR_PERPLL_ENS_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6609 
6619 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_LSB 1
6620 
6621 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_MSB 1
6622 
6623 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_WIDTH 1
6624 
6625 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET_MSK 0x00000002
6626 
6627 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_CLR_MSK 0xfffffffd
6628 
6629 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_RESET 0x1
6630 
6631 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6632 
6633 #define ALT_CLKMGR_PERPLL_ENS_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6634 
6644 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_LSB 2
6645 
6646 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_MSB 2
6647 
6648 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_WIDTH 1
6649 
6650 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET_MSK 0x00000004
6651 
6652 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_CLR_MSK 0xfffffffb
6653 
6654 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_RESET 0x1
6655 
6656 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6657 
6658 #define ALT_CLKMGR_PERPLL_ENS_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
6659 
6669 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_LSB 3
6670 
6671 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_MSB 3
6672 
6673 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_WIDTH 1
6674 
6675 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET_MSK 0x00000008
6676 
6677 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_CLR_MSK 0xfffffff7
6678 
6679 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_RESET 0x1
6680 
6681 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
6682 
6683 #define ALT_CLKMGR_PERPLL_ENS_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
6684 
6694 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_LSB 4
6695 
6696 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_MSB 4
6697 
6698 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_WIDTH 1
6699 
6700 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET_MSK 0x00000010
6701 
6702 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_CLR_MSK 0xffffffef
6703 
6704 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_RESET 0x1
6705 
6706 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
6707 
6708 #define ALT_CLKMGR_PERPLL_ENS_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
6709 
6720 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_LSB 5
6721 
6722 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_MSB 5
6723 
6724 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_WIDTH 1
6725 
6726 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET_MSK 0x00000020
6727 
6728 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_CLR_MSK 0xffffffdf
6729 
6730 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_RESET 0x1
6731 
6732 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
6733 
6734 #define ALT_CLKMGR_PERPLL_ENS_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
6735 
6745 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_LSB 6
6746 
6747 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_MSB 6
6748 
6749 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_WIDTH 1
6750 
6751 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET_MSK 0x00000040
6752 
6753 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
6754 
6755 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_RESET 0x1
6756 
6757 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
6758 
6759 #define ALT_CLKMGR_PERPLL_ENS_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
6760 
6771 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_LSB 8
6772 
6773 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_MSB 8
6774 
6775 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_WIDTH 1
6776 
6777 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET_MSK 0x00000100
6778 
6779 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_CLR_MSK 0xfffffeff
6780 
6781 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_RESET 0x1
6782 
6783 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
6784 
6785 #define ALT_CLKMGR_PERPLL_ENS_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
6786 
6797 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_LSB 9
6798 
6799 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_MSB 9
6800 
6801 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_WIDTH 1
6802 
6803 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET_MSK 0x00000200
6804 
6805 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_CLR_MSK 0xfffffdff
6806 
6807 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_RESET 0x1
6808 
6809 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
6810 
6811 #define ALT_CLKMGR_PERPLL_ENS_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
6812 
6823 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_LSB 10
6824 
6825 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_MSB 10
6826 
6827 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_WIDTH 1
6828 
6829 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET_MSK 0x00000400
6830 
6831 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_CLR_MSK 0xfffffbff
6832 
6833 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_RESET 0x1
6834 
6835 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
6836 
6837 #define ALT_CLKMGR_PERPLL_ENS_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
6838 
6849 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_LSB 11
6850 
6851 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_MSB 11
6852 
6853 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_WIDTH 1
6854 
6855 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET_MSK 0x00000800
6856 
6857 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_CLR_MSK 0xfffff7ff
6858 
6859 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_RESET 0x1
6860 
6861 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
6862 
6863 #define ALT_CLKMGR_PERPLL_ENS_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
6864 
6865 #ifndef __ASSEMBLY__
6866 
6877 {
6878  uint32_t emac0en : 1;
6879  uint32_t emac1en : 1;
6880  uint32_t emac2en : 1;
6881  uint32_t emacptpen : 1;
6882  uint32_t gpiodben : 1;
6883  uint32_t sdmmcclken : 1;
6884  uint32_t s2fuser1clken : 1;
6885  uint32_t : 1;
6886  uint32_t usbclken : 1;
6887  uint32_t spimclken : 1;
6888  uint32_t nandclken : 1;
6889  uint32_t qspiclken : 1;
6890  uint32_t : 20;
6891 };
6892 
6895 #endif /* __ASSEMBLY__ */
6896 
6898 #define ALT_CLKMGR_PERPLL_ENS_RESET 0x00000f7f
6899 
6900 #define ALT_CLKMGR_PERPLL_ENS_OFST 0xc
6901 
6935 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_LSB 0
6936 
6937 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_MSB 0
6938 
6939 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_WIDTH 1
6940 
6941 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET_MSK 0x00000001
6942 
6943 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_CLR_MSK 0xfffffffe
6944 
6945 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_RESET 0x1
6946 
6947 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_GET(value) (((value) & 0x00000001) >> 0)
6948 
6949 #define ALT_CLKMGR_PERPLL_ENR_EMAC0EN_SET(value) (((value) << 0) & 0x00000001)
6950 
6960 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_LSB 1
6961 
6962 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_MSB 1
6963 
6964 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_WIDTH 1
6965 
6966 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET_MSK 0x00000002
6967 
6968 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_CLR_MSK 0xfffffffd
6969 
6970 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_RESET 0x1
6971 
6972 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_GET(value) (((value) & 0x00000002) >> 1)
6973 
6974 #define ALT_CLKMGR_PERPLL_ENR_EMAC1EN_SET(value) (((value) << 1) & 0x00000002)
6975 
6985 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_LSB 2
6986 
6987 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_MSB 2
6988 
6989 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_WIDTH 1
6990 
6991 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET_MSK 0x00000004
6992 
6993 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_CLR_MSK 0xfffffffb
6994 
6995 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_RESET 0x1
6996 
6997 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_GET(value) (((value) & 0x00000004) >> 2)
6998 
6999 #define ALT_CLKMGR_PERPLL_ENR_EMAC2EN_SET(value) (((value) << 2) & 0x00000004)
7000 
7010 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_LSB 3
7011 
7012 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_MSB 3
7013 
7014 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_WIDTH 1
7015 
7016 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET_MSK 0x00000008
7017 
7018 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_CLR_MSK 0xfffffff7
7019 
7020 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_RESET 0x1
7021 
7022 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_GET(value) (((value) & 0x00000008) >> 3)
7023 
7024 #define ALT_CLKMGR_PERPLL_ENR_EMACPTPEN_SET(value) (((value) << 3) & 0x00000008)
7025 
7035 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_LSB 4
7036 
7037 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_MSB 4
7038 
7039 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_WIDTH 1
7040 
7041 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET_MSK 0x00000010
7042 
7043 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_CLR_MSK 0xffffffef
7044 
7045 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_RESET 0x1
7046 
7047 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_GET(value) (((value) & 0x00000010) >> 4)
7048 
7049 #define ALT_CLKMGR_PERPLL_ENR_GPIODBEN_SET(value) (((value) << 4) & 0x00000010)
7050 
7061 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_LSB 5
7062 
7063 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_MSB 5
7064 
7065 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_WIDTH 1
7066 
7067 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET_MSK 0x00000020
7068 
7069 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_CLR_MSK 0xffffffdf
7070 
7071 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_RESET 0x1
7072 
7073 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_GET(value) (((value) & 0x00000020) >> 5)
7074 
7075 #define ALT_CLKMGR_PERPLL_ENR_SDMMCCLKEN_SET(value) (((value) << 5) & 0x00000020)
7076 
7086 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_LSB 6
7087 
7088 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_MSB 6
7089 
7090 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_WIDTH 1
7091 
7092 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET_MSK 0x00000040
7093 
7094 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_CLR_MSK 0xffffffbf
7095 
7096 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_RESET 0x1
7097 
7098 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_GET(value) (((value) & 0x00000040) >> 6)
7099 
7100 #define ALT_CLKMGR_PERPLL_ENR_S2FUSER1CLKEN_SET(value) (((value) << 6) & 0x00000040)
7101 
7112 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_LSB 8
7113 
7114 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_MSB 8
7115 
7116 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_WIDTH 1
7117 
7118 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET_MSK 0x00000100
7119 
7120 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_CLR_MSK 0xfffffeff
7121 
7122 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_RESET 0x1
7123 
7124 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_GET(value) (((value) & 0x00000100) >> 8)
7125 
7126 #define ALT_CLKMGR_PERPLL_ENR_USBCLKEN_SET(value) (((value) << 8) & 0x00000100)
7127 
7138 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_LSB 9
7139 
7140 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_MSB 9
7141 
7142 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_WIDTH 1
7143 
7144 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET_MSK 0x00000200
7145 
7146 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_CLR_MSK 0xfffffdff
7147 
7148 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_RESET 0x1
7149 
7150 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_GET(value) (((value) & 0x00000200) >> 9)
7151 
7152 #define ALT_CLKMGR_PERPLL_ENR_SPIMCLKEN_SET(value) (((value) << 9) & 0x00000200)
7153 
7164 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_LSB 10
7165 
7166 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_MSB 10
7167 
7168 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_WIDTH 1
7169 
7170 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET_MSK 0x00000400
7171 
7172 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_CLR_MSK 0xfffffbff
7173 
7174 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_RESET 0x1
7175 
7176 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_GET(value) (((value) & 0x00000400) >> 10)
7177 
7178 #define ALT_CLKMGR_PERPLL_ENR_NANDCLKEN_SET(value) (((value) << 10) & 0x00000400)
7179 
7190 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_LSB 11
7191 
7192 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_MSB 11
7193 
7194 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_WIDTH 1
7195 
7196 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_SET_MSK 0x00000800
7197 
7198 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_CLR_MSK 0xfffff7ff
7199 
7200 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_RESET 0x1
7201 
7202 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_GET(value) (((value) & 0x00000800) >> 11)
7203 
7204 #define ALT_CLKMGR_PERPLL_ENR_QSPICLKEN_SET(value) (((value) << 11) & 0x00000800)
7205 
7206 #ifndef __ASSEMBLY__
7207 
7218 {
7219  uint32_t emac0en : 1;
7220  uint32_t emac1en : 1;
7221  uint32_t emac2en : 1;
7222  uint32_t emacptpen : 1;
7223  uint32_t gpiodben : 1;
7224  uint32_t sdmmcclken : 1;
7225  uint32_t s2fuser1clken : 1;
7226  uint32_t : 1;
7227  uint32_t usbclken : 1;
7228  uint32_t spimclken : 1;
7229  uint32_t nandclken : 1;
7230  uint32_t qspiclken : 1;
7231  uint32_t : 20;
7232 };
7233 
7236 #endif /* __ASSEMBLY__ */
7237 
7239 #define ALT_CLKMGR_PERPLL_ENR_RESET 0x00000f7f
7240 
7241 #define ALT_CLKMGR_PERPLL_ENR_OFST 0x10
7242 
7277 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_LSB 0
7278 
7279 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_MSB 0
7280 
7281 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_WIDTH 1
7282 
7283 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET_MSK 0x00000001
7284 
7285 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_CLR_MSK 0xfffffffe
7286 
7287 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_RESET 0x1
7288 
7289 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7290 
7291 #define ALT_CLKMGR_PERPLL_BYPASS_EMACA_SET(value) (((value) << 0) & 0x00000001)
7292 
7303 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_LSB 1
7304 
7305 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_MSB 1
7306 
7307 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_WIDTH 1
7308 
7309 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET_MSK 0x00000002
7310 
7311 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_CLR_MSK 0xfffffffd
7312 
7313 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_RESET 0x1
7314 
7315 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7316 
7317 #define ALT_CLKMGR_PERPLL_BYPASS_EMACB_SET(value) (((value) << 1) & 0x00000002)
7318 
7329 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_LSB 2
7330 
7331 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_MSB 2
7332 
7333 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_WIDTH 1
7334 
7335 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET_MSK 0x00000004
7336 
7337 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_CLR_MSK 0xfffffffb
7338 
7339 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_RESET 0x1
7340 
7341 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7342 
7343 #define ALT_CLKMGR_PERPLL_BYPASS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7344 
7355 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_LSB 3
7356 
7357 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_MSB 3
7358 
7359 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_WIDTH 1
7360 
7361 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET_MSK 0x00000008
7362 
7363 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_CLR_MSK 0xfffffff7
7364 
7365 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_RESET 0x1
7366 
7367 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7368 
7369 #define ALT_CLKMGR_PERPLL_BYPASS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7370 
7381 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_LSB 4
7382 
7383 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_MSB 4
7384 
7385 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_WIDTH 1
7386 
7387 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET_MSK 0x00000010
7388 
7389 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_CLR_MSK 0xffffffef
7390 
7391 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_RESET 0x1
7392 
7393 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7394 
7395 #define ALT_CLKMGR_PERPLL_BYPASS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7396 
7407 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_LSB 5
7408 
7409 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_MSB 5
7410 
7411 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_WIDTH 1
7412 
7413 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET_MSK 0x00000020
7414 
7415 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_CLR_MSK 0xffffffdf
7416 
7417 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_RESET 0x1
7418 
7419 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7420 
7421 #define ALT_CLKMGR_PERPLL_BYPASS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7422 
7434 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_LSB 6
7435 
7436 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_MSB 6
7437 
7438 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_WIDTH 1
7439 
7440 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_SET_MSK 0x00000040
7441 
7442 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_CLR_MSK 0xffffffbf
7443 
7444 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_RESET 0x1
7445 
7446 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7447 
7448 #define ALT_CLKMGR_PERPLL_BYPASS_RFEN_SET(value) (((value) << 6) & 0x00000040)
7449 
7460 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_LSB 7
7461 
7462 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_MSB 7
7463 
7464 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_WIDTH 1
7465 
7466 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_SET_MSK 0x00000080
7467 
7468 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_CLR_MSK 0xffffff7f
7469 
7470 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_RESET 0x1
7471 
7472 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7473 
7474 #define ALT_CLKMGR_PERPLL_BYPASS_FBEN_SET(value) (((value) << 7) & 0x00000080)
7475 
7476 #ifndef __ASSEMBLY__
7477 
7488 {
7489  uint32_t emaca : 1;
7490  uint32_t emacb : 1;
7491  uint32_t emacptp : 1;
7492  uint32_t gpiodb : 1;
7493  uint32_t sdmmc : 1;
7494  uint32_t s2fuser1 : 1;
7495  uint32_t rfen : 1;
7496  uint32_t fben : 1;
7497  uint32_t : 24;
7498 };
7499 
7502 #endif /* __ASSEMBLY__ */
7503 
7505 #define ALT_CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
7506 
7507 #define ALT_CLKMGR_PERPLL_BYPASS_OFST 0x14
7508 
7539 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_LSB 0
7540 
7541 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_MSB 0
7542 
7543 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_WIDTH 1
7544 
7545 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET_MSK 0x00000001
7546 
7547 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_CLR_MSK 0xfffffffe
7548 
7549 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_RESET 0x1
7550 
7551 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7552 
7553 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACA_SET(value) (((value) << 0) & 0x00000001)
7554 
7565 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_LSB 1
7566 
7567 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_MSB 1
7568 
7569 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_WIDTH 1
7570 
7571 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET_MSK 0x00000002
7572 
7573 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_CLR_MSK 0xfffffffd
7574 
7575 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_RESET 0x1
7576 
7577 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7578 
7579 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACB_SET(value) (((value) << 1) & 0x00000002)
7580 
7591 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_LSB 2
7592 
7593 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_MSB 2
7594 
7595 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_WIDTH 1
7596 
7597 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET_MSK 0x00000004
7598 
7599 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_CLR_MSK 0xfffffffb
7600 
7601 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_RESET 0x1
7602 
7603 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7604 
7605 #define ALT_CLKMGR_PERPLL_BYPASSS_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7606 
7617 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_LSB 3
7618 
7619 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_MSB 3
7620 
7621 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_WIDTH 1
7622 
7623 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET_MSK 0x00000008
7624 
7625 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_CLR_MSK 0xfffffff7
7626 
7627 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_RESET 0x1
7628 
7629 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7630 
7631 #define ALT_CLKMGR_PERPLL_BYPASSS_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7632 
7643 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_LSB 4
7644 
7645 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_MSB 4
7646 
7647 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_WIDTH 1
7648 
7649 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET_MSK 0x00000010
7650 
7651 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_CLR_MSK 0xffffffef
7652 
7653 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_RESET 0x1
7654 
7655 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7656 
7657 #define ALT_CLKMGR_PERPLL_BYPASSS_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7658 
7669 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_LSB 5
7670 
7671 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_MSB 5
7672 
7673 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_WIDTH 1
7674 
7675 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET_MSK 0x00000020
7676 
7677 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_CLR_MSK 0xffffffdf
7678 
7679 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_RESET 0x1
7680 
7681 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7682 
7683 #define ALT_CLKMGR_PERPLL_BYPASSS_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7684 
7696 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_LSB 6
7697 
7698 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_MSB 6
7699 
7700 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_WIDTH 1
7701 
7702 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_SET_MSK 0x00000040
7703 
7704 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_CLR_MSK 0xffffffbf
7705 
7706 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_RESET 0x1
7707 
7708 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7709 
7710 #define ALT_CLKMGR_PERPLL_BYPASSS_RFEN_SET(value) (((value) << 6) & 0x00000040)
7711 
7722 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_LSB 7
7723 
7724 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_MSB 7
7725 
7726 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_WIDTH 1
7727 
7728 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_SET_MSK 0x00000080
7729 
7730 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_CLR_MSK 0xffffff7f
7731 
7732 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_RESET 0x1
7733 
7734 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7735 
7736 #define ALT_CLKMGR_PERPLL_BYPASSS_FBEN_SET(value) (((value) << 7) & 0x00000080)
7737 
7738 #ifndef __ASSEMBLY__
7739 
7750 {
7751  uint32_t emaca : 1;
7752  uint32_t emacb : 1;
7753  uint32_t emacptp : 1;
7754  uint32_t gpiodb : 1;
7755  uint32_t sdmmc : 1;
7756  uint32_t s2fuser1 : 1;
7757  uint32_t rfen : 1;
7758  uint32_t fben : 1;
7759  uint32_t : 24;
7760 };
7761 
7764 #endif /* __ASSEMBLY__ */
7765 
7767 #define ALT_CLKMGR_PERPLL_BYPASSS_RESET 0x000000ff
7768 
7769 #define ALT_CLKMGR_PERPLL_BYPASSS_OFST 0x18
7770 
7801 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_LSB 0
7802 
7803 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_MSB 0
7804 
7805 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_WIDTH 1
7806 
7807 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET_MSK 0x00000001
7808 
7809 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_CLR_MSK 0xfffffffe
7810 
7811 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_RESET 0x1
7812 
7813 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_GET(value) (((value) & 0x00000001) >> 0)
7814 
7815 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACA_SET(value) (((value) << 0) & 0x00000001)
7816 
7827 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_LSB 1
7828 
7829 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_MSB 1
7830 
7831 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_WIDTH 1
7832 
7833 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET_MSK 0x00000002
7834 
7835 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_CLR_MSK 0xfffffffd
7836 
7837 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_RESET 0x1
7838 
7839 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_GET(value) (((value) & 0x00000002) >> 1)
7840 
7841 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACB_SET(value) (((value) << 1) & 0x00000002)
7842 
7853 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_LSB 2
7854 
7855 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_MSB 2
7856 
7857 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_WIDTH 1
7858 
7859 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET_MSK 0x00000004
7860 
7861 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_CLR_MSK 0xfffffffb
7862 
7863 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_RESET 0x1
7864 
7865 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_GET(value) (((value) & 0x00000004) >> 2)
7866 
7867 #define ALT_CLKMGR_PERPLL_BYPASSR_EMACPTP_SET(value) (((value) << 2) & 0x00000004)
7868 
7879 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_LSB 3
7880 
7881 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_MSB 3
7882 
7883 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_WIDTH 1
7884 
7885 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET_MSK 0x00000008
7886 
7887 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_CLR_MSK 0xfffffff7
7888 
7889 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_RESET 0x1
7890 
7891 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_GET(value) (((value) & 0x00000008) >> 3)
7892 
7893 #define ALT_CLKMGR_PERPLL_BYPASSR_GPIODB_SET(value) (((value) << 3) & 0x00000008)
7894 
7905 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_LSB 4
7906 
7907 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_MSB 4
7908 
7909 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_WIDTH 1
7910 
7911 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET_MSK 0x00000010
7912 
7913 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_CLR_MSK 0xffffffef
7914 
7915 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_RESET 0x1
7916 
7917 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_GET(value) (((value) & 0x00000010) >> 4)
7918 
7919 #define ALT_CLKMGR_PERPLL_BYPASSR_SDMMC_SET(value) (((value) << 4) & 0x00000010)
7920 
7931 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_LSB 5
7932 
7933 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_MSB 5
7934 
7935 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_WIDTH 1
7936 
7937 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET_MSK 0x00000020
7938 
7939 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_CLR_MSK 0xffffffdf
7940 
7941 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_RESET 0x1
7942 
7943 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_GET(value) (((value) & 0x00000020) >> 5)
7944 
7945 #define ALT_CLKMGR_PERPLL_BYPASSR_S2FUSER1_SET(value) (((value) << 5) & 0x00000020)
7946 
7958 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_LSB 6
7959 
7960 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_MSB 6
7961 
7962 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_WIDTH 1
7963 
7964 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_SET_MSK 0x00000040
7965 
7966 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_CLR_MSK 0xffffffbf
7967 
7968 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_RESET 0x1
7969 
7970 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_GET(value) (((value) & 0x00000040) >> 6)
7971 
7972 #define ALT_CLKMGR_PERPLL_BYPASSR_RFEN_SET(value) (((value) << 6) & 0x00000040)
7973 
7984 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_LSB 7
7985 
7986 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_MSB 7
7987 
7988 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_WIDTH 1
7989 
7990 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_SET_MSK 0x00000080
7991 
7992 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_CLR_MSK 0xffffff7f
7993 
7994 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_RESET 0x1
7995 
7996 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_GET(value) (((value) & 0x00000080) >> 7)
7997 
7998 #define ALT_CLKMGR_PERPLL_BYPASSR_FBEN_SET(value) (((value) << 7) & 0x00000080)
7999 
8000 #ifndef __ASSEMBLY__
8001 
8012 {
8013  uint32_t emaca : 1;
8014  uint32_t emacb : 1;
8015  uint32_t emacptp : 1;
8016  uint32_t gpiodb : 1;
8017  uint32_t sdmmc : 1;
8018  uint32_t s2fuser1 : 1;
8019  uint32_t rfen : 1;
8020  uint32_t fben : 1;
8021  uint32_t : 24;
8022 };
8023 
8026 #endif /* __ASSEMBLY__ */
8027 
8029 #define ALT_CLKMGR_PERPLL_BYPASSR_RESET 0x000000ff
8030 
8031 #define ALT_CLKMGR_PERPLL_BYPASSR_OFST 0x1c
8032 
8058 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_LSB 0
8059 
8060 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_MSB 10
8061 
8062 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_WIDTH 11
8063 
8064 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET_MSK 0x000007ff
8065 
8066 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_CLR_MSK 0xfffff800
8067 
8068 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_RESET 0x0
8069 
8070 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8071 
8072 #define ALT_CLKMGR_PERPLL_CNTR2CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8073 
8097 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_MAIN 0x0
8098 
8102 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_PERI 0x1
8103 
8107 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_OSC1 0x2
8108 
8112 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_INTOSC 0x3
8113 
8117 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_E_FPGA 0x4
8118 
8120 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
8121 
8122 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_MSB 18
8123 
8124 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_WIDTH 3
8125 
8126 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET_MSK 0x00070000
8127 
8128 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_CLR_MSK 0xfff8ffff
8129 
8130 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_RESET 0x0
8131 
8132 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8133 
8134 #define ALT_CLKMGR_PERPLL_CNTR2CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8135 
8136 #ifndef __ASSEMBLY__
8137 
8148 {
8149  uint32_t cnt : 11;
8150  uint32_t : 5;
8151  uint32_t src : 3;
8152  uint32_t : 13;
8153 };
8154 
8157 #endif /* __ASSEMBLY__ */
8158 
8160 #define ALT_CLKMGR_PERPLL_CNTR2CLK_RESET 0x00000000
8161 
8162 #define ALT_CLKMGR_PERPLL_CNTR2CLK_OFST 0x28
8163 
8189 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_LSB 0
8190 
8191 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_MSB 10
8192 
8193 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_WIDTH 11
8194 
8195 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET_MSK 0x000007ff
8196 
8197 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_CLR_MSK 0xfffff800
8198 
8199 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_RESET 0x0
8200 
8201 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8202 
8203 #define ALT_CLKMGR_PERPLL_CNTR3CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8204 
8228 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_MAIN 0x0
8229 
8233 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_PERI 0x1
8234 
8238 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_OSC1 0x2
8239 
8243 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_INTOSC 0x3
8244 
8248 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_E_FPGA 0x4
8249 
8251 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
8252 
8253 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_MSB 18
8254 
8255 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_WIDTH 3
8256 
8257 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET_MSK 0x00070000
8258 
8259 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_CLR_MSK 0xfff8ffff
8260 
8261 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_RESET 0x0
8262 
8263 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8264 
8265 #define ALT_CLKMGR_PERPLL_CNTR3CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8266 
8267 #ifndef __ASSEMBLY__
8268 
8279 {
8280  uint32_t cnt : 11;
8281  uint32_t : 5;
8282  uint32_t src : 3;
8283  uint32_t : 13;
8284 };
8285 
8288 #endif /* __ASSEMBLY__ */
8289 
8291 #define ALT_CLKMGR_PERPLL_CNTR3CLK_RESET 0x00000000
8292 
8293 #define ALT_CLKMGR_PERPLL_CNTR3CLK_OFST 0x2c
8294 
8320 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_LSB 0
8321 
8322 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_MSB 10
8323 
8324 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_WIDTH 11
8325 
8326 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET_MSK 0x000007ff
8327 
8328 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_CLR_MSK 0xfffff800
8329 
8330 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_RESET 0x0
8331 
8332 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8333 
8334 #define ALT_CLKMGR_PERPLL_CNTR4CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8335 
8359 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_MAIN 0x0
8360 
8364 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_PERI 0x1
8365 
8369 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_OSC1 0x2
8370 
8374 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_INTOSC 0x3
8375 
8379 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_E_FPGA 0x4
8380 
8382 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
8383 
8384 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_MSB 18
8385 
8386 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_WIDTH 3
8387 
8388 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET_MSK 0x00070000
8389 
8390 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_CLR_MSK 0xfff8ffff
8391 
8392 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_RESET 0x0
8393 
8394 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8395 
8396 #define ALT_CLKMGR_PERPLL_CNTR4CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8397 
8398 #ifndef __ASSEMBLY__
8399 
8410 {
8411  uint32_t cnt : 11;
8412  uint32_t : 5;
8413  uint32_t src : 3;
8414  uint32_t : 13;
8415 };
8416 
8419 #endif /* __ASSEMBLY__ */
8420 
8422 #define ALT_CLKMGR_PERPLL_CNTR4CLK_RESET 0x00000000
8423 
8424 #define ALT_CLKMGR_PERPLL_CNTR4CLK_OFST 0x30
8425 
8451 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_LSB 0
8452 
8453 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_MSB 10
8454 
8455 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_WIDTH 11
8456 
8457 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET_MSK 0x000007ff
8458 
8459 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_CLR_MSK 0xfffff800
8460 
8461 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_RESET 0x0
8462 
8463 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8464 
8465 #define ALT_CLKMGR_PERPLL_CNTR5CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8466 
8490 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_MAIN 0x0
8491 
8495 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_PERI 0x1
8496 
8500 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_OSC1 0x2
8501 
8505 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_INTOSC 0x3
8506 
8510 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_E_FPGA 0x4
8511 
8513 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
8514 
8515 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_MSB 18
8516 
8517 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_WIDTH 3
8518 
8519 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET_MSK 0x00070000
8520 
8521 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_CLR_MSK 0xfff8ffff
8522 
8523 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_RESET 0x0
8524 
8525 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8526 
8527 #define ALT_CLKMGR_PERPLL_CNTR5CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8528 
8529 #ifndef __ASSEMBLY__
8530 
8541 {
8542  uint32_t cnt : 11;
8543  uint32_t : 5;
8544  uint32_t src : 3;
8545  uint32_t : 13;
8546 };
8547 
8550 #endif /* __ASSEMBLY__ */
8551 
8553 #define ALT_CLKMGR_PERPLL_CNTR5CLK_RESET 0x00000000
8554 
8555 #define ALT_CLKMGR_PERPLL_CNTR5CLK_OFST 0x34
8556 
8582 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_LSB 0
8583 
8584 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_MSB 10
8585 
8586 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_WIDTH 11
8587 
8588 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET_MSK 0x000007ff
8589 
8590 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_CLR_MSK 0xfffff800
8591 
8592 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_RESET 0x0
8593 
8594 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8595 
8596 #define ALT_CLKMGR_PERPLL_CNTR6CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8597 
8621 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_MAIN 0x0
8622 
8626 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_PERI 0x1
8627 
8631 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_OSC1 0x2
8632 
8636 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_INTOSC 0x3
8637 
8641 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_E_FPGA 0x4
8642 
8644 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
8645 
8646 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_MSB 18
8647 
8648 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_WIDTH 3
8649 
8650 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET_MSK 0x00070000
8651 
8652 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_CLR_MSK 0xfff8ffff
8653 
8654 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_RESET 0x0
8655 
8656 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8657 
8658 #define ALT_CLKMGR_PERPLL_CNTR6CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8659 
8660 #ifndef __ASSEMBLY__
8661 
8672 {
8673  uint32_t cnt : 11;
8674  uint32_t : 5;
8675  uint32_t src : 3;
8676  uint32_t : 13;
8677 };
8678 
8681 #endif /* __ASSEMBLY__ */
8682 
8684 #define ALT_CLKMGR_PERPLL_CNTR6CLK_RESET 0x00000000
8685 
8686 #define ALT_CLKMGR_PERPLL_CNTR6CLK_OFST 0x38
8687 
8711 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_LSB 0
8712 
8713 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_MSB 10
8714 
8715 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_WIDTH 11
8716 
8717 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET_MSK 0x000007ff
8718 
8719 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_CLR_MSK 0xfffff800
8720 
8721 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_RESET 0x0
8722 
8723 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8724 
8725 #define ALT_CLKMGR_PERPLL_CNTR7CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8726 
8727 #ifndef __ASSEMBLY__
8728 
8739 {
8740  uint32_t cnt : 11;
8741  uint32_t : 21;
8742 };
8743 
8746 #endif /* __ASSEMBLY__ */
8747 
8749 #define ALT_CLKMGR_PERPLL_CNTR7CLK_RESET 0x00000000
8750 
8751 #define ALT_CLKMGR_PERPLL_CNTR7CLK_OFST 0x3c
8752 
8778 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_LSB 0
8779 
8780 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_MSB 10
8781 
8782 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_WIDTH 11
8783 
8784 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET_MSK 0x000007ff
8785 
8786 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_CLR_MSK 0xfffff800
8787 
8788 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_RESET 0x0
8789 
8790 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8791 
8792 #define ALT_CLKMGR_PERPLL_CNTR8CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8793 
8817 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_MAIN 0x0
8818 
8822 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_PERI 0x1
8823 
8827 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_OSC1 0x2
8828 
8832 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_INTOSC 0x3
8833 
8837 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_E_FPGA 0x4
8838 
8840 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
8841 
8842 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_MSB 18
8843 
8844 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_WIDTH 3
8845 
8846 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET_MSK 0x00070000
8847 
8848 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_CLR_MSK 0xfff8ffff
8849 
8850 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_RESET 0x0
8851 
8852 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_GET(value) (((value) & 0x00070000) >> 16)
8853 
8854 #define ALT_CLKMGR_PERPLL_CNTR8CLK_SRC_SET(value) (((value) << 16) & 0x00070000)
8855 
8856 #ifndef __ASSEMBLY__
8857 
8868 {
8869  uint32_t cnt : 11;
8870  uint32_t : 5;
8871  uint32_t src : 3;
8872  uint32_t : 13;
8873 };
8874 
8877 #endif /* __ASSEMBLY__ */
8878 
8880 #define ALT_CLKMGR_PERPLL_CNTR8CLK_RESET 0x00000000
8881 
8882 #define ALT_CLKMGR_PERPLL_CNTR8CLK_OFST 0x40
8883 
8907 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_LSB 0
8908 
8909 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_MSB 10
8910 
8911 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_WIDTH 11
8912 
8913 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET_MSK 0x000007ff
8914 
8915 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_CLR_MSK 0xfffff800
8916 
8917 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_RESET 0x0
8918 
8919 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_GET(value) (((value) & 0x000007ff) >> 0)
8920 
8921 #define ALT_CLKMGR_PERPLL_CNTR9CLK_CNT_SET(value) (((value) << 0) & 0x000007ff)
8922 
8923 #ifndef __ASSEMBLY__
8924 
8935 {
8936  uint32_t cnt : 11;
8937  uint32_t : 21;
8938 };
8939 
8942 #endif /* __ASSEMBLY__ */
8943 
8945 #define ALT_CLKMGR_PERPLL_CNTR9CLK_RESET 0x00000000
8946 
8947 #define ALT_CLKMGR_PERPLL_CNTR9CLK_OFST 0x44
8948 
8987 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_LSB 0
8988 
8989 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_MSB 15
8990 
8991 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_WIDTH 16
8992 
8993 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_SET_MSK 0x0000ffff
8994 
8995 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_CLR_MSK 0xffff0000
8996 
8997 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_RESET 0x0
8998 
8999 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_GET(value) (((value) & 0x0000ffff) >> 0)
9000 
9001 #define ALT_CLKMGR_PERPLL_OUTRST_OUTRST_SET(value) (((value) << 0) & 0x0000ffff)
9002 
9003 #ifndef __ASSEMBLY__
9004 
9015 {
9016  uint32_t outreset : 16;
9017  uint32_t : 16;
9018 };
9019 
9022 #endif /* __ASSEMBLY__ */
9023 
9025 #define ALT_CLKMGR_PERPLL_OUTRST_RESET 0x00000000
9026 
9027 #define ALT_CLKMGR_PERPLL_OUTRST_OFST 0x60
9028 
9074 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_IDLE 0x0
9075 
9080 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_E_ACK_RXD 0x1
9081 
9083 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_LSB 0
9084 
9085 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_MSB 15
9086 
9087 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_WIDTH 16
9088 
9089 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_SET_MSK 0x0000ffff
9090 
9091 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_CLR_MSK 0xffff0000
9092 
9093 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_RESET 0x0
9094 
9095 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_GET(value) (((value) & 0x0000ffff) >> 0)
9096 
9097 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OUTRSTACK_SET(value) (((value) << 0) & 0x0000ffff)
9098 
9099 #ifndef __ASSEMBLY__
9100 
9111 {
9112  const uint32_t outresetack : 16;
9113  uint32_t : 16;
9114 };
9115 
9118 #endif /* __ASSEMBLY__ */
9119 
9121 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_RESET 0x00000000
9122 
9123 #define ALT_CLKMGR_PERPLL_OUTRSTSTAT_OFST 0x64
9124 
9162 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACA 0x0
9163 
9168 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_E_EMACB 0x1
9169 
9171 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
9172 
9173 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_MSB 26
9174 
9175 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_WIDTH 1
9176 
9177 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET_MSK 0x04000000
9178 
9179 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_CLR_MSK 0xfbffffff
9180 
9181 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_RESET 0x0
9182 
9183 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_GET(value) (((value) & 0x04000000) >> 26)
9184 
9185 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC0SEL_SET(value) (((value) << 26) & 0x04000000)
9186 
9207 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACA 0x0
9208 
9213 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_E_EMACB 0x1
9214 
9216 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
9217 
9218 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_MSB 27
9219 
9220 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_WIDTH 1
9221 
9222 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET_MSK 0x08000000
9223 
9224 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_CLR_MSK 0xf7ffffff
9225 
9226 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_RESET 0x0
9227 
9228 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_GET(value) (((value) & 0x08000000) >> 27)
9229 
9230 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC1SEL_SET(value) (((value) << 27) & 0x08000000)
9231 
9252 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACA 0x0
9253 
9258 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_E_EMACB 0x1
9259 
9261 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
9262 
9263 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_MSB 28
9264 
9265 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_WIDTH 1
9266 
9267 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET_MSK 0x10000000
9268 
9269 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_CLR_MSK 0xefffffff
9270 
9271 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_RESET 0x0
9272 
9273 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_GET(value) (((value) & 0x10000000) >> 28)
9274 
9275 #define ALT_CLKMGR_PERPLL_EMACCTL_EMAC2SEL_SET(value) (((value) << 28) & 0x10000000)
9276 
9277 #ifndef __ASSEMBLY__
9278 
9289 {
9290  uint32_t : 26;
9291  uint32_t emac0sel : 1;
9292  uint32_t emac1sel : 1;
9293  uint32_t emac2sel : 1;
9294  uint32_t : 3;
9295 };
9296 
9299 #endif /* __ASSEMBLY__ */
9300 
9302 #define ALT_CLKMGR_PERPLL_EMACCTL_RESET 0x00000000
9303 
9304 #define ALT_CLKMGR_PERPLL_EMACCTL_OFST 0x68
9305 
9330 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB 0
9331 
9332 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB 15
9333 
9334 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH 16
9335 
9336 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK 0x0000ffff
9337 
9338 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK 0xffff0000
9339 
9340 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET 0x1
9341 
9342 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value) (((value) & 0x0000ffff) >> 0)
9343 
9344 #define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value) (((value) << 0) & 0x0000ffff)
9345 
9346 #ifndef __ASSEMBLY__
9347 
9358 {
9359  uint32_t gpiodbclk : 16;
9360  uint32_t : 16;
9361 };
9362 
9365 #endif /* __ASSEMBLY__ */
9366 
9368 #define ALT_CLKMGR_PERPLL_GPIODIV_RESET 0x00000001
9369 
9370 #define ALT_CLKMGR_PERPLL_GPIODIV_OFST 0x6c
9371 
9372 #ifndef __ASSEMBLY__
9373 
9384 {
9393  volatile uint32_t _pad_0x20_0x27[2];
9402  volatile uint32_t _pad_0x48_0x5f[6];
9407  volatile uint32_t _pad_0x70_0x80[4];
9408 };
9409 
9414 {
9415  volatile uint32_t vco0;
9416  volatile uint32_t vco1;
9417  volatile uint32_t en;
9418  volatile uint32_t ens;
9419  volatile uint32_t enr;
9420  volatile uint32_t bypass;
9421  volatile uint32_t bypasss;
9422  volatile uint32_t bypassr;
9423  volatile uint32_t _pad_0x20_0x27[2];
9424  volatile uint32_t cntr2clk;
9425  volatile uint32_t cntr3clk;
9426  volatile uint32_t cntr4clk;
9427  volatile uint32_t cntr5clk;
9428  volatile uint32_t cntr6clk;
9429  volatile uint32_t cntr7clk;
9430  volatile uint32_t cntr8clk;
9431  volatile uint32_t cntr9clk;
9432  volatile uint32_t _pad_0x48_0x5f[6];
9433  volatile uint32_t outrst;
9434  volatile uint32_t outrststat;
9435  volatile uint32_t emacctl;
9436  volatile uint32_t gpiodiv;
9437  volatile uint32_t _pad_0x70_0x80[4];
9438 };
9439 
9442 #endif /* __ASSEMBLY__ */
9443 
9476 #define ALT_CLKMGR_NOCCLK_MAINCNT_LSB 0
9477 
9478 #define ALT_CLKMGR_NOCCLK_MAINCNT_MSB 10
9479 
9480 #define ALT_CLKMGR_NOCCLK_MAINCNT_WIDTH 11
9481 
9482 #define ALT_CLKMGR_NOCCLK_MAINCNT_SET_MSK 0x000007ff
9483 
9484 #define ALT_CLKMGR_NOCCLK_MAINCNT_CLR_MSK 0xfffff800
9485 
9486 #define ALT_CLKMGR_NOCCLK_MAINCNT_RESET 0x3
9487 
9488 #define ALT_CLKMGR_NOCCLK_MAINCNT_GET(value) (((value) & 0x000007ff) >> 0)
9489 
9490 #define ALT_CLKMGR_NOCCLK_MAINCNT_SET(value) (((value) << 0) & 0x000007ff)
9491 
9503 #define ALT_CLKMGR_NOCCLK_PERICNT_LSB 16
9504 
9505 #define ALT_CLKMGR_NOCCLK_PERICNT_MSB 26
9506 
9507 #define ALT_CLKMGR_NOCCLK_PERICNT_WIDTH 11
9508 
9509 #define ALT_CLKMGR_NOCCLK_PERICNT_SET_MSK 0x07ff0000
9510 
9511 #define ALT_CLKMGR_NOCCLK_PERICNT_CLR_MSK 0xf800ffff
9512 
9513 #define ALT_CLKMGR_NOCCLK_PERICNT_RESET 0x3
9514 
9515 #define ALT_CLKMGR_NOCCLK_PERICNT_GET(value) (((value) & 0x07ff0000) >> 16)
9516 
9517 #define ALT_CLKMGR_NOCCLK_PERICNT_SET(value) (((value) << 16) & 0x07ff0000)
9518 
9519 #ifndef __ASSEMBLY__
9520 
9531 {
9532  uint32_t maincnt : 11;
9533  uint32_t : 5;
9534  uint32_t pericnt : 11;
9535  uint32_t : 5;
9536 };
9537 
9540 #endif /* __ASSEMBLY__ */
9541 
9543 #define ALT_CLKMGR_NOCCLK_RESET 0x00030003
9544 
9545 #define ALT_CLKMGR_NOCCLK_OFST 0x4
9546 
9547 #ifndef __ASSEMBLY__
9548 
9559 {
9560  volatile uint32_t _pad_0x0_0x3;
9562  volatile uint32_t _pad_0x8_0x40[14];
9563 };
9564 
9569 {
9570  volatile uint32_t _pad_0x0_0x3;
9571  volatile uint32_t nocclk;
9572  volatile uint32_t _pad_0x8_0x40[14];
9573 };
9574 
9577 #endif /* __ASSEMBLY__ */
9578 
9580 #ifdef __cplusplus
9581 }
9582 #endif /* __cplusplus */
9583 #endif /* __ALT_SOCAL_CLKMGR_H__ */
9584