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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN |
[3:1] | ??? | Unknown | UNDEFINED |
[4] | RW | 0x1 | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS |
[7:5] | ??? | Unknown | UNDEFINED |
[8] | RW | 0x1 | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN |
[31:9] | ??? | Unknown | UNDEFINED |
Field : chip_interleave_enable | |
This bit informs the controller to enable or disable interleaving among banks/LUNS to increase the net performance of the controller. [list][*]1 - Enable interleaving [*]0 - Disable Interleaving[/list] Field Access Macros: | |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0 |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0 |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1 |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001 |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0 |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : allow_int_reads_within_luns | |
This bit informs the controller to enable or disable simultaneous read accesses to different LUNS in the same bank. This bit is of importance only if the controller supports interleaved operations among LUNs and if the device has multiple LUNS. If the bit is disabled, the controller will send read commands to different LUNS of of the same bank only sequentially and if enabled, the controller will issue simultaneous read accesses to LUNS of same bank if required. [list][*]1 - Enable [*]0 - Disable[/list] Field Access Macros: | |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4 |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4 |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1 |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010 |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1 |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010) |
Field : cmd_dma_error_enable | |
This bit informs the CDMA channels to stop working on any new MAP10 Command DMAcommands from the host after encountering an error situation till the error bit for that corresponding channel is cleared in the cmd_dma_channel_error register by f/w. When the CDMA channel encounters an error, it will set the corresponding error bit in cmd_dma_channel_error register If this bit is set, the channel will stop executing any further commands till f/w comes and clears the error bit in the cmd_dma_channel_error_register. If this bit is not set, controller will still keep on executing new commands issued from f/w. Field Access Macros: | |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_LSB 8 |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_MSB 8 |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_WIDTH 1 |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET_MSK 0x00000100 |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_CLR_MSK 0xfffffeff |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_RESET 0x1 |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET(value) (((value) << 8) & 0x00000100) |
Data Structures | |
struct | ALT_NAND_DMA_INTRLV_s |
Macros | |
#define | ALT_NAND_DMA_INTRLV_RESET 0x00000110 |
#define | ALT_NAND_DMA_INTRLV_OFST 0x80 |
Typedefs | |
typedef struct ALT_NAND_DMA_INTRLV_s | ALT_NAND_DMA_INTRLV_t |
struct ALT_NAND_DMA_INTRLV_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_DMA_INTRLV.
Data Fields | ||
---|---|---|
uint32_t | chip_interleave_enable: 1 | ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN |
uint32_t | __pad0__: 3 | UNDEFINED |
uint32_t | allow_int_reads_within_luns: 1 | ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS |
uint32_t | __pad1__: 3 | UNDEFINED |
uint32_t | cmd_dma_error_enable: 1 | ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN |
uint32_t | __pad2__: 23 | UNDEFINED |
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0 |
The reset value of the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN field value from a register.
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN register field value suitable for setting the register.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010 |
The mask used to set the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef |
The mask used to clear the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1 |
The reset value of the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS field value from a register.
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS register field value suitable for setting the register.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET_MSK 0x00000100 |
The mask used to set the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_RESET 0x1 |
The reset value of the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN field value from a register.
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN register field value suitable for setting the register.
#define ALT_NAND_DMA_INTRLV_RESET 0x00000110 |
The reset value of the ALT_NAND_DMA_INTRLV register.
#define ALT_NAND_DMA_INTRLV_OFST 0x80 |
The byte offset of the ALT_NAND_DMA_INTRLV register from the beginning of the component.
typedef struct ALT_NAND_DMA_INTRLV_s ALT_NAND_DMA_INTRLV_t |
The typedef declaration for register ALT_NAND_DMA_INTRLV.