Altera HWLIB
16.0
The Altera HW Manager API Reference Manual
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Address Space
Data Structures
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Data Structures
Files
Functions
Variables
Typedefs
Enumerations
Enumerator
Groups
Address Space
The components and component instances of the Hammerhead-P HPS address space:
[detail level
1
2
3
]
UART Driver API
UART Basic
UART FIFO Interface
UART Baudrate Interface
UART Interrupt Interface
UART Modem Interface
UART Line Interface
The Address Space Manager
Address Space Mapping Control
L2 Cache Address Filter
ACP Memory Coherence and ID Mapping
Cache Management API
System Level Cache Management API
L1 Cache Management API
L2 Cache Management API
CAN Controller API
DMA Controller API
DMA API Compile Options
DMA API for Configuration, Control, and Status
DMA API for Standard Operations
DMA Controller Common API Definitions
DMA Controller Programming API
Support for DMAMOV CCR
Error Correcting Code (ECC) Management
The General Purpose Input/Output Manager API
General-Purpose IO Configuration Functions
General-Purpose IO Interrupt Functions
General-Purpose IO via Bit Index
General-Purpose IO Utility Functions
The Global Timer Manager API
I2C Controller API
SDA Hold Time Configuration
General Call
Interrupt and Status Conditions
RX FIFO Management
TX FIFO Management
DMA Interface
Interrupt Controller Low-Level API [Secure]
Interrupt Controller Preprocessor Defines [Secure]
Interrupt Controller Global Interface [Secure]
Interrupt Controller Distributor Interface [Secure]
Software Generated Interrupts [Secure]
Interrupt Controller CPU Interface [Secure]
Interrupt Service Routine [Secure]
Interrupt Utility Functions [Secure]
Interrupt Controller Common Definitions
MMU Management API
MMU Management
MMU Management Macros - First Level Translation Table
MMU Management Macros - Second Level Translation Table
MMU Management Data Structures - First Level Translation Table
MMU Management Data Structures - Second Level Translation Table
MMU Virtual Address Space Creation
MMU Virtual Address to Physical Address
NAND Flash Controller
QSPI Flash Controller Module
General Control and Status Functions
General Purpose Block I/O
Flash Device Configuration
Direct Access Mode
Indirect Access Mode
SRAM Partition
Flash Erase
DMA Peripheral Interface
The Reset Manager
Reset Status
Reset Control
SD/MMC Controller API
General Control and Status Functions
Card Interface
SD/MMC Controller Internal DMA
SD/MMC Controller FIFO
General Purpose Block I/O
SPI Flash Controller Module
Interrupt Status Conditions
RX Sample Delay Configuration
RX FIFO Management
TX FIFO Management
Transfer Functions
SPI Master Controller Transfer Functions
SPI Slave Controller Transfer Functions
DMA Interface
The System Manager
FPGA Interface Group
The General Purpose Timer Manager API
Enable, Disable, and Status
Counters Interface
Interrupts
Mode Control
The Watchdog Timer Manager API
Watchdog Timer Enable, Disable, Restart, Status
Watchdog Timer Counter Configuration
Watchdog Timer Interrupt Management
Watchdog Timer Miscellaneous Configuration
The AXI Bridge Manager
The Clock Manager API
Clock Manager Status
Safe Mode Options
PLL Bypass Control
Clock Gating Control
Clock Source Selection
Clock Frequency Control
Clock Manager Interrupt Management
Clock Group Configuration
The FPGA Manager
FPGA Manager Status and Control
FPGA Configuration
FPGA Full Configuration
FPGA Manager Interrupt Control
SoC to FPGA General Purpose I/O Signals
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