Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dbgmatch

Description

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO
[31:16] RW 0x0 ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE

Field : counter_zero

counter value

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_LSB   0
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_MSB   15
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_WIDTH   16
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_CLR_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : counter_one

counter value

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_LSB   16
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_MSB   31
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_WIDTH   16
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_CLR_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DBGMATCH_s
 

Macros

#define ALT_IO48_HMC_MMR_DBGMATCH_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DBGMATCH_OFST   0xfc
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DBGMATCH_s 
ALT_IO48_HMC_MMR_DBGMATCH_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DBGMATCH_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DBGMATCH.

Data Fields
uint32_t counter_zero: 16 ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO
uint32_t counter_one: 16 ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE

Macro Definitions

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET_MSK   0x0000ffff

The mask used to set the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_CLR_MSK   0xffff0000

The mask used to clear the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO field value from a register.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ZERO register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET_MSK   0xffff0000

The mask used to set the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_CLR_MSK   0x0000ffff

The mask used to clear the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE field value from a register.

#define ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_IO48_HMC_MMR_DBGMATCH_CNTR_ONE register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGMATCH_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DBGMATCH register.

#define ALT_IO48_HMC_MMR_DBGMATCH_OFST   0xfc

The byte offset of the ALT_IO48_HMC_MMR_DBGMATCH register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DBGMATCH.