Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : trace_d4 Mux Selection Register - GENERALIO5

Description

This register is used to control the peripherals connected to trace_d4

Only reset by a cold reset (ignores warm reset).

NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.

Register Layout

Bits Access Reset Description
[1:0] RW 0x0 trace_d4 Mux Selection Field
[31:2] ??? 0x0 UNDEFINED

Field : trace_d4 Mux Selection Field - sel

Select peripheral signals connected trace_d4.

0 : Pin is connected to GPIO/LoanIO number 53.

1 : Pin is connected to Peripheral signal CAN1.RX.

2 : Pin is connected to Peripheral signal SPIS1.CLK.

3 : Pin is connected to Peripheral signal TRACE.D4.

Field Access Macros:

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB   0
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB   1
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH   2
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK   0x00000003
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK   0xfffffffc
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET   0x0
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET(value)   (((value) << 0) & 0x00000003)
 

Data Structures

struct  ALT_SYSMGR_PINMUX_GENERALIO5_s
 

Macros

#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST   0x94
 

Typedefs

typedef struct
ALT_SYSMGR_PINMUX_GENERALIO5_s 
ALT_SYSMGR_PINMUX_GENERALIO5_t
 

Data Structure Documentation

struct ALT_SYSMGR_PINMUX_GENERALIO5_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_PINMUX_GENERALIO5.

Data Fields
uint32_t sel: 2 trace_d4 Mux Selection Field
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_WIDTH   2

The width in bits of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET_MSK   0x00000003

The mask used to set the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_CLR_MSK   0xfffffffc

The mask used to clear the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_RESET   0x0

The reset value of the ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_SYSMGR_PINMUX_GENERALIO5_SEL field value from a register.

#define ALT_SYSMGR_PINMUX_GENERALIO5_SEL_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_SYSMGR_PINMUX_GENERALIO5_SEL register field value suitable for setting the register.

#define ALT_SYSMGR_PINMUX_GENERALIO5_OFST   0x94

The byte offset of the ALT_SYSMGR_PINMUX_GENERALIO5 register from the beginning of the component.

Typedef Documentation