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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains settings that control the SDRAM PLL VCO. The VCO output frequency is the input frequency multiplied by the numerator (M+1) and divided by the denominator (N+1).
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | BG PWRDN |
[1] | RW | 0x0 | Enable |
[2] | RW | 0x1 | Power down |
[15:3] | RW | 0x1 | Numerator (M) |
[21:16] | RW | 0x1 | Denominator (N) |
[23:22] | RW | 0x0 | Clock Source |
[24] | RW | 0x0 | SDRAM All Output Counter Reset |
[30:25] | RW | 0x0 | Output Counter Reset |
[31] | RW | 0x1 | External Regulator Input Select |
Field : BG PWRDN - bgpwrdn | |
If '1', powers down bandgap. If '0', bandgap is not power down. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) |
Field : Enable - en | |
If '1', VCO is enabled. If '0', VCO is in reset. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_SDRPLL_VCO_EN_SET(value) (((value) << 1) & 0x00000002) |
Field : Power down - pwrdn | |
If '1', power down analog circuitry. If '0', analog circuitry not powered down. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET(value) (((value) << 2) & 0x00000004) |
Field : Numerator (M) - numer | |
Numerator in VCO output frequency equation. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_GET(value) (((value) & 0x0000fff8) >> 3) |
#define | ALT_CLKMGR_SDRPLL_VCO_NUMER_SET(value) (((value) << 3) & 0x0000fff8) |
Field : Denominator (N) - denom | |
Denominator in VCO output frequency equation. For incremental frequency change, if the new value lead to less than 20% of the frequency change, this value can be changed without resetting the PLL. The Numerator and Denominator can not be changed at the same time for incremental frequency changed. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_GET(value) (((value) & 0x003f0000) >> 16) |
#define | ALT_CLKMGR_SDRPLL_VCO_DENOM_SET(value) (((value) << 16) & 0x003f0000) |
Field : Clock Source - ssrc | |||||||||||||
Controls the VCO input clock source. The PLL must by bypassed to eosc1_clk before changing this field. Qsys and user documenation refer to f2s_sdram_ref_clk as f2h_sdram_ref_clk. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_GET(value) (((value) & 0x00c00000) >> 22) | ||||||||||||
#define | ALT_CLKMGR_SDRPLL_VCO_SSRC_SET(value) (((value) << 22) & 0x00c00000) | ||||||||||||
Field : SDRAM All Output Counter Reset - outresetall | |
Before releasing Bypass, All Output Counter Reset must be set and cleared by software for correct clock operation. If '1', Reset phase multiplexer and output counter state. So that after the assertion all the clocks output are start from rising edge align. If '0', phase multiplexer and output counter state not reset and no change to the phase of the clock outputs. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET(value) (((value) << 24) & 0x01000000) |
Field : Output Counter Reset - outreset | |
Resets the individual PLL output counter. For software to change the PLL output counter without producing glitches on the respective clock, SW must set the VCO register respective Output Counter Reset bit. Software then polls the respective Output Counter Reset Acknowledge bit in the Output Counter Reset Ack Status Register. Software then writes the appropriate counter register, and then clears the respective VCO register Output Counter Reset bit. LSB 'outreset[0]' corresponds to PLL output clock C0, etc. If set to '1', reset output divider, no clock output from counter. If set to '0', counter is not reset. The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET(value) (((value) & 0x7e000000) >> 25) |
#define | ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET(value) (((value) << 25) & 0x7e000000) |
Field : External Regulator Input Select - regextsel | |
If set to '1', the external regulator is selected for the PLL. If set to '0', the internal regulator is slected. It is strongly recommended to select the external regulator while the PLL is not enabled (in reset), and then disable the external regulater once the PLL becomes enabled. Software should simulateously update the 'Enable' bit and the 'External Regulator Input Select' in the same write access to the VCO register. When the 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa. The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_CLKMGR_SDRPLL_VCO_s |
Macros | |
#define | ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 |
Typedefs | |
typedef struct ALT_CLKMGR_SDRPLL_VCO_s | ALT_CLKMGR_SDRPLL_VCO_t |
struct ALT_CLKMGR_SDRPLL_VCO_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_SDRPLL_VCO.
Data Fields | ||
---|---|---|
uint32_t | bgpwrdn: 1 | BG PWRDN |
uint32_t | en: 1 | Enable |
uint32_t | pwrdn: 1 | Power down |
uint32_t | numer: 13 | Numerator (M) |
uint32_t | denom: 6 | Denominator (N) |
uint32_t | ssrc: 2 | Clock Source |
uint32_t | outresetall: 1 | SDRAM All Output Counter Reset |
uint32_t | outreset: 6 | Output Counter Reset |
uint32_t | regextsel: 1 | External Regulator Input Select |
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_BGPWRDN field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_BGPWRDN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_SDRPLL_VCO_BGPWRDN register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_EN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field.
#define ALT_CLKMGR_SDRPLL_VCO_EN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_EN register field.
#define ALT_CLKMGR_SDRPLL_VCO_EN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_EN register field.
#define ALT_CLKMGR_SDRPLL_VCO_EN_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_EN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_EN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_EN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_EN_RESET 0x0 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_EN register field.
#define ALT_CLKMGR_SDRPLL_VCO_EN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_EN field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_EN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_SDRPLL_VCO_EN register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_PWRDN register field.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_PWRDN field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_PWRDN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_SDRPLL_VCO_PWRDN register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_WIDTH 13 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET_MSK 0x0000fff8 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_CLR_MSK 0xffff0007 |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_NUMER register field value.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_NUMER register field.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_GET | ( | value | ) | (((value) & 0x0000fff8) >> 3) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_NUMER field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_NUMER_SET | ( | value | ) | (((value) << 3) & 0x0000fff8) |
Produces a ALT_CLKMGR_SDRPLL_VCO_NUMER register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_WIDTH 6 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET_MSK 0x003f0000 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_CLR_MSK 0xffc0ffff |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_DENOM register field value.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_DENOM register field.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_GET | ( | value | ) | (((value) & 0x003f0000) >> 16) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_DENOM field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_DENOM_SET | ( | value | ) | (((value) << 16) & 0x003f0000) |
Produces a ALT_CLKMGR_SDRPLL_VCO_DENOM register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC1 0x0 |
Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
eosc1_clk
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_EOSC2 0x1 |
Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
eosc2_clk
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_E_F2S_SDRAM_REF 0x2 |
Enumerated value for register field ALT_CLKMGR_SDRPLL_VCO_SSRC
f2s_sdram_ref_clk
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_WIDTH 2 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET_MSK 0x00c00000 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_CLR_MSK 0xff3fffff |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_SSRC register field value.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_RESET 0x0 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_SSRC register field.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_GET | ( | value | ) | (((value) & 0x00c00000) >> 22) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_SSRC field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_SSRC_SET | ( | value | ) | (((value) << 22) & 0x00c00000) |
Produces a ALT_CLKMGR_SDRPLL_VCO_SSRC register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET_MSK 0x01000000 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_RESET 0x0 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRSTALL register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_WIDTH 6 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET_MSK 0x7e000000 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_CLR_MSK 0x81ffffff |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_RESET 0x0 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_OUTRST register field.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_GET | ( | value | ) | (((value) & 0x7e000000) >> 25) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_OUTRST field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_OUTRST_SET | ( | value | ) | (((value) << 25) & 0x7e000000) |
Produces a ALT_CLKMGR_SDRPLL_VCO_OUTRST register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET_MSK 0x80000000 |
The mask used to set the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL field value from a register.
#define ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_CLKMGR_SDRPLL_VCO_REGEXTSEL register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_VCO_OFST 0x0 |
The byte offset of the ALT_CLKMGR_SDRPLL_VCO register from the beginning of the component.
typedef struct ALT_CLKMGR_SDRPLL_VCO_s ALT_CLKMGR_SDRPLL_VCO_t |
The typedef declaration for register ALT_CLKMGR_SDRPLL_VCO.