Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : bmod

Description

Bus Mode Register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_SDMMC_BMOD_SWR
[1] RW 0x0 ALT_SDMMC_BMOD_FB
[6:2] RW 0x0 ALT_SDMMC_BMOD_DSL
[7] RW 0x0 ALT_SDMMC_BMOD_DE
[10:8] R 0x0 ALT_SDMMC_BMOD_PBL
[31:11] ??? 0x0 UNDEFINED

Field : swr

Software Reset.When set,the DMA Controller resets all its internal registers.

SWR is read/write. It is automatically cleared after 1 clock cycle.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0 No reset - default
ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1 Resets DMA Internal Registers

Field Access Macros:

#define ALT_SDMMC_BMOD_SWR_E_NOSFTRST   0x0
 
#define ALT_SDMMC_BMOD_SWR_E_SFTRST   0x1
 
#define ALT_SDMMC_BMOD_SWR_LSB   0
 
#define ALT_SDMMC_BMOD_SWR_MSB   0
 
#define ALT_SDMMC_BMOD_SWR_WIDTH   1
 
#define ALT_SDMMC_BMOD_SWR_SET_MSK   0x00000001
 
#define ALT_SDMMC_BMOD_SWR_CLR_MSK   0xfffffffe
 
#define ALT_SDMMC_BMOD_SWR_RESET   0x0
 
#define ALT_SDMMC_BMOD_SWR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SDMMC_BMOD_SWR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : fb

Fixed Burst. Controls whether the AHB Master interface performs fixed burst transfers or not. When set,the AHB will use only SINGLE, INCR4, INCR8 or

INCR16 during start of normal burst transfers.When reset,the AHB will use SINGLE and INCR burst transfer operations.

FB is read/write.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0 Non Fixed Burst - default
ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1 AHB Master Fixed Burst

Field Access Macros:

#define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST   0x0
 
#define ALT_SDMMC_BMOD_FB_E_FIXEDBRST   0x1
 
#define ALT_SDMMC_BMOD_FB_LSB   1
 
#define ALT_SDMMC_BMOD_FB_MSB   1
 
#define ALT_SDMMC_BMOD_FB_WIDTH   1
 
#define ALT_SDMMC_BMOD_FB_SET_MSK   0x00000002
 
#define ALT_SDMMC_BMOD_FB_CLR_MSK   0xfffffffd
 
#define ALT_SDMMC_BMOD_FB_RESET   0x0
 
#define ALT_SDMMC_BMOD_FB_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SDMMC_BMOD_FB_SET(value)   (((value) << 1) & 0x00000002)
 

Field : dsl

Descriptor Skip Length. Specifies the number of HWord/Word/Dword (depending on 16/32/64-bit bus) to skip between two unchained descriptors. This is applicable only for dual buffer structure.

DSL is read/write.

Field Access Macros:

#define ALT_SDMMC_BMOD_DSL_LSB   2
 
#define ALT_SDMMC_BMOD_DSL_MSB   6
 
#define ALT_SDMMC_BMOD_DSL_WIDTH   5
 
#define ALT_SDMMC_BMOD_DSL_SET_MSK   0x0000007c
 
#define ALT_SDMMC_BMOD_DSL_CLR_MSK   0xffffff83
 
#define ALT_SDMMC_BMOD_DSL_RESET   0x0
 
#define ALT_SDMMC_BMOD_DSL_GET(value)   (((value) & 0x0000007c) >> 2)
 
#define ALT_SDMMC_BMOD_DSL_SET(value)   (((value) << 2) & 0x0000007c)
 

Field : de

IDMAC Enable. When set, the IDMAC is enabled.

DE is read/write.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_BMOD_DE_E_DISD 0x0 IDMAC Disable
ALT_SDMMC_BMOD_DE_E_END 0x1 IDMAC Enable

Field Access Macros:

#define ALT_SDMMC_BMOD_DE_E_DISD   0x0
 
#define ALT_SDMMC_BMOD_DE_E_END   0x1
 
#define ALT_SDMMC_BMOD_DE_LSB   7
 
#define ALT_SDMMC_BMOD_DE_MSB   7
 
#define ALT_SDMMC_BMOD_DE_WIDTH   1
 
#define ALT_SDMMC_BMOD_DE_SET_MSK   0x00000080
 
#define ALT_SDMMC_BMOD_DE_CLR_MSK   0xffffff7f
 
#define ALT_SDMMC_BMOD_DE_RESET   0x0
 
#define ALT_SDMMC_BMOD_DE_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SDMMC_BMOD_DE_SET(value)   (((value) << 7) & 0x00000080)
 

Field : pbl

Programmable Burst Length. These bits indicate the maximum number of beats to be performed in one IDMAC transaction. The IDMAC will always attempt to burst as specified in PBL each time it starts a Burst transfer on the host bus. The permissible values are 1, 4, 8, 16, 32, 64, 128 and 256. This value is the mirror of MSIZE of FIFOTH register. In order to change this value, write the required value

to FIFOTH register. This is an encode value as follows.

000 1 transfers

001 4 transfers

010 8 transfers

011 16 transfers

100 32 transfers

101 64 transfers

110 128 transfers

111 256 transfers

Transfer unit is either 16, 32, or 64 bits, based on HDATA_WIDTH.

PBL is a read-only value and is applicable only for Data Access; it does not apply to descriptor accesses.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0 Transfer 1
ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1 Transfer 4
ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2 Transfer 8
ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3 Transfer 16
ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4 Transfer 32
ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5 Transfer 64
ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6 Transfer 128
ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7 Transfer 256

Field Access Macros:

#define ALT_SDMMC_BMOD_PBL_E_TRANS1   0x0
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS4   0x1
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS8   0x2
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS16   0x3
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS32   0x4
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS64   0x5
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS128   0x6
 
#define ALT_SDMMC_BMOD_PBL_E_TRANS256   0x7
 
#define ALT_SDMMC_BMOD_PBL_LSB   8
 
#define ALT_SDMMC_BMOD_PBL_MSB   10
 
#define ALT_SDMMC_BMOD_PBL_WIDTH   3
 
#define ALT_SDMMC_BMOD_PBL_SET_MSK   0x00000700
 
#define ALT_SDMMC_BMOD_PBL_CLR_MSK   0xfffff8ff
 
#define ALT_SDMMC_BMOD_PBL_RESET   0x0
 
#define ALT_SDMMC_BMOD_PBL_GET(value)   (((value) & 0x00000700) >> 8)
 
#define ALT_SDMMC_BMOD_PBL_SET(value)   (((value) << 8) & 0x00000700)
 

Data Structures

struct  ALT_SDMMC_BMOD_s
 

Macros

#define ALT_SDMMC_BMOD_RESET   0x00000000
 
#define ALT_SDMMC_BMOD_OFST   0x80
 

Typedefs

typedef struct ALT_SDMMC_BMOD_s ALT_SDMMC_BMOD_t
 

Data Structure Documentation

struct ALT_SDMMC_BMOD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_BMOD.

Data Fields
uint32_t swr: 1 ALT_SDMMC_BMOD_SWR
uint32_t fb: 1 ALT_SDMMC_BMOD_FB
uint32_t dsl: 5 ALT_SDMMC_BMOD_DSL
uint32_t de: 1 ALT_SDMMC_BMOD_DE
const uint32_t pbl: 3 ALT_SDMMC_BMOD_PBL
uint32_t __pad0__: 21 UNDEFINED

Macro Definitions

#define ALT_SDMMC_BMOD_SWR_E_NOSFTRST   0x0

Enumerated value for register field ALT_SDMMC_BMOD_SWR

No reset - default

#define ALT_SDMMC_BMOD_SWR_E_SFTRST   0x1

Enumerated value for register field ALT_SDMMC_BMOD_SWR

Resets DMA Internal Registers

#define ALT_SDMMC_BMOD_SWR_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_SWR register field.

#define ALT_SDMMC_BMOD_SWR_MSB   0

The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_SWR register field.

#define ALT_SDMMC_BMOD_SWR_WIDTH   1

The width in bits of the ALT_SDMMC_BMOD_SWR register field.

#define ALT_SDMMC_BMOD_SWR_SET_MSK   0x00000001

The mask used to set the ALT_SDMMC_BMOD_SWR register field value.

#define ALT_SDMMC_BMOD_SWR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SDMMC_BMOD_SWR register field value.

#define ALT_SDMMC_BMOD_SWR_RESET   0x0

The reset value of the ALT_SDMMC_BMOD_SWR register field.

#define ALT_SDMMC_BMOD_SWR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SDMMC_BMOD_SWR field value from a register.

#define ALT_SDMMC_BMOD_SWR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SDMMC_BMOD_SWR register field value suitable for setting the register.

#define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST   0x0

Enumerated value for register field ALT_SDMMC_BMOD_FB

Non Fixed Burst - default

#define ALT_SDMMC_BMOD_FB_E_FIXEDBRST   0x1

Enumerated value for register field ALT_SDMMC_BMOD_FB

AHB Master Fixed Burst

#define ALT_SDMMC_BMOD_FB_LSB   1

The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_FB register field.

#define ALT_SDMMC_BMOD_FB_MSB   1

The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_FB register field.

#define ALT_SDMMC_BMOD_FB_WIDTH   1

The width in bits of the ALT_SDMMC_BMOD_FB register field.

#define ALT_SDMMC_BMOD_FB_SET_MSK   0x00000002

The mask used to set the ALT_SDMMC_BMOD_FB register field value.

#define ALT_SDMMC_BMOD_FB_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SDMMC_BMOD_FB register field value.

#define ALT_SDMMC_BMOD_FB_RESET   0x0

The reset value of the ALT_SDMMC_BMOD_FB register field.

#define ALT_SDMMC_BMOD_FB_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SDMMC_BMOD_FB field value from a register.

#define ALT_SDMMC_BMOD_FB_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SDMMC_BMOD_FB register field value suitable for setting the register.

#define ALT_SDMMC_BMOD_DSL_LSB   2

The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DSL register field.

#define ALT_SDMMC_BMOD_DSL_MSB   6

The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DSL register field.

#define ALT_SDMMC_BMOD_DSL_WIDTH   5

The width in bits of the ALT_SDMMC_BMOD_DSL register field.

#define ALT_SDMMC_BMOD_DSL_SET_MSK   0x0000007c

The mask used to set the ALT_SDMMC_BMOD_DSL register field value.

#define ALT_SDMMC_BMOD_DSL_CLR_MSK   0xffffff83

The mask used to clear the ALT_SDMMC_BMOD_DSL register field value.

#define ALT_SDMMC_BMOD_DSL_RESET   0x0

The reset value of the ALT_SDMMC_BMOD_DSL register field.

#define ALT_SDMMC_BMOD_DSL_GET (   value)    (((value) & 0x0000007c) >> 2)

Extracts the ALT_SDMMC_BMOD_DSL field value from a register.

#define ALT_SDMMC_BMOD_DSL_SET (   value)    (((value) << 2) & 0x0000007c)

Produces a ALT_SDMMC_BMOD_DSL register field value suitable for setting the register.

#define ALT_SDMMC_BMOD_DE_E_DISD   0x0

Enumerated value for register field ALT_SDMMC_BMOD_DE

IDMAC Disable

#define ALT_SDMMC_BMOD_DE_E_END   0x1

Enumerated value for register field ALT_SDMMC_BMOD_DE

IDMAC Enable

#define ALT_SDMMC_BMOD_DE_LSB   7

The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_DE register field.

#define ALT_SDMMC_BMOD_DE_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_DE register field.

#define ALT_SDMMC_BMOD_DE_WIDTH   1

The width in bits of the ALT_SDMMC_BMOD_DE register field.

#define ALT_SDMMC_BMOD_DE_SET_MSK   0x00000080

The mask used to set the ALT_SDMMC_BMOD_DE register field value.

#define ALT_SDMMC_BMOD_DE_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SDMMC_BMOD_DE register field value.

#define ALT_SDMMC_BMOD_DE_RESET   0x0

The reset value of the ALT_SDMMC_BMOD_DE register field.

#define ALT_SDMMC_BMOD_DE_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SDMMC_BMOD_DE field value from a register.

#define ALT_SDMMC_BMOD_DE_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SDMMC_BMOD_DE register field value suitable for setting the register.

#define ALT_SDMMC_BMOD_PBL_E_TRANS1   0x0

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 1

#define ALT_SDMMC_BMOD_PBL_E_TRANS4   0x1

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 4

#define ALT_SDMMC_BMOD_PBL_E_TRANS8   0x2

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 8

#define ALT_SDMMC_BMOD_PBL_E_TRANS16   0x3

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 16

#define ALT_SDMMC_BMOD_PBL_E_TRANS32   0x4

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 32

#define ALT_SDMMC_BMOD_PBL_E_TRANS64   0x5

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 64

#define ALT_SDMMC_BMOD_PBL_E_TRANS128   0x6

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 128

#define ALT_SDMMC_BMOD_PBL_E_TRANS256   0x7

Enumerated value for register field ALT_SDMMC_BMOD_PBL

Transfer 256

#define ALT_SDMMC_BMOD_PBL_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_BMOD_PBL register field.

#define ALT_SDMMC_BMOD_PBL_MSB   10

The Most Significant Bit (MSB) position of the ALT_SDMMC_BMOD_PBL register field.

#define ALT_SDMMC_BMOD_PBL_WIDTH   3

The width in bits of the ALT_SDMMC_BMOD_PBL register field.

#define ALT_SDMMC_BMOD_PBL_SET_MSK   0x00000700

The mask used to set the ALT_SDMMC_BMOD_PBL register field value.

#define ALT_SDMMC_BMOD_PBL_CLR_MSK   0xfffff8ff

The mask used to clear the ALT_SDMMC_BMOD_PBL register field value.

#define ALT_SDMMC_BMOD_PBL_RESET   0x0

The reset value of the ALT_SDMMC_BMOD_PBL register field.

#define ALT_SDMMC_BMOD_PBL_GET (   value)    (((value) & 0x00000700) >> 8)

Extracts the ALT_SDMMC_BMOD_PBL field value from a register.

#define ALT_SDMMC_BMOD_PBL_SET (   value)    (((value) << 8) & 0x00000700)

Produces a ALT_SDMMC_BMOD_PBL register field value suitable for setting the register.

#define ALT_SDMMC_BMOD_RESET   0x00000000

The reset value of the ALT_SDMMC_BMOD register.

#define ALT_SDMMC_BMOD_OFST   0x80

The byte offset of the ALT_SDMMC_BMOD register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_BMOD.