Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register - ctrl

Description

Contains fields that control the entire Clock Manager.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Boot Mode
[7:1] ??? 0x1 UNDEFINED
[8] RW 0x0 SW Control Boot Clock Enable
[9] RW 0x0 SW Control Boot Clock Select
[31:10] ??? 0x0 UNDEFINED

Field : Boot Mode - bootmode

When set the Clock Manager is in Boot Mode.

In Boot Mode Clock Manager register settings defining clock behavior are ignored and clocks are set to their Boot Mode settings. All clocks will be bypassed and external HW managed counters and dividers will be set to divide by 1.

This bit should only be cleared when clocks have been correctly configured.

This field is set on a cold reset and optionally on a warm reset. SW may set this bit to force the clocks into Boot Mode. SW exits Boot Mode by clearing this bit.

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_LSB   0
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_MSB   0
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_WIDTH   1
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK   0x00000001
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_RESET   0x1
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : SW Control Boot Clock Enable - swctrlbtclken

If set, then Software will take control of the boot_clk mux select. If set, then swctrlbtclksel will determine the mux setting. If not set, the security features will determine the fuse settings.

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_LSB   8
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_MSB   8
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_WIDTH   1
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET_MSK   0x00000100
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_CLR_MSK   0xfffffeff
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_RESET   0x0
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : SW Control Boot Clock Select - swctrlbtclksel

This bit is only used if swctrlbtclken is set.

If 1, boot_clk source will be from cb_intosc_hs_clk divided by 2. If 0, boot_clk source will be from the external oscillator (EOSC1).

This bit is cleared on a cold reset. Warm reset has no affect on this bit.

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_LSB   9
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_MSB   9
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_WIDTH   1
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET_MSK   0x00000200
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_CLR_MSK   0xfffffdff
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_RESET   0x0
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET(value)   (((value) << 9) & 0x00000200)
 

Data Structures

struct  ALT_CLKMGR_CLKMGR_CTL_s
 

Macros

#define ALT_CLKMGR_CLKMGR_CTL_RESET   0x00000003
 
#define ALT_CLKMGR_CLKMGR_CTL_OFST   0x0
 

Typedefs

typedef struct
ALT_CLKMGR_CLKMGR_CTL_s 
ALT_CLKMGR_CLKMGR_CTL_t
 

Data Structure Documentation

struct ALT_CLKMGR_CLKMGR_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_CLKMGR_CTL.

Data Fields
uint32_t bootmode: 1 Boot Mode
uint32_t __pad0__: 7 UNDEFINED
uint32_t swctrlbtclken: 1 SW Control Boot Clock Enable
uint32_t swctrlbtclksel: 1 SW Control Boot Clock Select
uint32_t __pad1__: 22 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_WIDTH   1

The width in bits of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_RESET   0x1

The reset value of the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_CLKMGR_CTL_BOOTMOD field value from a register.

#define ALT_CLKMGR_CLKMGR_CTL_BOOTMOD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_CLKMGR_CTL_BOOTMOD register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_LSB   8

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_MSB   8

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_WIDTH   1

The width in bits of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET_MSK   0x00000100

The mask used to set the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_RESET   0x0

The reset value of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN field value from a register.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKEN register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_LSB   9

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_MSB   9

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_WIDTH   1

The width in bits of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET_MSK   0x00000200

The mask used to set the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_CLR_MSK   0xfffffdff

The mask used to clear the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_RESET   0x0

The reset value of the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL field value from a register.

#define ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_CLKMGR_CLKMGR_CTL_SWCTLBTCLKSEL register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_CTL_RESET   0x00000003

The reset value of the ALT_CLKMGR_CLKMGR_CTL register.

#define ALT_CLKMGR_CLKMGR_CTL_OFST   0x0

The byte offset of the ALT_CLKMGR_CLKMGR_CTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_CLKMGR_CTL.