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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[3:0] | RW | Unknown | CAS Write Latency |
[8:4] | RW | Unknown | Additive Latency |
[13:9] | RW | Unknown | CAS Read Latency |
[17:14] | RW | Unknown | Activate to Activate Delay |
[23:18] | RW | Unknown | Four Activate Window Time |
[31:24] | RW | Unknown | Refresh Cycle Time |
Field : CAS Write Latency - tcwl | |
Memory write latency. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0) |
#define | ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f) |
Field : Additive Latency - tal | |
Memory additive latency. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4) |
#define | ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0) |
Field : CAS Read Latency - tcl | |
Memory read latency. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9) |
#define | ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00) |
Field : Activate to Activate Delay - trrd | |
The activate to activate, different banks timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14) |
#define | ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000) |
Field : Four Activate Window Time - tfaw | |
The four-activate window timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18) |
#define | ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000) |
Field : Refresh Cycle Time - trfc | |
The refresh cycle timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24) |
#define | ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000) |
Data Structures | |
struct | ALT_SDR_CTL_DRAMTIMING1_s |
Macros | |
#define | ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 |
Typedefs | |
typedef struct ALT_SDR_CTL_DRAMTIMING1_s | ALT_SDR_CTL_DRAMTIMING1_t |
struct ALT_SDR_CTL_DRAMTIMING1_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_DRAMTIMING1.
Data Fields | ||
---|---|---|
uint32_t | tcwl: 4 | CAS Write Latency |
uint32_t | tal: 5 | Additive Latency |
uint32_t | tcl: 5 | CAS Read Latency |
uint32_t | trrd: 4 | Activate to Activate Delay |
uint32_t | tfaw: 6 | Four Activate Window Time |
uint32_t | trfc: 8 | Refresh Cycle Time |
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0 |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCWL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCWL register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET | ( | value | ) | (((value) & 0x0000000f) >> 0) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TCWL field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET | ( | value | ) | (((value) << 0) & 0x0000000f) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TCWL register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TAL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TAL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TAL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TAL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TAL register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_GET | ( | value | ) | (((value) & 0x000001f0) >> 4) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TAL field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TAL_SET | ( | value | ) | (((value) << 4) & 0x000001f0) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TAL register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TCL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TCL register field.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TCL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TCL register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TCL register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_GET | ( | value | ) | (((value) & 0x00003e00) >> 9) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TCL field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TCL_SET | ( | value | ) | (((value) << 9) & 0x00003e00) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TCL register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRRD register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRRD register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET | ( | value | ) | (((value) & 0x0003c000) >> 14) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TRRD field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET | ( | value | ) | (((value) << 14) & 0x0003c000) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TRRD register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TFAW register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TFAW register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET | ( | value | ) | (((value) & 0x00fc0000) >> 18) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TFAW field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET | ( | value | ) | (((value) << 18) & 0x00fc0000) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TFAW register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING1_TRFC register field value.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING1_TRFC register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET | ( | value | ) | (((value) & 0xff000000) >> 24) |
Extracts the ALT_SDR_CTL_DRAMTIMING1_TRFC field value from a register.
#define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET | ( | value | ) | (((value) << 24) & 0xff000000) |
Produces a ALT_SDR_CTL_DRAMTIMING1_TRFC register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4 |
The byte offset of the ALT_SDR_CTL_DRAMTIMING1 register from the beginning of the component.
typedef struct ALT_SDR_CTL_DRAMTIMING1_s ALT_SDR_CTL_DRAMTIMING1_t |
The typedef declaration for register ALT_SDR_CTL_DRAMTIMING1.