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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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ddr timing definition.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x1c | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT |
[11:6] | RW | 0x13 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS |
[17:12] | RW | 0x21 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS |
[20:18] | RW | 0x2 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN |
[25:21] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR |
[30:26] | RW | 0xb | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD |
[31] | RW | 0x1 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO |
Field : ACTTOACT | |
Minimum number of scheduler clock cycles between two consecutive DRAM Activate commands on the same bank. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_MSB 5 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_WIDTH 6 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_RESET 0x1c |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET(value) (((value) << 0) & 0x0000003f) |
Field : RDTOMISS | |
Minimum number of scheduler clock cycles between the last DRAM Read command and a new Read or Write command in another page of the same bank. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_MSB 11 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_WIDTH 6 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_RESET 0x13 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_GET(value) (((value) & 0x00000fc0) >> 6) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET(value) (((value) << 6) & 0x00000fc0) |
Field : WRTOMISS | |
Minimum number of scheduler clock cycles between the last DRAM Write command and a new Read or Write command in another page of the same bank. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_MSB 17 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_WIDTH 6 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_RESET 0x21 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_GET(value) (((value) & 0x0003f000) >> 12) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET(value) (((value) << 12) & 0x0003f000) |
Field : BURSTLEN | |
DRAM burst duration on the DRAM data bus in scheduler clock cycles. Also equal to scheduler clock cycles between two DRAM commands. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_MSB 20 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_WIDTH 3 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_RESET 0x2 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_GET(value) (((value) & 0x001c0000) >> 18) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET(value) (((value) << 18) & 0x001c0000) |
Field : RDTOWR | |
Minimum number of scheduler clock cycles between the last DRAM Read command and a Write command. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_MSB 25 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_WIDTH 5 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET_MSK 0x03e00000 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_RESET 0x1 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_GET(value) (((value) & 0x03e00000) >> 21) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET(value) (((value) << 21) & 0x03e00000) |
Field : WRTORD | |
Minimum number of scheduler clock cycles between the last DRAM Write command and a Read command. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_MSB 30 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_WIDTH 5 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET_MSK 0x7c000000 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_RESET 0xb |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_GET(value) (((value) & 0x7c000000) >> 26) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET(value) (((value) << 26) & 0x7c000000) |
Field : BWRATIO | |
Number of cycle minus 1 the DDR chip needs to process one Generic socket word. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_MSB 31 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_WIDTH 1 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET_MSK 0x80000000 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_RESET 0x1 |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s |
Macros | |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RESET 0xac2a14dc |
#define | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_OFST 0xc |
Typedefs | |
typedef struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_t |
struct ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING.
Data Fields | ||
---|---|---|
uint32_t | ACTTOACT: 6 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT |
uint32_t | RDTOMISS: 6 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS |
uint32_t | WRTOMISS: 6 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS |
uint32_t | BURSTLEN: 3 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN |
uint32_t | RDTOWR: 5 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR |
uint32_t | WRTORD: 5 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD |
uint32_t | BWRATIO: 1 | ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO |
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_WIDTH 6 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET_MSK 0x0000003f |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_RESET 0x1c |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_ACTTOACT register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_WIDTH 6 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET_MSK 0x00000fc0 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_CLR_MSK 0xfffff03f |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_RESET 0x13 |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_GET | ( | value | ) | (((value) & 0x00000fc0) >> 6) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS_SET | ( | value | ) | (((value) << 6) & 0x00000fc0) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOMISS register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_WIDTH 6 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET_MSK 0x0003f000 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_CLR_MSK 0xfffc0fff |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_RESET 0x21 |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_GET | ( | value | ) | (((value) & 0x0003f000) >> 12) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS_SET | ( | value | ) | (((value) << 12) & 0x0003f000) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTOMISS register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_WIDTH 3 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET_MSK 0x001c0000 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_CLR_MSK 0xffe3ffff |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_RESET 0x2 |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_GET | ( | value | ) | (((value) & 0x001c0000) >> 18) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN_SET | ( | value | ) | (((value) << 18) & 0x001c0000) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BURSTLEN register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_WIDTH 5 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET_MSK 0x03e00000 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_CLR_MSK 0xfc1fffff |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_RESET 0x1 |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_GET | ( | value | ) | (((value) & 0x03e00000) >> 21) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR_SET | ( | value | ) | (((value) << 21) & 0x03e00000) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RDTOWR register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_WIDTH 5 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET_MSK 0x7c000000 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_CLR_MSK 0x83ffffff |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_RESET 0xb |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_GET | ( | value | ) | (((value) & 0x7c000000) >> 26) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD_SET | ( | value | ) | (((value) << 26) & 0x7c000000) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_WRTORD register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_WIDTH 1 |
The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET_MSK 0x80000000 |
The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_RESET 0x1 |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO field value from a register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_BWRATIO register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_RESET 0xac2a14dc |
The reset value of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING register.
#define ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING_OFST 0xc |
The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING register from the beginning of the component.
The typedef declaration for register ALT_NOC_MPU_DDR_T_SCHED_DDRTIMING.