Altera SoCAL  16.0
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alt_sysmgr.h
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32 
35 #ifndef __ALT_SOCAL_SYSMGR_H__
36 #define __ALT_SOCAL_SYSMGR_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
85 #define ALT_SYSMGR_SILICONID1_REV_E_REV1 0x3
86 
88 #define ALT_SYSMGR_SILICONID1_REV_LSB 0
89 
90 #define ALT_SYSMGR_SILICONID1_REV_MSB 15
91 
92 #define ALT_SYSMGR_SILICONID1_REV_WIDTH 16
93 
94 #define ALT_SYSMGR_SILICONID1_REV_SET_MSK 0x0000ffff
95 
96 #define ALT_SYSMGR_SILICONID1_REV_CLR_MSK 0xffff0000
97 
98 #define ALT_SYSMGR_SILICONID1_REV_RESET 0x1
99 
100 #define ALT_SYSMGR_SILICONID1_REV_GET(value) (((value) & 0x0000ffff) >> 0)
101 
102 #define ALT_SYSMGR_SILICONID1_REV_SET(value) (((value) << 0) & 0x0000ffff)
103 
122 #define ALT_SYSMGR_SILICONID1_ID_E_NIGHTFURY 0x3
123 
125 #define ALT_SYSMGR_SILICONID1_ID_LSB 16
126 
127 #define ALT_SYSMGR_SILICONID1_ID_MSB 31
128 
129 #define ALT_SYSMGR_SILICONID1_ID_WIDTH 16
130 
131 #define ALT_SYSMGR_SILICONID1_ID_SET_MSK 0xffff0000
132 
133 #define ALT_SYSMGR_SILICONID1_ID_CLR_MSK 0x0000ffff
134 
135 #define ALT_SYSMGR_SILICONID1_ID_RESET 0x1
136 
137 #define ALT_SYSMGR_SILICONID1_ID_GET(value) (((value) & 0xffff0000) >> 16)
138 
139 #define ALT_SYSMGR_SILICONID1_ID_SET(value) (((value) << 16) & 0xffff0000)
140 
141 #ifndef __ASSEMBLY__
142 
153 {
154  const uint32_t rev : 16;
155  const uint32_t id : 16;
156 };
157 
160 #endif /* __ASSEMBLY__ */
161 
163 #define ALT_SYSMGR_SILICONID1_RESET 0x00010001
164 
165 #define ALT_SYSMGR_SILICONID1_OFST 0x0
166 
190 #define ALT_SYSMGR_SILICONID2_RSV_LSB 0
191 
192 #define ALT_SYSMGR_SILICONID2_RSV_MSB 31
193 
194 #define ALT_SYSMGR_SILICONID2_RSV_WIDTH 32
195 
196 #define ALT_SYSMGR_SILICONID2_RSV_SET_MSK 0xffffffff
197 
198 #define ALT_SYSMGR_SILICONID2_RSV_CLR_MSK 0x00000000
199 
200 #define ALT_SYSMGR_SILICONID2_RSV_RESET 0x0
201 
202 #define ALT_SYSMGR_SILICONID2_RSV_GET(value) (((value) & 0xffffffff) >> 0)
203 
204 #define ALT_SYSMGR_SILICONID2_RSV_SET(value) (((value) << 0) & 0xffffffff)
205 
206 #ifndef __ASSEMBLY__
207 
218 {
219  const uint32_t rsv : 32;
220 };
221 
224 #endif /* __ASSEMBLY__ */
225 
227 #define ALT_SYSMGR_SILICONID2_RESET 0x00000000
228 
229 #define ALT_SYSMGR_SILICONID2_OFST 0x4
230 
270 #define ALT_SYSMGR_WDDBG_MOD_0_E_CONTINUE 0x0
271 
275 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU0 0x1
276 
280 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSECPU1 0x2
281 
285 #define ALT_SYSMGR_WDDBG_MOD_0_E_PAUSEEITHER 0x3
286 
288 #define ALT_SYSMGR_WDDBG_MOD_0_LSB 0
289 
290 #define ALT_SYSMGR_WDDBG_MOD_0_MSB 1
291 
292 #define ALT_SYSMGR_WDDBG_MOD_0_WIDTH 2
293 
294 #define ALT_SYSMGR_WDDBG_MOD_0_SET_MSK 0x00000003
295 
296 #define ALT_SYSMGR_WDDBG_MOD_0_CLR_MSK 0xfffffffc
297 
298 #define ALT_SYSMGR_WDDBG_MOD_0_RESET 0x3
299 
300 #define ALT_SYSMGR_WDDBG_MOD_0_GET(value) (((value) & 0x00000003) >> 0)
301 
302 #define ALT_SYSMGR_WDDBG_MOD_0_SET(value) (((value) << 0) & 0x00000003)
303 
326 #define ALT_SYSMGR_WDDBG_MOD_1_E_CONTINUE 0x0
327 
331 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU0 0x1
332 
336 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSECPU1 0x2
337 
341 #define ALT_SYSMGR_WDDBG_MOD_1_E_PAUSEEITHER 0x3
342 
344 #define ALT_SYSMGR_WDDBG_MOD_1_LSB 2
345 
346 #define ALT_SYSMGR_WDDBG_MOD_1_MSB 3
347 
348 #define ALT_SYSMGR_WDDBG_MOD_1_WIDTH 2
349 
350 #define ALT_SYSMGR_WDDBG_MOD_1_SET_MSK 0x0000000c
351 
352 #define ALT_SYSMGR_WDDBG_MOD_1_CLR_MSK 0xfffffff3
353 
354 #define ALT_SYSMGR_WDDBG_MOD_1_RESET 0x3
355 
356 #define ALT_SYSMGR_WDDBG_MOD_1_GET(value) (((value) & 0x0000000c) >> 2)
357 
358 #define ALT_SYSMGR_WDDBG_MOD_1_SET(value) (((value) << 2) & 0x0000000c)
359 
360 #ifndef __ASSEMBLY__
361 
372 {
373  uint32_t mode_0 : 2;
374  uint32_t mode_1 : 2;
375  uint32_t : 28;
376 };
377 
379 typedef volatile struct ALT_SYSMGR_WDDBG_s ALT_SYSMGR_WDDBG_t;
380 #endif /* __ASSEMBLY__ */
381 
383 #define ALT_SYSMGR_WDDBG_RESET 0x0000000f
384 
385 #define ALT_SYSMGR_WDDBG_OFST 0x8
386 
426 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_LSB 0
427 
428 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_MSB 0
429 
430 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_WIDTH 1
431 
432 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET_MSK 0x00000001
433 
434 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_CLR_MSK 0xfffffffe
435 
436 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_RESET 0x0
437 
438 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_GET(value) (((value) & 0x00000001) >> 0)
439 
440 #define ALT_SYSMGR_BOOT_FPGA_BSEL_EN_SET(value) (((value) << 0) & 0x00000001)
441 
475 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_RSVDX 0x0
476 
480 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_FPGA 0x1
481 
485 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_1_8V 0x2
486 
490 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_NAND_FLSH_3_0V 0x3
491 
495 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
496 
500 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
501 
505 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_1_8V 0x6
506 
510 #define ALT_SYSMGR_BOOT_FPGA_BSEL_E_QSPI_FLSH_3_0V 0x7
511 
513 #define ALT_SYSMGR_BOOT_FPGA_BSEL_LSB 4
514 
515 #define ALT_SYSMGR_BOOT_FPGA_BSEL_MSB 6
516 
517 #define ALT_SYSMGR_BOOT_FPGA_BSEL_WIDTH 3
518 
519 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET_MSK 0x00000070
520 
521 #define ALT_SYSMGR_BOOT_FPGA_BSEL_CLR_MSK 0xffffff8f
522 
523 #define ALT_SYSMGR_BOOT_FPGA_BSEL_RESET 0x0
524 
525 #define ALT_SYSMGR_BOOT_FPGA_BSEL_GET(value) (((value) & 0x00000070) >> 4)
526 
527 #define ALT_SYSMGR_BOOT_FPGA_BSEL_SET(value) (((value) << 4) & 0x00000070)
528 
555 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_RSVDX 0x0
556 
560 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_FPGA 0x1
561 
565 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_1_8V 0x2
566 
570 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_NAND_FLSH_3_0V 0x3
571 
575 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
576 
580 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
581 
585 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_1_8V 0x6
586 
590 #define ALT_SYSMGR_BOOT_PIN_BSEL_E_QSPI_FLSH_3_0V 0x7
591 
593 #define ALT_SYSMGR_BOOT_PIN_BSEL_LSB 8
594 
595 #define ALT_SYSMGR_BOOT_PIN_BSEL_MSB 10
596 
597 #define ALT_SYSMGR_BOOT_PIN_BSEL_WIDTH 3
598 
599 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET_MSK 0x00000700
600 
601 #define ALT_SYSMGR_BOOT_PIN_BSEL_CLR_MSK 0xfffff8ff
602 
603 #define ALT_SYSMGR_BOOT_PIN_BSEL_RESET 0x0
604 
605 #define ALT_SYSMGR_BOOT_PIN_BSEL_GET(value) (((value) & 0x00000700) >> 8)
606 
607 #define ALT_SYSMGR_BOOT_PIN_BSEL_SET(value) (((value) << 8) & 0x00000700)
608 
634 #define ALT_SYSMGR_BOOT_BSEL_E_RSVDX 0x0
635 
639 #define ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1
640 
644 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2
645 
649 #define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3
650 
654 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4
655 
659 #define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5
660 
664 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6
665 
669 #define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7
670 
672 #define ALT_SYSMGR_BOOT_BSEL_LSB 12
673 
674 #define ALT_SYSMGR_BOOT_BSEL_MSB 14
675 
676 #define ALT_SYSMGR_BOOT_BSEL_WIDTH 3
677 
678 #define ALT_SYSMGR_BOOT_BSEL_SET_MSK 0x00007000
679 
680 #define ALT_SYSMGR_BOOT_BSEL_CLR_MSK 0xffff8fff
681 
682 #define ALT_SYSMGR_BOOT_BSEL_RESET 0x0
683 
684 #define ALT_SYSMGR_BOOT_BSEL_GET(value) (((value) & 0x00007000) >> 12)
685 
686 #define ALT_SYSMGR_BOOT_BSEL_SET(value) (((value) << 12) & 0x00007000)
687 
688 #ifndef __ASSEMBLY__
689 
700 {
701  const uint32_t fpga_bsel_en : 1;
702  uint32_t : 3;
703  const uint32_t fpga_bsel : 3;
704  uint32_t : 1;
705  const uint32_t pin_bsel : 3;
706  uint32_t : 1;
707  const uint32_t bsel : 3;
708  uint32_t : 17;
709 };
710 
712 typedef volatile struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t;
713 #endif /* __ASSEMBLY__ */
714 
716 #define ALT_SYSMGR_BOOT_RESET 0x00000000
717 
718 #define ALT_SYSMGR_BOOT_OFST 0xc
719 
756 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_LSB 0
757 
758 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_MSB 0
759 
760 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_WIDTH 1
761 
762 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET_MSK 0x00000001
763 
764 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_CLR_MSK 0xfffffffe
765 
766 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_RESET 0x0
767 
768 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
769 
770 #define ALT_SYSMGR_MPU_CTL_L2_ECC_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
771 
786 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_LSB 8
787 
788 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_MSB 8
789 
790 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_WIDTH 1
791 
792 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET_MSK 0x00000100
793 
794 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_CLR_MSK 0xfffffeff
795 
796 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_RESET 0x0
797 
798 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_GET(value) (((value) & 0x00000100) >> 8)
799 
800 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_EN_SET(value) (((value) << 8) & 0x00000100)
801 
822 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_SINGLE_BIT 0x0
823 
827 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_E_DOUBLE_BIT 0x1
828 
830 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_LSB 16
831 
832 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_MSB 16
833 
834 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_WIDTH 1
835 
836 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET_MSK 0x00010000
837 
838 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_CLR_MSK 0xfffeffff
839 
840 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_RESET 0x0
841 
842 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_GET(value) (((value) & 0x00010000) >> 16)
843 
844 #define ALT_SYSMGR_MPU_CTL_L2_ECC_INJ_TYPE_SET(value) (((value) << 16) & 0x00010000)
845 
846 #ifndef __ASSEMBLY__
847 
858 {
859  uint32_t ecc_en : 1;
860  uint32_t : 7;
861  uint32_t inj_en : 1;
862  uint32_t : 7;
863  uint32_t inj_type : 1;
864  uint32_t : 15;
865 };
866 
869 #endif /* __ASSEMBLY__ */
870 
872 #define ALT_SYSMGR_MPU_CTL_L2_ECC_RESET 0x00000000
873 
874 #define ALT_SYSMGR_MPU_CTL_L2_ECC_OFST 0x10
875 
921 #define ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA 0x0
922 
926 #define ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX 0x1
927 
929 #define ALT_SYSMGR_DMA_CHANSEL_0_LSB 0
930 
931 #define ALT_SYSMGR_DMA_CHANSEL_0_MSB 0
932 
933 #define ALT_SYSMGR_DMA_CHANSEL_0_WIDTH 1
934 
935 #define ALT_SYSMGR_DMA_CHANSEL_0_SET_MSK 0x00000001
936 
937 #define ALT_SYSMGR_DMA_CHANSEL_0_CLR_MSK 0xfffffffe
938 
939 #define ALT_SYSMGR_DMA_CHANSEL_0_RESET 0x0
940 
941 #define ALT_SYSMGR_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0)
942 
943 #define ALT_SYSMGR_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001)
944 
965 #define ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA 0x0
966 
970 #define ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX 0x1
971 
973 #define ALT_SYSMGR_DMA_CHANSEL_1_LSB 4
974 
975 #define ALT_SYSMGR_DMA_CHANSEL_1_MSB 4
976 
977 #define ALT_SYSMGR_DMA_CHANSEL_1_WIDTH 1
978 
979 #define ALT_SYSMGR_DMA_CHANSEL_1_SET_MSK 0x00000010
980 
981 #define ALT_SYSMGR_DMA_CHANSEL_1_CLR_MSK 0xffffffef
982 
983 #define ALT_SYSMGR_DMA_CHANSEL_1_RESET 0x0
984 
985 #define ALT_SYSMGR_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4)
986 
987 #define ALT_SYSMGR_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010)
988 
1009 #define ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA 0x0
1010 
1014 #define ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR 0x1
1015 
1017 #define ALT_SYSMGR_DMA_CHANSEL_2_LSB 8
1018 
1019 #define ALT_SYSMGR_DMA_CHANSEL_2_MSB 8
1020 
1021 #define ALT_SYSMGR_DMA_CHANSEL_2_WIDTH 1
1022 
1023 #define ALT_SYSMGR_DMA_CHANSEL_2_SET_MSK 0x00000100
1024 
1025 #define ALT_SYSMGR_DMA_CHANSEL_2_CLR_MSK 0xfffffeff
1026 
1027 #define ALT_SYSMGR_DMA_CHANSEL_2_RESET 0x1
1028 
1029 #define ALT_SYSMGR_DMA_CHANSEL_2_GET(value) (((value) & 0x00000100) >> 8)
1030 
1031 #define ALT_SYSMGR_DMA_CHANSEL_2_SET(value) (((value) << 8) & 0x00000100)
1032 
1048 #define ALT_SYSMGR_DMA_MGR_NS_LSB 16
1049 
1050 #define ALT_SYSMGR_DMA_MGR_NS_MSB 16
1051 
1052 #define ALT_SYSMGR_DMA_MGR_NS_WIDTH 1
1053 
1054 #define ALT_SYSMGR_DMA_MGR_NS_SET_MSK 0x00010000
1055 
1056 #define ALT_SYSMGR_DMA_MGR_NS_CLR_MSK 0xfffeffff
1057 
1058 #define ALT_SYSMGR_DMA_MGR_NS_RESET 0x0
1059 
1060 #define ALT_SYSMGR_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16)
1061 
1062 #define ALT_SYSMGR_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000)
1063 
1078 #define ALT_SYSMGR_DMA_IRQ_NS_LSB 24
1079 
1080 #define ALT_SYSMGR_DMA_IRQ_NS_MSB 31
1081 
1082 #define ALT_SYSMGR_DMA_IRQ_NS_WIDTH 8
1083 
1084 #define ALT_SYSMGR_DMA_IRQ_NS_SET_MSK 0xff000000
1085 
1086 #define ALT_SYSMGR_DMA_IRQ_NS_CLR_MSK 0x00ffffff
1087 
1088 #define ALT_SYSMGR_DMA_IRQ_NS_RESET 0x0
1089 
1090 #define ALT_SYSMGR_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24)
1091 
1092 #define ALT_SYSMGR_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000)
1093 
1094 #ifndef __ASSEMBLY__
1095 
1106 {
1107  uint32_t chansel_0 : 1;
1108  uint32_t : 3;
1109  uint32_t chansel_1 : 1;
1110  uint32_t : 3;
1111  uint32_t chansel_2 : 1;
1112  uint32_t : 7;
1113  uint32_t mgr_ns : 1;
1114  uint32_t : 7;
1115  uint32_t irq_ns : 8;
1116 };
1117 
1119 typedef volatile struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t;
1120 #endif /* __ASSEMBLY__ */
1121 
1123 #define ALT_SYSMGR_DMA_RESET 0x00000100
1124 
1125 #define ALT_SYSMGR_DMA_OFST 0x20
1126 
1159 #define ALT_SYSMGR_DMA_PERIPH_NS_LSB 0
1160 
1161 #define ALT_SYSMGR_DMA_PERIPH_NS_MSB 31
1162 
1163 #define ALT_SYSMGR_DMA_PERIPH_NS_WIDTH 32
1164 
1165 #define ALT_SYSMGR_DMA_PERIPH_NS_SET_MSK 0xffffffff
1166 
1167 #define ALT_SYSMGR_DMA_PERIPH_NS_CLR_MSK 0x00000000
1168 
1169 #define ALT_SYSMGR_DMA_PERIPH_NS_RESET 0x0
1170 
1171 #define ALT_SYSMGR_DMA_PERIPH_NS_GET(value) (((value) & 0xffffffff) >> 0)
1172 
1173 #define ALT_SYSMGR_DMA_PERIPH_NS_SET(value) (((value) << 0) & 0xffffffff)
1174 
1175 #ifndef __ASSEMBLY__
1176 
1187 {
1188  uint32_t ns : 32;
1189 };
1190 
1193 #endif /* __ASSEMBLY__ */
1194 
1196 #define ALT_SYSMGR_DMA_PERIPH_RESET 0x00000000
1197 
1198 #define ALT_SYSMGR_DMA_PERIPH_OFST 0x24
1199 
1241 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES0 0x0
1242 
1246 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES45 0x1
1247 
1251 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES90 0x2
1252 
1256 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES135 0x3
1257 
1261 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES180 0x4
1262 
1266 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES225 0x5
1267 
1271 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES270 0x6
1272 
1276 #define ALT_SYSMGR_SDMMC_DRVSEL_E_DEGREES315 0x7
1277 
1279 #define ALT_SYSMGR_SDMMC_DRVSEL_LSB 0
1280 
1281 #define ALT_SYSMGR_SDMMC_DRVSEL_MSB 2
1282 
1283 #define ALT_SYSMGR_SDMMC_DRVSEL_WIDTH 3
1284 
1285 #define ALT_SYSMGR_SDMMC_DRVSEL_SET_MSK 0x00000007
1286 
1287 #define ALT_SYSMGR_SDMMC_DRVSEL_CLR_MSK 0xfffffff8
1288 
1289 #define ALT_SYSMGR_SDMMC_DRVSEL_RESET 0x0
1290 
1291 #define ALT_SYSMGR_SDMMC_DRVSEL_GET(value) (((value) & 0x00000007) >> 0)
1292 
1293 #define ALT_SYSMGR_SDMMC_DRVSEL_SET(value) (((value) << 0) & 0x00000007)
1294 
1320 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES0 0x0
1321 
1325 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES45 0x1
1326 
1330 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES90 0x2
1331 
1335 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES135 0x3
1336 
1340 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES180 0x4
1341 
1345 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES225 0x5
1346 
1350 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES270 0x6
1351 
1355 #define ALT_SYSMGR_SDMMC_SMPLSEL_E_DEGREES315 0x7
1356 
1358 #define ALT_SYSMGR_SDMMC_SMPLSEL_LSB 4
1359 
1360 #define ALT_SYSMGR_SDMMC_SMPLSEL_MSB 6
1361 
1362 #define ALT_SYSMGR_SDMMC_SMPLSEL_WIDTH 3
1363 
1364 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET_MSK 0x00000070
1365 
1366 #define ALT_SYSMGR_SDMMC_SMPLSEL_CLR_MSK 0xffffff8f
1367 
1368 #define ALT_SYSMGR_SDMMC_SMPLSEL_RESET 0x0
1369 
1370 #define ALT_SYSMGR_SDMMC_SMPLSEL_GET(value) (((value) & 0x00000070) >> 4)
1371 
1372 #define ALT_SYSMGR_SDMMC_SMPLSEL_SET(value) (((value) << 4) & 0x00000070)
1373 
1374 #ifndef __ASSEMBLY__
1375 
1386 {
1387  uint32_t drvsel : 3;
1388  uint32_t : 1;
1389  uint32_t smplsel : 3;
1390  uint32_t : 25;
1391 };
1392 
1394 typedef volatile struct ALT_SYSMGR_SDMMC_s ALT_SYSMGR_SDMMC_t;
1395 #endif /* __ASSEMBLY__ */
1396 
1398 #define ALT_SYSMGR_SDMMC_RESET 0x00000000
1399 
1400 #define ALT_SYSMGR_SDMMC_OFST 0x28
1401 
1505 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_LSB 0
1506 
1507 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_MSB 4
1508 
1509 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_WIDTH 5
1510 
1511 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET_MSK 0x0000001f
1512 
1513 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_CLR_MSK 0xffffffe0
1514 
1515 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_RESET 0x3
1516 
1517 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_GET(value) (((value) & 0x0000001f) >> 0)
1518 
1519 #define ALT_SYSMGR_SDMMC_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000001f)
1520 
1521 #ifndef __ASSEMBLY__
1522 
1533 {
1534  uint32_t hprot : 5;
1535  uint32_t : 27;
1536 };
1537 
1540 #endif /* __ASSEMBLY__ */
1541 
1543 #define ALT_SYSMGR_SDMMC_L3MST_RESET 0x00000003
1544 
1545 #define ALT_SYSMGR_SDMMC_L3MST_OFST 0x2c
1546 
1581 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_LSB 0
1582 
1583 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_MSB 0
1584 
1585 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_WIDTH 1
1586 
1587 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET_MSK 0x00000001
1588 
1589 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_CLR_MSK 0xfffffffe
1590 
1591 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_RESET 0x0
1592 
1593 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_GET(value) (((value) & 0x00000001) >> 0)
1594 
1595 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOINIT_SET(value) (((value) << 0) & 0x00000001)
1596 
1607 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_LSB 8
1608 
1609 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_MSB 8
1610 
1611 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_WIDTH 1
1612 
1613 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET_MSK 0x00000100
1614 
1615 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_CLR_MSK 0xfffffeff
1616 
1617 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_RESET 0x0
1618 
1619 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_GET(value) (((value) & 0x00000100) >> 8)
1620 
1621 #define ALT_SYSMGR_NAND_BOOTSTRAP_NOLDB0P0_SET(value) (((value) << 8) & 0x00000100)
1622 
1633 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_LSB 16
1634 
1635 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_MSB 16
1636 
1637 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_WIDTH 1
1638 
1639 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET_MSK 0x00010000
1640 
1641 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_CLR_MSK 0xfffeffff
1642 
1643 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_RESET 0x0
1644 
1645 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_GET(value) (((value) & 0x00010000) >> 16)
1646 
1647 #define ALT_SYSMGR_NAND_BOOTSTRAP_TWOROWADDR_SET(value) (((value) << 16) & 0x00010000)
1648 
1658 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_LSB 24
1659 
1660 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_MSB 24
1661 
1662 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_WIDTH 1
1663 
1664 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET_MSK 0x01000000
1665 
1666 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_CLR_MSK 0xfeffffff
1667 
1668 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_RESET 0x0
1669 
1670 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_GET(value) (((value) & 0x01000000) >> 24)
1671 
1672 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_SET(value) (((value) << 24) & 0x01000000)
1673 
1689 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_LSB 28
1690 
1691 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_MSB 28
1692 
1693 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_WIDTH 1
1694 
1695 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET_MSK 0x10000000
1696 
1697 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_CLR_MSK 0xefffffff
1698 
1699 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_RESET 0x0
1700 
1701 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_GET(value) (((value) & 0x10000000) >> 28)
1702 
1703 #define ALT_SYSMGR_NAND_BOOTSTRAP_PAGE512_X16_SET(value) (((value) << 28) & 0x10000000)
1704 
1705 #ifndef __ASSEMBLY__
1706 
1717 {
1718  uint32_t noinit : 1;
1719  uint32_t : 7;
1720  uint32_t noloadb0p0 : 1;
1721  uint32_t : 7;
1722  uint32_t tworowaddr : 1;
1723  uint32_t : 7;
1724  uint32_t page512 : 1;
1725  uint32_t : 3;
1726  uint32_t page512_x16 : 1;
1727  uint32_t : 3;
1728 };
1729 
1732 #endif /* __ASSEMBLY__ */
1733 
1735 #define ALT_SYSMGR_NAND_BOOTSTRAP_RESET 0x00000000
1736 
1737 #define ALT_SYSMGR_NAND_BOOTSTRAP_OFST 0x30
1738 
1792 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0
1793 
1797 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_BUFF 0x1
1798 
1802 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2
1803 
1807 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1808 
1812 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD1 0x4
1813 
1817 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD2 0x5
1818 
1822 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1823 
1827 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1828 
1832 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD3 0x8
1833 
1837 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD4 0x9
1838 
1842 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1843 
1847 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1848 
1852 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD5 0xc
1853 
1857 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_RSVD6 0xd
1858 
1862 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1863 
1867 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1868 
1870 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_LSB 0
1871 
1872 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_MSB 3
1873 
1874 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_WIDTH 4
1875 
1876 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET_MSK 0x0000000f
1877 
1878 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_CLR_MSK 0xfffffff0
1879 
1880 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_RESET 0x0
1881 
1882 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_GET(value) (((value) & 0x0000000f) >> 0)
1883 
1884 #define ALT_SYSMGR_NAND_L3MST_ARCACHE_0_SET(value) (((value) << 0) & 0x0000000f)
1885 
1919 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0
1920 
1924 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_BUFF 0x1
1925 
1929 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2
1930 
1934 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3
1935 
1939 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD1 0x4
1940 
1944 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD2 0x5
1945 
1949 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6
1950 
1954 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7
1955 
1959 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD3 0x8
1960 
1964 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD4 0x9
1965 
1969 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa
1970 
1974 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb
1975 
1979 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD5 0xc
1980 
1984 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_RSVD6 0xd
1985 
1989 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe
1990 
1994 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf
1995 
1997 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_LSB 4
1998 
1999 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_MSB 7
2000 
2001 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_WIDTH 4
2002 
2003 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET_MSK 0x000000f0
2004 
2005 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_CLR_MSK 0xffffff0f
2006 
2007 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_RESET 0x0
2008 
2009 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_GET(value) (((value) & 0x000000f0) >> 4)
2010 
2011 #define ALT_SYSMGR_NAND_L3MST_AWCACHE_0_SET(value) (((value) << 4) & 0x000000f0)
2012 
2013 #ifndef __ASSEMBLY__
2014 
2025 {
2026  uint32_t arcache_0 : 4;
2027  uint32_t awcache_0 : 4;
2028  uint32_t : 24;
2029 };
2030 
2033 #endif /* __ASSEMBLY__ */
2034 
2036 #define ALT_SYSMGR_NAND_L3MST_RESET 0x00000000
2037 
2038 #define ALT_SYSMGR_NAND_L3MST_OFST 0x34
2039 
2102 #define ALT_SYSMGR_USB0_L3MST_HPROT_LSB 0
2103 
2104 #define ALT_SYSMGR_USB0_L3MST_HPROT_MSB 3
2105 
2106 #define ALT_SYSMGR_USB0_L3MST_HPROT_WIDTH 4
2107 
2108 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET_MSK 0x0000000f
2109 
2110 #define ALT_SYSMGR_USB0_L3MST_HPROT_CLR_MSK 0xfffffff0
2111 
2112 #define ALT_SYSMGR_USB0_L3MST_HPROT_RESET 0x1
2113 
2114 #define ALT_SYSMGR_USB0_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2115 
2116 #define ALT_SYSMGR_USB0_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2117 
2118 #ifndef __ASSEMBLY__
2119 
2130 {
2131  uint32_t hprot : 4;
2132  uint32_t : 28;
2133 };
2134 
2137 #endif /* __ASSEMBLY__ */
2138 
2140 #define ALT_SYSMGR_USB0_L3MST_RESET 0x00000001
2141 
2142 #define ALT_SYSMGR_USB0_L3MST_OFST 0x38
2143 
2206 #define ALT_SYSMGR_USB1_L3MST_HPROT_LSB 0
2207 
2208 #define ALT_SYSMGR_USB1_L3MST_HPROT_MSB 3
2209 
2210 #define ALT_SYSMGR_USB1_L3MST_HPROT_WIDTH 4
2211 
2212 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET_MSK 0x0000000f
2213 
2214 #define ALT_SYSMGR_USB1_L3MST_HPROT_CLR_MSK 0xfffffff0
2215 
2216 #define ALT_SYSMGR_USB1_L3MST_HPROT_RESET 0x1
2217 
2218 #define ALT_SYSMGR_USB1_L3MST_HPROT_GET(value) (((value) & 0x0000000f) >> 0)
2219 
2220 #define ALT_SYSMGR_USB1_L3MST_HPROT_SET(value) (((value) << 0) & 0x0000000f)
2221 
2222 #ifndef __ASSEMBLY__
2223 
2234 {
2235  uint32_t hprot : 4;
2236  uint32_t : 28;
2237 };
2238 
2241 #endif /* __ASSEMBLY__ */
2242 
2244 #define ALT_SYSMGR_USB1_L3MST_RESET 0x00000001
2245 
2246 #define ALT_SYSMGR_USB1_L3MST_OFST 0x3c
2247 
2287 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK 0x0
2288 
2292 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK 0x1
2293 
2295 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_LSB 0
2296 
2297 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_MSB 0
2298 
2299 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_WIDTH 1
2300 
2301 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET_MSK 0x00000001
2302 
2303 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_CLR_MSK 0xfffffffe
2304 
2305 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_RESET 0x0
2306 
2307 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_GET(value) (((value) & 0x00000001) >> 0)
2308 
2309 #define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET(value) (((value) << 0) & 0x00000001)
2310 
2311 #ifndef __ASSEMBLY__
2312 
2323 {
2324  uint32_t ptp_clk_sel : 1;
2325  uint32_t : 31;
2326 };
2327 
2330 #endif /* __ASSEMBLY__ */
2331 
2333 #define ALT_SYSMGR_EMAC_GLOB_RESET 0x00000000
2334 
2335 #define ALT_SYSMGR_EMAC_GLOB_OFST 0x40
2336 
2390 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_GMII_MII 0x0
2391 
2395 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RGMII 0x1
2396 
2400 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RMII 0x2
2401 
2405 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_E_RST 0x3
2406 
2408 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_LSB 0
2409 
2410 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_MSB 1
2411 
2412 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_WIDTH 2
2413 
2414 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET_MSK 0x00000003
2415 
2416 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_CLR_MSK 0xfffffffc
2417 
2418 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_RESET 0x3
2419 
2420 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
2421 
2422 #define ALT_SYSMGR_EMAC0_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
2423 
2446 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_INTERNAL 0x0
2447 
2451 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_E_EXTERNAL 0x1
2452 
2454 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_LSB 8
2455 
2456 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_MSB 8
2457 
2458 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_WIDTH 1
2459 
2460 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET_MSK 0x00000100
2461 
2462 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_CLR_MSK 0xfffffeff
2463 
2464 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_RESET 0x0
2465 
2466 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
2467 
2468 #define ALT_SYSMGR_EMAC0_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
2469 
2491 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_L4_MP_CLK 0x0
2492 
2496 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_E_F2S_AP_CLK 0x1
2497 
2499 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_LSB 12
2500 
2501 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_MSB 12
2502 
2503 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_WIDTH 1
2504 
2505 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET_MSK 0x00001000
2506 
2507 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_CLR_MSK 0xffffefff
2508 
2509 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_RESET 0x0
2510 
2511 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
2512 
2513 #define ALT_SYSMGR_EMAC0_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
2514 
2550 #define ALT_SYSMGR_EMAC0_ARCACHE_E_NONCACHE_NONBUFF 0x0
2551 
2555 #define ALT_SYSMGR_EMAC0_ARCACHE_E_BUFF 0x1
2556 
2560 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_NONALLOC 0x2
2561 
2565 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
2566 
2570 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD1 0x4
2571 
2575 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD2 0x5
2576 
2580 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2581 
2585 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2586 
2590 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD3 0x8
2591 
2595 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD4 0x9
2596 
2600 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2601 
2605 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2606 
2610 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD5 0xc
2611 
2615 #define ALT_SYSMGR_EMAC0_ARCACHE_E_RSVD6 0xd
2616 
2620 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2621 
2625 #define ALT_SYSMGR_EMAC0_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
2626 
2628 #define ALT_SYSMGR_EMAC0_ARCACHE_LSB 16
2629 
2630 #define ALT_SYSMGR_EMAC0_ARCACHE_MSB 19
2631 
2632 #define ALT_SYSMGR_EMAC0_ARCACHE_WIDTH 4
2633 
2634 #define ALT_SYSMGR_EMAC0_ARCACHE_SET_MSK 0x000f0000
2635 
2636 #define ALT_SYSMGR_EMAC0_ARCACHE_CLR_MSK 0xfff0ffff
2637 
2638 #define ALT_SYSMGR_EMAC0_ARCACHE_RESET 0x0
2639 
2640 #define ALT_SYSMGR_EMAC0_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
2641 
2642 #define ALT_SYSMGR_EMAC0_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
2643 
2679 #define ALT_SYSMGR_EMAC0_AWCACHE_E_NONCACHE_NONBUFF 0x0
2680 
2684 #define ALT_SYSMGR_EMAC0_AWCACHE_E_BUFF 0x1
2685 
2689 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_NONALLOC 0x2
2690 
2694 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
2695 
2699 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD1 0x4
2700 
2704 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD2 0x5
2705 
2709 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
2710 
2714 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
2715 
2719 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD3 0x8
2720 
2724 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD4 0x9
2725 
2729 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
2730 
2734 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
2735 
2739 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD5 0xc
2740 
2744 #define ALT_SYSMGR_EMAC0_AWCACHE_E_RSVD6 0xd
2745 
2749 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
2750 
2754 #define ALT_SYSMGR_EMAC0_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
2755 
2757 #define ALT_SYSMGR_EMAC0_AWCACHE_LSB 20
2758 
2759 #define ALT_SYSMGR_EMAC0_AWCACHE_MSB 23
2760 
2761 #define ALT_SYSMGR_EMAC0_AWCACHE_WIDTH 4
2762 
2763 #define ALT_SYSMGR_EMAC0_AWCACHE_SET_MSK 0x00f00000
2764 
2765 #define ALT_SYSMGR_EMAC0_AWCACHE_CLR_MSK 0xff0fffff
2766 
2767 #define ALT_SYSMGR_EMAC0_AWCACHE_RESET 0x0
2768 
2769 #define ALT_SYSMGR_EMAC0_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
2770 
2771 #define ALT_SYSMGR_EMAC0_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
2772 
2813 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_NORMAL 0x0
2814 
2819 #define ALT_SYSMGR_EMAC0_ARPROT_E_SECURE_PRIVILEGED 0x1
2820 
2825 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_NORMAL 0x2
2826 
2831 #define ALT_SYSMGR_EMAC0_ARPROT_E_NONSECURE_PRIVILEGED 0x3
2832 
2834 #define ALT_SYSMGR_EMAC0_ARPROT_LSB 24
2835 
2836 #define ALT_SYSMGR_EMAC0_ARPROT_MSB 25
2837 
2838 #define ALT_SYSMGR_EMAC0_ARPROT_WIDTH 2
2839 
2840 #define ALT_SYSMGR_EMAC0_ARPROT_SET_MSK 0x03000000
2841 
2842 #define ALT_SYSMGR_EMAC0_ARPROT_CLR_MSK 0xfcffffff
2843 
2844 #define ALT_SYSMGR_EMAC0_ARPROT_RESET 0x2
2845 
2846 #define ALT_SYSMGR_EMAC0_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
2847 
2848 #define ALT_SYSMGR_EMAC0_ARPROT_SET(value) (((value) << 24) & 0x03000000)
2849 
2890 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_NORMAL 0x0
2891 
2896 #define ALT_SYSMGR_EMAC0_AWPROT_E_SECURE_PRIVILEGED 0x1
2897 
2902 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_NORMAL 0x2
2903 
2908 #define ALT_SYSMGR_EMAC0_AWPROT_E_NONSECURE_PRIVILEGED 0x3
2909 
2911 #define ALT_SYSMGR_EMAC0_AWPROT_LSB 27
2912 
2913 #define ALT_SYSMGR_EMAC0_AWPROT_MSB 28
2914 
2915 #define ALT_SYSMGR_EMAC0_AWPROT_WIDTH 2
2916 
2917 #define ALT_SYSMGR_EMAC0_AWPROT_SET_MSK 0x18000000
2918 
2919 #define ALT_SYSMGR_EMAC0_AWPROT_CLR_MSK 0xe7ffffff
2920 
2921 #define ALT_SYSMGR_EMAC0_AWPROT_RESET 0x2
2922 
2923 #define ALT_SYSMGR_EMAC0_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
2924 
2925 #define ALT_SYSMGR_EMAC0_AWPROT_SET(value) (((value) << 27) & 0x18000000)
2926 
2948 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
2949 
2953 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
2954 
2956 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_LSB 30
2957 
2958 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_MSB 30
2959 
2960 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_WIDTH 1
2961 
2962 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
2963 
2964 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
2965 
2966 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_RESET 0x0
2967 
2968 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
2969 
2970 #define ALT_SYSMGR_EMAC0_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
2971 
2981 #define ALT_SYSMGR_EMAC0_AXI_DIS_LSB 31
2982 
2983 #define ALT_SYSMGR_EMAC0_AXI_DIS_MSB 31
2984 
2985 #define ALT_SYSMGR_EMAC0_AXI_DIS_WIDTH 1
2986 
2987 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET_MSK 0x80000000
2988 
2989 #define ALT_SYSMGR_EMAC0_AXI_DIS_CLR_MSK 0x7fffffff
2990 
2991 #define ALT_SYSMGR_EMAC0_AXI_DIS_RESET 0x0
2992 
2993 #define ALT_SYSMGR_EMAC0_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
2994 
2995 #define ALT_SYSMGR_EMAC0_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
2996 
2997 #ifndef __ASSEMBLY__
2998 
3009 {
3010  uint32_t phy_intf_sel : 2;
3011  uint32_t : 6;
3012  uint32_t ptp_ref_sel : 1;
3013  uint32_t : 3;
3014  uint32_t app_clk_sel : 1;
3015  uint32_t : 3;
3016  uint32_t arcache : 4;
3017  uint32_t awcache : 4;
3018  uint32_t arprot : 2;
3019  uint32_t : 1;
3020  uint32_t awprot : 2;
3021  uint32_t : 1;
3022  uint32_t sbd_data_endianness : 1;
3023  uint32_t axi_disable : 1;
3024 };
3025 
3027 typedef volatile struct ALT_SYSMGR_EMAC0_s ALT_SYSMGR_EMAC0_t;
3028 #endif /* __ASSEMBLY__ */
3029 
3031 #define ALT_SYSMGR_EMAC0_RESET 0x12000003
3032 
3033 #define ALT_SYSMGR_EMAC0_OFST 0x44
3034 
3088 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_GMII_MII 0x0
3089 
3093 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RGMII 0x1
3094 
3098 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RMII 0x2
3099 
3103 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_E_RST 0x3
3104 
3106 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_LSB 0
3107 
3108 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_MSB 1
3109 
3110 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_WIDTH 2
3111 
3112 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET_MSK 0x00000003
3113 
3114 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3115 
3116 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_RESET 0x3
3117 
3118 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3119 
3120 #define ALT_SYSMGR_EMAC1_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3121 
3144 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_INTERNAL 0x0
3145 
3149 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_E_EXTERNAL 0x1
3150 
3152 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_LSB 8
3153 
3154 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_MSB 8
3155 
3156 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_WIDTH 1
3157 
3158 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET_MSK 0x00000100
3159 
3160 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_CLR_MSK 0xfffffeff
3161 
3162 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_RESET 0x0
3163 
3164 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3165 
3166 #define ALT_SYSMGR_EMAC1_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3167 
3189 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_L4_MP_CLK 0x0
3190 
3194 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3195 
3197 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_LSB 12
3198 
3199 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_MSB 12
3200 
3201 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_WIDTH 1
3202 
3203 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET_MSK 0x00001000
3204 
3205 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_CLR_MSK 0xffffefff
3206 
3207 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_RESET 0x0
3208 
3209 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3210 
3211 #define ALT_SYSMGR_EMAC1_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3212 
3248 #define ALT_SYSMGR_EMAC1_ARCACHE_E_NONCACHE_NONBUFF 0x0
3249 
3253 #define ALT_SYSMGR_EMAC1_ARCACHE_E_BUFF 0x1
3254 
3258 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_NONALLOC 0x2
3259 
3263 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3264 
3268 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD1 0x4
3269 
3273 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD2 0x5
3274 
3278 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3279 
3283 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3284 
3288 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD3 0x8
3289 
3293 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD4 0x9
3294 
3298 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3299 
3303 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3304 
3308 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD5 0xc
3309 
3313 #define ALT_SYSMGR_EMAC1_ARCACHE_E_RSVD6 0xd
3314 
3318 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3319 
3323 #define ALT_SYSMGR_EMAC1_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
3324 
3326 #define ALT_SYSMGR_EMAC1_ARCACHE_LSB 16
3327 
3328 #define ALT_SYSMGR_EMAC1_ARCACHE_MSB 19
3329 
3330 #define ALT_SYSMGR_EMAC1_ARCACHE_WIDTH 4
3331 
3332 #define ALT_SYSMGR_EMAC1_ARCACHE_SET_MSK 0x000f0000
3333 
3334 #define ALT_SYSMGR_EMAC1_ARCACHE_CLR_MSK 0xfff0ffff
3335 
3336 #define ALT_SYSMGR_EMAC1_ARCACHE_RESET 0x0
3337 
3338 #define ALT_SYSMGR_EMAC1_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
3339 
3340 #define ALT_SYSMGR_EMAC1_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
3341 
3377 #define ALT_SYSMGR_EMAC1_AWCACHE_E_NONCACHE_NONBUFF 0x0
3378 
3382 #define ALT_SYSMGR_EMAC1_AWCACHE_E_BUFF 0x1
3383 
3387 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_NONALLOC 0x2
3388 
3392 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
3393 
3397 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD1 0x4
3398 
3402 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD2 0x5
3403 
3407 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3408 
3412 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3413 
3417 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD3 0x8
3418 
3422 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD4 0x9
3423 
3427 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3428 
3432 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
3433 
3437 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD5 0xc
3438 
3442 #define ALT_SYSMGR_EMAC1_AWCACHE_E_RSVD6 0xd
3443 
3447 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
3448 
3452 #define ALT_SYSMGR_EMAC1_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
3453 
3455 #define ALT_SYSMGR_EMAC1_AWCACHE_LSB 20
3456 
3457 #define ALT_SYSMGR_EMAC1_AWCACHE_MSB 23
3458 
3459 #define ALT_SYSMGR_EMAC1_AWCACHE_WIDTH 4
3460 
3461 #define ALT_SYSMGR_EMAC1_AWCACHE_SET_MSK 0x00f00000
3462 
3463 #define ALT_SYSMGR_EMAC1_AWCACHE_CLR_MSK 0xff0fffff
3464 
3465 #define ALT_SYSMGR_EMAC1_AWCACHE_RESET 0x0
3466 
3467 #define ALT_SYSMGR_EMAC1_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
3468 
3469 #define ALT_SYSMGR_EMAC1_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
3470 
3511 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_NORMAL 0x0
3512 
3517 #define ALT_SYSMGR_EMAC1_ARPROT_E_SECURE_PRIVILEGED 0x1
3518 
3523 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_NORMAL 0x2
3524 
3529 #define ALT_SYSMGR_EMAC1_ARPROT_E_NONSECURE_PRIVILEGED 0x3
3530 
3532 #define ALT_SYSMGR_EMAC1_ARPROT_LSB 24
3533 
3534 #define ALT_SYSMGR_EMAC1_ARPROT_MSB 25
3535 
3536 #define ALT_SYSMGR_EMAC1_ARPROT_WIDTH 2
3537 
3538 #define ALT_SYSMGR_EMAC1_ARPROT_SET_MSK 0x03000000
3539 
3540 #define ALT_SYSMGR_EMAC1_ARPROT_CLR_MSK 0xfcffffff
3541 
3542 #define ALT_SYSMGR_EMAC1_ARPROT_RESET 0x2
3543 
3544 #define ALT_SYSMGR_EMAC1_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
3545 
3546 #define ALT_SYSMGR_EMAC1_ARPROT_SET(value) (((value) << 24) & 0x03000000)
3547 
3588 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_NORMAL 0x0
3589 
3594 #define ALT_SYSMGR_EMAC1_AWPROT_E_SECURE_PRIVILEGED 0x1
3595 
3600 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_NORMAL 0x2
3601 
3606 #define ALT_SYSMGR_EMAC1_AWPROT_E_NONSECURE_PRIVILEGED 0x3
3607 
3609 #define ALT_SYSMGR_EMAC1_AWPROT_LSB 27
3610 
3611 #define ALT_SYSMGR_EMAC1_AWPROT_MSB 28
3612 
3613 #define ALT_SYSMGR_EMAC1_AWPROT_WIDTH 2
3614 
3615 #define ALT_SYSMGR_EMAC1_AWPROT_SET_MSK 0x18000000
3616 
3617 #define ALT_SYSMGR_EMAC1_AWPROT_CLR_MSK 0xe7ffffff
3618 
3619 #define ALT_SYSMGR_EMAC1_AWPROT_RESET 0x2
3620 
3621 #define ALT_SYSMGR_EMAC1_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
3622 
3623 #define ALT_SYSMGR_EMAC1_AWPROT_SET(value) (((value) << 27) & 0x18000000)
3624 
3646 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
3647 
3651 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
3652 
3654 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_LSB 30
3655 
3656 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_MSB 30
3657 
3658 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_WIDTH 1
3659 
3660 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
3661 
3662 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
3663 
3664 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_RESET 0x0
3665 
3666 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
3667 
3668 #define ALT_SYSMGR_EMAC1_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
3669 
3679 #define ALT_SYSMGR_EMAC1_AXI_DIS_LSB 31
3680 
3681 #define ALT_SYSMGR_EMAC1_AXI_DIS_MSB 31
3682 
3683 #define ALT_SYSMGR_EMAC1_AXI_DIS_WIDTH 1
3684 
3685 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET_MSK 0x80000000
3686 
3687 #define ALT_SYSMGR_EMAC1_AXI_DIS_CLR_MSK 0x7fffffff
3688 
3689 #define ALT_SYSMGR_EMAC1_AXI_DIS_RESET 0x0
3690 
3691 #define ALT_SYSMGR_EMAC1_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
3692 
3693 #define ALT_SYSMGR_EMAC1_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
3694 
3695 #ifndef __ASSEMBLY__
3696 
3707 {
3708  uint32_t phy_intf_sel : 2;
3709  uint32_t : 6;
3710  uint32_t ptp_ref_sel : 1;
3711  uint32_t : 3;
3712  uint32_t app_clk_sel : 1;
3713  uint32_t : 3;
3714  uint32_t arcache : 4;
3715  uint32_t awcache : 4;
3716  uint32_t arprot : 2;
3717  uint32_t : 1;
3718  uint32_t awprot : 2;
3719  uint32_t : 1;
3720  uint32_t sbd_data_endianness : 1;
3721  uint32_t axi_disable : 1;
3722 };
3723 
3725 typedef volatile struct ALT_SYSMGR_EMAC1_s ALT_SYSMGR_EMAC1_t;
3726 #endif /* __ASSEMBLY__ */
3727 
3729 #define ALT_SYSMGR_EMAC1_RESET 0x12000003
3730 
3731 #define ALT_SYSMGR_EMAC1_OFST 0x48
3732 
3786 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_GMII_MII 0x0
3787 
3791 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RGMII 0x1
3792 
3796 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RMII 0x2
3797 
3801 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_E_RST 0x3
3802 
3804 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_LSB 0
3805 
3806 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_MSB 1
3807 
3808 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_WIDTH 2
3809 
3810 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET_MSK 0x00000003
3811 
3812 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_CLR_MSK 0xfffffffc
3813 
3814 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_RESET 0x3
3815 
3816 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_GET(value) (((value) & 0x00000003) >> 0)
3817 
3818 #define ALT_SYSMGR_EMAC2_PHY_INTF_SEL_SET(value) (((value) << 0) & 0x00000003)
3819 
3842 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_INTERNAL 0x0
3843 
3847 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_E_EXTERNAL 0x1
3848 
3850 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_LSB 8
3851 
3852 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_MSB 8
3853 
3854 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_WIDTH 1
3855 
3856 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET_MSK 0x00000100
3857 
3858 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_CLR_MSK 0xfffffeff
3859 
3860 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_RESET 0x0
3861 
3862 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_GET(value) (((value) & 0x00000100) >> 8)
3863 
3864 #define ALT_SYSMGR_EMAC2_PTP_REF_SEL_SET(value) (((value) << 8) & 0x00000100)
3865 
3887 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_L4_MP_CLK 0x0
3888 
3892 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_E_F2S_AP_CLK 0x1
3893 
3895 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_LSB 12
3896 
3897 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_MSB 12
3898 
3899 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_WIDTH 1
3900 
3901 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET_MSK 0x00001000
3902 
3903 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_CLR_MSK 0xffffefff
3904 
3905 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_RESET 0x0
3906 
3907 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_GET(value) (((value) & 0x00001000) >> 12)
3908 
3909 #define ALT_SYSMGR_EMAC2_APP_CLK_SEL_SET(value) (((value) << 12) & 0x00001000)
3910 
3946 #define ALT_SYSMGR_EMAC2_ARCACHE_E_NONCACHE_NONBUFF 0x0
3947 
3951 #define ALT_SYSMGR_EMAC2_ARCACHE_E_BUFF 0x1
3952 
3956 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_NONALLOC 0x2
3957 
3961 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_BUFF_NONALLOC 0x3
3962 
3966 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD1 0x4
3967 
3971 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD2 0x5
3972 
3976 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
3977 
3981 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_RDALLOC 0x7
3982 
3986 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD3 0x8
3987 
3991 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD4 0x9
3992 
3996 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
3997 
4001 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4002 
4006 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD5 0xc
4007 
4011 #define ALT_SYSMGR_EMAC2_ARCACHE_E_RSVD6 0xd
4012 
4016 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4017 
4021 #define ALT_SYSMGR_EMAC2_ARCACHE_E_CACHE_WRBACK_ALLOC 0xf
4022 
4024 #define ALT_SYSMGR_EMAC2_ARCACHE_LSB 16
4025 
4026 #define ALT_SYSMGR_EMAC2_ARCACHE_MSB 19
4027 
4028 #define ALT_SYSMGR_EMAC2_ARCACHE_WIDTH 4
4029 
4030 #define ALT_SYSMGR_EMAC2_ARCACHE_SET_MSK 0x000f0000
4031 
4032 #define ALT_SYSMGR_EMAC2_ARCACHE_CLR_MSK 0xfff0ffff
4033 
4034 #define ALT_SYSMGR_EMAC2_ARCACHE_RESET 0x0
4035 
4036 #define ALT_SYSMGR_EMAC2_ARCACHE_GET(value) (((value) & 0x000f0000) >> 16)
4037 
4038 #define ALT_SYSMGR_EMAC2_ARCACHE_SET(value) (((value) << 16) & 0x000f0000)
4039 
4075 #define ALT_SYSMGR_EMAC2_AWCACHE_E_NONCACHE_NONBUFF 0x0
4076 
4080 #define ALT_SYSMGR_EMAC2_AWCACHE_E_BUFF 0x1
4081 
4085 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_NONALLOC 0x2
4086 
4090 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_BUFF_NONALLOC 0x3
4091 
4095 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD1 0x4
4096 
4100 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD2 0x5
4101 
4105 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_RDALLOC 0x6
4106 
4110 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_RDALLOC 0x7
4111 
4115 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD3 0x8
4116 
4120 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD4 0x9
4121 
4125 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_WRALLOC 0xa
4126 
4130 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_WRALLOC 0xb
4131 
4135 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD5 0xc
4136 
4140 #define ALT_SYSMGR_EMAC2_AWCACHE_E_RSVD6 0xd
4141 
4145 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRTHRU_ALLOC 0xe
4146 
4150 #define ALT_SYSMGR_EMAC2_AWCACHE_E_CACHE_WRBACK_ALLOC 0xf
4151 
4153 #define ALT_SYSMGR_EMAC2_AWCACHE_LSB 20
4154 
4155 #define ALT_SYSMGR_EMAC2_AWCACHE_MSB 23
4156 
4157 #define ALT_SYSMGR_EMAC2_AWCACHE_WIDTH 4
4158 
4159 #define ALT_SYSMGR_EMAC2_AWCACHE_SET_MSK 0x00f00000
4160 
4161 #define ALT_SYSMGR_EMAC2_AWCACHE_CLR_MSK 0xff0fffff
4162 
4163 #define ALT_SYSMGR_EMAC2_AWCACHE_RESET 0x0
4164 
4165 #define ALT_SYSMGR_EMAC2_AWCACHE_GET(value) (((value) & 0x00f00000) >> 20)
4166 
4167 #define ALT_SYSMGR_EMAC2_AWCACHE_SET(value) (((value) << 20) & 0x00f00000)
4168 
4209 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_NORMAL 0x0
4210 
4215 #define ALT_SYSMGR_EMAC2_ARPROT_E_SECURE_PRIVILEGED 0x1
4216 
4221 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_NORMAL 0x2
4222 
4227 #define ALT_SYSMGR_EMAC2_ARPROT_E_NONSECURE_PRIVILEGED 0x3
4228 
4230 #define ALT_SYSMGR_EMAC2_ARPROT_LSB 24
4231 
4232 #define ALT_SYSMGR_EMAC2_ARPROT_MSB 25
4233 
4234 #define ALT_SYSMGR_EMAC2_ARPROT_WIDTH 2
4235 
4236 #define ALT_SYSMGR_EMAC2_ARPROT_SET_MSK 0x03000000
4237 
4238 #define ALT_SYSMGR_EMAC2_ARPROT_CLR_MSK 0xfcffffff
4239 
4240 #define ALT_SYSMGR_EMAC2_ARPROT_RESET 0x2
4241 
4242 #define ALT_SYSMGR_EMAC2_ARPROT_GET(value) (((value) & 0x03000000) >> 24)
4243 
4244 #define ALT_SYSMGR_EMAC2_ARPROT_SET(value) (((value) << 24) & 0x03000000)
4245 
4286 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_NORMAL 0x0
4287 
4292 #define ALT_SYSMGR_EMAC2_AWPROT_E_SECURE_PRIVILEGED 0x1
4293 
4298 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_NORMAL 0x2
4299 
4304 #define ALT_SYSMGR_EMAC2_AWPROT_E_NONSECURE_PRIVILEGED 0x3
4305 
4307 #define ALT_SYSMGR_EMAC2_AWPROT_LSB 27
4308 
4309 #define ALT_SYSMGR_EMAC2_AWPROT_MSB 28
4310 
4311 #define ALT_SYSMGR_EMAC2_AWPROT_WIDTH 2
4312 
4313 #define ALT_SYSMGR_EMAC2_AWPROT_SET_MSK 0x18000000
4314 
4315 #define ALT_SYSMGR_EMAC2_AWPROT_CLR_MSK 0xe7ffffff
4316 
4317 #define ALT_SYSMGR_EMAC2_AWPROT_RESET 0x2
4318 
4319 #define ALT_SYSMGR_EMAC2_AWPROT_GET(value) (((value) & 0x18000000) >> 27)
4320 
4321 #define ALT_SYSMGR_EMAC2_AWPROT_SET(value) (((value) << 27) & 0x18000000)
4322 
4344 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_LITTLE_ENDIAN 0x0
4345 
4349 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_E_BIG_ENDIAN 0x1
4350 
4352 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_LSB 30
4353 
4354 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_MSB 30
4355 
4356 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_WIDTH 1
4357 
4358 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET_MSK 0x40000000
4359 
4360 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_CLR_MSK 0xbfffffff
4361 
4362 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_RESET 0x0
4363 
4364 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_GET(value) (((value) & 0x40000000) >> 30)
4365 
4366 #define ALT_SYSMGR_EMAC2_SBD_DATA_ENDIANNESS_SET(value) (((value) << 30) & 0x40000000)
4367 
4377 #define ALT_SYSMGR_EMAC2_AXI_DIS_LSB 31
4378 
4379 #define ALT_SYSMGR_EMAC2_AXI_DIS_MSB 31
4380 
4381 #define ALT_SYSMGR_EMAC2_AXI_DIS_WIDTH 1
4382 
4383 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET_MSK 0x80000000
4384 
4385 #define ALT_SYSMGR_EMAC2_AXI_DIS_CLR_MSK 0x7fffffff
4386 
4387 #define ALT_SYSMGR_EMAC2_AXI_DIS_RESET 0x0
4388 
4389 #define ALT_SYSMGR_EMAC2_AXI_DIS_GET(value) (((value) & 0x80000000) >> 31)
4390 
4391 #define ALT_SYSMGR_EMAC2_AXI_DIS_SET(value) (((value) << 31) & 0x80000000)
4392 
4393 #ifndef __ASSEMBLY__
4394 
4405 {
4406  uint32_t phy_intf_sel : 2;
4407  uint32_t : 6;
4408  uint32_t ptp_ref_sel : 1;
4409  uint32_t : 3;
4410  uint32_t app_clk_sel : 1;
4411  uint32_t : 3;
4412  uint32_t arcache : 4;
4413  uint32_t awcache : 4;
4414  uint32_t arprot : 2;
4415  uint32_t : 1;
4416  uint32_t awprot : 2;
4417  uint32_t : 1;
4418  uint32_t sbd_data_endianness : 1;
4419  uint32_t axi_disable : 1;
4420 };
4421 
4423 typedef volatile struct ALT_SYSMGR_EMAC2_s ALT_SYSMGR_EMAC2_t;
4424 #endif /* __ASSEMBLY__ */
4425 
4427 #define ALT_SYSMGR_EMAC2_RESET 0x12000003
4428 
4429 #define ALT_SYSMGR_EMAC2_OFST 0x4c
4430 
4466 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_DIS 0x0
4467 
4471 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_E_EN 0x1
4472 
4474 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_LSB 0
4475 
4476 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_MSB 0
4477 
4478 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_WIDTH 1
4479 
4480 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET_MSK 0x00000001
4481 
4482 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_CLR_MSK 0xfffffffe
4483 
4484 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_RESET 0x1
4485 
4486 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_GET(value) (((value) & 0x00000001) >> 0)
4487 
4488 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_INTF_SET(value) (((value) << 0) & 0x00000001)
4489 
4490 #ifndef __ASSEMBLY__
4491 
4502 {
4503  uint32_t intf : 1;
4504  uint32_t : 31;
4505 };
4506 
4509 #endif /* __ASSEMBLY__ */
4510 
4512 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_RESET 0x00000001
4513 
4514 #define ALT_SYSMGR_FPGAINTF_EN_GLOB_OFST 0x60
4515 
4558 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS 0x0
4559 
4563 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN 0x1
4564 
4566 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_LSB 0
4567 
4568 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_MSB 0
4569 
4570 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_WIDTH 1
4571 
4572 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET_MSK 0x00000001
4573 
4574 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_CLR_MSK 0xfffffffe
4575 
4576 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_RESET 0x1
4577 
4578 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_GET(value) (((value) & 0x00000001) >> 0)
4579 
4580 #define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET(value) (((value) << 0) & 0x00000001)
4581 
4605 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS 0x0
4606 
4610 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN 0x1
4611 
4613 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_LSB 8
4614 
4615 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_MSB 8
4616 
4617 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_WIDTH 1
4618 
4619 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET_MSK 0x00000100
4620 
4621 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_CLR_MSK 0xfffffeff
4622 
4623 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_RESET 0x1
4624 
4625 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_GET(value) (((value) & 0x00000100) >> 8)
4626 
4627 #define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET(value) (((value) << 8) & 0x00000100)
4628 
4651 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS 0x0
4652 
4656 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN 0x1
4657 
4659 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_LSB 16
4660 
4661 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_MSB 16
4662 
4663 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_WIDTH 1
4664 
4665 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET_MSK 0x00010000
4666 
4667 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_CLR_MSK 0xfffeffff
4668 
4669 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_RESET 0x1
4670 
4671 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_GET(value) (((value) & 0x00010000) >> 16)
4672 
4673 #define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET(value) (((value) << 16) & 0x00010000)
4674 
4675 #ifndef __ASSEMBLY__
4676 
4687 {
4688  uint32_t rstreq : 1;
4689  uint32_t : 7;
4690  uint32_t cfgio : 1;
4691  uint32_t : 7;
4692  uint32_t bscan : 1;
4693  uint32_t : 15;
4694 };
4695 
4698 #endif /* __ASSEMBLY__ */
4699 
4701 #define ALT_SYSMGR_FPGAINTF_EN_0_RESET 0xffffffff
4702 
4703 #define ALT_SYSMGR_FPGAINTF_EN_0_OFST 0x64
4704 
4747 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_DIS 0x0
4748 
4752 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_E_EN 0x1
4753 
4755 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_LSB 4
4756 
4757 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_MSB 4
4758 
4759 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_WIDTH 1
4760 
4761 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET_MSK 0x00000010
4762 
4763 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_CLR_MSK 0xffffffef
4764 
4765 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_RESET 0x1
4766 
4767 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_GET(value) (((value) & 0x00000010) >> 4)
4768 
4769 #define ALT_SYSMGR_FPGAINTF_EN_1_TRACE_SET(value) (((value) << 4) & 0x00000010)
4770 
4791 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_DIS 0x0
4792 
4796 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_E_EN 0x1
4797 
4799 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_LSB 8
4800 
4801 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_MSB 8
4802 
4803 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_WIDTH 1
4804 
4805 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET_MSK 0x00000100
4806 
4807 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_CLR_MSK 0xfffffeff
4808 
4809 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_RESET 0x1
4810 
4811 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_GET(value) (((value) & 0x00000100) >> 8)
4812 
4813 #define ALT_SYSMGR_FPGAINTF_EN_1_DBGAPB_SET(value) (((value) << 8) & 0x00000100)
4814 
4835 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_DIS 0x0
4836 
4840 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_E_EN 0x1
4841 
4843 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_LSB 16
4844 
4845 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_MSB 16
4846 
4847 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_WIDTH 1
4848 
4849 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET_MSK 0x00010000
4850 
4851 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_CLR_MSK 0xfffeffff
4852 
4853 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_RESET 0x1
4854 
4855 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_GET(value) (((value) & 0x00010000) >> 16)
4856 
4857 #define ALT_SYSMGR_FPGAINTF_EN_1_STMEVENT_SET(value) (((value) << 16) & 0x00010000)
4858 
4880 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_DIS 0x0
4881 
4885 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_E_EN 0x1
4886 
4888 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_LSB 24
4889 
4890 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_MSB 24
4891 
4892 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_WIDTH 1
4893 
4894 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET_MSK 0x01000000
4895 
4896 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_CLR_MSK 0xfeffffff
4897 
4898 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_RESET 0x1
4899 
4900 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_GET(value) (((value) & 0x01000000) >> 24)
4901 
4902 #define ALT_SYSMGR_FPGAINTF_EN_1_CTMTRIGGER_SET(value) (((value) << 24) & 0x01000000)
4903 
4904 #ifndef __ASSEMBLY__
4905 
4916 {
4917  uint32_t : 4;
4918  uint32_t trace : 1;
4919  uint32_t : 3;
4920  uint32_t dbgapb : 1;
4921  uint32_t : 7;
4922  uint32_t stmevent : 1;
4923  uint32_t : 7;
4924  uint32_t ctmtrigger : 1;
4925  uint32_t : 7;
4926 };
4927 
4930 #endif /* __ASSEMBLY__ */
4931 
4933 #define ALT_SYSMGR_FPGAINTF_EN_1_RESET 0xffffffff
4934 
4935 #define ALT_SYSMGR_FPGAINTF_EN_1_OFST 0x68
4936 
4979 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS 0x0
4980 
4984 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN 0x1
4985 
4987 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_LSB 4
4988 
4989 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_MSB 4
4990 
4991 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_WIDTH 1
4992 
4993 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010
4994 
4995 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef
4996 
4997 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_RESET 0x0
4998 
4999 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4)
5000 
5001 #define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010)
5002 
5023 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS 0x0
5024 
5028 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN 0x1
5029 
5031 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_LSB 8
5032 
5033 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_MSB 8
5034 
5035 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_WIDTH 1
5036 
5037 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100
5038 
5039 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff
5040 
5041 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_RESET 0x0
5042 
5043 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8)
5044 
5045 #define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100)
5046 
5069 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS 0x0
5070 
5074 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN 0x1
5075 
5077 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_LSB 16
5078 
5079 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_MSB 16
5080 
5081 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_WIDTH 1
5082 
5083 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000
5084 
5085 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff
5086 
5087 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_RESET 0x0
5088 
5089 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16)
5090 
5091 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000)
5092 
5115 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS 0x0
5116 
5120 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN 0x1
5121 
5123 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_LSB 24
5124 
5125 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_MSB 24
5126 
5127 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_WIDTH 1
5128 
5129 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000
5130 
5131 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff
5132 
5133 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_RESET 0x0
5134 
5135 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24)
5136 
5137 #define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000)
5138 
5139 #ifndef __ASSEMBLY__
5140 
5151 {
5152  uint32_t : 4;
5153  uint32_t nand : 1;
5154  uint32_t : 3;
5155  uint32_t sdmmc : 1;
5156  uint32_t : 7;
5157  uint32_t spim_0 : 1;
5158  uint32_t : 7;
5159  uint32_t spim_1 : 1;
5160  uint32_t : 7;
5161 };
5162 
5165 #endif /* __ASSEMBLY__ */
5166 
5168 #define ALT_SYSMGR_FPGAINTF_EN_2_RESET 0x00000000
5169 
5170 #define ALT_SYSMGR_FPGAINTF_EN_2_OFST 0x6c
5171 
5219 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_DIS 0x0
5220 
5224 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_E_EN 0x1
5225 
5227 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_LSB 0
5228 
5229 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_MSB 0
5230 
5231 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_WIDTH 1
5232 
5233 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET_MSK 0x00000001
5234 
5235 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_CLR_MSK 0xfffffffe
5236 
5237 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_RESET 0x0
5238 
5239 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_GET(value) (((value) & 0x00000001) >> 0)
5240 
5241 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SET(value) (((value) << 0) & 0x00000001)
5242 
5262 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_DIS 0x0
5263 
5267 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_E_EN 0x1
5268 
5270 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_LSB 4
5271 
5272 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_MSB 4
5273 
5274 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_WIDTH 1
5275 
5276 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET_MSK 0x00000010
5277 
5278 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_CLR_MSK 0xffffffef
5279 
5280 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_RESET 0x0
5281 
5282 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_GET(value) (((value) & 0x00000010) >> 4)
5283 
5284 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_0_SWITCH_SET(value) (((value) << 4) & 0x00000010)
5285 
5308 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_DIS 0x0
5309 
5313 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_E_EN 0x1
5314 
5316 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_LSB 8
5317 
5318 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_MSB 8
5319 
5320 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_WIDTH 1
5321 
5322 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET_MSK 0x00000100
5323 
5324 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_CLR_MSK 0xfffffeff
5325 
5326 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_RESET 0x0
5327 
5328 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_GET(value) (((value) & 0x00000100) >> 8)
5329 
5330 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SET(value) (((value) << 8) & 0x00000100)
5331 
5351 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_DIS 0x0
5352 
5356 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_E_EN 0x1
5357 
5359 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_LSB 12
5360 
5361 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_MSB 12
5362 
5363 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_WIDTH 1
5364 
5365 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET_MSK 0x00001000
5366 
5367 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_CLR_MSK 0xffffefff
5368 
5369 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_RESET 0x0
5370 
5371 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_GET(value) (((value) & 0x00001000) >> 12)
5372 
5373 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_1_SWITCH_SET(value) (((value) << 12) & 0x00001000)
5374 
5397 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_DIS 0x0
5398 
5402 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_E_EN 0x1
5403 
5405 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_LSB 16
5406 
5407 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_MSB 16
5408 
5409 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_WIDTH 1
5410 
5411 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET_MSK 0x00010000
5412 
5413 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_CLR_MSK 0xfffeffff
5414 
5415 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_RESET 0x0
5416 
5417 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_GET(value) (((value) & 0x00010000) >> 16)
5418 
5419 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SET(value) (((value) << 16) & 0x00010000)
5420 
5440 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_DIS 0x0
5441 
5445 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_E_EN 0x1
5446 
5448 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_LSB 20
5449 
5450 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_MSB 20
5451 
5452 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_WIDTH 1
5453 
5454 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET_MSK 0x00100000
5455 
5456 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_CLR_MSK 0xffefffff
5457 
5458 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_RESET 0x0
5459 
5460 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_GET(value) (((value) & 0x00100000) >> 20)
5461 
5462 #define ALT_SYSMGR_FPGAINTF_EN_3_EMAC_2_SWITCH_SET(value) (((value) << 20) & 0x00100000)
5463 
5464 #ifndef __ASSEMBLY__
5465 
5476 {
5477  uint32_t emac_0 : 1;
5478  uint32_t : 3;
5479  uint32_t emac_0_switch : 1;
5480  uint32_t : 3;
5481  uint32_t emac_1 : 1;
5482  uint32_t : 3;
5483  uint32_t emac_1_switch : 1;
5484  uint32_t : 3;
5485  uint32_t emac_2 : 1;
5486  uint32_t : 3;
5487  uint32_t emac_2_switch : 1;
5488  uint32_t : 11;
5489 };
5490 
5493 #endif /* __ASSEMBLY__ */
5494 
5496 #define ALT_SYSMGR_FPGAINTF_EN_3_RESET 0x00000000
5497 
5498 #define ALT_SYSMGR_FPGAINTF_EN_3_OFST 0x70
5499 
5533 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_LSB 0
5534 
5535 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_MSB 0
5536 
5537 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_WIDTH 1
5538 
5539 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET_MSK 0x00000001
5540 
5541 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_CLR_MSK 0xfffffffe
5542 
5543 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_RESET 0x0
5544 
5545 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5546 
5547 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5548 
5567 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_LSB 1
5568 
5569 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_MSB 1
5570 
5571 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_WIDTH 1
5572 
5573 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET_MSK 0x00000002
5574 
5575 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_CLR_MSK 0xfffffffd
5576 
5577 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_RESET 0x0
5578 
5579 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5580 
5581 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5582 
5583 #ifndef __ASSEMBLY__
5584 
5595 {
5596  uint32_t remap0 : 1;
5597  uint32_t remap1 : 1;
5598  uint32_t : 30;
5599 };
5600 
5603 #endif /* __ASSEMBLY__ */
5604 
5606 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_RESET 0x00000000
5607 
5608 #define ALT_SYSMGR_NOC_ADDR_REMAP_VALUE_OFST 0x80
5609 
5636 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_LSB 0
5637 
5638 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_MSB 0
5639 
5640 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_WIDTH 1
5641 
5642 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET_MSK 0x00000001
5643 
5644 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_CLR_MSK 0xfffffffe
5645 
5646 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_RESET 0x0
5647 
5648 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5649 
5650 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5651 
5659 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_LSB 1
5660 
5661 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_MSB 1
5662 
5663 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_WIDTH 1
5664 
5665 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET_MSK 0x00000002
5666 
5667 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_CLR_MSK 0xfffffffd
5668 
5669 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_RESET 0x0
5670 
5671 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5672 
5673 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5674 
5675 #ifndef __ASSEMBLY__
5676 
5687 {
5688  uint32_t remap0 : 1;
5689  uint32_t remap1 : 1;
5690  uint32_t : 30;
5691 };
5692 
5695 #endif /* __ASSEMBLY__ */
5696 
5698 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_RESET 0x00000000
5699 
5700 #define ALT_SYSMGR_NOC_ADDR_REMAP_SET_OFST 0x84
5701 
5728 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_LSB 0
5729 
5730 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_MSB 0
5731 
5732 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_WIDTH 1
5733 
5734 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET_MSK 0x00000001
5735 
5736 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_CLR_MSK 0xfffffffe
5737 
5738 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_RESET 0x0
5739 
5740 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_GET(value) (((value) & 0x00000001) >> 0)
5741 
5742 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP0_SET(value) (((value) << 0) & 0x00000001)
5743 
5751 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_LSB 1
5752 
5753 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_MSB 1
5754 
5755 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_WIDTH 1
5756 
5757 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET_MSK 0x00000002
5758 
5759 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_CLR_MSK 0xfffffffd
5760 
5761 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_RESET 0x0
5762 
5763 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_GET(value) (((value) & 0x00000002) >> 1)
5764 
5765 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_REMAP1_SET(value) (((value) << 1) & 0x00000002)
5766 
5767 #ifndef __ASSEMBLY__
5768 
5779 {
5780  uint32_t remap0 : 1;
5781  uint32_t remap1 : 1;
5782  uint32_t : 30;
5783 };
5784 
5787 #endif /* __ASSEMBLY__ */
5788 
5790 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_RESET 0x00000000
5791 
5792 #define ALT_SYSMGR_NOC_ADDR_REMAP_CLR_OFST 0x88
5793 
5834 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_LSB 0
5835 
5836 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_MSB 0
5837 
5838 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_WIDTH 1
5839 
5840 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET_MSK 0x00000001
5841 
5842 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_CLR_MSK 0xfffffffe
5843 
5844 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_RESET 0x0
5845 
5846 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_GET(value) (((value) & 0x00000001) >> 0)
5847 
5848 #define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET(value) (((value) << 0) & 0x00000001)
5849 
5857 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_LSB 1
5858 
5859 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_MSB 1
5860 
5861 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_WIDTH 1
5862 
5863 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET_MSK 0x00000002
5864 
5865 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_CLR_MSK 0xfffffffd
5866 
5867 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_RESET 0x0
5868 
5869 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
5870 
5871 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET(value) (((value) << 1) & 0x00000002)
5872 
5880 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_LSB 2
5881 
5882 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_MSB 2
5883 
5884 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_WIDTH 1
5885 
5886 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET_MSK 0x00000004
5887 
5888 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_CLR_MSK 0xfffffffb
5889 
5890 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_RESET 0x0
5891 
5892 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_GET(value) (((value) & 0x00000004) >> 2)
5893 
5894 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET(value) (((value) << 2) & 0x00000004)
5895 
5903 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_LSB 3
5904 
5905 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_MSB 3
5906 
5907 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_WIDTH 1
5908 
5909 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET_MSK 0x00000008
5910 
5911 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_CLR_MSK 0xfffffff7
5912 
5913 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_RESET 0x0
5914 
5915 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_GET(value) (((value) & 0x00000008) >> 3)
5916 
5917 #define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET(value) (((value) << 3) & 0x00000008)
5918 
5926 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_LSB 4
5927 
5928 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_MSB 4
5929 
5930 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_WIDTH 1
5931 
5932 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET_MSK 0x00000010
5933 
5934 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_CLR_MSK 0xffffffef
5935 
5936 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_RESET 0x0
5937 
5938 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
5939 
5940 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
5941 
5949 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_LSB 5
5950 
5951 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_MSB 5
5952 
5953 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_WIDTH 1
5954 
5955 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET_MSK 0x00000020
5956 
5957 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_CLR_MSK 0xffffffdf
5958 
5959 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_RESET 0x0
5960 
5961 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
5962 
5963 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
5964 
5972 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_LSB 6
5973 
5974 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_MSB 6
5975 
5976 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_WIDTH 1
5977 
5978 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET_MSK 0x00000040
5979 
5980 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_CLR_MSK 0xffffffbf
5981 
5982 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_RESET 0x0
5983 
5984 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
5985 
5986 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
5987 
5995 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_LSB 7
5996 
5997 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_MSB 7
5998 
5999 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_WIDTH 1
6000 
6001 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET_MSK 0x00000080
6002 
6003 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_CLR_MSK 0xffffff7f
6004 
6005 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_RESET 0x0
6006 
6007 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6008 
6009 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6010 
6018 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_LSB 8
6019 
6020 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_MSB 8
6021 
6022 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_WIDTH 1
6023 
6024 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET_MSK 0x00000100
6025 
6026 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_CLR_MSK 0xfffffeff
6027 
6028 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_RESET 0x0
6029 
6030 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6031 
6032 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6033 
6041 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_LSB 9
6042 
6043 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_MSB 9
6044 
6045 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_WIDTH 1
6046 
6047 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET_MSK 0x00000200
6048 
6049 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_CLR_MSK 0xfffffdff
6050 
6051 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_RESET 0x0
6052 
6053 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6054 
6055 #define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6056 
6064 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_LSB 10
6065 
6066 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_MSB 10
6067 
6068 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_WIDTH 1
6069 
6070 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET_MSK 0x00000400
6071 
6072 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_CLR_MSK 0xfffffbff
6073 
6074 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_RESET 0x0
6075 
6076 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_GET(value) (((value) & 0x00000400) >> 10)
6077 
6078 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET(value) (((value) << 10) & 0x00000400)
6079 
6087 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_LSB 11
6088 
6089 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_MSB 11
6090 
6091 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_WIDTH 1
6092 
6093 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET_MSK 0x00000800
6094 
6095 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_CLR_MSK 0xfffff7ff
6096 
6097 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_RESET 0x0
6098 
6099 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6100 
6101 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6102 
6110 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_LSB 12
6111 
6112 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_MSB 12
6113 
6114 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_WIDTH 1
6115 
6116 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET_MSK 0x00001000
6117 
6118 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_CLR_MSK 0xffffefff
6119 
6120 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_RESET 0x0
6121 
6122 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6123 
6124 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6125 
6133 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_LSB 13
6134 
6135 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_MSB 13
6136 
6137 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_WIDTH 1
6138 
6139 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET_MSK 0x00002000
6140 
6141 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_CLR_MSK 0xffffdfff
6142 
6143 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_RESET 0x0
6144 
6145 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6146 
6147 #define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6148 
6156 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_LSB 14
6157 
6158 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_MSB 14
6159 
6160 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_WIDTH 1
6161 
6162 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET_MSK 0x00004000
6163 
6164 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_CLR_MSK 0xffffbfff
6165 
6166 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_RESET 0x0
6167 
6168 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6169 
6170 #define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET(value) (((value) << 14) & 0x00004000)
6171 
6179 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_LSB 15
6180 
6181 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_MSB 15
6182 
6183 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_WIDTH 1
6184 
6185 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET_MSK 0x00008000
6186 
6187 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_CLR_MSK 0xffff7fff
6188 
6189 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_RESET 0x0
6190 
6191 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6192 
6193 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6194 
6202 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_LSB 16
6203 
6204 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_MSB 16
6205 
6206 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_WIDTH 1
6207 
6208 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET_MSK 0x00010000
6209 
6210 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_CLR_MSK 0xfffeffff
6211 
6212 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_RESET 0x0
6213 
6214 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6215 
6216 #define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6217 
6225 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_LSB 17
6226 
6227 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_MSB 17
6228 
6229 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_WIDTH 1
6230 
6231 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET_MSK 0x00020000
6232 
6233 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_CLR_MSK 0xfffdffff
6234 
6235 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_RESET 0x0
6236 
6237 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6238 
6239 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET(value) (((value) << 17) & 0x00020000)
6240 
6248 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_LSB 18
6249 
6250 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_MSB 18
6251 
6252 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_WIDTH 1
6253 
6254 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET_MSK 0x00040000
6255 
6256 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_CLR_MSK 0xfffbffff
6257 
6258 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_RESET 0x0
6259 
6260 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6261 
6262 #define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET(value) (((value) << 18) & 0x00040000)
6263 
6264 #ifndef __ASSEMBLY__
6265 
6276 {
6277  uint32_t l2 : 1;
6278  uint32_t ocram : 1;
6279  uint32_t usb0 : 1;
6280  uint32_t usb1 : 1;
6281  uint32_t emac0_rx : 1;
6282  uint32_t emac0_tx : 1;
6283  uint32_t emac1_rx : 1;
6284  uint32_t emac1_tx : 1;
6285  uint32_t emac2_rx : 1;
6286  uint32_t emac2_tx : 1;
6287  uint32_t dma : 1;
6288  uint32_t nand_buf : 1;
6289  uint32_t nand_wr : 1;
6290  uint32_t nand_rd : 1;
6291  uint32_t qspi : 1;
6292  uint32_t sdmmca : 1;
6293  uint32_t sdmmcb : 1;
6294  uint32_t ddr0 : 1;
6295  uint32_t ddr1 : 1;
6296  uint32_t : 13;
6297 };
6298 
6301 #endif /* __ASSEMBLY__ */
6302 
6304 #define ALT_SYSMGR_ECC_INTMSK_VALUE_RESET 0x00000000
6305 
6306 #define ALT_SYSMGR_ECC_INTMSK_VALUE_OFST 0x90
6307 
6348 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_LSB 0
6349 
6350 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_MSB 0
6351 
6352 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_WIDTH 1
6353 
6354 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET_MSK 0x00000001
6355 
6356 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_CLR_MSK 0xfffffffe
6357 
6358 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_RESET 0x0
6359 
6360 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_GET(value) (((value) & 0x00000001) >> 0)
6361 
6362 #define ALT_SYSMGR_ECC_INTMSK_SET_L2_SET(value) (((value) << 0) & 0x00000001)
6363 
6371 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_LSB 1
6372 
6373 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_MSB 1
6374 
6375 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_WIDTH 1
6376 
6377 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET_MSK 0x00000002
6378 
6379 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_CLR_MSK 0xfffffffd
6380 
6381 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_RESET 0x0
6382 
6383 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6384 
6385 #define ALT_SYSMGR_ECC_INTMSK_SET_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6386 
6394 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_LSB 2
6395 
6396 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_MSB 2
6397 
6398 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_WIDTH 1
6399 
6400 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET_MSK 0x00000004
6401 
6402 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_CLR_MSK 0xfffffffb
6403 
6404 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_RESET 0x0
6405 
6406 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_GET(value) (((value) & 0x00000004) >> 2)
6407 
6408 #define ALT_SYSMGR_ECC_INTMSK_SET_USB0_SET(value) (((value) << 2) & 0x00000004)
6409 
6417 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_LSB 3
6418 
6419 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_MSB 3
6420 
6421 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_WIDTH 1
6422 
6423 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET_MSK 0x00000008
6424 
6425 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_CLR_MSK 0xfffffff7
6426 
6427 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_RESET 0x0
6428 
6429 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_GET(value) (((value) & 0x00000008) >> 3)
6430 
6431 #define ALT_SYSMGR_ECC_INTMSK_SET_USB1_SET(value) (((value) << 3) & 0x00000008)
6432 
6440 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_LSB 4
6441 
6442 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_MSB 4
6443 
6444 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_WIDTH 1
6445 
6446 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET_MSK 0x00000010
6447 
6448 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_CLR_MSK 0xffffffef
6449 
6450 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_RESET 0x0
6451 
6452 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6453 
6454 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6455 
6463 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_LSB 5
6464 
6465 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_MSB 5
6466 
6467 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_WIDTH 1
6468 
6469 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET_MSK 0x00000020
6470 
6471 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_CLR_MSK 0xffffffdf
6472 
6473 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_RESET 0x0
6474 
6475 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6476 
6477 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6478 
6486 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_LSB 6
6487 
6488 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_MSB 6
6489 
6490 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_WIDTH 1
6491 
6492 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET_MSK 0x00000040
6493 
6494 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_CLR_MSK 0xffffffbf
6495 
6496 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_RESET 0x0
6497 
6498 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
6499 
6500 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
6501 
6509 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_LSB 7
6510 
6511 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_MSB 7
6512 
6513 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_WIDTH 1
6514 
6515 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET_MSK 0x00000080
6516 
6517 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_CLR_MSK 0xffffff7f
6518 
6519 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_RESET 0x0
6520 
6521 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
6522 
6523 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
6524 
6532 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_LSB 8
6533 
6534 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_MSB 8
6535 
6536 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_WIDTH 1
6537 
6538 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET_MSK 0x00000100
6539 
6540 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_CLR_MSK 0xfffffeff
6541 
6542 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_RESET 0x0
6543 
6544 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
6545 
6546 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
6547 
6555 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_LSB 9
6556 
6557 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_MSB 9
6558 
6559 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_WIDTH 1
6560 
6561 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET_MSK 0x00000200
6562 
6563 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_CLR_MSK 0xfffffdff
6564 
6565 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_RESET 0x0
6566 
6567 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
6568 
6569 #define ALT_SYSMGR_ECC_INTMSK_SET_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
6570 
6578 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_LSB 10
6579 
6580 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_MSB 10
6581 
6582 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_WIDTH 1
6583 
6584 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET_MSK 0x00000400
6585 
6586 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_CLR_MSK 0xfffffbff
6587 
6588 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_RESET 0x0
6589 
6590 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_GET(value) (((value) & 0x00000400) >> 10)
6591 
6592 #define ALT_SYSMGR_ECC_INTMSK_SET_DMA_SET(value) (((value) << 10) & 0x00000400)
6593 
6601 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_LSB 11
6602 
6603 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_MSB 11
6604 
6605 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_WIDTH 1
6606 
6607 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET_MSK 0x00000800
6608 
6609 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_CLR_MSK 0xfffff7ff
6610 
6611 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_RESET 0x0
6612 
6613 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
6614 
6615 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
6616 
6624 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_LSB 12
6625 
6626 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_MSB 12
6627 
6628 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_WIDTH 1
6629 
6630 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET_MSK 0x00001000
6631 
6632 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_CLR_MSK 0xffffefff
6633 
6634 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_RESET 0x0
6635 
6636 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
6637 
6638 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
6639 
6647 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_LSB 13
6648 
6649 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_MSB 13
6650 
6651 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_WIDTH 1
6652 
6653 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET_MSK 0x00002000
6654 
6655 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_CLR_MSK 0xffffdfff
6656 
6657 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_RESET 0x0
6658 
6659 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
6660 
6661 #define ALT_SYSMGR_ECC_INTMSK_SET_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
6662 
6670 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_LSB 14
6671 
6672 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_MSB 14
6673 
6674 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_WIDTH 1
6675 
6676 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET_MSK 0x00004000
6677 
6678 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_CLR_MSK 0xffffbfff
6679 
6680 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_RESET 0x0
6681 
6682 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_GET(value) (((value) & 0x00004000) >> 14)
6683 
6684 #define ALT_SYSMGR_ECC_INTMSK_SET_QSPI_SET(value) (((value) << 14) & 0x00004000)
6685 
6693 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_LSB 15
6694 
6695 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_MSB 15
6696 
6697 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_WIDTH 1
6698 
6699 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET_MSK 0x00008000
6700 
6701 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_CLR_MSK 0xffff7fff
6702 
6703 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_RESET 0x0
6704 
6705 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
6706 
6707 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
6708 
6716 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_LSB 16
6717 
6718 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_MSB 16
6719 
6720 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_WIDTH 1
6721 
6722 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET_MSK 0x00010000
6723 
6724 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_CLR_MSK 0xfffeffff
6725 
6726 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_RESET 0x0
6727 
6728 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
6729 
6730 #define ALT_SYSMGR_ECC_INTMSK_SET_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
6731 
6739 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_LSB 17
6740 
6741 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_MSB 17
6742 
6743 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_WIDTH 1
6744 
6745 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET_MSK 0x00020000
6746 
6747 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_CLR_MSK 0xfffdffff
6748 
6749 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_RESET 0x0
6750 
6751 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_GET(value) (((value) & 0x00020000) >> 17)
6752 
6753 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR0_SET(value) (((value) << 17) & 0x00020000)
6754 
6762 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_LSB 18
6763 
6764 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_MSB 18
6765 
6766 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_WIDTH 1
6767 
6768 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET_MSK 0x00040000
6769 
6770 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_CLR_MSK 0xfffbffff
6771 
6772 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_RESET 0x0
6773 
6774 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_GET(value) (((value) & 0x00040000) >> 18)
6775 
6776 #define ALT_SYSMGR_ECC_INTMSK_SET_DDR1_SET(value) (((value) << 18) & 0x00040000)
6777 
6778 #ifndef __ASSEMBLY__
6779 
6790 {
6791  uint32_t l2 : 1;
6792  uint32_t ocram : 1;
6793  uint32_t usb0 : 1;
6794  uint32_t usb1 : 1;
6795  uint32_t emac0_rx : 1;
6796  uint32_t emac0_tx : 1;
6797  uint32_t emac1_rx : 1;
6798  uint32_t emac1_tx : 1;
6799  uint32_t emac2_rx : 1;
6800  uint32_t emac2_tx : 1;
6801  uint32_t dma : 1;
6802  uint32_t nand_buf : 1;
6803  uint32_t nand_wr : 1;
6804  uint32_t nand_rd : 1;
6805  uint32_t qspi : 1;
6806  uint32_t sdmmca : 1;
6807  uint32_t sdmmcb : 1;
6808  uint32_t ddr0 : 1;
6809  uint32_t ddr1 : 1;
6810  uint32_t : 13;
6811 };
6812 
6815 #endif /* __ASSEMBLY__ */
6816 
6818 #define ALT_SYSMGR_ECC_INTMSK_SET_RESET 0x00000000
6819 
6820 #define ALT_SYSMGR_ECC_INTMSK_SET_OFST 0x94
6821 
6862 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_LSB 0
6863 
6864 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_MSB 0
6865 
6866 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_WIDTH 1
6867 
6868 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET_MSK 0x00000001
6869 
6870 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_CLR_MSK 0xfffffffe
6871 
6872 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_RESET 0x0
6873 
6874 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_GET(value) (((value) & 0x00000001) >> 0)
6875 
6876 #define ALT_SYSMGR_ECC_INTMSK_CLR_L2_SET(value) (((value) << 0) & 0x00000001)
6877 
6885 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_LSB 1
6886 
6887 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_MSB 1
6888 
6889 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_WIDTH 1
6890 
6891 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET_MSK 0x00000002
6892 
6893 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_CLR_MSK 0xfffffffd
6894 
6895 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_RESET 0x0
6896 
6897 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
6898 
6899 #define ALT_SYSMGR_ECC_INTMSK_CLR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
6900 
6908 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_LSB 2
6909 
6910 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_MSB 2
6911 
6912 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_WIDTH 1
6913 
6914 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET_MSK 0x00000004
6915 
6916 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_CLR_MSK 0xfffffffb
6917 
6918 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_RESET 0x0
6919 
6920 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_GET(value) (((value) & 0x00000004) >> 2)
6921 
6922 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB0_SET(value) (((value) << 2) & 0x00000004)
6923 
6931 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_LSB 3
6932 
6933 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_MSB 3
6934 
6935 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_WIDTH 1
6936 
6937 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET_MSK 0x00000008
6938 
6939 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_CLR_MSK 0xfffffff7
6940 
6941 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_RESET 0x0
6942 
6943 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_GET(value) (((value) & 0x00000008) >> 3)
6944 
6945 #define ALT_SYSMGR_ECC_INTMSK_CLR_USB1_SET(value) (((value) << 3) & 0x00000008)
6946 
6954 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_LSB 4
6955 
6956 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_MSB 4
6957 
6958 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_WIDTH 1
6959 
6960 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET_MSK 0x00000010
6961 
6962 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_CLR_MSK 0xffffffef
6963 
6964 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_RESET 0x0
6965 
6966 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
6967 
6968 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
6969 
6977 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_LSB 5
6978 
6979 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_MSB 5
6980 
6981 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_WIDTH 1
6982 
6983 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET_MSK 0x00000020
6984 
6985 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_CLR_MSK 0xffffffdf
6986 
6987 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_RESET 0x0
6988 
6989 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
6990 
6991 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
6992 
7000 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_LSB 6
7001 
7002 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_MSB 6
7003 
7004 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_WIDTH 1
7005 
7006 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET_MSK 0x00000040
7007 
7008 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_CLR_MSK 0xffffffbf
7009 
7010 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_RESET 0x0
7011 
7012 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7013 
7014 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7015 
7023 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_LSB 7
7024 
7025 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_MSB 7
7026 
7027 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_WIDTH 1
7028 
7029 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET_MSK 0x00000080
7030 
7031 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_CLR_MSK 0xffffff7f
7032 
7033 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_RESET 0x0
7034 
7035 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7036 
7037 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7038 
7046 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_LSB 8
7047 
7048 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_MSB 8
7049 
7050 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_WIDTH 1
7051 
7052 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET_MSK 0x00000100
7053 
7054 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_CLR_MSK 0xfffffeff
7055 
7056 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_RESET 0x0
7057 
7058 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7059 
7060 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7061 
7069 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_LSB 9
7070 
7071 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_MSB 9
7072 
7073 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_WIDTH 1
7074 
7075 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET_MSK 0x00000200
7076 
7077 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_CLR_MSK 0xfffffdff
7078 
7079 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_RESET 0x0
7080 
7081 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7082 
7083 #define ALT_SYSMGR_ECC_INTMSK_CLR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7084 
7092 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_LSB 10
7093 
7094 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_MSB 10
7095 
7096 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_WIDTH 1
7097 
7098 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET_MSK 0x00000400
7099 
7100 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_CLR_MSK 0xfffffbff
7101 
7102 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_RESET 0x0
7103 
7104 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7105 
7106 #define ALT_SYSMGR_ECC_INTMSK_CLR_DMA_SET(value) (((value) << 10) & 0x00000400)
7107 
7115 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_LSB 11
7116 
7117 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_MSB 11
7118 
7119 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_WIDTH 1
7120 
7121 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET_MSK 0x00000800
7122 
7123 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_CLR_MSK 0xfffff7ff
7124 
7125 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_RESET 0x0
7126 
7127 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7128 
7129 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7130 
7138 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_LSB 12
7139 
7140 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_MSB 12
7141 
7142 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_WIDTH 1
7143 
7144 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET_MSK 0x00001000
7145 
7146 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_CLR_MSK 0xffffefff
7147 
7148 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_RESET 0x0
7149 
7150 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7151 
7152 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7153 
7161 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_LSB 13
7162 
7163 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_MSB 13
7164 
7165 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_WIDTH 1
7166 
7167 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET_MSK 0x00002000
7168 
7169 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_CLR_MSK 0xffffdfff
7170 
7171 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_RESET 0x0
7172 
7173 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7174 
7175 #define ALT_SYSMGR_ECC_INTMSK_CLR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7176 
7184 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_LSB 14
7185 
7186 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_MSB 14
7187 
7188 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_WIDTH 1
7189 
7190 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET_MSK 0x00004000
7191 
7192 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_CLR_MSK 0xffffbfff
7193 
7194 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_RESET 0x0
7195 
7196 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7197 
7198 #define ALT_SYSMGR_ECC_INTMSK_CLR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7199 
7207 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_LSB 15
7208 
7209 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_MSB 15
7210 
7211 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_WIDTH 1
7212 
7213 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET_MSK 0x00008000
7214 
7215 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_CLR_MSK 0xffff7fff
7216 
7217 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_RESET 0x0
7218 
7219 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7220 
7221 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7222 
7230 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_LSB 16
7231 
7232 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_MSB 16
7233 
7234 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_WIDTH 1
7235 
7236 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET_MSK 0x00010000
7237 
7238 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_CLR_MSK 0xfffeffff
7239 
7240 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_RESET 0x0
7241 
7242 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7243 
7244 #define ALT_SYSMGR_ECC_INTMSK_CLR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7245 
7253 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_LSB 17
7254 
7255 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_MSB 17
7256 
7257 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_WIDTH 1
7258 
7259 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET_MSK 0x00020000
7260 
7261 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_CLR_MSK 0xfffdffff
7262 
7263 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_RESET 0x0
7264 
7265 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7266 
7267 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7268 
7276 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_LSB 18
7277 
7278 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_MSB 18
7279 
7280 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_WIDTH 1
7281 
7282 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET_MSK 0x00040000
7283 
7284 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_CLR_MSK 0xfffbffff
7285 
7286 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_RESET 0x0
7287 
7288 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7289 
7290 #define ALT_SYSMGR_ECC_INTMSK_CLR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7291 
7292 #ifndef __ASSEMBLY__
7293 
7304 {
7305  uint32_t l2 : 1;
7306  uint32_t ocram : 1;
7307  uint32_t usb0 : 1;
7308  uint32_t usb1 : 1;
7309  uint32_t emac0_rx : 1;
7310  uint32_t emac0_tx : 1;
7311  uint32_t emac1_rx : 1;
7312  uint32_t emac1_tx : 1;
7313  uint32_t emac2_rx : 1;
7314  uint32_t emac2_tx : 1;
7315  uint32_t dma : 1;
7316  uint32_t nand_buf : 1;
7317  uint32_t nand_wr : 1;
7318  uint32_t nand_rd : 1;
7319  uint32_t qspi : 1;
7320  uint32_t sdmmca : 1;
7321  uint32_t sdmmcb : 1;
7322  uint32_t ddr0 : 1;
7323  uint32_t ddr1 : 1;
7324  uint32_t : 13;
7325 };
7326 
7329 #endif /* __ASSEMBLY__ */
7330 
7332 #define ALT_SYSMGR_ECC_INTMSK_CLR_RESET 0x00000000
7333 
7334 #define ALT_SYSMGR_ECC_INTMSK_CLR_OFST 0x98
7335 
7376 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_LSB 0
7377 
7378 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_MSB 0
7379 
7380 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_WIDTH 1
7381 
7382 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET_MSK 0x00000001
7383 
7384 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_CLR_MSK 0xfffffffe
7385 
7386 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_RESET 0x0
7387 
7388 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7389 
7390 #define ALT_SYSMGR_ECC_INTSTAT_SERR_L2_SET(value) (((value) << 0) & 0x00000001)
7391 
7399 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_LSB 1
7400 
7401 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_MSB 1
7402 
7403 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_WIDTH 1
7404 
7405 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET_MSK 0x00000002
7406 
7407 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_CLR_MSK 0xfffffffd
7408 
7409 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_RESET 0x0
7410 
7411 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7412 
7413 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7414 
7422 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_LSB 2
7423 
7424 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_MSB 2
7425 
7426 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_WIDTH 1
7427 
7428 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET_MSK 0x00000004
7429 
7430 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_CLR_MSK 0xfffffffb
7431 
7432 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_RESET 0x0
7433 
7434 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7435 
7436 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7437 
7445 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_LSB 3
7446 
7447 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_MSB 3
7448 
7449 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_WIDTH 1
7450 
7451 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET_MSK 0x00000008
7452 
7453 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_CLR_MSK 0xfffffff7
7454 
7455 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_RESET 0x0
7456 
7457 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7458 
7459 #define ALT_SYSMGR_ECC_INTSTAT_SERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7460 
7468 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_LSB 4
7469 
7470 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_MSB 4
7471 
7472 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_WIDTH 1
7473 
7474 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET_MSK 0x00000010
7475 
7476 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_CLR_MSK 0xffffffef
7477 
7478 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_RESET 0x0
7479 
7480 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7481 
7482 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7483 
7491 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_LSB 5
7492 
7493 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_MSB 5
7494 
7495 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_WIDTH 1
7496 
7497 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET_MSK 0x00000020
7498 
7499 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_CLR_MSK 0xffffffdf
7500 
7501 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_RESET 0x0
7502 
7503 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
7504 
7505 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
7506 
7514 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_LSB 6
7515 
7516 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_MSB 6
7517 
7518 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_WIDTH 1
7519 
7520 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET_MSK 0x00000040
7521 
7522 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_CLR_MSK 0xffffffbf
7523 
7524 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_RESET 0x0
7525 
7526 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
7527 
7528 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
7529 
7537 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_LSB 7
7538 
7539 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_MSB 7
7540 
7541 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_WIDTH 1
7542 
7543 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET_MSK 0x00000080
7544 
7545 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_CLR_MSK 0xffffff7f
7546 
7547 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_RESET 0x0
7548 
7549 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
7550 
7551 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
7552 
7560 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_LSB 8
7561 
7562 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_MSB 8
7563 
7564 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_WIDTH 1
7565 
7566 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET_MSK 0x00000100
7567 
7568 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_CLR_MSK 0xfffffeff
7569 
7570 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_RESET 0x0
7571 
7572 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
7573 
7574 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
7575 
7583 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_LSB 9
7584 
7585 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_MSB 9
7586 
7587 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_WIDTH 1
7588 
7589 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET_MSK 0x00000200
7590 
7591 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_CLR_MSK 0xfffffdff
7592 
7593 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_RESET 0x0
7594 
7595 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
7596 
7597 #define ALT_SYSMGR_ECC_INTSTAT_SERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
7598 
7606 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_LSB 10
7607 
7608 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_MSB 10
7609 
7610 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_WIDTH 1
7611 
7612 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET_MSK 0x00000400
7613 
7614 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_CLR_MSK 0xfffffbff
7615 
7616 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_RESET 0x0
7617 
7618 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
7619 
7620 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DMA_SET(value) (((value) << 10) & 0x00000400)
7621 
7629 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_LSB 11
7630 
7631 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_MSB 11
7632 
7633 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_WIDTH 1
7634 
7635 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET_MSK 0x00000800
7636 
7637 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_CLR_MSK 0xfffff7ff
7638 
7639 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_RESET 0x0
7640 
7641 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
7642 
7643 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
7644 
7652 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_LSB 12
7653 
7654 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_MSB 12
7655 
7656 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_WIDTH 1
7657 
7658 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET_MSK 0x00001000
7659 
7660 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_CLR_MSK 0xffffefff
7661 
7662 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_RESET 0x0
7663 
7664 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
7665 
7666 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
7667 
7675 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_LSB 13
7676 
7677 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_MSB 13
7678 
7679 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_WIDTH 1
7680 
7681 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET_MSK 0x00002000
7682 
7683 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_CLR_MSK 0xffffdfff
7684 
7685 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_RESET 0x0
7686 
7687 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
7688 
7689 #define ALT_SYSMGR_ECC_INTSTAT_SERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
7690 
7698 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_LSB 14
7699 
7700 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_MSB 14
7701 
7702 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_WIDTH 1
7703 
7704 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET_MSK 0x00004000
7705 
7706 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_CLR_MSK 0xffffbfff
7707 
7708 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_RESET 0x0
7709 
7710 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
7711 
7712 #define ALT_SYSMGR_ECC_INTSTAT_SERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
7713 
7721 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_LSB 15
7722 
7723 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_MSB 15
7724 
7725 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_WIDTH 1
7726 
7727 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET_MSK 0x00008000
7728 
7729 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_CLR_MSK 0xffff7fff
7730 
7731 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_RESET 0x0
7732 
7733 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
7734 
7735 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
7736 
7744 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_LSB 16
7745 
7746 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_MSB 16
7747 
7748 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_WIDTH 1
7749 
7750 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET_MSK 0x00010000
7751 
7752 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_CLR_MSK 0xfffeffff
7753 
7754 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_RESET 0x0
7755 
7756 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
7757 
7758 #define ALT_SYSMGR_ECC_INTSTAT_SERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
7759 
7767 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_LSB 17
7768 
7769 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_MSB 17
7770 
7771 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_WIDTH 1
7772 
7773 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET_MSK 0x00020000
7774 
7775 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_CLR_MSK 0xfffdffff
7776 
7777 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_RESET 0x0
7778 
7779 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
7780 
7781 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
7782 
7790 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_LSB 18
7791 
7792 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_MSB 18
7793 
7794 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_WIDTH 1
7795 
7796 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET_MSK 0x00040000
7797 
7798 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_CLR_MSK 0xfffbffff
7799 
7800 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_RESET 0x0
7801 
7802 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
7803 
7804 #define ALT_SYSMGR_ECC_INTSTAT_SERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
7805 
7806 #ifndef __ASSEMBLY__
7807 
7818 {
7819  uint32_t l2 : 1;
7820  uint32_t ocram : 1;
7821  uint32_t usb0 : 1;
7822  uint32_t usb1 : 1;
7823  uint32_t emac0_rx : 1;
7824  uint32_t emac0_tx : 1;
7825  uint32_t emac1_rx : 1;
7826  uint32_t emac1_tx : 1;
7827  uint32_t emac2_rx : 1;
7828  uint32_t emac2_tx : 1;
7829  uint32_t dma : 1;
7830  uint32_t nand_buf : 1;
7831  uint32_t nand_wr : 1;
7832  uint32_t nand_rd : 1;
7833  uint32_t qspi : 1;
7834  uint32_t sdmmca : 1;
7835  uint32_t sdmmcb : 1;
7836  uint32_t ddr0 : 1;
7837  uint32_t ddr1 : 1;
7838  uint32_t : 13;
7839 };
7840 
7843 #endif /* __ASSEMBLY__ */
7844 
7846 #define ALT_SYSMGR_ECC_INTSTAT_SERR_RESET 0x00000000
7847 
7848 #define ALT_SYSMGR_ECC_INTSTAT_SERR_OFST 0x9c
7849 
7890 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_LSB 0
7891 
7892 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_MSB 0
7893 
7894 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_WIDTH 1
7895 
7896 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET_MSK 0x00000001
7897 
7898 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_CLR_MSK 0xfffffffe
7899 
7900 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_RESET 0x0
7901 
7902 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_GET(value) (((value) & 0x00000001) >> 0)
7903 
7904 #define ALT_SYSMGR_ECC_INTSTAT_DERR_L2_SET(value) (((value) << 0) & 0x00000001)
7905 
7913 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_LSB 1
7914 
7915 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_MSB 1
7916 
7917 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_WIDTH 1
7918 
7919 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET_MSK 0x00000002
7920 
7921 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_CLR_MSK 0xfffffffd
7922 
7923 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_RESET 0x0
7924 
7925 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_GET(value) (((value) & 0x00000002) >> 1)
7926 
7927 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OCRAM_SET(value) (((value) << 1) & 0x00000002)
7928 
7936 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_LSB 2
7937 
7938 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_MSB 2
7939 
7940 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_WIDTH 1
7941 
7942 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET_MSK 0x00000004
7943 
7944 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_CLR_MSK 0xfffffffb
7945 
7946 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_RESET 0x0
7947 
7948 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_GET(value) (((value) & 0x00000004) >> 2)
7949 
7950 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB0_SET(value) (((value) << 2) & 0x00000004)
7951 
7959 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_LSB 3
7960 
7961 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_MSB 3
7962 
7963 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_WIDTH 1
7964 
7965 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET_MSK 0x00000008
7966 
7967 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_CLR_MSK 0xfffffff7
7968 
7969 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_RESET 0x0
7970 
7971 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_GET(value) (((value) & 0x00000008) >> 3)
7972 
7973 #define ALT_SYSMGR_ECC_INTSTAT_DERR_USB1_SET(value) (((value) << 3) & 0x00000008)
7974 
7982 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_LSB 4
7983 
7984 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_MSB 4
7985 
7986 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_WIDTH 1
7987 
7988 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET_MSK 0x00000010
7989 
7990 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_CLR_MSK 0xffffffef
7991 
7992 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_RESET 0x0
7993 
7994 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_GET(value) (((value) & 0x00000010) >> 4)
7995 
7996 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_RX_SET(value) (((value) << 4) & 0x00000010)
7997 
8005 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_LSB 5
8006 
8007 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_MSB 5
8008 
8009 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_WIDTH 1
8010 
8011 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET_MSK 0x00000020
8012 
8013 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_CLR_MSK 0xffffffdf
8014 
8015 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_RESET 0x0
8016 
8017 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_GET(value) (((value) & 0x00000020) >> 5)
8018 
8019 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC0_TX_SET(value) (((value) << 5) & 0x00000020)
8020 
8028 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_LSB 6
8029 
8030 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_MSB 6
8031 
8032 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_WIDTH 1
8033 
8034 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET_MSK 0x00000040
8035 
8036 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_CLR_MSK 0xffffffbf
8037 
8038 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_RESET 0x0
8039 
8040 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_GET(value) (((value) & 0x00000040) >> 6)
8041 
8042 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_RX_SET(value) (((value) << 6) & 0x00000040)
8043 
8051 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_LSB 7
8052 
8053 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_MSB 7
8054 
8055 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_WIDTH 1
8056 
8057 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET_MSK 0x00000080
8058 
8059 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_CLR_MSK 0xffffff7f
8060 
8061 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_RESET 0x0
8062 
8063 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_GET(value) (((value) & 0x00000080) >> 7)
8064 
8065 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC1_TX_SET(value) (((value) << 7) & 0x00000080)
8066 
8074 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_LSB 8
8075 
8076 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_MSB 8
8077 
8078 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_WIDTH 1
8079 
8080 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET_MSK 0x00000100
8081 
8082 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_CLR_MSK 0xfffffeff
8083 
8084 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_RESET 0x0
8085 
8086 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_GET(value) (((value) & 0x00000100) >> 8)
8087 
8088 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_RX_SET(value) (((value) << 8) & 0x00000100)
8089 
8097 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_LSB 9
8098 
8099 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_MSB 9
8100 
8101 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_WIDTH 1
8102 
8103 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET_MSK 0x00000200
8104 
8105 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_CLR_MSK 0xfffffdff
8106 
8107 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_RESET 0x0
8108 
8109 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_GET(value) (((value) & 0x00000200) >> 9)
8110 
8111 #define ALT_SYSMGR_ECC_INTSTAT_DERR_EMAC2_TX_SET(value) (((value) << 9) & 0x00000200)
8112 
8120 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_LSB 10
8121 
8122 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_MSB 10
8123 
8124 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_WIDTH 1
8125 
8126 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET_MSK 0x00000400
8127 
8128 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_CLR_MSK 0xfffffbff
8129 
8130 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_RESET 0x0
8131 
8132 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_GET(value) (((value) & 0x00000400) >> 10)
8133 
8134 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DMA_SET(value) (((value) << 10) & 0x00000400)
8135 
8143 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_LSB 11
8144 
8145 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_MSB 11
8146 
8147 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_WIDTH 1
8148 
8149 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET_MSK 0x00000800
8150 
8151 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_CLR_MSK 0xfffff7ff
8152 
8153 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_RESET 0x0
8154 
8155 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_GET(value) (((value) & 0x00000800) >> 11)
8156 
8157 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_BUF_SET(value) (((value) << 11) & 0x00000800)
8158 
8166 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_LSB 12
8167 
8168 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_MSB 12
8169 
8170 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_WIDTH 1
8171 
8172 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET_MSK 0x00001000
8173 
8174 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_CLR_MSK 0xffffefff
8175 
8176 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_RESET 0x0
8177 
8178 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_GET(value) (((value) & 0x00001000) >> 12)
8179 
8180 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_WR_SET(value) (((value) << 12) & 0x00001000)
8181 
8189 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_LSB 13
8190 
8191 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_MSB 13
8192 
8193 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_WIDTH 1
8194 
8195 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET_MSK 0x00002000
8196 
8197 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_CLR_MSK 0xffffdfff
8198 
8199 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_RESET 0x0
8200 
8201 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_GET(value) (((value) & 0x00002000) >> 13)
8202 
8203 #define ALT_SYSMGR_ECC_INTSTAT_DERR_NAND_RD_SET(value) (((value) << 13) & 0x00002000)
8204 
8212 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_LSB 14
8213 
8214 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_MSB 14
8215 
8216 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_WIDTH 1
8217 
8218 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET_MSK 0x00004000
8219 
8220 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_CLR_MSK 0xffffbfff
8221 
8222 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_RESET 0x0
8223 
8224 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_GET(value) (((value) & 0x00004000) >> 14)
8225 
8226 #define ALT_SYSMGR_ECC_INTSTAT_DERR_QSPI_SET(value) (((value) << 14) & 0x00004000)
8227 
8235 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_LSB 15
8236 
8237 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_MSB 15
8238 
8239 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_WIDTH 1
8240 
8241 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET_MSK 0x00008000
8242 
8243 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_CLR_MSK 0xffff7fff
8244 
8245 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_RESET 0x0
8246 
8247 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_GET(value) (((value) & 0x00008000) >> 15)
8248 
8249 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCA_SET(value) (((value) << 15) & 0x00008000)
8250 
8258 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_LSB 16
8259 
8260 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_MSB 16
8261 
8262 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_WIDTH 1
8263 
8264 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET_MSK 0x00010000
8265 
8266 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_CLR_MSK 0xfffeffff
8267 
8268 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_RESET 0x0
8269 
8270 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_GET(value) (((value) & 0x00010000) >> 16)
8271 
8272 #define ALT_SYSMGR_ECC_INTSTAT_DERR_SDMMCB_SET(value) (((value) << 16) & 0x00010000)
8273 
8281 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_LSB 17
8282 
8283 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_MSB 17
8284 
8285 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_WIDTH 1
8286 
8287 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET_MSK 0x00020000
8288 
8289 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_CLR_MSK 0xfffdffff
8290 
8291 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_RESET 0x0
8292 
8293 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_GET(value) (((value) & 0x00020000) >> 17)
8294 
8295 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR0_SET(value) (((value) << 17) & 0x00020000)
8296 
8304 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_LSB 18
8305 
8306 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_MSB 18
8307 
8308 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_WIDTH 1
8309 
8310 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET_MSK 0x00040000
8311 
8312 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_CLR_MSK 0xfffbffff
8313 
8314 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_RESET 0x0
8315 
8316 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_GET(value) (((value) & 0x00040000) >> 18)
8317 
8318 #define ALT_SYSMGR_ECC_INTSTAT_DERR_DDR1_SET(value) (((value) << 18) & 0x00040000)
8319 
8320 #ifndef __ASSEMBLY__
8321 
8332 {
8333  uint32_t l2 : 1;
8334  uint32_t ocram : 1;
8335  uint32_t usb0 : 1;
8336  uint32_t usb1 : 1;
8337  uint32_t emac0_rx : 1;
8338  uint32_t emac0_tx : 1;
8339  uint32_t emac1_rx : 1;
8340  uint32_t emac1_tx : 1;
8341  uint32_t emac2_rx : 1;
8342  uint32_t emac2_tx : 1;
8343  uint32_t dma : 1;
8344  uint32_t nand_buf : 1;
8345  uint32_t nand_wr : 1;
8346  uint32_t nand_rd : 1;
8347  uint32_t qspi : 1;
8348  uint32_t sdmmca : 1;
8349  uint32_t sdmmcb : 1;
8350  uint32_t ddr0 : 1;
8351  uint32_t ddr1 : 1;
8352  uint32_t : 13;
8353 };
8354 
8357 #endif /* __ASSEMBLY__ */
8358 
8360 #define ALT_SYSMGR_ECC_INTSTAT_DERR_RESET 0x00000000
8361 
8362 #define ALT_SYSMGR_ECC_INTSTAT_DERR_OFST 0xa0
8363 
8395 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_LSB 0
8396 
8397 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_MSB 11
8398 
8399 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_WIDTH 12
8400 
8401 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET_MSK 0x00000fff
8402 
8403 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_CLR_MSK 0xfffff000
8404 
8405 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_RESET 0x0
8406 
8407 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_GET(value) (((value) & 0x00000fff) >> 0)
8408 
8409 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET(value) (((value) << 0) & 0x00000fff)
8410 
8420 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_LSB 15
8421 
8422 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_MSB 15
8423 
8424 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_WIDTH 1
8425 
8426 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET_MSK 0x00008000
8427 
8428 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_CLR_MSK 0xffff7fff
8429 
8430 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_RESET 0x0
8431 
8432 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_GET(value) (((value) & 0x00008000) >> 15)
8433 
8434 #define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET(value) (((value) << 15) & 0x00008000)
8435 
8447 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_LSB 16
8448 
8449 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_MSB 27
8450 
8451 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_WIDTH 12
8452 
8453 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET_MSK 0x0fff0000
8454 
8455 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_CLR_MSK 0xf000ffff
8456 
8457 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_RESET 0x0
8458 
8459 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_GET(value) (((value) & 0x0fff0000) >> 16)
8460 
8461 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET(value) (((value) << 16) & 0x0fff0000)
8462 
8472 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_LSB 31
8473 
8474 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_MSB 31
8475 
8476 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_WIDTH 1
8477 
8478 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET_MSK 0x80000000
8479 
8480 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_CLR_MSK 0x7fffffff
8481 
8482 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_RESET 0x0
8483 
8484 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_GET(value) (((value) & 0x80000000) >> 31)
8485 
8486 #define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET(value) (((value) << 31) & 0x80000000)
8487 
8488 #ifndef __ASSEMBLY__
8489 
8500 {
8501  uint32_t serr_info : 12;
8502  uint32_t : 3;
8503  uint32_t serr_pending : 1;
8504  uint32_t merr_info : 12;
8505  uint32_t : 3;
8506  uint32_t merr_pending : 1;
8507 };
8508 
8511 #endif /* __ASSEMBLY__ */
8512 
8514 #define ALT_SYSMGR_MPU_STAT_L2_ECC_RESET 0x00000000
8515 
8516 #define ALT_SYSMGR_MPU_STAT_L2_ECC_OFST 0xa4
8517 
8546 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_LSB 15
8547 
8548 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_MSB 15
8549 
8550 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_WIDTH 1
8551 
8552 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET_MSK 0x00008000
8553 
8554 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_CLR_MSK 0xffff7fff
8555 
8556 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_RESET 0x0
8557 
8558 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_GET(value) (((value) & 0x00008000) >> 15)
8559 
8560 #define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET(value) (((value) << 15) & 0x00008000)
8561 
8572 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_LSB 31
8573 
8574 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_MSB 31
8575 
8576 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_WIDTH 1
8577 
8578 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET_MSK 0x80000000
8579 
8580 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_CLR_MSK 0x7fffffff
8581 
8582 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_RESET 0x0
8583 
8584 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_GET(value) (((value) & 0x80000000) >> 31)
8585 
8586 #define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET(value) (((value) << 31) & 0x80000000)
8587 
8588 #ifndef __ASSEMBLY__
8589 
8600 {
8601  uint32_t : 15;
8602  uint32_t serr : 1;
8603  uint32_t : 15;
8604  uint32_t merr : 1;
8605 };
8606 
8609 #endif /* __ASSEMBLY__ */
8610 
8612 #define ALT_SYSMGR_MPU_CLR_L2_ECC_RESET 0x00000000
8613 
8614 #define ALT_SYSMGR_MPU_CLR_L2_ECC_OFST 0xa8
8615 
8678 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_LSB 0
8679 
8680 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_MSB 7
8681 
8682 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_WIDTH 8
8683 
8684 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET_MSK 0x000000ff
8685 
8686 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8687 
8688 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_RESET 0x0
8689 
8690 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8691 
8692 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8693 
8703 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_LSB 8
8704 
8705 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_MSB 15
8706 
8707 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_WIDTH 8
8708 
8709 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8710 
8711 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8712 
8713 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_RESET 0x0
8714 
8715 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8716 
8717 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8718 
8728 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_LSB 16
8729 
8730 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_MSB 17
8731 
8732 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_WIDTH 2
8733 
8734 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET_MSK 0x00030000
8735 
8736 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8737 
8738 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_RESET 0x0
8739 
8740 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8741 
8742 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8743 
8744 #ifndef __ASSEMBLY__
8745 
8756 {
8757  uint32_t cpu0 : 8;
8758  uint32_t cpu1 : 8;
8759  uint32_t scu : 2;
8760  uint32_t : 14;
8761 };
8762 
8765 #endif /* __ASSEMBLY__ */
8766 
8768 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_RESET 0x00000000
8769 
8770 #define ALT_SYSMGR_MPU_STAT_L1_PARITY_OFST 0xac
8771 
8837 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_LSB 0
8838 
8839 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_MSB 7
8840 
8841 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_WIDTH 8
8842 
8843 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET_MSK 0x000000ff
8844 
8845 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_CLR_MSK 0xffffff00
8846 
8847 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_RESET 0x0
8848 
8849 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
8850 
8851 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
8852 
8862 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_LSB 8
8863 
8864 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_MSB 15
8865 
8866 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_WIDTH 8
8867 
8868 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET_MSK 0x0000ff00
8869 
8870 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
8871 
8872 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_RESET 0x0
8873 
8874 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
8875 
8876 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
8877 
8887 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_LSB 16
8888 
8889 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_MSB 17
8890 
8891 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_WIDTH 2
8892 
8893 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET_MSK 0x00030000
8894 
8895 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_CLR_MSK 0xfffcffff
8896 
8897 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_RESET 0x0
8898 
8899 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
8900 
8901 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
8902 
8903 #ifndef __ASSEMBLY__
8904 
8915 {
8916  uint32_t cpu0 : 8;
8917  uint32_t cpu1 : 8;
8918  uint32_t scu : 2;
8919  uint32_t : 14;
8920 };
8921 
8924 #endif /* __ASSEMBLY__ */
8925 
8927 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_RESET 0x00000000
8928 
8929 #define ALT_SYSMGR_MPU_CLR_L1_PARITY_OFST 0xb0
8930 
8998 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_LSB 0
8999 
9000 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_MSB 7
9001 
9002 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_WIDTH 8
9003 
9004 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET_MSK 0x000000ff
9005 
9006 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_CLR_MSK 0xffffff00
9007 
9008 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_RESET 0x0
9009 
9010 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_GET(value) (((value) & 0x000000ff) >> 0)
9011 
9012 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET(value) (((value) << 0) & 0x000000ff)
9013 
9023 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_LSB 8
9024 
9025 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_MSB 15
9026 
9027 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_WIDTH 8
9028 
9029 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET_MSK 0x0000ff00
9030 
9031 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_CLR_MSK 0xffff00ff
9032 
9033 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_RESET 0x0
9034 
9035 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_GET(value) (((value) & 0x0000ff00) >> 8)
9036 
9037 #define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET(value) (((value) << 8) & 0x0000ff00)
9038 
9048 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_LSB 16
9049 
9050 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_MSB 17
9051 
9052 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_WIDTH 2
9053 
9054 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET_MSK 0x00030000
9055 
9056 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_CLR_MSK 0xfffcffff
9057 
9058 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_RESET 0x0
9059 
9060 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_GET(value) (((value) & 0x00030000) >> 16)
9061 
9062 #define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET(value) (((value) << 16) & 0x00030000)
9063 
9064 #ifndef __ASSEMBLY__
9065 
9076 {
9077  uint32_t cpu0 : 8;
9078  uint32_t cpu1 : 8;
9079  uint32_t scu : 2;
9080  uint32_t : 14;
9081 };
9082 
9085 #endif /* __ASSEMBLY__ */
9086 
9088 #define ALT_SYSMGR_MPU_SET_L1_PARITY_RESET 0x00000000
9089 
9090 #define ALT_SYSMGR_MPU_SET_L1_PARITY_OFST 0xb4
9091 
9112 #define ALT_SYSMGR_NOC_TMO_EN_LSB 0
9113 
9114 #define ALT_SYSMGR_NOC_TMO_EN_MSB 0
9115 
9116 #define ALT_SYSMGR_NOC_TMO_EN_WIDTH 1
9117 
9118 #define ALT_SYSMGR_NOC_TMO_EN_SET_MSK 0x00000001
9119 
9120 #define ALT_SYSMGR_NOC_TMO_EN_CLR_MSK 0xfffffffe
9121 
9122 #define ALT_SYSMGR_NOC_TMO_EN_RESET 0x0
9123 
9124 #define ALT_SYSMGR_NOC_TMO_EN_GET(value) (((value) & 0x00000001) >> 0)
9125 
9126 #define ALT_SYSMGR_NOC_TMO_EN_SET(value) (((value) << 0) & 0x00000001)
9127 
9128 #ifndef __ASSEMBLY__
9129 
9140 {
9141  uint32_t en : 1;
9142  uint32_t : 31;
9143 };
9144 
9147 #endif /* __ASSEMBLY__ */
9148 
9150 #define ALT_SYSMGR_NOC_TMO_RESET 0x00000000
9151 
9152 #define ALT_SYSMGR_NOC_TMO_OFST 0xc0
9153 
9184 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_LSB 0
9185 
9186 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_MSB 0
9187 
9188 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_WIDTH 1
9189 
9190 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET_MSK 0x00000001
9191 
9192 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_CLR_MSK 0xfffffffe
9193 
9194 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_RESET 0x0
9195 
9196 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_GET(value) (((value) & 0x00000001) >> 0)
9197 
9198 #define ALT_SYSMGR_NOC_IDLEREQ_SET_H2F_SET(value) (((value) << 0) & 0x00000001)
9199 
9207 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_LSB 4
9208 
9209 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_MSB 4
9210 
9211 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_WIDTH 1
9212 
9213 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET_MSK 0x00000010
9214 
9215 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_CLR_MSK 0xffffffef
9216 
9217 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_RESET 0x0
9218 
9219 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9220 
9221 #define ALT_SYSMGR_NOC_IDLEREQ_SET_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9222 
9230 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_LSB 8
9231 
9232 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_MSB 8
9233 
9234 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_WIDTH 1
9235 
9236 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET_MSK 0x00000100
9237 
9238 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_CLR_MSK 0xfffffeff
9239 
9240 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_RESET 0x0
9241 
9242 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_GET(value) (((value) & 0x00000100) >> 8)
9243 
9244 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2H_SET(value) (((value) << 8) & 0x00000100)
9245 
9253 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_LSB 16
9254 
9255 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_MSB 16
9256 
9257 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_WIDTH 1
9258 
9259 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET_MSK 0x00010000
9260 
9261 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_CLR_MSK 0xfffeffff
9262 
9263 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_RESET 0x0
9264 
9265 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9266 
9267 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9268 
9276 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_LSB 20
9277 
9278 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_MSB 20
9279 
9280 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_WIDTH 1
9281 
9282 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET_MSK 0x00100000
9283 
9284 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_CLR_MSK 0xffefffff
9285 
9286 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_RESET 0x0
9287 
9288 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9289 
9290 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9291 
9299 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_LSB 24
9300 
9301 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_MSB 24
9302 
9303 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_WIDTH 1
9304 
9305 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET_MSK 0x01000000
9306 
9307 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_CLR_MSK 0xfeffffff
9308 
9309 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_RESET 0x0
9310 
9311 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9312 
9313 #define ALT_SYSMGR_NOC_IDLEREQ_SET_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9314 
9315 #ifndef __ASSEMBLY__
9316 
9327 {
9328  uint32_t soc2fpga : 1;
9329  uint32_t : 3;
9330  uint32_t lwsoc2fpga : 1;
9331  uint32_t : 3;
9332  uint32_t fpga2soc : 1;
9333  uint32_t : 7;
9334  uint32_t fpga2sdram0 : 1;
9335  uint32_t : 3;
9336  uint32_t fpga2sdram1 : 1;
9337  uint32_t : 3;
9338  uint32_t fpga2sdram2 : 1;
9339  uint32_t : 7;
9340 };
9341 
9344 #endif /* __ASSEMBLY__ */
9345 
9347 #define ALT_SYSMGR_NOC_IDLEREQ_SET_RESET 0x00000000
9348 
9349 #define ALT_SYSMGR_NOC_IDLEREQ_SET_OFST 0xc4
9350 
9381 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_LSB 0
9382 
9383 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_MSB 0
9384 
9385 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_WIDTH 1
9386 
9387 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET_MSK 0x00000001
9388 
9389 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_CLR_MSK 0xfffffffe
9390 
9391 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_RESET 0x0
9392 
9393 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_GET(value) (((value) & 0x00000001) >> 0)
9394 
9395 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_H2F_SET(value) (((value) << 0) & 0x00000001)
9396 
9404 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_LSB 4
9405 
9406 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_MSB 4
9407 
9408 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_WIDTH 1
9409 
9410 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET_MSK 0x00000010
9411 
9412 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_CLR_MSK 0xffffffef
9413 
9414 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_RESET 0x0
9415 
9416 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9417 
9418 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9419 
9427 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_LSB 8
9428 
9429 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_MSB 8
9430 
9431 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_WIDTH 1
9432 
9433 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET_MSK 0x00000100
9434 
9435 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_CLR_MSK 0xfffffeff
9436 
9437 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_RESET 0x0
9438 
9439 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_GET(value) (((value) & 0x00000100) >> 8)
9440 
9441 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2H_SET(value) (((value) << 8) & 0x00000100)
9442 
9450 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_LSB 16
9451 
9452 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_MSB 16
9453 
9454 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_WIDTH 1
9455 
9456 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET_MSK 0x00010000
9457 
9458 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_CLR_MSK 0xfffeffff
9459 
9460 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_RESET 0x0
9461 
9462 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9463 
9464 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9465 
9473 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_LSB 20
9474 
9475 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_MSB 20
9476 
9477 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_WIDTH 1
9478 
9479 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET_MSK 0x00100000
9480 
9481 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_CLR_MSK 0xffefffff
9482 
9483 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_RESET 0x0
9484 
9485 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9486 
9487 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9488 
9496 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_LSB 24
9497 
9498 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_MSB 24
9499 
9500 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_WIDTH 1
9501 
9502 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET_MSK 0x01000000
9503 
9504 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_CLR_MSK 0xfeffffff
9505 
9506 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_RESET 0x0
9507 
9508 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9509 
9510 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9511 
9512 #ifndef __ASSEMBLY__
9513 
9524 {
9525  uint32_t soc2fpga : 1;
9526  uint32_t : 3;
9527  uint32_t lwsoc2fpga : 1;
9528  uint32_t : 3;
9529  uint32_t fpga2soc : 1;
9530  uint32_t : 7;
9531  uint32_t fpga2sdram0 : 1;
9532  uint32_t : 3;
9533  uint32_t fpga2sdram1 : 1;
9534  uint32_t : 3;
9535  uint32_t fpga2sdram2 : 1;
9536  uint32_t : 7;
9537 };
9538 
9541 #endif /* __ASSEMBLY__ */
9542 
9544 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_RESET 0x00000000
9545 
9546 #define ALT_SYSMGR_NOC_IDLEREQ_CLR_OFST 0xc8
9547 
9584 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_LSB 0
9585 
9586 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_MSB 0
9587 
9588 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_WIDTH 1
9589 
9590 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET_MSK 0x00000001
9591 
9592 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_CLR_MSK 0xfffffffe
9593 
9594 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_RESET 0x0
9595 
9596 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_GET(value) (((value) & 0x00000001) >> 0)
9597 
9598 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_H2F_SET(value) (((value) << 0) & 0x00000001)
9599 
9607 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_LSB 4
9608 
9609 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_MSB 4
9610 
9611 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_WIDTH 1
9612 
9613 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET_MSK 0x00000010
9614 
9615 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_CLR_MSK 0xffffffef
9616 
9617 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_RESET 0x0
9618 
9619 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9620 
9621 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9622 
9630 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_LSB 8
9631 
9632 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_MSB 8
9633 
9634 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_WIDTH 1
9635 
9636 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET_MSK 0x00000100
9637 
9638 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_CLR_MSK 0xfffffeff
9639 
9640 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_RESET 0x0
9641 
9642 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_GET(value) (((value) & 0x00000100) >> 8)
9643 
9644 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2H_SET(value) (((value) << 8) & 0x00000100)
9645 
9653 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_LSB 16
9654 
9655 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_MSB 16
9656 
9657 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_WIDTH 1
9658 
9659 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET_MSK 0x00010000
9660 
9661 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_CLR_MSK 0xfffeffff
9662 
9663 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_RESET 0x0
9664 
9665 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9666 
9667 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9668 
9676 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_LSB 20
9677 
9678 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_MSB 20
9679 
9680 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_WIDTH 1
9681 
9682 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET_MSK 0x00100000
9683 
9684 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_CLR_MSK 0xffefffff
9685 
9686 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_RESET 0x0
9687 
9688 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9689 
9690 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9691 
9699 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_LSB 24
9700 
9701 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_MSB 24
9702 
9703 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_WIDTH 1
9704 
9705 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET_MSK 0x01000000
9706 
9707 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_CLR_MSK 0xfeffffff
9708 
9709 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_RESET 0x0
9710 
9711 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9712 
9713 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9714 
9715 #ifndef __ASSEMBLY__
9716 
9727 {
9728  uint32_t soc2fpga : 1;
9729  uint32_t : 3;
9730  uint32_t lwsoc2fpga : 1;
9731  uint32_t : 3;
9732  uint32_t fpga2soc : 1;
9733  uint32_t : 7;
9734  uint32_t fpga2sdram0 : 1;
9735  uint32_t : 3;
9736  uint32_t fpga2sdram1 : 1;
9737  uint32_t : 3;
9738  uint32_t fpga2sdram2 : 1;
9739  uint32_t : 7;
9740 };
9741 
9744 #endif /* __ASSEMBLY__ */
9745 
9747 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_RESET 0x00000000
9748 
9749 #define ALT_SYSMGR_NOC_IDLEREQ_VALUE_OFST 0xcc
9750 
9782 #define ALT_SYSMGR_NOC_IDLEACK_H2F_LSB 0
9783 
9784 #define ALT_SYSMGR_NOC_IDLEACK_H2F_MSB 0
9785 
9786 #define ALT_SYSMGR_NOC_IDLEACK_H2F_WIDTH 1
9787 
9788 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET_MSK 0x00000001
9789 
9790 #define ALT_SYSMGR_NOC_IDLEACK_H2F_CLR_MSK 0xfffffffe
9791 
9792 #define ALT_SYSMGR_NOC_IDLEACK_H2F_RESET 0x0
9793 
9794 #define ALT_SYSMGR_NOC_IDLEACK_H2F_GET(value) (((value) & 0x00000001) >> 0)
9795 
9796 #define ALT_SYSMGR_NOC_IDLEACK_H2F_SET(value) (((value) << 0) & 0x00000001)
9797 
9805 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_LSB 4
9806 
9807 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_MSB 4
9808 
9809 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_WIDTH 1
9810 
9811 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET_MSK 0x00000010
9812 
9813 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_CLR_MSK 0xffffffef
9814 
9815 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_RESET 0x0
9816 
9817 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
9818 
9819 #define ALT_SYSMGR_NOC_IDLEACK_LWH2F_SET(value) (((value) << 4) & 0x00000010)
9820 
9828 #define ALT_SYSMGR_NOC_IDLEACK_F2H_LSB 8
9829 
9830 #define ALT_SYSMGR_NOC_IDLEACK_F2H_MSB 8
9831 
9832 #define ALT_SYSMGR_NOC_IDLEACK_F2H_WIDTH 1
9833 
9834 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET_MSK 0x00000100
9835 
9836 #define ALT_SYSMGR_NOC_IDLEACK_F2H_CLR_MSK 0xfffffeff
9837 
9838 #define ALT_SYSMGR_NOC_IDLEACK_F2H_RESET 0x0
9839 
9840 #define ALT_SYSMGR_NOC_IDLEACK_F2H_GET(value) (((value) & 0x00000100) >> 8)
9841 
9842 #define ALT_SYSMGR_NOC_IDLEACK_F2H_SET(value) (((value) << 8) & 0x00000100)
9843 
9851 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_LSB 16
9852 
9853 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_MSB 16
9854 
9855 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_WIDTH 1
9856 
9857 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET_MSK 0x00010000
9858 
9859 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_CLR_MSK 0xfffeffff
9860 
9861 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_RESET 0x0
9862 
9863 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
9864 
9865 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
9866 
9874 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_LSB 20
9875 
9876 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_MSB 20
9877 
9878 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_WIDTH 1
9879 
9880 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET_MSK 0x00100000
9881 
9882 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_CLR_MSK 0xffefffff
9883 
9884 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_RESET 0x0
9885 
9886 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
9887 
9888 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
9889 
9897 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_LSB 24
9898 
9899 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_MSB 24
9900 
9901 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_WIDTH 1
9902 
9903 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET_MSK 0x01000000
9904 
9905 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_CLR_MSK 0xfeffffff
9906 
9907 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_RESET 0x0
9908 
9909 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
9910 
9911 #define ALT_SYSMGR_NOC_IDLEACK_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
9912 
9913 #ifndef __ASSEMBLY__
9914 
9925 {
9926  uint32_t soc2fpga : 1;
9927  uint32_t : 3;
9928  uint32_t lwsoc2fpga : 1;
9929  uint32_t : 3;
9930  uint32_t fpga2soc : 1;
9931  uint32_t : 7;
9932  uint32_t fpga2sdram0 : 1;
9933  uint32_t : 3;
9934  uint32_t fpga2sdram1 : 1;
9935  uint32_t : 3;
9936  uint32_t fpga2sdram2 : 1;
9937  uint32_t : 7;
9938 };
9939 
9942 #endif /* __ASSEMBLY__ */
9943 
9945 #define ALT_SYSMGR_NOC_IDLEACK_RESET 0x00000000
9946 
9947 #define ALT_SYSMGR_NOC_IDLEACK_OFST 0xd0
9948 
9980 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_LSB 0
9981 
9982 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_MSB 0
9983 
9984 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_WIDTH 1
9985 
9986 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET_MSK 0x00000001
9987 
9988 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_CLR_MSK 0xfffffffe
9989 
9990 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_RESET 0x0
9991 
9992 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_GET(value) (((value) & 0x00000001) >> 0)
9993 
9994 #define ALT_SYSMGR_NOC_IDLESTAT_H2F_SET(value) (((value) << 0) & 0x00000001)
9995 
10003 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_LSB 4
10004 
10005 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_MSB 4
10006 
10007 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_WIDTH 1
10008 
10009 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET_MSK 0x00000010
10010 
10011 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_CLR_MSK 0xffffffef
10012 
10013 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_RESET 0x0
10014 
10015 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_GET(value) (((value) & 0x00000010) >> 4)
10016 
10017 #define ALT_SYSMGR_NOC_IDLESTAT_LWH2F_SET(value) (((value) << 4) & 0x00000010)
10018 
10026 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_LSB 8
10027 
10028 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_MSB 8
10029 
10030 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_WIDTH 1
10031 
10032 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET_MSK 0x00000100
10033 
10034 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_CLR_MSK 0xfffffeff
10035 
10036 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_RESET 0x0
10037 
10038 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_GET(value) (((value) & 0x00000100) >> 8)
10039 
10040 #define ALT_SYSMGR_NOC_IDLESTAT_F2H_SET(value) (((value) << 8) & 0x00000100)
10041 
10049 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_LSB 16
10050 
10051 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_MSB 16
10052 
10053 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_WIDTH 1
10054 
10055 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET_MSK 0x00010000
10056 
10057 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_CLR_MSK 0xfffeffff
10058 
10059 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_RESET 0x0
10060 
10061 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_GET(value) (((value) & 0x00010000) >> 16)
10062 
10063 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR0_SET(value) (((value) << 16) & 0x00010000)
10064 
10072 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_LSB 20
10073 
10074 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_MSB 20
10075 
10076 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_WIDTH 1
10077 
10078 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET_MSK 0x00100000
10079 
10080 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_CLR_MSK 0xffefffff
10081 
10082 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_RESET 0x0
10083 
10084 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_GET(value) (((value) & 0x00100000) >> 20)
10085 
10086 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR1_SET(value) (((value) << 20) & 0x00100000)
10087 
10095 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_LSB 24
10096 
10097 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_MSB 24
10098 
10099 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_WIDTH 1
10100 
10101 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET_MSK 0x01000000
10102 
10103 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_CLR_MSK 0xfeffffff
10104 
10105 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_RESET 0x0
10106 
10107 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_GET(value) (((value) & 0x01000000) >> 24)
10108 
10109 #define ALT_SYSMGR_NOC_IDLESTAT_F2SDR2_SET(value) (((value) << 24) & 0x01000000)
10110 
10111 #ifndef __ASSEMBLY__
10112 
10123 {
10124  uint32_t soc2fpga : 1;
10125  uint32_t : 3;
10126  uint32_t lwsoc2fpga : 1;
10127  uint32_t : 3;
10128  uint32_t fpga2soc : 1;
10129  uint32_t : 7;
10130  uint32_t fpga2sdram0 : 1;
10131  uint32_t : 3;
10132  uint32_t fpga2sdram1 : 1;
10133  uint32_t : 3;
10134  uint32_t fpga2sdram2 : 1;
10135  uint32_t : 7;
10136 };
10137 
10140 #endif /* __ASSEMBLY__ */
10141 
10143 #define ALT_SYSMGR_NOC_IDLESTAT_RESET 0x00000000
10144 
10145 #define ALT_SYSMGR_NOC_IDLESTAT_OFST 0xd4
10146 
10169 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_LSB 0
10170 
10171 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_MSB 0
10172 
10173 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_WIDTH 1
10174 
10175 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET_MSK 0x00000001
10176 
10177 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_CLR_MSK 0xfffffffe
10178 
10179 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_RESET 0x0
10180 
10181 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_GET(value) (((value) & 0x00000001) >> 0)
10182 
10183 #define ALT_SYSMGR_F2H_CTL_ALLOW_SECURE_SET(value) (((value) << 0) & 0x00000001)
10184 
10185 #ifndef __ASSEMBLY__
10186 
10197 {
10198  uint32_t allow_secure : 1;
10199  uint32_t : 31;
10200 };
10201 
10204 #endif /* __ASSEMBLY__ */
10205 
10207 #define ALT_SYSMGR_F2H_CTL_RESET 0x00000000
10208 
10209 #define ALT_SYSMGR_F2H_CTL_OFST 0xd8
10210 
10241 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_LSB 0
10242 
10243 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_MSB 1
10244 
10245 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_WIDTH 2
10246 
10247 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET_MSK 0x00000003
10248 
10249 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_CLR_MSK 0xfffffffc
10250 
10251 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_RESET 0x1
10252 
10253 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_GET(value) (((value) & 0x00000003) >> 0)
10254 
10255 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_RTSEL_SET(value) (((value) << 0) & 0x00000003)
10256 
10264 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_LSB 4
10265 
10266 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_MSB 5
10267 
10268 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_WIDTH 2
10269 
10270 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET_MSK 0x00000030
10271 
10272 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_CLR_MSK 0xffffffcf
10273 
10274 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_RESET 0x1
10275 
10276 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_GET(value) (((value) & 0x00000030) >> 4)
10277 
10278 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_PTSEL_SET(value) (((value) << 4) & 0x00000030)
10279 
10287 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_LSB 8
10288 
10289 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_MSB 9
10290 
10291 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_WIDTH 2
10292 
10293 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET_MSK 0x00000300
10294 
10295 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_CLR_MSK 0xfffffcff
10296 
10297 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_RESET 0x1
10298 
10299 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_GET(value) (((value) & 0x00000300) >> 8)
10300 
10301 #define ALT_SYSMGR_TSMC_TSEL_0_ROM_TRB_SET(value) (((value) << 8) & 0x00000300)
10302 
10310 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_LSB 16
10311 
10312 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_MSB 17
10313 
10314 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_WIDTH 2
10315 
10316 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET_MSK 0x00030000
10317 
10318 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_CLR_MSK 0xfffcffff
10319 
10320 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_RESET 0x0
10321 
10322 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_GET(value) (((value) & 0x00030000) >> 16)
10323 
10324 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCW_SET(value) (((value) << 16) & 0x00030000)
10325 
10333 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_LSB 20
10334 
10335 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_MSB 21
10336 
10337 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_WIDTH 2
10338 
10339 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET_MSK 0x00300000
10340 
10341 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_CLR_MSK 0xffcfffff
10342 
10343 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_RESET 0x0
10344 
10345 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_GET(value) (((value) & 0x00300000) >> 20)
10346 
10347 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL1_MCR_SET(value) (((value) << 20) & 0x00300000)
10348 
10356 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_LSB 24
10357 
10358 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_MSB 26
10359 
10360 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_WIDTH 3
10361 
10362 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET_MSK 0x07000000
10363 
10364 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_CLR_MSK 0xf8ffffff
10365 
10366 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_RESET 0x0
10367 
10368 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10369 
10370 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10371 
10379 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_LSB 28
10380 
10381 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_MSB 29
10382 
10383 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_WIDTH 2
10384 
10385 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET_MSK 0x30000000
10386 
10387 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_CLR_MSK 0xcfffffff
10388 
10389 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_RESET 0x1
10390 
10391 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10392 
10393 #define ALT_SYSMGR_TSMC_TSEL_0_MPUL2_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10394 
10395 #ifndef __ASSEMBLY__
10396 
10407 {
10408  uint32_t rom_rtsel : 2;
10409  uint32_t : 2;
10410  uint32_t rom_ptsel : 2;
10411  uint32_t : 2;
10412  uint32_t rom_trb : 2;
10413  uint32_t : 6;
10414  uint32_t mpul1_mcw : 2;
10415  uint32_t : 2;
10416  uint32_t mpul1_mcr : 2;
10417  uint32_t : 2;
10418  uint32_t mpul2_wtsel : 3;
10419  uint32_t : 1;
10420  uint32_t mpul2_rtsel : 2;
10421  uint32_t : 2;
10422 };
10423 
10426 #endif /* __ASSEMBLY__ */
10427 
10429 #define ALT_SYSMGR_TSMC_TSEL_0_RESET 0x10000111
10430 
10431 #define ALT_SYSMGR_TSMC_TSEL_0_OFST 0x100
10432 
10465 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_LSB 0
10466 
10467 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_MSB 2
10468 
10469 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_WIDTH 3
10470 
10471 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET_MSK 0x00000007
10472 
10473 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_CLR_MSK 0xfffffff8
10474 
10475 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_RESET 0x0
10476 
10477 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_GET(value) (((value) & 0x00000007) >> 0)
10478 
10479 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_WTSEL_SET(value) (((value) << 0) & 0x00000007)
10480 
10488 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_LSB 4
10489 
10490 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_MSB 5
10491 
10492 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_WIDTH 2
10493 
10494 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET_MSK 0x00000030
10495 
10496 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_CLR_MSK 0xffffffcf
10497 
10498 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_RESET 0x1
10499 
10500 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_GET(value) (((value) & 0x00000030) >> 4)
10501 
10502 #define ALT_SYSMGR_TSMC_TSEL_1_OCRAM_RTSEL_SET(value) (((value) << 4) & 0x00000030)
10503 
10511 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_LSB 8
10512 
10513 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_MSB 10
10514 
10515 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_WIDTH 3
10516 
10517 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET_MSK 0x00000700
10518 
10519 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_CLR_MSK 0xfffff8ff
10520 
10521 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_RESET 0x0
10522 
10523 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_GET(value) (((value) & 0x00000700) >> 8)
10524 
10525 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_WTSEL_SET(value) (((value) << 8) & 0x00000700)
10526 
10534 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_LSB 12
10535 
10536 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_MSB 13
10537 
10538 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_WIDTH 2
10539 
10540 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET_MSK 0x00003000
10541 
10542 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_CLR_MSK 0xffffcfff
10543 
10544 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_RESET 0x1
10545 
10546 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_GET(value) (((value) & 0x00003000) >> 12)
10547 
10548 #define ALT_SYSMGR_TSMC_TSEL_1_OTG_RTSEL_SET(value) (((value) << 12) & 0x00003000)
10549 
10557 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_LSB 16
10558 
10559 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_MSB 18
10560 
10561 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_WIDTH 3
10562 
10563 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET_MSK 0x00070000
10564 
10565 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_CLR_MSK 0xfff8ffff
10566 
10567 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_RESET 0x0
10568 
10569 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_GET(value) (((value) & 0x00070000) >> 16)
10570 
10571 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_WTSEL_SET(value) (((value) << 16) & 0x00070000)
10572 
10580 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_LSB 20
10581 
10582 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_MSB 21
10583 
10584 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_WIDTH 2
10585 
10586 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET_MSK 0x00300000
10587 
10588 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_CLR_MSK 0xffcfffff
10589 
10590 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_RESET 0x1
10591 
10592 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_GET(value) (((value) & 0x00300000) >> 20)
10593 
10594 #define ALT_SYSMGR_TSMC_TSEL_1_QSPI_RTSEL_SET(value) (((value) << 20) & 0x00300000)
10595 
10603 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_LSB 24
10604 
10605 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_MSB 26
10606 
10607 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_WIDTH 3
10608 
10609 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET_MSK 0x07000000
10610 
10611 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_CLR_MSK 0xf8ffffff
10612 
10613 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_RESET 0x0
10614 
10615 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_GET(value) (((value) & 0x07000000) >> 24)
10616 
10617 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_WTSEL_SET(value) (((value) << 24) & 0x07000000)
10618 
10626 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_LSB 28
10627 
10628 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_MSB 29
10629 
10630 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_WIDTH 2
10631 
10632 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET_MSK 0x30000000
10633 
10634 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_CLR_MSK 0xcfffffff
10635 
10636 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_RESET 0x1
10637 
10638 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_GET(value) (((value) & 0x30000000) >> 28)
10639 
10640 #define ALT_SYSMGR_TSMC_TSEL_1_ETF_RTSEL_SET(value) (((value) << 28) & 0x30000000)
10641 
10642 #ifndef __ASSEMBLY__
10643 
10654 {
10655  uint32_t ocram_wtsel : 3;
10656  uint32_t : 1;
10657  uint32_t ocram_rtsel : 2;
10658  uint32_t : 2;
10659  uint32_t otg_wtsel : 3;
10660  uint32_t : 1;
10661  uint32_t otg_rtsel : 2;
10662  uint32_t : 2;
10663  uint32_t qspi_wtsel : 3;
10664  uint32_t : 1;
10665  uint32_t qspi_rtsel : 2;
10666  uint32_t : 2;
10667  uint32_t etf_wtsel : 3;
10668  uint32_t : 1;
10669  uint32_t etf_rtsel : 2;
10670  uint32_t : 2;
10671 };
10672 
10675 #endif /* __ASSEMBLY__ */
10676 
10678 #define ALT_SYSMGR_TSMC_TSEL_1_RESET 0x10101010
10679 
10680 #define ALT_SYSMGR_TSMC_TSEL_1_OFST 0x104
10681 
10714 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_LSB 0
10715 
10716 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_MSB 1
10717 
10718 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_WIDTH 2
10719 
10720 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET_MSK 0x00000003
10721 
10722 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_CLR_MSK 0xfffffffc
10723 
10724 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_RESET 0x2
10725 
10726 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_GET(value) (((value) & 0x00000003) >> 0)
10727 
10728 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_WCT_SET(value) (((value) << 0) & 0x00000003)
10729 
10737 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_LSB 2
10738 
10739 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_MSB 3
10740 
10741 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_WIDTH 2
10742 
10743 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET_MSK 0x0000000c
10744 
10745 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_CLR_MSK 0xfffffff3
10746 
10747 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_RESET 0x2
10748 
10749 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_GET(value) (((value) & 0x0000000c) >> 2)
10750 
10751 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_RCT_SET(value) (((value) << 2) & 0x0000000c)
10752 
10760 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_LSB 4
10761 
10762 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_MSB 6
10763 
10764 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_WIDTH 3
10765 
10766 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET_MSK 0x00000070
10767 
10768 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_CLR_MSK 0xffffff8f
10769 
10770 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_RESET 0x4
10771 
10772 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_GET(value) (((value) & 0x00000070) >> 4)
10773 
10774 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_KP_SET(value) (((value) << 4) & 0x00000070)
10775 
10783 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_LSB 7
10784 
10785 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_MSB 7
10786 
10787 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_WIDTH 1
10788 
10789 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET_MSK 0x00000080
10790 
10791 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_CLR_MSK 0xffffff7f
10792 
10793 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_RESET 0x0
10794 
10795 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_GET(value) (((value) & 0x00000080) >> 7)
10796 
10797 #define ALT_SYSMGR_TSMC_TSEL_2_NANDECC_TM_SET(value) (((value) << 7) & 0x00000080)
10798 
10806 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_LSB 8
10807 
10808 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_MSB 9
10809 
10810 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_WIDTH 2
10811 
10812 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET_MSK 0x00000300
10813 
10814 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_CLR_MSK 0xfffffcff
10815 
10816 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_RESET 0x2
10817 
10818 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_GET(value) (((value) & 0x00000300) >> 8)
10819 
10820 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_WCT_SET(value) (((value) << 8) & 0x00000300)
10821 
10829 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_LSB 10
10830 
10831 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_MSB 11
10832 
10833 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_WIDTH 2
10834 
10835 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET_MSK 0x00000c00
10836 
10837 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_CLR_MSK 0xfffff3ff
10838 
10839 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_RESET 0x2
10840 
10841 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_GET(value) (((value) & 0x00000c00) >> 10)
10842 
10843 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_RCT_SET(value) (((value) << 10) & 0x00000c00)
10844 
10852 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_LSB 12
10853 
10854 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_MSB 14
10855 
10856 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_WIDTH 3
10857 
10858 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET_MSK 0x00007000
10859 
10860 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_CLR_MSK 0xffff8fff
10861 
10862 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_RESET 0x4
10863 
10864 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_GET(value) (((value) & 0x00007000) >> 12)
10865 
10866 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_KP_SET(value) (((value) << 12) & 0x00007000)
10867 
10875 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_LSB 15
10876 
10877 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_MSB 15
10878 
10879 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_WIDTH 1
10880 
10881 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET_MSK 0x00008000
10882 
10883 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_CLR_MSK 0xffff7fff
10884 
10885 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_RESET 0x0
10886 
10887 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_GET(value) (((value) & 0x00008000) >> 15)
10888 
10889 #define ALT_SYSMGR_TSMC_TSEL_2_NANDWR_TM_SET(value) (((value) << 15) & 0x00008000)
10890 
10898 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_LSB 16
10899 
10900 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_MSB 17
10901 
10902 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_WIDTH 2
10903 
10904 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET_MSK 0x00030000
10905 
10906 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_CLR_MSK 0xfffcffff
10907 
10908 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_RESET 0x2
10909 
10910 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_GET(value) (((value) & 0x00030000) >> 16)
10911 
10912 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_WCT_SET(value) (((value) << 16) & 0x00030000)
10913 
10921 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_LSB 18
10922 
10923 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_MSB 19
10924 
10925 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_WIDTH 2
10926 
10927 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET_MSK 0x000c0000
10928 
10929 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_CLR_MSK 0xfff3ffff
10930 
10931 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_RESET 0x2
10932 
10933 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_GET(value) (((value) & 0x000c0000) >> 18)
10934 
10935 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_RCT_SET(value) (((value) << 18) & 0x000c0000)
10936 
10944 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_LSB 20
10945 
10946 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_MSB 22
10947 
10948 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_WIDTH 3
10949 
10950 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET_MSK 0x00700000
10951 
10952 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_CLR_MSK 0xff8fffff
10953 
10954 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_RESET 0x4
10955 
10956 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_GET(value) (((value) & 0x00700000) >> 20)
10957 
10958 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_KP_SET(value) (((value) << 20) & 0x00700000)
10959 
10967 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_LSB 23
10968 
10969 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_MSB 23
10970 
10971 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_WIDTH 1
10972 
10973 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET_MSK 0x00800000
10974 
10975 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_CLR_MSK 0xff7fffff
10976 
10977 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_RESET 0x0
10978 
10979 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_GET(value) (((value) & 0x00800000) >> 23)
10980 
10981 #define ALT_SYSMGR_TSMC_TSEL_2_NANDRD_TM_SET(value) (((value) << 23) & 0x00800000)
10982 
10990 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_LSB 24
10991 
10992 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_MSB 25
10993 
10994 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_WIDTH 2
10995 
10996 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET_MSK 0x03000000
10997 
10998 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_CLR_MSK 0xfcffffff
10999 
11000 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_RESET 0x2
11001 
11002 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_GET(value) (((value) & 0x03000000) >> 24)
11003 
11004 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_WCT_SET(value) (((value) << 24) & 0x03000000)
11005 
11013 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_LSB 26
11014 
11015 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_MSB 27
11016 
11017 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_WIDTH 2
11018 
11019 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET_MSK 0x0c000000
11020 
11021 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_CLR_MSK 0xf3ffffff
11022 
11023 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_RESET 0x2
11024 
11025 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_GET(value) (((value) & 0x0c000000) >> 26)
11026 
11027 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_RCT_SET(value) (((value) << 26) & 0x0c000000)
11028 
11036 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_LSB 28
11037 
11038 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_MSB 30
11039 
11040 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_WIDTH 3
11041 
11042 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET_MSK 0x70000000
11043 
11044 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_CLR_MSK 0x8fffffff
11045 
11046 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_RESET 0x4
11047 
11048 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_GET(value) (((value) & 0x70000000) >> 28)
11049 
11050 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_KP_SET(value) (((value) << 28) & 0x70000000)
11051 
11059 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_LSB 31
11060 
11061 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_MSB 31
11062 
11063 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_WIDTH 1
11064 
11065 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET_MSK 0x80000000
11066 
11067 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_CLR_MSK 0x7fffffff
11068 
11069 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_RESET 0x0
11070 
11071 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_GET(value) (((value) & 0x80000000) >> 31)
11072 
11073 #define ALT_SYSMGR_TSMC_TSEL_2_SDMMC_TM_SET(value) (((value) << 31) & 0x80000000)
11074 
11075 #ifndef __ASSEMBLY__
11076 
11087 {
11088  uint32_t nandecc_wct : 2;
11089  uint32_t nandecc_rct : 2;
11090  uint32_t nandecc_kp : 3;
11091  uint32_t nandecc_tm : 1;
11092  uint32_t nandwr_wct : 2;
11093  uint32_t nandwr_rct : 2;
11094  uint32_t nandwr_kp : 3;
11095  uint32_t nandwr_tm : 1;
11096  uint32_t nandrd_wct : 2;
11097  uint32_t nandrd_rct : 2;
11098  uint32_t nandrd_kp : 3;
11099  uint32_t nandrd_tm : 1;
11100  uint32_t sdmmc_wct : 2;
11101  uint32_t sdmmc_rct : 2;
11102  uint32_t sdmmc_kp : 3;
11103  uint32_t sdmmc_tm : 1;
11104 };
11105 
11108 #endif /* __ASSEMBLY__ */
11109 
11111 #define ALT_SYSMGR_TSMC_TSEL_2_RESET 0x4a4a4a4a
11112 
11113 #define ALT_SYSMGR_TSMC_TSEL_2_OFST 0x108
11114 
11144 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_LSB 0
11145 
11146 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_MSB 1
11147 
11148 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_WIDTH 2
11149 
11150 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET_MSK 0x00000003
11151 
11152 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_CLR_MSK 0xfffffffc
11153 
11154 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_RESET 0x2
11155 
11156 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_GET(value) (((value) & 0x00000003) >> 0)
11157 
11158 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_WCT_SET(value) (((value) << 0) & 0x00000003)
11159 
11167 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_LSB 2
11168 
11169 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_MSB 3
11170 
11171 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_WIDTH 2
11172 
11173 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET_MSK 0x0000000c
11174 
11175 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_CLR_MSK 0xfffffff3
11176 
11177 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_RESET 0x2
11178 
11179 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_GET(value) (((value) & 0x0000000c) >> 2)
11180 
11181 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_RCT_SET(value) (((value) << 2) & 0x0000000c)
11182 
11190 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_LSB 4
11191 
11192 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_MSB 6
11193 
11194 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_WIDTH 3
11195 
11196 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET_MSK 0x00000070
11197 
11198 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_CLR_MSK 0xffffff8f
11199 
11200 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_RESET 0x4
11201 
11202 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_GET(value) (((value) & 0x00000070) >> 4)
11203 
11204 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_KP_SET(value) (((value) << 4) & 0x00000070)
11205 
11213 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_LSB 7
11214 
11215 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_MSB 7
11216 
11217 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_WIDTH 1
11218 
11219 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET_MSK 0x00000080
11220 
11221 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_CLR_MSK 0xffffff7f
11222 
11223 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_RESET 0x0
11224 
11225 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_GET(value) (((value) & 0x00000080) >> 7)
11226 
11227 #define ALT_SYSMGR_TSMC_TSEL_3_EMACRX_TM_SET(value) (((value) << 7) & 0x00000080)
11228 
11236 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_LSB 8
11237 
11238 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_MSB 9
11239 
11240 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_WIDTH 2
11241 
11242 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET_MSK 0x00000300
11243 
11244 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_CLR_MSK 0xfffffcff
11245 
11246 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_RESET 0x2
11247 
11248 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_GET(value) (((value) & 0x00000300) >> 8)
11249 
11250 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_WCT_SET(value) (((value) << 8) & 0x00000300)
11251 
11259 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_LSB 10
11260 
11261 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_MSB 11
11262 
11263 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_WIDTH 2
11264 
11265 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET_MSK 0x00000c00
11266 
11267 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_CLR_MSK 0xfffff3ff
11268 
11269 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_RESET 0x2
11270 
11271 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_GET(value) (((value) & 0x00000c00) >> 10)
11272 
11273 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_RCT_SET(value) (((value) << 10) & 0x00000c00)
11274 
11282 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_LSB 12
11283 
11284 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_MSB 14
11285 
11286 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_WIDTH 3
11287 
11288 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET_MSK 0x00007000
11289 
11290 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_CLR_MSK 0xffff8fff
11291 
11292 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_RESET 0x4
11293 
11294 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_GET(value) (((value) & 0x00007000) >> 12)
11295 
11296 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_KP_SET(value) (((value) << 12) & 0x00007000)
11297 
11305 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_LSB 15
11306 
11307 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_MSB 15
11308 
11309 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_WIDTH 1
11310 
11311 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET_MSK 0x00008000
11312 
11313 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_CLR_MSK 0xffff7fff
11314 
11315 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_RESET 0x0
11316 
11317 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_GET(value) (((value) & 0x00008000) >> 15)
11318 
11319 #define ALT_SYSMGR_TSMC_TSEL_3_EMACTX_TM_SET(value) (((value) << 15) & 0x00008000)
11320 
11328 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_LSB 16
11329 
11330 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_MSB 17
11331 
11332 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_WIDTH 2
11333 
11334 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET_MSK 0x00030000
11335 
11336 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_CLR_MSK 0xfffcffff
11337 
11338 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_RESET 0x2
11339 
11340 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_GET(value) (((value) & 0x00030000) >> 16)
11341 
11342 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_WCT_SET(value) (((value) << 16) & 0x00030000)
11343 
11351 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_LSB 18
11352 
11353 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_MSB 19
11354 
11355 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_WIDTH 2
11356 
11357 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET_MSK 0x000c0000
11358 
11359 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_CLR_MSK 0xfff3ffff
11360 
11361 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_RESET 0x2
11362 
11363 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_GET(value) (((value) & 0x000c0000) >> 18)
11364 
11365 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_RCT_SET(value) (((value) << 18) & 0x000c0000)
11366 
11374 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_LSB 20
11375 
11376 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_MSB 22
11377 
11378 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_WIDTH 3
11379 
11380 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET_MSK 0x00700000
11381 
11382 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_CLR_MSK 0xff8fffff
11383 
11384 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_RESET 0x4
11385 
11386 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_GET(value) (((value) & 0x00700000) >> 20)
11387 
11388 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_KP_SET(value) (((value) << 20) & 0x00700000)
11389 
11397 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_LSB 23
11398 
11399 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_MSB 23
11400 
11401 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_WIDTH 1
11402 
11403 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET_MSK 0x00800000
11404 
11405 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_CLR_MSK 0xff7fffff
11406 
11407 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_RESET 0x0
11408 
11409 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_GET(value) (((value) & 0x00800000) >> 23)
11410 
11411 #define ALT_SYSMGR_TSMC_TSEL_3_DMAC_TM_SET(value) (((value) << 23) & 0x00800000)
11412 
11413 #ifndef __ASSEMBLY__
11414 
11425 {
11426  uint32_t emacrx_wct : 2;
11427  uint32_t emacrx_rct : 2;
11428  uint32_t emacrx_kp : 3;
11429  uint32_t emacrx_tm : 1;
11430  uint32_t emactx_wct : 2;
11431  uint32_t emactx_rct : 2;
11432  uint32_t emactx_kp : 3;
11433  uint32_t emactx_tm : 1;
11434  uint32_t dmac_wct : 2;
11435  uint32_t dmac_rct : 2;
11436  uint32_t dmac_kp : 3;
11437  uint32_t dmac_tm : 1;
11438  uint32_t : 8;
11439 };
11440 
11443 #endif /* __ASSEMBLY__ */
11444 
11446 #define ALT_SYSMGR_TSMC_TSEL_3_RESET 0x004a4a4a
11447 
11448 #define ALT_SYSMGR_TSMC_TSEL_3_OFST 0x10c
11449 
11450 #ifndef __ASSEMBLY__
11451 
11462 {
11468  volatile uint32_t _pad_0x14_0x1f[3];
11481  volatile uint32_t _pad_0x50_0x5f[4];
11487  volatile uint32_t _pad_0x74_0x7f[3];
11491  volatile uint32_t _pad_0x8c_0x8f;
11502  volatile uint32_t _pad_0xb8_0xbf[2];
11510  volatile uint32_t _pad_0xdc_0xff[9];
11515  volatile uint32_t _pad_0x110_0x200[60];
11516 };
11517 
11519 typedef volatile struct ALT_SYSMGR_s ALT_SYSMGR_t;
11522 {
11523  volatile uint32_t siliconid1;
11524  volatile uint32_t siliconid2;
11525  volatile uint32_t wddbg;
11526  volatile uint32_t bootinfo;
11527  volatile uint32_t mpu_ctrl_l2_ecc;
11528  volatile uint32_t _pad_0x14_0x1f[3];
11529  volatile uint32_t dma;
11530  volatile uint32_t dma_periph;
11531  volatile uint32_t sdmmc;
11532  volatile uint32_t sdmmc_l3master;
11533  volatile uint32_t nand_bootstrap;
11534  volatile uint32_t nand_l3master;
11535  volatile uint32_t usb0_l3master;
11536  volatile uint32_t usb1_l3master;
11537  volatile uint32_t emac_global;
11538  volatile uint32_t emac0;
11539  volatile uint32_t emac1;
11540  volatile uint32_t emac2;
11541  volatile uint32_t _pad_0x50_0x5f[4];
11542  volatile uint32_t fpgaintf_en_global;
11543  volatile uint32_t fpgaintf_en_0;
11544  volatile uint32_t fpgaintf_en_1;
11545  volatile uint32_t fpgaintf_en_2;
11546  volatile uint32_t fpgaintf_en_3;
11547  volatile uint32_t _pad_0x74_0x7f[3];
11548  volatile uint32_t noc_addr_remap_value;
11549  volatile uint32_t noc_addr_remap_set;
11550  volatile uint32_t noc_addr_remap_clear;
11551  volatile uint32_t _pad_0x8c_0x8f;
11552  volatile uint32_t ecc_intmask_value;
11553  volatile uint32_t ecc_intmask_set;
11554  volatile uint32_t ecc_intmask_clr;
11555  volatile uint32_t ecc_intstatus_serr;
11556  volatile uint32_t ecc_intstatus_derr;
11557  volatile uint32_t mpu_status_l2_ecc;
11558  volatile uint32_t mpu_clear_l2_ecc;
11559  volatile uint32_t mpu_status_l1_parity;
11560  volatile uint32_t mpu_clear_l1_parity;
11561  volatile uint32_t mpu_set_l1_parity;
11562  volatile uint32_t _pad_0xb8_0xbf[2];
11563  volatile uint32_t noc_timeout;
11564  volatile uint32_t noc_idlereq_set;
11565  volatile uint32_t noc_idlereq_clr;
11566  volatile uint32_t noc_idlereq_value;
11567  volatile uint32_t noc_idleack;
11568  volatile uint32_t noc_idlestatus;
11569  volatile uint32_t fpga2soc_ctrl;
11570  volatile uint32_t _pad_0xdc_0xff[9];
11571  volatile uint32_t tsmc_tsel_0;
11572  volatile uint32_t tsmc_tsel_1;
11573  volatile uint32_t tsmc_tsel_2;
11574  volatile uint32_t tsmc_tsel_3;
11575  volatile uint32_t _pad_0x110_0x200[60];
11576 };
11577 
11579 typedef volatile struct ALT_SYSMGR_raw_s ALT_SYSMGR_raw_t;
11580 #endif /* __ASSEMBLY__ */
11581 
11624 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_DIS 0x0
11625 
11629 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_E_EN 0x1
11630 
11632 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_LSB 0
11633 
11634 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_MSB 0
11635 
11636 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_WIDTH 1
11637 
11638 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001
11639 
11640 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe
11641 
11642 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_RESET 0x0
11643 
11644 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0)
11645 
11646 #define ALT_SYSMGR_ROM_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001)
11647 
11648 #ifndef __ASSEMBLY__
11649 
11660 {
11661  uint32_t waitstate : 1;
11662  uint32_t : 31;
11663 };
11664 
11667 #endif /* __ASSEMBLY__ */
11668 
11670 #define ALT_SYSMGR_ROM_ROMHW_CTL_RESET 0x00000100
11671 
11672 #define ALT_SYSMGR_ROM_ROMHW_CTL_OFST 0x0
11673 
11713 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0
11714 
11718 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1
11719 
11721 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0
11722 
11723 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0
11724 
11725 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1
11726 
11727 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001
11728 
11729 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe
11730 
11731 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0
11732 
11733 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0)
11734 
11735 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001)
11736 
11760 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0
11761 
11765 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1
11766 
11768 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_LSB 1
11769 
11770 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_MSB 1
11771 
11772 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1
11773 
11774 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002
11775 
11776 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd
11777 
11778 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0
11779 
11780 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1)
11781 
11782 #define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002)
11783 
11784 #ifndef __ASSEMBLY__
11785 
11796 {
11797  uint32_t warmrstcfgpinmux : 1;
11798  uint32_t warmrstcfgio : 1;
11799  uint32_t : 30;
11800 };
11801 
11804 #endif /* __ASSEMBLY__ */
11805 
11807 #define ALT_SYSMGR_ROM_ROMCODE_CTL_RESET 0x00000000
11808 
11809 #define ALT_SYSMGR_ROM_ROMCODE_CTL_OFST 0x4
11810 
11852 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_LSB 0
11853 
11854 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_MSB 31
11855 
11856 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_WIDTH 32
11857 
11858 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET_MSK 0xffffffff
11859 
11860 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_CLR_MSK 0x00000000
11861 
11862 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_RESET 0x0
11863 
11864 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11865 
11866 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11867 
11868 #ifndef __ASSEMBLY__
11869 
11880 {
11881  uint32_t value : 32;
11882 };
11883 
11886 #endif /* __ASSEMBLY__ */
11887 
11889 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_RESET 0x00000000
11890 
11891 #define ALT_SYSMGR_ROM_ROMCODE_QSPI_RST_CMD_OFST 0x8
11892 
11927 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_INVALID 0x0
11928 
11932 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_E_VALID 0x49535756
11933 
11935 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_LSB 0
11936 
11937 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_MSB 31
11938 
11939 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_WIDTH 32
11940 
11941 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET_MSK 0xffffffff
11942 
11943 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_CLR_MSK 0x00000000
11944 
11945 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_RESET 0x0
11946 
11947 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
11948 
11949 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
11950 
11951 #ifndef __ASSEMBLY__
11952 
11963 {
11964  uint32_t value : 32;
11965 };
11966 
11969 #endif /* __ASSEMBLY__ */
11970 
11972 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_RESET 0x00000000
11973 
11974 #define ALT_SYSMGR_ROM_ROMCODE_INITSWSTATE_OFST 0xc
11975 
12001 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_LSB 0
12002 
12003 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_MSB 1
12004 
12005 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_WIDTH 2
12006 
12007 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET_MSK 0x00000003
12008 
12009 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_CLR_MSK 0xfffffffc
12010 
12011 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_RESET 0x0
12012 
12013 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_GET(value) (((value) & 0x00000003) >> 0)
12014 
12015 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_INDEX_SET(value) (((value) << 0) & 0x00000003)
12016 
12017 #ifndef __ASSEMBLY__
12018 
12029 {
12030  uint32_t index : 2;
12031  uint32_t : 30;
12032 };
12033 
12036 #endif /* __ASSEMBLY__ */
12037 
12039 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_RESET 0x00000000
12040 
12041 #define ALT_SYSMGR_ROM_ROMCODE_INITSWLASTLD_OFST 0x10
12042 
12080 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_DISD 0x0
12081 
12085 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_E_END 0xae9efebc
12086 
12088 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_LSB 0
12089 
12090 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_MSB 31
12091 
12092 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_WIDTH 32
12093 
12094 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET_MSK 0xffffffff
12095 
12096 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_CLR_MSK 0x00000000
12097 
12098 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_RESET 0x0
12099 
12100 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_GET(value) (((value) & 0xffffffff) >> 0)
12101 
12102 #define ALT_SYSMGR_ROM_WARMRAM_EN_MAGIC_SET(value) (((value) << 0) & 0xffffffff)
12103 
12104 #ifndef __ASSEMBLY__
12105 
12116 {
12117  uint32_t magic : 32;
12118 };
12119 
12122 #endif /* __ASSEMBLY__ */
12123 
12125 #define ALT_SYSMGR_ROM_WARMRAM_EN_RESET 0x00000000
12126 
12127 #define ALT_SYSMGR_ROM_WARMRAM_EN_OFST 0x18
12128 
12155 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_LSB 0
12156 
12157 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_MSB 31
12158 
12159 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_WIDTH 32
12160 
12161 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET_MSK 0xffffffff
12162 
12163 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_CLR_MSK 0x00000000
12164 
12165 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_RESET 0x0
12166 
12167 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12168 
12169 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12170 
12171 #ifndef __ASSEMBLY__
12172 
12183 {
12184  uint32_t offset : 32;
12185 };
12186 
12189 #endif /* __ASSEMBLY__ */
12190 
12192 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_RESET 0x00000000
12193 
12194 #define ALT_SYSMGR_ROM_WARMRAM_DATASTART_OFST 0x1c
12195 
12230 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_LSB 0
12231 
12232 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_MSB 31
12233 
12234 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_WIDTH 32
12235 
12236 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET_MSK 0xffffffff
12237 
12238 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_CLR_MSK 0x00000000
12239 
12240 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_RESET 0x0
12241 
12242 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_GET(value) (((value) & 0xffffffff) >> 0)
12243 
12244 #define ALT_SYSMGR_ROM_WARMRAM_LEN_SIZE_SET(value) (((value) << 0) & 0xffffffff)
12245 
12246 #ifndef __ASSEMBLY__
12247 
12258 {
12259  uint32_t size : 32;
12260 };
12261 
12264 #endif /* __ASSEMBLY__ */
12265 
12267 #define ALT_SYSMGR_ROM_WARMRAM_LEN_RESET 0x00000000
12268 
12269 #define ALT_SYSMGR_ROM_WARMRAM_LEN_OFST 0x20
12270 
12297 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_LSB 0
12298 
12299 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_MSB 31
12300 
12301 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_WIDTH 32
12302 
12303 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET_MSK 0xffffffff
12304 
12305 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_CLR_MSK 0x00000000
12306 
12307 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_RESET 0x0
12308 
12309 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_GET(value) (((value) & 0xffffffff) >> 0)
12310 
12311 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFFSET_SET(value) (((value) << 0) & 0xffffffff)
12312 
12313 #ifndef __ASSEMBLY__
12314 
12325 {
12326  uint32_t offset : 32;
12327 };
12328 
12331 #endif /* __ASSEMBLY__ */
12332 
12334 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_RESET 0x00000000
12335 
12336 #define ALT_SYSMGR_ROM_WARMRAM_EXECUTION_OFST 0x24
12337 
12376 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_LSB 0
12377 
12378 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_MSB 31
12379 
12380 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_WIDTH 32
12381 
12382 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET_MSK 0xffffffff
12383 
12384 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_CLR_MSK 0x00000000
12385 
12386 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_RESET 0x0
12387 
12388 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_GET(value) (((value) & 0xffffffff) >> 0)
12389 
12390 #define ALT_SYSMGR_ROM_WARMRAM_CRC_EXPECTED_SET(value) (((value) << 0) & 0xffffffff)
12391 
12392 #ifndef __ASSEMBLY__
12393 
12404 {
12405  uint32_t expected : 32;
12406 };
12407 
12410 #endif /* __ASSEMBLY__ */
12411 
12413 #define ALT_SYSMGR_ROM_WARMRAM_CRC_RESET 0x00000000
12414 
12415 #define ALT_SYSMGR_ROM_WARMRAM_CRC_OFST 0x28
12416 
12442 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_LSB 0
12443 
12444 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_MSB 31
12445 
12446 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_WIDTH 32
12447 
12448 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET_MSK 0xffffffff
12449 
12450 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_CLR_MSK 0x00000000
12451 
12452 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_RESET 0x0
12453 
12454 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_GET(value) (((value) & 0xffffffff) >> 0)
12455 
12456 #define ALT_SYSMGR_ROM_ISW_HANDOFF_ISW_HANDOFF_SET(value) (((value) << 0) & 0xffffffff)
12457 
12458 #ifndef __ASSEMBLY__
12459 
12470 {
12471  uint32_t isw_handoff : 32;
12472 };
12473 
12476 #endif /* __ASSEMBLY__ */
12477 
12479 #define ALT_SYSMGR_ROM_ISW_HANDOFF_RESET 0x00000000
12480 
12481 #define ALT_SYSMGR_ROM_ISW_HANDOFF_OFST 0x30
12482 
12505 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_LSB 0
12506 
12507 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_MSB 31
12508 
12509 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_WIDTH 32
12510 
12511 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET_MSK 0xffffffff
12512 
12513 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_CLR_MSK 0x00000000
12514 
12515 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_RESET 0x0
12516 
12517 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12518 
12519 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12520 
12521 #ifndef __ASSEMBLY__
12522 
12533 {
12534  uint32_t value : 32;
12535 };
12536 
12539 #endif /* __ASSEMBLY__ */
12540 
12542 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_RESET 0x00000000
12543 
12544 #define ALT_SYSMGR_ROM_ROMCODE_BOOTROMSWSTATE_OFST 0x50
12545 
12569 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_LSB 0
12570 
12571 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_MSB 31
12572 
12573 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_WIDTH 32
12574 
12575 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET_MSK 0xffffffff
12576 
12577 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_CLR_MSK 0x00000000
12578 
12579 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_RESET 0x0
12580 
12581 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12582 
12583 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12584 
12585 #ifndef __ASSEMBLY__
12586 
12597 {
12598  uint32_t value : 32;
12599 };
12600 
12603 #endif /* __ASSEMBLY__ */
12604 
12606 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_RESET 0x00000000
12607 
12608 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_WARMCLR_OFST 0x70
12609 
12633 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_LSB 0
12634 
12635 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_MSB 31
12636 
12637 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_WIDTH 32
12638 
12639 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET_MSK 0xffffffff
12640 
12641 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_CLR_MSK 0x00000000
12642 
12643 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_RESET 0x0
12644 
12645 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
12646 
12647 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
12648 
12649 #ifndef __ASSEMBLY__
12650 
12661 {
12662  uint32_t value : 32;
12663 };
12664 
12667 #endif /* __ASSEMBLY__ */
12668 
12670 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_RESET 0x00000000
12671 
12672 #define ALT_SYSMGR_ROM_ROMCODE_STICKYSET_COLDCLR_OFST 0x74
12673 
12674 #ifndef __ASSEMBLY__
12675 
12686 {
12692  volatile uint32_t _pad_0x14_0x17;
12698  volatile uint32_t _pad_0x2c_0x2f;
12703  volatile uint32_t _pad_0x78_0x100[34];
12704 };
12705 
12707 typedef volatile struct ALT_SYSMGR_ROM_s ALT_SYSMGR_ROM_t;
12710 {
12711  volatile uint32_t romhw_ctrl;
12712  volatile uint32_t romcode_ctrl;
12713  volatile uint32_t romcode_qspi_reset_command;
12714  volatile uint32_t romcode_initswstate;
12715  volatile uint32_t romcode_initswlastld;
12716  volatile uint32_t _pad_0x14_0x17;
12717  volatile uint32_t warmram_enable;
12718  volatile uint32_t warmram_datastart;
12719  volatile uint32_t warmram_length;
12720  volatile uint32_t warmram_execution;
12721  volatile uint32_t warmram_crc;
12722  volatile uint32_t _pad_0x2c_0x2f;
12723  volatile uint32_t isw_handoff[8];
12724  volatile uint32_t romcode_bootromswstate[8];
12725  volatile uint32_t romcode_stickyset_warmclr;
12726  volatile uint32_t romcode_stickyset_coldclr;
12727  volatile uint32_t _pad_0x78_0x100[34];
12728 };
12729 
12732 #endif /* __ASSEMBLY__ */
12733 
12735 #ifdef __cplusplus
12736 }
12737 #endif /* __cplusplus */
12738 #endif /* __ALT_SOCAL_SYSMGR_H__ */
12739