Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : INTSTAT

Description

This bit is used to enable interrupt generation on SERR lookup table overflow. When all the entries in the table are valid=1 and this is bit is enabled, serr_req signal will be asserted.

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA
[7:1] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA
[31:9] ??? 0x0 UNDEFINED

Field : SERRPENA

Single-bit error pending for PORTA.

Field Access Macros:

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_LSB   0
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_MSB   0
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_WIDTH   1
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET_MSK   0x00000001
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_CLR_MSK   0xfffffffe
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_RESET   0x0
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET(value)   (((value) << 0) & 0x00000001)
 

Field : DERRPENA

Double-bit error pending for PORTA.

Field Access Macros:

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_LSB   8
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_MSB   8
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_WIDTH   1
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET_MSK   0x00000100
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_CLR_MSK   0xfffffeff
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_RESET   0x0
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET(value)   (((value) << 8) & 0x00000100)
 

Data Structures

struct  ALT_ECC_EMAC1_TX_ECC_INTSTAT_s
 

Macros

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_RESET   0x00000000
 
#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_OFST   0x20
 

Typedefs

typedef struct
ALT_ECC_EMAC1_TX_ECC_INTSTAT_s 
ALT_ECC_EMAC1_TX_ECC_INTSTAT_t
 

Data Structure Documentation

struct ALT_ECC_EMAC1_TX_ECC_INTSTAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_EMAC1_TX_ECC_INTSTAT.

Data Fields
uint32_t SERRPENA: 1 ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA
uint32_t __pad0__: 7 UNDEFINED
uint32_t DERRPENA: 1 ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA
uint32_t __pad1__: 23 UNDEFINED

Macro Definitions

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_WIDTH   1

The width in bits of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET_MSK   0x00000001

The mask used to set the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field value.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field value.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_RESET   0x0

The reset value of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA field value from a register.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_EMAC1_TX_ECC_INTSTAT_SERRPENA register field value suitable for setting the register.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_MSB   8

The Most Significant Bit (MSB) position of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_WIDTH   1

The width in bits of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET_MSK   0x00000100

The mask used to set the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field value.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_CLR_MSK   0xfffffeff

The mask used to clear the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field value.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_RESET   0x0

The reset value of the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA field value from a register.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_ECC_EMAC1_TX_ECC_INTSTAT_DERRPENA register field value suitable for setting the register.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_RESET   0x00000000

The reset value of the ALT_ECC_EMAC1_TX_ECC_INTSTAT register.

#define ALT_ECC_EMAC1_TX_ECC_INTSTAT_OFST   0x20

The byte offset of the ALT_ECC_EMAC1_TX_ECC_INTSTAT register from the beginning of the component.

Typedef Documentation