Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : intmask

Description

Interrupt Mask Register

Register Layout

Bits Access Reset Description
[0] RW 0x0 Interrupt Mask
[1] RW 0x0 Interrupt Mask
[2] RW 0x0 Command Done
[3] RW 0x0 Data Transfer Over
[4] RW 0x0 Transmit FIFO Data Request
[5] RW 0x0 Receive FIFO Data Request (
[6] RW 0x0 Response CRC Error
[7] RW 0x0 Data CRC Error
[8] RW 0x0 Response Timeout
[9] RW 0x0 Data Read Timeout
[10] RW 0x0 Data Starvation Host Timeout
[11] RW 0x0 FIFO Underrun Overrun Error
[12] RW 0x0 Hardware Locked Write Error
[13] RW 0x0 Start-bit Error
[14] RW 0x0 Auto Command Done
[15] RW 0x0 End-bit Error Read Write no CRC
[31:16] RW 0x0 ALT_SDMMC_INTMSK_SDIO_INT_MSK

Field : Interrupt Mask - cd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_CD_E_MSK 0x0 Card Detected Mask
ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1 Card Detect No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_CD_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_CD_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_CD_LSB   0
 
#define ALT_SDMMC_INTMSK_CD_MSB   0
 
#define ALT_SDMMC_INTMSK_CD_WIDTH   1
 
#define ALT_SDMMC_INTMSK_CD_SET_MSK   0x00000001
 
#define ALT_SDMMC_INTMSK_CD_CLR_MSK   0xfffffffe
 
#define ALT_SDMMC_INTMSK_CD_RESET   0x0
 
#define ALT_SDMMC_INTMSK_CD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SDMMC_INTMSK_CD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Interrupt Mask - re

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_RE_E_MSK 0x0 Response error Mask
ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1 Response error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_RE_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_RE_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_RE_LSB   1
 
#define ALT_SDMMC_INTMSK_RE_MSB   1
 
#define ALT_SDMMC_INTMSK_RE_WIDTH   1
 
#define ALT_SDMMC_INTMSK_RE_SET_MSK   0x00000002
 
#define ALT_SDMMC_INTMSK_RE_CLR_MSK   0xfffffffd
 
#define ALT_SDMMC_INTMSK_RE_RESET   0x0
 
#define ALT_SDMMC_INTMSK_RE_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SDMMC_INTMSK_RE_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Command Done - cmd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_CMD_E_MSK 0x0 Command Done Mask
ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1 Command Done No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_CMD_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_CMD_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_CMD_LSB   2
 
#define ALT_SDMMC_INTMSK_CMD_MSB   2
 
#define ALT_SDMMC_INTMSK_CMD_WIDTH   1
 
#define ALT_SDMMC_INTMSK_CMD_SET_MSK   0x00000004
 
#define ALT_SDMMC_INTMSK_CMD_CLR_MSK   0xfffffffb
 
#define ALT_SDMMC_INTMSK_CMD_RESET   0x0
 
#define ALT_SDMMC_INTMSK_CMD_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SDMMC_INTMSK_CMD_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Data Transfer Over - dto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_DTO_E_MSK 0x0 Data transfer over Mask
ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1 Data transfer over No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_DTO_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_DTO_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_DTO_LSB   3
 
#define ALT_SDMMC_INTMSK_DTO_MSB   3
 
#define ALT_SDMMC_INTMSK_DTO_WIDTH   1
 
#define ALT_SDMMC_INTMSK_DTO_SET_MSK   0x00000008
 
#define ALT_SDMMC_INTMSK_DTO_CLR_MSK   0xfffffff7
 
#define ALT_SDMMC_INTMSK_DTO_RESET   0x0
 
#define ALT_SDMMC_INTMSK_DTO_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SDMMC_INTMSK_DTO_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Transmit FIFO Data Request - txdr

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0 Transmit FIFO data request Mask
ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1 Transmit FIFO data request No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_TXDR_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_TXDR_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_TXDR_LSB   4
 
#define ALT_SDMMC_INTMSK_TXDR_MSB   4
 
#define ALT_SDMMC_INTMSK_TXDR_WIDTH   1
 
#define ALT_SDMMC_INTMSK_TXDR_SET_MSK   0x00000010
 
#define ALT_SDMMC_INTMSK_TXDR_CLR_MSK   0xffffffef
 
#define ALT_SDMMC_INTMSK_TXDR_RESET   0x0
 
#define ALT_SDMMC_INTMSK_TXDR_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SDMMC_INTMSK_TXDR_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Receive FIFO Data Request ( - rxdr

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0 Receive FIFO data request Mask
ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1 Receive FIFO data request No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_RXDR_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_RXDR_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_RXDR_LSB   5
 
#define ALT_SDMMC_INTMSK_RXDR_MSB   5
 
#define ALT_SDMMC_INTMSK_RXDR_WIDTH   1
 
#define ALT_SDMMC_INTMSK_RXDR_SET_MSK   0x00000020
 
#define ALT_SDMMC_INTMSK_RXDR_CLR_MSK   0xffffffdf
 
#define ALT_SDMMC_INTMSK_RXDR_RESET   0x0
 
#define ALT_SDMMC_INTMSK_RXDR_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SDMMC_INTMSK_RXDR_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Response CRC Error - rcrc

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0 Response CRC error Mask
ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1 Response CRC error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_RCRC_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_RCRC_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_RCRC_LSB   6
 
#define ALT_SDMMC_INTMSK_RCRC_MSB   6
 
#define ALT_SDMMC_INTMSK_RCRC_WIDTH   1
 
#define ALT_SDMMC_INTMSK_RCRC_SET_MSK   0x00000040
 
#define ALT_SDMMC_INTMSK_RCRC_CLR_MSK   0xffffffbf
 
#define ALT_SDMMC_INTMSK_RCRC_RESET   0x0
 
#define ALT_SDMMC_INTMSK_RCRC_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SDMMC_INTMSK_RCRC_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Data CRC Error - dcrc

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0 Data CRC error Mask
ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1 Data CRC error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_DCRC_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_DCRC_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_DCRC_LSB   7
 
#define ALT_SDMMC_INTMSK_DCRC_MSB   7
 
#define ALT_SDMMC_INTMSK_DCRC_WIDTH   1
 
#define ALT_SDMMC_INTMSK_DCRC_SET_MSK   0x00000080
 
#define ALT_SDMMC_INTMSK_DCRC_CLR_MSK   0xffffff7f
 
#define ALT_SDMMC_INTMSK_DCRC_RESET   0x0
 
#define ALT_SDMMC_INTMSK_DCRC_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SDMMC_INTMSK_DCRC_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Response Timeout - rto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_RTO_E_MSK 0x0 Response timeout Mask
ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1 Response timeout No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_RTO_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_RTO_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_RTO_LSB   8
 
#define ALT_SDMMC_INTMSK_RTO_MSB   8
 
#define ALT_SDMMC_INTMSK_RTO_WIDTH   1
 
#define ALT_SDMMC_INTMSK_RTO_SET_MSK   0x00000100
 
#define ALT_SDMMC_INTMSK_RTO_CLR_MSK   0xfffffeff
 
#define ALT_SDMMC_INTMSK_RTO_RESET   0x0
 
#define ALT_SDMMC_INTMSK_RTO_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SDMMC_INTMSK_RTO_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Data Read Timeout - drt

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_DRT_E_MSK 0x0 Data read timeout Mask
ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1 Data read timeout No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_DRT_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_DRT_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_DRT_LSB   9
 
#define ALT_SDMMC_INTMSK_DRT_MSB   9
 
#define ALT_SDMMC_INTMSK_DRT_WIDTH   1
 
#define ALT_SDMMC_INTMSK_DRT_SET_MSK   0x00000200
 
#define ALT_SDMMC_INTMSK_DRT_CLR_MSK   0xfffffdff
 
#define ALT_SDMMC_INTMSK_DRT_RESET   0x0
 
#define ALT_SDMMC_INTMSK_DRT_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SDMMC_INTMSK_DRT_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Data Starvation Host Timeout - hto

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_HTO_E_MSK 0x0 Data starvation by host timeout Mask
ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1 Data starvation by host timeout No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_HTO_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_HTO_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_HTO_LSB   10
 
#define ALT_SDMMC_INTMSK_HTO_MSB   10
 
#define ALT_SDMMC_INTMSK_HTO_WIDTH   1
 
#define ALT_SDMMC_INTMSK_HTO_SET_MSK   0x00000400
 
#define ALT_SDMMC_INTMSK_HTO_CLR_MSK   0xfffffbff
 
#define ALT_SDMMC_INTMSK_HTO_RESET   0x0
 
#define ALT_SDMMC_INTMSK_HTO_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SDMMC_INTMSK_HTO_SET(value)   (((value) << 10) & 0x00000400)
 

Field : FIFO Underrun Overrun Error - frun

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0 FIFO underrun/overrun error Mask
ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1 FIFO underrun/overrun error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_FRUN_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_FRUN_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_FRUN_LSB   11
 
#define ALT_SDMMC_INTMSK_FRUN_MSB   11
 
#define ALT_SDMMC_INTMSK_FRUN_WIDTH   1
 
#define ALT_SDMMC_INTMSK_FRUN_SET_MSK   0x00000800
 
#define ALT_SDMMC_INTMSK_FRUN_CLR_MSK   0xfffff7ff
 
#define ALT_SDMMC_INTMSK_FRUN_RESET   0x0
 
#define ALT_SDMMC_INTMSK_FRUN_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SDMMC_INTMSK_FRUN_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Hardware Locked Write Error - hle

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_HLE_E_MSK 0x0 Hardware locked write error Mask
ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1 Hardware locked write error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_HLE_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_HLE_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_HLE_LSB   12
 
#define ALT_SDMMC_INTMSK_HLE_MSB   12
 
#define ALT_SDMMC_INTMSK_HLE_WIDTH   1
 
#define ALT_SDMMC_INTMSK_HLE_SET_MSK   0x00001000
 
#define ALT_SDMMC_INTMSK_HLE_CLR_MSK   0xffffefff
 
#define ALT_SDMMC_INTMSK_HLE_RESET   0x0
 
#define ALT_SDMMC_INTMSK_HLE_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_SDMMC_INTMSK_HLE_SET(value)   (((value) << 12) & 0x00001000)
 

Field : Start-bit Error - sbe

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_SBE_E_MSK 0x0 Start-bit error Mask
ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1 Start-bit error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_SBE_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_SBE_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_SBE_LSB   13
 
#define ALT_SDMMC_INTMSK_SBE_MSB   13
 
#define ALT_SDMMC_INTMSK_SBE_WIDTH   1
 
#define ALT_SDMMC_INTMSK_SBE_SET_MSK   0x00002000
 
#define ALT_SDMMC_INTMSK_SBE_CLR_MSK   0xffffdfff
 
#define ALT_SDMMC_INTMSK_SBE_RESET   0x0
 
#define ALT_SDMMC_INTMSK_SBE_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_SDMMC_INTMSK_SBE_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Auto Command Done - acd

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_ACD_E_MSK 0x0 Auto command done Mask
ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1 Auto command done No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_ACD_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_ACD_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_ACD_LSB   14
 
#define ALT_SDMMC_INTMSK_ACD_MSB   14
 
#define ALT_SDMMC_INTMSK_ACD_WIDTH   1
 
#define ALT_SDMMC_INTMSK_ACD_SET_MSK   0x00004000
 
#define ALT_SDMMC_INTMSK_ACD_CLR_MSK   0xffffbfff
 
#define ALT_SDMMC_INTMSK_ACD_RESET   0x0
 
#define ALT_SDMMC_INTMSK_ACD_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_SDMMC_INTMSK_ACD_SET(value)   (((value) << 14) & 0x00004000)
 

Field : End-bit Error Read Write no CRC - ebe

Bits used to mask unwanted interrupts. Value of 0 masks interrupts, value of 1 enables interrupt.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_EBE_E_MSK 0x0 End-bit error Mask
ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1 End-bit error No Mask

Field Access Macros:

#define ALT_SDMMC_INTMSK_EBE_E_MSK   0x0
 
#define ALT_SDMMC_INTMSK_EBE_E_NOMSK   0x1
 
#define ALT_SDMMC_INTMSK_EBE_LSB   15
 
#define ALT_SDMMC_INTMSK_EBE_MSB   15
 
#define ALT_SDMMC_INTMSK_EBE_WIDTH   1
 
#define ALT_SDMMC_INTMSK_EBE_SET_MSK   0x00008000
 
#define ALT_SDMMC_INTMSK_EBE_CLR_MSK   0xffff7fff
 
#define ALT_SDMMC_INTMSK_EBE_RESET   0x0
 
#define ALT_SDMMC_INTMSK_EBE_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_SDMMC_INTMSK_EBE_SET(value)   (((value) << 15) & 0x00008000)
 

Field : sdio_int_mask

Mask SDIO interrupts

One bit for each card. Bit[31] corresponds to card[15], and bit[16] corresponds to card[0]. When masked, SDIO interrupt detection for that card is disabled. A 0 masks an interrupt, and 1 enables an interrupt.

In MMC-Ver3.3-only mode, these bits are always 0.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0 SDIO Mask Interrupt Disabled
ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1 SDIO Interrupt Enabled

Field Access Macros:

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD   0x0
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END   0x1
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB   16
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB   31
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH   16
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK   0xffff0000
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK   0x0000ffff
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET   0x0
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_SDMMC_INTMSK_s
 

Macros

#define ALT_SDMMC_INTMSK_RESET   0x00000000
 
#define ALT_SDMMC_INTMSK_OFST   0x24
 

Typedefs

typedef struct ALT_SDMMC_INTMSK_s ALT_SDMMC_INTMSK_t
 

Data Structure Documentation

struct ALT_SDMMC_INTMSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_INTMSK.

Data Fields
uint32_t cd: 1 Interrupt Mask
uint32_t re: 1 Interrupt Mask
uint32_t cmd: 1 Command Done
uint32_t dto: 1 Data Transfer Over
uint32_t txdr: 1 Transmit FIFO Data Request
uint32_t rxdr: 1 Receive FIFO Data Request (
uint32_t rcrc: 1 Response CRC Error
uint32_t dcrc: 1 Data CRC Error
uint32_t rto: 1 Response Timeout
uint32_t drt: 1 Data Read Timeout
uint32_t hto: 1 Data Starvation Host Timeout
uint32_t frun: 1 FIFO Underrun Overrun Error
uint32_t hle: 1 Hardware Locked Write Error
uint32_t sbe: 1 Start-bit Error
uint32_t acd: 1 Auto Command Done
uint32_t ebe: 1 End-bit Error Read Write no CRC
uint32_t sdio_int_mask: 16 ALT_SDMMC_INTMSK_SDIO_INT_MSK

Macro Definitions

#define ALT_SDMMC_INTMSK_CD_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_CD

Card Detected Mask

#define ALT_SDMMC_INTMSK_CD_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_CD

Card Detect No Mask

#define ALT_SDMMC_INTMSK_CD_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CD register field.

#define ALT_SDMMC_INTMSK_CD_MSB   0

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CD register field.

#define ALT_SDMMC_INTMSK_CD_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_CD register field.

#define ALT_SDMMC_INTMSK_CD_SET_MSK   0x00000001

The mask used to set the ALT_SDMMC_INTMSK_CD register field value.

#define ALT_SDMMC_INTMSK_CD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SDMMC_INTMSK_CD register field value.

#define ALT_SDMMC_INTMSK_CD_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_CD register field.

#define ALT_SDMMC_INTMSK_CD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SDMMC_INTMSK_CD field value from a register.

#define ALT_SDMMC_INTMSK_CD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SDMMC_INTMSK_CD register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_RE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_RE

Response error Mask

#define ALT_SDMMC_INTMSK_RE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_RE

Response error No Mask

#define ALT_SDMMC_INTMSK_RE_LSB   1

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RE register field.

#define ALT_SDMMC_INTMSK_RE_MSB   1

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RE register field.

#define ALT_SDMMC_INTMSK_RE_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_RE register field.

#define ALT_SDMMC_INTMSK_RE_SET_MSK   0x00000002

The mask used to set the ALT_SDMMC_INTMSK_RE register field value.

#define ALT_SDMMC_INTMSK_RE_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SDMMC_INTMSK_RE register field value.

#define ALT_SDMMC_INTMSK_RE_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_RE register field.

#define ALT_SDMMC_INTMSK_RE_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SDMMC_INTMSK_RE field value from a register.

#define ALT_SDMMC_INTMSK_RE_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SDMMC_INTMSK_RE register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_CMD_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_CMD

Command Done Mask

#define ALT_SDMMC_INTMSK_CMD_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_CMD

Command Done No Mask

#define ALT_SDMMC_INTMSK_CMD_LSB   2

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_CMD register field.

#define ALT_SDMMC_INTMSK_CMD_MSB   2

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_CMD register field.

#define ALT_SDMMC_INTMSK_CMD_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_CMD register field.

#define ALT_SDMMC_INTMSK_CMD_SET_MSK   0x00000004

The mask used to set the ALT_SDMMC_INTMSK_CMD register field value.

#define ALT_SDMMC_INTMSK_CMD_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SDMMC_INTMSK_CMD register field value.

#define ALT_SDMMC_INTMSK_CMD_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_CMD register field.

#define ALT_SDMMC_INTMSK_CMD_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SDMMC_INTMSK_CMD field value from a register.

#define ALT_SDMMC_INTMSK_CMD_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SDMMC_INTMSK_CMD register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_DTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_DTO

Data transfer over Mask

#define ALT_SDMMC_INTMSK_DTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_DTO

Data transfer over No Mask

#define ALT_SDMMC_INTMSK_DTO_LSB   3

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DTO register field.

#define ALT_SDMMC_INTMSK_DTO_MSB   3

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DTO register field.

#define ALT_SDMMC_INTMSK_DTO_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_DTO register field.

#define ALT_SDMMC_INTMSK_DTO_SET_MSK   0x00000008

The mask used to set the ALT_SDMMC_INTMSK_DTO register field value.

#define ALT_SDMMC_INTMSK_DTO_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SDMMC_INTMSK_DTO register field value.

#define ALT_SDMMC_INTMSK_DTO_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_DTO register field.

#define ALT_SDMMC_INTMSK_DTO_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SDMMC_INTMSK_DTO field value from a register.

#define ALT_SDMMC_INTMSK_DTO_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SDMMC_INTMSK_DTO register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_TXDR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_TXDR

Transmit FIFO data request Mask

#define ALT_SDMMC_INTMSK_TXDR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_TXDR

Transmit FIFO data request No Mask

#define ALT_SDMMC_INTMSK_TXDR_LSB   4

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_TXDR register field.

#define ALT_SDMMC_INTMSK_TXDR_MSB   4

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_TXDR register field.

#define ALT_SDMMC_INTMSK_TXDR_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_TXDR register field.

#define ALT_SDMMC_INTMSK_TXDR_SET_MSK   0x00000010

The mask used to set the ALT_SDMMC_INTMSK_TXDR register field value.

#define ALT_SDMMC_INTMSK_TXDR_CLR_MSK   0xffffffef

The mask used to clear the ALT_SDMMC_INTMSK_TXDR register field value.

#define ALT_SDMMC_INTMSK_TXDR_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_TXDR register field.

#define ALT_SDMMC_INTMSK_TXDR_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SDMMC_INTMSK_TXDR field value from a register.

#define ALT_SDMMC_INTMSK_TXDR_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SDMMC_INTMSK_TXDR register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_RXDR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_RXDR

Receive FIFO data request Mask

#define ALT_SDMMC_INTMSK_RXDR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_RXDR

Receive FIFO data request No Mask

#define ALT_SDMMC_INTMSK_RXDR_LSB   5

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RXDR register field.

#define ALT_SDMMC_INTMSK_RXDR_MSB   5

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RXDR register field.

#define ALT_SDMMC_INTMSK_RXDR_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_RXDR register field.

#define ALT_SDMMC_INTMSK_RXDR_SET_MSK   0x00000020

The mask used to set the ALT_SDMMC_INTMSK_RXDR register field value.

#define ALT_SDMMC_INTMSK_RXDR_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SDMMC_INTMSK_RXDR register field value.

#define ALT_SDMMC_INTMSK_RXDR_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_RXDR register field.

#define ALT_SDMMC_INTMSK_RXDR_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SDMMC_INTMSK_RXDR field value from a register.

#define ALT_SDMMC_INTMSK_RXDR_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SDMMC_INTMSK_RXDR register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_RCRC_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_RCRC

Response CRC error Mask

#define ALT_SDMMC_INTMSK_RCRC_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_RCRC

Response CRC error No Mask

#define ALT_SDMMC_INTMSK_RCRC_LSB   6

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RCRC register field.

#define ALT_SDMMC_INTMSK_RCRC_MSB   6

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RCRC register field.

#define ALT_SDMMC_INTMSK_RCRC_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_RCRC register field.

#define ALT_SDMMC_INTMSK_RCRC_SET_MSK   0x00000040

The mask used to set the ALT_SDMMC_INTMSK_RCRC register field value.

#define ALT_SDMMC_INTMSK_RCRC_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SDMMC_INTMSK_RCRC register field value.

#define ALT_SDMMC_INTMSK_RCRC_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_RCRC register field.

#define ALT_SDMMC_INTMSK_RCRC_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SDMMC_INTMSK_RCRC field value from a register.

#define ALT_SDMMC_INTMSK_RCRC_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SDMMC_INTMSK_RCRC register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_DCRC_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_DCRC

Data CRC error Mask

#define ALT_SDMMC_INTMSK_DCRC_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_DCRC

Data CRC error No Mask

#define ALT_SDMMC_INTMSK_DCRC_LSB   7

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DCRC register field.

#define ALT_SDMMC_INTMSK_DCRC_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DCRC register field.

#define ALT_SDMMC_INTMSK_DCRC_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_DCRC register field.

#define ALT_SDMMC_INTMSK_DCRC_SET_MSK   0x00000080

The mask used to set the ALT_SDMMC_INTMSK_DCRC register field value.

#define ALT_SDMMC_INTMSK_DCRC_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SDMMC_INTMSK_DCRC register field value.

#define ALT_SDMMC_INTMSK_DCRC_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_DCRC register field.

#define ALT_SDMMC_INTMSK_DCRC_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SDMMC_INTMSK_DCRC field value from a register.

#define ALT_SDMMC_INTMSK_DCRC_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SDMMC_INTMSK_DCRC register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_RTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_RTO

Response timeout Mask

#define ALT_SDMMC_INTMSK_RTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_RTO

Response timeout No Mask

#define ALT_SDMMC_INTMSK_RTO_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_RTO register field.

#define ALT_SDMMC_INTMSK_RTO_MSB   8

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_RTO register field.

#define ALT_SDMMC_INTMSK_RTO_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_RTO register field.

#define ALT_SDMMC_INTMSK_RTO_SET_MSK   0x00000100

The mask used to set the ALT_SDMMC_INTMSK_RTO register field value.

#define ALT_SDMMC_INTMSK_RTO_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SDMMC_INTMSK_RTO register field value.

#define ALT_SDMMC_INTMSK_RTO_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_RTO register field.

#define ALT_SDMMC_INTMSK_RTO_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SDMMC_INTMSK_RTO field value from a register.

#define ALT_SDMMC_INTMSK_RTO_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SDMMC_INTMSK_RTO register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_DRT_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_DRT

Data read timeout Mask

#define ALT_SDMMC_INTMSK_DRT_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_DRT

Data read timeout No Mask

#define ALT_SDMMC_INTMSK_DRT_LSB   9

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_DRT register field.

#define ALT_SDMMC_INTMSK_DRT_MSB   9

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_DRT register field.

#define ALT_SDMMC_INTMSK_DRT_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_DRT register field.

#define ALT_SDMMC_INTMSK_DRT_SET_MSK   0x00000200

The mask used to set the ALT_SDMMC_INTMSK_DRT register field value.

#define ALT_SDMMC_INTMSK_DRT_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SDMMC_INTMSK_DRT register field value.

#define ALT_SDMMC_INTMSK_DRT_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_DRT register field.

#define ALT_SDMMC_INTMSK_DRT_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SDMMC_INTMSK_DRT field value from a register.

#define ALT_SDMMC_INTMSK_DRT_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SDMMC_INTMSK_DRT register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_HTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_HTO

Data starvation by host timeout Mask

#define ALT_SDMMC_INTMSK_HTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_HTO

Data starvation by host timeout No Mask

#define ALT_SDMMC_INTMSK_HTO_LSB   10

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HTO register field.

#define ALT_SDMMC_INTMSK_HTO_MSB   10

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HTO register field.

#define ALT_SDMMC_INTMSK_HTO_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_HTO register field.

#define ALT_SDMMC_INTMSK_HTO_SET_MSK   0x00000400

The mask used to set the ALT_SDMMC_INTMSK_HTO register field value.

#define ALT_SDMMC_INTMSK_HTO_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SDMMC_INTMSK_HTO register field value.

#define ALT_SDMMC_INTMSK_HTO_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_HTO register field.

#define ALT_SDMMC_INTMSK_HTO_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SDMMC_INTMSK_HTO field value from a register.

#define ALT_SDMMC_INTMSK_HTO_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SDMMC_INTMSK_HTO register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_FRUN_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_FRUN

FIFO underrun/overrun error Mask

#define ALT_SDMMC_INTMSK_FRUN_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_FRUN

FIFO underrun/overrun error No Mask

#define ALT_SDMMC_INTMSK_FRUN_LSB   11

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_FRUN register field.

#define ALT_SDMMC_INTMSK_FRUN_MSB   11

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_FRUN register field.

#define ALT_SDMMC_INTMSK_FRUN_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_FRUN register field.

#define ALT_SDMMC_INTMSK_FRUN_SET_MSK   0x00000800

The mask used to set the ALT_SDMMC_INTMSK_FRUN register field value.

#define ALT_SDMMC_INTMSK_FRUN_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SDMMC_INTMSK_FRUN register field value.

#define ALT_SDMMC_INTMSK_FRUN_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_FRUN register field.

#define ALT_SDMMC_INTMSK_FRUN_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SDMMC_INTMSK_FRUN field value from a register.

#define ALT_SDMMC_INTMSK_FRUN_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SDMMC_INTMSK_FRUN register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_HLE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_HLE

Hardware locked write error Mask

#define ALT_SDMMC_INTMSK_HLE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_HLE

Hardware locked write error No Mask

#define ALT_SDMMC_INTMSK_HLE_LSB   12

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_HLE register field.

#define ALT_SDMMC_INTMSK_HLE_MSB   12

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_HLE register field.

#define ALT_SDMMC_INTMSK_HLE_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_HLE register field.

#define ALT_SDMMC_INTMSK_HLE_SET_MSK   0x00001000

The mask used to set the ALT_SDMMC_INTMSK_HLE register field value.

#define ALT_SDMMC_INTMSK_HLE_CLR_MSK   0xffffefff

The mask used to clear the ALT_SDMMC_INTMSK_HLE register field value.

#define ALT_SDMMC_INTMSK_HLE_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_HLE register field.

#define ALT_SDMMC_INTMSK_HLE_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_SDMMC_INTMSK_HLE field value from a register.

#define ALT_SDMMC_INTMSK_HLE_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_SDMMC_INTMSK_HLE register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_SBE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_SBE

Start-bit error Mask

#define ALT_SDMMC_INTMSK_SBE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_SBE

Start-bit error No Mask

#define ALT_SDMMC_INTMSK_SBE_LSB   13

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SBE register field.

#define ALT_SDMMC_INTMSK_SBE_MSB   13

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SBE register field.

#define ALT_SDMMC_INTMSK_SBE_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_SBE register field.

#define ALT_SDMMC_INTMSK_SBE_SET_MSK   0x00002000

The mask used to set the ALT_SDMMC_INTMSK_SBE register field value.

#define ALT_SDMMC_INTMSK_SBE_CLR_MSK   0xffffdfff

The mask used to clear the ALT_SDMMC_INTMSK_SBE register field value.

#define ALT_SDMMC_INTMSK_SBE_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_SBE register field.

#define ALT_SDMMC_INTMSK_SBE_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_SDMMC_INTMSK_SBE field value from a register.

#define ALT_SDMMC_INTMSK_SBE_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_SDMMC_INTMSK_SBE register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_ACD_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_ACD

Auto command done Mask

#define ALT_SDMMC_INTMSK_ACD_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_ACD

Auto command done No Mask

#define ALT_SDMMC_INTMSK_ACD_LSB   14

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_ACD register field.

#define ALT_SDMMC_INTMSK_ACD_MSB   14

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_ACD register field.

#define ALT_SDMMC_INTMSK_ACD_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_ACD register field.

#define ALT_SDMMC_INTMSK_ACD_SET_MSK   0x00004000

The mask used to set the ALT_SDMMC_INTMSK_ACD register field value.

#define ALT_SDMMC_INTMSK_ACD_CLR_MSK   0xffffbfff

The mask used to clear the ALT_SDMMC_INTMSK_ACD register field value.

#define ALT_SDMMC_INTMSK_ACD_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_ACD register field.

#define ALT_SDMMC_INTMSK_ACD_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_SDMMC_INTMSK_ACD field value from a register.

#define ALT_SDMMC_INTMSK_ACD_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_SDMMC_INTMSK_ACD register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_EBE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_EBE

End-bit error Mask

#define ALT_SDMMC_INTMSK_EBE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_EBE

End-bit error No Mask

#define ALT_SDMMC_INTMSK_EBE_LSB   15

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_EBE register field.

#define ALT_SDMMC_INTMSK_EBE_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_EBE register field.

#define ALT_SDMMC_INTMSK_EBE_WIDTH   1

The width in bits of the ALT_SDMMC_INTMSK_EBE register field.

#define ALT_SDMMC_INTMSK_EBE_SET_MSK   0x00008000

The mask used to set the ALT_SDMMC_INTMSK_EBE register field value.

#define ALT_SDMMC_INTMSK_EBE_CLR_MSK   0xffff7fff

The mask used to clear the ALT_SDMMC_INTMSK_EBE register field value.

#define ALT_SDMMC_INTMSK_EBE_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_EBE register field.

#define ALT_SDMMC_INTMSK_EBE_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_SDMMC_INTMSK_EBE field value from a register.

#define ALT_SDMMC_INTMSK_EBE_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_SDMMC_INTMSK_EBE register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD   0x0

Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK

SDIO Mask Interrupt Disabled

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END   0x1

Enumerated value for register field ALT_SDMMC_INTMSK_SDIO_INT_MSK

SDIO Interrupt Enabled

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB   31

The Most Significant Bit (MSB) position of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH   16

The width in bits of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK   0xffff0000

The mask used to set the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK   0x0000ffff

The mask used to clear the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET   0x0

The reset value of the ALT_SDMMC_INTMSK_SDIO_INT_MSK register field.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_SDMMC_INTMSK_SDIO_INT_MSK field value from a register.

#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_SDMMC_INTMSK_SDIO_INT_MSK register field value suitable for setting the register.

#define ALT_SDMMC_INTMSK_RESET   0x00000000

The reset value of the ALT_SDMMC_INTMSK register.

#define ALT_SDMMC_INTMSK_OFST   0x24

The byte offset of the ALT_SDMMC_INTMSK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_INTMSK.