Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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MMU Management Macros - First Level Translation Table

Description

The macro definitions in this section support access to the short-descriptor first-level table entries and their constituent fields.

These macros may be used to create descriptor entry values that are passed to a first level translation table contruction function such as alt_mmu_ttb1_desc_set().

Each short-descriptor has a set of macro definitions of the following form:

First Level Translation Table Page Table Entry [NS]

The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map.

#define ALT_MMU_TTB1_PAGE_TBL_NS_MASK   0x00000008
 
#define ALT_MMU_TTB1_PAGE_TBL_NS_GET(desc)   (((desc) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) >> 3)
 
#define ALT_MMU_TTB1_PAGE_TBL_NS_SET(val)   (((val) << 3) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK)
 

First Level Translation Table Page Table Entry [DOMAIN]

Domain field. Page table descriptor applies to all entries in the corresponding second-level translation table.

#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK   0x000001e0
 
#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_GET(desc)   (((desc) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) >> 5)
 
#define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(val)   (((val) << 5) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK)
 

First Level Translation Table Page Table Entry Page Table Base Address

#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK   0xfffffc00
 
#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_GET(desc)   (((desc) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) >> 10)
 
#define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(val)   (((val) << 10) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK)
 

First Level Translation Table Section Entry [B]

The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute.

#define ALT_MMU_TTB1_SECTION_B_MASK   0x00000004
 
#define ALT_MMU_TTB1_SECTION_B_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_B_MASK) >> 2)
 
#define ALT_MMU_TTB1_SECTION_B_SET(val)   (((val) << 2) & ALT_MMU_TTB1_SECTION_B_MASK)
 

First Level Translation Table Section Entry [C]

The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute.

#define ALT_MMU_TTB1_SECTION_C_MASK   0x00000008
 
#define ALT_MMU_TTB1_SECTION_C_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_C_MASK) >> 3)
 
#define ALT_MMU_TTB1_SECTION_C_SET(val)   (((val) << 3) & ALT_MMU_TTB1_SECTION_C_MASK)
 

First Level Translation Table Section Entry [XN]

The Execute-Never bit. Determines whether the processor can execute software from the addressed region.

#define ALT_MMU_TTB1_SECTION_XN_MASK   0x00000010
 
#define ALT_MMU_TTB1_SECTION_XN_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_XN_MASK) >> 4)
 
#define ALT_MMU_TTB1_SECTION_XN_SET(val)   (((val) << 4) & ALT_MMU_TTB1_SECTION_XN_MASK)
 

First Level Translation Table Section Entry [DOMAIN]

Domain field.

#define ALT_MMU_TTB1_SECTION_DOMAIN_MASK   0x000001e0
 
#define ALT_MMU_TTB1_SECTION_DOMAIN_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) >> 5)
 
#define ALT_MMU_TTB1_SECTION_DOMAIN_SET(val)   (((val) << 5) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK)
 

First Level Translation Table Section Entry [AP]

Access Permissions bits.

#define ALT_MMU_TTB1_SECTION_AP_MASK   0x00008c00
 
#define ALT_MMU_TTB1_SECTION_AP_GET(desc)   ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
 
#define ALT_MMU_TTB1_SECTION_AP_SET(val)   ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
 

First Level Translation Table Section Entry [TEX]

The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute.

#define ALT_MMU_TTB1_SECTION_TEX_MASK   0x00007000
 
#define ALT_MMU_TTB1_SECTION_TEX_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_TEX_MASK) >> 12)
 
#define ALT_MMU_TTB1_SECTION_TEX_SET(val)   (((val) << 12) & ALT_MMU_TTB1_SECTION_TEX_MASK)
 

First Level Translation Table Section Entry [S]

The Shareable bit. Determines whether the addressed region is shareable memory.

#define ALT_MMU_TTB1_SECTION_S_MASK   0x00010000
 
#define ALT_MMU_TTB1_SECTION_S_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_S_MASK) >> 16)
 
#define ALT_MMU_TTB1_SECTION_S_SET(val)   (((val) << 16) & ALT_MMU_TTB1_SECTION_S_MASK)
 

First Level Translation Table Section Entry [nG]

The not global bit. Determines how the translation is marked in the TLB.

#define ALT_MMU_TTB1_SECTION_NG_MASK   0x00020000
 
#define ALT_MMU_TTB1_SECTION_NG_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_NG_MASK) >> 17)
 
#define ALT_MMU_TTB1_SECTION_NG_SET(val)   (((val) << 17) & ALT_MMU_TTB1_SECTION_NG_MASK)
 

First Level Translation Table Section Entry [NS]

The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map.

#define ALT_MMU_TTB1_SECTION_NS_MASK   0x00080000
 
#define ALT_MMU_TTB1_SECTION_NS_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_NS_MASK) >> 19)
 
#define ALT_MMU_TTB1_SECTION_NS_SET(val)   (((val) << 19) & ALT_MMU_TTB1_SECTION_NS_MASK)
 

First Level Translation Table Section Entry Section Base Address

#define ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK   0xfff00000
 
#define ALT_MMU_TTB1_SECTION_BASE_ADDR_GET(desc)   (((desc) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) >> 20)
 
#define ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(val)   (((val) << 20) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK)
 

First Level Translation Table Supersection Entry [B]

The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute.

#define ALT_MMU_TTB1_SUPERSECTION_B_MASK   0x00000004
 
#define ALT_MMU_TTB1_SUPERSECTION_B_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) >> 2)
 
#define ALT_MMU_TTB1_SUPERSECTION_B_SET(val)   (((val) << 2) & ALT_MMU_TTB1_SUPERSECTION_B_MASK)
 

First Level Translation Table Supersection Entry [C]

The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute.

#define ALT_MMU_TTB1_SUPERSECTION_C_MASK   0x00000008
 
#define ALT_MMU_TTB1_SUPERSECTION_C_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) >> 3)
 
#define ALT_MMU_TTB1_SUPERSECTION_C_SET(val)   (((val) << 3) & ALT_MMU_TTB1_SUPERSECTION_C_MASK)
 

First Level Translation Table Supersection Entry [XN]

The Execute-Never bit. Determines whether the processor can execute software from the addressed region.

#define ALT_MMU_TTB1_SUPERSECTION_XN_MASK   0x00000010
 
#define ALT_MMU_TTB1_SUPERSECTION_XN_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) >> 4)
 
#define ALT_MMU_TTB1_SUPERSECTION_XN_SET(val)   (((val) << 4) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK)
 

First Level Translation Table Supersection Entry [DOMAIN]

Domain field.

#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK   0x000001e0
 
#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) >> 5)
 
#define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(val)   (((val) << 5) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK)
 

First Level Translation Table Supersection Entry [AP]

Access Permissions bits.

#define ALT_MMU_TTB1_SUPERSECTION_AP_MASK   0x00008c00
 
#define ALT_MMU_TTB1_SUPERSECTION_AP_GET(desc)   ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
 
#define ALT_MMU_TTB1_SUPERSECTION_AP_SET(val)   ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
 

First Level Translation Table Supersection Entry [TEX]

The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute.

#define ALT_MMU_TTB1_SUPERSECTION_TEX_MASK   0x00007000
 
#define ALT_MMU_TTB1_SUPERSECTION_TEX_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) >> 12)
 
#define ALT_MMU_TTB1_SUPERSECTION_TEX_SET(val)   (((val) << 12) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK)
 

First Level Translation Table Supersection Entry [S]

The Shareable bit. Determines whether the addressed region is shareable memory.

#define ALT_MMU_TTB1_SUPERSECTION_S_MASK   0x00010000
 
#define ALT_MMU_TTB1_SUPERSECTION_S_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) >> 16)
 
#define ALT_MMU_TTB1_SUPERSECTION_S_SET(val)   (((val) << 16) & ALT_MMU_TTB1_SUPERSECTION_S_MASK)
 

First Level Translation Table Supersection Entry [nG]

The not global bit. Determines how the translation is marked in the TLB.

#define ALT_MMU_TTB1_SUPERSECTION_NG_MASK   0x00020000
 
#define ALT_MMU_TTB1_SUPERSECTION_NG_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) >> 17)
 
#define ALT_MMU_TTB1_SUPERSECTION_NG_SET(val)   (((val) << 17) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK)
 

First Level Translation Table Supersection Entry [NS]

The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map.

#define ALT_MMU_TTB1_SUPERSECTION_NS_MASK   0x00080000
 
#define ALT_MMU_TTB1_SUPERSECTION_NS_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) >> 19)
 
#define ALT_MMU_TTB1_SUPERSECTION_NS_SET(val)   (((val) << 19) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK)
 

First Level Translation Table Supersection Entry Supersection Base Address

#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK   0xff000000
 
#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_GET(desc)   (((desc) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) >> 24)
 
#define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(val)   (((val) << 24) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK)