Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : counter1mask

Description

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK

Field : counter_one_mask

Performance monitoring register. This register is used to mask off the internal signals selected by the debug select byte to either examine a bit (and expect it to be a one or a zero) or to ignore the bit.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_LSB   0
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_MSB   31
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_WIDTH   32
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET_MSK   0xffffffff
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_CLR_MSK   0x00000000
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CNTR1MSK_s
 

Macros

#define ALT_IO48_HMC_MMR_CNTR1MSK_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CNTR1MSK_OFST   0x104
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CNTR1MSK_s 
ALT_IO48_HMC_MMR_CNTR1MSK_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CNTR1MSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CNTR1MSK.

Data Fields
uint32_t counter_one_mask: 32 ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK

Macro Definitions

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_WIDTH   32

The width in bits of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET_MSK   0xffffffff

The mask used to set the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_CLR_MSK   0x00000000

The mask used to clear the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK field value from a register.

#define ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_IO48_HMC_MMR_CNTR1MSK_CNTR_ONE_MSK register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CNTR1MSK_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CNTR1MSK register.

#define ALT_IO48_HMC_MMR_CNTR1MSK_OFST   0x104

The byte offset of the ALT_IO48_HMC_MMR_CNTR1MSK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CNTR1MSK.