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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Regsiter 67 (MMC Receive Interrupt Mask Register)
The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when the receive statistic counters reach half of their maximum value, or maximum value. This register is 32-bits wide.
Register Layout
Field : rxgbfrmim | |
MMC Receive Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxframecount_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB 0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB 0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET(value) (((value) << 0) & 0x00000001) |
Field : rxgboctim | |
MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET(value) (((value) << 1) & 0x00000002) |
Field : rxgoctim | |
MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB 2 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB 2 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK 0x00000004 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK 0xfffffffb |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET(value) (((value) << 2) & 0x00000004) |
Field : rxbcgfim | |
MMC Receive Broadcast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB 3 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB 3 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET(value) (((value) << 3) & 0x00000008) |
Field : rxmcgfim | |
MMC Receive Multicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB 4 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB 4 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK 0x00000010 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK 0xffffffef |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET(value) (((value) << 4) & 0x00000010) |
Field : rxcrcerfim | |
MMC Receive CRC Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB 5 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB 5 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK 0x00000020 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK 0xffffffdf |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET(value) (((value) << 5) & 0x00000020) |
Field : rxalgnerfim | |
MMC Receive Alignment Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB 6 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB 6 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK 0x00000040 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK 0xffffffbf |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET(value) (((value) << 6) & 0x00000040) |
Field : rxruntfim | |
MMC Receive Runt Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB 7 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB 7 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK 0x00000080 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK 0xffffff7f |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET(value) (((value) << 7) & 0x00000080) |
Field : rxjaberfim | |
MMC Receive Jabber Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB 8 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB 8 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK 0x00000100 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK 0xfffffeff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET(value) (((value) << 8) & 0x00000100) |
Field : rxusizegfim | |
MMC Receive Undersize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB 9 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB 9 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK 0x00000200 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK 0xfffffdff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET(value) (((value) << 9) & 0x00000200) |
Field : rxosizegfim | |
MMC Receive Oversize Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB 10 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB 10 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK 0x00000400 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfffffbff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET(value) (((value) << 10) & 0x00000400) |
Field : rx64octgbfim | |
MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB 11 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB 11 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000800 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK 0xfffff7ff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET(value) (((value) << 11) & 0x00000800) |
Field : rx65t127octgbfim | |
MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB 12 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB 12 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00001000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffefff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET(value) (((value) << 12) & 0x00001000) |
Field : rx128t255octgbfim | |
MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB 13 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB 13 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00002000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffdfff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET(value) (((value) << 13) & 0x00002000) |
Field : rx256t511octgbfim | |
MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB 14 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB 14 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00004000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffbfff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET(value) (((value) << 14) & 0x00004000) |
Field : rx512t1023octgbfim | |
MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB 15 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB 15 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00008000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xffff7fff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET(value) (((value) << 15) & 0x00008000) |
Field : rx1024tmaxoctgbfim | |
MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB 16 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB 16 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET(value) (((value) << 16) & 0x00010000) |
Field : rxucgfim | |
MMC Receive Unicast Good Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB 17 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB 17 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK 0x00020000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK 0xfffdffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET(value) (((value) << 17) & 0x00020000) |
Field : rxlenerfim | |
MMC Receive Length Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB 18 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB 18 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK 0x00040000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK 0xfffbffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET(value) (((value) << 18) & 0x00040000) |
Field : rxorangefim | |
MMC Receive Out Of Range Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB 19 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB 19 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK 0x00080000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK 0xfff7ffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET(value) (((value) << 19) & 0x00080000) |
Field : rxpausfim | |
MMC Receive Pause Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxpauseframes counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB 20 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB 20 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK 0x00100000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK 0xffefffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET(value) (((value) << 20) & 0x00100000) |
Field : rxfovfim | |
MMC Receive FIFO Overflow Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB 21 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB 21 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK 0x00200000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK 0xffdfffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET(value) (((value) << 21) & 0x00200000) |
Field : rxvlangbfim | |
MMC Receive VLAN Good Bad Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanframes_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB 22 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB 22 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK 0x00400000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK 0xffbfffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET(value) (((value) << 22) & 0x00400000) |
Field : rxwdogfim | |
MMC Receive Watchdog Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB 23 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB 23 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK 0x00800000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK 0xff7fffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET(value) (((value) << 23) & 0x00800000) |
Field : rxrcverrfim | |
MMC Receive Error Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror error counter reaches half the maximum value, and also when it reaches the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB 24 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB 24 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK 0x01000000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK 0xfeffffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET(value) (((value) << 24) & 0x01000000) |
Field : rxctrlfim | |
MMC Receive Control Frame Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlframes counter reaches half the maximum value, and also when it reaches the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR | 0x0 | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR 0x1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB 25 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB 25 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK 0x02000000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK 0xfdffffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET(value) (((value) << 25) & 0x02000000) |
Field : reserved_31_26 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_LSB 26 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_MSB 31 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_WIDTH 6 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET_MSK 0xfc000000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_CLR_MSK 0x03ffffff |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26) |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000) |
Data Structures | |
struct | ALT_EMAC_GMAC_MMC_RX_INT_MSK_s |
Macros | |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST 0x10c |
#define | ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s | ALT_EMAC_GMAC_MMC_RX_INT_MSK_t |
struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBFRMIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GBOCTIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_GOCTIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_BCGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_MCGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CRCERFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET_MSK 0x00000040 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ALGNERFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RUNTFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_JABERFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET_MSK 0x00000200 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_USIZEGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET_MSK 0x00000400 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_OSIZEGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET_MSK 0x00000800 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_64OCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET_MSK 0x00001000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_CLR_MSK 0xffffefff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET_MSK 0x00004000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET_MSK 0x00008000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET_MSK 0x00020000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_UCGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_LENERFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_ORANGEFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET_MSK 0x00100000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_CLR_MSK 0xffefffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_PAUSFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET_MSK 0x00200000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_FOVFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET_MSK 0x00400000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_VLANGBFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET_MSK 0x00800000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_WDOGFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RCVERRFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_NOMSKINTR 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_E_MSKINTR 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_CTLFIM register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_WIDTH 6 |
The width in bits of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET_MSK 0xfc000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_CLR_MSK 0x03ffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_GET | ( | value | ) | (((value) & 0xfc000000) >> 26) |
Extracts the ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 field value from a register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26_SET | ( | value | ) | (((value) << 26) & 0xfc000000) |
Produces a ALT_EMAC_GMAC_MMC_RX_INT_MSK_RSVD_31_26 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST 0x10c |
The byte offset of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register from the beginning of the component.
#define ALT_EMAC_GMAC_MMC_RX_INT_MSK_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_RX_INT_MSK_OFST)) |
The address of the ALT_EMAC_GMAC_MMC_RX_INT_MSK register.
typedef struct ALT_EMAC_GMAC_MMC_RX_INT_MSK_s ALT_EMAC_GMAC_MMC_RX_INT_MSK_t |
The typedef declaration for register ALT_EMAC_GMAC_MMC_RX_INT_MSK.