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alt_nand.h
1
/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NAND_H__
36
#define __ALT_SOCAL_NAND_H__
37
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#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
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extern
"C"
42
{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
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81
#define ALT_NAND_CFG_DEVICE_RST_BANK0_LSB 0
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_MSB 0
84
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_WIDTH 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET_MSK 0x00000001
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_CLR_MSK 0xfffffffe
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_RESET 0x0
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NAND_CFG_DEVICE_RST_BANK0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_LSB 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_MSB 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_WIDTH 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET_MSK 0x00000002
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_CLR_MSK 0xfffffffd
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_RESET 0x0
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NAND_CFG_DEVICE_RST_BANK1_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_LSB 2
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_MSB 2
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_WIDTH 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET_MSK 0x00000004
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_CLR_MSK 0xfffffffb
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_RESET 0x0
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NAND_CFG_DEVICE_RST_BANK2_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_LSB 3
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_MSB 3
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_WIDTH 1
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET_MSK 0x00000008
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_CLR_MSK 0xfffffff7
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_RESET 0x0
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NAND_CFG_DEVICE_RST_BANK3_SET(value) (((value) << 3) & 0x00000008)
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#ifndef __ASSEMBLY__
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struct
ALT_NAND_CFG_DEVICE_RST_s
190
{
191
uint32_t
bank0
: 1;
192
uint32_t
bank1
: 1;
193
uint32_t
bank2
: 1;
194
uint32_t
bank3
: 1;
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uint32_t : 28;
196
};
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199
typedef
volatile
struct
ALT_NAND_CFG_DEVICE_RST_s
ALT_NAND_CFG_DEVICE_RST_t
;
200
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_DEVICE_RST_RESET 0x00000000
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#define ALT_NAND_CFG_DEVICE_RST_OFST 0x0
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_LSB 0
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_MSB 0
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_WIDTH 1
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET_MSK 0x00000001
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_CLR_MSK 0xfffffffe
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_RESET 0x0
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NAND_CFG_TFR_SPARE_REG_FLAG_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
252
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struct
ALT_NAND_CFG_TFR_SPARE_REG_s
263
{
264
uint32_t
flag
: 1;
265
uint32_t : 31;
266
};
267
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typedef
volatile
struct
ALT_NAND_CFG_TFR_SPARE_REG_s
ALT_NAND_CFG_TFR_SPARE_REG_t
;
270
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_TFR_SPARE_REG_RESET 0x00000000
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#define ALT_NAND_CFG_TFR_SPARE_REG_OFST 0x10
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_LSB 0
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_MSB 15
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_WIDTH 16
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_RESET 0x1f4
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_NAND_CFG_LD_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NAND_CFG_LD_WAIT_CNT_s
343
{
344
uint32_t
value
: 16;
345
uint32_t : 16;
346
};
347
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typedef
volatile
struct
ALT_NAND_CFG_LD_WAIT_CNT_s
ALT_NAND_CFG_LD_WAIT_CNT_t
;
350
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_LD_WAIT_CNT_RESET 0x000001f4
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#define ALT_NAND_CFG_LD_WAIT_CNT_OFST 0x20
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_LSB 0
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_MSB 15
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_WIDTH 16
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_RESET 0x1f40
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
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#ifndef __ASSEMBLY__
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426
struct
ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
427
{
428
uint32_t
value
: 16;
429
uint32_t : 16;
430
};
431
433
typedef
volatile
struct
ALT_NAND_CFG_PROGRAM_WAIT_CNT_s
ALT_NAND_CFG_PROGRAM_WAIT_CNT_t
;
434
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_RESET 0x00001f40
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#define ALT_NAND_CFG_PROGRAM_WAIT_CNT_OFST 0x30
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_LSB 0
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_MSB 15
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_WIDTH 16
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET_MSK 0x0000ffff
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_CLR_MSK 0xffff0000
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_RESET 0x1f40
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NAND_CFG_ERASE_WAIT_CNT_s
511
{
512
uint32_t
value
: 16;
513
uint32_t : 16;
514
};
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typedef
volatile
struct
ALT_NAND_CFG_ERASE_WAIT_CNT_s
ALT_NAND_CFG_ERASE_WAIT_CNT_t
;
518
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_RESET 0x00001f40
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#define ALT_NAND_CFG_ERASE_WAIT_CNT_OFST 0x40
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_LSB 0
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_MSB 15
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_WIDTH 16
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET_MSK 0x0000ffff
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_CLR_MSK 0xffff0000
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_RESET 0x1f4
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_NAND_CFG_INT_MON_CYCCNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NAND_CFG_INT_MON_CYCCNT_s
581
{
582
uint32_t
value
: 16;
583
uint32_t : 16;
584
};
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typedef
volatile
struct
ALT_NAND_CFG_INT_MON_CYCCNT_s
ALT_NAND_CFG_INT_MON_CYCCNT_t
;
588
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_INT_MON_CYCCNT_RESET 0x000001f4
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#define ALT_NAND_CFG_INT_MON_CYCCNT_OFST 0x50
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_LSB 0
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_MSB 0
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_WIDTH 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_SET_MSK 0x00000001
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_CLR_MSK 0xfffffffe
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_RESET 0x1
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NAND_CFG_RB_PIN_END_BANK0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_LSB 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_MSB 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_WIDTH 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_SET_MSK 0x00000002
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_CLR_MSK 0xfffffffd
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_RESET 0x0
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NAND_CFG_RB_PIN_END_BANK1_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_LSB 2
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_MSB 2
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_WIDTH 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_SET_MSK 0x00000004
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_CLR_MSK 0xfffffffb
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_RESET 0x0
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NAND_CFG_RB_PIN_END_BANK2_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_LSB 3
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_MSB 3
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_WIDTH 1
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_SET_MSK 0x00000008
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_CLR_MSK 0xfffffff7
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_RESET 0x0
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NAND_CFG_RB_PIN_END_BANK3_SET(value) (((value) << 3) & 0x00000008)
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#ifndef __ASSEMBLY__
728
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struct
ALT_NAND_CFG_RB_PIN_END_s
739
{
740
uint32_t
bank0
: 1;
741
uint32_t
bank1
: 1;
742
uint32_t
bank2
: 1;
743
uint32_t
bank3
: 1;
744
uint32_t : 28;
745
};
746
748
typedef
volatile
struct
ALT_NAND_CFG_RB_PIN_END_s
ALT_NAND_CFG_RB_PIN_END_t
;
749
#endif
/* __ASSEMBLY__ */
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#define ALT_NAND_CFG_RB_PIN_END_RESET 0x00000001
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#define ALT_NAND_CFG_RB_PIN_END_OFST 0x60
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_LSB 0
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_MSB 0
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_WIDTH 1
787
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET_MSK 0x00000001
789
790
#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_CLR_MSK 0xfffffffe
791
792
#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_RESET 0x0
793
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NAND_CFG_MULTIPLANE_OP_FLAG_SET(value) (((value) << 0) & 0x00000001)
797
798
#ifndef __ASSEMBLY__
799
809
struct
ALT_NAND_CFG_MULTIPLANE_OP_s
810
{
811
uint32_t
flag
: 1;
812
uint32_t : 31;
813
};
814
816
typedef
volatile
struct
ALT_NAND_CFG_MULTIPLANE_OP_s
ALT_NAND_CFG_MULTIPLANE_OP_t
;
817
#endif
/* __ASSEMBLY__ */
818
820
#define ALT_NAND_CFG_MULTIPLANE_OP_RESET 0x00000000
821
822
#define ALT_NAND_CFG_MULTIPLANE_OP_OFST 0x70
823
858
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_LSB 0
859
860
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_MSB 0
861
862
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_WIDTH 1
863
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#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET_MSK 0x00000001
865
866
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_CLR_MSK 0xfffffffe
867
868
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_RESET 0x0
869
870
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
871
872
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
873
874
#ifndef __ASSEMBLY__
875
885
struct
ALT_NAND_CFG_MULTIPLANE_RD_EN_s
886
{
887
uint32_t
flag
: 1;
888
uint32_t : 31;
889
};
890
892
typedef
volatile
struct
ALT_NAND_CFG_MULTIPLANE_RD_EN_s
ALT_NAND_CFG_MULTIPLANE_RD_EN_t
;
893
#endif
/* __ASSEMBLY__ */
894
896
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_RESET 0x00000000
897
898
#define ALT_NAND_CFG_MULTIPLANE_RD_EN_OFST 0x80
899
922
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_LSB 0
923
924
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_MSB 0
925
926
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_WIDTH 1
927
928
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET_MSK 0x00000001
929
930
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_CLR_MSK 0xfffffffe
931
932
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_RESET 0x0
933
934
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_GET(value) (((value) & 0x00000001) >> 0)
935
936
#define ALT_NAND_CFG_COPYBACK_DIS_FLAG_SET(value) (((value) << 0) & 0x00000001)
937
938
#ifndef __ASSEMBLY__
939
949
struct
ALT_NAND_CFG_COPYBACK_DIS_s
950
{
951
uint32_t
flag
: 1;
952
uint32_t : 31;
953
};
954
956
typedef
volatile
struct
ALT_NAND_CFG_COPYBACK_DIS_s
ALT_NAND_CFG_COPYBACK_DIS_t
;
957
#endif
/* __ASSEMBLY__ */
958
960
#define ALT_NAND_CFG_COPYBACK_DIS_RESET 0x00000000
961
962
#define ALT_NAND_CFG_COPYBACK_DIS_OFST 0x90
963
986
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_LSB 0
987
988
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_MSB 0
989
990
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_WIDTH 1
991
992
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET_MSK 0x00000001
993
994
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_CLR_MSK 0xfffffffe
995
996
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_RESET 0x0
997
998
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
999
1000
#define ALT_NAND_CFG_CACHE_WR_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1001
1002
#ifndef __ASSEMBLY__
1003
1013
struct
ALT_NAND_CFG_CACHE_WR_EN_s
1014
{
1015
uint32_t
flag
: 1;
1016
uint32_t : 31;
1017
};
1018
1020
typedef
volatile
struct
ALT_NAND_CFG_CACHE_WR_EN_s
ALT_NAND_CFG_CACHE_WR_EN_t
;
1021
#endif
/* __ASSEMBLY__ */
1022
1024
#define ALT_NAND_CFG_CACHE_WR_EN_RESET 0x00000000
1025
1026
#define ALT_NAND_CFG_CACHE_WR_EN_OFST 0xa0
1027
1050
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_LSB 0
1051
1052
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_MSB 0
1053
1054
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_WIDTH 1
1055
1056
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET_MSK 0x00000001
1057
1058
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_CLR_MSK 0xfffffffe
1059
1060
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_RESET 0x0
1061
1062
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1063
1064
#define ALT_NAND_CFG_CACHE_RD_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1065
1066
#ifndef __ASSEMBLY__
1067
1077
struct
ALT_NAND_CFG_CACHE_RD_EN_s
1078
{
1079
uint32_t
flag
: 1;
1080
uint32_t : 31;
1081
};
1082
1084
typedef
volatile
struct
ALT_NAND_CFG_CACHE_RD_EN_s
ALT_NAND_CFG_CACHE_RD_EN_t
;
1085
#endif
/* __ASSEMBLY__ */
1086
1088
#define ALT_NAND_CFG_CACHE_RD_EN_RESET 0x00000000
1089
1090
#define ALT_NAND_CFG_CACHE_RD_EN_OFST 0xb0
1091
1116
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_LSB 0
1117
1118
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_MSB 0
1119
1120
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_WIDTH 1
1121
1122
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET_MSK 0x00000001
1123
1124
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_CLR_MSK 0xfffffffe
1125
1126
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_RESET 0x1
1127
1128
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_GET(value) (((value) & 0x00000001) >> 0)
1129
1130
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_EN_SET(value) (((value) << 0) & 0x00000001)
1131
1155
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_LSB 4
1156
1157
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_MSB 15
1158
1159
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_WIDTH 12
1160
1161
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET_MSK 0x0000fff0
1162
1163
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_CLR_MSK 0xffff000f
1164
1165
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_RESET 0x0
1166
1167
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_GET(value) (((value) & 0x0000fff0) >> 4)
1168
1169
#define ALT_NAND_CFG_PREFETCH_MOD_PREFETCH_BURST_LEN_SET(value) (((value) << 4) & 0x0000fff0)
1170
1171
#ifndef __ASSEMBLY__
1172
1182
struct
ALT_NAND_CFG_PREFETCH_MOD_s
1183
{
1184
uint32_t
prefetch_en
: 1;
1185
uint32_t : 3;
1186
uint32_t
prefetch_burst_length
: 12;
1187
uint32_t : 16;
1188
};
1189
1191
typedef
volatile
struct
ALT_NAND_CFG_PREFETCH_MOD_s
ALT_NAND_CFG_PREFETCH_MOD_t
;
1192
#endif
/* __ASSEMBLY__ */
1193
1195
#define ALT_NAND_CFG_PREFETCH_MOD_RESET 0x00000001
1196
1197
#define ALT_NAND_CFG_PREFETCH_MOD_OFST 0xc0
1198
1225
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_LSB 0
1226
1227
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_MSB 0
1228
1229
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_WIDTH 1
1230
1231
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET_MSK 0x00000001
1232
1233
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_CLR_MSK 0xfffffffe
1234
1235
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_RESET 0x0
1236
1237
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1238
1239
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_FLAG_SET(value) (((value) << 0) & 0x00000001)
1240
1241
#ifndef __ASSEMBLY__
1242
1252
struct
ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
1253
{
1254
uint32_t
flag
: 1;
1255
uint32_t : 31;
1256
};
1257
1259
typedef
volatile
struct
ALT_NAND_CFG_CHIP_EN_DONT_CARE_s
ALT_NAND_CFG_CHIP_EN_DONT_CARE_t
;
1260
#endif
/* __ASSEMBLY__ */
1261
1263
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_RESET 0x00000000
1264
1265
#define ALT_NAND_CFG_CHIP_EN_DONT_CARE_OFST 0xd0
1266
1299
#define ALT_NAND_CFG_ECC_EN_FLAG_LSB 0
1300
1301
#define ALT_NAND_CFG_ECC_EN_FLAG_MSB 0
1302
1303
#define ALT_NAND_CFG_ECC_EN_FLAG_WIDTH 1
1304
1305
#define ALT_NAND_CFG_ECC_EN_FLAG_SET_MSK 0x00000001
1306
1307
#define ALT_NAND_CFG_ECC_EN_FLAG_CLR_MSK 0xfffffffe
1308
1309
#define ALT_NAND_CFG_ECC_EN_FLAG_RESET 0x1
1310
1311
#define ALT_NAND_CFG_ECC_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1312
1313
#define ALT_NAND_CFG_ECC_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1314
1315
#ifndef __ASSEMBLY__
1316
1326
struct
ALT_NAND_CFG_ECC_EN_s
1327
{
1328
uint32_t
flag
: 1;
1329
uint32_t : 31;
1330
};
1331
1333
typedef
volatile
struct
ALT_NAND_CFG_ECC_EN_s
ALT_NAND_CFG_ECC_EN_t
;
1334
#endif
/* __ASSEMBLY__ */
1335
1337
#define ALT_NAND_CFG_ECC_EN_RESET 0x00000001
1338
1339
#define ALT_NAND_CFG_ECC_EN_OFST 0xe0
1340
1367
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_LSB 0
1368
1369
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_MSB 0
1370
1371
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_WIDTH 1
1372
1373
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET_MSK 0x00000001
1374
1375
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_CLR_MSK 0xfffffffe
1376
1377
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_RESET 0x0
1378
1379
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
1380
1381
#define ALT_NAND_CFG_GLOB_INT_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
1382
1394
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_LSB 4
1395
1396
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_MSB 4
1397
1398
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_WIDTH 1
1399
1400
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET_MSK 0x00000010
1401
1402
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_CLR_MSK 0xffffffef
1403
1404
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_RESET 0x0
1405
1406
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_GET(value) (((value) & 0x00000010) >> 4)
1407
1408
#define ALT_NAND_CFG_GLOB_INT_EN_TMO_DIS_SET(value) (((value) << 4) & 0x00000010)
1409
1421
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_LSB 8
1422
1423
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_MSB 8
1424
1425
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_WIDTH 1
1426
1427
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET_MSK 0x00000100
1428
1429
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_CLR_MSK 0xfffffeff
1430
1431
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_RESET 0x0
1432
1433
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_GET(value) (((value) & 0x00000100) >> 8)
1434
1435
#define ALT_NAND_CFG_GLOB_INT_EN_ERROR_RPT_DIS_SET(value) (((value) << 8) & 0x00000100)
1436
1437
#ifndef __ASSEMBLY__
1438
1448
struct
ALT_NAND_CFG_GLOB_INT_EN_s
1449
{
1450
uint32_t
flag
: 1;
1451
uint32_t : 3;
1452
uint32_t
timeout_disable
: 1;
1453
uint32_t : 3;
1454
uint32_t
error_rpt_disable
: 1;
1455
uint32_t : 23;
1456
};
1457
1459
typedef
volatile
struct
ALT_NAND_CFG_GLOB_INT_EN_s
ALT_NAND_CFG_GLOB_INT_EN_t
;
1460
#endif
/* __ASSEMBLY__ */
1461
1463
#define ALT_NAND_CFG_GLOB_INT_EN_RESET 0x00000000
1464
1465
#define ALT_NAND_CFG_GLOB_INT_EN_OFST 0xf0
1466
1494
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_LSB 0
1495
1496
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_MSB 5
1497
1498
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_WIDTH 6
1499
1500
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET_MSK 0x0000003f
1501
1502
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_CLR_MSK 0xffffffc0
1503
1504
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_RESET 0x32
1505
1506
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_GET(value) (((value) & 0x0000003f) >> 0)
1507
1508
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_WE_2_RE_SET(value) (((value) << 0) & 0x0000003f)
1509
1522
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_LSB 8
1523
1524
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_MSB 13
1525
1526
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_WIDTH 6
1527
1528
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET_MSK 0x00003f00
1529
1530
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_CLR_MSK 0xffffc0ff
1531
1532
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_RESET 0x14
1533
1534
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_GET(value) (((value) & 0x00003f00) >> 8)
1535
1536
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_TWHR2_SET(value) (((value) << 8) & 0x00003f00)
1537
1538
#ifndef __ASSEMBLY__
1539
1549
struct
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
1550
{
1551
uint32_t
we_2_re
: 6;
1552
uint32_t : 2;
1553
uint32_t
twhr2
: 6;
1554
uint32_t : 18;
1555
};
1556
1558
typedef
volatile
struct
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_s
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t
;
1559
#endif
/* __ASSEMBLY__ */
1560
1562
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_RESET 0x00001432
1563
1564
#define ALT_NAND_CFG_TWHR2_AND_WE_2_RE_OFST 0x100
1565
1593
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0
1594
1595
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 6
1596
1597
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 7
1598
1599
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000007f
1600
1601
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffff80
1602
1603
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32
1604
1605
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000007f) >> 0)
1606
1607
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000007f)
1608
1623
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8
1624
1625
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13
1626
1627
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6
1628
1629
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00
1630
1631
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff
1632
1633
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14
1634
1635
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8)
1636
1637
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00)
1638
1639
#ifndef __ASSEMBLY__
1640
1650
struct
ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
1651
{
1652
uint32_t
addr_2_data
: 7;
1653
uint32_t : 1;
1654
uint32_t
tcwaw
: 6;
1655
uint32_t : 18;
1656
};
1657
1659
typedef
volatile
struct
ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s
ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t
;
1660
#endif
/* __ASSEMBLY__ */
1661
1663
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_RESET 0x00001432
1664
1665
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110
1666
1694
#define ALT_NAND_CFG_RE_2_WE_VALUE_LSB 0
1695
1696
#define ALT_NAND_CFG_RE_2_WE_VALUE_MSB 5
1697
1698
#define ALT_NAND_CFG_RE_2_WE_VALUE_WIDTH 6
1699
1700
#define ALT_NAND_CFG_RE_2_WE_VALUE_SET_MSK 0x0000003f
1701
1702
#define ALT_NAND_CFG_RE_2_WE_VALUE_CLR_MSK 0xffffffc0
1703
1704
#define ALT_NAND_CFG_RE_2_WE_VALUE_RESET 0x32
1705
1706
#define ALT_NAND_CFG_RE_2_WE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
1707
1708
#define ALT_NAND_CFG_RE_2_WE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
1709
1710
#ifndef __ASSEMBLY__
1711
1721
struct
ALT_NAND_CFG_RE_2_WE_s
1722
{
1723
uint32_t
value
: 6;
1724
uint32_t : 26;
1725
};
1726
1728
typedef
volatile
struct
ALT_NAND_CFG_RE_2_WE_s
ALT_NAND_CFG_RE_2_WE_t
;
1729
#endif
/* __ASSEMBLY__ */
1730
1732
#define ALT_NAND_CFG_RE_2_WE_RESET 0x00000032
1733
1734
#define ALT_NAND_CFG_RE_2_WE_OFST 0x120
1735
1762
#define ALT_NAND_CFG_ACC_CLKS_VALUE_LSB 0
1763
1764
#define ALT_NAND_CFG_ACC_CLKS_VALUE_MSB 3
1765
1766
#define ALT_NAND_CFG_ACC_CLKS_VALUE_WIDTH 4
1767
1768
#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET_MSK 0x0000000f
1769
1770
#define ALT_NAND_CFG_ACC_CLKS_VALUE_CLR_MSK 0xfffffff0
1771
1772
#define ALT_NAND_CFG_ACC_CLKS_VALUE_RESET 0x0
1773
1774
#define ALT_NAND_CFG_ACC_CLKS_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
1775
1776
#define ALT_NAND_CFG_ACC_CLKS_VALUE_SET(value) (((value) << 0) & 0x0000000f)
1777
1778
#ifndef __ASSEMBLY__
1779
1789
struct
ALT_NAND_CFG_ACC_CLKS_s
1790
{
1791
uint32_t
value
: 4;
1792
uint32_t : 28;
1793
};
1794
1796
typedef
volatile
struct
ALT_NAND_CFG_ACC_CLKS_s
ALT_NAND_CFG_ACC_CLKS_t
;
1797
#endif
/* __ASSEMBLY__ */
1798
1800
#define ALT_NAND_CFG_ACC_CLKS_RESET 0x00000000
1801
1802
#define ALT_NAND_CFG_ACC_CLKS_OFST 0x130
1803
1844
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_LSB 0
1845
1846
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_MSB 2
1847
1848
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_WIDTH 3
1849
1850
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET_MSK 0x00000007
1851
1852
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_CLR_MSK 0xfffffff8
1853
1854
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_RESET 0x0
1855
1856
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_GET(value) (((value) & 0x00000007) >> 0)
1857
1858
#define ALT_NAND_CFG_NUMBER_OF_PLANES_VALUE_SET(value) (((value) << 0) & 0x00000007)
1859
1860
#ifndef __ASSEMBLY__
1861
1871
struct
ALT_NAND_CFG_NUMBER_OF_PLANES_s
1872
{
1873
uint32_t
value
: 3;
1874
uint32_t : 29;
1875
};
1876
1878
typedef
volatile
struct
ALT_NAND_CFG_NUMBER_OF_PLANES_s
ALT_NAND_CFG_NUMBER_OF_PLANES_t
;
1879
#endif
/* __ASSEMBLY__ */
1880
1882
#define ALT_NAND_CFG_NUMBER_OF_PLANES_RESET 0x00000000
1883
1884
#define ALT_NAND_CFG_NUMBER_OF_PLANES_OFST 0x140
1885
1914
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_LSB 0
1915
1916
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_MSB 15
1917
1918
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_WIDTH 16
1919
1920
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET_MSK 0x0000ffff
1921
1922
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_CLR_MSK 0xffff0000
1923
1924
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_RESET 0x0
1925
1926
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
1927
1928
#define ALT_NAND_CFG_PAGES_PER_BLOCK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
1929
1930
#ifndef __ASSEMBLY__
1931
1941
struct
ALT_NAND_CFG_PAGES_PER_BLOCK_s
1942
{
1943
uint32_t
value
: 16;
1944
uint32_t : 16;
1945
};
1946
1948
typedef
volatile
struct
ALT_NAND_CFG_PAGES_PER_BLOCK_s
ALT_NAND_CFG_PAGES_PER_BLOCK_t
;
1949
#endif
/* __ASSEMBLY__ */
1950
1952
#define ALT_NAND_CFG_PAGES_PER_BLOCK_RESET 0x00000000
1953
1954
#define ALT_NAND_CFG_PAGES_PER_BLOCK_OFST 0x150
1955
1986
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_LSB 0
1987
1988
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_MSB 1
1989
1990
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_WIDTH 2
1991
1992
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET_MSK 0x00000003
1993
1994
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_CLR_MSK 0xfffffffc
1995
1996
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_RESET 0x3
1997
1998
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_GET(value) (((value) & 0x00000003) >> 0)
1999
2000
#define ALT_NAND_CFG_DEVICE_WIDTH_VALUE_SET(value) (((value) << 0) & 0x00000003)
2001
2002
#ifndef __ASSEMBLY__
2003
2013
struct
ALT_NAND_CFG_DEVICE_WIDTH_s
2014
{
2015
uint32_t
value
: 2;
2016
uint32_t : 30;
2017
};
2018
2020
typedef
volatile
struct
ALT_NAND_CFG_DEVICE_WIDTH_s
ALT_NAND_CFG_DEVICE_WIDTH_t
;
2021
#endif
/* __ASSEMBLY__ */
2022
2024
#define ALT_NAND_CFG_DEVICE_WIDTH_RESET 0x00000003
2025
2026
#define ALT_NAND_CFG_DEVICE_WIDTH_OFST 0x160
2027
2056
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_LSB 0
2057
2058
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_MSB 15
2059
2060
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_WIDTH 16
2061
2062
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2063
2064
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2065
2066
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_RESET 0x0
2067
2068
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2069
2070
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2071
2072
#ifndef __ASSEMBLY__
2073
2083
struct
ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
2084
{
2085
uint32_t
value
: 16;
2086
uint32_t : 16;
2087
};
2088
2090
typedef
volatile
struct
ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_s
ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t
;
2091
#endif
/* __ASSEMBLY__ */
2092
2094
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_RESET 0x00000000
2095
2096
#define ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_OFST 0x170
2097
2126
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_LSB 0
2127
2128
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_MSB 15
2129
2130
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_WIDTH 16
2131
2132
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET_MSK 0x0000ffff
2133
2134
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_CLR_MSK 0xffff0000
2135
2136
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_RESET 0x0
2137
2138
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
2139
2140
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
2141
2142
#ifndef __ASSEMBLY__
2143
2153
struct
ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
2154
{
2155
uint32_t
value
: 16;
2156
uint32_t : 16;
2157
};
2158
2160
typedef
volatile
struct
ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_s
ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t
;
2161
#endif
/* __ASSEMBLY__ */
2162
2164
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_RESET 0x00000000
2165
2166
#define ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_OFST 0x180
2167
2196
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0
2197
2198
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0
2199
2200
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1
2201
2202
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001
2203
2204
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe
2205
2206
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0
2207
2208
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2209
2210
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001)
2211
2223
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4
2224
2225
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4
2226
2227
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1
2228
2229
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010
2230
2231
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef
2232
2233
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0
2234
2235
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4)
2236
2237
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010)
2238
2239
#ifndef __ASSEMBLY__
2240
2250
struct
ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
2251
{
2252
uint32_t
flag
: 1;
2253
uint32_t : 3;
2254
uint32_t
four
: 1;
2255
uint32_t : 27;
2256
};
2257
2259
typedef
volatile
struct
ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s
ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t
;
2260
#endif
/* __ASSEMBLY__ */
2261
2263
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000
2264
2265
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190
2266
2295
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_LSB 0
2296
2297
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_MSB 0
2298
2299
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_WIDTH 1
2300
2301
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET_MSK 0x00000001
2302
2303
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_CLR_MSK 0xfffffffe
2304
2305
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_RESET 0x0
2306
2307
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
2308
2309
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_FLAG_SET(value) (((value) << 0) & 0x00000001)
2310
2311
#ifndef __ASSEMBLY__
2312
2322
struct
ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
2323
{
2324
uint32_t
flag
: 1;
2325
uint32_t : 31;
2326
};
2327
2329
typedef
volatile
struct
ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_s
ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t
;
2330
#endif
/* __ASSEMBLY__ */
2331
2333
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_RESET 0x00000000
2334
2335
#define ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_OFST 0x1a0
2336
2376
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_LSB 0
2377
2378
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_MSB 7
2379
2380
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_WIDTH 8
2381
2382
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET_MSK 0x000000ff
2383
2384
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_CLR_MSK 0xffffff00
2385
2386
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_RESET 0x8
2387
2388
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
2389
2390
#define ALT_NAND_CFG_ECC_CORRECTION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
2391
2423
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_LSB 16
2424
2425
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_MSB 31
2426
2427
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_WIDTH 16
2428
2429
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET_MSK 0xffff0000
2430
2431
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_CLR_MSK 0x0000ffff
2432
2433
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_RESET 0x0
2434
2435
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_GET(value) (((value) & 0xffff0000) >> 16)
2436
2437
#define ALT_NAND_CFG_ECC_CORRECTION_ERASE_THRESHOLD_SET(value) (((value) << 16) & 0xffff0000)
2438
2439
#ifndef __ASSEMBLY__
2440
2450
struct
ALT_NAND_CFG_ECC_CORRECTION_s
2451
{
2452
uint32_t
value
: 8;
2453
uint32_t : 8;
2454
uint32_t
erase_threshold
: 16;
2455
};
2456
2458
typedef
volatile
struct
ALT_NAND_CFG_ECC_CORRECTION_s
ALT_NAND_CFG_ECC_CORRECTION_t
;
2459
#endif
/* __ASSEMBLY__ */
2460
2462
#define ALT_NAND_CFG_ECC_CORRECTION_RESET 0x00000008
2463
2464
#define ALT_NAND_CFG_ECC_CORRECTION_OFST 0x1b0
2465
2578
#define ALT_NAND_CFG_RD_MOD_VALUE_LSB 0
2579
2580
#define ALT_NAND_CFG_RD_MOD_VALUE_MSB 3
2581
2582
#define ALT_NAND_CFG_RD_MOD_VALUE_WIDTH 4
2583
2584
#define ALT_NAND_CFG_RD_MOD_VALUE_SET_MSK 0x0000000f
2585
2586
#define ALT_NAND_CFG_RD_MOD_VALUE_CLR_MSK 0xfffffff0
2587
2588
#define ALT_NAND_CFG_RD_MOD_VALUE_RESET 0x0
2589
2590
#define ALT_NAND_CFG_RD_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2591
2592
#define ALT_NAND_CFG_RD_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2593
2594
#ifndef __ASSEMBLY__
2595
2605
struct
ALT_NAND_CFG_RD_MOD_s
2606
{
2607
uint32_t
value
: 4;
2608
uint32_t : 28;
2609
};
2610
2612
typedef
volatile
struct
ALT_NAND_CFG_RD_MOD_s
ALT_NAND_CFG_RD_MOD_t
;
2613
#endif
/* __ASSEMBLY__ */
2614
2616
#define ALT_NAND_CFG_RD_MOD_RESET 0x00000000
2617
2618
#define ALT_NAND_CFG_RD_MOD_OFST 0x1c0
2619
2695
#define ALT_NAND_CFG_WR_MOD_VALUE_LSB 0
2696
2697
#define ALT_NAND_CFG_WR_MOD_VALUE_MSB 3
2698
2699
#define ALT_NAND_CFG_WR_MOD_VALUE_WIDTH 4
2700
2701
#define ALT_NAND_CFG_WR_MOD_VALUE_SET_MSK 0x0000000f
2702
2703
#define ALT_NAND_CFG_WR_MOD_VALUE_CLR_MSK 0xfffffff0
2704
2705
#define ALT_NAND_CFG_WR_MOD_VALUE_RESET 0x0
2706
2707
#define ALT_NAND_CFG_WR_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2708
2709
#define ALT_NAND_CFG_WR_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2710
2711
#ifndef __ASSEMBLY__
2712
2722
struct
ALT_NAND_CFG_WR_MOD_s
2723
{
2724
uint32_t
value
: 4;
2725
uint32_t : 28;
2726
};
2727
2729
typedef
volatile
struct
ALT_NAND_CFG_WR_MOD_s
ALT_NAND_CFG_WR_MOD_t
;
2730
#endif
/* __ASSEMBLY__ */
2731
2733
#define ALT_NAND_CFG_WR_MOD_RESET 0x00000000
2734
2735
#define ALT_NAND_CFG_WR_MOD_OFST 0x1d0
2736
2813
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_LSB 0
2814
2815
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_MSB 3
2816
2817
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_WIDTH 4
2818
2819
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET_MSK 0x0000000f
2820
2821
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_CLR_MSK 0xfffffff0
2822
2823
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_RESET 0x0
2824
2825
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
2826
2827
#define ALT_NAND_CFG_COPYBACK_MOD_VALUE_SET(value) (((value) << 0) & 0x0000000f)
2828
2829
#ifndef __ASSEMBLY__
2830
2840
struct
ALT_NAND_CFG_COPYBACK_MOD_s
2841
{
2842
uint32_t
value
: 4;
2843
uint32_t : 28;
2844
};
2845
2847
typedef
volatile
struct
ALT_NAND_CFG_COPYBACK_MOD_s
ALT_NAND_CFG_COPYBACK_MOD_t
;
2848
#endif
/* __ASSEMBLY__ */
2849
2851
#define ALT_NAND_CFG_COPYBACK_MOD_RESET 0x00000000
2852
2853
#define ALT_NAND_CFG_COPYBACK_MOD_OFST 0x1e0
2854
2886
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0
2887
2888
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4
2889
2890
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5
2891
2892
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f
2893
2894
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0
2895
2896
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12
2897
2898
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2899
2900
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2901
2902
#ifndef __ASSEMBLY__
2903
2913
struct
ALT_NAND_CFG_RDWR_EN_LO_CNT_s
2914
{
2915
uint32_t
value
: 5;
2916
uint32_t : 27;
2917
};
2918
2920
typedef
volatile
struct
ALT_NAND_CFG_RDWR_EN_LO_CNT_s
ALT_NAND_CFG_RDWR_EN_LO_CNT_t
;
2921
#endif
/* __ASSEMBLY__ */
2922
2924
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_RESET 0x00000012
2925
2926
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0
2927
2960
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_LSB 0
2961
2962
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_MSB 4
2963
2964
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_WIDTH 5
2965
2966
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET_MSK 0x0000001f
2967
2968
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_CLR_MSK 0xffffffe0
2969
2970
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_RESET 0xc
2971
2972
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
2973
2974
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
2975
2976
#ifndef __ASSEMBLY__
2977
2987
struct
ALT_NAND_CFG_RDWR_EN_HI_CNT_s
2988
{
2989
uint32_t
value
: 5;
2990
uint32_t : 27;
2991
};
2992
2994
typedef
volatile
struct
ALT_NAND_CFG_RDWR_EN_HI_CNT_s
ALT_NAND_CFG_RDWR_EN_HI_CNT_t
;
2995
#endif
/* __ASSEMBLY__ */
2996
2998
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_RESET 0x0000000c
2999
3000
#define ALT_NAND_CFG_RDWR_EN_HI_CNT_OFST 0x200
3001
3035
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB 0
3036
3037
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB 3
3038
3039
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH 4
3040
3041
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK 0x0000000f
3042
3043
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK 0xfffffff0
3044
3045
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET 0x0
3046
3047
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
3048
3049
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value) (((value) << 0) & 0x0000000f)
3050
3051
#ifndef __ASSEMBLY__
3052
3062
struct
ALT_NAND_CFG_MAX_RD_DELAY_s
3063
{
3064
uint32_t
value
: 4;
3065
uint32_t : 28;
3066
};
3067
3069
typedef
volatile
struct
ALT_NAND_CFG_MAX_RD_DELAY_s
ALT_NAND_CFG_MAX_RD_DELAY_t
;
3070
#endif
/* __ASSEMBLY__ */
3071
3073
#define ALT_NAND_CFG_MAX_RD_DELAY_RESET 0x00000000
3074
3075
#define ALT_NAND_CFG_MAX_RD_DELAY_OFST 0x210
3076
3116
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_LSB 0
3117
3118
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_MSB 4
3119
3120
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_WIDTH 5
3121
3122
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET_MSK 0x0000001f
3123
3124
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_CLR_MSK 0xffffffe0
3125
3126
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_RESET 0x3
3127
3128
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0)
3129
3130
#define ALT_NAND_CFG_CS_SETUP_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f)
3131
3143
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_LSB 12
3144
3145
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_MSB 17
3146
3147
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_WIDTH 6
3148
3149
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET_MSK 0x0003f000
3150
3151
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_CLR_MSK 0xfffc0fff
3152
3153
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_RESET 0xa
3154
3155
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_GET(value) (((value) & 0x0003f000) >> 12)
3156
3157
#define ALT_NAND_CFG_CS_SETUP_CNT_TWB_SET(value) (((value) << 12) & 0x0003f000)
3158
3159
#ifndef __ASSEMBLY__
3160
3170
struct
ALT_NAND_CFG_CS_SETUP_CNT_s
3171
{
3172
uint32_t
value
: 5;
3173
uint32_t : 7;
3174
uint32_t
twb
: 6;
3175
uint32_t : 14;
3176
};
3177
3179
typedef
volatile
struct
ALT_NAND_CFG_CS_SETUP_CNT_s
ALT_NAND_CFG_CS_SETUP_CNT_t
;
3180
#endif
/* __ASSEMBLY__ */
3181
3183
#define ALT_NAND_CFG_CS_SETUP_CNT_RESET 0x0000a003
3184
3185
#define ALT_NAND_CFG_CS_SETUP_CNT_OFST 0x220
3186
3221
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_LSB 0
3222
3223
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_MSB 5
3224
3225
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_WIDTH 6
3226
3227
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET_MSK 0x0000003f
3228
3229
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_CLR_MSK 0xffffffc0
3230
3231
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_RESET 0x0
3232
3233
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3234
3235
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3236
3237
#ifndef __ASSEMBLY__
3238
3248
struct
ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
3249
{
3250
uint32_t
value
: 6;
3251
uint32_t : 26;
3252
};
3253
3255
typedef
volatile
struct
ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_s
ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t
;
3256
#endif
/* __ASSEMBLY__ */
3257
3259
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_RESET 0x00000000
3260
3261
#define ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_OFST 0x230
3262
3287
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_LSB 0
3288
3289
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_MSB 15
3290
3291
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_WIDTH 16
3292
3293
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET_MSK 0x0000ffff
3294
3295
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_CLR_MSK 0xffff0000
3296
3297
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_RESET 0xffff
3298
3299
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3300
3301
#define ALT_NAND_CFG_SPARE_AREA_MARKER_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3302
3303
#ifndef __ASSEMBLY__
3304
3314
struct
ALT_NAND_CFG_SPARE_AREA_MARKER_s
3315
{
3316
uint32_t
value
: 16;
3317
uint32_t : 16;
3318
};
3319
3321
typedef
volatile
struct
ALT_NAND_CFG_SPARE_AREA_MARKER_s
ALT_NAND_CFG_SPARE_AREA_MARKER_t
;
3322
#endif
/* __ASSEMBLY__ */
3323
3325
#define ALT_NAND_CFG_SPARE_AREA_MARKER_RESET 0x0000ffff
3326
3327
#define ALT_NAND_CFG_SPARE_AREA_MARKER_OFST 0x240
3328
3353
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_LSB 0
3354
3355
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_MSB 2
3356
3357
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_WIDTH 3
3358
3359
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET_MSK 0x00000007
3360
3361
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_CLR_MSK 0xfffffff8
3362
3363
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_RESET 0x0
3364
3365
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_GET(value) (((value) & 0x00000007) >> 0)
3366
3367
#define ALT_NAND_CFG_DEVICES_CONNECTED_VALUE_SET(value) (((value) << 0) & 0x00000007)
3368
3369
#ifndef __ASSEMBLY__
3370
3380
struct
ALT_NAND_CFG_DEVICES_CONNECTED_s
3381
{
3382
uint32_t
value
: 3;
3383
uint32_t : 29;
3384
};
3385
3387
typedef
volatile
struct
ALT_NAND_CFG_DEVICES_CONNECTED_s
ALT_NAND_CFG_DEVICES_CONNECTED_t
;
3388
#endif
/* __ASSEMBLY__ */
3389
3391
#define ALT_NAND_CFG_DEVICES_CONNECTED_RESET 0x00000000
3392
3393
#define ALT_NAND_CFG_DEVICES_CONNECTED_OFST 0x250
3394
3434
#define ALT_NAND_CFG_DIE_MSK_VALUE_LSB 0
3435
3436
#define ALT_NAND_CFG_DIE_MSK_VALUE_MSB 15
3437
3438
#define ALT_NAND_CFG_DIE_MSK_VALUE_WIDTH 16
3439
3440
#define ALT_NAND_CFG_DIE_MSK_VALUE_SET_MSK 0x0000ffff
3441
3442
#define ALT_NAND_CFG_DIE_MSK_VALUE_CLR_MSK 0xffff0000
3443
3444
#define ALT_NAND_CFG_DIE_MSK_VALUE_RESET 0x0
3445
3446
#define ALT_NAND_CFG_DIE_MSK_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3447
3448
#define ALT_NAND_CFG_DIE_MSK_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3449
3450
#ifndef __ASSEMBLY__
3451
3461
struct
ALT_NAND_CFG_DIE_MSK_s
3462
{
3463
uint32_t
value
: 16;
3464
uint32_t : 16;
3465
};
3466
3468
typedef
volatile
struct
ALT_NAND_CFG_DIE_MSK_s
ALT_NAND_CFG_DIE_MSK_t
;
3469
#endif
/* __ASSEMBLY__ */
3470
3472
#define ALT_NAND_CFG_DIE_MSK_RESET 0x00000000
3473
3474
#define ALT_NAND_CFG_DIE_MSK_OFST 0x260
3475
3506
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_LSB 0
3507
3508
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_MSB 15
3509
3510
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_WIDTH 16
3511
3512
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET_MSK 0x0000ffff
3513
3514
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_CLR_MSK 0xffff0000
3515
3516
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_RESET 0x1
3517
3518
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3519
3520
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3521
3522
#ifndef __ASSEMBLY__
3523
3533
struct
ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
3534
{
3535
uint32_t
value
: 16;
3536
uint32_t : 16;
3537
};
3538
3540
typedef
volatile
struct
ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_s
ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t
;
3541
#endif
/* __ASSEMBLY__ */
3542
3544
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_RESET 0x00000001
3545
3546
#define ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_OFST 0x270
3547
3579
#define ALT_NAND_CFG_WR_PROTECT_FLAG_LSB 0
3580
3581
#define ALT_NAND_CFG_WR_PROTECT_FLAG_MSB 0
3582
3583
#define ALT_NAND_CFG_WR_PROTECT_FLAG_WIDTH 1
3584
3585
#define ALT_NAND_CFG_WR_PROTECT_FLAG_SET_MSK 0x00000001
3586
3587
#define ALT_NAND_CFG_WR_PROTECT_FLAG_CLR_MSK 0xfffffffe
3588
3589
#define ALT_NAND_CFG_WR_PROTECT_FLAG_RESET 0x1
3590
3591
#define ALT_NAND_CFG_WR_PROTECT_FLAG_GET(value) (((value) & 0x00000001) >> 0)
3592
3593
#define ALT_NAND_CFG_WR_PROTECT_FLAG_SET(value) (((value) << 0) & 0x00000001)
3594
3595
#ifndef __ASSEMBLY__
3596
3606
struct
ALT_NAND_CFG_WR_PROTECT_s
3607
{
3608
uint32_t
flag
: 1;
3609
uint32_t : 31;
3610
};
3611
3613
typedef
volatile
struct
ALT_NAND_CFG_WR_PROTECT_s
ALT_NAND_CFG_WR_PROTECT_t
;
3614
#endif
/* __ASSEMBLY__ */
3615
3617
#define ALT_NAND_CFG_WR_PROTECT_RESET 0x00000001
3618
3619
#define ALT_NAND_CFG_WR_PROTECT_OFST 0x280
3620
3650
#define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0
3651
3652
#define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5
3653
3654
#define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6
3655
3656
#define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f
3657
3658
#define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0
3659
3660
#define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32
3661
3662
#define ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
3663
3664
#define ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f)
3665
3666
#ifndef __ASSEMBLY__
3667
3677
struct
ALT_NAND_CFG_RE_2_RE_s
3678
{
3679
uint32_t
value
: 6;
3680
uint32_t : 26;
3681
};
3682
3684
typedef
volatile
struct
ALT_NAND_CFG_RE_2_RE_s
ALT_NAND_CFG_RE_2_RE_t
;
3685
#endif
/* __ASSEMBLY__ */
3686
3688
#define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032
3689
3690
#define ALT_NAND_CFG_RE_2_RE_OFST 0x290
3691
3721
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB 0
3722
3723
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB 15
3724
3725
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH 16
3726
3727
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3728
3729
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3730
3731
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET 0x13b
3732
3733
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3734
3735
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3736
3737
#ifndef __ASSEMBLY__
3738
3748
struct
ALT_NAND_CFG_POR_RST_COUNT_s
3749
{
3750
uint32_t
value
: 16;
3751
uint32_t : 16;
3752
};
3753
3755
typedef
volatile
struct
ALT_NAND_CFG_POR_RST_COUNT_s
ALT_NAND_CFG_POR_RST_COUNT_t
;
3756
#endif
/* __ASSEMBLY__ */
3757
3759
#define ALT_NAND_CFG_POR_RST_COUNT_RESET 0x0000013b
3760
3761
#define ALT_NAND_CFG_POR_RST_COUNT_OFST 0x2a0
3762
3793
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_LSB 0
3794
3795
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_MSB 15
3796
3797
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_WIDTH 16
3798
3799
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET_MSK 0x0000ffff
3800
3801
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_CLR_MSK 0xffff0000
3802
3803
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_RESET 0x5b9a
3804
3805
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
3806
3807
#define ALT_NAND_CFG_WD_RST_COUNT_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
3808
3809
#ifndef __ASSEMBLY__
3810
3820
struct
ALT_NAND_CFG_WD_RST_COUNT_s
3821
{
3822
uint32_t
value
: 16;
3823
uint32_t : 16;
3824
};
3825
3827
typedef
volatile
struct
ALT_NAND_CFG_WD_RST_COUNT_s
ALT_NAND_CFG_WD_RST_COUNT_t
;
3828
#endif
/* __ASSEMBLY__ */
3829
3831
#define ALT_NAND_CFG_WD_RST_COUNT_RESET 0x00005b9a
3832
3833
#define ALT_NAND_CFG_WD_RST_COUNT_OFST 0x2b0
3834
3835
#ifndef __ASSEMBLY__
3836
3846
struct
ALT_NAND_CFG_s
3847
{
3848
volatile
ALT_NAND_CFG_DEVICE_RST_t
device_reset
;
3849
volatile
uint32_t
_pad_0x4_0xf
[3];
3850
volatile
ALT_NAND_CFG_TFR_SPARE_REG_t
transfer_spare_reg
;
3851
volatile
uint32_t
_pad_0x14_0x1f
[3];
3852
volatile
ALT_NAND_CFG_LD_WAIT_CNT_t
load_wait_cnt
;
3853
volatile
uint32_t
_pad_0x24_0x2f
[3];
3854
volatile
ALT_NAND_CFG_PROGRAM_WAIT_CNT_t
program_wait_cnt
;
3855
volatile
uint32_t
_pad_0x34_0x3f
[3];
3856
volatile
ALT_NAND_CFG_ERASE_WAIT_CNT_t
erase_wait_cnt
;
3857
volatile
uint32_t
_pad_0x44_0x4f
[3];
3858
volatile
ALT_NAND_CFG_INT_MON_CYCCNT_t
int_mon_cyccnt
;
3859
volatile
uint32_t
_pad_0x54_0x5f
[3];
3860
volatile
ALT_NAND_CFG_RB_PIN_END_t
rb_pin_enabled
;
3861
volatile
uint32_t
_pad_0x64_0x6f
[3];
3862
volatile
ALT_NAND_CFG_MULTIPLANE_OP_t
multiplane_operation
;
3863
volatile
uint32_t
_pad_0x74_0x7f
[3];
3864
volatile
ALT_NAND_CFG_MULTIPLANE_RD_EN_t
multiplane_read_enable
;
3865
volatile
uint32_t
_pad_0x84_0x8f
[3];
3866
volatile
ALT_NAND_CFG_COPYBACK_DIS_t
copyback_disable
;
3867
volatile
uint32_t
_pad_0x94_0x9f
[3];
3868
volatile
ALT_NAND_CFG_CACHE_WR_EN_t
cache_write_enable
;
3869
volatile
uint32_t
_pad_0xa4_0xaf
[3];
3870
volatile
ALT_NAND_CFG_CACHE_RD_EN_t
cache_read_enable
;
3871
volatile
uint32_t
_pad_0xb4_0xbf
[3];
3872
volatile
ALT_NAND_CFG_PREFETCH_MOD_t
prefetch_mode
;
3873
volatile
uint32_t
_pad_0xc4_0xcf
[3];
3874
volatile
ALT_NAND_CFG_CHIP_EN_DONT_CARE_t
chip_enable_dont_care
;
3875
volatile
uint32_t
_pad_0xd4_0xdf
[3];
3876
volatile
ALT_NAND_CFG_ECC_EN_t
ecc_enable
;
3877
volatile
uint32_t
_pad_0xe4_0xef
[3];
3878
volatile
ALT_NAND_CFG_GLOB_INT_EN_t
global_int_enable
;
3879
volatile
uint32_t
_pad_0xf4_0xff
[3];
3880
volatile
ALT_NAND_CFG_TWHR2_AND_WE_2_RE_t
twhr2_and_we_2_re
;
3881
volatile
uint32_t
_pad_0x104_0x10f
[3];
3882
volatile
ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t
tcwaw_and_addr_2_data
;
3883
volatile
uint32_t
_pad_0x114_0x11f
[3];
3884
volatile
ALT_NAND_CFG_RE_2_WE_t
re_2_we
;
3885
volatile
uint32_t
_pad_0x124_0x12f
[3];
3886
volatile
ALT_NAND_CFG_ACC_CLKS_t
acc_clks
;
3887
volatile
uint32_t
_pad_0x134_0x13f
[3];
3888
volatile
ALT_NAND_CFG_NUMBER_OF_PLANES_t
number_of_planes
;
3889
volatile
uint32_t
_pad_0x144_0x14f
[3];
3890
volatile
ALT_NAND_CFG_PAGES_PER_BLOCK_t
pages_per_block
;
3891
volatile
uint32_t
_pad_0x154_0x15f
[3];
3892
volatile
ALT_NAND_CFG_DEVICE_WIDTH_t
device_width
;
3893
volatile
uint32_t
_pad_0x164_0x16f
[3];
3894
volatile
ALT_NAND_CFG_DEVICE_MAIN_AREA_SIZE_t
device_main_area_size
;
3895
volatile
uint32_t
_pad_0x174_0x17f
[3];
3896
volatile
ALT_NAND_CFG_DEVICE_SPARE_AREA_SIZE_t
device_spare_area_size
;
3897
volatile
uint32_t
_pad_0x184_0x18f
[3];
3898
volatile
ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t
two_row_addr_cycles
;
3899
volatile
uint32_t
_pad_0x194_0x19f
[3];
3900
volatile
ALT_NAND_CFG_MULTIPLANE_ADDR_RESTRICT_t
multiplane_addr_restrict
;
3901
volatile
uint32_t
_pad_0x1a4_0x1af
[3];
3902
volatile
ALT_NAND_CFG_ECC_CORRECTION_t
ecc_correction
;
3903
volatile
uint32_t
_pad_0x1b4_0x1bf
[3];
3904
volatile
ALT_NAND_CFG_RD_MOD_t
read_mode
;
3905
volatile
uint32_t
_pad_0x1c4_0x1cf
[3];
3906
volatile
ALT_NAND_CFG_WR_MOD_t
write_mode
;
3907
volatile
uint32_t
_pad_0x1d4_0x1df
[3];
3908
volatile
ALT_NAND_CFG_COPYBACK_MOD_t
copyback_mode
;
3909
volatile
uint32_t
_pad_0x1e4_0x1ef
[3];
3910
volatile
ALT_NAND_CFG_RDWR_EN_LO_CNT_t
rdwr_en_lo_cnt
;
3911
volatile
uint32_t
_pad_0x1f4_0x1ff
[3];
3912
volatile
ALT_NAND_CFG_RDWR_EN_HI_CNT_t
rdwr_en_hi_cnt
;
3913
volatile
uint32_t
_pad_0x204_0x20f
[3];
3914
volatile
ALT_NAND_CFG_MAX_RD_DELAY_t
max_rd_delay
;
3915
volatile
uint32_t
_pad_0x214_0x21f
[3];
3916
volatile
ALT_NAND_CFG_CS_SETUP_CNT_t
cs_setup_cnt
;
3917
volatile
uint32_t
_pad_0x224_0x22f
[3];
3918
volatile
ALT_NAND_CFG_SPARE_AREA_SKIP_BYTES_t
spare_area_skip_bytes
;
3919
volatile
uint32_t
_pad_0x234_0x23f
[3];
3920
volatile
ALT_NAND_CFG_SPARE_AREA_MARKER_t
spare_area_marker
;
3921
volatile
uint32_t
_pad_0x244_0x24f
[3];
3922
volatile
ALT_NAND_CFG_DEVICES_CONNECTED_t
devices_connected
;
3923
volatile
uint32_t
_pad_0x254_0x25f
[3];
3924
volatile
ALT_NAND_CFG_DIE_MSK_t
die_mask
;
3925
volatile
uint32_t
_pad_0x264_0x26f
[3];
3926
volatile
ALT_NAND_CFG_FIRST_BLOCK_OF_NEXT_PLANE_t
first_block_of_next_plane
;
3927
volatile
uint32_t
_pad_0x274_0x27f
[3];
3928
volatile
ALT_NAND_CFG_WR_PROTECT_t
write_protect
;
3929
volatile
uint32_t
_pad_0x284_0x28f
[3];
3930
volatile
ALT_NAND_CFG_RE_2_RE_t
re_2_re
;
3931
volatile
uint32_t
_pad_0x294_0x29f
[3];
3932
volatile
ALT_NAND_CFG_POR_RST_COUNT_t
por_reset_count
;
3933
volatile
uint32_t
_pad_0x2a4_0x2af
[3];
3934
volatile
ALT_NAND_CFG_WD_RST_COUNT_t
watchdog_reset_count
;
3935
};
3936
3938
typedef
volatile
struct
ALT_NAND_CFG_s
ALT_NAND_CFG_t
;
3940
struct
ALT_NAND_CFG_raw_s
3941
{
3942
volatile
uint32_t
device_reset
;
3943
volatile
uint32_t
_pad_0x4_0xf
[3];
3944
volatile
uint32_t
transfer_spare_reg
;
3945
volatile
uint32_t
_pad_0x14_0x1f
[3];
3946
volatile
uint32_t
load_wait_cnt
;
3947
volatile
uint32_t
_pad_0x24_0x2f
[3];
3948
volatile
uint32_t
program_wait_cnt
;
3949
volatile
uint32_t
_pad_0x34_0x3f
[3];
3950
volatile
uint32_t
erase_wait_cnt
;
3951
volatile
uint32_t
_pad_0x44_0x4f
[3];
3952
volatile
uint32_t
int_mon_cyccnt
;
3953
volatile
uint32_t
_pad_0x54_0x5f
[3];
3954
volatile
uint32_t
rb_pin_enabled
;
3955
volatile
uint32_t
_pad_0x64_0x6f
[3];
3956
volatile
uint32_t
multiplane_operation
;
3957
volatile
uint32_t
_pad_0x74_0x7f
[3];
3958
volatile
uint32_t
multiplane_read_enable
;
3959
volatile
uint32_t
_pad_0x84_0x8f
[3];
3960
volatile
uint32_t
copyback_disable
;
3961
volatile
uint32_t
_pad_0x94_0x9f
[3];
3962
volatile
uint32_t
cache_write_enable
;
3963
volatile
uint32_t
_pad_0xa4_0xaf
[3];
3964
volatile
uint32_t
cache_read_enable
;
3965
volatile
uint32_t
_pad_0xb4_0xbf
[3];
3966
volatile
uint32_t
prefetch_mode
;
3967
volatile
uint32_t
_pad_0xc4_0xcf
[3];
3968
volatile
uint32_t
chip_enable_dont_care
;
3969
volatile
uint32_t
_pad_0xd4_0xdf
[3];
3970
volatile
uint32_t
ecc_enable
;
3971
volatile
uint32_t
_pad_0xe4_0xef
[3];
3972
volatile
uint32_t
global_int_enable
;
3973
volatile
uint32_t
_pad_0xf4_0xff
[3];
3974
volatile
uint32_t
twhr2_and_we_2_re
;
3975
volatile
uint32_t
_pad_0x104_0x10f
[3];
3976
volatile
uint32_t
tcwaw_and_addr_2_data
;
3977
volatile
uint32_t
_pad_0x114_0x11f
[3];
3978
volatile
uint32_t
re_2_we
;
3979
volatile
uint32_t
_pad_0x124_0x12f
[3];
3980
volatile
uint32_t
acc_clks
;
3981
volatile
uint32_t
_pad_0x134_0x13f
[3];
3982
volatile
uint32_t
number_of_planes
;
3983
volatile
uint32_t
_pad_0x144_0x14f
[3];
3984
volatile
uint32_t
pages_per_block
;
3985
volatile
uint32_t
_pad_0x154_0x15f
[3];
3986
volatile
uint32_t
device_width
;
3987
volatile
uint32_t
_pad_0x164_0x16f
[3];
3988
volatile
uint32_t
device_main_area_size
;
3989
volatile
uint32_t
_pad_0x174_0x17f
[3];
3990
volatile
uint32_t
device_spare_area_size
;
3991
volatile
uint32_t
_pad_0x184_0x18f
[3];
3992
volatile
uint32_t
two_row_addr_cycles
;
3993
volatile
uint32_t
_pad_0x194_0x19f
[3];
3994
volatile
uint32_t
multiplane_addr_restrict
;
3995
volatile
uint32_t
_pad_0x1a4_0x1af
[3];
3996
volatile
uint32_t
ecc_correction
;
3997
volatile
uint32_t
_pad_0x1b4_0x1bf
[3];
3998
volatile
uint32_t
read_mode
;
3999
volatile
uint32_t
_pad_0x1c4_0x1cf
[3];
4000
volatile
uint32_t
write_mode
;
4001
volatile
uint32_t
_pad_0x1d4_0x1df
[3];
4002
volatile
uint32_t
copyback_mode
;
4003
volatile
uint32_t
_pad_0x1e4_0x1ef
[3];
4004
volatile
uint32_t
rdwr_en_lo_cnt
;
4005
volatile
uint32_t
_pad_0x1f4_0x1ff
[3];
4006
volatile
uint32_t
rdwr_en_hi_cnt
;
4007
volatile
uint32_t
_pad_0x204_0x20f
[3];
4008
volatile
uint32_t
max_rd_delay
;
4009
volatile
uint32_t
_pad_0x214_0x21f
[3];
4010
volatile
uint32_t
cs_setup_cnt
;
4011
volatile
uint32_t
_pad_0x224_0x22f
[3];
4012
volatile
uint32_t
spare_area_skip_bytes
;
4013
volatile
uint32_t
_pad_0x234_0x23f
[3];
4014
volatile
uint32_t
spare_area_marker
;
4015
volatile
uint32_t
_pad_0x244_0x24f
[3];
4016
volatile
uint32_t
devices_connected
;
4017
volatile
uint32_t
_pad_0x254_0x25f
[3];
4018
volatile
uint32_t
die_mask
;
4019
volatile
uint32_t
_pad_0x264_0x26f
[3];
4020
volatile
uint32_t
first_block_of_next_plane
;
4021
volatile
uint32_t
_pad_0x274_0x27f
[3];
4022
volatile
uint32_t
write_protect
;
4023
volatile
uint32_t
_pad_0x284_0x28f
[3];
4024
volatile
uint32_t
re_2_re
;
4025
volatile
uint32_t
_pad_0x294_0x29f
[3];
4026
volatile
uint32_t
por_reset_count
;
4027
volatile
uint32_t
_pad_0x2a4_0x2af
[3];
4028
volatile
uint32_t
watchdog_reset_count
;
4029
};
4030
4032
typedef
volatile
struct
ALT_NAND_CFG_raw_s
ALT_NAND_CFG_raw_t
;
4033
#endif
/* __ASSEMBLY__ */
4034
4060
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_LSB 0
4061
4062
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_MSB 7
4063
4064
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_WIDTH 8
4065
4066
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET_MSK 0x000000ff
4067
4068
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_CLR_MSK 0xffffff00
4069
4070
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_RESET 0x0
4071
4072
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4073
4074
#define ALT_NAND_PARAM_MANUFACTURER_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4075
4076
#ifndef __ASSEMBLY__
4077
4087
struct
ALT_NAND_PARAM_MANUFACTURER_ID_s
4088
{
4089
uint32_t
value
: 8;
4090
uint32_t : 24;
4091
};
4092
4094
typedef
volatile
struct
ALT_NAND_PARAM_MANUFACTURER_ID_s
ALT_NAND_PARAM_MANUFACTURER_ID_t
;
4095
#endif
/* __ASSEMBLY__ */
4096
4098
#define ALT_NAND_PARAM_MANUFACTURER_ID_RESET 0x00000000
4099
4100
#define ALT_NAND_PARAM_MANUFACTURER_ID_OFST 0x0
4101
4122
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_LSB 0
4123
4124
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_MSB 7
4125
4126
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_WIDTH 8
4127
4128
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET_MSK 0x000000ff
4129
4130
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_CLR_MSK 0xffffff00
4131
4132
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_RESET 0x0
4133
4134
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4135
4136
#define ALT_NAND_PARAM_DEVICE_ID_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4137
4138
#ifndef __ASSEMBLY__
4139
4149
struct
ALT_NAND_PARAM_DEVICE_ID_s
4150
{
4151
const
uint32_t
value
: 8;
4152
uint32_t : 24;
4153
};
4154
4156
typedef
volatile
struct
ALT_NAND_PARAM_DEVICE_ID_s
ALT_NAND_PARAM_DEVICE_ID_t
;
4157
#endif
/* __ASSEMBLY__ */
4158
4160
#define ALT_NAND_PARAM_DEVICE_ID_RESET 0x00000000
4161
4162
#define ALT_NAND_PARAM_DEVICE_ID_OFST 0x10
4163
4186
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_LSB 0
4187
4188
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_MSB 7
4189
4190
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_WIDTH 8
4191
4192
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET_MSK 0x000000ff
4193
4194
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_CLR_MSK 0xffffff00
4195
4196
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_RESET 0x0
4197
4198
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4199
4200
#define ALT_NAND_PARAM_DEVICE_PARAM_0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4201
4202
#ifndef __ASSEMBLY__
4203
4213
struct
ALT_NAND_PARAM_DEVICE_PARAM_0_s
4214
{
4215
const
uint32_t
value
: 8;
4216
uint32_t : 24;
4217
};
4218
4220
typedef
volatile
struct
ALT_NAND_PARAM_DEVICE_PARAM_0_s
ALT_NAND_PARAM_DEVICE_PARAM_0_t
;
4221
#endif
/* __ASSEMBLY__ */
4222
4224
#define ALT_NAND_PARAM_DEVICE_PARAM_0_RESET 0x00000000
4225
4226
#define ALT_NAND_PARAM_DEVICE_PARAM_0_OFST 0x20
4227
4250
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_LSB 0
4251
4252
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_MSB 7
4253
4254
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_WIDTH 8
4255
4256
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET_MSK 0x000000ff
4257
4258
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_CLR_MSK 0xffffff00
4259
4260
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_RESET 0x0
4261
4262
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4263
4264
#define ALT_NAND_PARAM_DEVICE_PARAM_1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4265
4266
#ifndef __ASSEMBLY__
4267
4277
struct
ALT_NAND_PARAM_DEVICE_PARAM_1_s
4278
{
4279
const
uint32_t
value
: 8;
4280
uint32_t : 24;
4281
};
4282
4284
typedef
volatile
struct
ALT_NAND_PARAM_DEVICE_PARAM_1_s
ALT_NAND_PARAM_DEVICE_PARAM_1_t
;
4285
#endif
/* __ASSEMBLY__ */
4286
4288
#define ALT_NAND_PARAM_DEVICE_PARAM_1_RESET 0x00000000
4289
4290
#define ALT_NAND_PARAM_DEVICE_PARAM_1_OFST 0x30
4291
4312
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_LSB 0
4313
4314
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_MSB 7
4315
4316
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_WIDTH 8
4317
4318
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET_MSK 0x000000ff
4319
4320
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_CLR_MSK 0xffffff00
4321
4322
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_RESET 0x0
4323
4324
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4325
4326
#define ALT_NAND_PARAM_DEVICE_PARAM_2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4327
4328
#ifndef __ASSEMBLY__
4329
4339
struct
ALT_NAND_PARAM_DEVICE_PARAM_2_s
4340
{
4341
const
uint32_t
value
: 8;
4342
uint32_t : 24;
4343
};
4344
4346
typedef
volatile
struct
ALT_NAND_PARAM_DEVICE_PARAM_2_s
ALT_NAND_PARAM_DEVICE_PARAM_2_t
;
4347
#endif
/* __ASSEMBLY__ */
4348
4350
#define ALT_NAND_PARAM_DEVICE_PARAM_2_RESET 0x00000000
4351
4352
#define ALT_NAND_PARAM_DEVICE_PARAM_2_OFST 0x40
4353
4380
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_LSB 0
4381
4382
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_MSB 15
4383
4384
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_WIDTH 16
4385
4386
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET_MSK 0x0000ffff
4387
4388
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_CLR_MSK 0xffff0000
4389
4390
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_RESET 0x0
4391
4392
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4393
4394
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4395
4396
#ifndef __ASSEMBLY__
4397
4407
struct
ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
4408
{
4409
const
uint32_t
value
: 16;
4410
uint32_t : 16;
4411
};
4412
4414
typedef
volatile
struct
ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_s
ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t
;
4415
#endif
/* __ASSEMBLY__ */
4416
4418
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_RESET 0x00000000
4419
4420
#define ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_OFST 0x50
4421
4448
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_LSB 0
4449
4450
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_MSB 15
4451
4452
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_WIDTH 16
4453
4454
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET_MSK 0x0000ffff
4455
4456
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_CLR_MSK 0xffff0000
4457
4458
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_RESET 0x0
4459
4460
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4461
4462
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4463
4464
#ifndef __ASSEMBLY__
4465
4475
struct
ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
4476
{
4477
const
uint32_t
value
: 16;
4478
uint32_t : 16;
4479
};
4480
4482
typedef
volatile
struct
ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_s
ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t
;
4483
#endif
/* __ASSEMBLY__ */
4484
4486
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_RESET 0x00000000
4487
4488
#define ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_OFST 0x60
4489
4513
#define ALT_NAND_PARAM_REVISION_VALUE_LSB 0
4514
4515
#define ALT_NAND_PARAM_REVISION_VALUE_MSB 7
4516
4517
#define ALT_NAND_PARAM_REVISION_VALUE_WIDTH 8
4518
4519
#define ALT_NAND_PARAM_REVISION_VALUE_SET_MSK 0x000000ff
4520
4521
#define ALT_NAND_PARAM_REVISION_VALUE_CLR_MSK 0xffffff00
4522
4523
#define ALT_NAND_PARAM_REVISION_VALUE_RESET 0x5
4524
4525
#define ALT_NAND_PARAM_REVISION_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
4526
4527
#define ALT_NAND_PARAM_REVISION_VALUE_SET(value) (((value) << 0) & 0x000000ff)
4528
4538
#define ALT_NAND_PARAM_REVISION_MINOR_LSB 8
4539
4540
#define ALT_NAND_PARAM_REVISION_MINOR_MSB 15
4541
4542
#define ALT_NAND_PARAM_REVISION_MINOR_WIDTH 8
4543
4544
#define ALT_NAND_PARAM_REVISION_MINOR_SET_MSK 0x0000ff00
4545
4546
#define ALT_NAND_PARAM_REVISION_MINOR_CLR_MSK 0xffff00ff
4547
4548
#define ALT_NAND_PARAM_REVISION_MINOR_RESET 0x1
4549
4550
#define ALT_NAND_PARAM_REVISION_MINOR_GET(value) (((value) & 0x0000ff00) >> 8)
4551
4552
#define ALT_NAND_PARAM_REVISION_MINOR_SET(value) (((value) << 8) & 0x0000ff00)
4553
4554
#ifndef __ASSEMBLY__
4555
4565
struct
ALT_NAND_PARAM_REVISION_s
4566
{
4567
const
uint32_t
value
: 8;
4568
const
uint32_t
minor
: 8;
4569
uint32_t : 16;
4570
};
4571
4573
typedef
volatile
struct
ALT_NAND_PARAM_REVISION_s
ALT_NAND_PARAM_REVISION_t
;
4574
#endif
/* __ASSEMBLY__ */
4575
4577
#define ALT_NAND_PARAM_REVISION_RESET 0x00000105
4578
4579
#define ALT_NAND_PARAM_REVISION_OFST 0x70
4580
4631
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_LSB 0
4632
4633
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_MSB 15
4634
4635
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_WIDTH 16
4636
4637
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET_MSK 0x0000ffff
4638
4639
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_CLR_MSK 0xffff0000
4640
4641
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_RESET 0x0
4642
4643
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4644
4645
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4646
4647
#ifndef __ASSEMBLY__
4648
4658
struct
ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
4659
{
4660
const
uint32_t
value
: 16;
4661
uint32_t : 16;
4662
};
4663
4665
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_DEV_FEATURES_s
ALT_NAND_PARAM_ONFI_DEV_FEATURES_t
;
4666
#endif
/* __ASSEMBLY__ */
4667
4669
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_RESET 0x00000000
4670
4671
#define ALT_NAND_PARAM_ONFI_DEV_FEATURES_OFST 0x80
4672
4721
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_LSB 0
4722
4723
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_MSB 15
4724
4725
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_WIDTH 16
4726
4727
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET_MSK 0x0000ffff
4728
4729
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_CLR_MSK 0xffff0000
4730
4731
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_RESET 0x0
4732
4733
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
4734
4735
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
4736
4737
#ifndef __ASSEMBLY__
4738
4748
struct
ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
4749
{
4750
const
uint32_t
value
: 16;
4751
uint32_t : 16;
4752
};
4753
4755
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_s
ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t
;
4756
#endif
/* __ASSEMBLY__ */
4757
4759
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_RESET 0x00000000
4760
4761
#define ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_OFST 0x90
4762
4797
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB 0
4798
4799
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB 5
4800
4801
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH 6
4802
4803
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4804
4805
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4806
4807
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET 0x0
4808
4809
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4810
4811
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4812
4813
#ifndef __ASSEMBLY__
4814
4824
struct
ALT_NAND_PARAM_ONFI_TIMING_MOD_s
4825
{
4826
const
uint32_t
value
: 6;
4827
uint32_t : 26;
4828
};
4829
4831
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_TIMING_MOD_s
ALT_NAND_PARAM_ONFI_TIMING_MOD_t
;
4832
#endif
/* __ASSEMBLY__ */
4833
4835
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_RESET 0x00000000
4836
4837
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST 0xa0
4838
4873
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_LSB 0
4874
4875
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_MSB 5
4876
4877
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_WIDTH 6
4878
4879
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET_MSK 0x0000003f
4880
4881
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_CLR_MSK 0xffffffc0
4882
4883
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_RESET 0x0
4884
4885
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_GET(value) (((value) & 0x0000003f) >> 0)
4886
4887
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_VALUE_SET(value) (((value) << 0) & 0x0000003f)
4888
4889
#ifndef __ASSEMBLY__
4890
4900
struct
ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
4901
{
4902
const
uint32_t
value
: 6;
4903
uint32_t : 26;
4904
};
4905
4907
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_s
ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t
;
4908
#endif
/* __ASSEMBLY__ */
4909
4911
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_RESET 0x00000000
4912
4913
#define ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_OFST 0xb0
4914
4946
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_LSB 0
4947
4948
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_MSB 7
4949
4950
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_WIDTH 8
4951
4952
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET_MSK 0x000000ff
4953
4954
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_CLR_MSK 0xffffff00
4955
4956
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_RESET 0x0
4957
4958
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_GET(value) (((value) & 0x000000ff) >> 0)
4959
4960
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_NO_OF_LUNS_SET(value) (((value) << 0) & 0x000000ff)
4961
4975
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_LSB 8
4976
4977
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_MSB 8
4978
4979
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_WIDTH 1
4980
4981
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET_MSK 0x00000100
4982
4983
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_CLR_MSK 0xfffffeff
4984
4985
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_RESET 0x0
4986
4987
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_GET(value) (((value) & 0x00000100) >> 8)
4988
4989
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_DEVICE_SET(value) (((value) << 8) & 0x00000100)
4990
5008
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_LSB 12
5009
5010
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_MSB 12
5011
5012
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_WIDTH 1
5013
5014
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET_MSK 0x00001000
5015
5016
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_CLR_MSK 0xffffefff
5017
5018
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_RESET 0x0
5019
5020
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_GET(value) (((value) & 0x00001000) >> 12)
5021
5022
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_PROG_PAGE_REG_CLR_ENHANCEMENT_SET(value) (((value) << 12) & 0x00001000)
5023
5038
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_LSB 16
5039
5040
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_MSB 16
5041
5042
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_WIDTH 1
5043
5044
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET_MSK 0x00010000
5045
5046
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_CLR_MSK 0xfffeffff
5047
5048
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_RESET 0x0
5049
5050
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_GET(value) (((value) & 0x00010000) >> 16)
5051
5052
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_ONFI_JEDEC_MULTIPLANE_ERASE_SEQ_SET(value) (((value) << 16) & 0x00010000)
5053
5070
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_LSB 20
5071
5072
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_MSB 20
5073
5074
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_WIDTH 1
5075
5076
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET_MSK 0x00100000
5077
5078
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_CLR_MSK 0xffefffff
5079
5080
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_RESET 0x0
5081
5082
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_GET(value) (((value) & 0x00100000) >> 20)
5083
5084
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_CE_REDUCTION_VOLUME_ADDR_AND_CHANGE_SET(value) (((value) << 20) & 0x00100000)
5085
5086
#ifndef __ASSEMBLY__
5087
5097
struct
ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
5098
{
5099
const
uint32_t
no_of_luns
: 8;
5100
uint32_t
onfi_device
: 1;
5101
uint32_t : 3;
5102
uint32_t
prog_page_reg_clear_enhancement
: 1;
5103
uint32_t : 3;
5104
uint32_t
onfi_jedec_multiplane_erase_seq
: 1;
5105
uint32_t : 3;
5106
uint32_t
ce_reduction_volume_addr_and_change
: 1;
5107
uint32_t : 11;
5108
};
5109
5111
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_s
ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t
;
5112
#endif
/* __ASSEMBLY__ */
5113
5115
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_RESET 0x00000000
5116
5117
#define ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_OFST 0xc0
5118
5145
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_LSB 0
5146
5147
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_MSB 15
5148
5149
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_WIDTH 16
5150
5151
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET_MSK 0x0000ffff
5152
5153
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_CLR_MSK 0xffff0000
5154
5155
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_RESET 0x0
5156
5157
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5158
5159
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5160
5161
#ifndef __ASSEMBLY__
5162
5172
struct
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
5173
{
5174
const
uint32_t
value
: 16;
5175
uint32_t : 16;
5176
};
5177
5179
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_s
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t
;
5180
#endif
/* __ASSEMBLY__ */
5181
5183
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_RESET 0x00000000
5184
5185
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_OFST 0xd0
5186
5213
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_LSB 0
5214
5215
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_MSB 15
5216
5217
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_WIDTH 16
5218
5219
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET_MSK 0x0000ffff
5220
5221
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_CLR_MSK 0xffff0000
5222
5223
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_RESET 0x0
5224
5225
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
5226
5227
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
5228
5229
#ifndef __ASSEMBLY__
5230
5240
struct
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
5241
{
5242
const
uint32_t
value
: 16;
5243
uint32_t : 16;
5244
};
5245
5247
typedef
volatile
struct
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_s
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t
;
5248
#endif
/* __ASSEMBLY__ */
5249
5251
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_RESET 0x00000000
5252
5253
#define ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_OFST 0xe0
5254
5296
#define ALT_NAND_PARAM_FEATURES_N_BANKS_LSB 0
5297
5298
#define ALT_NAND_PARAM_FEATURES_N_BANKS_MSB 1
5299
5300
#define ALT_NAND_PARAM_FEATURES_N_BANKS_WIDTH 2
5301
5302
#define ALT_NAND_PARAM_FEATURES_N_BANKS_SET_MSK 0x00000003
5303
5304
#define ALT_NAND_PARAM_FEATURES_N_BANKS_CLR_MSK 0xfffffffc
5305
5306
#define ALT_NAND_PARAM_FEATURES_N_BANKS_RESET 0x2
5307
5308
#define ALT_NAND_PARAM_FEATURES_N_BANKS_GET(value) (((value) & 0x00000003) >> 0)
5309
5310
#define ALT_NAND_PARAM_FEATURES_N_BANKS_SET(value) (((value) << 0) & 0x00000003)
5311
5321
#define ALT_NAND_PARAM_FEATURES_DMA_LSB 6
5322
5323
#define ALT_NAND_PARAM_FEATURES_DMA_MSB 6
5324
5325
#define ALT_NAND_PARAM_FEATURES_DMA_WIDTH 1
5326
5327
#define ALT_NAND_PARAM_FEATURES_DMA_SET_MSK 0x00000040
5328
5329
#define ALT_NAND_PARAM_FEATURES_DMA_CLR_MSK 0xffffffbf
5330
5331
#define ALT_NAND_PARAM_FEATURES_DMA_RESET 0x1
5332
5333
#define ALT_NAND_PARAM_FEATURES_DMA_GET(value) (((value) & 0x00000040) >> 6)
5334
5335
#define ALT_NAND_PARAM_FEATURES_DMA_SET(value) (((value) << 6) & 0x00000040)
5336
5346
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_LSB 7
5347
5348
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_MSB 7
5349
5350
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_WIDTH 1
5351
5352
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET_MSK 0x00000080
5353
5354
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_CLR_MSK 0xffffff7f
5355
5356
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_RESET 0x1
5357
5358
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_GET(value) (((value) & 0x00000080) >> 7)
5359
5360
#define ALT_NAND_PARAM_FEATURES_CMD_DMA_SET(value) (((value) << 7) & 0x00000080)
5361
5371
#define ALT_NAND_PARAM_FEATURES_PARTITION_LSB 8
5372
5373
#define ALT_NAND_PARAM_FEATURES_PARTITION_MSB 8
5374
5375
#define ALT_NAND_PARAM_FEATURES_PARTITION_WIDTH 1
5376
5377
#define ALT_NAND_PARAM_FEATURES_PARTITION_SET_MSK 0x00000100
5378
5379
#define ALT_NAND_PARAM_FEATURES_PARTITION_CLR_MSK 0xfffffeff
5380
5381
#define ALT_NAND_PARAM_FEATURES_PARTITION_RESET 0x0
5382
5383
#define ALT_NAND_PARAM_FEATURES_PARTITION_GET(value) (((value) & 0x00000100) >> 8)
5384
5385
#define ALT_NAND_PARAM_FEATURES_PARTITION_SET(value) (((value) << 8) & 0x00000100)
5386
5396
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_LSB 9
5397
5398
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_MSB 9
5399
5400
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_WIDTH 1
5401
5402
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET_MSK 0x00000200
5403
5404
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_CLR_MSK 0xfffffdff
5405
5406
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_RESET 0x0
5407
5408
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_GET(value) (((value) & 0x00000200) >> 9)
5409
5410
#define ALT_NAND_PARAM_FEATURES_XDMA_SIDEBAND_SET(value) (((value) << 9) & 0x00000200)
5411
5421
#define ALT_NAND_PARAM_FEATURES_GPREG_LSB 10
5422
5423
#define ALT_NAND_PARAM_FEATURES_GPREG_MSB 10
5424
5425
#define ALT_NAND_PARAM_FEATURES_GPREG_WIDTH 1
5426
5427
#define ALT_NAND_PARAM_FEATURES_GPREG_SET_MSK 0x00000400
5428
5429
#define ALT_NAND_PARAM_FEATURES_GPREG_CLR_MSK 0xfffffbff
5430
5431
#define ALT_NAND_PARAM_FEATURES_GPREG_RESET 0x0
5432
5433
#define ALT_NAND_PARAM_FEATURES_GPREG_GET(value) (((value) & 0x00000400) >> 10)
5434
5435
#define ALT_NAND_PARAM_FEATURES_GPREG_SET(value) (((value) << 10) & 0x00000400)
5436
5446
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_LSB 11
5447
5448
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_MSB 11
5449
5450
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_WIDTH 1
5451
5452
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET_MSK 0x00000800
5453
5454
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_CLR_MSK 0xfffff7ff
5455
5456
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_RESET 0x1
5457
5458
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_GET(value) (((value) & 0x00000800) >> 11)
5459
5460
#define ALT_NAND_PARAM_FEATURES_INDEX_ADDR_SET(value) (((value) << 11) & 0x00000800)
5461
5471
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_LSB 12
5472
5473
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_MSB 12
5474
5475
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_WIDTH 1
5476
5477
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET_MSK 0x00001000
5478
5479
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_CLR_MSK 0xffffefff
5480
5481
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_RESET 0x0
5482
5483
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_GET(value) (((value) & 0x00001000) >> 12)
5484
5485
#define ALT_NAND_PARAM_FEATURES_DFI_INTF_SET(value) (((value) << 12) & 0x00001000)
5486
5496
#define ALT_NAND_PARAM_FEATURES_LBA_LSB 13
5497
5498
#define ALT_NAND_PARAM_FEATURES_LBA_MSB 13
5499
5500
#define ALT_NAND_PARAM_FEATURES_LBA_WIDTH 1
5501
5502
#define ALT_NAND_PARAM_FEATURES_LBA_SET_MSK 0x00002000
5503
5504
#define ALT_NAND_PARAM_FEATURES_LBA_CLR_MSK 0xffffdfff
5505
5506
#define ALT_NAND_PARAM_FEATURES_LBA_RESET 0x0
5507
5508
#define ALT_NAND_PARAM_FEATURES_LBA_GET(value) (((value) & 0x00002000) >> 13)
5509
5510
#define ALT_NAND_PARAM_FEATURES_LBA_SET(value) (((value) << 13) & 0x00002000)
5511
5512
#ifndef __ASSEMBLY__
5513
5523
struct
ALT_NAND_PARAM_FEATURES_s
5524
{
5525
const
uint32_t
n_banks
: 2;
5526
uint32_t : 4;
5527
const
uint32_t
dma
: 1;
5528
const
uint32_t
cmd_dma
: 1;
5529
const
uint32_t
partition
: 1;
5530
const
uint32_t
xdma_sideband
: 1;
5531
const
uint32_t
gpreg
: 1;
5532
const
uint32_t
index_addr
: 1;
5533
const
uint32_t
dfi_intf
: 1;
5534
const
uint32_t
lba
: 1;
5535
uint32_t : 18;
5536
};
5537
5539
typedef
volatile
struct
ALT_NAND_PARAM_FEATURES_s
ALT_NAND_PARAM_FEATURES_t
;
5540
#endif
/* __ASSEMBLY__ */
5541
5543
#define ALT_NAND_PARAM_FEATURES_RESET 0x000008c2
5544
5545
#define ALT_NAND_PARAM_FEATURES_OFST 0xf0
5546
5547
#ifndef __ASSEMBLY__
5548
5558
struct
ALT_NAND_PARAM_s
5559
{
5560
volatile
ALT_NAND_PARAM_MANUFACTURER_ID_t
manufacturer_id
;
5561
volatile
uint32_t
_pad_0x4_0xf
[3];
5562
volatile
ALT_NAND_PARAM_DEVICE_ID_t
device_id
;
5563
volatile
uint32_t
_pad_0x14_0x1f
[3];
5564
volatile
ALT_NAND_PARAM_DEVICE_PARAM_0_t
device_param_0
;
5565
volatile
uint32_t
_pad_0x24_0x2f
[3];
5566
volatile
ALT_NAND_PARAM_DEVICE_PARAM_1_t
device_param_1
;
5567
volatile
uint32_t
_pad_0x34_0x3f
[3];
5568
volatile
ALT_NAND_PARAM_DEVICE_PARAM_2_t
device_param_2
;
5569
volatile
uint32_t
_pad_0x44_0x4f
[3];
5570
volatile
ALT_NAND_PARAM_LOGICAL_PAGE_DATA_SIZE_t
logical_page_data_size
;
5571
volatile
uint32_t
_pad_0x54_0x5f
[3];
5572
volatile
ALT_NAND_PARAM_LOGICAL_PAGE_SPARE_SIZE_t
logical_page_spare_size
;
5573
volatile
uint32_t
_pad_0x64_0x6f
[3];
5574
volatile
ALT_NAND_PARAM_REVISION_t
revision
;
5575
volatile
uint32_t
_pad_0x74_0x7f
[3];
5576
volatile
ALT_NAND_PARAM_ONFI_DEV_FEATURES_t
onfi_device_features
;
5577
volatile
uint32_t
_pad_0x84_0x8f
[3];
5578
volatile
ALT_NAND_PARAM_ONFI_OPTIONAL_CMDS_t
onfi_optional_commands
;
5579
volatile
uint32_t
_pad_0x94_0x9f
[3];
5580
volatile
ALT_NAND_PARAM_ONFI_TIMING_MOD_t
onfi_timing_mode
;
5581
volatile
uint32_t
_pad_0xa4_0xaf
[3];
5582
volatile
ALT_NAND_PARAM_ONFI_PGM_CACHE_TIMING_MOD_t
onfi_pgm_cache_timing_mode
;
5583
volatile
uint32_t
_pad_0xb4_0xbf
[3];
5584
volatile
ALT_NAND_PARAM_ONFI_DEV_NO_OF_LUNS_t
onfi_device_no_of_luns
;
5585
volatile
uint32_t
_pad_0xc4_0xcf
[3];
5586
volatile
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_L_t
onfi_device_no_of_blocks_per_lun_l
;
5587
volatile
uint32_t
_pad_0xd4_0xdf
[3];
5588
volatile
ALT_NAND_PARAM_ONFI_DEV_BLKS_PER_LUN_U_t
onfi_device_no_of_blocks_per_lun_u
;
5589
volatile
uint32_t
_pad_0xe4_0xef
[3];
5590
volatile
ALT_NAND_PARAM_FEATURES_t
features
;
5591
};
5592
5594
typedef
volatile
struct
ALT_NAND_PARAM_s
ALT_NAND_PARAM_t
;
5596
struct
ALT_NAND_PARAM_raw_s
5597
{
5598
volatile
uint32_t
manufacturer_id
;
5599
volatile
uint32_t
_pad_0x4_0xf
[3];
5600
volatile
uint32_t
device_id
;
5601
volatile
uint32_t
_pad_0x14_0x1f
[3];
5602
volatile
uint32_t
device_param_0
;
5603
volatile
uint32_t
_pad_0x24_0x2f
[3];
5604
volatile
uint32_t
device_param_1
;
5605
volatile
uint32_t
_pad_0x34_0x3f
[3];
5606
volatile
uint32_t
device_param_2
;
5607
volatile
uint32_t
_pad_0x44_0x4f
[3];
5608
volatile
uint32_t
logical_page_data_size
;
5609
volatile
uint32_t
_pad_0x54_0x5f
[3];
5610
volatile
uint32_t
logical_page_spare_size
;
5611
volatile
uint32_t
_pad_0x64_0x6f
[3];
5612
volatile
uint32_t
revision
;
5613
volatile
uint32_t
_pad_0x74_0x7f
[3];
5614
volatile
uint32_t
onfi_device_features
;
5615
volatile
uint32_t
_pad_0x84_0x8f
[3];
5616
volatile
uint32_t
onfi_optional_commands
;
5617
volatile
uint32_t
_pad_0x94_0x9f
[3];
5618
volatile
uint32_t
onfi_timing_mode
;
5619
volatile
uint32_t
_pad_0xa4_0xaf
[3];
5620
volatile
uint32_t
onfi_pgm_cache_timing_mode
;
5621
volatile
uint32_t
_pad_0xb4_0xbf
[3];
5622
volatile
uint32_t
onfi_device_no_of_luns
;
5623
volatile
uint32_t
_pad_0xc4_0xcf
[3];
5624
volatile
uint32_t
onfi_device_no_of_blocks_per_lun_l
;
5625
volatile
uint32_t
_pad_0xd4_0xdf
[3];
5626
volatile
uint32_t
onfi_device_no_of_blocks_per_lun_u
;
5627
volatile
uint32_t
_pad_0xe4_0xef
[3];
5628
volatile
uint32_t
features
;
5629
};
5630
5632
typedef
volatile
struct
ALT_NAND_PARAM_raw_s
ALT_NAND_PARAM_raw_t
;
5633
#endif
/* __ASSEMBLY__ */
5634
5668
#define ALT_NAND_STAT_TFR_MOD_VALUE0_LSB 0
5669
5670
#define ALT_NAND_STAT_TFR_MOD_VALUE0_MSB 1
5671
5672
#define ALT_NAND_STAT_TFR_MOD_VALUE0_WIDTH 2
5673
5674
#define ALT_NAND_STAT_TFR_MOD_VALUE0_SET_MSK 0x00000003
5675
5676
#define ALT_NAND_STAT_TFR_MOD_VALUE0_CLR_MSK 0xfffffffc
5677
5678
#define ALT_NAND_STAT_TFR_MOD_VALUE0_RESET 0x0
5679
5680
#define ALT_NAND_STAT_TFR_MOD_VALUE0_GET(value) (((value) & 0x00000003) >> 0)
5681
5682
#define ALT_NAND_STAT_TFR_MOD_VALUE0_SET(value) (((value) << 0) & 0x00000003)
5683
5694
#define ALT_NAND_STAT_TFR_MOD_VALUE1_LSB 2
5695
5696
#define ALT_NAND_STAT_TFR_MOD_VALUE1_MSB 3
5697
5698
#define ALT_NAND_STAT_TFR_MOD_VALUE1_WIDTH 2
5699
5700
#define ALT_NAND_STAT_TFR_MOD_VALUE1_SET_MSK 0x0000000c
5701
5702
#define ALT_NAND_STAT_TFR_MOD_VALUE1_CLR_MSK 0xfffffff3
5703
5704
#define ALT_NAND_STAT_TFR_MOD_VALUE1_RESET 0x0
5705
5706
#define ALT_NAND_STAT_TFR_MOD_VALUE1_GET(value) (((value) & 0x0000000c) >> 2)
5707
5708
#define ALT_NAND_STAT_TFR_MOD_VALUE1_SET(value) (((value) << 2) & 0x0000000c)
5709
5720
#define ALT_NAND_STAT_TFR_MOD_VALUE2_LSB 4
5721
5722
#define ALT_NAND_STAT_TFR_MOD_VALUE2_MSB 5
5723
5724
#define ALT_NAND_STAT_TFR_MOD_VALUE2_WIDTH 2
5725
5726
#define ALT_NAND_STAT_TFR_MOD_VALUE2_SET_MSK 0x00000030
5727
5728
#define ALT_NAND_STAT_TFR_MOD_VALUE2_CLR_MSK 0xffffffcf
5729
5730
#define ALT_NAND_STAT_TFR_MOD_VALUE2_RESET 0x0
5731
5732
#define ALT_NAND_STAT_TFR_MOD_VALUE2_GET(value) (((value) & 0x00000030) >> 4)
5733
5734
#define ALT_NAND_STAT_TFR_MOD_VALUE2_SET(value) (((value) << 4) & 0x00000030)
5735
5746
#define ALT_NAND_STAT_TFR_MOD_VALUE3_LSB 6
5747
5748
#define ALT_NAND_STAT_TFR_MOD_VALUE3_MSB 7
5749
5750
#define ALT_NAND_STAT_TFR_MOD_VALUE3_WIDTH 2
5751
5752
#define ALT_NAND_STAT_TFR_MOD_VALUE3_SET_MSK 0x000000c0
5753
5754
#define ALT_NAND_STAT_TFR_MOD_VALUE3_CLR_MSK 0xffffff3f
5755
5756
#define ALT_NAND_STAT_TFR_MOD_VALUE3_RESET 0x0
5757
5758
#define ALT_NAND_STAT_TFR_MOD_VALUE3_GET(value) (((value) & 0x000000c0) >> 6)
5759
5760
#define ALT_NAND_STAT_TFR_MOD_VALUE3_SET(value) (((value) << 6) & 0x000000c0)
5761
5762
#ifndef __ASSEMBLY__
5763
5773
struct
ALT_NAND_STAT_TFR_MOD_s
5774
{
5775
const
uint32_t
value0
: 2;
5776
const
uint32_t
value1
: 2;
5777
const
uint32_t
value2
: 2;
5778
const
uint32_t
value3
: 2;
5779
uint32_t : 24;
5780
};
5781
5783
typedef
volatile
struct
ALT_NAND_STAT_TFR_MOD_s
ALT_NAND_STAT_TFR_MOD_t
;
5784
#endif
/* __ASSEMBLY__ */
5785
5787
#define ALT_NAND_STAT_TFR_MOD_RESET 0x00000000
5788
5789
#define ALT_NAND_STAT_TFR_MOD_OFST 0x0
5790
5829
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_LSB 0
5830
5831
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_MSB 0
5832
5833
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_WIDTH 1
5834
5835
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET_MSK 0x00000001
5836
5837
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
5838
5839
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_RESET 0x0
5840
5841
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
5842
5843
#define ALT_NAND_STAT_INTR_STAT0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
5844
5854
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_LSB 2
5855
5856
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_MSB 2
5857
5858
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_WIDTH 1
5859
5860
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET_MSK 0x00000004
5861
5862
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
5863
5864
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_RESET 0x0
5865
5866
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
5867
5868
#define ALT_NAND_STAT_INTR_STAT0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
5869
5882
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_LSB 3
5883
5884
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_MSB 3
5885
5886
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_WIDTH 1
5887
5888
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET_MSK 0x00000008
5889
5890
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_CLR_MSK 0xfffffff7
5891
5892
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_RESET 0x0
5893
5894
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
5895
5896
#define ALT_NAND_STAT_INTR_STAT0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
5897
5911
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_LSB 4
5912
5913
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_MSB 4
5914
5915
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_WIDTH 1
5916
5917
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET_MSK 0x00000010
5918
5919
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_CLR_MSK 0xffffffef
5920
5921
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_RESET 0x0
5922
5923
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
5924
5925
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
5926
5940
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_LSB 5
5941
5942
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_MSB 5
5943
5944
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_WIDTH 1
5945
5946
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET_MSK 0x00000020
5947
5948
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_CLR_MSK 0xffffffdf
5949
5950
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_RESET 0x0
5951
5952
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
5953
5954
#define ALT_NAND_STAT_INTR_STAT0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
5955
5965
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_LSB 6
5966
5967
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_MSB 6
5968
5969
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_WIDTH 1
5970
5971
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET_MSK 0x00000040
5972
5973
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_CLR_MSK 0xffffffbf
5974
5975
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_RESET 0x0
5976
5977
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
5978
5979
#define ALT_NAND_STAT_INTR_STAT0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
5980
5990
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_LSB 7
5991
5992
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_MSB 7
5993
5994
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_WIDTH 1
5995
5996
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET_MSK 0x00000080
5997
5998
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_CLR_MSK 0xffffff7f
5999
6000
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_RESET 0x0
6001
6002
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6003
6004
#define ALT_NAND_STAT_INTR_STAT0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6005
6015
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_LSB 8
6016
6017
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_MSB 8
6018
6019
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_WIDTH 1
6020
6021
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET_MSK 0x00000100
6022
6023
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_CLR_MSK 0xfffffeff
6024
6025
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_RESET 0x0
6026
6027
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6028
6029
#define ALT_NAND_STAT_INTR_STAT0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6030
6041
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_LSB 9
6042
6043
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_MSB 9
6044
6045
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6046
6047
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6048
6049
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6050
6051
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6052
6053
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6054
6055
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6056
6069
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_LSB 10
6070
6071
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_MSB 10
6072
6073
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_WIDTH 1
6074
6075
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET_MSK 0x00000400
6076
6077
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_CLR_MSK 0xfffffbff
6078
6079
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_RESET 0x0
6080
6081
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6082
6083
#define ALT_NAND_STAT_INTR_STAT0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6084
6097
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_LSB 11
6098
6099
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_MSB 11
6100
6101
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_WIDTH 1
6102
6103
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET_MSK 0x00000800
6104
6105
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6106
6107
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_RESET 0x0
6108
6109
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6110
6111
#define ALT_NAND_STAT_INTR_STAT0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6112
6122
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_LSB 12
6123
6124
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_MSB 12
6125
6126
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_WIDTH 1
6127
6128
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET_MSK 0x00001000
6129
6130
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_CLR_MSK 0xffffefff
6131
6132
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_RESET 0x0
6133
6134
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6135
6136
#define ALT_NAND_STAT_INTR_STAT0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6137
6147
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_LSB 13
6148
6149
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_MSB 13
6150
6151
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_WIDTH 1
6152
6153
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET_MSK 0x00002000
6154
6155
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_CLR_MSK 0xffffdfff
6156
6157
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_RESET 0x0
6158
6159
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6160
6161
#define ALT_NAND_STAT_INTR_STAT0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6162
6178
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_LSB 14
6179
6180
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_MSB 14
6181
6182
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_WIDTH 1
6183
6184
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET_MSK 0x00004000
6185
6186
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6187
6188
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_RESET 0x0
6189
6190
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6191
6192
#define ALT_NAND_STAT_INTR_STAT0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6193
6203
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_LSB 15
6204
6205
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_MSB 15
6206
6207
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_WIDTH 1
6208
6209
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET_MSK 0x00008000
6210
6211
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6212
6213
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_RESET 0x0
6214
6215
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6216
6217
#define ALT_NAND_STAT_INTR_STAT0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6218
6250
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_LSB 16
6251
6252
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_MSB 16
6253
6254
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_WIDTH 1
6255
6256
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET_MSK 0x00010000
6257
6258
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_CLR_MSK 0xfffeffff
6259
6260
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_RESET 0x0
6261
6262
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6263
6264
#define ALT_NAND_STAT_INTR_STAT0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6265
6266
#ifndef __ASSEMBLY__
6267
6277
struct
ALT_NAND_STAT_INTR_STAT0_s
6278
{
6279
uint32_t
ecc_uncor_err
: 1;
6280
uint32_t : 1;
6281
uint32_t
dma_cmd_comp
: 1;
6282
uint32_t
time_out
: 1;
6283
uint32_t
program_fail
: 1;
6284
uint32_t
erase_fail
: 1;
6285
uint32_t
load_comp
: 1;
6286
uint32_t
program_comp
: 1;
6287
uint32_t
erase_comp
: 1;
6288
uint32_t
pipe_cpybck_cmd_comp
: 1;
6289
uint32_t
locked_blk
: 1;
6290
uint32_t
unsup_cmd
: 1;
6291
uint32_t
int_act
: 1;
6292
uint32_t
rst_comp
: 1;
6293
uint32_t
pipe_cmd_err
: 1;
6294
uint32_t
page_xfer_inc
: 1;
6295
uint32_t
erased_page
: 1;
6296
uint32_t : 15;
6297
};
6298
6300
typedef
volatile
struct
ALT_NAND_STAT_INTR_STAT0_s
ALT_NAND_STAT_INTR_STAT0_t
;
6301
#endif
/* __ASSEMBLY__ */
6302
6304
#define ALT_NAND_STAT_INTR_STAT0_RESET 0x00000000
6305
6306
#define ALT_NAND_STAT_INTR_STAT0_OFST 0x10
6307
6349
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_LSB 0
6350
6351
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_MSB 0
6352
6353
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_WIDTH 1
6354
6355
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET_MSK 0x00000001
6356
6357
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
6358
6359
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_RESET 0x0
6360
6361
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
6362
6363
#define ALT_NAND_STAT_INTR_EN0_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
6364
6374
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_LSB 2
6375
6376
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_MSB 2
6377
6378
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_WIDTH 1
6379
6380
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET_MSK 0x00000004
6381
6382
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_CLR_MSK 0xfffffffb
6383
6384
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_RESET 0x0
6385
6386
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
6387
6388
#define ALT_NAND_STAT_INTR_EN0_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
6389
6402
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_LSB 3
6403
6404
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_MSB 3
6405
6406
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_WIDTH 1
6407
6408
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET_MSK 0x00000008
6409
6410
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_CLR_MSK 0xfffffff7
6411
6412
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_RESET 0x0
6413
6414
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
6415
6416
#define ALT_NAND_STAT_INTR_EN0_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
6417
6431
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_LSB 4
6432
6433
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_MSB 4
6434
6435
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_WIDTH 1
6436
6437
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET_MSK 0x00000010
6438
6439
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_CLR_MSK 0xffffffef
6440
6441
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_RESET 0x0
6442
6443
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
6444
6445
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
6446
6460
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_LSB 5
6461
6462
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_MSB 5
6463
6464
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_WIDTH 1
6465
6466
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET_MSK 0x00000020
6467
6468
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_CLR_MSK 0xffffffdf
6469
6470
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_RESET 0x0
6471
6472
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
6473
6474
#define ALT_NAND_STAT_INTR_EN0_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
6475
6485
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_LSB 6
6486
6487
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_MSB 6
6488
6489
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_WIDTH 1
6490
6491
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET_MSK 0x00000040
6492
6493
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_CLR_MSK 0xffffffbf
6494
6495
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_RESET 0x0
6496
6497
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
6498
6499
#define ALT_NAND_STAT_INTR_EN0_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
6500
6510
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_LSB 7
6511
6512
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_MSB 7
6513
6514
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_WIDTH 1
6515
6516
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET_MSK 0x00000080
6517
6518
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_CLR_MSK 0xffffff7f
6519
6520
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_RESET 0x0
6521
6522
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
6523
6524
#define ALT_NAND_STAT_INTR_EN0_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
6525
6535
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_LSB 8
6536
6537
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_MSB 8
6538
6539
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_WIDTH 1
6540
6541
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET_MSK 0x00000100
6542
6543
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_CLR_MSK 0xfffffeff
6544
6545
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_RESET 0x0
6546
6547
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
6548
6549
#define ALT_NAND_STAT_INTR_EN0_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
6550
6561
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_LSB 9
6562
6563
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_MSB 9
6564
6565
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_WIDTH 1
6566
6567
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
6568
6569
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
6570
6571
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_RESET 0x0
6572
6573
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
6574
6575
#define ALT_NAND_STAT_INTR_EN0_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
6576
6589
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_LSB 10
6590
6591
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_MSB 10
6592
6593
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_WIDTH 1
6594
6595
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET_MSK 0x00000400
6596
6597
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_CLR_MSK 0xfffffbff
6598
6599
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_RESET 0x0
6600
6601
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
6602
6603
#define ALT_NAND_STAT_INTR_EN0_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
6604
6617
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_LSB 11
6618
6619
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_MSB 11
6620
6621
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_WIDTH 1
6622
6623
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET_MSK 0x00000800
6624
6625
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_CLR_MSK 0xfffff7ff
6626
6627
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_RESET 0x0
6628
6629
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
6630
6631
#define ALT_NAND_STAT_INTR_EN0_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
6632
6642
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_LSB 12
6643
6644
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_MSB 12
6645
6646
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_WIDTH 1
6647
6648
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET_MSK 0x00001000
6649
6650
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_CLR_MSK 0xffffefff
6651
6652
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_RESET 0x0
6653
6654
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
6655
6656
#define ALT_NAND_STAT_INTR_EN0_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
6657
6667
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_LSB 13
6668
6669
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_MSB 13
6670
6671
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_WIDTH 1
6672
6673
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET_MSK 0x00002000
6674
6675
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_CLR_MSK 0xffffdfff
6676
6677
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_RESET 0x1
6678
6679
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
6680
6681
#define ALT_NAND_STAT_INTR_EN0_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
6682
6698
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_LSB 14
6699
6700
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_MSB 14
6701
6702
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_WIDTH 1
6703
6704
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET_MSK 0x00004000
6705
6706
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
6707
6708
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_RESET 0x0
6709
6710
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
6711
6712
#define ALT_NAND_STAT_INTR_EN0_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
6713
6723
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_LSB 15
6724
6725
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_MSB 15
6726
6727
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_WIDTH 1
6728
6729
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET_MSK 0x00008000
6730
6731
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_CLR_MSK 0xffff7fff
6732
6733
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_RESET 0x0
6734
6735
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
6736
6737
#define ALT_NAND_STAT_INTR_EN0_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
6738
6770
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_LSB 16
6771
6772
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_MSB 16
6773
6774
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_WIDTH 1
6775
6776
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET_MSK 0x00010000
6777
6778
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_CLR_MSK 0xfffeffff
6779
6780
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_RESET 0x0
6781
6782
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
6783
6784
#define ALT_NAND_STAT_INTR_EN0_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
6785
6786
#ifndef __ASSEMBLY__
6787
6797
struct
ALT_NAND_STAT_INTR_EN0_s
6798
{
6799
uint32_t
ecc_uncor_err
: 1;
6800
uint32_t : 1;
6801
uint32_t
dma_cmd_comp
: 1;
6802
uint32_t
time_out
: 1;
6803
uint32_t
program_fail
: 1;
6804
uint32_t
erase_fail
: 1;
6805
uint32_t
load_comp
: 1;
6806
uint32_t
program_comp
: 1;
6807
uint32_t
erase_comp
: 1;
6808
uint32_t
pipe_cpybck_cmd_comp
: 1;
6809
uint32_t
locked_blk
: 1;
6810
uint32_t
unsup_cmd
: 1;
6811
uint32_t
int_act
: 1;
6812
uint32_t
rst_comp
: 1;
6813
uint32_t
pipe_cmd_err
: 1;
6814
uint32_t
page_xfer_inc
: 1;
6815
uint32_t
erased_page
: 1;
6816
uint32_t : 15;
6817
};
6818
6820
typedef
volatile
struct
ALT_NAND_STAT_INTR_EN0_s
ALT_NAND_STAT_INTR_EN0_t
;
6821
#endif
/* __ASSEMBLY__ */
6822
6824
#define ALT_NAND_STAT_INTR_EN0_RESET 0x00002000
6825
6826
#define ALT_NAND_STAT_INTR_EN0_OFST 0x20
6827
6852
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_LSB 0
6853
6854
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_MSB 7
6855
6856
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_WIDTH 8
6857
6858
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET_MSK 0x000000ff
6859
6860
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_CLR_MSK 0xffffff00
6861
6862
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_RESET 0x0
6863
6864
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
6865
6866
#define ALT_NAND_STAT_PAGE_CNT0_VALUE_SET(value) (((value) << 0) & 0x000000ff)
6867
6868
#ifndef __ASSEMBLY__
6869
6879
struct
ALT_NAND_STAT_PAGE_CNT0_s
6880
{
6881
const
uint32_t
value
: 8;
6882
uint32_t : 24;
6883
};
6884
6886
typedef
volatile
struct
ALT_NAND_STAT_PAGE_CNT0_s
ALT_NAND_STAT_PAGE_CNT0_t
;
6887
#endif
/* __ASSEMBLY__ */
6888
6890
#define ALT_NAND_STAT_PAGE_CNT0_RESET 0x00000000
6891
6892
#define ALT_NAND_STAT_PAGE_CNT0_OFST 0x30
6893
6918
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_LSB 0
6919
6920
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_MSB 15
6921
6922
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_WIDTH 16
6923
6924
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET_MSK 0x0000ffff
6925
6926
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_CLR_MSK 0xffff0000
6927
6928
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_RESET 0x0
6929
6930
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6931
6932
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6933
6934
#ifndef __ASSEMBLY__
6935
6945
struct
ALT_NAND_STAT_ERR_PAGE_ADDR0_s
6946
{
6947
const
uint32_t
value
: 16;
6948
uint32_t : 16;
6949
};
6950
6952
typedef
volatile
struct
ALT_NAND_STAT_ERR_PAGE_ADDR0_s
ALT_NAND_STAT_ERR_PAGE_ADDR0_t
;
6953
#endif
/* __ASSEMBLY__ */
6954
6956
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_RESET 0x00000000
6957
6958
#define ALT_NAND_STAT_ERR_PAGE_ADDR0_OFST 0x40
6959
6984
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_LSB 0
6985
6986
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_MSB 15
6987
6988
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_WIDTH 16
6989
6990
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET_MSK 0x0000ffff
6991
6992
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_CLR_MSK 0xffff0000
6993
6994
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_RESET 0x0
6995
6996
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
6997
6998
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
6999
7000
#ifndef __ASSEMBLY__
7001
7011
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
7012
{
7013
const
uint32_t
value
: 16;
7014
uint32_t : 16;
7015
};
7016
7018
typedef
volatile
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR0_s
ALT_NAND_STAT_ERR_BLOCK_ADDR0_t
;
7019
#endif
/* __ASSEMBLY__ */
7020
7022
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_RESET 0x00000000
7023
7024
#define ALT_NAND_STAT_ERR_BLOCK_ADDR0_OFST 0x50
7025
7064
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_LSB 0
7065
7066
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_MSB 0
7067
7068
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_WIDTH 1
7069
7070
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7071
7072
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7073
7074
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_RESET 0x0
7075
7076
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7077
7078
#define ALT_NAND_STAT_INTR_STAT1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7079
7089
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_LSB 2
7090
7091
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_MSB 2
7092
7093
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_WIDTH 1
7094
7095
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET_MSK 0x00000004
7096
7097
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7098
7099
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_RESET 0x0
7100
7101
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7102
7103
#define ALT_NAND_STAT_INTR_STAT1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7104
7117
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_LSB 3
7118
7119
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_MSB 3
7120
7121
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_WIDTH 1
7122
7123
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET_MSK 0x00000008
7124
7125
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_CLR_MSK 0xfffffff7
7126
7127
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_RESET 0x0
7128
7129
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7130
7131
#define ALT_NAND_STAT_INTR_STAT1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7132
7146
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_LSB 4
7147
7148
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_MSB 4
7149
7150
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_WIDTH 1
7151
7152
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET_MSK 0x00000010
7153
7154
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7155
7156
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_RESET 0x0
7157
7158
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7159
7160
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7161
7175
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_LSB 5
7176
7177
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_MSB 5
7178
7179
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_WIDTH 1
7180
7181
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET_MSK 0x00000020
7182
7183
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_CLR_MSK 0xffffffdf
7184
7185
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_RESET 0x0
7186
7187
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7188
7189
#define ALT_NAND_STAT_INTR_STAT1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7190
7200
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_LSB 6
7201
7202
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_MSB 6
7203
7204
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_WIDTH 1
7205
7206
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET_MSK 0x00000040
7207
7208
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_CLR_MSK 0xffffffbf
7209
7210
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_RESET 0x0
7211
7212
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7213
7214
#define ALT_NAND_STAT_INTR_STAT1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7215
7225
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_LSB 7
7226
7227
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_MSB 7
7228
7229
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_WIDTH 1
7230
7231
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET_MSK 0x00000080
7232
7233
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7234
7235
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_RESET 0x0
7236
7237
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7238
7239
#define ALT_NAND_STAT_INTR_STAT1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7240
7250
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_LSB 8
7251
7252
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_MSB 8
7253
7254
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_WIDTH 1
7255
7256
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET_MSK 0x00000100
7257
7258
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_CLR_MSK 0xfffffeff
7259
7260
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_RESET 0x0
7261
7262
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7263
7264
#define ALT_NAND_STAT_INTR_STAT1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7265
7276
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_LSB 9
7277
7278
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_MSB 9
7279
7280
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7281
7282
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7283
7284
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7285
7286
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7287
7288
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7289
7290
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7291
7304
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_LSB 10
7305
7306
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_MSB 10
7307
7308
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_WIDTH 1
7309
7310
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET_MSK 0x00000400
7311
7312
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_CLR_MSK 0xfffffbff
7313
7314
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_RESET 0x0
7315
7316
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7317
7318
#define ALT_NAND_STAT_INTR_STAT1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7319
7332
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_LSB 11
7333
7334
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_MSB 11
7335
7336
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_WIDTH 1
7337
7338
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET_MSK 0x00000800
7339
7340
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7341
7342
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_RESET 0x0
7343
7344
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7345
7346
#define ALT_NAND_STAT_INTR_STAT1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7347
7357
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_LSB 12
7358
7359
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_MSB 12
7360
7361
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_WIDTH 1
7362
7363
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET_MSK 0x00001000
7364
7365
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_CLR_MSK 0xffffefff
7366
7367
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_RESET 0x0
7368
7369
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7370
7371
#define ALT_NAND_STAT_INTR_STAT1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7372
7383
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_LSB 13
7384
7385
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_MSB 13
7386
7387
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_WIDTH 1
7388
7389
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET_MSK 0x00002000
7390
7391
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_CLR_MSK 0xffffdfff
7392
7393
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_RESET 0x0
7394
7395
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7396
7397
#define ALT_NAND_STAT_INTR_STAT1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7398
7414
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_LSB 14
7415
7416
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_MSB 14
7417
7418
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_WIDTH 1
7419
7420
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET_MSK 0x00004000
7421
7422
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7423
7424
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_RESET 0x0
7425
7426
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7427
7428
#define ALT_NAND_STAT_INTR_STAT1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7429
7439
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_LSB 15
7440
7441
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_MSB 15
7442
7443
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_WIDTH 1
7444
7445
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET_MSK 0x00008000
7446
7447
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7448
7449
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_RESET 0x0
7450
7451
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7452
7453
#define ALT_NAND_STAT_INTR_STAT1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7454
7486
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_LSB 16
7487
7488
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_MSB 16
7489
7490
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_WIDTH 1
7491
7492
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET_MSK 0x00010000
7493
7494
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_CLR_MSK 0xfffeffff
7495
7496
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_RESET 0x0
7497
7498
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
7499
7500
#define ALT_NAND_STAT_INTR_STAT1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
7501
7502
#ifndef __ASSEMBLY__
7503
7513
struct
ALT_NAND_STAT_INTR_STAT1_s
7514
{
7515
uint32_t
ecc_uncor_err
: 1;
7516
uint32_t : 1;
7517
uint32_t
dma_cmd_comp
: 1;
7518
uint32_t
time_out
: 1;
7519
uint32_t
program_fail
: 1;
7520
uint32_t
erase_fail
: 1;
7521
uint32_t
load_comp
: 1;
7522
uint32_t
program_comp
: 1;
7523
uint32_t
erase_comp
: 1;
7524
uint32_t
pipe_cpybck_cmd_comp
: 1;
7525
uint32_t
locked_blk
: 1;
7526
uint32_t
unsup_cmd
: 1;
7527
uint32_t
int_act
: 1;
7528
uint32_t
rst_comp
: 1;
7529
uint32_t
pipe_cmd_err
: 1;
7530
uint32_t
page_xfer_inc
: 1;
7531
uint32_t
erased_page
: 1;
7532
uint32_t : 15;
7533
};
7534
7536
typedef
volatile
struct
ALT_NAND_STAT_INTR_STAT1_s
ALT_NAND_STAT_INTR_STAT1_t
;
7537
#endif
/* __ASSEMBLY__ */
7538
7540
#define ALT_NAND_STAT_INTR_STAT1_RESET 0x00000000
7541
7542
#define ALT_NAND_STAT_INTR_STAT1_OFST 0x60
7543
7585
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_LSB 0
7586
7587
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_MSB 0
7588
7589
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_WIDTH 1
7590
7591
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET_MSK 0x00000001
7592
7593
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
7594
7595
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_RESET 0x0
7596
7597
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
7598
7599
#define ALT_NAND_STAT_INTR_EN1_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
7600
7610
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_LSB 2
7611
7612
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_MSB 2
7613
7614
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_WIDTH 1
7615
7616
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET_MSK 0x00000004
7617
7618
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_CLR_MSK 0xfffffffb
7619
7620
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_RESET 0x0
7621
7622
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
7623
7624
#define ALT_NAND_STAT_INTR_EN1_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
7625
7638
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_LSB 3
7639
7640
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_MSB 3
7641
7642
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_WIDTH 1
7643
7644
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET_MSK 0x00000008
7645
7646
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_CLR_MSK 0xfffffff7
7647
7648
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_RESET 0x0
7649
7650
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
7651
7652
#define ALT_NAND_STAT_INTR_EN1_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
7653
7667
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_LSB 4
7668
7669
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_MSB 4
7670
7671
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_WIDTH 1
7672
7673
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET_MSK 0x00000010
7674
7675
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_CLR_MSK 0xffffffef
7676
7677
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_RESET 0x0
7678
7679
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
7680
7681
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
7682
7696
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_LSB 5
7697
7698
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_MSB 5
7699
7700
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_WIDTH 1
7701
7702
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET_MSK 0x00000020
7703
7704
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_CLR_MSK 0xffffffdf
7705
7706
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_RESET 0x0
7707
7708
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
7709
7710
#define ALT_NAND_STAT_INTR_EN1_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
7711
7721
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_LSB 6
7722
7723
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_MSB 6
7724
7725
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_WIDTH 1
7726
7727
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET_MSK 0x00000040
7728
7729
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_CLR_MSK 0xffffffbf
7730
7731
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_RESET 0x0
7732
7733
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
7734
7735
#define ALT_NAND_STAT_INTR_EN1_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
7736
7746
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_LSB 7
7747
7748
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_MSB 7
7749
7750
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_WIDTH 1
7751
7752
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET_MSK 0x00000080
7753
7754
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_CLR_MSK 0xffffff7f
7755
7756
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_RESET 0x0
7757
7758
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
7759
7760
#define ALT_NAND_STAT_INTR_EN1_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
7761
7771
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_LSB 8
7772
7773
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_MSB 8
7774
7775
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_WIDTH 1
7776
7777
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET_MSK 0x00000100
7778
7779
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_CLR_MSK 0xfffffeff
7780
7781
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_RESET 0x0
7782
7783
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
7784
7785
#define ALT_NAND_STAT_INTR_EN1_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
7786
7797
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_LSB 9
7798
7799
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_MSB 9
7800
7801
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_WIDTH 1
7802
7803
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
7804
7805
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
7806
7807
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_RESET 0x0
7808
7809
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
7810
7811
#define ALT_NAND_STAT_INTR_EN1_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
7812
7825
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_LSB 10
7826
7827
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_MSB 10
7828
7829
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_WIDTH 1
7830
7831
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET_MSK 0x00000400
7832
7833
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_CLR_MSK 0xfffffbff
7834
7835
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_RESET 0x0
7836
7837
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
7838
7839
#define ALT_NAND_STAT_INTR_EN1_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
7840
7853
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_LSB 11
7854
7855
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_MSB 11
7856
7857
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_WIDTH 1
7858
7859
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET_MSK 0x00000800
7860
7861
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_CLR_MSK 0xfffff7ff
7862
7863
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_RESET 0x0
7864
7865
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
7866
7867
#define ALT_NAND_STAT_INTR_EN1_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
7868
7878
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_LSB 12
7879
7880
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_MSB 12
7881
7882
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_WIDTH 1
7883
7884
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET_MSK 0x00001000
7885
7886
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_CLR_MSK 0xffffefff
7887
7888
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_RESET 0x0
7889
7890
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
7891
7892
#define ALT_NAND_STAT_INTR_EN1_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
7893
7903
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_LSB 13
7904
7905
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_MSB 13
7906
7907
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_WIDTH 1
7908
7909
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET_MSK 0x00002000
7910
7911
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_CLR_MSK 0xffffdfff
7912
7913
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_RESET 0x1
7914
7915
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
7916
7917
#define ALT_NAND_STAT_INTR_EN1_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
7918
7934
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_LSB 14
7935
7936
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_MSB 14
7937
7938
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_WIDTH 1
7939
7940
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET_MSK 0x00004000
7941
7942
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
7943
7944
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_RESET 0x0
7945
7946
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
7947
7948
#define ALT_NAND_STAT_INTR_EN1_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
7949
7959
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_LSB 15
7960
7961
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_MSB 15
7962
7963
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_WIDTH 1
7964
7965
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET_MSK 0x00008000
7966
7967
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_CLR_MSK 0xffff7fff
7968
7969
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_RESET 0x0
7970
7971
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
7972
7973
#define ALT_NAND_STAT_INTR_EN1_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
7974
8006
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_LSB 16
8007
8008
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_MSB 16
8009
8010
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_WIDTH 1
8011
8012
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET_MSK 0x00010000
8013
8014
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_CLR_MSK 0xfffeffff
8015
8016
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_RESET 0x0
8017
8018
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8019
8020
#define ALT_NAND_STAT_INTR_EN1_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8021
8022
#ifndef __ASSEMBLY__
8023
8033
struct
ALT_NAND_STAT_INTR_EN1_s
8034
{
8035
uint32_t
ecc_uncor_err
: 1;
8036
uint32_t : 1;
8037
uint32_t
dma_cmd_comp
: 1;
8038
uint32_t
time_out
: 1;
8039
uint32_t
program_fail
: 1;
8040
uint32_t
erase_fail
: 1;
8041
uint32_t
load_comp
: 1;
8042
uint32_t
program_comp
: 1;
8043
uint32_t
erase_comp
: 1;
8044
uint32_t
pipe_cpybck_cmd_comp
: 1;
8045
uint32_t
locked_blk
: 1;
8046
uint32_t
unsup_cmd
: 1;
8047
uint32_t
int_act
: 1;
8048
uint32_t
rst_comp
: 1;
8049
uint32_t
pipe_cmd_err
: 1;
8050
uint32_t
page_xfer_inc
: 1;
8051
uint32_t
erased_page
: 1;
8052
uint32_t : 15;
8053
};
8054
8056
typedef
volatile
struct
ALT_NAND_STAT_INTR_EN1_s
ALT_NAND_STAT_INTR_EN1_t
;
8057
#endif
/* __ASSEMBLY__ */
8058
8060
#define ALT_NAND_STAT_INTR_EN1_RESET 0x00002000
8061
8062
#define ALT_NAND_STAT_INTR_EN1_OFST 0x70
8063
8088
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_LSB 0
8089
8090
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_MSB 7
8091
8092
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_WIDTH 8
8093
8094
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET_MSK 0x000000ff
8095
8096
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_CLR_MSK 0xffffff00
8097
8098
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_RESET 0x0
8099
8100
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
8101
8102
#define ALT_NAND_STAT_PAGE_CNT1_VALUE_SET(value) (((value) << 0) & 0x000000ff)
8103
8104
#ifndef __ASSEMBLY__
8105
8115
struct
ALT_NAND_STAT_PAGE_CNT1_s
8116
{
8117
const
uint32_t
value
: 8;
8118
uint32_t : 24;
8119
};
8120
8122
typedef
volatile
struct
ALT_NAND_STAT_PAGE_CNT1_s
ALT_NAND_STAT_PAGE_CNT1_t
;
8123
#endif
/* __ASSEMBLY__ */
8124
8126
#define ALT_NAND_STAT_PAGE_CNT1_RESET 0x00000000
8127
8128
#define ALT_NAND_STAT_PAGE_CNT1_OFST 0x80
8129
8154
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_LSB 0
8155
8156
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_MSB 15
8157
8158
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_WIDTH 16
8159
8160
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET_MSK 0x0000ffff
8161
8162
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_CLR_MSK 0xffff0000
8163
8164
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_RESET 0x0
8165
8166
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8167
8168
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8169
8170
#ifndef __ASSEMBLY__
8171
8181
struct
ALT_NAND_STAT_ERR_PAGE_ADDR1_s
8182
{
8183
const
uint32_t
value
: 16;
8184
uint32_t : 16;
8185
};
8186
8188
typedef
volatile
struct
ALT_NAND_STAT_ERR_PAGE_ADDR1_s
ALT_NAND_STAT_ERR_PAGE_ADDR1_t
;
8189
#endif
/* __ASSEMBLY__ */
8190
8192
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_RESET 0x00000000
8193
8194
#define ALT_NAND_STAT_ERR_PAGE_ADDR1_OFST 0x90
8195
8220
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_LSB 0
8221
8222
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_MSB 15
8223
8224
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_WIDTH 16
8225
8226
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET_MSK 0x0000ffff
8227
8228
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_CLR_MSK 0xffff0000
8229
8230
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_RESET 0x0
8231
8232
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
8233
8234
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
8235
8236
#ifndef __ASSEMBLY__
8237
8247
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
8248
{
8249
const
uint32_t
value
: 16;
8250
uint32_t : 16;
8251
};
8252
8254
typedef
volatile
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR1_s
ALT_NAND_STAT_ERR_BLOCK_ADDR1_t
;
8255
#endif
/* __ASSEMBLY__ */
8256
8258
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_RESET 0x00000000
8259
8260
#define ALT_NAND_STAT_ERR_BLOCK_ADDR1_OFST 0xa0
8261
8300
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_LSB 0
8301
8302
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_MSB 0
8303
8304
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_WIDTH 1
8305
8306
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8307
8308
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8309
8310
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_RESET 0x0
8311
8312
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8313
8314
#define ALT_NAND_STAT_INTR_STAT2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8315
8325
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_LSB 2
8326
8327
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_MSB 2
8328
8329
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_WIDTH 1
8330
8331
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET_MSK 0x00000004
8332
8333
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8334
8335
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_RESET 0x0
8336
8337
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8338
8339
#define ALT_NAND_STAT_INTR_STAT2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8340
8353
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_LSB 3
8354
8355
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_MSB 3
8356
8357
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_WIDTH 1
8358
8359
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET_MSK 0x00000008
8360
8361
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_CLR_MSK 0xfffffff7
8362
8363
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_RESET 0x0
8364
8365
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8366
8367
#define ALT_NAND_STAT_INTR_STAT2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8368
8382
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_LSB 4
8383
8384
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_MSB 4
8385
8386
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_WIDTH 1
8387
8388
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET_MSK 0x00000010
8389
8390
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8391
8392
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_RESET 0x0
8393
8394
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8395
8396
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8397
8411
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_LSB 5
8412
8413
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_MSB 5
8414
8415
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_WIDTH 1
8416
8417
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET_MSK 0x00000020
8418
8419
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_CLR_MSK 0xffffffdf
8420
8421
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_RESET 0x0
8422
8423
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8424
8425
#define ALT_NAND_STAT_INTR_STAT2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8426
8436
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_LSB 6
8437
8438
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_MSB 6
8439
8440
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_WIDTH 1
8441
8442
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET_MSK 0x00000040
8443
8444
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_CLR_MSK 0xffffffbf
8445
8446
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_RESET 0x0
8447
8448
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8449
8450
#define ALT_NAND_STAT_INTR_STAT2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8451
8461
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_LSB 7
8462
8463
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_MSB 7
8464
8465
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_WIDTH 1
8466
8467
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET_MSK 0x00000080
8468
8469
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8470
8471
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_RESET 0x0
8472
8473
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8474
8475
#define ALT_NAND_STAT_INTR_STAT2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8476
8486
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_LSB 8
8487
8488
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_MSB 8
8489
8490
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_WIDTH 1
8491
8492
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET_MSK 0x00000100
8493
8494
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_CLR_MSK 0xfffffeff
8495
8496
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_RESET 0x0
8497
8498
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
8499
8500
#define ALT_NAND_STAT_INTR_STAT2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
8501
8512
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_LSB 9
8513
8514
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_MSB 9
8515
8516
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
8517
8518
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
8519
8520
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
8521
8522
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
8523
8524
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
8525
8526
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
8527
8540
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_LSB 10
8541
8542
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_MSB 10
8543
8544
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_WIDTH 1
8545
8546
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET_MSK 0x00000400
8547
8548
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_CLR_MSK 0xfffffbff
8549
8550
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_RESET 0x0
8551
8552
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
8553
8554
#define ALT_NAND_STAT_INTR_STAT2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
8555
8568
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_LSB 11
8569
8570
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_MSB 11
8571
8572
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_WIDTH 1
8573
8574
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET_MSK 0x00000800
8575
8576
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_CLR_MSK 0xfffff7ff
8577
8578
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_RESET 0x0
8579
8580
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
8581
8582
#define ALT_NAND_STAT_INTR_STAT2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
8583
8593
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_LSB 12
8594
8595
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_MSB 12
8596
8597
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_WIDTH 1
8598
8599
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET_MSK 0x00001000
8600
8601
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_CLR_MSK 0xffffefff
8602
8603
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_RESET 0x0
8604
8605
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
8606
8607
#define ALT_NAND_STAT_INTR_STAT2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
8608
8619
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_LSB 13
8620
8621
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_MSB 13
8622
8623
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_WIDTH 1
8624
8625
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET_MSK 0x00002000
8626
8627
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_CLR_MSK 0xffffdfff
8628
8629
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_RESET 0x0
8630
8631
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
8632
8633
#define ALT_NAND_STAT_INTR_STAT2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
8634
8650
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_LSB 14
8651
8652
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_MSB 14
8653
8654
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_WIDTH 1
8655
8656
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET_MSK 0x00004000
8657
8658
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
8659
8660
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_RESET 0x0
8661
8662
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
8663
8664
#define ALT_NAND_STAT_INTR_STAT2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
8665
8675
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_LSB 15
8676
8677
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_MSB 15
8678
8679
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_WIDTH 1
8680
8681
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET_MSK 0x00008000
8682
8683
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
8684
8685
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_RESET 0x0
8686
8687
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
8688
8689
#define ALT_NAND_STAT_INTR_STAT2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
8690
8722
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_LSB 16
8723
8724
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_MSB 16
8725
8726
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_WIDTH 1
8727
8728
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET_MSK 0x00010000
8729
8730
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_CLR_MSK 0xfffeffff
8731
8732
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_RESET 0x0
8733
8734
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
8735
8736
#define ALT_NAND_STAT_INTR_STAT2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
8737
8738
#ifndef __ASSEMBLY__
8739
8749
struct
ALT_NAND_STAT_INTR_STAT2_s
8750
{
8751
uint32_t
ecc_uncor_err
: 1;
8752
uint32_t : 1;
8753
uint32_t
dma_cmd_comp
: 1;
8754
uint32_t
time_out
: 1;
8755
uint32_t
program_fail
: 1;
8756
uint32_t
erase_fail
: 1;
8757
uint32_t
load_comp
: 1;
8758
uint32_t
program_comp
: 1;
8759
uint32_t
erase_comp
: 1;
8760
uint32_t
pipe_cpybck_cmd_comp
: 1;
8761
uint32_t
locked_blk
: 1;
8762
uint32_t
unsup_cmd
: 1;
8763
uint32_t
int_act
: 1;
8764
uint32_t
rst_comp
: 1;
8765
uint32_t
pipe_cmd_err
: 1;
8766
uint32_t
page_xfer_inc
: 1;
8767
uint32_t
erased_page
: 1;
8768
uint32_t : 15;
8769
};
8770
8772
typedef
volatile
struct
ALT_NAND_STAT_INTR_STAT2_s
ALT_NAND_STAT_INTR_STAT2_t
;
8773
#endif
/* __ASSEMBLY__ */
8774
8776
#define ALT_NAND_STAT_INTR_STAT2_RESET 0x00000000
8777
8778
#define ALT_NAND_STAT_INTR_STAT2_OFST 0xb0
8779
8821
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_LSB 0
8822
8823
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_MSB 0
8824
8825
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_WIDTH 1
8826
8827
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET_MSK 0x00000001
8828
8829
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
8830
8831
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_RESET 0x0
8832
8833
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
8834
8835
#define ALT_NAND_STAT_INTR_EN2_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
8836
8846
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_LSB 2
8847
8848
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_MSB 2
8849
8850
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_WIDTH 1
8851
8852
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET_MSK 0x00000004
8853
8854
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_CLR_MSK 0xfffffffb
8855
8856
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_RESET 0x0
8857
8858
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
8859
8860
#define ALT_NAND_STAT_INTR_EN2_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
8861
8874
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_LSB 3
8875
8876
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_MSB 3
8877
8878
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_WIDTH 1
8879
8880
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET_MSK 0x00000008
8881
8882
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_CLR_MSK 0xfffffff7
8883
8884
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_RESET 0x0
8885
8886
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
8887
8888
#define ALT_NAND_STAT_INTR_EN2_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
8889
8903
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_LSB 4
8904
8905
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_MSB 4
8906
8907
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_WIDTH 1
8908
8909
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET_MSK 0x00000010
8910
8911
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_CLR_MSK 0xffffffef
8912
8913
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_RESET 0x0
8914
8915
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
8916
8917
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
8918
8932
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_LSB 5
8933
8934
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_MSB 5
8935
8936
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_WIDTH 1
8937
8938
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET_MSK 0x00000020
8939
8940
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_CLR_MSK 0xffffffdf
8941
8942
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_RESET 0x0
8943
8944
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
8945
8946
#define ALT_NAND_STAT_INTR_EN2_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
8947
8957
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_LSB 6
8958
8959
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_MSB 6
8960
8961
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_WIDTH 1
8962
8963
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET_MSK 0x00000040
8964
8965
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_CLR_MSK 0xffffffbf
8966
8967
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_RESET 0x0
8968
8969
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
8970
8971
#define ALT_NAND_STAT_INTR_EN2_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
8972
8982
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_LSB 7
8983
8984
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_MSB 7
8985
8986
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_WIDTH 1
8987
8988
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET_MSK 0x00000080
8989
8990
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_CLR_MSK 0xffffff7f
8991
8992
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_RESET 0x0
8993
8994
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
8995
8996
#define ALT_NAND_STAT_INTR_EN2_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
8997
9007
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_LSB 8
9008
9009
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_MSB 8
9010
9011
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_WIDTH 1
9012
9013
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET_MSK 0x00000100
9014
9015
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_CLR_MSK 0xfffffeff
9016
9017
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_RESET 0x0
9018
9019
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9020
9021
#define ALT_NAND_STAT_INTR_EN2_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9022
9033
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_LSB 9
9034
9035
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_MSB 9
9036
9037
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9038
9039
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9040
9041
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9042
9043
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9044
9045
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9046
9047
#define ALT_NAND_STAT_INTR_EN2_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9048
9061
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_LSB 10
9062
9063
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_MSB 10
9064
9065
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_WIDTH 1
9066
9067
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET_MSK 0x00000400
9068
9069
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_CLR_MSK 0xfffffbff
9070
9071
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_RESET 0x0
9072
9073
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9074
9075
#define ALT_NAND_STAT_INTR_EN2_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9076
9089
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_LSB 11
9090
9091
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_MSB 11
9092
9093
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_WIDTH 1
9094
9095
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET_MSK 0x00000800
9096
9097
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_CLR_MSK 0xfffff7ff
9098
9099
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_RESET 0x0
9100
9101
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9102
9103
#define ALT_NAND_STAT_INTR_EN2_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9104
9114
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_LSB 12
9115
9116
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_MSB 12
9117
9118
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_WIDTH 1
9119
9120
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET_MSK 0x00001000
9121
9122
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_CLR_MSK 0xffffefff
9123
9124
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_RESET 0x0
9125
9126
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9127
9128
#define ALT_NAND_STAT_INTR_EN2_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9129
9139
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_LSB 13
9140
9141
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_MSB 13
9142
9143
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_WIDTH 1
9144
9145
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET_MSK 0x00002000
9146
9147
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_CLR_MSK 0xffffdfff
9148
9149
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_RESET 0x1
9150
9151
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9152
9153
#define ALT_NAND_STAT_INTR_EN2_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9154
9170
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_LSB 14
9171
9172
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_MSB 14
9173
9174
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_WIDTH 1
9175
9176
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET_MSK 0x00004000
9177
9178
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9179
9180
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_RESET 0x0
9181
9182
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9183
9184
#define ALT_NAND_STAT_INTR_EN2_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9185
9195
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_LSB 15
9196
9197
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_MSB 15
9198
9199
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_WIDTH 1
9200
9201
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET_MSK 0x00008000
9202
9203
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9204
9205
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_RESET 0x0
9206
9207
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9208
9209
#define ALT_NAND_STAT_INTR_EN2_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9210
9242
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_LSB 16
9243
9244
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_MSB 16
9245
9246
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_WIDTH 1
9247
9248
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET_MSK 0x00010000
9249
9250
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_CLR_MSK 0xfffeffff
9251
9252
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_RESET 0x0
9253
9254
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9255
9256
#define ALT_NAND_STAT_INTR_EN2_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9257
9258
#ifndef __ASSEMBLY__
9259
9269
struct
ALT_NAND_STAT_INTR_EN2_s
9270
{
9271
uint32_t
ecc_uncor_err
: 1;
9272
uint32_t : 1;
9273
uint32_t
dma_cmd_comp
: 1;
9274
uint32_t
time_out
: 1;
9275
uint32_t
program_fail
: 1;
9276
uint32_t
erase_fail
: 1;
9277
uint32_t
load_comp
: 1;
9278
uint32_t
program_comp
: 1;
9279
uint32_t
erase_comp
: 1;
9280
uint32_t
pipe_cpybck_cmd_comp
: 1;
9281
uint32_t
locked_blk
: 1;
9282
uint32_t
unsup_cmd
: 1;
9283
uint32_t
int_act
: 1;
9284
uint32_t
rst_comp
: 1;
9285
uint32_t
pipe_cmd_err
: 1;
9286
uint32_t
page_xfer_inc
: 1;
9287
uint32_t
erased_page
: 1;
9288
uint32_t : 15;
9289
};
9290
9292
typedef
volatile
struct
ALT_NAND_STAT_INTR_EN2_s
ALT_NAND_STAT_INTR_EN2_t
;
9293
#endif
/* __ASSEMBLY__ */
9294
9296
#define ALT_NAND_STAT_INTR_EN2_RESET 0x00002000
9297
9298
#define ALT_NAND_STAT_INTR_EN2_OFST 0xc0
9299
9324
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_LSB 0
9325
9326
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_MSB 7
9327
9328
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_WIDTH 8
9329
9330
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET_MSK 0x000000ff
9331
9332
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_CLR_MSK 0xffffff00
9333
9334
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_RESET 0x0
9335
9336
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
9337
9338
#define ALT_NAND_STAT_PAGE_CNT2_VALUE_SET(value) (((value) << 0) & 0x000000ff)
9339
9340
#ifndef __ASSEMBLY__
9341
9351
struct
ALT_NAND_STAT_PAGE_CNT2_s
9352
{
9353
const
uint32_t
value
: 8;
9354
uint32_t : 24;
9355
};
9356
9358
typedef
volatile
struct
ALT_NAND_STAT_PAGE_CNT2_s
ALT_NAND_STAT_PAGE_CNT2_t
;
9359
#endif
/* __ASSEMBLY__ */
9360
9362
#define ALT_NAND_STAT_PAGE_CNT2_RESET 0x00000000
9363
9364
#define ALT_NAND_STAT_PAGE_CNT2_OFST 0xd0
9365
9390
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_LSB 0
9391
9392
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_MSB 15
9393
9394
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_WIDTH 16
9395
9396
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET_MSK 0x0000ffff
9397
9398
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_CLR_MSK 0xffff0000
9399
9400
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_RESET 0x0
9401
9402
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9403
9404
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9405
9406
#ifndef __ASSEMBLY__
9407
9417
struct
ALT_NAND_STAT_ERR_PAGE_ADDR2_s
9418
{
9419
const
uint32_t
value
: 16;
9420
uint32_t : 16;
9421
};
9422
9424
typedef
volatile
struct
ALT_NAND_STAT_ERR_PAGE_ADDR2_s
ALT_NAND_STAT_ERR_PAGE_ADDR2_t
;
9425
#endif
/* __ASSEMBLY__ */
9426
9428
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_RESET 0x00000000
9429
9430
#define ALT_NAND_STAT_ERR_PAGE_ADDR2_OFST 0xe0
9431
9456
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_LSB 0
9457
9458
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_MSB 15
9459
9460
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_WIDTH 16
9461
9462
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET_MSK 0x0000ffff
9463
9464
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_CLR_MSK 0xffff0000
9465
9466
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_RESET 0x0
9467
9468
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
9469
9470
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
9471
9472
#ifndef __ASSEMBLY__
9473
9483
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
9484
{
9485
const
uint32_t
value
: 16;
9486
uint32_t : 16;
9487
};
9488
9490
typedef
volatile
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR2_s
ALT_NAND_STAT_ERR_BLOCK_ADDR2_t
;
9491
#endif
/* __ASSEMBLY__ */
9492
9494
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_RESET 0x00000000
9495
9496
#define ALT_NAND_STAT_ERR_BLOCK_ADDR2_OFST 0xf0
9497
9536
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0
9537
9538
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0
9539
9540
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1
9541
9542
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001
9543
9544
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
9545
9546
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0
9547
9548
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
9549
9550
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
9551
9561
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2
9562
9563
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2
9564
9565
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1
9566
9567
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004
9568
9569
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
9570
9571
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0
9572
9573
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
9574
9575
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
9576
9589
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3
9590
9591
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3
9592
9593
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1
9594
9595
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008
9596
9597
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7
9598
9599
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0
9600
9601
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
9602
9603
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
9604
9618
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4
9619
9620
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4
9621
9622
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1
9623
9624
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010
9625
9626
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef
9627
9628
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0
9629
9630
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
9631
9632
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
9633
9647
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5
9648
9649
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5
9650
9651
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1
9652
9653
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020
9654
9655
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf
9656
9657
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0
9658
9659
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
9660
9661
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
9662
9672
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6
9673
9674
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6
9675
9676
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1
9677
9678
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040
9679
9680
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf
9681
9682
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0
9683
9684
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
9685
9686
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
9687
9697
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7
9698
9699
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7
9700
9701
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1
9702
9703
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080
9704
9705
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f
9706
9707
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0
9708
9709
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
9710
9711
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
9712
9722
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8
9723
9724
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8
9725
9726
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1
9727
9728
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100
9729
9730
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff
9731
9732
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0
9733
9734
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
9735
9736
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
9737
9748
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9
9749
9750
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9
9751
9752
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
9753
9754
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
9755
9756
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
9757
9758
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
9759
9760
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
9761
9762
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
9763
9776
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10
9777
9778
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10
9779
9780
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1
9781
9782
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400
9783
9784
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff
9785
9786
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0
9787
9788
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
9789
9790
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
9791
9804
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11
9805
9806
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11
9807
9808
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1
9809
9810
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800
9811
9812
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff
9813
9814
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0
9815
9816
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
9817
9818
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
9819
9829
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12
9830
9831
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12
9832
9833
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1
9834
9835
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000
9836
9837
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff
9838
9839
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0
9840
9841
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
9842
9843
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
9844
9855
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13
9856
9857
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13
9858
9859
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1
9860
9861
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000
9862
9863
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff
9864
9865
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0
9866
9867
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
9868
9869
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
9870
9886
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14
9887
9888
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14
9889
9890
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1
9891
9892
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000
9893
9894
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
9895
9896
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0
9897
9898
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
9899
9900
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
9901
9911
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15
9912
9913
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15
9914
9915
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1
9916
9917
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000
9918
9919
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
9920
9921
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0
9922
9923
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
9924
9925
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
9926
9958
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_LSB 16
9959
9960
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_MSB 16
9961
9962
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_WIDTH 1
9963
9964
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET_MSK 0x00010000
9965
9966
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_CLR_MSK 0xfffeffff
9967
9968
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_RESET 0x0
9969
9970
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
9971
9972
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
9973
9974
#ifndef __ASSEMBLY__
9975
9985
struct
ALT_NAND_STAT_INTR_STAT3_s
9986
{
9987
uint32_t
ecc_uncor_err
: 1;
9988
uint32_t : 1;
9989
uint32_t
dma_cmd_comp
: 1;
9990
uint32_t
time_out
: 1;
9991
uint32_t
program_fail
: 1;
9992
uint32_t
erase_fail
: 1;
9993
uint32_t
load_comp
: 1;
9994
uint32_t
program_comp
: 1;
9995
uint32_t
erase_comp
: 1;
9996
uint32_t
pipe_cpybck_cmd_comp
: 1;
9997
uint32_t
locked_blk
: 1;
9998
uint32_t
unsup_cmd
: 1;
9999
uint32_t
int_act
: 1;
10000
uint32_t
rst_comp
: 1;
10001
uint32_t
pipe_cmd_err
: 1;
10002
uint32_t
page_xfer_inc
: 1;
10003
uint32_t
erased_page
: 1;
10004
uint32_t : 15;
10005
};
10006
10008
typedef
volatile
struct
ALT_NAND_STAT_INTR_STAT3_s
ALT_NAND_STAT_INTR_STAT3_t
;
10009
#endif
/* __ASSEMBLY__ */
10010
10012
#define ALT_NAND_STAT_INTR_STAT3_RESET 0x00000000
10013
10014
#define ALT_NAND_STAT_INTR_STAT3_OFST 0x100
10015
10057
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_LSB 0
10058
10059
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_MSB 0
10060
10061
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_WIDTH 1
10062
10063
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET_MSK 0x00000001
10064
10065
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe
10066
10067
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_RESET 0x0
10068
10069
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0)
10070
10071
#define ALT_NAND_STAT_INTR_EN3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001)
10072
10082
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_LSB 2
10083
10084
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_MSB 2
10085
10086
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_WIDTH 1
10087
10088
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET_MSK 0x00000004
10089
10090
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_CLR_MSK 0xfffffffb
10091
10092
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_RESET 0x0
10093
10094
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2)
10095
10096
#define ALT_NAND_STAT_INTR_EN3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004)
10097
10110
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_LSB 3
10111
10112
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_MSB 3
10113
10114
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_WIDTH 1
10115
10116
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET_MSK 0x00000008
10117
10118
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_CLR_MSK 0xfffffff7
10119
10120
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_RESET 0x0
10121
10122
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3)
10123
10124
#define ALT_NAND_STAT_INTR_EN3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008)
10125
10139
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_LSB 4
10140
10141
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_MSB 4
10142
10143
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_WIDTH 1
10144
10145
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET_MSK 0x00000010
10146
10147
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_CLR_MSK 0xffffffef
10148
10149
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_RESET 0x0
10150
10151
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4)
10152
10153
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010)
10154
10168
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_LSB 5
10169
10170
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_MSB 5
10171
10172
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_WIDTH 1
10173
10174
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET_MSK 0x00000020
10175
10176
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_CLR_MSK 0xffffffdf
10177
10178
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_RESET 0x0
10179
10180
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5)
10181
10182
#define ALT_NAND_STAT_INTR_EN3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020)
10183
10193
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_LSB 6
10194
10195
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_MSB 6
10196
10197
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_WIDTH 1
10198
10199
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET_MSK 0x00000040
10200
10201
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_CLR_MSK 0xffffffbf
10202
10203
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_RESET 0x0
10204
10205
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6)
10206
10207
#define ALT_NAND_STAT_INTR_EN3_LD_COMP_SET(value) (((value) << 6) & 0x00000040)
10208
10218
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_LSB 7
10219
10220
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_MSB 7
10221
10222
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_WIDTH 1
10223
10224
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET_MSK 0x00000080
10225
10226
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_CLR_MSK 0xffffff7f
10227
10228
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_RESET 0x0
10229
10230
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7)
10231
10232
#define ALT_NAND_STAT_INTR_EN3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080)
10233
10243
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_LSB 8
10244
10245
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_MSB 8
10246
10247
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_WIDTH 1
10248
10249
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET_MSK 0x00000100
10250
10251
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_CLR_MSK 0xfffffeff
10252
10253
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_RESET 0x0
10254
10255
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8)
10256
10257
#define ALT_NAND_STAT_INTR_EN3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100)
10258
10269
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_LSB 9
10270
10271
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_MSB 9
10272
10273
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_WIDTH 1
10274
10275
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200
10276
10277
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff
10278
10279
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_RESET 0x0
10280
10281
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9)
10282
10283
#define ALT_NAND_STAT_INTR_EN3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200)
10284
10297
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_LSB 10
10298
10299
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_MSB 10
10300
10301
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_WIDTH 1
10302
10303
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET_MSK 0x00000400
10304
10305
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_CLR_MSK 0xfffffbff
10306
10307
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_RESET 0x0
10308
10309
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10)
10310
10311
#define ALT_NAND_STAT_INTR_EN3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400)
10312
10325
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_LSB 11
10326
10327
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_MSB 11
10328
10329
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_WIDTH 1
10330
10331
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET_MSK 0x00000800
10332
10333
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_CLR_MSK 0xfffff7ff
10334
10335
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_RESET 0x0
10336
10337
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11)
10338
10339
#define ALT_NAND_STAT_INTR_EN3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800)
10340
10350
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_LSB 12
10351
10352
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_MSB 12
10353
10354
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_WIDTH 1
10355
10356
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET_MSK 0x00001000
10357
10358
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_CLR_MSK 0xffffefff
10359
10360
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_RESET 0x0
10361
10362
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12)
10363
10364
#define ALT_NAND_STAT_INTR_EN3_INT_ACT_SET(value) (((value) << 12) & 0x00001000)
10365
10375
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_LSB 13
10376
10377
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_MSB 13
10378
10379
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_WIDTH 1
10380
10381
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET_MSK 0x00002000
10382
10383
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_CLR_MSK 0xffffdfff
10384
10385
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_RESET 0x1
10386
10387
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13)
10388
10389
#define ALT_NAND_STAT_INTR_EN3_RST_COMP_SET(value) (((value) << 13) & 0x00002000)
10390
10406
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_LSB 14
10407
10408
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_MSB 14
10409
10410
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_WIDTH 1
10411
10412
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET_MSK 0x00004000
10413
10414
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff
10415
10416
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_RESET 0x0
10417
10418
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14)
10419
10420
#define ALT_NAND_STAT_INTR_EN3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000)
10421
10431
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_LSB 15
10432
10433
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_MSB 15
10434
10435
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_WIDTH 1
10436
10437
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET_MSK 0x00008000
10438
10439
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_CLR_MSK 0xffff7fff
10440
10441
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_RESET 0x0
10442
10443
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15)
10444
10445
#define ALT_NAND_STAT_INTR_EN3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000)
10446
10478
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_LSB 16
10479
10480
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_MSB 16
10481
10482
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_WIDTH 1
10483
10484
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET_MSK 0x00010000
10485
10486
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_CLR_MSK 0xfffeffff
10487
10488
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_RESET 0x0
10489
10490
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16)
10491
10492
#define ALT_NAND_STAT_INTR_EN3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000)
10493
10494
#ifndef __ASSEMBLY__
10495
10505
struct
ALT_NAND_STAT_INTR_EN3_s
10506
{
10507
uint32_t
ecc_uncor_err
: 1;
10508
uint32_t : 1;
10509
uint32_t
dma_cmd_comp
: 1;
10510
uint32_t
time_out
: 1;
10511
uint32_t
program_fail
: 1;
10512
uint32_t
erase_fail
: 1;
10513
uint32_t
load_comp
: 1;
10514
uint32_t
program_comp
: 1;
10515
uint32_t
erase_comp
: 1;
10516
uint32_t
pipe_cpybck_cmd_comp
: 1;
10517
uint32_t
locked_blk
: 1;
10518
uint32_t
unsup_cmd
: 1;
10519
uint32_t
int_act
: 1;
10520
uint32_t
rst_comp
: 1;
10521
uint32_t
pipe_cmd_err
: 1;
10522
uint32_t
page_xfer_inc
: 1;
10523
uint32_t
erased_page
: 1;
10524
uint32_t : 15;
10525
};
10526
10528
typedef
volatile
struct
ALT_NAND_STAT_INTR_EN3_s
ALT_NAND_STAT_INTR_EN3_t
;
10529
#endif
/* __ASSEMBLY__ */
10530
10532
#define ALT_NAND_STAT_INTR_EN3_RESET 0x00002000
10533
10534
#define ALT_NAND_STAT_INTR_EN3_OFST 0x110
10535
10560
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_LSB 0
10561
10562
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_MSB 7
10563
10564
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_WIDTH 8
10565
10566
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET_MSK 0x000000ff
10567
10568
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_CLR_MSK 0xffffff00
10569
10570
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_RESET 0x0
10571
10572
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_GET(value) (((value) & 0x000000ff) >> 0)
10573
10574
#define ALT_NAND_STAT_PAGE_CNT3_VALUE_SET(value) (((value) << 0) & 0x000000ff)
10575
10576
#ifndef __ASSEMBLY__
10577
10587
struct
ALT_NAND_STAT_PAGE_CNT3_s
10588
{
10589
const
uint32_t
value
: 8;
10590
uint32_t : 24;
10591
};
10592
10594
typedef
volatile
struct
ALT_NAND_STAT_PAGE_CNT3_s
ALT_NAND_STAT_PAGE_CNT3_t
;
10595
#endif
/* __ASSEMBLY__ */
10596
10598
#define ALT_NAND_STAT_PAGE_CNT3_RESET 0x00000000
10599
10600
#define ALT_NAND_STAT_PAGE_CNT3_OFST 0x120
10601
10626
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_LSB 0
10627
10628
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_MSB 15
10629
10630
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_WIDTH 16
10631
10632
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET_MSK 0x0000ffff
10633
10634
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_CLR_MSK 0xffff0000
10635
10636
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_RESET 0x0
10637
10638
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10639
10640
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10641
10642
#ifndef __ASSEMBLY__
10643
10653
struct
ALT_NAND_STAT_ERR_PAGE_ADDR3_s
10654
{
10655
const
uint32_t
value
: 16;
10656
uint32_t : 16;
10657
};
10658
10660
typedef
volatile
struct
ALT_NAND_STAT_ERR_PAGE_ADDR3_s
ALT_NAND_STAT_ERR_PAGE_ADDR3_t
;
10661
#endif
/* __ASSEMBLY__ */
10662
10664
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_RESET 0x00000000
10665
10666
#define ALT_NAND_STAT_ERR_PAGE_ADDR3_OFST 0x130
10667
10692
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_LSB 0
10693
10694
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_MSB 15
10695
10696
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_WIDTH 16
10697
10698
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET_MSK 0x0000ffff
10699
10700
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_CLR_MSK 0xffff0000
10701
10702
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_RESET 0x0
10703
10704
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
10705
10706
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
10707
10708
#ifndef __ASSEMBLY__
10709
10719
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
10720
{
10721
const
uint32_t
value
: 16;
10722
uint32_t : 16;
10723
};
10724
10726
typedef
volatile
struct
ALT_NAND_STAT_ERR_BLOCK_ADDR3_s
ALT_NAND_STAT_ERR_BLOCK_ADDR3_t
;
10727
#endif
/* __ASSEMBLY__ */
10728
10730
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_RESET 0x00000000
10731
10732
#define ALT_NAND_STAT_ERR_BLOCK_ADDR3_OFST 0x140
10733
10734
#ifndef __ASSEMBLY__
10735
10745
struct
ALT_NAND_STAT_s
10746
{
10747
volatile
ALT_NAND_STAT_TFR_MOD_t
transfer_mode
;
10748
volatile
uint32_t
_pad_0x4_0xf
[3];
10749
volatile
ALT_NAND_STAT_INTR_STAT0_t
intr_status0
;
10750
volatile
uint32_t
_pad_0x14_0x1f
[3];
10751
volatile
ALT_NAND_STAT_INTR_EN0_t
intr_en0
;
10752
volatile
uint32_t
_pad_0x24_0x2f
[3];
10753
volatile
ALT_NAND_STAT_PAGE_CNT0_t
page_cnt0
;
10754
volatile
uint32_t
_pad_0x34_0x3f
[3];
10755
volatile
ALT_NAND_STAT_ERR_PAGE_ADDR0_t
err_page_addr0
;
10756
volatile
uint32_t
_pad_0x44_0x4f
[3];
10757
volatile
ALT_NAND_STAT_ERR_BLOCK_ADDR0_t
err_block_addr0
;
10758
volatile
uint32_t
_pad_0x54_0x5f
[3];
10759
volatile
ALT_NAND_STAT_INTR_STAT1_t
intr_status1
;
10760
volatile
uint32_t
_pad_0x64_0x6f
[3];
10761
volatile
ALT_NAND_STAT_INTR_EN1_t
intr_en1
;
10762
volatile
uint32_t
_pad_0x74_0x7f
[3];
10763
volatile
ALT_NAND_STAT_PAGE_CNT1_t
page_cnt1
;
10764
volatile
uint32_t
_pad_0x84_0x8f
[3];
10765
volatile
ALT_NAND_STAT_ERR_PAGE_ADDR1_t
err_page_addr1
;
10766
volatile
uint32_t
_pad_0x94_0x9f
[3];
10767
volatile
ALT_NAND_STAT_ERR_BLOCK_ADDR1_t
err_block_addr1
;
10768
volatile
uint32_t
_pad_0xa4_0xaf
[3];
10769
volatile
ALT_NAND_STAT_INTR_STAT2_t
intr_status2
;
10770
volatile
uint32_t
_pad_0xb4_0xbf
[3];
10771
volatile
ALT_NAND_STAT_INTR_EN2_t
intr_en2
;
10772
volatile
uint32_t
_pad_0xc4_0xcf
[3];
10773
volatile
ALT_NAND_STAT_PAGE_CNT2_t
page_cnt2
;
10774
volatile
uint32_t
_pad_0xd4_0xdf
[3];
10775
volatile
ALT_NAND_STAT_ERR_PAGE_ADDR2_t
err_page_addr2
;
10776
volatile
uint32_t
_pad_0xe4_0xef
[3];
10777
volatile
ALT_NAND_STAT_ERR_BLOCK_ADDR2_t
err_block_addr2
;
10778
volatile
uint32_t
_pad_0xf4_0xff
[3];
10779
volatile
ALT_NAND_STAT_INTR_STAT3_t
intr_status3
;
10780
volatile
uint32_t
_pad_0x104_0x10f
[3];
10781
volatile
ALT_NAND_STAT_INTR_EN3_t
intr_en3
;
10782
volatile
uint32_t
_pad_0x114_0x11f
[3];
10783
volatile
ALT_NAND_STAT_PAGE_CNT3_t
page_cnt3
;
10784
volatile
uint32_t
_pad_0x124_0x12f
[3];
10785
volatile
ALT_NAND_STAT_ERR_PAGE_ADDR3_t
err_page_addr3
;
10786
volatile
uint32_t
_pad_0x134_0x13f
[3];
10787
volatile
ALT_NAND_STAT_ERR_BLOCK_ADDR3_t
err_block_addr3
;
10788
};
10789
10791
typedef
volatile
struct
ALT_NAND_STAT_s
ALT_NAND_STAT_t
;
10793
struct
ALT_NAND_STAT_raw_s
10794
{
10795
volatile
uint32_t
transfer_mode
;
10796
volatile
uint32_t
_pad_0x4_0xf
[3];
10797
volatile
uint32_t
intr_status0
;
10798
volatile
uint32_t
_pad_0x14_0x1f
[3];
10799
volatile
uint32_t
intr_en0
;
10800
volatile
uint32_t
_pad_0x24_0x2f
[3];
10801
volatile
uint32_t
page_cnt0
;
10802
volatile
uint32_t
_pad_0x34_0x3f
[3];
10803
volatile
uint32_t
err_page_addr0
;
10804
volatile
uint32_t
_pad_0x44_0x4f
[3];
10805
volatile
uint32_t
err_block_addr0
;
10806
volatile
uint32_t
_pad_0x54_0x5f
[3];
10807
volatile
uint32_t
intr_status1
;
10808
volatile
uint32_t
_pad_0x64_0x6f
[3];
10809
volatile
uint32_t
intr_en1
;
10810
volatile
uint32_t
_pad_0x74_0x7f
[3];
10811
volatile
uint32_t
page_cnt1
;
10812
volatile
uint32_t
_pad_0x84_0x8f
[3];
10813
volatile
uint32_t
err_page_addr1
;
10814
volatile
uint32_t
_pad_0x94_0x9f
[3];
10815
volatile
uint32_t
err_block_addr1
;
10816
volatile
uint32_t
_pad_0xa4_0xaf
[3];
10817
volatile
uint32_t
intr_status2
;
10818
volatile
uint32_t
_pad_0xb4_0xbf
[3];
10819
volatile
uint32_t
intr_en2
;
10820
volatile
uint32_t
_pad_0xc4_0xcf
[3];
10821
volatile
uint32_t
page_cnt2
;
10822
volatile
uint32_t
_pad_0xd4_0xdf
[3];
10823
volatile
uint32_t
err_page_addr2
;
10824
volatile
uint32_t
_pad_0xe4_0xef
[3];
10825
volatile
uint32_t
err_block_addr2
;
10826
volatile
uint32_t
_pad_0xf4_0xff
[3];
10827
volatile
uint32_t
intr_status3
;
10828
volatile
uint32_t
_pad_0x104_0x10f
[3];
10829
volatile
uint32_t
intr_en3
;
10830
volatile
uint32_t
_pad_0x114_0x11f
[3];
10831
volatile
uint32_t
page_cnt3
;
10832
volatile
uint32_t
_pad_0x124_0x12f
[3];
10833
volatile
uint32_t
err_page_addr3
;
10834
volatile
uint32_t
_pad_0x134_0x13f
[3];
10835
volatile
uint32_t
err_block_addr3
;
10836
};
10837
10839
typedef
volatile
struct
ALT_NAND_STAT_raw_s
ALT_NAND_STAT_raw_t
;
10840
#endif
/* __ASSEMBLY__ */
10841
10882
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_LSB 0
10883
10884
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_MSB 6
10885
10886
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_WIDTH 7
10887
10888
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET_MSK 0x0000007f
10889
10890
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_CLR_MSK 0xffffff80
10891
10892
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_RESET 0x0
10893
10894
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_GET(value) (((value) & 0x0000007f) >> 0)
10895
10896
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B0_SET(value) (((value) << 0) & 0x0000007f)
10897
10910
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_LSB 7
10911
10912
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_MSB 7
10913
10914
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_WIDTH 1
10915
10916
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET_MSK 0x00000080
10917
10918
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_CLR_MSK 0xffffff7f
10919
10920
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_RESET 0x0
10921
10922
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_GET(value) (((value) & 0x00000080) >> 7)
10923
10924
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B0_SET(value) (((value) << 7) & 0x00000080)
10925
10941
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_LSB 8
10942
10943
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_MSB 14
10944
10945
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_WIDTH 7
10946
10947
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET_MSK 0x00007f00
10948
10949
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_CLR_MSK 0xffff80ff
10950
10951
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_RESET 0x0
10952
10953
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_GET(value) (((value) & 0x00007f00) >> 8)
10954
10955
#define ALT_NAND_ECC_ECCCORINFO_B01_MAX_ERRORS_B1_SET(value) (((value) << 8) & 0x00007f00)
10956
10969
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_LSB 15
10970
10971
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_MSB 15
10972
10973
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_WIDTH 1
10974
10975
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET_MSK 0x00008000
10976
10977
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_CLR_MSK 0xffff7fff
10978
10979
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_RESET 0x0
10980
10981
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_GET(value) (((value) & 0x00008000) >> 15)
10982
10983
#define ALT_NAND_ECC_ECCCORINFO_B01_UNCOR_ERR_B1_SET(value) (((value) << 15) & 0x00008000)
10984
10985
#ifndef __ASSEMBLY__
10986
10996
struct
ALT_NAND_ECC_ECCCORINFO_B01_s
10997
{
10998
const
uint32_t
max_errors_b0
: 7;
10999
const
uint32_t
uncor_err_b0
: 1;
11000
const
uint32_t
max_errors_b1
: 7;
11001
const
uint32_t
uncor_err_b1
: 1;
11002
uint32_t : 16;
11003
};
11004
11006
typedef
volatile
struct
ALT_NAND_ECC_ECCCORINFO_B01_s
ALT_NAND_ECC_ECCCORINFO_B01_t
;
11007
#endif
/* __ASSEMBLY__ */
11008
11010
#define ALT_NAND_ECC_ECCCORINFO_B01_RESET 0x00000000
11011
11012
#define ALT_NAND_ECC_ECCCORINFO_B01_OFST 0x0
11013
11049
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_LSB 0
11050
11051
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_MSB 6
11052
11053
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_WIDTH 7
11054
11055
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET_MSK 0x0000007f
11056
11057
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_CLR_MSK 0xffffff80
11058
11059
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_RESET 0x0
11060
11061
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_GET(value) (((value) & 0x0000007f) >> 0)
11062
11063
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B2_SET(value) (((value) << 0) & 0x0000007f)
11064
11077
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_LSB 7
11078
11079
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_MSB 7
11080
11081
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_WIDTH 1
11082
11083
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET_MSK 0x00000080
11084
11085
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_CLR_MSK 0xffffff7f
11086
11087
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_RESET 0x0
11088
11089
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_GET(value) (((value) & 0x00000080) >> 7)
11090
11091
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B2_SET(value) (((value) << 7) & 0x00000080)
11092
11108
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_LSB 8
11109
11110
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_MSB 14
11111
11112
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_WIDTH 7
11113
11114
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET_MSK 0x00007f00
11115
11116
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_CLR_MSK 0xffff80ff
11117
11118
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_RESET 0x0
11119
11120
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_GET(value) (((value) & 0x00007f00) >> 8)
11121
11122
#define ALT_NAND_ECC_ECCCORINFO_B23_MAX_ERRORS_B3_SET(value) (((value) << 8) & 0x00007f00)
11123
11136
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_LSB 15
11137
11138
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_MSB 15
11139
11140
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_WIDTH 1
11141
11142
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET_MSK 0x00008000
11143
11144
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_CLR_MSK 0xffff7fff
11145
11146
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_RESET 0x0
11147
11148
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_GET(value) (((value) & 0x00008000) >> 15)
11149
11150
#define ALT_NAND_ECC_ECCCORINFO_B23_UNCOR_ERR_B3_SET(value) (((value) << 15) & 0x00008000)
11151
11152
#ifndef __ASSEMBLY__
11153
11163
struct
ALT_NAND_ECC_ECCCORINFO_B23_s
11164
{
11165
const
uint32_t
max_errors_b2
: 7;
11166
const
uint32_t
uncor_err_b2
: 1;
11167
const
uint32_t
max_errors_b3
: 7;
11168
const
uint32_t
uncor_err_b3
: 1;
11169
uint32_t : 16;
11170
};
11171
11173
typedef
volatile
struct
ALT_NAND_ECC_ECCCORINFO_B23_s
ALT_NAND_ECC_ECCCORINFO_B23_t
;
11174
#endif
/* __ASSEMBLY__ */
11175
11177
#define ALT_NAND_ECC_ECCCORINFO_B23_RESET 0x00000000
11178
11179
#define ALT_NAND_ECC_ECCCORINFO_B23_OFST 0x10
11180
11181
#ifndef __ASSEMBLY__
11182
11192
struct
ALT_NAND_ECC_s
11193
{
11194
volatile
ALT_NAND_ECC_ECCCORINFO_B01_t
ecccorinfo_b01
;
11195
volatile
uint32_t
_pad_0x4_0xf
[3];
11196
volatile
ALT_NAND_ECC_ECCCORINFO_B23_t
ecccorinfo_b23
;
11197
};
11198
11200
typedef
volatile
struct
ALT_NAND_ECC_s
ALT_NAND_ECC_t
;
11202
struct
ALT_NAND_ECC_raw_s
11203
{
11204
volatile
uint32_t
ecccorinfo_b01
;
11205
volatile
uint32_t
_pad_0x4_0xf
[3];
11206
volatile
uint32_t
ecccorinfo_b23
;
11207
};
11208
11210
typedef
volatile
struct
ALT_NAND_ECC_raw_s
ALT_NAND_ECC_raw_t
;
11211
#endif
/* __ASSEMBLY__ */
11212
11240
#define ALT_NAND_DMA_DMA_EN_FLAG_LSB 0
11241
11242
#define ALT_NAND_DMA_DMA_EN_FLAG_MSB 0
11243
11244
#define ALT_NAND_DMA_DMA_EN_FLAG_WIDTH 1
11245
11246
#define ALT_NAND_DMA_DMA_EN_FLAG_SET_MSK 0x00000001
11247
11248
#define ALT_NAND_DMA_DMA_EN_FLAG_CLR_MSK 0xfffffffe
11249
11250
#define ALT_NAND_DMA_DMA_EN_FLAG_RESET 0x0
11251
11252
#define ALT_NAND_DMA_DMA_EN_FLAG_GET(value) (((value) & 0x00000001) >> 0)
11253
11254
#define ALT_NAND_DMA_DMA_EN_FLAG_SET(value) (((value) << 0) & 0x00000001)
11255
11256
#ifndef __ASSEMBLY__
11257
11267
struct
ALT_NAND_DMA_DMA_EN_s
11268
{
11269
uint32_t
flag
: 1;
11270
uint32_t : 31;
11271
};
11272
11274
typedef
volatile
struct
ALT_NAND_DMA_DMA_EN_s
ALT_NAND_DMA_DMA_EN_t
;
11275
#endif
/* __ASSEMBLY__ */
11276
11278
#define ALT_NAND_DMA_DMA_EN_RESET 0x00000000
11279
11280
#define ALT_NAND_DMA_DMA_EN_OFST 0x0
11281
11311
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_LSB 0
11312
11313
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_MSB 0
11314
11315
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_WIDTH 1
11316
11317
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET_MSK 0x00000001
11318
11319
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_CLR_MSK 0xfffffffe
11320
11321
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_RESET 0x0
11322
11323
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11324
11325
#define ALT_NAND_DMA_DMA_INTR_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11326
11337
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_LSB 1
11338
11339
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_MSB 1
11340
11341
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_WIDTH 1
11342
11343
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11344
11345
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11346
11347
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_RESET 0x0
11348
11349
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11350
11351
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11352
11363
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_LSB 2
11364
11365
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_MSB 2
11366
11367
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_WIDTH 1
11368
11369
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11370
11371
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11372
11373
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_RESET 0x0
11374
11375
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11376
11377
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11378
11389
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_LSB 3
11390
11391
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_MSB 3
11392
11393
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_WIDTH 1
11394
11395
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11396
11397
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11398
11399
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_RESET 0x0
11400
11401
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11402
11403
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11404
11415
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_LSB 4
11416
11417
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_MSB 4
11418
11419
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_WIDTH 1
11420
11421
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11422
11423
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11424
11425
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_RESET 0x0
11426
11427
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11428
11429
#define ALT_NAND_DMA_DMA_INTR_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11430
11440
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_LSB 6
11441
11442
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_MSB 6
11443
11444
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_WIDTH 1
11445
11446
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET_MSK 0x00000040
11447
11448
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11449
11450
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_RESET 0x0
11451
11452
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11453
11454
#define ALT_NAND_DMA_DMA_INTR_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11455
11456
#ifndef __ASSEMBLY__
11457
11467
struct
ALT_NAND_DMA_DMA_INTR_s
11468
{
11469
uint32_t
target_error
: 1;
11470
uint32_t
desc_comp_channel0
: 1;
11471
uint32_t
desc_comp_channel1
: 1;
11472
uint32_t
desc_comp_channel2
: 1;
11473
uint32_t
desc_comp_channel3
: 1;
11474
uint32_t : 1;
11475
uint32_t
cmddma_idle
: 1;
11476
uint32_t : 25;
11477
};
11478
11480
typedef
volatile
struct
ALT_NAND_DMA_DMA_INTR_s
ALT_NAND_DMA_DMA_INTR_t
;
11481
#endif
/* __ASSEMBLY__ */
11482
11484
#define ALT_NAND_DMA_DMA_INTR_RESET 0x00000000
11485
11486
#define ALT_NAND_DMA_DMA_INTR_OFST 0x20
11487
11517
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB 0
11518
11519
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB 0
11520
11521
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH 1
11522
11523
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK 0x00000001
11524
11525
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK 0xfffffffe
11526
11527
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET 0x0
11528
11529
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value) (((value) & 0x00000001) >> 0)
11530
11531
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value) (((value) << 0) & 0x00000001)
11532
11543
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB 1
11544
11545
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB 1
11546
11547
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH 1
11548
11549
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK 0x00000002
11550
11551
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK 0xfffffffd
11552
11553
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET 0x0
11554
11555
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value) (((value) & 0x00000002) >> 1)
11556
11557
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value) (((value) << 1) & 0x00000002)
11558
11569
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB 2
11570
11571
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB 2
11572
11573
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH 1
11574
11575
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK 0x00000004
11576
11577
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK 0xfffffffb
11578
11579
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET 0x0
11580
11581
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value) (((value) & 0x00000004) >> 2)
11582
11583
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value) (((value) << 2) & 0x00000004)
11584
11595
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB 3
11596
11597
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB 3
11598
11599
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH 1
11600
11601
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK 0x00000008
11602
11603
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK 0xfffffff7
11604
11605
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET 0x0
11606
11607
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value) (((value) & 0x00000008) >> 3)
11608
11609
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value) (((value) << 3) & 0x00000008)
11610
11621
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB 4
11622
11623
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB 4
11624
11625
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH 1
11626
11627
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK 0x00000010
11628
11629
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK 0xffffffef
11630
11631
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET 0x0
11632
11633
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value) (((value) & 0x00000010) >> 4)
11634
11635
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value) (((value) << 4) & 0x00000010)
11636
11648
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB 6
11649
11650
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB 6
11651
11652
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH 1
11653
11654
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK 0x00000040
11655
11656
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK 0xffffffbf
11657
11658
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET 0x0
11659
11660
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value) (((value) & 0x00000040) >> 6)
11661
11662
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value) (((value) << 6) & 0x00000040)
11663
11664
#ifndef __ASSEMBLY__
11665
11675
struct
ALT_NAND_DMA_DMA_INTR_EN_s
11676
{
11677
uint32_t
target_error
: 1;
11678
uint32_t
desc_comp_channel0
: 1;
11679
uint32_t
desc_comp_channel1
: 1;
11680
uint32_t
desc_comp_channel2
: 1;
11681
uint32_t
desc_comp_channel3
: 1;
11682
uint32_t : 1;
11683
uint32_t
cmddma_idle
: 1;
11684
uint32_t : 25;
11685
};
11686
11688
typedef
volatile
struct
ALT_NAND_DMA_DMA_INTR_EN_s
ALT_NAND_DMA_DMA_INTR_EN_t
;
11689
#endif
/* __ASSEMBLY__ */
11690
11692
#define ALT_NAND_DMA_DMA_INTR_EN_RESET 0x00000000
11693
11694
#define ALT_NAND_DMA_DMA_INTR_EN_OFST 0x30
11695
11719
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_LSB 0
11720
11721
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_MSB 15
11722
11723
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_WIDTH 16
11724
11725
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET_MSK 0x0000ffff
11726
11727
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_CLR_MSK 0xffff0000
11728
11729
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_RESET 0x0
11730
11731
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11732
11733
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11734
11735
#ifndef __ASSEMBLY__
11736
11746
struct
ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
11747
{
11748
const
uint32_t
value
: 16;
11749
uint32_t : 16;
11750
};
11751
11753
typedef
volatile
struct
ALT_NAND_DMA_TGT_ERR_ADDR_LO_s
ALT_NAND_DMA_TGT_ERR_ADDR_LO_t
;
11754
#endif
/* __ASSEMBLY__ */
11755
11757
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_RESET 0x00000000
11758
11759
#define ALT_NAND_DMA_TGT_ERR_ADDR_LO_OFST 0x40
11760
11784
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_LSB 0
11785
11786
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_MSB 15
11787
11788
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_WIDTH 16
11789
11790
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET_MSK 0x0000ffff
11791
11792
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_CLR_MSK 0xffff0000
11793
11794
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_RESET 0x0
11795
11796
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
11797
11798
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
11799
11800
#ifndef __ASSEMBLY__
11801
11811
struct
ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
11812
{
11813
const
uint32_t
value
: 16;
11814
uint32_t : 16;
11815
};
11816
11818
typedef
volatile
struct
ALT_NAND_DMA_TGT_ERR_ADDR_HI_s
ALT_NAND_DMA_TGT_ERR_ADDR_HI_t
;
11819
#endif
/* __ASSEMBLY__ */
11820
11822
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_RESET 0x00000000
11823
11824
#define ALT_NAND_DMA_TGT_ERR_ADDR_HI_OFST 0x50
11825
11851
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_LSB 0
11852
11853
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_MSB 0
11854
11855
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_WIDTH 1
11856
11857
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET_MSK 0x00000001
11858
11859
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_CLR_MSK 0xfffffffe
11860
11861
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_RESET 0x0
11862
11863
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
11864
11865
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
11866
11876
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_LSB 1
11877
11878
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_MSB 1
11879
11880
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_WIDTH 1
11881
11882
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET_MSK 0x00000002
11883
11884
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_CLR_MSK 0xfffffffd
11885
11886
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_RESET 0x0
11887
11888
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
11889
11890
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
11891
11901
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_LSB 2
11902
11903
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_MSB 2
11904
11905
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_WIDTH 1
11906
11907
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET_MSK 0x00000004
11908
11909
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_CLR_MSK 0xfffffffb
11910
11911
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_RESET 0x0
11912
11913
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
11914
11915
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
11916
11926
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_LSB 3
11927
11928
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_MSB 3
11929
11930
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_WIDTH 1
11931
11932
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET_MSK 0x00000008
11933
11934
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_CLR_MSK 0xfffffff7
11935
11936
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_RESET 0x0
11937
11938
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
11939
11940
#define ALT_NAND_DMA_CHNL_ACT_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
11941
11942
#ifndef __ASSEMBLY__
11943
11953
struct
ALT_NAND_DMA_CHNL_ACT_s
11954
{
11955
const
uint32_t
channel0
: 1;
11956
const
uint32_t
channel1
: 1;
11957
const
uint32_t
channel2
: 1;
11958
const
uint32_t
channel3
: 1;
11959
uint32_t : 28;
11960
};
11961
11963
typedef
volatile
struct
ALT_NAND_DMA_CHNL_ACT_s
ALT_NAND_DMA_CHNL_ACT_t
;
11964
#endif
/* __ASSEMBLY__ */
11965
11967
#define ALT_NAND_DMA_CHNL_ACT_RESET 0x00000000
11968
11969
#define ALT_NAND_DMA_CHNL_ACT_OFST 0x60
11970
12008
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_LSB 0
12009
12010
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_MSB 1
12011
12012
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_WIDTH 2
12013
12014
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET_MSK 0x00000003
12015
12016
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_CLR_MSK 0xfffffffc
12017
12018
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_RESET 0x1
12019
12020
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_GET(value) (((value) & 0x00000003) >> 0)
12021
12022
#define ALT_NAND_DMA_FLSH_BURST_LEN_VALUE_SET(value) (((value) << 0) & 0x00000003)
12023
12037
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_LSB 4
12038
12039
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_MSB 4
12040
12041
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_WIDTH 1
12042
12043
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET_MSK 0x00000010
12044
12045
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_CLR_MSK 0xffffffef
12046
12047
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_RESET 0x0
12048
12049
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_GET(value) (((value) & 0x00000010) >> 4)
12050
12051
#define ALT_NAND_DMA_FLSH_BURST_LEN_CONTINOUS_BURST_SET(value) (((value) << 4) & 0x00000010)
12052
12065
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_LSB 8
12066
12067
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_MSB 31
12068
12069
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_WIDTH 24
12070
12071
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET_MSK 0xffffff00
12072
12073
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_CLR_MSK 0x000000ff
12074
12075
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_RESET 0x0
12076
12077
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_GET(value) (((value) & 0xffffff00) >> 8)
12078
12079
#define ALT_NAND_DMA_FLSH_BURST_LEN_POLLING_SYNC_CNTR_VALUE_SET(value) (((value) << 8) & 0xffffff00)
12080
12081
#ifndef __ASSEMBLY__
12082
12092
struct
ALT_NAND_DMA_FLSH_BURST_LEN_s
12093
{
12094
uint32_t
value
: 2;
12095
uint32_t : 2;
12096
uint32_t
continous_burst
: 1;
12097
uint32_t : 3;
12098
uint32_t
polling_sync_counter_value
: 24;
12099
};
12100
12102
typedef
volatile
struct
ALT_NAND_DMA_FLSH_BURST_LEN_s
ALT_NAND_DMA_FLSH_BURST_LEN_t
;
12103
#endif
/* __ASSEMBLY__ */
12104
12106
#define ALT_NAND_DMA_FLSH_BURST_LEN_RESET 0x00000001
12107
12108
#define ALT_NAND_DMA_FLSH_BURST_LEN_OFST 0x70
12109
12138
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_LSB 0
12139
12140
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_MSB 0
12141
12142
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_WIDTH 1
12143
12144
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET_MSK 0x00000001
12145
12146
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_CLR_MSK 0xfffffffe
12147
12148
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_RESET 0x0
12149
12150
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_GET(value) (((value) & 0x00000001) >> 0)
12151
12152
#define ALT_NAND_DMA_INTRLV_CHIP_INTRLV_EN_SET(value) (((value) << 0) & 0x00000001)
12153
12178
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_LSB 4
12179
12180
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_MSB 4
12181
12182
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_WIDTH 1
12183
12184
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET_MSK 0x00000010
12185
12186
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_CLR_MSK 0xffffffef
12187
12188
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_RESET 0x1
12189
12190
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_GET(value) (((value) & 0x00000010) >> 4)
12191
12192
#define ALT_NAND_DMA_INTRLV_ALLOW_INT_RDS_WITHIN_LUNS_SET(value) (((value) << 4) & 0x00000010)
12193
12217
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_LSB 8
12218
12219
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_MSB 8
12220
12221
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_WIDTH 1
12222
12223
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET_MSK 0x00000100
12224
12225
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_CLR_MSK 0xfffffeff
12226
12227
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_RESET 0x1
12228
12229
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_GET(value) (((value) & 0x00000100) >> 8)
12230
12231
#define ALT_NAND_DMA_INTRLV_CMD_DMA_ERROR_EN_SET(value) (((value) << 8) & 0x00000100)
12232
12233
#ifndef __ASSEMBLY__
12234
12244
struct
ALT_NAND_DMA_INTRLV_s
12245
{
12246
uint32_t
chip_interleave_enable
: 1;
12247
uint32_t : 3;
12248
uint32_t
allow_int_reads_within_luns
: 1;
12249
uint32_t : 3;
12250
uint32_t
cmd_dma_error_enable
: 1;
12251
uint32_t : 23;
12252
};
12253
12255
typedef
volatile
struct
ALT_NAND_DMA_INTRLV_s
ALT_NAND_DMA_INTRLV_t
;
12256
#endif
/* __ASSEMBLY__ */
12257
12259
#define ALT_NAND_DMA_INTRLV_RESET 0x00000110
12260
12261
#define ALT_NAND_DMA_INTRLV_OFST 0x80
12262
12294
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_LSB 0
12295
12296
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_MSB 3
12297
12298
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_WIDTH 4
12299
12300
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET_MSK 0x0000000f
12301
12302
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_CLR_MSK 0xfffffff0
12303
12304
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_RESET 0x0
12305
12306
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_GET(value) (((value) & 0x0000000f) >> 0)
12307
12308
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_FLAG_SET(value) (((value) << 0) & 0x0000000f)
12309
12310
#ifndef __ASSEMBLY__
12311
12321
struct
ALT_NAND_DMA_RESCAN_BUF_FLAG_s
12322
{
12323
uint32_t
flag
: 4;
12324
uint32_t : 28;
12325
};
12326
12328
typedef
volatile
struct
ALT_NAND_DMA_RESCAN_BUF_FLAG_s
ALT_NAND_DMA_RESCAN_BUF_FLAG_t
;
12329
#endif
/* __ASSEMBLY__ */
12330
12332
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_RESET 0x00000000
12333
12334
#define ALT_NAND_DMA_RESCAN_BUF_FLAG_OFST 0x90
12335
12379
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0
12380
12381
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3
12382
12383
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4
12384
12385
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f
12386
12387
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0
12388
12389
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf
12390
12391
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0)
12392
12393
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f)
12394
12410
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24
12411
12412
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24
12413
12414
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1
12415
12416
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000
12417
12418
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff
12419
12420
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0
12421
12422
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET(value) (((value) & 0x01000000) >> 24)
12423
12424
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET(value) (((value) << 24) & 0x01000000)
12425
12444
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_LSB 28
12445
12446
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_MSB 28
12447
12448
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_WIDTH 1
12449
12450
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET_MSK 0x10000000
12451
12452
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_CLR_MSK 0xefffffff
12453
12454
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_RESET 0x0
12455
12456
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28)
12457
12458
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000)
12459
12460
#ifndef __ASSEMBLY__
12461
12471
struct
ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
12472
{
12473
uint32_t
value
: 4;
12474
uint32_t : 20;
12475
uint32_t
update_sync_before_prog_comp
: 1;
12476
uint32_t : 3;
12477
uint32_t
issue_read_before_sync
: 1;
12478
uint32_t : 3;
12479
};
12480
12482
typedef
volatile
struct
ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s
ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t
;
12483
#endif
/* __ASSEMBLY__ */
12484
12486
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f
12487
12488
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0
12489
12518
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_LSB 0
12519
12520
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_MSB 15
12521
12522
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_WIDTH 16
12523
12524
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET_MSK 0x0000ffff
12525
12526
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_CLR_MSK 0xffff0000
12527
12528
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_RESET 0x7878
12529
12530
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_GET(value) (((value) & 0x0000ffff) >> 0)
12531
12532
#define ALT_NAND_DMA_LUN_STAT_CMD_VALUE_SET(value) (((value) << 0) & 0x0000ffff)
12533
12534
#ifndef __ASSEMBLY__
12535
12545
struct
ALT_NAND_DMA_LUN_STAT_CMD_s
12546
{
12547
uint32_t
value
: 16;
12548
uint32_t : 16;
12549
};
12550
12552
typedef
volatile
struct
ALT_NAND_DMA_LUN_STAT_CMD_s
ALT_NAND_DMA_LUN_STAT_CMD_t
;
12553
#endif
/* __ASSEMBLY__ */
12554
12556
#define ALT_NAND_DMA_LUN_STAT_CMD_RESET 0x00007878
12557
12558
#define ALT_NAND_DMA_LUN_STAT_CMD_OFST 0xb0
12559
12586
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_LSB 0
12587
12588
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_MSB 0
12589
12590
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_WIDTH 1
12591
12592
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET_MSK 0x00000001
12593
12594
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_CLR_MSK 0xfffffffe
12595
12596
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_RESET 0x0
12597
12598
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12599
12600
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12601
12611
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_LSB 1
12612
12613
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_MSB 1
12614
12615
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_WIDTH 1
12616
12617
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET_MSK 0x00000002
12618
12619
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_CLR_MSK 0xfffffffd
12620
12621
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_RESET 0x0
12622
12623
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12624
12625
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12626
12636
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_LSB 2
12637
12638
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_MSB 2
12639
12640
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_WIDTH 1
12641
12642
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET_MSK 0x00000004
12643
12644
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_CLR_MSK 0xfffffffb
12645
12646
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_RESET 0x0
12647
12648
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12649
12650
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12651
12661
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_LSB 3
12662
12663
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_MSB 3
12664
12665
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_WIDTH 1
12666
12667
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET_MSK 0x00000008
12668
12669
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_CLR_MSK 0xfffffff7
12670
12671
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_RESET 0x0
12672
12673
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12674
12675
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12676
12677
#ifndef __ASSEMBLY__
12678
12688
struct
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
12689
{
12690
uint32_t
channel0
: 1;
12691
uint32_t
channel1
: 1;
12692
uint32_t
channel2
: 1;
12693
uint32_t
channel3
: 1;
12694
uint32_t : 28;
12695
};
12696
12698
typedef
volatile
struct
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_s
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t
;
12699
#endif
/* __ASSEMBLY__ */
12700
12702
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_RESET 0x00000000
12703
12704
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_OFST 0xc0
12705
12732
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_LSB 0
12733
12734
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_MSB 0
12735
12736
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_WIDTH 1
12737
12738
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET_MSK 0x00000001
12739
12740
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_CLR_MSK 0xfffffffe
12741
12742
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_RESET 0x0
12743
12744
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_GET(value) (((value) & 0x00000001) >> 0)
12745
12746
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL0_SET(value) (((value) << 0) & 0x00000001)
12747
12757
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_LSB 1
12758
12759
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_MSB 1
12760
12761
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_WIDTH 1
12762
12763
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET_MSK 0x00000002
12764
12765
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_CLR_MSK 0xfffffffd
12766
12767
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_RESET 0x0
12768
12769
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_GET(value) (((value) & 0x00000002) >> 1)
12770
12771
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL1_SET(value) (((value) << 1) & 0x00000002)
12772
12782
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_LSB 2
12783
12784
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_MSB 2
12785
12786
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_WIDTH 1
12787
12788
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET_MSK 0x00000004
12789
12790
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_CLR_MSK 0xfffffffb
12791
12792
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_RESET 0x0
12793
12794
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_GET(value) (((value) & 0x00000004) >> 2)
12795
12796
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL2_SET(value) (((value) << 2) & 0x00000004)
12797
12807
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_LSB 3
12808
12809
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_MSB 3
12810
12811
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_WIDTH 1
12812
12813
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET_MSK 0x00000008
12814
12815
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_CLR_MSK 0xfffffff7
12816
12817
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_RESET 0x0
12818
12819
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_GET(value) (((value) & 0x00000008) >> 3)
12820
12821
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_CHANNEL3_SET(value) (((value) << 3) & 0x00000008)
12822
12823
#ifndef __ASSEMBLY__
12824
12834
struct
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
12835
{
12836
uint32_t
channel0
: 1;
12837
uint32_t
channel1
: 1;
12838
uint32_t
channel2
: 1;
12839
uint32_t
channel3
: 1;
12840
uint32_t : 28;
12841
};
12842
12844
typedef
volatile
struct
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_s
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t
;
12845
#endif
/* __ASSEMBLY__ */
12846
12848
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_RESET 0x00000000
12849
12850
#define ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_OFST 0xd0
12851
12852
#ifndef __ASSEMBLY__
12853
12863
struct
ALT_NAND_DMA_s
12864
{
12865
volatile
ALT_NAND_DMA_DMA_EN_t
dma_enable
;
12866
volatile
uint32_t
_pad_0x4_0x1f
[7];
12867
volatile
ALT_NAND_DMA_DMA_INTR_t
dma_intr
;
12868
volatile
uint32_t
_pad_0x24_0x2f
[3];
12869
volatile
ALT_NAND_DMA_DMA_INTR_EN_t
dma_intr_en
;
12870
volatile
uint32_t
_pad_0x34_0x3f
[3];
12871
volatile
ALT_NAND_DMA_TGT_ERR_ADDR_LO_t
target_err_addr_lo
;
12872
volatile
uint32_t
_pad_0x44_0x4f
[3];
12873
volatile
ALT_NAND_DMA_TGT_ERR_ADDR_HI_t
target_err_addr_hi
;
12874
volatile
uint32_t
_pad_0x54_0x5f
[3];
12875
volatile
ALT_NAND_DMA_CHNL_ACT_t
chnl_active
;
12876
volatile
uint32_t
_pad_0x64_0x6f
[3];
12877
volatile
ALT_NAND_DMA_FLSH_BURST_LEN_t
flash_burst_length
;
12878
volatile
uint32_t
_pad_0x74_0x7f
[3];
12879
volatile
ALT_NAND_DMA_INTRLV_t
chip_interleave_enable_and_allow_int_reads
;
12880
volatile
uint32_t
_pad_0x84_0x8f
[3];
12881
volatile
ALT_NAND_DMA_RESCAN_BUF_FLAG_t
rescan_buffer_flag
;
12882
volatile
uint32_t
_pad_0x94_0x9f
[3];
12883
volatile
ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t
no_of_blocks_per_lun
;
12884
volatile
uint32_t
_pad_0xa4_0xaf
[3];
12885
volatile
ALT_NAND_DMA_LUN_STAT_CMD_t
lun_status_cmd
;
12886
volatile
uint32_t
_pad_0xb4_0xbf
[3];
12887
volatile
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_t
cmd_dma_channel_error
;
12888
volatile
uint32_t
_pad_0xc4_0xcf
[3];
12889
volatile
ALT_NAND_DMA_CMD_DMA_CHANNEL_ERROR_EN_t
cmd_dma_channel_error_en
;
12890
};
12891
12893
typedef
volatile
struct
ALT_NAND_DMA_s
ALT_NAND_DMA_t
;
12895
struct
ALT_NAND_DMA_raw_s
12896
{
12897
volatile
uint32_t
dma_enable
;
12898
volatile
uint32_t
_pad_0x4_0x1f
[7];
12899
volatile
uint32_t
dma_intr
;
12900
volatile
uint32_t
_pad_0x24_0x2f
[3];
12901
volatile
uint32_t
dma_intr_en
;
12902
volatile
uint32_t
_pad_0x34_0x3f
[3];
12903
volatile
uint32_t
target_err_addr_lo
;
12904
volatile
uint32_t
_pad_0x44_0x4f
[3];
12905
volatile
uint32_t
target_err_addr_hi
;
12906
volatile
uint32_t
_pad_0x54_0x5f
[3];
12907
volatile
uint32_t
chnl_active
;
12908
volatile
uint32_t
_pad_0x64_0x6f
[3];
12909
volatile
uint32_t
flash_burst_length
;
12910
volatile
uint32_t
_pad_0x74_0x7f
[3];
12911
volatile
uint32_t
chip_interleave_enable_and_allow_int_reads
;
12912
volatile
uint32_t
_pad_0x84_0x8f
[3];
12913
volatile
uint32_t
rescan_buffer_flag
;
12914
volatile
uint32_t
_pad_0x94_0x9f
[3];
12915
volatile
uint32_t
no_of_blocks_per_lun
;
12916
volatile
uint32_t
_pad_0xa4_0xaf
[3];
12917
volatile
uint32_t
lun_status_cmd
;
12918
volatile
uint32_t
_pad_0xb4_0xbf
[3];
12919
volatile
uint32_t
cmd_dma_channel_error
;
12920
volatile
uint32_t
_pad_0xc4_0xcf
[3];
12921
volatile
uint32_t
cmd_dma_channel_error_en
;
12922
};
12923
12925
typedef
volatile
struct
ALT_NAND_DMA_raw_s
ALT_NAND_DMA_raw_t
;
12926
#endif
/* __ASSEMBLY__ */
12927
12929
#ifdef __cplusplus
12930
}
12931
#endif
/* __cplusplus */
12932
#endif
/* __ALT_SOCAL_NAND_H__ */
12933
include
soc_a10
socal
alt_nand.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
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