![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x2 | Write Opcode |
[11:8] | R | 0x0 | Reserved |
[13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes |
[15:14] | R | 0x0 | Reserved |
[17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes |
[23:18] | R | 0x0 | Reserved |
[28:24] | RW | 0x0 | Dummy Write Clock Cycles |
[31:29] | R | 0x0 | Reserved |
Field : Write Opcode - wropcode | |
Write Opcode Field Access Macros: | |
#define | ALT_QSPI_DEVWR_WROPCODE_LSB 0 |
#define | ALT_QSPI_DEVWR_WROPCODE_MSB 7 |
#define | ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 |
#define | ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff |
#define | ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 |
#define | ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 |
#define | ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff) |
Field : Reserved - wr_instr_resv1_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8) |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00) |
Field : Address Transfer Type for Standard SPI modes - addrwidth | ||||||||||||||||||||||||||||||||||||||||
0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) | |||||||||||||||||||||||||||||||||||||||
Field : Reserved - wr_instr_resv2_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000) |
Field : Data Transfer Type for Standard SPI modes - datawidth | ||||||||||||||||||||||||||||||||||||||||
0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) | |||||||||||||||||||||||||||||||||||||||
Field : Reserved - wr_instr_resv3_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18) |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000) |
Field : Dummy Write Clock Cycles - dummywrclks | |
Number of dummy clock cycles required by device for write instruction. Field Access Macros: | |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24) |
#define | ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000) |
Field : Reserved - wr_instr_resv4_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29) |
#define | ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000) |
Data Structures | |
struct | ALT_QSPI_DEVWR_s |
Macros | |
#define | ALT_QSPI_DEVWR_RESET 0x00000002 |
#define | ALT_QSPI_DEVWR_OFST 0x8 |
Typedefs | |
typedef struct ALT_QSPI_DEVWR_s | ALT_QSPI_DEVWR_t |
struct ALT_QSPI_DEVWR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_DEVWR.
Data Fields | ||
---|---|---|
uint32_t | wropcode: 8 | Write Opcode |
const uint32_t | wr_instr_resv1_fld: 4 | Reserved |
uint32_t | addrwidth: 2 | Address Transfer Type for Standard SPI modes |
const uint32_t | wr_instr_resv2_fld: 2 | Reserved |
uint32_t | datawidth: 2 | Data Transfer Type for Standard SPI modes |
const uint32_t | wr_instr_resv3_fld: 6 | Reserved |
uint32_t | dummywrclks: 5 | Dummy Write Clock Cycles |
const uint32_t | wr_instr_resv4_fld: 3 | Reserved |
#define ALT_QSPI_DEVWR_WROPCODE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WROPCODE register field.
#define ALT_QSPI_DEVWR_WROPCODE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WROPCODE register field.
#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8 |
The width in bits of the ALT_QSPI_DEVWR_WROPCODE register field.
#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff |
The mask used to set the ALT_QSPI_DEVWR_WROPCODE register field value.
#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_QSPI_DEVWR_WROPCODE register field value.
#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2 |
The reset value of the ALT_QSPI_DEVWR_WROPCODE register field.
#define ALT_QSPI_DEVWR_WROPCODE_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_QSPI_DEVWR_WROPCODE field value from a register.
#define ALT_QSPI_DEVWR_WROPCODE_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_QSPI_DEVWR_WROPCODE register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4 |
The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00 |
The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff |
The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET | ( | value | ) | (((value) & 0x00000f00) >> 8) |
Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD field value from a register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET | ( | value | ) | (((value) << 8) & 0x00000f00) |
Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0 |
Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
Write address transferred on DQ0. Supported by all SPI flash devices
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1 |
Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2 |
Enumerated value for register field ALT_QSPI_DEVWR_ADDRWIDTH
Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field.
#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_ADDRWIDTH register field.
#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVWR_ADDRWIDTH register field.
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000 |
The mask used to set the ALT_QSPI_DEVWR_ADDRWIDTH register field value.
#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff |
The mask used to clear the ALT_QSPI_DEVWR_ADDRWIDTH register field value.
#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_ADDRWIDTH register field.
#define ALT_QSPI_DEVWR_ADDRWIDTH_GET | ( | value | ) | (((value) & 0x00003000) >> 12) |
Extracts the ALT_QSPI_DEVWR_ADDRWIDTH field value from a register.
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET | ( | value | ) | (((value) << 12) & 0x00003000) |
Produces a ALT_QSPI_DEVWR_ADDRWIDTH register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000 |
The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD field value from a register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0 |
Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
Write data transferred on DQ0. Supported by all SPI flash devices
#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1 |
Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2 |
Enumerated value for register field ALT_QSPI_DEVWR_DATAWIDTH
Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field.
#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DATAWIDTH register field.
#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVWR_DATAWIDTH register field.
#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000 |
The mask used to set the ALT_QSPI_DEVWR_DATAWIDTH register field value.
#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_QSPI_DEVWR_DATAWIDTH register field value.
#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_DATAWIDTH register field.
#define ALT_QSPI_DEVWR_DATAWIDTH_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_QSPI_DEVWR_DATAWIDTH field value from a register.
#define ALT_QSPI_DEVWR_DATAWIDTH_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_QSPI_DEVWR_DATAWIDTH register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6 |
The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000 |
The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff |
The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET | ( | value | ) | (((value) & 0x00fc0000) >> 18) |
Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD field value from a register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET | ( | value | ) | (((value) << 18) & 0x00fc0000) |
Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5 |
The width in bits of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000 |
The mask used to set the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff |
The mask used to clear the ALT_QSPI_DEVWR_DUMMYWRCLKS register field value.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_DUMMYWRCLKS register field.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET | ( | value | ) | (((value) & 0x1f000000) >> 24) |
Extracts the ALT_QSPI_DEVWR_DUMMYWRCLKS field value from a register.
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET | ( | value | ) | (((value) << 24) & 0x1f000000) |
Produces a ALT_QSPI_DEVWR_DUMMYWRCLKS register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3 |
The width in bits of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000 |
The mask used to set the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff |
The mask used to clear the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET | ( | value | ) | (((value) & 0xe0000000) >> 29) |
Extracts the ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD field value from a register.
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET | ( | value | ) | (((value) << 29) & 0xe0000000) |
Produces a ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVWR_RESET 0x00000002 |
The reset value of the ALT_QSPI_DEVWR register.
#define ALT_QSPI_DEVWR_OFST 0x8 |
The byte offset of the ALT_QSPI_DEVWR register from the beginning of the component.
typedef struct ALT_QSPI_DEVWR_s ALT_QSPI_DEVWR_t |
The typedef declaration for register ALT_QSPI_DEVWR.