Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECC_DECSTAT

Description

Diagnostic decoder status

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG
[1] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG
[2] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG
[3] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG
[4] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG
[5] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG
[6] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG
[7] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG
[8] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG
[9] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG
[10] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG
[11] RW 0x0 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG
[31:12] ??? 0x0 UNDEFINED

Field : DEC0SERRFLG

indicates decoder for data [63:0] has detected SBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_LSB   0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_MSB   0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK   0x00000001
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK   0xfffffffe
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET(value)   (((value) << 0) & 0x00000001)
 

Field : DEC1SERRFLG

indicates decoder for data [127:64] has detected SBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_LSB   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_MSB   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK   0x00000002
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK   0xfffffffd
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET(value)   (((value) << 1) & 0x00000002)
 

Field : DEC2SERRFLG

indicates decoder for data [191:128] has detected SBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_LSB   2
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_MSB   2
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK   0x00000004
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK   0xfffffffb
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET(value)   (((value) << 2) & 0x00000004)
 

Field : DEC3SERRFLG

indicates decoder for data [255:192] has detected SBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a single bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_LSB   3
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_MSB   3
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK   0x00000008
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK   0xfffffff7
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET(value)   (((value) << 3) & 0x00000008)
 

Field : DEC0ADDRFLG

indicates decoder for data [63:0] has detected address error.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_LSB   4
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_MSB   4
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK   0x00000010
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK   0xffffffef
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET(value)   (((value) << 4) & 0x00000010)
 

Field : DEC1ADDRFLG

indicates decoder for data [127:64] has detected address error.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_LSB   5
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_MSB   5
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK   0x00000020
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK   0xffffffdf
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET(value)   (((value) << 5) & 0x00000020)
 

Field : DEC2ADDRFLG

indicates decoder for data [191:128] has detected address error.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_LSB   6
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_MSB   6
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK   0x00000040
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK   0xffffffbf
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET(value)   (((value) << 6) & 0x00000040)
 

Field : DEC3ADDRFLG

indicates decoder for data [255:192] has detected address error.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected an address mismatch error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears.Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_LSB   7
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_MSB   7
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK   0x00000080
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK   0xffffff7f
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET(value)   (((value) << 7) & 0x00000080)
 

Field : DEC0DERRFLG

indicates decoder for data [63:0] has detected DBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_LSB   8
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_MSB   8
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK   0x00000100
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK   0xfffffeff
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET(value)   (((value) << 8) & 0x00000100)
 

Field : DEC1DERRFLG

indicates decoder for data [127:64] has detected DBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_LSB   9
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_MSB   9
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK   0x00000200
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK   0xfffffdff
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET(value)   (((value) << 9) & 0x00000200)
 

Field : DEC2DERRFLG

indicates decoder for data [191:128] has detected DBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit.Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_LSB   10
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_MSB   10
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK   0x00000400
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK   0xfffffbff
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET(value)   (((value) << 10) & 0x00000400)
 

Field : DEC3DERRFLG

indicates decoder for data [255:192] has detected DBE.

1'b0: No error has been captured with this flag.

1'b1: Decoder 0 detected a double-bit error. This flag will be set by the hardware and it will be cleared by the writing 1. This flag will be set till SW clears. Additional errors will not change the state of this bit. Error flag is set on the first beat of erred data.

This won't be reset by the ecc_en bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_LSB   11
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_MSB   11
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK   0x00000800
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK   0xfffff7ff
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET(value)   (((value) << 11) & 0x00000800)
 

Data Structures

struct  ALT_ECC_HMC_OCP_ECC_DECSTAT_s
 

Macros

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_ECC_DECSTAT_OFST   0x154
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_ECC_DECSTAT_s 
ALT_ECC_HMC_OCP_ECC_DECSTAT_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_ECC_DECSTAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_ECC_DECSTAT.

Data Fields
uint32_t DEC0SERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG
uint32_t DEC1SERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG
uint32_t DEC2SERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG
uint32_t DEC3SERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG
uint32_t DEC0ADDRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG
uint32_t DEC1ADDRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG
uint32_t DEC2ADDRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG
uint32_t DEC3ADDRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG
uint32_t DEC0DERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG
uint32_t DEC1DERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG
uint32_t DEC2DERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG
uint32_t DEC3DERRFLG: 1 ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG
uint32_t __pad0__: 20 UNDEFINED

Macro Definitions

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET_MSK   0x00000001

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0SERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_LSB   1

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_MSB   1

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET_MSK   0x00000002

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_CLR_MSK   0xfffffffd

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1SERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_LSB   2

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_MSB   2

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET_MSK   0x00000004

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_CLR_MSK   0xfffffffb

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2SERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_LSB   3

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_MSB   3

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET_MSK   0x00000008

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_CLR_MSK   0xfffffff7

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3SERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_LSB   4

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_MSB   4

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET_MSK   0x00000010

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_CLR_MSK   0xffffffef

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0ADDRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_LSB   5

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_MSB   5

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET_MSK   0x00000020

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_CLR_MSK   0xffffffdf

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1ADDRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_LSB   6

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_MSB   6

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET_MSK   0x00000040

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_CLR_MSK   0xffffffbf

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2ADDRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_LSB   7

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_MSB   7

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET_MSK   0x00000080

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_CLR_MSK   0xffffff7f

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3ADDRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_MSB   8

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET_MSK   0x00000100

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_CLR_MSK   0xfffffeff

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC0DERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_LSB   9

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_MSB   9

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET_MSK   0x00000200

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_CLR_MSK   0xfffffdff

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC1DERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_LSB   10

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_MSB   10

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET_MSK   0x00000400

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_CLR_MSK   0xfffffbff

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC2DERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_LSB   11

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_MSB   11

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET_MSK   0x00000800

The mask used to set the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG field value from a register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_ECC_HMC_OCP_ECC_DECSTAT_DEC3DERRFLG register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_ECC_DECSTAT register.

#define ALT_ECC_HMC_OCP_ECC_DECSTAT_OFST   0x154

The byte offset of the ALT_ECC_HMC_OCP_ECC_DECSTAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_ECC_HMC_OCP_ECC_DECSTAT.