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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 12 (LPI Control and Status Register)
The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN |
[1] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX |
[2] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN |
[3] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX |
[7:4] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 |
[8] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST |
[9] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST |
[15:10] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 |
[16] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN |
[17] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS |
[18] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN |
[19] | RW | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA |
[31:20] | R | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 |
Field : tlpien | |
Transmit LPI Entry When set, this bit indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB 0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB 0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET(value) (((value) << 0) & 0x00000001) |
Field : tlpiex | |
Transmit LPI Exit When set, this bit indicates that the MAC transmitter has exited the LPI state after the user has cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET(value) (((value) << 1) & 0x00000002) |
Field : rlpien | |
Receive LPI Entry When set, this bit indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB 2 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB 2 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK 0x00000004 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK 0xfffffffb |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET(value) (((value) << 2) & 0x00000004) |
Field : rlpiex | |
Receive LPI Exit When set, this bit indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the normal reception. This bit is cleared by a read into this register. Note: This bit may not get set if the MAC stops receiving the LPI pattern for a very short duration, such as, less than 3 clock cycles of CSR clock. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB 3 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB 3 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET(value) (((value) << 3) & 0x00000008) |
Field : reserved_7_4 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_LSB 4 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_MSB 7 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_WIDTH 4 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET_MSK 0x000000f0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_CLR_MSK 0xffffff0f |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_GET(value) (((value) & 0x000000f0) >> 4) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET(value) (((value) << 4) & 0x000000f0) |
Field : tlpist | |
Transmit LPI State When set, this bit indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB 8 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB 8 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK 0x00000100 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK 0xfffffeff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET(value) (((value) << 8) & 0x00000100) |
Field : rlpist | |
Receive LPI State When set, this bit indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB 9 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB 9 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK 0x00000200 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK 0xfffffdff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET(value) (((value) << 9) & 0x00000200) |
Field : reserved_15_10 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_LSB 10 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_MSB 15 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_WIDTH 6 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET_MSK 0x0000fc00 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_CLR_MSK 0xffff03ff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_GET(value) (((value) & 0x0000fc00) >> 10) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET(value) (((value) << 10) & 0x0000fc00) |
Field : lpien | |
LPI Enable When set, this bit instructs the MAC Transmitter to enter the LPI state. When reset, this bit instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC exits the LPI state because of the arrival of a new packet for transmission. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB 16 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB 16 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET(value) (((value) << 16) & 0x00010000) |
Field : pls | |
PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (okay) at least for the time indicated by the LPI LS TIMER. When set, the link is considered to be okay (up) and when reset, the link is considered to be down. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB 17 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB 17 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK 0x00020000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK 0xfffdffff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET(value) (((value) << 17) & 0x00020000) |
Field : plsen | |
PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or SMII receive paths to be used for activating the LPI LS TIMER. When set, the MAC uses the link-status bits of Register 54 (SGMII/RGMII/SMII Status Register) and Bit 17 (PLS) for the LPI LS Timer trigger. When cleared, the MAC ignores the link-status bits of Register 54 and takes only the PLS bit. This bit is RO and reserved if you have not selected the RGMII, SGMII, or SMII PHY interface. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB 18 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB 18 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK 0x00040000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK 0xfffbffff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET(value) (((value) << 18) & 0x00040000) |
Field : lpitxa | |
LPI TX Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the transmit side. This bit is not functional in the GMAC-CORE configuration in which the Tx clock gating is done during the LPI mode. If the LPITXA and LPIEN bits are set to 1, the MAC enters the LPI mode only after all outstanding frames (in the core) and pending frames (in the application interface) have been transmitted. The MAC comes out of the LPI mode when the application sends any frame for transmission or the application issues a TX FIFO Flush command. In addition, the MAC automatically clears the LPIEN bit when it exits the LPI state. If TX FIFO Flush is set, in Bit 20 of Register 6 (Operation Mode Register), when the MAC is in the LPI mode, the MAC exits the LPI mode. When this bit is 0, the LPIEN bit directly controls behavior of the MAC when it is entering or coming out of the LPI mode. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD | 0x0 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB 19 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB 19 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH 1 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK 0x00080000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK 0xfff7ffff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET(value) (((value) << 19) & 0x00080000) |
Field : reserved_31_20 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_LSB 20 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_MSB 31 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_WIDTH 12 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET_MSK 0xfff00000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_CLR_MSK 0x000fffff |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_RESET 0x0 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_GET(value) (((value) & 0xfff00000) >> 20) |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET(value) (((value) << 20) & 0xfff00000) |
Data Structures | |
struct | ALT_EMAC_GMAC_LPI_CTL_STAT_s |
Macros | |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_OFST 0x30 |
#define | ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_LPI_CTL_STAT_s | ALT_EMAC_GMAC_LPI_CTL_STAT_t |
struct ALT_EMAC_GMAC_LPI_CTL_STAT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.
Data Fields | ||
---|---|---|
const uint32_t | tlpien: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN |
const uint32_t | tlpiex: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX |
const uint32_t | rlpien: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN |
const uint32_t | rlpiex: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX |
const uint32_t | reserved_7_4: 4 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 |
const uint32_t | tlpist: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST |
const uint32_t | rlpist: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST |
const uint32_t | reserved_15_10: 6 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 |
uint32_t | lpien: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN |
uint32_t | pls: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLS |
const uint32_t | plsen: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN |
uint32_t | lpitxa: 1 | ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA |
const uint32_t | reserved_31_20: 12 | ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 |
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEN register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIEX register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEN register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIEX register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_WIDTH 4 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET_MSK 0x000000f0 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_CLR_MSK 0xffffff0f |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_GET | ( | value | ) | (((value) & 0x000000f0) >> 4) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4_SET | ( | value | ) | (((value) << 4) & 0x000000f0) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_7_4 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_TLPIST register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET_MSK 0x00000200 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RLPIST register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_WIDTH 6 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET_MSK 0x0000fc00 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_CLR_MSK 0xffff03ff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_GET | ( | value | ) | (((value) & 0x0000fc00) >> 10) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10_SET | ( | value | ) | (((value) << 10) & 0x0000fc00) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_15_10 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPIEN register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLS
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET_MSK 0x00020000 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLS field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLS_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_PLSEN register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_LPITXA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_WIDTH 12 |
The width in bits of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET_MSK 0xfff00000 |
The mask used to set the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_CLR_MSK 0x000fffff |
The mask used to clear the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_GET | ( | value | ) | (((value) & 0xfff00000) >> 20) |
Extracts the ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 field value from a register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20_SET | ( | value | ) | (((value) << 20) & 0xfff00000) |
Produces a ALT_EMAC_GMAC_LPI_CTL_STAT_RSVD_31_20 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_LPI_CTL_STAT register.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_OFST 0x30 |
The byte offset of the ALT_EMAC_GMAC_LPI_CTL_STAT register from the beginning of the component.
#define ALT_EMAC_GMAC_LPI_CTL_STAT_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_CTL_STAT_OFST)) |
The address of the ALT_EMAC_GMAC_LPI_CTL_STAT register.
typedef struct ALT_EMAC_GMAC_LPI_CTL_STAT_s ALT_EMAC_GMAC_LPI_CTL_STAT_t |
The typedef declaration for register ALT_EMAC_GMAC_LPI_CTL_STAT.