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The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_qspi.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_QSPI_H__
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#define __ALT_SOCAL_QSPI_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_QSPI_CFG_EN_E_DIS 0x0
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#define ALT_QSPI_CFG_EN_E_EN 0x1
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#define ALT_QSPI_CFG_EN_LSB 0
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#define ALT_QSPI_CFG_EN_MSB 0
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#define ALT_QSPI_CFG_EN_WIDTH 1
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#define ALT_QSPI_CFG_EN_SET_MSK 0x00000001
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#define ALT_QSPI_CFG_EN_CLR_MSK 0xfffffffe
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#define ALT_QSPI_CFG_EN_RESET 0x0
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#define ALT_QSPI_CFG_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_QSPI_CFG_EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0
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#define ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1
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#define ALT_QSPI_CFG_SELCLKPOL_LSB 1
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#define ALT_QSPI_CFG_SELCLKPOL_MSB 1
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#define ALT_QSPI_CFG_SELCLKPOL_WIDTH 1
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#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK 0x00000002
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#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK 0xfffffffd
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#define ALT_QSPI_CFG_SELCLKPOL_RESET 0x0
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#define ALT_QSPI_CFG_SELCLKPOL_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_QSPI_CFG_SELCLKPOL_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0
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#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1
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#define ALT_QSPI_CFG_SELCLKPHASE_LSB 2
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#define ALT_QSPI_CFG_SELCLKPHASE_MSB 2
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#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH 1
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#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK 0x00000004
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#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK 0xfffffffb
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#define ALT_QSPI_CFG_SELCLKPHASE_RESET 0x0
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#define ALT_QSPI_CFG_SELCLKPHASE_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_QSPI_CFG_SELCLKPHASE_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_LSB 3
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_MSB 6
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_WIDTH 4
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_SET_MSK 0x00000078
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_CLR_MSK 0xffffff87
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_RESET 0x0
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_GET(value) (((value) & 0x00000078) >> 3)
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#define ALT_QSPI_CFG_CFG_RESV1_FLD_SET(value) (((value) << 3) & 0x00000078)
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#define ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0
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#define ALT_QSPI_CFG_ENDIRACC_E_EN 0x1
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#define ALT_QSPI_CFG_ENDIRACC_LSB 7
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#define ALT_QSPI_CFG_ENDIRACC_MSB 7
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#define ALT_QSPI_CFG_ENDIRACC_WIDTH 1
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#define ALT_QSPI_CFG_ENDIRACC_SET_MSK 0x00000080
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#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK 0xffffff7f
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#define ALT_QSPI_CFG_ENDIRACC_RESET 0x0
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#define ALT_QSPI_CFG_ENDIRACC_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_QSPI_CFG_ENDIRACC_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0
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#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1
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#define ALT_QSPI_CFG_ENLEGACYIP_LSB 8
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#define ALT_QSPI_CFG_ENLEGACYIP_MSB 8
324
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#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH 1
326
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#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK 0x00000100
328
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#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK 0xfffffeff
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331
#define ALT_QSPI_CFG_ENLEGACYIP_RESET 0x0
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#define ALT_QSPI_CFG_ENLEGACYIP_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_QSPI_CFG_ENLEGACYIP_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0
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#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1
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#define ALT_QSPI_CFG_PERSELDEC_LSB 9
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#define ALT_QSPI_CFG_PERSELDEC_MSB 9
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#define ALT_QSPI_CFG_PERSELDEC_WIDTH 1
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#define ALT_QSPI_CFG_PERSELDEC_SET_MSK 0x00000200
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#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK 0xfffffdff
376
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#define ALT_QSPI_CFG_PERSELDEC_RESET 0x0
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#define ALT_QSPI_CFG_PERSELDEC_GET(value) (((value) & 0x00000200) >> 9)
380
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#define ALT_QSPI_CFG_PERSELDEC_SET(value) (((value) << 9) & 0x00000200)
382
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#define ALT_QSPI_CFG_PERCSLINES_LSB 10
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#define ALT_QSPI_CFG_PERCSLINES_MSB 13
397
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#define ALT_QSPI_CFG_PERCSLINES_WIDTH 4
399
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#define ALT_QSPI_CFG_PERCSLINES_SET_MSK 0x00003c00
401
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#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK 0xffffc3ff
403
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#define ALT_QSPI_CFG_PERCSLINES_RESET 0x0
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#define ALT_QSPI_CFG_PERCSLINES_GET(value) (((value) & 0x00003c00) >> 10)
407
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#define ALT_QSPI_CFG_PERCSLINES_SET(value) (((value) << 10) & 0x00003c00)
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431
#define ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0
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#define ALT_QSPI_CFG_WP_E_WRPROTON 0x1
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#define ALT_QSPI_CFG_WP_LSB 14
441
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#define ALT_QSPI_CFG_WP_MSB 14
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#define ALT_QSPI_CFG_WP_WIDTH 1
445
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#define ALT_QSPI_CFG_WP_SET_MSK 0x00004000
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#define ALT_QSPI_CFG_WP_CLR_MSK 0xffffbfff
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#define ALT_QSPI_CFG_WP_RESET 0x0
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#define ALT_QSPI_CFG_WP_GET(value) (((value) & 0x00004000) >> 14)
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#define ALT_QSPI_CFG_WP_SET(value) (((value) << 14) & 0x00004000)
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#define ALT_QSPI_CFG_ENDMA_E_DIS 0x0
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#define ALT_QSPI_CFG_ENDMA_E_EN 0x1
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#define ALT_QSPI_CFG_ENDMA_LSB 15
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#define ALT_QSPI_CFG_ENDMA_MSB 15
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#define ALT_QSPI_CFG_ENDMA_WIDTH 1
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#define ALT_QSPI_CFG_ENDMA_SET_MSK 0x00008000
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#define ALT_QSPI_CFG_ENDMA_CLR_MSK 0xffff7fff
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#define ALT_QSPI_CFG_ENDMA_RESET 0x0
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#define ALT_QSPI_CFG_ENDMA_GET(value) (((value) & 0x00008000) >> 15)
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#define ALT_QSPI_CFG_ENDMA_SET(value) (((value) << 15) & 0x00008000)
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#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0
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#define ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1
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#define ALT_QSPI_CFG_ENAHBREMAP_LSB 16
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#define ALT_QSPI_CFG_ENAHBREMAP_MSB 16
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#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH 1
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#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK 0x00010000
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#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK 0xfffeffff
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#define ALT_QSPI_CFG_ENAHBREMAP_RESET 0x0
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#define ALT_QSPI_CFG_ENAHBREMAP_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_QSPI_CFG_ENAHBREMAP_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB 17
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB 17
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH 1
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK 0x00020000
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK 0xfffdffff
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET 0x0
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value) (((value) & 0x00020000) >> 17)
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#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value) (((value) << 17) & 0x00020000)
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#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0
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#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1
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#define ALT_QSPI_CFG_ENTERXIPIMM_LSB 18
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#define ALT_QSPI_CFG_ENTERXIPIMM_MSB 18
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#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH 1
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#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK 0x00040000
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#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK 0xfffbffff
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#define ALT_QSPI_CFG_ENTERXIPIMM_RESET 0x0
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#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value) (((value) & 0x00040000) >> 18)
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#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value) (((value) << 18) & 0x00040000)
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe
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#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf
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#define ALT_QSPI_CFG_BAUDDIV_LSB 19
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#define ALT_QSPI_CFG_BAUDDIV_MSB 22
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#define ALT_QSPI_CFG_BAUDDIV_WIDTH 4
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#define ALT_QSPI_CFG_BAUDDIV_SET_MSK 0x00780000
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#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK 0xff87ffff
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#define ALT_QSPI_CFG_BAUDDIV_RESET 0xf
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#define ALT_QSPI_CFG_BAUDDIV_GET(value) (((value) & 0x00780000) >> 19)
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#define ALT_QSPI_CFG_BAUDDIV_SET(value) (((value) << 19) & 0x00780000)
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_LSB 23
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_MSB 30
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_WIDTH 8
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_SET_MSK 0x7f800000
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_CLR_MSK 0x807fffff
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_RESET 0x0
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_GET(value) (((value) & 0x7f800000) >> 23)
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#define ALT_QSPI_CFG_CFG_RESV2_FLD_SET(value) (((value) << 23) & 0x7f800000)
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#define ALT_QSPI_CFG_IDLE_E_NOTSET 0x0
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#define ALT_QSPI_CFG_IDLE_E_SET 0x1
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#define ALT_QSPI_CFG_IDLE_LSB 31
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#define ALT_QSPI_CFG_IDLE_MSB 31
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#define ALT_QSPI_CFG_IDLE_WIDTH 1
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#define ALT_QSPI_CFG_IDLE_SET_MSK 0x80000000
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#define ALT_QSPI_CFG_IDLE_CLR_MSK 0x7fffffff
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#define ALT_QSPI_CFG_IDLE_RESET 0x1
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#define ALT_QSPI_CFG_IDLE_GET(value) (((value) & 0x80000000) >> 31)
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#define ALT_QSPI_CFG_IDLE_SET(value) (((value) << 31) & 0x80000000)
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#ifndef __ASSEMBLY__
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struct
ALT_QSPI_CFG_s
882
{
883
uint32_t
en
: 1;
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uint32_t
selclkpol
: 1;
885
uint32_t
selclkphase
: 1;
886
const
uint32_t
config_resv1_fld
: 4;
887
uint32_t
endiracc
: 1;
888
uint32_t
enlegacyip
: 1;
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uint32_t
perseldec
: 1;
890
uint32_t
percslines
: 4;
891
uint32_t
wp
: 1;
892
uint32_t
endma
: 1;
893
uint32_t
enahbremap
: 1;
894
uint32_t
enterxipnextrd
: 1;
895
uint32_t
enterxipimm
: 1;
896
uint32_t
bauddiv
: 4;
897
const
uint32_t
config_resv2_fld
: 8;
898
const
uint32_t
idle
: 1;
899
};
900
902
typedef
volatile
struct
ALT_QSPI_CFG_s
ALT_QSPI_CFG_t
;
903
#endif
/* __ASSEMBLY__ */
904
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#define ALT_QSPI_CFG_RESET 0x80780000
907
908
#define ALT_QSPI_CFG_OFST 0x0
909
950
#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3
951
956
#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb
957
959
#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0
960
961
#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7
962
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#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8
964
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#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff
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#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00
968
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#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3
970
971
#define ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0)
972
973
#define ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff)
974
1004
#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0
1005
1011
#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1
1012
1018
#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2
1019
1021
#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8
1022
1023
#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9
1024
1025
#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2
1026
1027
#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300
1028
1029
#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff
1030
1031
#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0
1032
1033
#define ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8)
1034
1035
#define ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300)
1036
1044
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10
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1046
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11
1047
1048
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2
1049
1050
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00
1051
1052
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff
1053
1054
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0
1055
1056
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10)
1057
1058
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00)
1059
1092
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0
1093
1100
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1
1101
1108
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2
1109
1111
#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12
1112
1113
#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13
1114
1115
#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2
1116
1117
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000
1118
1119
#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff
1120
1121
#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0
1122
1123
#define ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1124
1125
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1126
1134
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14
1135
1136
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15
1137
1138
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2
1139
1140
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1141
1142
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1143
1144
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0
1145
1146
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1147
1148
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1149
1184
#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0
1185
1192
#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1
1193
1200
#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2
1201
1203
#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16
1204
1205
#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17
1206
1207
#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2
1208
1209
#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000
1210
1211
#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff
1212
1213
#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0
1214
1215
#define ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1216
1217
#define ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1218
1226
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18
1227
1228
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19
1229
1230
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2
1231
1232
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000
1233
1234
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff
1235
1236
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0
1237
1238
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18)
1239
1240
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000)
1241
1263
#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0
1264
1269
#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1
1270
1272
#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20
1273
1274
#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20
1275
1276
#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1
1277
1278
#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000
1279
1280
#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff
1281
1282
#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0
1283
1284
#define ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20)
1285
1286
#define ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000)
1287
1295
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21
1296
1297
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23
1298
1299
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3
1300
1301
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000
1302
1303
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff
1304
1305
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0
1306
1307
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21)
1308
1309
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000)
1310
1320
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24
1321
1322
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28
1323
1324
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5
1325
1326
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000
1327
1328
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff
1329
1330
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0
1331
1332
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1333
1334
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000)
1335
1343
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29
1344
1345
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31
1346
1347
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3
1348
1349
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000
1350
1351
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff
1352
1353
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0
1354
1355
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1356
1357
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000)
1358
1359
#ifndef __ASSEMBLY__
1360
1370
struct
ALT_QSPI_DEVRD_s
1371
{
1372
uint32_t
rdopcode
: 8;
1373
uint32_t
instwidth
: 2;
1374
const
uint32_t
rd_instr_resv1_fld
: 2;
1375
uint32_t
addrwidth
: 2;
1376
const
uint32_t
rd_instr_resv2_fld
: 2;
1377
uint32_t
datawidth
: 2;
1378
const
uint32_t
rd_instr_resv3_fld
: 2;
1379
uint32_t
enmodebits
: 1;
1380
const
uint32_t
rd_instr_resv4_fld
: 3;
1381
uint32_t
dummyrdclks
: 5;
1382
const
uint32_t
rd_instr_resv5_fld
: 3;
1383
};
1384
1386
typedef
volatile
struct
ALT_QSPI_DEVRD_s
ALT_QSPI_DEVRD_t
;
1387
#endif
/* __ASSEMBLY__ */
1388
1390
#define ALT_QSPI_DEVRD_RESET 0x00000003
1391
1392
#define ALT_QSPI_DEVRD_OFST 0x4
1393
1420
#define ALT_QSPI_DEVWR_WROPCODE_LSB 0
1421
1422
#define ALT_QSPI_DEVWR_WROPCODE_MSB 7
1423
1424
#define ALT_QSPI_DEVWR_WROPCODE_WIDTH 8
1425
1426
#define ALT_QSPI_DEVWR_WROPCODE_SET_MSK 0x000000ff
1427
1428
#define ALT_QSPI_DEVWR_WROPCODE_CLR_MSK 0xffffff00
1429
1430
#define ALT_QSPI_DEVWR_WROPCODE_RESET 0x2
1431
1432
#define ALT_QSPI_DEVWR_WROPCODE_GET(value) (((value) & 0x000000ff) >> 0)
1433
1434
#define ALT_QSPI_DEVWR_WROPCODE_SET(value) (((value) << 0) & 0x000000ff)
1435
1443
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_LSB 8
1444
1445
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_MSB 11
1446
1447
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_WIDTH 4
1448
1449
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET_MSK 0x00000f00
1450
1451
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_CLR_MSK 0xfffff0ff
1452
1453
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_RESET 0x0
1454
1455
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000f00) >> 8)
1456
1457
#define ALT_QSPI_DEVWR_WR_INSTR_RESV1_FLD_SET(value) (((value) << 8) & 0x00000f00)
1458
1491
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_SINGLE 0x0
1492
1499
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_DUAL 0x1
1500
1507
#define ALT_QSPI_DEVWR_ADDRWIDTH_E_QUAD 0x2
1508
1510
#define ALT_QSPI_DEVWR_ADDRWIDTH_LSB 12
1511
1512
#define ALT_QSPI_DEVWR_ADDRWIDTH_MSB 13
1513
1514
#define ALT_QSPI_DEVWR_ADDRWIDTH_WIDTH 2
1515
1516
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET_MSK 0x00003000
1517
1518
#define ALT_QSPI_DEVWR_ADDRWIDTH_CLR_MSK 0xffffcfff
1519
1520
#define ALT_QSPI_DEVWR_ADDRWIDTH_RESET 0x0
1521
1522
#define ALT_QSPI_DEVWR_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12)
1523
1524
#define ALT_QSPI_DEVWR_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000)
1525
1533
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_LSB 14
1534
1535
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_MSB 15
1536
1537
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_WIDTH 2
1538
1539
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET_MSK 0x0000c000
1540
1541
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff
1542
1543
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_RESET 0x0
1544
1545
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14)
1546
1547
#define ALT_QSPI_DEVWR_WR_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000)
1548
1583
#define ALT_QSPI_DEVWR_DATAWIDTH_E_SINGLE 0x0
1584
1591
#define ALT_QSPI_DEVWR_DATAWIDTH_E_DUAL 0x1
1592
1599
#define ALT_QSPI_DEVWR_DATAWIDTH_E_QUAD 0x2
1600
1602
#define ALT_QSPI_DEVWR_DATAWIDTH_LSB 16
1603
1604
#define ALT_QSPI_DEVWR_DATAWIDTH_MSB 17
1605
1606
#define ALT_QSPI_DEVWR_DATAWIDTH_WIDTH 2
1607
1608
#define ALT_QSPI_DEVWR_DATAWIDTH_SET_MSK 0x00030000
1609
1610
#define ALT_QSPI_DEVWR_DATAWIDTH_CLR_MSK 0xfffcffff
1611
1612
#define ALT_QSPI_DEVWR_DATAWIDTH_RESET 0x0
1613
1614
#define ALT_QSPI_DEVWR_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16)
1615
1616
#define ALT_QSPI_DEVWR_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000)
1617
1625
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_LSB 18
1626
1627
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_MSB 23
1628
1629
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_WIDTH 6
1630
1631
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET_MSK 0x00fc0000
1632
1633
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_CLR_MSK 0xff03ffff
1634
1635
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_RESET 0x0
1636
1637
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_GET(value) (((value) & 0x00fc0000) >> 18)
1638
1639
#define ALT_QSPI_DEVWR_WR_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x00fc0000)
1640
1650
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_LSB 24
1651
1652
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_MSB 28
1653
1654
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_WIDTH 5
1655
1656
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET_MSK 0x1f000000
1657
1658
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_CLR_MSK 0xe0ffffff
1659
1660
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_RESET 0x0
1661
1662
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_GET(value) (((value) & 0x1f000000) >> 24)
1663
1664
#define ALT_QSPI_DEVWR_DUMMYWRCLKS_SET(value) (((value) << 24) & 0x1f000000)
1665
1673
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_LSB 29
1674
1675
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_MSB 31
1676
1677
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_WIDTH 3
1678
1679
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET_MSK 0xe0000000
1680
1681
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_CLR_MSK 0x1fffffff
1682
1683
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_RESET 0x0
1684
1685
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_GET(value) (((value) & 0xe0000000) >> 29)
1686
1687
#define ALT_QSPI_DEVWR_WR_INSTR_RESV4_FLD_SET(value) (((value) << 29) & 0xe0000000)
1688
1689
#ifndef __ASSEMBLY__
1690
1700
struct
ALT_QSPI_DEVWR_s
1701
{
1702
uint32_t
wropcode
: 8;
1703
const
uint32_t
wr_instr_resv1_fld
: 4;
1704
uint32_t
addrwidth
: 2;
1705
const
uint32_t
wr_instr_resv2_fld
: 2;
1706
uint32_t
datawidth
: 2;
1707
const
uint32_t
wr_instr_resv3_fld
: 6;
1708
uint32_t
dummywrclks
: 5;
1709
const
uint32_t
wr_instr_resv4_fld
: 3;
1710
};
1711
1713
typedef
volatile
struct
ALT_QSPI_DEVWR_s
ALT_QSPI_DEVWR_t
;
1714
#endif
/* __ASSEMBLY__ */
1715
1717
#define ALT_QSPI_DEVWR_RESET 0x00000002
1718
1719
#define ALT_QSPI_DEVWR_OFST 0x8
1720
1748
#define ALT_QSPI_DELAY_INIT_LSB 0
1749
1750
#define ALT_QSPI_DELAY_INIT_MSB 7
1751
1752
#define ALT_QSPI_DELAY_INIT_WIDTH 8
1753
1754
#define ALT_QSPI_DELAY_INIT_SET_MSK 0x000000ff
1755
1756
#define ALT_QSPI_DELAY_INIT_CLR_MSK 0xffffff00
1757
1758
#define ALT_QSPI_DELAY_INIT_RESET 0x0
1759
1760
#define ALT_QSPI_DELAY_INIT_GET(value) (((value) & 0x000000ff) >> 0)
1761
1762
#define ALT_QSPI_DELAY_INIT_SET(value) (((value) << 0) & 0x000000ff)
1763
1775
#define ALT_QSPI_DELAY_AFTER_LSB 8
1776
1777
#define ALT_QSPI_DELAY_AFTER_MSB 15
1778
1779
#define ALT_QSPI_DELAY_AFTER_WIDTH 8
1780
1781
#define ALT_QSPI_DELAY_AFTER_SET_MSK 0x0000ff00
1782
1783
#define ALT_QSPI_DELAY_AFTER_CLR_MSK 0xffff00ff
1784
1785
#define ALT_QSPI_DELAY_AFTER_RESET 0x0
1786
1787
#define ALT_QSPI_DELAY_AFTER_GET(value) (((value) & 0x0000ff00) >> 8)
1788
1789
#define ALT_QSPI_DELAY_AFTER_SET(value) (((value) << 8) & 0x0000ff00)
1790
1802
#define ALT_QSPI_DELAY_BTWN_LSB 16
1803
1804
#define ALT_QSPI_DELAY_BTWN_MSB 23
1805
1806
#define ALT_QSPI_DELAY_BTWN_WIDTH 8
1807
1808
#define ALT_QSPI_DELAY_BTWN_SET_MSK 0x00ff0000
1809
1810
#define ALT_QSPI_DELAY_BTWN_CLR_MSK 0xff00ffff
1811
1812
#define ALT_QSPI_DELAY_BTWN_RESET 0x0
1813
1814
#define ALT_QSPI_DELAY_BTWN_GET(value) (((value) & 0x00ff0000) >> 16)
1815
1816
#define ALT_QSPI_DELAY_BTWN_SET(value) (((value) << 16) & 0x00ff0000)
1817
1829
#define ALT_QSPI_DELAY_NSS_LSB 24
1830
1831
#define ALT_QSPI_DELAY_NSS_MSB 31
1832
1833
#define ALT_QSPI_DELAY_NSS_WIDTH 8
1834
1835
#define ALT_QSPI_DELAY_NSS_SET_MSK 0xff000000
1836
1837
#define ALT_QSPI_DELAY_NSS_CLR_MSK 0x00ffffff
1838
1839
#define ALT_QSPI_DELAY_NSS_RESET 0x0
1840
1841
#define ALT_QSPI_DELAY_NSS_GET(value) (((value) & 0xff000000) >> 24)
1842
1843
#define ALT_QSPI_DELAY_NSS_SET(value) (((value) << 24) & 0xff000000)
1844
1845
#ifndef __ASSEMBLY__
1846
1856
struct
ALT_QSPI_DELAY_s
1857
{
1858
uint32_t
init
: 8;
1859
uint32_t
after
: 8;
1860
uint32_t
btwn
: 8;
1861
uint32_t
nss
: 8;
1862
};
1863
1865
typedef
volatile
struct
ALT_QSPI_DELAY_s
ALT_QSPI_DELAY_t
;
1866
#endif
/* __ASSEMBLY__ */
1867
1869
#define ALT_QSPI_DELAY_RESET 0x00000000
1870
1871
#define ALT_QSPI_DELAY_OFST 0xc
1872
1905
#define ALT_QSPI_RDDATACAP_BYP_E_BYPASS 0x0
1906
1911
#define ALT_QSPI_RDDATACAP_BYP_E_NOBYPASS 0x1
1912
1914
#define ALT_QSPI_RDDATACAP_BYP_LSB 0
1915
1916
#define ALT_QSPI_RDDATACAP_BYP_MSB 0
1917
1918
#define ALT_QSPI_RDDATACAP_BYP_WIDTH 1
1919
1920
#define ALT_QSPI_RDDATACAP_BYP_SET_MSK 0x00000001
1921
1922
#define ALT_QSPI_RDDATACAP_BYP_CLR_MSK 0xfffffffe
1923
1924
#define ALT_QSPI_RDDATACAP_BYP_RESET 0x1
1925
1926
#define ALT_QSPI_RDDATACAP_BYP_GET(value) (((value) & 0x00000001) >> 0)
1927
1928
#define ALT_QSPI_RDDATACAP_BYP_SET(value) (((value) << 0) & 0x00000001)
1929
1939
#define ALT_QSPI_RDDATACAP_DELAY_LSB 1
1940
1941
#define ALT_QSPI_RDDATACAP_DELAY_MSB 4
1942
1943
#define ALT_QSPI_RDDATACAP_DELAY_WIDTH 4
1944
1945
#define ALT_QSPI_RDDATACAP_DELAY_SET_MSK 0x0000001e
1946
1947
#define ALT_QSPI_RDDATACAP_DELAY_CLR_MSK 0xffffffe1
1948
1949
#define ALT_QSPI_RDDATACAP_DELAY_RESET 0x0
1950
1951
#define ALT_QSPI_RDDATACAP_DELAY_GET(value) (((value) & 0x0000001e) >> 1)
1952
1953
#define ALT_QSPI_RDDATACAP_DELAY_SET(value) (((value) << 1) & 0x0000001e)
1954
1962
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_LSB 5
1963
1964
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_MSB 31
1965
1966
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_WIDTH 27
1967
1968
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET_MSK 0xffffffe0
1969
1970
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_CLR_MSK 0x0000001f
1971
1972
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_RESET 0x0
1973
1974
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_GET(value) (((value) & 0xffffffe0) >> 5)
1975
1976
#define ALT_QSPI_RDDATACAP_RD_DATA_RESV_FLD_SET(value) (((value) << 5) & 0xffffffe0)
1977
1978
#ifndef __ASSEMBLY__
1979
1989
struct
ALT_QSPI_RDDATACAP_s
1990
{
1991
uint32_t
byp
: 1;
1992
uint32_t
delay
: 4;
1993
const
uint32_t
rd_data_resv_fld
: 27;
1994
};
1995
1997
typedef
volatile
struct
ALT_QSPI_RDDATACAP_s
ALT_QSPI_RDDATACAP_t
;
1998
#endif
/* __ASSEMBLY__ */
1999
2001
#define ALT_QSPI_RDDATACAP_RESET 0x00000001
2002
2003
#define ALT_QSPI_RDDATACAP_OFST 0x10
2004
2027
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_LSB 0
2028
2029
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_MSB 3
2030
2031
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_WIDTH 4
2032
2033
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET_MSK 0x0000000f
2034
2035
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_CLR_MSK 0xfffffff0
2036
2037
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_RESET 0x2
2038
2039
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2040
2041
#define ALT_QSPI_DEVSZ_NUMADDRBYTES_SET(value) (((value) << 0) & 0x0000000f)
2042
2053
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_LSB 4
2054
2055
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_MSB 15
2056
2057
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_WIDTH 12
2058
2059
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET_MSK 0x0000fff0
2060
2061
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_CLR_MSK 0xffff000f
2062
2063
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_RESET 0x100
2064
2065
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_GET(value) (((value) & 0x0000fff0) >> 4)
2066
2067
#define ALT_QSPI_DEVSZ_BYTESPERDEVICEPAGE_SET(value) (((value) << 4) & 0x0000fff0)
2068
2080
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_LSB 16
2081
2082
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_MSB 20
2083
2084
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_WIDTH 5
2085
2086
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET_MSK 0x001f0000
2087
2088
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_CLR_MSK 0xffe0ffff
2089
2090
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_RESET 0x10
2091
2092
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_GET(value) (((value) & 0x001f0000) >> 16)
2093
2094
#define ALT_QSPI_DEVSZ_BYTESPERSUBSECTOR_SET(value) (((value) << 16) & 0x001f0000)
2095
2103
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_LSB 21
2104
2105
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_MSB 31
2106
2107
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_WIDTH 11
2108
2109
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET_MSK 0xffe00000
2110
2111
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_CLR_MSK 0x001fffff
2112
2113
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_RESET 0x0
2114
2115
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_GET(value) (((value) & 0xffe00000) >> 21)
2116
2117
#define ALT_QSPI_DEVSZ_DEV_SIZE_RESV_FLD_SET(value) (((value) << 21) & 0xffe00000)
2118
2119
#ifndef __ASSEMBLY__
2120
2130
struct
ALT_QSPI_DEVSZ_s
2131
{
2132
uint32_t
numaddrbytes
: 4;
2133
uint32_t
bytesperdevicepage
: 12;
2134
uint32_t
bytespersubsector
: 5;
2135
const
uint32_t
dev_size_resv_fld
: 11;
2136
};
2137
2139
typedef
volatile
struct
ALT_QSPI_DEVSZ_s
ALT_QSPI_DEVSZ_t
;
2140
#endif
/* __ASSEMBLY__ */
2141
2143
#define ALT_QSPI_DEVSZ_RESET 0x00101002
2144
2145
#define ALT_QSPI_DEVSZ_OFST 0x14
2146
2170
#define ALT_QSPI_SRAMPART_ADDR_LSB 0
2171
2172
#define ALT_QSPI_SRAMPART_ADDR_MSB 7
2173
2174
#define ALT_QSPI_SRAMPART_ADDR_WIDTH 8
2175
2176
#define ALT_QSPI_SRAMPART_ADDR_SET_MSK 0x000000ff
2177
2178
#define ALT_QSPI_SRAMPART_ADDR_CLR_MSK 0xffffff00
2179
2180
#define ALT_QSPI_SRAMPART_ADDR_RESET 0x80
2181
2182
#define ALT_QSPI_SRAMPART_ADDR_GET(value) (((value) & 0x000000ff) >> 0)
2183
2184
#define ALT_QSPI_SRAMPART_ADDR_SET(value) (((value) << 0) & 0x000000ff)
2185
2193
#define ALT_QSPI_SRAMPART_RESV_FLD_LSB 8
2194
2195
#define ALT_QSPI_SRAMPART_RESV_FLD_MSB 31
2196
2197
#define ALT_QSPI_SRAMPART_RESV_FLD_WIDTH 24
2198
2199
#define ALT_QSPI_SRAMPART_RESV_FLD_SET_MSK 0xffffff00
2200
2201
#define ALT_QSPI_SRAMPART_RESV_FLD_CLR_MSK 0x000000ff
2202
2203
#define ALT_QSPI_SRAMPART_RESV_FLD_RESET 0x0
2204
2205
#define ALT_QSPI_SRAMPART_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2206
2207
#define ALT_QSPI_SRAMPART_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2208
2209
#ifndef __ASSEMBLY__
2210
2220
struct
ALT_QSPI_SRAMPART_s
2221
{
2222
uint32_t
addr
: 8;
2223
const
uint32_t
resv_fld
: 24;
2224
};
2225
2227
typedef
volatile
struct
ALT_QSPI_SRAMPART_s
ALT_QSPI_SRAMPART_t
;
2228
#endif
/* __ASSEMBLY__ */
2229
2231
#define ALT_QSPI_SRAMPART_RESET 0x00000080
2232
2233
#define ALT_QSPI_SRAMPART_OFST 0x18
2234
2257
#define ALT_QSPI_INDADDRTRIG_ADDR_LSB 0
2258
2259
#define ALT_QSPI_INDADDRTRIG_ADDR_MSB 31
2260
2261
#define ALT_QSPI_INDADDRTRIG_ADDR_WIDTH 32
2262
2263
#define ALT_QSPI_INDADDRTRIG_ADDR_SET_MSK 0xffffffff
2264
2265
#define ALT_QSPI_INDADDRTRIG_ADDR_CLR_MSK 0x00000000
2266
2267
#define ALT_QSPI_INDADDRTRIG_ADDR_RESET 0x0
2268
2269
#define ALT_QSPI_INDADDRTRIG_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2270
2271
#define ALT_QSPI_INDADDRTRIG_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2272
2273
#ifndef __ASSEMBLY__
2274
2284
struct
ALT_QSPI_INDADDRTRIG_s
2285
{
2286
uint32_t
addr
: 32;
2287
};
2288
2290
typedef
volatile
struct
ALT_QSPI_INDADDRTRIG_s
ALT_QSPI_INDADDRTRIG_t
;
2291
#endif
/* __ASSEMBLY__ */
2292
2294
#define ALT_QSPI_INDADDRTRIG_RESET 0x00000000
2295
2296
#define ALT_QSPI_INDADDRTRIG_OFST 0x1c
2297
2323
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_LSB 0
2324
2325
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_MSB 3
2326
2327
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_WIDTH 4
2328
2329
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET_MSK 0x0000000f
2330
2331
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_CLR_MSK 0xfffffff0
2332
2333
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_RESET 0x0
2334
2335
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_GET(value) (((value) & 0x0000000f) >> 0)
2336
2337
#define ALT_QSPI_DMAPER_NUMSGLREQBYTES_SET(value) (((value) << 0) & 0x0000000f)
2338
2346
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_LSB 4
2347
2348
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_MSB 7
2349
2350
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_WIDTH 4
2351
2352
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET_MSK 0x000000f0
2353
2354
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_CLR_MSK 0xffffff0f
2355
2356
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_RESET 0x0
2357
2358
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_GET(value) (((value) & 0x000000f0) >> 4)
2359
2360
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV1_FLD_SET(value) (((value) << 4) & 0x000000f0)
2361
2374
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_LSB 8
2375
2376
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_MSB 11
2377
2378
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_WIDTH 4
2379
2380
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET_MSK 0x00000f00
2381
2382
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_CLR_MSK 0xfffff0ff
2383
2384
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_RESET 0x0
2385
2386
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_GET(value) (((value) & 0x00000f00) >> 8)
2387
2388
#define ALT_QSPI_DMAPER_NUMBURSTREQBYTES_SET(value) (((value) << 8) & 0x00000f00)
2389
2397
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_LSB 12
2398
2399
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_MSB 31
2400
2401
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_WIDTH 20
2402
2403
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET_MSK 0xfffff000
2404
2405
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_CLR_MSK 0x00000fff
2406
2407
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_RESET 0x0
2408
2409
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_GET(value) (((value) & 0xfffff000) >> 12)
2410
2411
#define ALT_QSPI_DMAPER_DMA_PERIPH_RESV2_FLD_SET(value) (((value) << 12) & 0xfffff000)
2412
2413
#ifndef __ASSEMBLY__
2414
2424
struct
ALT_QSPI_DMAPER_s
2425
{
2426
uint32_t
numsglreqbytes
: 4;
2427
const
uint32_t
dma_periph_resv1_fld
: 4;
2428
uint32_t
numburstreqbytes
: 4;
2429
const
uint32_t
dma_periph_resv2_fld
: 20;
2430
};
2431
2433
typedef
volatile
struct
ALT_QSPI_DMAPER_s
ALT_QSPI_DMAPER_t
;
2434
#endif
/* __ASSEMBLY__ */
2435
2437
#define ALT_QSPI_DMAPER_RESET 0x00000000
2438
2439
#define ALT_QSPI_DMAPER_OFST 0x20
2440
2461
#define ALT_QSPI_REMAPADDR_VALUE_LSB 0
2462
2463
#define ALT_QSPI_REMAPADDR_VALUE_MSB 31
2464
2465
#define ALT_QSPI_REMAPADDR_VALUE_WIDTH 32
2466
2467
#define ALT_QSPI_REMAPADDR_VALUE_SET_MSK 0xffffffff
2468
2469
#define ALT_QSPI_REMAPADDR_VALUE_CLR_MSK 0x00000000
2470
2471
#define ALT_QSPI_REMAPADDR_VALUE_RESET 0x0
2472
2473
#define ALT_QSPI_REMAPADDR_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
2474
2475
#define ALT_QSPI_REMAPADDR_VALUE_SET(value) (((value) << 0) & 0xffffffff)
2476
2477
#ifndef __ASSEMBLY__
2478
2488
struct
ALT_QSPI_REMAPADDR_s
2489
{
2490
uint32_t
value
: 32;
2491
};
2492
2494
typedef
volatile
struct
ALT_QSPI_REMAPADDR_s
ALT_QSPI_REMAPADDR_t
;
2495
#endif
/* __ASSEMBLY__ */
2496
2498
#define ALT_QSPI_REMAPADDR_RESET 0x00000000
2499
2500
#define ALT_QSPI_REMAPADDR_OFST 0x24
2501
2523
#define ALT_QSPI_MODBIT_MOD_LSB 0
2524
2525
#define ALT_QSPI_MODBIT_MOD_MSB 7
2526
2527
#define ALT_QSPI_MODBIT_MOD_WIDTH 8
2528
2529
#define ALT_QSPI_MODBIT_MOD_SET_MSK 0x000000ff
2530
2531
#define ALT_QSPI_MODBIT_MOD_CLR_MSK 0xffffff00
2532
2533
#define ALT_QSPI_MODBIT_MOD_RESET 0x0
2534
2535
#define ALT_QSPI_MODBIT_MOD_GET(value) (((value) & 0x000000ff) >> 0)
2536
2537
#define ALT_QSPI_MODBIT_MOD_SET(value) (((value) << 0) & 0x000000ff)
2538
2546
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_LSB 8
2547
2548
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_MSB 31
2549
2550
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_WIDTH 24
2551
2552
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET_MSK 0xffffff00
2553
2554
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_CLR_MSK 0x000000ff
2555
2556
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_RESET 0x0
2557
2558
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
2559
2560
#define ALT_QSPI_MODBIT_MOD_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
2561
2562
#ifndef __ASSEMBLY__
2563
2573
struct
ALT_QSPI_MODBIT_s
2574
{
2575
uint32_t
mode
: 8;
2576
const
uint32_t
mode_resv_fld
: 24;
2577
};
2578
2580
typedef
volatile
struct
ALT_QSPI_MODBIT_s
ALT_QSPI_MODBIT_t
;
2581
#endif
/* __ASSEMBLY__ */
2582
2584
#define ALT_QSPI_MODBIT_RESET 0x00000000
2585
2586
#define ALT_QSPI_MODBIT_OFST 0x28
2587
2608
#define ALT_QSPI_SRAMFILL_INDRDPART_LSB 0
2609
2610
#define ALT_QSPI_SRAMFILL_INDRDPART_MSB 15
2611
2612
#define ALT_QSPI_SRAMFILL_INDRDPART_WIDTH 16
2613
2614
#define ALT_QSPI_SRAMFILL_INDRDPART_SET_MSK 0x0000ffff
2615
2616
#define ALT_QSPI_SRAMFILL_INDRDPART_CLR_MSK 0xffff0000
2617
2618
#define ALT_QSPI_SRAMFILL_INDRDPART_RESET 0x0
2619
2620
#define ALT_QSPI_SRAMFILL_INDRDPART_GET(value) (((value) & 0x0000ffff) >> 0)
2621
2622
#define ALT_QSPI_SRAMFILL_INDRDPART_SET(value) (((value) << 0) & 0x0000ffff)
2623
2633
#define ALT_QSPI_SRAMFILL_INDWRPART_LSB 16
2634
2635
#define ALT_QSPI_SRAMFILL_INDWRPART_MSB 31
2636
2637
#define ALT_QSPI_SRAMFILL_INDWRPART_WIDTH 16
2638
2639
#define ALT_QSPI_SRAMFILL_INDWRPART_SET_MSK 0xffff0000
2640
2641
#define ALT_QSPI_SRAMFILL_INDWRPART_CLR_MSK 0x0000ffff
2642
2643
#define ALT_QSPI_SRAMFILL_INDWRPART_RESET 0x0
2644
2645
#define ALT_QSPI_SRAMFILL_INDWRPART_GET(value) (((value) & 0xffff0000) >> 16)
2646
2647
#define ALT_QSPI_SRAMFILL_INDWRPART_SET(value) (((value) << 16) & 0xffff0000)
2648
2649
#ifndef __ASSEMBLY__
2650
2660
struct
ALT_QSPI_SRAMFILL_s
2661
{
2662
const
uint32_t
indrdpart
: 16;
2663
const
uint32_t
indwrpart
: 16;
2664
};
2665
2667
typedef
volatile
struct
ALT_QSPI_SRAMFILL_s
ALT_QSPI_SRAMFILL_t
;
2668
#endif
/* __ASSEMBLY__ */
2669
2671
#define ALT_QSPI_SRAMFILL_RESET 0x00000000
2672
2673
#define ALT_QSPI_SRAMFILL_OFST 0x2c
2674
2695
#define ALT_QSPI_TXTHRESH_LEVEL_LSB 0
2696
2697
#define ALT_QSPI_TXTHRESH_LEVEL_MSB 3
2698
2699
#define ALT_QSPI_TXTHRESH_LEVEL_WIDTH 4
2700
2701
#define ALT_QSPI_TXTHRESH_LEVEL_SET_MSK 0x0000000f
2702
2703
#define ALT_QSPI_TXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2704
2705
#define ALT_QSPI_TXTHRESH_LEVEL_RESET 0x1
2706
2707
#define ALT_QSPI_TXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2708
2709
#define ALT_QSPI_TXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2710
2718
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_LSB 4
2719
2720
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_MSB 31
2721
2722
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_WIDTH 28
2723
2724
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2725
2726
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2727
2728
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_RESET 0x0
2729
2730
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2731
2732
#define ALT_QSPI_TXTHRESH_TX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2733
2734
#ifndef __ASSEMBLY__
2735
2745
struct
ALT_QSPI_TXTHRESH_s
2746
{
2747
uint32_t
level
: 4;
2748
const
uint32_t
tx_thresh_resv_fld
: 28;
2749
};
2750
2752
typedef
volatile
struct
ALT_QSPI_TXTHRESH_s
ALT_QSPI_TXTHRESH_t
;
2753
#endif
/* __ASSEMBLY__ */
2754
2756
#define ALT_QSPI_TXTHRESH_RESET 0x00000001
2757
2758
#define ALT_QSPI_TXTHRESH_OFST 0x30
2759
2782
#define ALT_QSPI_RXTHRESH_LEVEL_LSB 0
2783
2784
#define ALT_QSPI_RXTHRESH_LEVEL_MSB 3
2785
2786
#define ALT_QSPI_RXTHRESH_LEVEL_WIDTH 4
2787
2788
#define ALT_QSPI_RXTHRESH_LEVEL_SET_MSK 0x0000000f
2789
2790
#define ALT_QSPI_RXTHRESH_LEVEL_CLR_MSK 0xfffffff0
2791
2792
#define ALT_QSPI_RXTHRESH_LEVEL_RESET 0x1
2793
2794
#define ALT_QSPI_RXTHRESH_LEVEL_GET(value) (((value) & 0x0000000f) >> 0)
2795
2796
#define ALT_QSPI_RXTHRESH_LEVEL_SET(value) (((value) << 0) & 0x0000000f)
2797
2805
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_LSB 4
2806
2807
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_MSB 31
2808
2809
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_WIDTH 28
2810
2811
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET_MSK 0xfffffff0
2812
2813
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_CLR_MSK 0x0000000f
2814
2815
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_RESET 0x0
2816
2817
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_GET(value) (((value) & 0xfffffff0) >> 4)
2818
2819
#define ALT_QSPI_RXTHRESH_RX_THRESH_RESV_FLD_SET(value) (((value) << 4) & 0xfffffff0)
2820
2821
#ifndef __ASSEMBLY__
2822
2832
struct
ALT_QSPI_RXTHRESH_s
2833
{
2834
uint32_t
level
: 4;
2835
const
uint32_t
rx_thresh_resv_fld
: 28;
2836
};
2837
2839
typedef
volatile
struct
ALT_QSPI_RXTHRESH_s
ALT_QSPI_RXTHRESH_t
;
2840
#endif
/* __ASSEMBLY__ */
2841
2843
#define ALT_QSPI_RXTHRESH_RESET 0x00000001
2844
2845
#define ALT_QSPI_RXTHRESH_OFST 0x34
2846
2889
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_LSB 0
2890
2891
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_MSB 0
2892
2893
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_WIDTH 1
2894
2895
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET_MSK 0x00000001
2896
2897
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_CLR_MSK 0xfffffffe
2898
2899
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_RESET 0x0
2900
2901
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_GET(value) (((value) & 0x00000001) >> 0)
2902
2903
#define ALT_QSPI_IRQSTAT_MOD_M_FAIL_FLD_SET(value) (((value) << 0) & 0x00000001)
2904
2929
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0
2930
2935
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1
2936
2938
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1
2939
2940
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1
2941
2942
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1
2943
2944
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002
2945
2946
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd
2947
2948
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0
2949
2950
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
2951
2952
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
2953
2974
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0
2975
2980
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1
2981
2983
#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2
2984
2985
#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2
2986
2987
#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1
2988
2989
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004
2990
2991
#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb
2992
2993
#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0
2994
2995
#define ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
2996
2997
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
2998
3020
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0
3021
3026
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1
3027
3029
#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3
3030
3031
#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3
3032
3033
#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1
3034
3035
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008
3036
3037
#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7
3038
3039
#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0
3040
3041
#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3042
3043
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3044
3065
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0
3066
3071
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1
3072
3074
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4
3075
3076
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4
3077
3078
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1
3079
3080
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010
3081
3082
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef
3083
3084
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0
3085
3086
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3087
3088
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3089
3111
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0
3112
3117
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1
3118
3120
#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5
3121
3122
#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5
3123
3124
#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1
3125
3126
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020
3127
3128
#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf
3129
3130
#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0
3131
3132
#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3133
3134
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3135
3156
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0
3157
3162
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1
3163
3165
#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6
3166
3167
#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6
3168
3169
#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1
3170
3171
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040
3172
3173
#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf
3174
3175
#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0
3176
3177
#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3178
3179
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3180
3205
#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0
3206
3211
#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1
3212
3214
#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7
3215
3216
#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7
3217
3218
#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1
3219
3220
#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080
3221
3222
#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f
3223
3224
#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0
3225
3226
#define ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3227
3228
#define ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3229
3251
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0
3252
3257
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1
3258
3260
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8
3261
3262
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8
3263
3264
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1
3265
3266
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100
3267
3268
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff
3269
3270
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1
3271
3272
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3273
3274
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3275
3297
#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0
3298
3303
#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1
3304
3306
#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9
3307
3308
#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9
3309
3310
#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1
3311
3312
#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200
3313
3314
#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff
3315
3316
#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0
3317
3318
#define ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3319
3320
#define ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3321
3343
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0
3344
3349
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1
3350
3352
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10
3353
3354
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10
3355
3356
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1
3357
3358
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400
3359
3360
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff
3361
3362
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0
3363
3364
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3365
3366
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
3367
3389
#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0
3390
3395
#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1
3396
3398
#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11
3399
3400
#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11
3401
3402
#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1
3403
3404
#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800
3405
3406
#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff
3407
3408
#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0
3409
3410
#define ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
3411
3412
#define ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800)
3413
3435
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0
3436
3441
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1
3442
3444
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12
3445
3446
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12
3447
3448
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1
3449
3450
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000
3451
3452
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff
3453
3454
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0
3455
3456
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
3457
3458
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
3459
3467
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_LSB 13
3468
3469
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_MSB 31
3470
3471
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_WIDTH 19
3472
3473
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET_MSK 0xffffe000
3474
3475
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_CLR_MSK 0x00001fff
3476
3477
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_RESET 0x0
3478
3479
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
3480
3481
#define ALT_QSPI_IRQSTAT_IRQ_STAT_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
3482
3483
#ifndef __ASSEMBLY__
3484
3494
struct
ALT_QSPI_IRQSTAT_s
3495
{
3496
uint32_t
mode_m_fail_fld
: 1;
3497
uint32_t
underflowdet
: 1;
3498
uint32_t
indopdone
: 1;
3499
uint32_t
indrdreject
: 1;
3500
uint32_t
protwrattempt
: 1;
3501
uint32_t
illegalacc
: 1;
3502
uint32_t
indxfrlvl
: 1;
3503
uint32_t
rxover
: 1;
3504
uint32_t
txthreshcmp
: 1;
3505
uint32_t
txfull
: 1;
3506
uint32_t
rxthreshcmp
: 1;
3507
uint32_t
rxfull
: 1;
3508
uint32_t
indsramfull
: 1;
3509
const
uint32_t
irq_stat_resv_fld
: 19;
3510
};
3511
3513
typedef
volatile
struct
ALT_QSPI_IRQSTAT_s
ALT_QSPI_IRQSTAT_t
;
3514
#endif
/* __ASSEMBLY__ */
3515
3517
#define ALT_QSPI_IRQSTAT_RESET 0x00000100
3518
3519
#define ALT_QSPI_IRQSTAT_OFST 0x40
3520
3555
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_LSB 0
3556
3557
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_MSB 0
3558
3559
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_WIDTH 1
3560
3561
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET_MSK 0x00000001
3562
3563
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_CLR_MSK 0xfffffffe
3564
3565
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_RESET 0x0
3566
3567
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_GET(value) (((value) & 0x00000001) >> 0)
3568
3569
#define ALT_QSPI_IRQMSK_MOD_M_FAIL_MSK_FLD_SET(value) (((value) << 0) & 0x00000001)
3570
3589
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0
3590
3595
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1
3596
3598
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB 1
3599
3600
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB 1
3601
3602
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH 1
3603
3604
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK 0x00000002
3605
3606
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK 0xfffffffd
3607
3608
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET 0x0
3609
3610
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1)
3611
3612
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002)
3613
3632
#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0
3633
3638
#define ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1
3639
3641
#define ALT_QSPI_IRQMSK_INDOPDONE_LSB 2
3642
3643
#define ALT_QSPI_IRQMSK_INDOPDONE_MSB 2
3644
3645
#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH 1
3646
3647
#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK 0x00000004
3648
3649
#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK 0xfffffffb
3650
3651
#define ALT_QSPI_IRQMSK_INDOPDONE_RESET 0x0
3652
3653
#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2)
3654
3655
#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value) (((value) << 2) & 0x00000004)
3656
3675
#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0
3676
3681
#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1
3682
3684
#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB 3
3685
3686
#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB 3
3687
3688
#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH 1
3689
3690
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK 0x00000008
3691
3692
#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK 0xfffffff7
3693
3694
#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET 0x0
3695
3696
#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3)
3697
3698
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008)
3699
3718
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0
3719
3724
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1
3725
3727
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB 4
3728
3729
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB 4
3730
3731
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH 1
3732
3733
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK 0x00000010
3734
3735
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK 0xffffffef
3736
3737
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET 0x0
3738
3739
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4)
3740
3741
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010)
3742
3761
#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0
3762
3767
#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1
3768
3770
#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB 5
3771
3772
#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB 5
3773
3774
#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH 1
3775
3776
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK 0x00000020
3777
3778
#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK 0xffffffdf
3779
3780
#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET 0x0
3781
3782
#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5)
3783
3784
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020)
3785
3804
#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0
3805
3810
#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1
3811
3813
#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB 6
3814
3815
#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB 6
3816
3817
#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH 1
3818
3819
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK 0x00000040
3820
3821
#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK 0xffffffbf
3822
3823
#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET 0x0
3824
3825
#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6)
3826
3827
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040)
3828
3847
#define ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0
3848
3853
#define ALT_QSPI_IRQMSK_RXOVER_E_END 0x1
3854
3856
#define ALT_QSPI_IRQMSK_RXOVER_LSB 7
3857
3858
#define ALT_QSPI_IRQMSK_RXOVER_MSB 7
3859
3860
#define ALT_QSPI_IRQMSK_RXOVER_WIDTH 1
3861
3862
#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK 0x00000080
3863
3864
#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK 0xffffff7f
3865
3866
#define ALT_QSPI_IRQMSK_RXOVER_RESET 0x0
3867
3868
#define ALT_QSPI_IRQMSK_RXOVER_GET(value) (((value) & 0x00000080) >> 7)
3869
3870
#define ALT_QSPI_IRQMSK_RXOVER_SET(value) (((value) << 7) & 0x00000080)
3871
3890
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0
3891
3896
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1
3897
3899
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB 8
3900
3901
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB 8
3902
3903
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH 1
3904
3905
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK 0x00000100
3906
3907
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK 0xfffffeff
3908
3909
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET 0x0
3910
3911
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8)
3912
3913
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100)
3914
3933
#define ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0
3934
3939
#define ALT_QSPI_IRQMSK_TXFULL_E_END 0x1
3940
3942
#define ALT_QSPI_IRQMSK_TXFULL_LSB 9
3943
3944
#define ALT_QSPI_IRQMSK_TXFULL_MSB 9
3945
3946
#define ALT_QSPI_IRQMSK_TXFULL_WIDTH 1
3947
3948
#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK 0x00000200
3949
3950
#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK 0xfffffdff
3951
3952
#define ALT_QSPI_IRQMSK_TXFULL_RESET 0x0
3953
3954
#define ALT_QSPI_IRQMSK_TXFULL_GET(value) (((value) & 0x00000200) >> 9)
3955
3956
#define ALT_QSPI_IRQMSK_TXFULL_SET(value) (((value) << 9) & 0x00000200)
3957
3976
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0
3977
3982
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1
3983
3985
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB 10
3986
3987
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB 10
3988
3989
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH 1
3990
3991
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK 0x00000400
3992
3993
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK 0xfffffbff
3994
3995
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET 0x0
3996
3997
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10)
3998
3999
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400)
4000
4019
#define ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0
4020
4025
#define ALT_QSPI_IRQMSK_RXFULL_E_END 0x1
4026
4028
#define ALT_QSPI_IRQMSK_RXFULL_LSB 11
4029
4030
#define ALT_QSPI_IRQMSK_RXFULL_MSB 11
4031
4032
#define ALT_QSPI_IRQMSK_RXFULL_WIDTH 1
4033
4034
#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK 0x00000800
4035
4036
#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK 0xfffff7ff
4037
4038
#define ALT_QSPI_IRQMSK_RXFULL_RESET 0x0
4039
4040
#define ALT_QSPI_IRQMSK_RXFULL_GET(value) (((value) & 0x00000800) >> 11)
4041
4042
#define ALT_QSPI_IRQMSK_RXFULL_SET(value) (((value) << 11) & 0x00000800)
4043
4062
#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0
4063
4068
#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1
4069
4071
#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB 12
4072
4073
#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB 12
4074
4075
#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH 1
4076
4077
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK 0x00001000
4078
4079
#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK 0xffffefff
4080
4081
#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET 0x0
4082
4083
#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12)
4084
4085
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000)
4086
4094
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_LSB 13
4095
4096
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_MSB 31
4097
4098
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_WIDTH 19
4099
4100
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET_MSK 0xffffe000
4101
4102
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_CLR_MSK 0x00001fff
4103
4104
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_RESET 0x0
4105
4106
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_GET(value) (((value) & 0xffffe000) >> 13)
4107
4108
#define ALT_QSPI_IRQMSK_IRQ_MSK_RESV_FLD_SET(value) (((value) << 13) & 0xffffe000)
4109
4110
#ifndef __ASSEMBLY__
4111
4121
struct
ALT_QSPI_IRQMSK_s
4122
{
4123
uint32_t
mode_m_fail_mask_fld
: 1;
4124
uint32_t
underflowdet
: 1;
4125
uint32_t
indopdone
: 1;
4126
uint32_t
indrdreject
: 1;
4127
uint32_t
protwrattempt
: 1;
4128
uint32_t
illegalacc
: 1;
4129
uint32_t
indxfrlvl
: 1;
4130
uint32_t
rxover
: 1;
4131
uint32_t
txthreshcmp
: 1;
4132
uint32_t
txfull
: 1;
4133
uint32_t
rxthreshcmp
: 1;
4134
uint32_t
rxfull
: 1;
4135
uint32_t
indsramfull
: 1;
4136
const
uint32_t
irq_mask_resv_fld
: 19;
4137
};
4138
4140
typedef
volatile
struct
ALT_QSPI_IRQMSK_s
ALT_QSPI_IRQMSK_t
;
4141
#endif
/* __ASSEMBLY__ */
4142
4144
#define ALT_QSPI_IRQMSK_RESET 0x00000000
4145
4146
#define ALT_QSPI_IRQMSK_OFST 0x44
4147
4169
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_LSB 0
4170
4171
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_MSB 31
4172
4173
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_WIDTH 32
4174
4175
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4176
4177
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4178
4179
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_RESET 0x0
4180
4181
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4182
4183
#define ALT_QSPI_LOWWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4184
4185
#ifndef __ASSEMBLY__
4186
4196
struct
ALT_QSPI_LOWWRPROT_s
4197
{
4198
uint32_t
subsector
: 32;
4199
};
4200
4202
typedef
volatile
struct
ALT_QSPI_LOWWRPROT_s
ALT_QSPI_LOWWRPROT_t
;
4203
#endif
/* __ASSEMBLY__ */
4204
4206
#define ALT_QSPI_LOWWRPROT_RESET 0x00000000
4207
4208
#define ALT_QSPI_LOWWRPROT_OFST 0x50
4209
4231
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_LSB 0
4232
4233
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_MSB 31
4234
4235
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_WIDTH 32
4236
4237
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET_MSK 0xffffffff
4238
4239
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_CLR_MSK 0x00000000
4240
4241
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_RESET 0x0
4242
4243
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_GET(value) (((value) & 0xffffffff) >> 0)
4244
4245
#define ALT_QSPI_UPPWRPROT_SUBSECTOR_SET(value) (((value) << 0) & 0xffffffff)
4246
4247
#ifndef __ASSEMBLY__
4248
4258
struct
ALT_QSPI_UPPWRPROT_s
4259
{
4260
uint32_t
subsector
: 32;
4261
};
4262
4264
typedef
volatile
struct
ALT_QSPI_UPPWRPROT_s
ALT_QSPI_UPPWRPROT_t
;
4265
#endif
/* __ASSEMBLY__ */
4266
4268
#define ALT_QSPI_UPPWRPROT_RESET 0x00000000
4269
4270
#define ALT_QSPI_UPPWRPROT_OFST 0x54
4271
4308
#define ALT_QSPI_WRPROT_INV_E_DIS 0x0
4309
4314
#define ALT_QSPI_WRPROT_INV_E_EN 0x1
4315
4317
#define ALT_QSPI_WRPROT_INV_LSB 0
4318
4319
#define ALT_QSPI_WRPROT_INV_MSB 0
4320
4321
#define ALT_QSPI_WRPROT_INV_WIDTH 1
4322
4323
#define ALT_QSPI_WRPROT_INV_SET_MSK 0x00000001
4324
4325
#define ALT_QSPI_WRPROT_INV_CLR_MSK 0xfffffffe
4326
4327
#define ALT_QSPI_WRPROT_INV_RESET 0x0
4328
4329
#define ALT_QSPI_WRPROT_INV_GET(value) (((value) & 0x00000001) >> 0)
4330
4331
#define ALT_QSPI_WRPROT_INV_SET(value) (((value) << 0) & 0x00000001)
4332
4356
#define ALT_QSPI_WRPROT_EN_E_DIS 0x0
4357
4362
#define ALT_QSPI_WRPROT_EN_E_EN 0x1
4363
4365
#define ALT_QSPI_WRPROT_EN_LSB 1
4366
4367
#define ALT_QSPI_WRPROT_EN_MSB 1
4368
4369
#define ALT_QSPI_WRPROT_EN_WIDTH 1
4370
4371
#define ALT_QSPI_WRPROT_EN_SET_MSK 0x00000002
4372
4373
#define ALT_QSPI_WRPROT_EN_CLR_MSK 0xfffffffd
4374
4375
#define ALT_QSPI_WRPROT_EN_RESET 0x0
4376
4377
#define ALT_QSPI_WRPROT_EN_GET(value) (((value) & 0x00000002) >> 1)
4378
4379
#define ALT_QSPI_WRPROT_EN_SET(value) (((value) << 1) & 0x00000002)
4380
4388
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_LSB 2
4389
4390
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_MSB 31
4391
4392
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_WIDTH 30
4393
4394
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET_MSK 0xfffffffc
4395
4396
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_CLR_MSK 0x00000003
4397
4398
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_RESET 0x0
4399
4400
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_GET(value) (((value) & 0xfffffffc) >> 2)
4401
4402
#define ALT_QSPI_WRPROT_WR_PROT_CTL_RESV_FLD_SET(value) (((value) << 2) & 0xfffffffc)
4403
4404
#ifndef __ASSEMBLY__
4405
4415
struct
ALT_QSPI_WRPROT_s
4416
{
4417
uint32_t
inv
: 1;
4418
uint32_t
en
: 1;
4419
const
uint32_t
wr_prot_ctrl_resv_fld
: 30;
4420
};
4421
4423
typedef
volatile
struct
ALT_QSPI_WRPROT_s
ALT_QSPI_WRPROT_t
;
4424
#endif
/* __ASSEMBLY__ */
4425
4427
#define ALT_QSPI_WRPROT_RESET 0x00000000
4428
4429
#define ALT_QSPI_WRPROT_OFST 0x58
4430
4470
#define ALT_QSPI_INDRD_START_E_DISD 0x0
4471
4476
#define ALT_QSPI_INDRD_START_E_END 0x1
4477
4479
#define ALT_QSPI_INDRD_START_LSB 0
4480
4481
#define ALT_QSPI_INDRD_START_MSB 0
4482
4483
#define ALT_QSPI_INDRD_START_WIDTH 1
4484
4485
#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001
4486
4487
#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe
4488
4489
#define ALT_QSPI_INDRD_START_RESET 0x0
4490
4491
#define ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0)
4492
4493
#define ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001)
4494
4515
#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0
4516
4521
#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1
4522
4524
#define ALT_QSPI_INDRD_CANCEL_LSB 1
4525
4526
#define ALT_QSPI_INDRD_CANCEL_MSB 1
4527
4528
#define ALT_QSPI_INDRD_CANCEL_WIDTH 1
4529
4530
#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002
4531
4532
#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd
4533
4534
#define ALT_QSPI_INDRD_CANCEL_RESET 0x0
4535
4536
#define ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
4537
4538
#define ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002)
4539
4560
#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0
4561
4566
#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1
4567
4569
#define ALT_QSPI_INDRD_RD_STAT_LSB 2
4570
4571
#define ALT_QSPI_INDRD_RD_STAT_MSB 2
4572
4573
#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1
4574
4575
#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004
4576
4577
#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb
4578
4579
#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0
4580
4581
#define ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2)
4582
4583
#define ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004)
4584
4606
#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0
4607
4612
#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1
4613
4615
#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3
4616
4617
#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3
4618
4619
#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1
4620
4621
#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008
4622
4623
#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7
4624
4625
#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0
4626
4627
#define ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3)
4628
4629
#define ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008)
4630
4651
#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0
4652
4657
#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1
4658
4660
#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4
4661
4662
#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4
4663
4664
#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1
4665
4666
#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010
4667
4668
#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef
4669
4670
#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0
4671
4672
#define ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4)
4673
4674
#define ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010)
4675
4697
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0
4698
4703
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1
4704
4706
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5
4707
4708
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5
4709
4710
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1
4711
4712
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020
4713
4714
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf
4715
4716
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0
4717
4718
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5)
4719
4720
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020)
4721
4734
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6
4735
4736
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7
4737
4738
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2
4739
4740
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0
4741
4742
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f
4743
4744
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0
4745
4746
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6)
4747
4748
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0)
4749
4757
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_LSB 8
4758
4759
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_MSB 31
4760
4761
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_WIDTH 24
4762
4763
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET_MSK 0xffffff00
4764
4765
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_CLR_MSK 0x000000ff
4766
4767
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_RESET 0x0
4768
4769
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_GET(value) (((value) & 0xffffff00) >> 8)
4770
4771
#define ALT_QSPI_INDRD_INDIR_RD_XFER_RESV_FLD_SET(value) (((value) << 8) & 0xffffff00)
4772
4773
#ifndef __ASSEMBLY__
4774
4784
struct
ALT_QSPI_INDRD_s
4785
{
4786
uint32_t
start
: 1;
4787
uint32_t
cancel
: 1;
4788
const
uint32_t
rd_status
: 1;
4789
uint32_t
sram_full
: 1;
4790
const
uint32_t
rd_queued
: 1;
4791
uint32_t
ind_ops_done_status
: 1;
4792
const
uint32_t
num_ind_ops_done
: 2;
4793
const
uint32_t
indir_rd_xfer_resv_fld
: 24;
4794
};
4795
4797
typedef
volatile
struct
ALT_QSPI_INDRD_s
ALT_QSPI_INDRD_t
;
4798
#endif
/* __ASSEMBLY__ */
4799
4801
#define ALT_QSPI_INDRD_RESET 0x00000000
4802
4803
#define ALT_QSPI_INDRD_OFST 0x60
4804
4826
#define ALT_QSPI_INDRDWATER_LEVEL_LSB 0
4827
4828
#define ALT_QSPI_INDRDWATER_LEVEL_MSB 31
4829
4830
#define ALT_QSPI_INDRDWATER_LEVEL_WIDTH 32
4831
4832
#define ALT_QSPI_INDRDWATER_LEVEL_SET_MSK 0xffffffff
4833
4834
#define ALT_QSPI_INDRDWATER_LEVEL_CLR_MSK 0x00000000
4835
4836
#define ALT_QSPI_INDRDWATER_LEVEL_RESET 0x0
4837
4838
#define ALT_QSPI_INDRDWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
4839
4840
#define ALT_QSPI_INDRDWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
4841
4842
#ifndef __ASSEMBLY__
4843
4853
struct
ALT_QSPI_INDRDWATER_s
4854
{
4855
uint32_t
level
: 32;
4856
};
4857
4859
typedef
volatile
struct
ALT_QSPI_INDRDWATER_s
ALT_QSPI_INDRDWATER_t
;
4860
#endif
/* __ASSEMBLY__ */
4861
4863
#define ALT_QSPI_INDRDWATER_RESET 0x00000000
4864
4865
#define ALT_QSPI_INDRDWATER_OFST 0x64
4866
4887
#define ALT_QSPI_INDRDSTADDR_ADDR_LSB 0
4888
4889
#define ALT_QSPI_INDRDSTADDR_ADDR_MSB 31
4890
4891
#define ALT_QSPI_INDRDSTADDR_ADDR_WIDTH 32
4892
4893
#define ALT_QSPI_INDRDSTADDR_ADDR_SET_MSK 0xffffffff
4894
4895
#define ALT_QSPI_INDRDSTADDR_ADDR_CLR_MSK 0x00000000
4896
4897
#define ALT_QSPI_INDRDSTADDR_ADDR_RESET 0x0
4898
4899
#define ALT_QSPI_INDRDSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
4900
4901
#define ALT_QSPI_INDRDSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
4902
4903
#ifndef __ASSEMBLY__
4904
4914
struct
ALT_QSPI_INDRDSTADDR_s
4915
{
4916
uint32_t
addr
: 32;
4917
};
4918
4920
typedef
volatile
struct
ALT_QSPI_INDRDSTADDR_s
ALT_QSPI_INDRDSTADDR_t
;
4921
#endif
/* __ASSEMBLY__ */
4922
4924
#define ALT_QSPI_INDRDSTADDR_RESET 0x00000000
4925
4926
#define ALT_QSPI_INDRDSTADDR_OFST 0x68
4927
4948
#define ALT_QSPI_INDRDCNT_VALUE_LSB 0
4949
4950
#define ALT_QSPI_INDRDCNT_VALUE_MSB 31
4951
4952
#define ALT_QSPI_INDRDCNT_VALUE_WIDTH 32
4953
4954
#define ALT_QSPI_INDRDCNT_VALUE_SET_MSK 0xffffffff
4955
4956
#define ALT_QSPI_INDRDCNT_VALUE_CLR_MSK 0x00000000
4957
4958
#define ALT_QSPI_INDRDCNT_VALUE_RESET 0x0
4959
4960
#define ALT_QSPI_INDRDCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
4961
4962
#define ALT_QSPI_INDRDCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
4963
4964
#ifndef __ASSEMBLY__
4965
4975
struct
ALT_QSPI_INDRDCNT_s
4976
{
4977
uint32_t
value
: 32;
4978
};
4979
4981
typedef
volatile
struct
ALT_QSPI_INDRDCNT_s
ALT_QSPI_INDRDCNT_t
;
4982
#endif
/* __ASSEMBLY__ */
4983
4985
#define ALT_QSPI_INDRDCNT_RESET 0x00000000
4986
4987
#define ALT_QSPI_INDRDCNT_OFST 0x6c
4988
5028
#define ALT_QSPI_INDWR_START_E_DISD 0x0
5029
5034
#define ALT_QSPI_INDWR_START_E_END 0x1
5035
5037
#define ALT_QSPI_INDWR_START_LSB 0
5038
5039
#define ALT_QSPI_INDWR_START_MSB 0
5040
5041
#define ALT_QSPI_INDWR_START_WIDTH 1
5042
5043
#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001
5044
5045
#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe
5046
5047
#define ALT_QSPI_INDWR_START_RESET 0x0
5048
5049
#define ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0)
5050
5051
#define ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001)
5052
5073
#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0
5074
5079
#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1
5080
5082
#define ALT_QSPI_INDWR_CANCEL_LSB 1
5083
5084
#define ALT_QSPI_INDWR_CANCEL_MSB 1
5085
5086
#define ALT_QSPI_INDWR_CANCEL_WIDTH 1
5087
5088
#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002
5089
5090
#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd
5091
5092
#define ALT_QSPI_INDWR_CANCEL_RESET 0x0
5093
5094
#define ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1)
5095
5096
#define ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002)
5097
5118
#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0
5119
5124
#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1
5125
5127
#define ALT_QSPI_INDWR_RDSTAT_LSB 2
5128
5129
#define ALT_QSPI_INDWR_RDSTAT_MSB 2
5130
5131
#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1
5132
5133
#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004
5134
5135
#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb
5136
5137
#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0
5138
5139
#define ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2)
5140
5141
#define ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004)
5142
5150
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_LSB 3
5151
5152
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_MSB 3
5153
5154
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_WIDTH 1
5155
5156
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET_MSK 0x00000008
5157
5158
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_CLR_MSK 0xfffffff7
5159
5160
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_RESET 0x0
5161
5162
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_GET(value) (((value) & 0x00000008) >> 3)
5163
5164
#define ALT_QSPI_INDWR_INDIR_WR_RSVD_FLD_SET(value) (((value) << 3) & 0x00000008)
5165
5186
#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0
5187
5192
#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1
5193
5195
#define ALT_QSPI_INDWR_RDQUEUED_LSB 4
5196
5197
#define ALT_QSPI_INDWR_RDQUEUED_MSB 4
5198
5199
#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1
5200
5201
#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010
5202
5203
#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef
5204
5205
#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0
5206
5207
#define ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4)
5208
5209
#define ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010)
5210
5232
#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0
5233
5238
#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1
5239
5241
#define ALT_QSPI_INDWR_INDDONE_LSB 5
5242
5243
#define ALT_QSPI_INDWR_INDDONE_MSB 5
5244
5245
#define ALT_QSPI_INDWR_INDDONE_WIDTH 1
5246
5247
#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020
5248
5249
#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf
5250
5251
#define ALT_QSPI_INDWR_INDDONE_RESET 0x0
5252
5253
#define ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5)
5254
5255
#define ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020)
5256
5269
#define ALT_QSPI_INDWR_INDCNT_LSB 6
5270
5271
#define ALT_QSPI_INDWR_INDCNT_MSB 7
5272
5273
#define ALT_QSPI_INDWR_INDCNT_WIDTH 2
5274
5275
#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0
5276
5277
#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f
5278
5279
#define ALT_QSPI_INDWR_INDCNT_RESET 0x0
5280
5281
#define ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6)
5282
5283
#define ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0)
5284
5292
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_LSB 8
5293
5294
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_MSB 31
5295
5296
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_WIDTH 24
5297
5298
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET_MSK 0xffffff00
5299
5300
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_CLR_MSK 0x000000ff
5301
5302
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_RESET 0x0
5303
5304
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_GET(value) (((value) & 0xffffff00) >> 8)
5305
5306
#define ALT_QSPI_INDWR_INDIR_WR_XFER_RESV2_FLD_SET(value) (((value) << 8) & 0xffffff00)
5307
5308
#ifndef __ASSEMBLY__
5309
5319
struct
ALT_QSPI_INDWR_s
5320
{
5321
uint32_t
start
: 1;
5322
uint32_t
cancel
: 1;
5323
const
uint32_t
rdstat
: 1;
5324
const
uint32_t
indir_wr_rsvd_fld
: 1;
5325
const
uint32_t
rdqueued
: 1;
5326
uint32_t
inddone
: 1;
5327
const
uint32_t
indcnt
: 2;
5328
const
uint32_t
indir_wr_xfer_resv2_fld
: 24;
5329
};
5330
5332
typedef
volatile
struct
ALT_QSPI_INDWR_s
ALT_QSPI_INDWR_t
;
5333
#endif
/* __ASSEMBLY__ */
5334
5336
#define ALT_QSPI_INDWR_RESET 0x00000000
5337
5338
#define ALT_QSPI_INDWR_OFST 0x70
5339
5362
#define ALT_QSPI_INDWRWATER_LEVEL_LSB 0
5363
5364
#define ALT_QSPI_INDWRWATER_LEVEL_MSB 31
5365
5366
#define ALT_QSPI_INDWRWATER_LEVEL_WIDTH 32
5367
5368
#define ALT_QSPI_INDWRWATER_LEVEL_SET_MSK 0xffffffff
5369
5370
#define ALT_QSPI_INDWRWATER_LEVEL_CLR_MSK 0x00000000
5371
5372
#define ALT_QSPI_INDWRWATER_LEVEL_RESET 0xffffffff
5373
5374
#define ALT_QSPI_INDWRWATER_LEVEL_GET(value) (((value) & 0xffffffff) >> 0)
5375
5376
#define ALT_QSPI_INDWRWATER_LEVEL_SET(value) (((value) << 0) & 0xffffffff)
5377
5378
#ifndef __ASSEMBLY__
5379
5389
struct
ALT_QSPI_INDWRWATER_s
5390
{
5391
uint32_t
level
: 32;
5392
};
5393
5395
typedef
volatile
struct
ALT_QSPI_INDWRWATER_s
ALT_QSPI_INDWRWATER_t
;
5396
#endif
/* __ASSEMBLY__ */
5397
5399
#define ALT_QSPI_INDWRWATER_RESET 0xffffffff
5400
5401
#define ALT_QSPI_INDWRWATER_OFST 0x74
5402
5423
#define ALT_QSPI_INDWRSTADDR_ADDR_LSB 0
5424
5425
#define ALT_QSPI_INDWRSTADDR_ADDR_MSB 31
5426
5427
#define ALT_QSPI_INDWRSTADDR_ADDR_WIDTH 32
5428
5429
#define ALT_QSPI_INDWRSTADDR_ADDR_SET_MSK 0xffffffff
5430
5431
#define ALT_QSPI_INDWRSTADDR_ADDR_CLR_MSK 0x00000000
5432
5433
#define ALT_QSPI_INDWRSTADDR_ADDR_RESET 0x0
5434
5435
#define ALT_QSPI_INDWRSTADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
5436
5437
#define ALT_QSPI_INDWRSTADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
5438
5439
#ifndef __ASSEMBLY__
5440
5450
struct
ALT_QSPI_INDWRSTADDR_s
5451
{
5452
uint32_t
addr
: 32;
5453
};
5454
5456
typedef
volatile
struct
ALT_QSPI_INDWRSTADDR_s
ALT_QSPI_INDWRSTADDR_t
;
5457
#endif
/* __ASSEMBLY__ */
5458
5460
#define ALT_QSPI_INDWRSTADDR_RESET 0x00000000
5461
5462
#define ALT_QSPI_INDWRSTADDR_OFST 0x78
5463
5484
#define ALT_QSPI_INDWRCNT_VALUE_LSB 0
5485
5486
#define ALT_QSPI_INDWRCNT_VALUE_MSB 31
5487
5488
#define ALT_QSPI_INDWRCNT_VALUE_WIDTH 32
5489
5490
#define ALT_QSPI_INDWRCNT_VALUE_SET_MSK 0xffffffff
5491
5492
#define ALT_QSPI_INDWRCNT_VALUE_CLR_MSK 0x00000000
5493
5494
#define ALT_QSPI_INDWRCNT_VALUE_RESET 0x0
5495
5496
#define ALT_QSPI_INDWRCNT_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
5497
5498
#define ALT_QSPI_INDWRCNT_VALUE_SET(value) (((value) << 0) & 0xffffffff)
5499
5500
#ifndef __ASSEMBLY__
5501
5511
struct
ALT_QSPI_INDWRCNT_s
5512
{
5513
uint32_t
value
: 32;
5514
};
5515
5517
typedef
volatile
struct
ALT_QSPI_INDWRCNT_s
ALT_QSPI_INDWRCNT_t
;
5518
#endif
/* __ASSEMBLY__ */
5519
5521
#define ALT_QSPI_INDWRCNT_RESET 0x00000000
5522
5523
#define ALT_QSPI_INDWRCNT_OFST 0x7c
5524
5566
#define ALT_QSPI_FLSHCMD_EXECCMD_E_NOACTION 0x0
5567
5572
#define ALT_QSPI_FLSHCMD_EXECCMD_E_EXECUTE 0x1
5573
5575
#define ALT_QSPI_FLSHCMD_EXECCMD_LSB 0
5576
5577
#define ALT_QSPI_FLSHCMD_EXECCMD_MSB 0
5578
5579
#define ALT_QSPI_FLSHCMD_EXECCMD_WIDTH 1
5580
5581
#define ALT_QSPI_FLSHCMD_EXECCMD_SET_MSK 0x00000001
5582
5583
#define ALT_QSPI_FLSHCMD_EXECCMD_CLR_MSK 0xfffffffe
5584
5585
#define ALT_QSPI_FLSHCMD_EXECCMD_RESET 0x0
5586
5587
#define ALT_QSPI_FLSHCMD_EXECCMD_GET(value) (((value) & 0x00000001) >> 0)
5588
5589
#define ALT_QSPI_FLSHCMD_EXECCMD_SET(value) (((value) << 0) & 0x00000001)
5590
5611
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_NOACTION 0x0
5612
5617
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_E_EXECUTESTAT 0x1
5618
5620
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_LSB 1
5621
5622
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_MSB 1
5623
5624
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_WIDTH 1
5625
5626
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET_MSK 0x00000002
5627
5628
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_CLR_MSK 0xfffffffd
5629
5630
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_RESET 0x0
5631
5632
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_GET(value) (((value) & 0x00000002) >> 1)
5633
5634
#define ALT_QSPI_FLSHCMD_CMDEXECSTAT_SET(value) (((value) << 1) & 0x00000002)
5635
5643
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_LSB 2
5644
5645
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_MSB 6
5646
5647
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_WIDTH 5
5648
5649
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET_MSK 0x0000007c
5650
5651
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_CLR_MSK 0xffffff83
5652
5653
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_RESET 0x0
5654
5655
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_GET(value) (((value) & 0x0000007c) >> 2)
5656
5657
#define ALT_QSPI_FLSHCMD_FLSH_CMD_CNTRL_RESV1_FLD_SET(value) (((value) << 2) & 0x0000007c)
5658
5669
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_LSB 7
5670
5671
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_MSB 11
5672
5673
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_WIDTH 5
5674
5675
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET_MSK 0x00000f80
5676
5677
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_CLR_MSK 0xfffff07f
5678
5679
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_RESET 0x0
5680
5681
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_GET(value) (((value) & 0x00000f80) >> 7)
5682
5683
#define ALT_QSPI_FLSHCMD_NUMDUMMYBYTES_SET(value) (((value) << 7) & 0x00000f80)
5684
5712
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE1 0x0
5713
5718
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE2 0x1
5719
5724
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE3 0x2
5725
5730
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE4 0x3
5731
5736
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE5 0x4
5737
5742
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE6 0x5
5743
5748
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE7 0x6
5749
5754
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_E_WRBYTE8 0x7
5755
5757
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_LSB 12
5758
5759
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_MSB 14
5760
5761
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_WIDTH 3
5762
5763
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET_MSK 0x00007000
5764
5765
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_CLR_MSK 0xffff8fff
5766
5767
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_RESET 0x0
5768
5769
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_GET(value) (((value) & 0x00007000) >> 12)
5770
5771
#define ALT_QSPI_FLSHCMD_NUMWRDATABYTES_SET(value) (((value) << 12) & 0x00007000)
5772
5794
#define ALT_QSPI_FLSHCMD_ENWRDATA_E_NOACTION 0x0
5795
5800
#define ALT_QSPI_FLSHCMD_ENWRDATA_E_WRDATABYTES 0x1
5801
5803
#define ALT_QSPI_FLSHCMD_ENWRDATA_LSB 15
5804
5805
#define ALT_QSPI_FLSHCMD_ENWRDATA_MSB 15
5806
5807
#define ALT_QSPI_FLSHCMD_ENWRDATA_WIDTH 1
5808
5809
#define ALT_QSPI_FLSHCMD_ENWRDATA_SET_MSK 0x00008000
5810
5811
#define ALT_QSPI_FLSHCMD_ENWRDATA_CLR_MSK 0xffff7fff
5812
5813
#define ALT_QSPI_FLSHCMD_ENWRDATA_RESET 0x0
5814
5815
#define ALT_QSPI_FLSHCMD_ENWRDATA_GET(value) (((value) & 0x00008000) >> 15)
5816
5817
#define ALT_QSPI_FLSHCMD_ENWRDATA_SET(value) (((value) << 15) & 0x00008000)
5818
5844
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE1 0x0
5845
5850
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE2 0x1
5851
5856
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE3 0x2
5857
5862
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_E_ADDRBYTE4 0x3
5863
5865
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_LSB 16
5866
5867
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_MSB 17
5868
5869
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_WIDTH 2
5870
5871
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET_MSK 0x00030000
5872
5873
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_CLR_MSK 0xfffcffff
5874
5875
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_RESET 0x0
5876
5877
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_GET(value) (((value) & 0x00030000) >> 16)
5878
5879
#define ALT_QSPI_FLSHCMD_NUMADDRBYTES_SET(value) (((value) << 16) & 0x00030000)
5880
5902
#define ALT_QSPI_FLSHCMD_ENMODBIT_E_DISD 0x0
5903
5908
#define ALT_QSPI_FLSHCMD_ENMODBIT_E_END 0x1
5909
5911
#define ALT_QSPI_FLSHCMD_ENMODBIT_LSB 18
5912
5913
#define ALT_QSPI_FLSHCMD_ENMODBIT_MSB 18
5914
5915
#define ALT_QSPI_FLSHCMD_ENMODBIT_WIDTH 1
5916
5917
#define ALT_QSPI_FLSHCMD_ENMODBIT_SET_MSK 0x00040000
5918
5919
#define ALT_QSPI_FLSHCMD_ENMODBIT_CLR_MSK 0xfffbffff
5920
5921
#define ALT_QSPI_FLSHCMD_ENMODBIT_RESET 0x0
5922
5923
#define ALT_QSPI_FLSHCMD_ENMODBIT_GET(value) (((value) & 0x00040000) >> 18)
5924
5925
#define ALT_QSPI_FLSHCMD_ENMODBIT_SET(value) (((value) << 18) & 0x00040000)
5926
5948
#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_DISD 0x0
5949
5954
#define ALT_QSPI_FLSHCMD_ENCMDADDR_E_END 0x1
5955
5957
#define ALT_QSPI_FLSHCMD_ENCMDADDR_LSB 19
5958
5959
#define ALT_QSPI_FLSHCMD_ENCMDADDR_MSB 19
5960
5961
#define ALT_QSPI_FLSHCMD_ENCMDADDR_WIDTH 1
5962
5963
#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET_MSK 0x00080000
5964
5965
#define ALT_QSPI_FLSHCMD_ENCMDADDR_CLR_MSK 0xfff7ffff
5966
5967
#define ALT_QSPI_FLSHCMD_ENCMDADDR_RESET 0x0
5968
5969
#define ALT_QSPI_FLSHCMD_ENCMDADDR_GET(value) (((value) & 0x00080000) >> 19)
5970
5971
#define ALT_QSPI_FLSHCMD_ENCMDADDR_SET(value) (((value) << 19) & 0x00080000)
5972
6000
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE1 0x0
6001
6006
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE2 0x1
6007
6012
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE3 0x2
6013
6018
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE4 0x3
6019
6024
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE5 0x4
6025
6030
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE6 0x5
6031
6036
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE7 0x6
6037
6042
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_E_RDBYTE8 0x7
6043
6045
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_LSB 20
6046
6047
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_MSB 22
6048
6049
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_WIDTH 3
6050
6051
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET_MSK 0x00700000
6052
6053
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_CLR_MSK 0xff8fffff
6054
6055
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_RESET 0x0
6056
6057
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_GET(value) (((value) & 0x00700000) >> 20)
6058
6059
#define ALT_QSPI_FLSHCMD_NUMRDDATABYTES_SET(value) (((value) << 20) & 0x00700000)
6060
6082
#define ALT_QSPI_FLSHCMD_ENRDDATA_E_NOACTION 0x0
6083
6088
#define ALT_QSPI_FLSHCMD_ENRDDATA_E_EN 0x1
6089
6091
#define ALT_QSPI_FLSHCMD_ENRDDATA_LSB 23
6092
6093
#define ALT_QSPI_FLSHCMD_ENRDDATA_MSB 23
6094
6095
#define ALT_QSPI_FLSHCMD_ENRDDATA_WIDTH 1
6096
6097
#define ALT_QSPI_FLSHCMD_ENRDDATA_SET_MSK 0x00800000
6098
6099
#define ALT_QSPI_FLSHCMD_ENRDDATA_CLR_MSK 0xff7fffff
6100
6101
#define ALT_QSPI_FLSHCMD_ENRDDATA_RESET 0x0
6102
6103
#define ALT_QSPI_FLSHCMD_ENRDDATA_GET(value) (((value) & 0x00800000) >> 23)
6104
6105
#define ALT_QSPI_FLSHCMD_ENRDDATA_SET(value) (((value) << 23) & 0x00800000)
6106
6126
#define ALT_QSPI_FLSHCMD_CMDOPCODE_LSB 24
6127
6128
#define ALT_QSPI_FLSHCMD_CMDOPCODE_MSB 31
6129
6130
#define ALT_QSPI_FLSHCMD_CMDOPCODE_WIDTH 8
6131
6132
#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET_MSK 0xff000000
6133
6134
#define ALT_QSPI_FLSHCMD_CMDOPCODE_CLR_MSK 0x00ffffff
6135
6136
#define ALT_QSPI_FLSHCMD_CMDOPCODE_RESET 0x0
6137
6138
#define ALT_QSPI_FLSHCMD_CMDOPCODE_GET(value) (((value) & 0xff000000) >> 24)
6139
6140
#define ALT_QSPI_FLSHCMD_CMDOPCODE_SET(value) (((value) << 24) & 0xff000000)
6141
6142
#ifndef __ASSEMBLY__
6143
6153
struct
ALT_QSPI_FLSHCMD_s
6154
{
6155
uint32_t
execcmd
: 1;
6156
const
uint32_t
cmdexecstat
: 1;
6157
const
uint32_t
flash_cmd_cntrl_resv1_fld
: 5;
6158
uint32_t
numdummybytes
: 5;
6159
uint32_t
numwrdatabytes
: 3;
6160
uint32_t
enwrdata
: 1;
6161
uint32_t
numaddrbytes
: 2;
6162
uint32_t
enmodebit
: 1;
6163
uint32_t
encmdaddr
: 1;
6164
uint32_t
numrddatabytes
: 3;
6165
uint32_t
enrddata
: 1;
6166
uint32_t
cmdopcode
: 8;
6167
};
6168
6170
typedef
volatile
struct
ALT_QSPI_FLSHCMD_s
ALT_QSPI_FLSHCMD_t
;
6171
#endif
/* __ASSEMBLY__ */
6172
6174
#define ALT_QSPI_FLSHCMD_RESET 0x00000000
6175
6176
#define ALT_QSPI_FLSHCMD_OFST 0x90
6177
6200
#define ALT_QSPI_FLSHCMDADDR_ADDR_LSB 0
6201
6202
#define ALT_QSPI_FLSHCMDADDR_ADDR_MSB 31
6203
6204
#define ALT_QSPI_FLSHCMDADDR_ADDR_WIDTH 32
6205
6206
#define ALT_QSPI_FLSHCMDADDR_ADDR_SET_MSK 0xffffffff
6207
6208
#define ALT_QSPI_FLSHCMDADDR_ADDR_CLR_MSK 0x00000000
6209
6210
#define ALT_QSPI_FLSHCMDADDR_ADDR_RESET 0x0
6211
6212
#define ALT_QSPI_FLSHCMDADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
6213
6214
#define ALT_QSPI_FLSHCMDADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
6215
6216
#ifndef __ASSEMBLY__
6217
6227
struct
ALT_QSPI_FLSHCMDADDR_s
6228
{
6229
uint32_t
addr
: 32;
6230
};
6231
6233
typedef
volatile
struct
ALT_QSPI_FLSHCMDADDR_s
ALT_QSPI_FLSHCMDADDR_t
;
6234
#endif
/* __ASSEMBLY__ */
6235
6237
#define ALT_QSPI_FLSHCMDADDR_RESET 0x00000000
6238
6239
#define ALT_QSPI_FLSHCMDADDR_OFST 0x94
6240
6263
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_LSB 0
6264
6265
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_MSB 31
6266
6267
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_WIDTH 32
6268
6269
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET_MSK 0xffffffff
6270
6271
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_CLR_MSK 0x00000000
6272
6273
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_RESET 0x0
6274
6275
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6276
6277
#define ALT_QSPI_FLSHCMDRDDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6278
6279
#ifndef __ASSEMBLY__
6280
6290
struct
ALT_QSPI_FLSHCMDRDDATALO_s
6291
{
6292
uint32_t
data
: 32;
6293
};
6294
6296
typedef
volatile
struct
ALT_QSPI_FLSHCMDRDDATALO_s
ALT_QSPI_FLSHCMDRDDATALO_t
;
6297
#endif
/* __ASSEMBLY__ */
6298
6300
#define ALT_QSPI_FLSHCMDRDDATALO_RESET 0x00000000
6301
6302
#define ALT_QSPI_FLSHCMDRDDATALO_OFST 0xa0
6303
6328
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_LSB 0
6329
6330
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_MSB 31
6331
6332
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_WIDTH 32
6333
6334
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET_MSK 0xffffffff
6335
6336
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_CLR_MSK 0x00000000
6337
6338
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_RESET 0x0
6339
6340
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6341
6342
#define ALT_QSPI_FLSHCMDRDDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6343
6344
#ifndef __ASSEMBLY__
6345
6355
struct
ALT_QSPI_FLSHCMDRDDATAUP_s
6356
{
6357
uint32_t
data
: 32;
6358
};
6359
6361
typedef
volatile
struct
ALT_QSPI_FLSHCMDRDDATAUP_s
ALT_QSPI_FLSHCMDRDDATAUP_t
;
6362
#endif
/* __ASSEMBLY__ */
6363
6365
#define ALT_QSPI_FLSHCMDRDDATAUP_RESET 0x00000000
6366
6367
#define ALT_QSPI_FLSHCMDRDDATAUP_OFST 0xa4
6368
6392
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_LSB 0
6393
6394
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_MSB 31
6395
6396
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_WIDTH 32
6397
6398
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET_MSK 0xffffffff
6399
6400
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_CLR_MSK 0x00000000
6401
6402
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_RESET 0x0
6403
6404
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6405
6406
#define ALT_QSPI_FLSHCMDWRDATALO_DATA_SET(value) (((value) << 0) & 0xffffffff)
6407
6408
#ifndef __ASSEMBLY__
6409
6419
struct
ALT_QSPI_FLSHCMDWRDATALO_s
6420
{
6421
uint32_t
data
: 32;
6422
};
6423
6425
typedef
volatile
struct
ALT_QSPI_FLSHCMDWRDATALO_s
ALT_QSPI_FLSHCMDWRDATALO_t
;
6426
#endif
/* __ASSEMBLY__ */
6427
6429
#define ALT_QSPI_FLSHCMDWRDATALO_RESET 0x00000000
6430
6431
#define ALT_QSPI_FLSHCMDWRDATALO_OFST 0xa8
6432
6456
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_LSB 0
6457
6458
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_MSB 31
6459
6460
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_WIDTH 32
6461
6462
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET_MSK 0xffffffff
6463
6464
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_CLR_MSK 0x00000000
6465
6466
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_RESET 0x0
6467
6468
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_GET(value) (((value) & 0xffffffff) >> 0)
6469
6470
#define ALT_QSPI_FLSHCMDWRDATAUP_DATA_SET(value) (((value) << 0) & 0xffffffff)
6471
6472
#ifndef __ASSEMBLY__
6473
6483
struct
ALT_QSPI_FLSHCMDWRDATAUP_s
6484
{
6485
uint32_t
data
: 32;
6486
};
6487
6489
typedef
volatile
struct
ALT_QSPI_FLSHCMDWRDATAUP_s
ALT_QSPI_FLSHCMDWRDATAUP_t
;
6490
#endif
/* __ASSEMBLY__ */
6491
6493
#define ALT_QSPI_FLSHCMDWRDATAUP_RESET 0x00000000
6494
6495
#define ALT_QSPI_FLSHCMDWRDATAUP_OFST 0xac
6496
6515
#define ALT_QSPI_MODULEID_VALUE_LSB 0
6516
6517
#define ALT_QSPI_MODULEID_VALUE_MSB 24
6518
6519
#define ALT_QSPI_MODULEID_VALUE_WIDTH 25
6520
6521
#define ALT_QSPI_MODULEID_VALUE_SET_MSK 0x01ffffff
6522
6523
#define ALT_QSPI_MODULEID_VALUE_CLR_MSK 0xfe000000
6524
6525
#define ALT_QSPI_MODULEID_VALUE_RESET 0x1001
6526
6527
#define ALT_QSPI_MODULEID_VALUE_GET(value) (((value) & 0x01ffffff) >> 0)
6528
6529
#define ALT_QSPI_MODULEID_VALUE_SET(value) (((value) << 0) & 0x01ffffff)
6530
6538
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_LSB 25
6539
6540
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_MSB 31
6541
6542
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_WIDTH 7
6543
6544
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET_MSK 0xfe000000
6545
6546
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_CLR_MSK 0x01ffffff
6547
6548
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_RESET 0x0
6549
6550
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_GET(value) (((value) & 0xfe000000) >> 25)
6551
6552
#define ALT_QSPI_MODULEID_MOD_ID_RESV_FLD_SET(value) (((value) << 25) & 0xfe000000)
6553
6554
#ifndef __ASSEMBLY__
6555
6565
struct
ALT_QSPI_MODULEID_s
6566
{
6567
const
uint32_t
value
: 25;
6568
const
uint32_t
mod_id_resv_fld
: 7;
6569
};
6570
6572
typedef
volatile
struct
ALT_QSPI_MODULEID_s
ALT_QSPI_MODULEID_t
;
6573
#endif
/* __ASSEMBLY__ */
6574
6576
#define ALT_QSPI_MODULEID_RESET 0x00001001
6577
6578
#define ALT_QSPI_MODULEID_OFST 0xfc
6579
6580
#ifndef __ASSEMBLY__
6581
6591
struct
ALT_QSPI_s
6592
{
6593
volatile
ALT_QSPI_CFG_t
cfg
;
6594
volatile
ALT_QSPI_DEVRD_t
devrd
;
6595
volatile
ALT_QSPI_DEVWR_t
devwr
;
6596
volatile
ALT_QSPI_DELAY_t
delay
;
6597
volatile
ALT_QSPI_RDDATACAP_t
rddatacap
;
6598
volatile
ALT_QSPI_DEVSZ_t
devsz
;
6599
volatile
ALT_QSPI_SRAMPART_t
srampart
;
6600
volatile
ALT_QSPI_INDADDRTRIG_t
indaddrtrig
;
6601
volatile
ALT_QSPI_DMAPER_t
dmaper
;
6602
volatile
ALT_QSPI_REMAPADDR_t
remapaddr
;
6603
volatile
ALT_QSPI_MODBIT_t
modebit
;
6604
volatile
ALT_QSPI_SRAMFILL_t
sramfill
;
6605
volatile
ALT_QSPI_TXTHRESH_t
txthresh
;
6606
volatile
ALT_QSPI_RXTHRESH_t
rxthresh
;
6607
volatile
uint32_t
_pad_0x38_0x3f
[2];
6608
volatile
ALT_QSPI_IRQSTAT_t
irqstat
;
6609
volatile
ALT_QSPI_IRQMSK_t
irqmask
;
6610
volatile
uint32_t
_pad_0x48_0x4f
[2];
6611
volatile
ALT_QSPI_LOWWRPROT_t
lowwrprot
;
6612
volatile
ALT_QSPI_UPPWRPROT_t
uppwrprot
;
6613
volatile
ALT_QSPI_WRPROT_t
wrprot
;
6614
volatile
uint32_t
_pad_0x5c_0x5f
;
6615
volatile
ALT_QSPI_INDRD_t
indrd
;
6616
volatile
ALT_QSPI_INDRDWATER_t
indrdwater
;
6617
volatile
ALT_QSPI_INDRDSTADDR_t
indrdstaddr
;
6618
volatile
ALT_QSPI_INDRDCNT_t
indrdcnt
;
6619
volatile
ALT_QSPI_INDWR_t
indwr
;
6620
volatile
ALT_QSPI_INDWRWATER_t
indwrwater
;
6621
volatile
ALT_QSPI_INDWRSTADDR_t
indwrstaddr
;
6622
volatile
ALT_QSPI_INDWRCNT_t
indwrcnt
;
6623
volatile
uint32_t
_pad_0x80_0x8f
[4];
6624
volatile
ALT_QSPI_FLSHCMD_t
flashcmd
;
6625
volatile
ALT_QSPI_FLSHCMDADDR_t
flashcmdaddr
;
6626
volatile
uint32_t
_pad_0x98_0x9f
[2];
6627
volatile
ALT_QSPI_FLSHCMDRDDATALO_t
flashcmdrddatalo
;
6628
volatile
ALT_QSPI_FLSHCMDRDDATAUP_t
flashcmdrddataup
;
6629
volatile
ALT_QSPI_FLSHCMDWRDATALO_t
flashcmdwrdatalo
;
6630
volatile
ALT_QSPI_FLSHCMDWRDATAUP_t
flashcmdwrdataup
;
6631
volatile
uint32_t
_pad_0xb0_0xfb
[19];
6632
volatile
ALT_QSPI_MODULEID_t
moduleid
;
6633
};
6634
6636
typedef
volatile
struct
ALT_QSPI_s
ALT_QSPI_t
;
6638
struct
ALT_QSPI_raw_s
6639
{
6640
volatile
uint32_t
cfg
;
6641
volatile
uint32_t
devrd
;
6642
volatile
uint32_t
devwr
;
6643
volatile
uint32_t
delay
;
6644
volatile
uint32_t
rddatacap
;
6645
volatile
uint32_t
devsz
;
6646
volatile
uint32_t
srampart
;
6647
volatile
uint32_t
indaddrtrig
;
6648
volatile
uint32_t
dmaper
;
6649
volatile
uint32_t
remapaddr
;
6650
volatile
uint32_t
modebit
;
6651
volatile
uint32_t
sramfill
;
6652
volatile
uint32_t
txthresh
;
6653
volatile
uint32_t
rxthresh
;
6654
volatile
uint32_t
_pad_0x38_0x3f
[2];
6655
volatile
uint32_t
irqstat
;
6656
volatile
uint32_t
irqmask
;
6657
volatile
uint32_t
_pad_0x48_0x4f
[2];
6658
volatile
uint32_t
lowwrprot
;
6659
volatile
uint32_t
uppwrprot
;
6660
volatile
uint32_t
wrprot
;
6661
volatile
uint32_t
_pad_0x5c_0x5f
;
6662
volatile
uint32_t
indrd
;
6663
volatile
uint32_t
indrdwater
;
6664
volatile
uint32_t
indrdstaddr
;
6665
volatile
uint32_t
indrdcnt
;
6666
volatile
uint32_t
indwr
;
6667
volatile
uint32_t
indwrwater
;
6668
volatile
uint32_t
indwrstaddr
;
6669
volatile
uint32_t
indwrcnt
;
6670
volatile
uint32_t
_pad_0x80_0x8f
[4];
6671
volatile
uint32_t
flashcmd
;
6672
volatile
uint32_t
flashcmdaddr
;
6673
volatile
uint32_t
_pad_0x98_0x9f
[2];
6674
volatile
uint32_t
flashcmdrddatalo
;
6675
volatile
uint32_t
flashcmdrddataup
;
6676
volatile
uint32_t
flashcmdwrdatalo
;
6677
volatile
uint32_t
flashcmdwrdataup
;
6678
volatile
uint32_t
_pad_0xb0_0xfb
[19];
6679
volatile
uint32_t
moduleid
;
6680
};
6681
6683
typedef
volatile
struct
ALT_QSPI_raw_s
ALT_QSPI_raw_t
;
6684
#endif
/* __ASSEMBLY__ */
6685
6687
#ifdef __cplusplus
6688
}
6689
#endif
/* __cplusplus */
6690
#endif
/* __ALT_SOCAL_QSPI_H__ */
6691
include
soc_a10
socal
alt_qspi.h
Generated on Tue Sep 8 2015 13:33:02 for Altera SoCAL by
1.8.2