Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ECC_WDataecc1bus

Description

The msb bit for the register is configured based on DAT parameter (RAM word size). Unimplemented bytes of this register will be reserved.

Register Layout

Bits Access Reset Description
[5:0] RW 0x0 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS
[7:6] ??? 0x0 UNDEFINED
[13:8] RW 0x0 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS
[15:14] ??? 0x0 UNDEFINED
[21:16] RW 0x0 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS
[23:22] ??? 0x0 UNDEFINED
[29:24] RW 0x0 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS
[31:30] ??? 0x0 UNDEFINED

Field : ECC_WDataecc4BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB   0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB   5
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH   6
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK   0x0000003f
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK   0xffffffc0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET   0x0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value)   (((value) & 0x0000003f) >> 0)
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value)   (((value) << 0) & 0x0000003f)
 

Field : ECC_WDataecc5BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB   8
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB   13
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH   6
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK   0x00003f00
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK   0xffffc0ff
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET   0x0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value)   (((value) & 0x00003f00) >> 8)
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value)   (((value) << 8) & 0x00003f00)
 

Field : ECC_WDataecc6BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB   16
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB   21
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH   6
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK   0x003f0000
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK   0xffc0ffff
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET   0x0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value)   (((value) & 0x003f0000) >> 16)
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value)   (((value) << 16) & 0x003f0000)
 

Field : ECC_WDataecc7BUS

Eccdata from the register will be written to the RAM.

Field Access Macros:

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB   24
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB   29
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH   6
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK   0x3f000000
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK   0xc0ffffff
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET   0x0
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value)   (((value) & 0x3f000000) >> 24)
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value)   (((value) << 24) & 0x3f000000)
 

Data Structures

struct  ALT_ECC_NAND_ECC_WDATAECC1BUS_s
 

Macros

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_RESET   0x00000000
 
#define ALT_ECC_NAND_ECC_WDATAECC1BUS_OFST   0x70
 

Typedefs

typedef struct
ALT_ECC_NAND_ECC_WDATAECC1BUS_s 
ALT_ECC_NAND_ECC_WDATAECC1BUS_t
 

Data Structure Documentation

struct ALT_ECC_NAND_ECC_WDATAECC1BUS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_NAND_ECC_WDATAECC1BUS.

Data Fields
uint32_t ECC_WDataecc4BUS: 6 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS
uint32_t __pad0__: 2 UNDEFINED
uint32_t ECC_WDataecc5BUS: 6 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS
uint32_t __pad1__: 2 UNDEFINED
uint32_t ECC_WDataecc6BUS: 6 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS
uint32_t __pad2__: 2 UNDEFINED
uint32_t ECC_WDataecc7BUS: 6 ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS
uint32_t __pad3__: 2 UNDEFINED

Macro Definitions

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB   5

The Most Significant Bit (MSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH   6

The width in bits of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK   0x0000003f

The mask used to set the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK   0xffffffc0

The mask used to clear the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET   0x0

The reset value of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET (   value)    (((value) & 0x0000003f) >> 0)

Extracts the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS field value from a register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET (   value)    (((value) << 0) & 0x0000003f)

Produces a ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS register field value suitable for setting the register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB   13

The Most Significant Bit (MSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH   6

The width in bits of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK   0x00003f00

The mask used to set the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK   0xffffc0ff

The mask used to clear the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET   0x0

The reset value of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET (   value)    (((value) & 0x00003f00) >> 8)

Extracts the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS field value from a register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET (   value)    (((value) << 8) & 0x00003f00)

Produces a ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS register field value suitable for setting the register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB   16

The Least Significant Bit (LSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB   21

The Most Significant Bit (MSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH   6

The width in bits of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK   0x003f0000

The mask used to set the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK   0xffc0ffff

The mask used to clear the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET   0x0

The reset value of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET (   value)    (((value) & 0x003f0000) >> 16)

Extracts the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS field value from a register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET (   value)    (((value) << 16) & 0x003f0000)

Produces a ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS register field value suitable for setting the register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB   24

The Least Significant Bit (LSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB   29

The Most Significant Bit (MSB) position of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH   6

The width in bits of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK   0x3f000000

The mask used to set the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK   0xc0ffffff

The mask used to clear the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET   0x0

The reset value of the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET (   value)    (((value) & 0x3f000000) >> 24)

Extracts the ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS field value from a register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET (   value)    (((value) << 24) & 0x3f000000)

Produces a ALT_ECC_NAND_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS register field value suitable for setting the register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_RESET   0x00000000

The reset value of the ALT_ECC_NAND_ECC_WDATAECC1BUS register.

#define ALT_ECC_NAND_ECC_WDATAECC1BUS_OFST   0x70

The byte offset of the ALT_ECC_NAND_ECC_WDATAECC1BUS register from the beginning of the component.

Typedef Documentation