![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set, the interrupt output is asserted high. The fields are each cleared by writing a 1 to the field. Note that bit fields 7 thru 11 are only valid when legacy SPI mode is active.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | ??? | 0x0 | UNDEFINED |
[1] | RW | 0x0 | Underflow Detected |
[2] | RW | 0x0 | Indirect Operation Complete |
[3] | RW | 0x0 | Indirect Read Reject |
[4] | RW | 0x0 | Protected Area Write Attempt |
[5] | RW | 0x0 | Illegal AHB Access Detected |
[6] | RW | 0x0 | Transfer Watermark Reached |
[7] | RW | 0x0 | Receive Overflow |
[8] | RW | 0x1 | Transmit FIFO Compared to Threshold |
[9] | RW | 0x0 | Transmit FIFO Full |
[10] | RW | 0x0 | Receive FIFO Compared to Threshold |
[11] | RW | 0x0 | Receive FIFO Full |
[12] | RW | 0x0 | Indirect Read Partition overflow |
[31:13] | ??? | 0x0 | UNDEFINED |
Field : Underflow Detected - underflowdet | ||||||||||
An underflow is detected when an attempt to transfer data is made when the transmit FIFO is empty. This may occur when the AHB write data is being supplied too slowly to keep up with the requested write operation. This bit is reset only by a system reset and cleared only when the register is read. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Indirect Operation Complete - indopdone | ||||||||||
Controller has completed last triggered indirect operation Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_QSPI_IRQSTAT_INDOPDONE_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : Indirect Read Reject - indrdreject | ||||||||||
Indirect operation was requested but could not be accepted. Two indirect operations already in storage. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_QSPI_IRQSTAT_INDRDREJECT_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Protected Area Write Attempt - protwrattempt | ||||||||||
Write to protected area was attempted and rejected. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : Illegal AHB Access Detected - illegalacc | ||||||||||
Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_QSPI_IRQSTAT_ILLEGALACC_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : Transfer Watermark Reached - indxfrlvl | ||||||||||
Indirect Transfer Watermark Level Reached Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_QSPI_IRQSTAT_INDXFRLVL_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : Receive Overflow - rxover | ||||||||||
This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX FIFO occurs coincident with a register read this flag will remain set. 0 : no overflow has been detected. 1 : an overflow has occurred. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_LSB 7 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_MSB 7 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_QSPI_IRQSTAT_RXOVER_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : Transmit FIFO Compared to Threshold - txthreshcmp | ||||||||||
Indicates the number of entries in the transmit FIFO with respect to the threshold specified in the TXTHRESH register. Only relevant in SPI legacy mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : Transmit FIFO Full - txfull | ||||||||||
Indicates that the transmit FIFO is full or not. Only relevant in SPI legacy mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_LSB 9 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_MSB 9 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_GET(value) (((value) & 0x00000200) >> 9) | |||||||||
#define | ALT_QSPI_IRQSTAT_TXFULL_SET(value) (((value) << 9) & 0x00000200) | |||||||||
Field : Receive FIFO Compared to Threshold - rxthreshcmp | ||||||||||
Indicates the number of entries in the receive FIFO with respect to the threshold specified in the RXTHRESH register. Only relevant in SPI legacy mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET(value) (((value) & 0x00000400) >> 10) | |||||||||
#define | ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET(value) (((value) << 10) & 0x00000400) | |||||||||
Field : Receive FIFO Full - rxfull | ||||||||||
Indicates that the receive FIFO is full or not. Only relevant in SPI legacy mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_LSB 11 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_MSB 11 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_GET(value) (((value) & 0x00000800) >> 11) | |||||||||
#define | ALT_QSPI_IRQSTAT_RXFULL_SET(value) (((value) << 11) & 0x00000800) | |||||||||
Field : Indirect Read Partition overflow - indsramfull | ||||||||||
Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_GET(value) (((value) & 0x00001000) >> 12) | |||||||||
#define | ALT_QSPI_IRQSTAT_INDSRAMFULL_SET(value) (((value) << 12) & 0x00001000) | |||||||||
Data Structures | |
struct | ALT_QSPI_IRQSTAT_s |
Macros | |
#define | ALT_QSPI_IRQSTAT_OFST 0x40 |
Typedefs | |
typedef struct ALT_QSPI_IRQSTAT_s | ALT_QSPI_IRQSTAT_t |
struct ALT_QSPI_IRQSTAT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_IRQSTAT.
Data Fields | ||
---|---|---|
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | underflowdet: 1 | Underflow Detected |
uint32_t | indopdone: 1 | Indirect Operation Complete |
uint32_t | indrdreject: 1 | Indirect Read Reject |
uint32_t | protwrattempt: 1 | Protected Area Write Attempt |
uint32_t | illegalacc: 1 | Illegal AHB Access Detected |
uint32_t | indxfrlvl: 1 | Transfer Watermark Reached |
uint32_t | rxover: 1 | Receive Overflow |
uint32_t | txthreshcmp: 1 | Transmit FIFO Compared to Threshold |
uint32_t | txfull: 1 | Transmit FIFO Full |
uint32_t | rxthreshcmp: 1 | Receive FIFO Compared to Threshold |
uint32_t | rxfull: 1 | Receive FIFO Full |
uint32_t | indsramfull: 1 | Indirect Read Partition overflow |
uint32_t | __pad1__: 19 | UNDEFINED |
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_UNDERFLOW 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
Underflow
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_E_NOUNDERFLOW 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_UNDERFLOWDET
No Underflow
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET_MSK 0x00000002 |
The mask used to set the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_UNDERFLOWDET register field.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_QSPI_IRQSTAT_UNDERFLOWDET field value from a register.
#define ALT_QSPI_IRQSTAT_UNDERFLOWDET_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_QSPI_IRQSTAT_UNDERFLOWDET register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_INDIRECTOP 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
Completed Indirect Operation
#define ALT_QSPI_IRQSTAT_INDOPDONE_E_NOINDIRECTOP 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDOPDONE
No Indirect Operation
#define ALT_QSPI_IRQSTAT_INDOPDONE_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field.
#define ALT_QSPI_IRQSTAT_INDOPDONE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDOPDONE register field.
#define ALT_QSPI_IRQSTAT_INDOPDONE_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_INDOPDONE register field.
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET_MSK 0x00000004 |
The mask used to set the ALT_QSPI_IRQSTAT_INDOPDONE register field value.
#define ALT_QSPI_IRQSTAT_INDOPDONE_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_QSPI_IRQSTAT_INDOPDONE register field value.
#define ALT_QSPI_IRQSTAT_INDOPDONE_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_INDOPDONE register field.
#define ALT_QSPI_IRQSTAT_INDOPDONE_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_QSPI_IRQSTAT_INDOPDONE field value from a register.
#define ALT_QSPI_IRQSTAT_INDOPDONE_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_QSPI_IRQSTAT_INDOPDONE register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_INDIRECTREQ 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
Indirect Operation Requested
#define ALT_QSPI_IRQSTAT_INDRDREJECT_E_NOINDIRECTREQ 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDRDREJECT
No Indirect Operation
#define ALT_QSPI_IRQSTAT_INDRDREJECT_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDRDREJECT register field.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_INDRDREJECT register field.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET_MSK 0x00000008 |
The mask used to set the ALT_QSPI_IRQSTAT_INDRDREJECT register field value.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_QSPI_IRQSTAT_INDRDREJECT register field value.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_INDRDREJECT register field.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_QSPI_IRQSTAT_INDRDREJECT field value from a register.
#define ALT_QSPI_IRQSTAT_INDRDREJECT_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_QSPI_IRQSTAT_INDRDREJECT register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_WRPROT 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
Write Attempt to protected area
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_E_NOWRPROT 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_PROTWRATTEMPT
No Write Attempt
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET_MSK 0x00000010 |
The mask used to set the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_CLR_MSK 0xffffffef |
The mask used to clear the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_QSPI_IRQSTAT_PROTWRATTEMPT field value from a register.
#define ALT_QSPI_IRQSTAT_PROTWRATTEMPT_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_QSPI_IRQSTAT_PROTWRATTEMPT register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_ILLEGALAHB 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
Illegal AHB attempt
#define ALT_QSPI_IRQSTAT_ILLEGALACC_E_NOILLEGALAHB 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_ILLEGALACC
No Illegal AHB attempt
#define ALT_QSPI_IRQSTAT_ILLEGALACC_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_ILLEGALACC register field.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_ILLEGALACC register field.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET_MSK 0x00000020 |
The mask used to set the ALT_QSPI_IRQSTAT_ILLEGALACC register field value.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_QSPI_IRQSTAT_ILLEGALACC register field value.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_ILLEGALACC register field.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_QSPI_IRQSTAT_ILLEGALACC field value from a register.
#define ALT_QSPI_IRQSTAT_ILLEGALACC_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_QSPI_IRQSTAT_ILLEGALACC register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_WATERLEVL 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
Water level reached
#define ALT_QSPI_IRQSTAT_INDXFRLVL_E_NOWATERLVL 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDXFRLVL
No water level reached
#define ALT_QSPI_IRQSTAT_INDXFRLVL_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDXFRLVL register field.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_INDXFRLVL register field.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET_MSK 0x00000040 |
The mask used to set the ALT_QSPI_IRQSTAT_INDXFRLVL register field value.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_QSPI_IRQSTAT_INDXFRLVL register field value.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_INDXFRLVL register field.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_QSPI_IRQSTAT_INDXFRLVL field value from a register.
#define ALT_QSPI_IRQSTAT_INDXFRLVL_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_QSPI_IRQSTAT_INDXFRLVL register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_RXOVER_E_RCVOVER 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
Receive Overflow
#define ALT_QSPI_IRQSTAT_RXOVER_E_NORCVOVER 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXOVER
No Receive Overflow
#define ALT_QSPI_IRQSTAT_RXOVER_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field.
#define ALT_QSPI_IRQSTAT_RXOVER_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXOVER register field.
#define ALT_QSPI_IRQSTAT_RXOVER_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_RXOVER register field.
#define ALT_QSPI_IRQSTAT_RXOVER_SET_MSK 0x00000080 |
The mask used to set the ALT_QSPI_IRQSTAT_RXOVER register field value.
#define ALT_QSPI_IRQSTAT_RXOVER_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_QSPI_IRQSTAT_RXOVER register field value.
#define ALT_QSPI_IRQSTAT_RXOVER_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_RXOVER register field.
#define ALT_QSPI_IRQSTAT_RXOVER_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_QSPI_IRQSTAT_RXOVER field value from a register.
#define ALT_QSPI_IRQSTAT_RXOVER_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_QSPI_IRQSTAT_RXOVER register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_GT 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
FIFO has > TXTHRESH entries
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_E_LE 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_TXTHRESHCMP
FIFO has <= TXTHRESH entries
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET_MSK 0x00000100 |
The mask used to set the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_RESET 0x1 |
The reset value of the ALT_QSPI_IRQSTAT_TXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_QSPI_IRQSTAT_TXTHRESHCMP field value from a register.
#define ALT_QSPI_IRQSTAT_TXTHRESHCMP_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_QSPI_IRQSTAT_TXTHRESHCMP register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_TXFULL_E_NOTFULL 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
Transmit FIFO Not Full
#define ALT_QSPI_IRQSTAT_TXFULL_E_FULL 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_TXFULL
Transmit FIFO Full
#define ALT_QSPI_IRQSTAT_TXFULL_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field.
#define ALT_QSPI_IRQSTAT_TXFULL_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_TXFULL register field.
#define ALT_QSPI_IRQSTAT_TXFULL_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_TXFULL register field.
#define ALT_QSPI_IRQSTAT_TXFULL_SET_MSK 0x00000200 |
The mask used to set the ALT_QSPI_IRQSTAT_TXFULL register field value.
#define ALT_QSPI_IRQSTAT_TXFULL_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_QSPI_IRQSTAT_TXFULL register field value.
#define ALT_QSPI_IRQSTAT_TXFULL_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_TXFULL register field.
#define ALT_QSPI_IRQSTAT_TXFULL_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_QSPI_IRQSTAT_TXFULL field value from a register.
#define ALT_QSPI_IRQSTAT_TXFULL_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_QSPI_IRQSTAT_TXFULL register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_LE 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
FIFO has <= RXTHRESH entries
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_E_GT 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXTHRESHCMP
FIFO has > RXTHRESH entries
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET_MSK 0x00000400 |
The mask used to set the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_RXTHRESHCMP register field.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_QSPI_IRQSTAT_RXTHRESHCMP field value from a register.
#define ALT_QSPI_IRQSTAT_RXTHRESHCMP_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_QSPI_IRQSTAT_RXTHRESHCMP register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_RXFULL_E_NOTFULL 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
Receive FIFO Not Full
#define ALT_QSPI_IRQSTAT_RXFULL_E_FULL 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_RXFULL
Receive FIFO Full
#define ALT_QSPI_IRQSTAT_RXFULL_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field.
#define ALT_QSPI_IRQSTAT_RXFULL_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_RXFULL register field.
#define ALT_QSPI_IRQSTAT_RXFULL_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_RXFULL register field.
#define ALT_QSPI_IRQSTAT_RXFULL_SET_MSK 0x00000800 |
The mask used to set the ALT_QSPI_IRQSTAT_RXFULL register field value.
#define ALT_QSPI_IRQSTAT_RXFULL_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_QSPI_IRQSTAT_RXFULL register field value.
#define ALT_QSPI_IRQSTAT_RXFULL_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_RXFULL register field.
#define ALT_QSPI_IRQSTAT_RXFULL_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_QSPI_IRQSTAT_RXFULL field value from a register.
#define ALT_QSPI_IRQSTAT_RXFULL_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_QSPI_IRQSTAT_RXFULL register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTFULL 0x1 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
SRAM is full
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_E_RDPARTNOTFULL 0x0 |
Enumerated value for register field ALT_QSPI_IRQSTAT_INDSRAMFULL
SRAM is not full
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_WIDTH 1 |
The width in bits of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET_MSK 0x00001000 |
The mask used to set the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_CLR_MSK 0xffffefff |
The mask used to clear the ALT_QSPI_IRQSTAT_INDSRAMFULL register field value.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_RESET 0x0 |
The reset value of the ALT_QSPI_IRQSTAT_INDSRAMFULL register field.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_QSPI_IRQSTAT_INDSRAMFULL field value from a register.
#define ALT_QSPI_IRQSTAT_INDSRAMFULL_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_QSPI_IRQSTAT_INDSRAMFULL register field value suitable for setting the register.
#define ALT_QSPI_IRQSTAT_OFST 0x40 |
The byte offset of the ALT_QSPI_IRQSTAT register from the beginning of the component.
typedef struct ALT_QSPI_IRQSTAT_s ALT_QSPI_IRQSTAT_t |
The typedef declaration for register ALT_QSPI_IRQSTAT.