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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Field : cfg_ctrl_cmd_rate | |
3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_LSB 0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_MSB 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET_MSK 0x00000007 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_CLR_MSK 0xfffffff8 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_GET(value) (((value) & 0x00000007) >> 0) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET(value) (((value) << 0) & 0x00000007) |
Field : cfg_dbc0_cmd_rate | |
3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_LSB 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_MSB 5 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_GET(value) (((value) & 0x00000038) >> 3) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET(value) (((value) << 3) & 0x00000038) |
Field : cfg_dbc1_cmd_rate | |
3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_LSB 6 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_MSB 8 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_GET(value) (((value) & 0x000001c0) >> 6) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET(value) (((value) << 6) & 0x000001c0) |
Field : cfg_dbc2_cmd_rate | |
3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_LSB 9 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_MSB 11 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_GET(value) (((value) & 0x00000e00) >> 9) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET(value) (((value) << 9) & 0x00000e00) |
Field : cfg_dbc3_cmd_rate | |
3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_LSB 12 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_MSB 14 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_GET(value) (((value) & 0x00007000) >> 12) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET(value) (((value) << 12) & 0x00007000) |
Field : cfg_ctrl_in_protocol | |
1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_LSB 15 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_MSB 15 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET_MSK 0x00008000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_CLR_MSK 0xffff7fff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET(value) (((value) << 15) & 0x00008000) |
Field : cfg_dbc0_in_protocol | |
1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET(value) (((value) << 16) & 0x00010000) |
Field : cfg_dbc1_in_protocol | |
1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET(value) (((value) << 17) & 0x00020000) |
Field : cfg_dbc2_in_protocol | |
1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET(value) (((value) << 18) & 0x00040000) |
Field : cfg_dbc3_in_protocol | |
1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET(value) (((value) << 19) & 0x00080000) |
Field : cfg_ctrl_dualport_en | |
Enable the second command port for RLDRAM3 only (BL=2 or 4) Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_LSB 20 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_MSB 20 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET_MSK 0x00100000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_CLR_MSK 0xffefffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET(value) (((value) << 20) & 0x00100000) |
Field : cfg_dbc0_dualport_en | |
Enable the second data port for RLDRAM3 only (BL=2 or 4) Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET(value) (((value) << 21) & 0x00200000) |
Field : cfg_dbc1_dualport_en | |
Enable the second data port for RLDRAM3 only (BL=2 or 4) Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET(value) (((value) << 22) & 0x00400000) |
Field : cfg_dbc2_dualport_en | |
Enable the second data port for RLDRAM3 only (BL=2 or 4) Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET(value) (((value) << 23) & 0x00800000) |
Field : cfg_dbc3_dualport_en | |
Enable the second data port for RLDRAM3 only (BL=2 or 4) Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET(value) (((value) << 24) & 0x01000000) |
Field : cfg_arbiter_type | |
Indicates controller arbiter operating mode. Set this to: - 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_LSB 25 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_MSB 25 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET(value) (((value) << 25) & 0x02000000) |
Field : cfg_open_page_en | |
Set to 1 to enable the open page policy when command reordering is disabled (cfg_cmd_reorder = 0). This bit does not matter when cfg_cmd_reorder is 1. Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_LSB 26 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_MSB 26 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_GET(value) (((value) & 0x04000000) >> 26) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET(value) (((value) << 26) & 0x04000000) |
Field : cfg_geardn_en | |
Set to 1 to enable the gear down mode for DDR4 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_LSB 27 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_MSB 27 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_GET(value) (((value) & 0x08000000) >> 27) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET(value) (((value) << 27) & 0x08000000) |
Field : cfg_rld3_multibank_mode | |
Multibank setting, specific for RLDRAM3. Set this to: - 3 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_LSB 28 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_MSB 30 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_WIDTH 3 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET_MSK 0x70000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_CLR_MSK 0x8fffffff |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_GET(value) (((value) & 0x70000000) >> 28) |
#define | ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET(value) (((value) << 28) & 0x70000000) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_CTLCFG3_s |
Macros | |
#define | ALT_IO48_HMC_MMR_CTLCFG3_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG3_OFST 0x34 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_CTLCFG3_s | ALT_IO48_HMC_MMR_CTLCFG3_t |
struct ALT_IO48_HMC_MMR_CTLCFG3_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG3.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET_MSK 0x00000007 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_CLR_MSK 0xfffffff8 |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_GET | ( | value | ) | (((value) & 0x00000007) >> 0) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE_SET | ( | value | ) | (((value) << 0) & 0x00000007) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_CMD_RATE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET_MSK 0x00000038 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_CLR_MSK 0xffffffc7 |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_GET | ( | value | ) | (((value) & 0x00000038) >> 3) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE_SET | ( | value | ) | (((value) << 3) & 0x00000038) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_CMD_RATE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET_MSK 0x000001c0 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_CLR_MSK 0xfffffe3f |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_GET | ( | value | ) | (((value) & 0x000001c0) >> 6) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE_SET | ( | value | ) | (((value) << 6) & 0x000001c0) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_CMD_RATE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET_MSK 0x00000e00 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_CLR_MSK 0xfffff1ff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_GET | ( | value | ) | (((value) & 0x00000e00) >> 9) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE_SET | ( | value | ) | (((value) << 9) & 0x00000e00) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_CMD_RATE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET_MSK 0x00007000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_CLR_MSK 0xffff8fff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_GET | ( | value | ) | (((value) & 0x00007000) >> 12) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE_SET | ( | value | ) | (((value) << 12) & 0x00007000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_CMD_RATE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET_MSK 0x00008000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_IN_PROTOCOL register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET_MSK 0x00010000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_IN_PROTOCOL register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET_MSK 0x00020000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_IN_PROTOCOL register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET_MSK 0x00040000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_IN_PROTOCOL register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET_MSK 0x00080000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_IN_PROTOCOL register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET_MSK 0x00100000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_CLR_MSK 0xffefffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_CTL_DUALPORT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET_MSK 0x00200000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC0_DUALPORT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET_MSK 0x00400000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC1_DUALPORT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET_MSK 0x00800000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC2_DUALPORT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET_MSK 0x01000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_DBC3_DUALPORT_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET_MSK 0x02000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_ARBITER_TYPE register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET_MSK 0x04000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_OPEN_PAGE_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET_MSK 0x08000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_GEARDN_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_WIDTH 3 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET_MSK 0x70000000 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_CLR_MSK 0x8fffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_GET | ( | value | ) | (((value) & 0x70000000) >> 28) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD_SET | ( | value | ) | (((value) << 28) & 0x70000000) |
Produces a ALT_IO48_HMC_MMR_CTLCFG3_CFG_RLD3_MULTIBANK_MOD register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG3_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG3 register.
#define ALT_IO48_HMC_MMR_CTLCFG3_OFST 0x34 |
The byte offset of the ALT_IO48_HMC_MMR_CTLCFG3 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_CTLCFG3_s ALT_IO48_HMC_MMR_CTLCFG3_t |
The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG3.