Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : txftlr

Description

Transmit FIFO Threshold Level.

This register controls the threshold value for the transmit FIFO memory.

The DW_apb_ssi is enabled and disabled by writing to the SSIENR register.

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 ALT_SPIS_TXFTLR_TFT
[31:8] ??? 0x0 UNDEFINED

Field : tft

Transmit FIFO Threshold.

Controls the level of entries (or below) at which the transmit FIFO controller

triggers an interrupt. The FIFO depth is configurable in the range 2-256;

this register is sized to the number of address bits needed to access the

FIFO. If you attempt to set this value greater than or equal to the depth

of the FIFO, this field is not written and retains its current value. When

the number of transmit FIFO entries is less than or equal to this value,

the transmit FIFO empty interrupt is triggered.

Field Access Macros:

#define ALT_SPIS_TXFTLR_TFT_LSB   0
 
#define ALT_SPIS_TXFTLR_TFT_MSB   7
 
#define ALT_SPIS_TXFTLR_TFT_WIDTH   8
 
#define ALT_SPIS_TXFTLR_TFT_SET_MSK   0x000000ff
 
#define ALT_SPIS_TXFTLR_TFT_CLR_MSK   0xffffff00
 
#define ALT_SPIS_TXFTLR_TFT_RESET   0x0
 
#define ALT_SPIS_TXFTLR_TFT_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_SPIS_TXFTLR_TFT_SET(value)   (((value) << 0) & 0x000000ff)
 

Data Structures

struct  ALT_SPIS_TXFTLR_s
 

Macros

#define ALT_SPIS_TXFTLR_RESET   0x00000000
 
#define ALT_SPIS_TXFTLR_OFST   0x18
 
#define ALT_SPIS_TXFTLR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))
 

Typedefs

typedef struct ALT_SPIS_TXFTLR_s ALT_SPIS_TXFTLR_t
 

Data Structure Documentation

struct ALT_SPIS_TXFTLR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SPIS_TXFTLR.

Data Fields
uint32_t tft: 8 ALT_SPIS_TXFTLR_TFT
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_SPIS_TXFTLR_TFT_LSB   0

The Least Significant Bit (LSB) position of the ALT_SPIS_TXFTLR_TFT register field.

#define ALT_SPIS_TXFTLR_TFT_MSB   7

The Most Significant Bit (MSB) position of the ALT_SPIS_TXFTLR_TFT register field.

#define ALT_SPIS_TXFTLR_TFT_WIDTH   8

The width in bits of the ALT_SPIS_TXFTLR_TFT register field.

#define ALT_SPIS_TXFTLR_TFT_SET_MSK   0x000000ff

The mask used to set the ALT_SPIS_TXFTLR_TFT register field value.

#define ALT_SPIS_TXFTLR_TFT_CLR_MSK   0xffffff00

The mask used to clear the ALT_SPIS_TXFTLR_TFT register field value.

#define ALT_SPIS_TXFTLR_TFT_RESET   0x0

The reset value of the ALT_SPIS_TXFTLR_TFT register field.

#define ALT_SPIS_TXFTLR_TFT_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_SPIS_TXFTLR_TFT field value from a register.

#define ALT_SPIS_TXFTLR_TFT_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_SPIS_TXFTLR_TFT register field value suitable for setting the register.

#define ALT_SPIS_TXFTLR_RESET   0x00000000

The reset value of the ALT_SPIS_TXFTLR register.

#define ALT_SPIS_TXFTLR_OFST   0x18

The byte offset of the ALT_SPIS_TXFTLR register from the beginning of the component.

#define ALT_SPIS_TXFTLR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_TXFTLR_OFST))

The address of the ALT_SPIS_TXFTLR register.

Typedef Documentation

The typedef declaration for register ALT_SPIS_TXFTLR.