![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | Unknown | Interrupt Enable |
[1] | RW | Unknown | Mask Single Bit Error Interrupt |
[2] | RW | Unknown | Mask Double Bit Error Interrupt |
[3] | RW | Unknown | Mask Dropped Auto-correction Interrupt |
[4] | RW | Unknown | Clear Interrupt Signal |
[31:5] | ??? | 0x0 | UNDEFINED |
Field : Interrupt Enable - intren | |
Enable the interrupt output. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001) |
Field : Mask Single Bit Error Interrupt - sbemask | |
Mask the single bit error interrupt. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002) |
Field : Mask Double Bit Error Interrupt - dbemask | |
Mask the double bit error interrupt. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004) |
Field : Mask Dropped Auto-correction Interrupt - corrdropmask | |
Set this bit to a one to mask interrupts for an ECC correction write back needing to be dropped. This indicates a burst of memory errors in a short period of time. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008) |
Field : Clear Interrupt Signal - intrclr | |
Writing to this self-clearing bit clears the interrupt signal. Writing to this bit also clears the error count and error address registers. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010) |
Data Structures | |
struct | ALT_SDR_CTL_DRAMINTR_s |
Macros | |
#define | ALT_SDR_CTL_DRAMINTR_OFST 0x3c |
Typedefs | |
typedef struct ALT_SDR_CTL_DRAMINTR_s | ALT_SDR_CTL_DRAMINTR_t |
struct ALT_SDR_CTL_DRAMINTR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_DRAMINTR.
Data Fields | ||
---|---|---|
uint32_t | intren: 1 | Interrupt Enable |
uint32_t | sbemask: 1 | Mask Single Bit Error Interrupt |
uint32_t | dbemask: 1 | Mask Double Bit Error Interrupt |
uint32_t | corrdropmask: 1 | Mask Dropped Auto-correction Interrupt |
uint32_t | intrclr: 1 | Clear Interrupt Signal |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field.
#define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTREN register field.
#define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_DRAMINTR_INTREN register field.
#define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001 |
The mask used to set the ALT_SDR_CTL_DRAMINTR_INTREN register field value.
#define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTREN register field value.
#define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMINTR_INTREN register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMINTR_INTREN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDR_CTL_DRAMINTR_INTREN field value from a register.
#define ALT_SDR_CTL_DRAMINTR_INTREN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDR_CTL_DRAMINTR_INTREN register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002 |
The mask used to set the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SDR_CTL_DRAMINTR_SBEMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMINTR_SBEMSK register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SDR_CTL_DRAMINTR_SBEMSK field value from a register.
#define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SDR_CTL_DRAMINTR_SBEMSK register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004 |
The mask used to set the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SDR_CTL_DRAMINTR_DBEMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMINTR_DBEMSK register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SDR_CTL_DRAMINTR_DBEMSK field value from a register.
#define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SDR_CTL_DRAMINTR_DBEMSK register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008 |
The mask used to set the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SDR_CTL_DRAMINTR_CORRDROPMSK field value from a register.
#define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SDR_CTL_DRAMINTR_CORRDROPMSK register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010 |
The mask used to set the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SDR_CTL_DRAMINTR_INTRCLR register field value.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMINTR_INTRCLR register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SDR_CTL_DRAMINTR_INTRCLR field value from a register.
#define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SDR_CTL_DRAMINTR_INTRCLR register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMINTR_OFST 0x3c |
The byte offset of the ALT_SDR_CTL_DRAMINTR register from the beginning of the component.
typedef struct ALT_SDR_CTL_DRAMINTR_s ALT_SDR_CTL_DRAMINTR_t |
The typedef declaration for register ALT_SDR_CTL_DRAMINTR.