Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : clkdiv

Description

Clock Divider Register

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 ALT_SDMMC_CLKDIV_CLK_DIVR0
[15:8] R 0x0 ALT_SDMMC_CLKDIV_CLK_DIVR1
[23:16] R 0x0 ALT_SDMMC_CLKDIV_CLK_DIVR2
[31:24] R 0x0 ALT_SDMMC_CLKDIV_CLK_DIVR3

Field : clk_divider0

Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on.

Field Access Macros:

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB   0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB   7
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK   0x000000ff
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK   0xffffff00
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET   0x0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : clk_divider1

Clock divider-1 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported

Field Access Macros:

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_LSB   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_MSB   15
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_WIDTH   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET_MSK   0x0000ff00
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_CLR_MSK   0xffff00ff
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_RESET   0x0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_GET(value)   (((value) & 0x0000ff00) >> 8)
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET(value)   (((value) << 8) & 0x0000ff00)
 

Field : clk_divider2

Clock divider-2 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.

Field Access Macros:

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_LSB   16
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_MSB   23
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_WIDTH   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET_MSK   0x00ff0000
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_CLR_MSK   0xff00ffff
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_RESET   0x0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_GET(value)   (((value) & 0x00ff0000) >> 16)
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET(value)   (((value) << 16) & 0x00ff0000)
 

Field : clk_divider3

Clock divider-3 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), a value of 1 means divide by 2*1 = 2, a value of “ff” means divide by 2*255 = 510, and so on. In MMC-Ver3.3-only mode, bits not implemented because only one clock divider is supported.

Field Access Macros:

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_LSB   24
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_MSB   31
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_WIDTH   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET_MSK   0xff000000
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_CLR_MSK   0x00ffffff
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_RESET   0x0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_GET(value)   (((value) & 0xff000000) >> 24)
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET(value)   (((value) << 24) & 0xff000000)
 

Data Structures

struct  ALT_SDMMC_CLKDIV_s
 

Macros

#define ALT_SDMMC_CLKDIV_RESET   0x00000000
 
#define ALT_SDMMC_CLKDIV_OFST   0x8
 

Typedefs

typedef struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t
 

Data Structure Documentation

struct ALT_SDMMC_CLKDIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_CLKDIV.

Data Fields
uint32_t clk_divider0: 8 ALT_SDMMC_CLKDIV_CLK_DIVR0
const uint32_t clk_divider1: 8 ALT_SDMMC_CLKDIV_CLK_DIVR1
const uint32_t clk_divider2: 8 ALT_SDMMC_CLKDIV_CLK_DIVR2
const uint32_t clk_divider3: 8 ALT_SDMMC_CLKDIV_CLK_DIVR3

Macro Definitions

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH   8

The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK   0x000000ff

The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK   0xffffff00

The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET   0x0

The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR0 field value from a register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value suitable for setting the register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_WIDTH   8

The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET_MSK   0x0000ff00

The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_CLR_MSK   0xffff00ff

The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_RESET   0x0

The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR1 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_GET (   value)    (((value) & 0x0000ff00) >> 8)

Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR1 field value from a register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET (   value)    (((value) << 8) & 0x0000ff00)

Produces a ALT_SDMMC_CLKDIV_CLK_DIVR1 register field value suitable for setting the register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_MSB   23

The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_WIDTH   8

The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET_MSK   0x00ff0000

The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_CLR_MSK   0xff00ffff

The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_RESET   0x0

The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR2 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_GET (   value)    (((value) & 0x00ff0000) >> 16)

Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR2 field value from a register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET (   value)    (((value) << 16) & 0x00ff0000)

Produces a ALT_SDMMC_CLKDIV_CLK_DIVR2 register field value suitable for setting the register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_LSB   24

The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_MSB   31

The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_WIDTH   8

The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET_MSK   0xff000000

The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_CLR_MSK   0x00ffffff

The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_RESET   0x0

The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR3 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_GET (   value)    (((value) & 0xff000000) >> 24)

Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR3 field value from a register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET (   value)    (((value) << 24) & 0xff000000)

Produces a ALT_SDMMC_CLKDIV_CLK_DIVR3 register field value suitable for setting the register.

#define ALT_SDMMC_CLKDIV_RESET   0x00000000

The reset value of the ALT_SDMMC_CLKDIV register.

#define ALT_SDMMC_CLKDIV_OFST   0x8

The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_CLKDIV.