Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dramodt1

Description

Register Layout

Bits Access Reset Description
[5:0] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON
[11:6] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON
[17:12] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD
[23:18] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD
[31:24] ??? 0x0 UNDEFINED

Field : cfg_wr_odt_on

Indicates number of memory clock cycle gap between write command and ODT signal rising edge

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_LSB   0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_MSB   5
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET_MSK   0x0000003f
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK   0xffffffc0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_GET(value)   (((value) & 0x0000003f) >> 0)
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET(value)   (((value) << 0) & 0x0000003f)
 

Field : cfg_rd_odt_on

Indicates number of memory clock cycle gap between read command and ODT signal rising edge

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_LSB   6
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_MSB   11
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET_MSK   0x00000fc0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK   0xfffff03f
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_GET(value)   (((value) & 0x00000fc0) >> 6)
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET(value)   (((value) << 6) & 0x00000fc0)
 

Field : cfg_wr_odt_period

Indicates number of memory clock cycle write ODT signal should stay asserted after rising edge

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_LSB   12
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_MSB   17
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK   0x0003f000
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK   0xfffc0fff
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_GET(value)   (((value) & 0x0003f000) >> 12)
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET(value)   (((value) << 12) & 0x0003f000)
 

Field : cfg_rd_odt_period

Indicates number of memory clock cycle read ODT signal should stay asserted after rising edge

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_LSB   18
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_MSB   23
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK   0x00fc0000
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK   0xff03ffff
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_GET(value)   (((value) & 0x00fc0000) >> 18)
 
#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET(value)   (((value) << 18) & 0x00fc0000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DRAMODT1_s
 

Macros

#define ALT_IO48_HMC_MMR_DRAMODT1_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DRAMODT1_OFST   0x58
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DRAMODT1_s 
ALT_IO48_HMC_MMR_DRAMODT1_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DRAMODT1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DRAMODT1.

Data Fields
uint32_t cfg_wr_odt_on: 6 ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON
uint32_t cfg_rd_odt_on: 6 ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON
uint32_t cfg_wr_odt_period: 6 ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD
uint32_t cfg_rd_odt_period: 6 ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD
uint32_t __pad0__: 8 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_MSB   5

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET_MSK   0x0000003f

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_CLR_MSK   0xffffffc0

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_GET (   value)    (((value) & 0x0000003f) >> 0)

Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON_SET (   value)    (((value) << 0) & 0x0000003f)

Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_ON register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_LSB   6

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_MSB   11

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET_MSK   0x00000fc0

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_CLR_MSK   0xfffff03f

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_GET (   value)    (((value) & 0x00000fc0) >> 6)

Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON_SET (   value)    (((value) << 6) & 0x00000fc0)

Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_ON register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_LSB   12

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_MSB   17

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET_MSK   0x0003f000

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_CLR_MSK   0xfffc0fff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_GET (   value)    (((value) & 0x0003f000) >> 12)

Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD_SET (   value)    (((value) << 12) & 0x0003f000)

Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_WR_ODT_PERIOD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_LSB   18

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_MSB   23

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET_MSK   0x00fc0000

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_CLR_MSK   0xff03ffff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_GET (   value)    (((value) & 0x00fc0000) >> 18)

Extracts the ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD_SET (   value)    (((value) << 18) & 0x00fc0000)

Produces a ALT_IO48_HMC_MMR_DRAMODT1_CFG_RD_ODT_PERIOD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT1_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DRAMODT1 register.

#define ALT_IO48_HMC_MMR_DRAMODT1_OFST   0x58

The byte offset of the ALT_IO48_HMC_MMR_DRAMODT1 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DRAMODT1.