Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 459 (PPS Control Register) - gmacgrp_pps_control

Description

Controls timestamp Pulse-Per-Second output

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 PPSCTRL0 or PPSCMD0
[4] RW 0x0 Flexible PPS Output Mode Enable
[6:5] RW 0x0 Target Time Register Mode for PPS0 Output
[31:7] ??? 0x0 UNDEFINED

Field : PPSCTRL0 or PPSCMD0 - ppsctrl_ppscmd

PPSCTRL0: PPS0 Output Frequency Control

This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000, and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL, the PPS output becomes a generated clock of following frequencies:

  • 0001: The binary rollover is 2 Hz, and the digital rollover is 1 Hz.
  • 0010: The binary rollover is 4 Hz, and the digital rollover is 2 Hz.
  • 0011: The binary rollover is 8 Hz, and the digital rollover is 4 Hz.
  • 0100: The binary rollover is 16 Hz, and the digital rollover is 8 Hz.
  • ...
  • 1111: The binary rollover is 32.768 KHz, and the digital rollover is 16.384 KHz.

Note:

In the binary rollover mode, the PPS output (ptp_pps_o) has a duty cycle of 50 percent with these frequencies.

In the digital rollover mode, the PPS output frequency is an average number. The actual clock is of different frequency that gets synchronized every second. For example:

- When PPSCTRL = 0001, the PPS (1 Hz) has a low period of 537 ms and a high
  period of 463 ms

- When PPSCTRL = 0010, the PPS (2 Hz) is a sequence of:
  • One clock of 50 percent duty cycle and 537 ms period
  • Second clock of 463 ms period (268 ms low and 195 ms high)

    • When PPSCTRL = 0011, the PPS (4 Hz) is a sequence of:
  • Three clocks of 50 percent duty cycle and 268 ms period
  • Fourth clock of 195 ms period (134 ms low and 61 ms high)

This behavior is because of the non-linear toggling of bits in the digital rollover mode in Register 451 (System Time - Nanoseconds Register).

Flexible PPS0 Output (ptp_pps_o[0]) Control

Programming these bits with a non-zero value instructs the MAC to initiate an event. Once the command is transferred or synchronized to the PTP clock domain, these bits get cleared automatically. The Software should ensure that these bits are programmed only when they are all-zero. The following list describes the values of PPSCMD0:

- 0000: No Command

- 0001: START Single Pulse

This command generates single pulse rising at the start point defined in Target Time Registers (register 455 and 456) and of a duration defined in the PPS0 Width Register.

- 0010: START Pulse Train

This command generates the train of pulses rising at the start point defined in the Target Time Registers and of a duration defined in the PPS0 Width Register and repeated at interval defined in the PPS Interval Register. By default, the PPS pulse train is free-running unless stopped by 'STOP Pulse train at time' or 'STOP Pulse Train immediately' commands.

- 0011: Cancel START

This command cancels the START Single Pulse and START Pulse Train commands if the system time has not crossed the programmed start time.

- 0100: STOP Pulse train at time

This command stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010) after the time programmed in the Target Time registers elapses.

- 0101: STOP Pulse Train immediately

This command immediately stops the train of pulses initiated by the START Pulse Train command (PPSCMD = 0010).

- 0110: Cancel STOP Pulse train

This command cancels the STOP pulse train at time command if the programmed stop time has not elapsed. The PPS pulse train becomes free-running on the successful execution of this command.

- 0111-1111: Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB   0
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB   3
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH   4
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK   0x0000000f
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK   0xfffffff0
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET   0x0
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : Flexible PPS Output Mode Enable - ppsen0

When set low, Bits[3:0] function as PPSCTRL (backward compatible). When set high, Bits[3:0] function as PPSCMD.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL | 0x0 | ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL   0x0
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD   0x1
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB   4
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB   4
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH   1
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET   0x0
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Target Time Register Mode for PPS0 Output - trgtmodsel0

This field indicates the Target Time registers (register 455 and 456) mode for PPS0 output signal

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY | 0x0 | ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0 | 0x2 | ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER | 0x3 |

Field Access Macros:

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY   0x0
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0   0x2
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER   0x3
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB   5
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB   6
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH   2
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK   0x00000060
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK   0xffffff9f
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET   0x0
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET(value)   (((value) & 0x00000060) >> 5)
 
#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET(value)   (((value) << 5) & 0x00000060)
 

Data Structures

struct  ALT_EMAC_GMAC_PPS_CTL_s
 

Macros

#define ALT_EMAC_GMAC_PPS_CTL_RESET   0x00000000
 
#define ALT_EMAC_GMAC_PPS_CTL_OFST   0x72c
 
#define ALT_EMAC_GMAC_PPS_CTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_PPS_CTL_s 
ALT_EMAC_GMAC_PPS_CTL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_PPS_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_PPS_CTL.

Data Fields
uint32_t ppsctrl_ppscmd: 4 PPSCTRL0 or PPSCMD0
uint32_t ppsen0: 1 Flexible PPS Output Mode Enable
uint32_t trgtmodsel0: 2 Target Time Register Mode for PPS0 Output
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_WIDTH   4

The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET_MSK   0x0000000f

The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_CLR_MSK   0xfffffff0

The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD field value from a register.

#define ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_EMAC_GMAC_PPS_CTL_PPSCTL_PPSCMD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCTL   0x0

Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_E_PPSCMD   0x1

Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_PPSEN0

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_PPS_CTL_PPSEN0 field value from a register.

#define ALT_EMAC_GMAC_PPS_CTL_PPSEN0_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_PPS_CTL_PPSEN0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTERONLY   0x0

Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTINTPPS0   0x2

Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_E_TRGTNOINTER   0x3

Enumerated value for register field ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET_MSK   0x00000060

The mask used to set the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_CLR_MSK   0xffffff9f

The mask used to clear the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_GET (   value)    (((value) & 0x00000060) >> 5)

Extracts the ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 field value from a register.

#define ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0_SET (   value)    (((value) << 5) & 0x00000060)

Produces a ALT_EMAC_GMAC_PPS_CTL_TRGTMODSEL0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_PPS_CTL_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_PPS_CTL register.

#define ALT_EMAC_GMAC_PPS_CTL_OFST   0x72c

The byte offset of the ALT_EMAC_GMAC_PPS_CTL register from the beginning of the component.

#define ALT_EMAC_GMAC_PPS_CTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_PPS_CTL_OFST))

The address of the ALT_EMAC_GMAC_PPS_CTL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_PPS_CTL.