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alt_noc_fw_ocram_scr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__
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#define __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_LSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_MSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_LSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_MSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_LSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_MSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_LSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_MSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_LSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_MSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG4EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_LSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_MSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_OCRAM_SCR_EN_REG5EN_SET(value) (((value) << 5) & 0x00000020)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_OCRAM_SCR_EN_s
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{
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uint32_t
region0enable
: 1;
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uint32_t
region1enable
: 1;
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uint32_t
region2enable
: 1;
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uint32_t
region3enable
: 1;
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uint32_t
region4enable
: 1;
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uint32_t
region5enable
: 1;
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uint32_t : 26;
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};
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typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_EN_s
ALT_NOC_FW_OCRAM_SCR_EN_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_OCRAM_SCR_EN_RESET 0x00000000
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#define ALT_NOC_FW_OCRAM_SCR_EN_OFST 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_LSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_MSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_LSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_MSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_LSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_MSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_LSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_MSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_LSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_MSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG4EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_LSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_MSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_REG5EN_SET(value) (((value) << 5) & 0x00000020)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_OCRAM_SCR_EN_SET_s
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{
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uint32_t
region0enable
: 1;
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uint32_t
region1enable
: 1;
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uint32_t
region2enable
: 1;
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uint32_t
region3enable
: 1;
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uint32_t
region4enable
: 1;
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uint32_t
region5enable
: 1;
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uint32_t : 26;
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};
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typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_EN_SET_s
ALT_NOC_FW_OCRAM_SCR_EN_SET_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_RESET 0x00000000
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#define ALT_NOC_FW_OCRAM_SCR_EN_SET_OFST 0x4
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_LSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_MSB 0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_LSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_MSB 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_LSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_MSB 2
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_LSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_MSB 3
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_LSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_MSB 4
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG4EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_LSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_MSB 5
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_WIDTH 1
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_REG5EN_SET(value) (((value) << 5) & 0x00000020)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_OCRAM_SCR_EN_CLR_s
684
{
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uint32_t
region0enable
: 1;
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uint32_t
region1enable
: 1;
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uint32_t
region2enable
: 1;
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uint32_t
region3enable
: 1;
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uint32_t
region4enable
: 1;
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uint32_t
region5enable
: 1;
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uint32_t : 26;
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};
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typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_EN_CLR_s
ALT_NOC_FW_OCRAM_SCR_EN_CLR_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_RESET 0x00000000
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#define ALT_NOC_FW_OCRAM_SCR_EN_CLR_OFST 0x8
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_LSB 0
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_MSB 5
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_WIDTH 6
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_SET_MSK 0x0000003f
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_CLR_MSK 0xffffffc0
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_LSB 16
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_MSB 21
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_WIDTH 6
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_SET_MSK 0x003f0000
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_CLR_MSK 0xffc0ffff
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_RESET 0x0
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
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#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
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#ifndef __ASSEMBLY__
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781
struct
ALT_NOC_FW_OCRAM_SCR_REG0ADDR_s
782
{
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uint32_t
base
: 6;
784
uint32_t : 10;
785
uint32_t
limit
: 6;
786
uint32_t : 10;
787
};
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790
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG0ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG0ADDR_t
;
791
#endif
/* __ASSEMBLY__ */
792
794
#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_RESET 0x00000000
795
796
#define ALT_NOC_FW_OCRAM_SCR_REG0ADDR_OFST 0xc
797
823
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_LSB 0
824
825
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_MSB 5
826
827
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_WIDTH 6
828
829
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_SET_MSK 0x0000003f
830
831
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_CLR_MSK 0xffffffc0
832
833
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_RESET 0x0
834
835
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
836
837
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
838
849
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_LSB 16
850
851
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_MSB 21
852
853
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_WIDTH 6
854
855
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_SET_MSK 0x003f0000
856
857
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_CLR_MSK 0xffc0ffff
858
859
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_RESET 0x0
860
861
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
862
863
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
864
865
#ifndef __ASSEMBLY__
866
876
struct
ALT_NOC_FW_OCRAM_SCR_REG1ADDR_s
877
{
878
uint32_t
base
: 6;
879
uint32_t : 10;
880
uint32_t
limit
: 6;
881
uint32_t : 10;
882
};
883
885
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG1ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG1ADDR_t
;
886
#endif
/* __ASSEMBLY__ */
887
889
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_RESET 0x00000000
890
891
#define ALT_NOC_FW_OCRAM_SCR_REG1ADDR_OFST 0x10
892
918
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_LSB 0
919
920
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_MSB 5
921
922
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_WIDTH 6
923
924
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_SET_MSK 0x0000003f
925
926
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_CLR_MSK 0xffffffc0
927
928
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_RESET 0x0
929
930
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
931
932
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
933
944
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_LSB 16
945
946
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_MSB 21
947
948
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_WIDTH 6
949
950
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_SET_MSK 0x003f0000
951
952
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_CLR_MSK 0xffc0ffff
953
954
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_RESET 0x0
955
956
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
957
958
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
959
960
#ifndef __ASSEMBLY__
961
971
struct
ALT_NOC_FW_OCRAM_SCR_REG2ADDR_s
972
{
973
uint32_t
base
: 6;
974
uint32_t : 10;
975
uint32_t
limit
: 6;
976
uint32_t : 10;
977
};
978
980
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG2ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG2ADDR_t
;
981
#endif
/* __ASSEMBLY__ */
982
984
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_RESET 0x00000000
985
986
#define ALT_NOC_FW_OCRAM_SCR_REG2ADDR_OFST 0x14
987
1013
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_LSB 0
1014
1015
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_MSB 5
1016
1017
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_WIDTH 6
1018
1019
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_SET_MSK 0x0000003f
1020
1021
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_CLR_MSK 0xffffffc0
1022
1023
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_RESET 0x0
1024
1025
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1026
1027
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1028
1039
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_LSB 16
1040
1041
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_MSB 21
1042
1043
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_WIDTH 6
1044
1045
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_SET_MSK 0x003f0000
1046
1047
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_CLR_MSK 0xffc0ffff
1048
1049
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_RESET 0x0
1050
1051
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1052
1053
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1054
1055
#ifndef __ASSEMBLY__
1056
1066
struct
ALT_NOC_FW_OCRAM_SCR_REG3ADDR_s
1067
{
1068
uint32_t
base
: 6;
1069
uint32_t : 10;
1070
uint32_t
limit
: 6;
1071
uint32_t : 10;
1072
};
1073
1075
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG3ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG3ADDR_t
;
1076
#endif
/* __ASSEMBLY__ */
1077
1079
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_RESET 0x00000000
1080
1081
#define ALT_NOC_FW_OCRAM_SCR_REG3ADDR_OFST 0x18
1082
1108
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_LSB 0
1109
1110
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_MSB 5
1111
1112
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_WIDTH 6
1113
1114
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_SET_MSK 0x0000003f
1115
1116
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_CLR_MSK 0xffffffc0
1117
1118
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_RESET 0x0
1119
1120
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1121
1122
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1123
1134
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_LSB 16
1135
1136
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_MSB 21
1137
1138
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_WIDTH 6
1139
1140
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_SET_MSK 0x003f0000
1141
1142
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_CLR_MSK 0xffc0ffff
1143
1144
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_RESET 0x0
1145
1146
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1147
1148
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1149
1150
#ifndef __ASSEMBLY__
1151
1161
struct
ALT_NOC_FW_OCRAM_SCR_REG4ADDR_s
1162
{
1163
uint32_t
base
: 6;
1164
uint32_t : 10;
1165
uint32_t
limit
: 6;
1166
uint32_t : 10;
1167
};
1168
1170
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG4ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG4ADDR_t
;
1171
#endif
/* __ASSEMBLY__ */
1172
1174
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_RESET 0x00000000
1175
1176
#define ALT_NOC_FW_OCRAM_SCR_REG4ADDR_OFST 0x1c
1177
1203
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_LSB 0
1204
1205
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_MSB 5
1206
1207
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_WIDTH 6
1208
1209
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_SET_MSK 0x0000003f
1210
1211
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_CLR_MSK 0xffffffc0
1212
1213
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_RESET 0x0
1214
1215
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_GET(value) (((value) & 0x0000003f) >> 0)
1216
1217
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_BASE_SET(value) (((value) << 0) & 0x0000003f)
1218
1229
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_LSB 16
1230
1231
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_MSB 21
1232
1233
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_WIDTH 6
1234
1235
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_SET_MSK 0x003f0000
1236
1237
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_CLR_MSK 0xffc0ffff
1238
1239
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_RESET 0x0
1240
1241
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_GET(value) (((value) & 0x003f0000) >> 16)
1242
1243
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_LIMIT_SET(value) (((value) << 16) & 0x003f0000)
1244
1245
#ifndef __ASSEMBLY__
1246
1256
struct
ALT_NOC_FW_OCRAM_SCR_REG5ADDR_s
1257
{
1258
uint32_t
base
: 6;
1259
uint32_t : 10;
1260
uint32_t
limit
: 6;
1261
uint32_t : 10;
1262
};
1263
1265
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_REG5ADDR_s
ALT_NOC_FW_OCRAM_SCR_REG5ADDR_t
;
1266
#endif
/* __ASSEMBLY__ */
1267
1269
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_RESET 0x00000000
1270
1271
#define ALT_NOC_FW_OCRAM_SCR_REG5ADDR_OFST 0x20
1272
1273
#ifndef __ASSEMBLY__
1274
1284
struct
ALT_NOC_FW_OCRAM_SCR_s
1285
{
1286
volatile
ALT_NOC_FW_OCRAM_SCR_EN_t
enable
;
1287
volatile
ALT_NOC_FW_OCRAM_SCR_EN_SET_t
enable_set
;
1288
volatile
ALT_NOC_FW_OCRAM_SCR_EN_CLR_t
enable_clear
;
1289
volatile
ALT_NOC_FW_OCRAM_SCR_REG0ADDR_t
region0addr
;
1290
volatile
ALT_NOC_FW_OCRAM_SCR_REG1ADDR_t
region1addr
;
1291
volatile
ALT_NOC_FW_OCRAM_SCR_REG2ADDR_t
region2addr
;
1292
volatile
ALT_NOC_FW_OCRAM_SCR_REG3ADDR_t
region3addr
;
1293
volatile
ALT_NOC_FW_OCRAM_SCR_REG4ADDR_t
region4addr
;
1294
volatile
ALT_NOC_FW_OCRAM_SCR_REG5ADDR_t
region5addr
;
1295
volatile
uint32_t
_pad_0x24_0x100
[55];
1296
};
1297
1299
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_s
ALT_NOC_FW_OCRAM_SCR_t
;
1301
struct
ALT_NOC_FW_OCRAM_SCR_raw_s
1302
{
1303
volatile
uint32_t
enable
;
1304
volatile
uint32_t
enable_set
;
1305
volatile
uint32_t
enable_clear
;
1306
volatile
uint32_t
region0addr
;
1307
volatile
uint32_t
region1addr
;
1308
volatile
uint32_t
region2addr
;
1309
volatile
uint32_t
region3addr
;
1310
volatile
uint32_t
region4addr
;
1311
volatile
uint32_t
region5addr
;
1312
volatile
uint32_t
_pad_0x24_0x100
[55];
1313
};
1314
1316
typedef
volatile
struct
ALT_NOC_FW_OCRAM_SCR_raw_s
ALT_NOC_FW_OCRAM_SCR_raw_t
;
1317
#endif
/* __ASSEMBLY__ */
1318
1320
#ifdef __cplusplus
1321
}
1322
#endif
/* __cplusplus */
1323
#endif
/* __ALT_SOCAL_NOC_FW_OCRAM_SCR_H__ */
1324
include
soc_a10
socal
alt_noc_fw_ocram_scr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2