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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Component Parameter Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | R | 0x2 | ALT_UART_CPR_APBDATAWIDTH |
[3:2] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_3TO2 |
[4] | R | 0x1 | ALT_UART_CPR_AFCE_MOD |
[5] | R | 0x1 | ALT_UART_CPR_THRE_MOD |
[6] | R | 0x0 | ALT_UART_CPR_SIR_MOD |
[7] | R | 0x0 | ALT_UART_CPR_SIR_LP_MOD |
[8] | R | 0x1 | ALT_UART_CPR_ADDITIONAL_FEAT |
[9] | R | 0x1 | ALT_UART_CPR_FIFO_ACCESS |
[10] | R | 0x1 | ALT_UART_CPR_FIFO_STAT |
[11] | R | 0x1 | ALT_UART_CPR_SHADOW |
[12] | R | 0x1 | ALT_UART_CPR_UART_ADD_ENC_PARAM |
[13] | R | 0x1 | ALT_UART_CPR_DMA_EXTRA |
[15:14] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_15TO14 |
[23:16] | R | 0x8 | ALT_UART_CPR_FIFO_MOD |
[31:24] | R | 0x0 | ALT_UART_CPR_RSVD_CPR_31TO24 |
Field : apbdatawidth | |||||||
Encoding of APB_DATA_WIDTH configuration parameter value. 00 = 8 bits, 01 = 16 bits, 10 = 32 bits, 11 = reserved Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_LSB 0 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_MSB 1 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_GET(value) (((value) & 0x00000003) >> 0) | ||||||
#define | ALT_UART_CPR_APBDATAWIDTH_SET(value) (((value) << 0) & 0x00000003) | ||||||
Field : rsvd_cpr_3to2 | |
Reserved bits [3:2] - Read Only Field Access Macros: | |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_LSB 2 |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_MSB 3 |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_WIDTH 2 |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_SET_MSK 0x0000000c |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_CLR_MSK 0xfffffff3 |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_RESET 0x0 |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_GET(value) (((value) & 0x0000000c) >> 2) |
#define | ALT_UART_CPR_RSVD_CPR_3TO2_SET(value) (((value) << 2) & 0x0000000c) |
Field : afce_mode | |||||||
Encoding of AFCE_MODE configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_AFCE_MOD_E_END 0x1 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_LSB 4 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_MSB 4 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_WIDTH 1 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef | ||||||
#define | ALT_UART_CPR_AFCE_MOD_RESET 0x1 | ||||||
#define | ALT_UART_CPR_AFCE_MOD_GET(value) (((value) & 0x00000010) >> 4) | ||||||
#define | ALT_UART_CPR_AFCE_MOD_SET(value) (((value) << 4) & 0x00000010) | ||||||
Field : thre_mode | ||||||||||
Encoding of THRE_MODE configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_CPR_THRE_MOD_E_END 0x1 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_LSB 5 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_MSB 5 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_WIDTH 1 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_UART_CPR_THRE_MOD_RESET 0x1 | |||||||||
#define | ALT_UART_CPR_THRE_MOD_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_UART_CPR_THRE_MOD_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : sir_mode | |||||||
Encoding of SIR_MODE configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_SIR_MOD_E_DISD 0x0 | ||||||
#define | ALT_UART_CPR_SIR_MOD_LSB 6 | ||||||
#define | ALT_UART_CPR_SIR_MOD_MSB 6 | ||||||
#define | ALT_UART_CPR_SIR_MOD_WIDTH 1 | ||||||
#define | ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 | ||||||
#define | ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf | ||||||
#define | ALT_UART_CPR_SIR_MOD_RESET 0x0 | ||||||
#define | ALT_UART_CPR_SIR_MOD_GET(value) (((value) & 0x00000040) >> 6) | ||||||
#define | ALT_UART_CPR_SIR_MOD_SET(value) (((value) << 6) & 0x00000040) | ||||||
Field : sir_lp_mode | |||||||
Encoding of SIR_LP_MODE configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_LSB 7 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_MSB 7 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_GET(value) (((value) & 0x00000080) >> 7) | ||||||
#define | ALT_UART_CPR_SIR_LP_MOD_SET(value) (((value) << 7) & 0x00000080) | ||||||
Field : additional_feat | |||||||
Encoding of ADDITIONAL_FEATURES configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_GET(value) (((value) & 0x00000100) >> 8) | ||||||
#define | ALT_UART_CPR_ADDITIONAL_FEAT_SET(value) (((value) << 8) & 0x00000100) | ||||||
Field : fifo_access | |||||||
Encoding of FIFO_ACCESS configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_LSB 9 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_MSB 9 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_GET(value) (((value) & 0x00000200) >> 9) | ||||||
#define | ALT_UART_CPR_FIFO_ACCESS_SET(value) (((value) << 9) & 0x00000200) | ||||||
Field : fifo_stat | |||||||
Encoding of FIFO_STAT configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_FIFO_STAT_E_END 0x1 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_LSB 10 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_MSB 10 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_WIDTH 1 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff | ||||||
#define | ALT_UART_CPR_FIFO_STAT_RESET 0x1 | ||||||
#define | ALT_UART_CPR_FIFO_STAT_GET(value) (((value) & 0x00000400) >> 10) | ||||||
#define | ALT_UART_CPR_FIFO_STAT_SET(value) (((value) << 10) & 0x00000400) | ||||||
Field : shadow | |||||||
Encoding of SHADOW configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_SHADOW_E_END 0x1 | ||||||
#define | ALT_UART_CPR_SHADOW_LSB 11 | ||||||
#define | ALT_UART_CPR_SHADOW_MSB 11 | ||||||
#define | ALT_UART_CPR_SHADOW_WIDTH 1 | ||||||
#define | ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 | ||||||
#define | ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff | ||||||
#define | ALT_UART_CPR_SHADOW_RESET 0x1 | ||||||
#define | ALT_UART_CPR_SHADOW_GET(value) (((value) & 0x00000800) >> 11) | ||||||
#define | ALT_UART_CPR_SHADOW_SET(value) (((value) << 11) & 0x00000800) | ||||||
Field : uart_add_encoded_param | |||||||
Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value. 0 = FALSE, 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value) (((value) & 0x00001000) >> 12) | ||||||
#define | ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value) (((value) << 12) & 0x00001000) | ||||||
Field : dma_extra | |||||||
Encoding of DMA_EXTRA configuration parameter value. 0 = FALSE,DW_apb_uart.ralf 1 = TRUE Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_DMA_EXTRA_E_END 0x1 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_LSB 13 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_MSB 13 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_WIDTH 1 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_RESET 0x1 | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_GET(value) (((value) & 0x00002000) >> 13) | ||||||
#define | ALT_UART_CPR_DMA_EXTRA_SET(value) (((value) << 13) & 0x00002000) | ||||||
Field : rsvd_cpr_15to14 | |
Reserved bits [15:14] - Read Only Field Access Macros: | |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_LSB 14 |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_MSB 15 |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_WIDTH 2 |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_SET_MSK 0x0000c000 |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_CLR_MSK 0xffff3fff |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_RESET 0x0 |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_UART_CPR_RSVD_CPR_15TO14_SET(value) (((value) << 14) & 0x0000c000) |
Field : fifo_mode | |||||||
Encoding of FIFO_MODE configuration parameter value.DW_apb_uart.ralf 0x00 = 0, 0x01 = 16, 0x02 = 32, toset 0x80 = 2048, 0x81- 0xff = reserved Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_LSB 16 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_MSB 23 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_WIDTH 8 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff | ||||||
#define | ALT_UART_CPR_FIFO_MOD_RESET 0x8 | ||||||
#define | ALT_UART_CPR_FIFO_MOD_GET(value) (((value) & 0x00ff0000) >> 16) | ||||||
#define | ALT_UART_CPR_FIFO_MOD_SET(value) (((value) << 16) & 0x00ff0000) | ||||||
Field : rsvd_cpr_31to24 | |
Reserved bits [31:24] - Read Only Field Access Macros: | |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_LSB 24 |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_MSB 31 |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_WIDTH 8 |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_SET_MSK 0xff000000 |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_CLR_MSK 0x00ffffff |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_RESET 0x0 |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_GET(value) (((value) & 0xff000000) >> 24) |
#define | ALT_UART_CPR_RSVD_CPR_31TO24_SET(value) (((value) << 24) & 0xff000000) |
Data Structures | |
struct | ALT_UART_CPR_s |
Macros | |
#define | ALT_UART_CPR_RESET 0x00083f32 |
#define | ALT_UART_CPR_OFST 0xf4 |
#define | ALT_UART_CPR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) |
Typedefs | |
typedef struct ALT_UART_CPR_s | ALT_UART_CPR_t |
struct ALT_UART_CPR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_UART_CPR.
Data Fields | ||
---|---|---|
const uint32_t | apbdatawidth: 2 | ALT_UART_CPR_APBDATAWIDTH |
const uint32_t | rsvd_cpr_3to2: 2 | ALT_UART_CPR_RSVD_CPR_3TO2 |
const uint32_t | afce_mode: 1 | ALT_UART_CPR_AFCE_MOD |
const uint32_t | thre_mode: 1 | ALT_UART_CPR_THRE_MOD |
const uint32_t | sir_mode: 1 | ALT_UART_CPR_SIR_MOD |
const uint32_t | sir_lp_mode: 1 | ALT_UART_CPR_SIR_LP_MOD |
const uint32_t | additional_feat: 1 | ALT_UART_CPR_ADDITIONAL_FEAT |
const uint32_t | fifo_access: 1 | ALT_UART_CPR_FIFO_ACCESS |
const uint32_t | fifo_stat: 1 | ALT_UART_CPR_FIFO_STAT |
const uint32_t | shadow: 1 | ALT_UART_CPR_SHADOW |
const uint32_t | uart_add_encoded_param: 1 | ALT_UART_CPR_UART_ADD_ENC_PARAM |
const uint32_t | dma_extra: 1 | ALT_UART_CPR_DMA_EXTRA |
const uint32_t | rsvd_cpr_15to14: 2 | ALT_UART_CPR_RSVD_CPR_15TO14 |
const uint32_t | fifo_mode: 8 | ALT_UART_CPR_FIFO_MOD |
const uint32_t | rsvd_cpr_31to24: 8 | ALT_UART_CPR_RSVD_CPR_31TO24 |
#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 |
Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH
APB Data Width = 32-bits
#define ALT_UART_CPR_APBDATAWIDTH_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field.
#define ALT_UART_CPR_APBDATAWIDTH_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field.
#define ALT_UART_CPR_APBDATAWIDTH_WIDTH 2 |
The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field.
#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK 0x00000003 |
The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value.
#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value.
#define ALT_UART_CPR_APBDATAWIDTH_RESET 0x2 |
The reset value of the ALT_UART_CPR_APBDATAWIDTH register field.
#define ALT_UART_CPR_APBDATAWIDTH_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register.
#define ALT_UART_CPR_APBDATAWIDTH_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register.
#define ALT_UART_CPR_RSVD_CPR_3TO2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field.
#define ALT_UART_CPR_RSVD_CPR_3TO2_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_3TO2 register field.
#define ALT_UART_CPR_RSVD_CPR_3TO2_WIDTH 2 |
The width in bits of the ALT_UART_CPR_RSVD_CPR_3TO2 register field.
#define ALT_UART_CPR_RSVD_CPR_3TO2_SET_MSK 0x0000000c |
The mask used to set the ALT_UART_CPR_RSVD_CPR_3TO2 register field value.
#define ALT_UART_CPR_RSVD_CPR_3TO2_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_UART_CPR_RSVD_CPR_3TO2 register field value.
#define ALT_UART_CPR_RSVD_CPR_3TO2_RESET 0x0 |
The reset value of the ALT_UART_CPR_RSVD_CPR_3TO2 register field.
#define ALT_UART_CPR_RSVD_CPR_3TO2_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_UART_CPR_RSVD_CPR_3TO2 field value from a register.
#define ALT_UART_CPR_RSVD_CPR_3TO2_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_UART_CPR_RSVD_CPR_3TO2 register field value suitable for setting the register.
#define ALT_UART_CPR_AFCE_MOD_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_AFCE_MOD
Auto Flow
#define ALT_UART_CPR_AFCE_MOD_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field.
#define ALT_UART_CPR_AFCE_MOD_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field.
#define ALT_UART_CPR_AFCE_MOD_WIDTH 1 |
The width in bits of the ALT_UART_CPR_AFCE_MOD register field.
#define ALT_UART_CPR_AFCE_MOD_SET_MSK 0x00000010 |
The mask used to set the ALT_UART_CPR_AFCE_MOD register field value.
#define ALT_UART_CPR_AFCE_MOD_CLR_MSK 0xffffffef |
The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value.
#define ALT_UART_CPR_AFCE_MOD_RESET 0x1 |
The reset value of the ALT_UART_CPR_AFCE_MOD register field.
#define ALT_UART_CPR_AFCE_MOD_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_UART_CPR_AFCE_MOD field value from a register.
#define ALT_UART_CPR_AFCE_MOD_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register.
#define ALT_UART_CPR_THRE_MOD_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_THRE_MOD
Programmable Tx Hold Reg. Empty interrupt present
#define ALT_UART_CPR_THRE_MOD_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field.
#define ALT_UART_CPR_THRE_MOD_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field.
#define ALT_UART_CPR_THRE_MOD_WIDTH 1 |
The width in bits of the ALT_UART_CPR_THRE_MOD register field.
#define ALT_UART_CPR_THRE_MOD_SET_MSK 0x00000020 |
The mask used to set the ALT_UART_CPR_THRE_MOD register field value.
#define ALT_UART_CPR_THRE_MOD_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_UART_CPR_THRE_MOD register field value.
#define ALT_UART_CPR_THRE_MOD_RESET 0x1 |
The reset value of the ALT_UART_CPR_THRE_MOD register field.
#define ALT_UART_CPR_THRE_MOD_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_UART_CPR_THRE_MOD field value from a register.
#define ALT_UART_CPR_THRE_MOD_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register.
#define ALT_UART_CPR_SIR_MOD_E_DISD 0x0 |
Enumerated value for register field ALT_UART_CPR_SIR_MOD
Sir Mode Not Supported
#define ALT_UART_CPR_SIR_MOD_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field.
#define ALT_UART_CPR_SIR_MOD_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field.
#define ALT_UART_CPR_SIR_MOD_WIDTH 1 |
The width in bits of the ALT_UART_CPR_SIR_MOD register field.
#define ALT_UART_CPR_SIR_MOD_SET_MSK 0x00000040 |
The mask used to set the ALT_UART_CPR_SIR_MOD register field value.
#define ALT_UART_CPR_SIR_MOD_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_UART_CPR_SIR_MOD register field value.
#define ALT_UART_CPR_SIR_MOD_RESET 0x0 |
The reset value of the ALT_UART_CPR_SIR_MOD register field.
#define ALT_UART_CPR_SIR_MOD_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_UART_CPR_SIR_MOD field value from a register.
#define ALT_UART_CPR_SIR_MOD_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register.
#define ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 |
Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD
LP Sir Mode Not Supported
#define ALT_UART_CPR_SIR_LP_MOD_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field.
#define ALT_UART_CPR_SIR_LP_MOD_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field.
#define ALT_UART_CPR_SIR_LP_MOD_WIDTH 1 |
The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field.
#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK 0x00000080 |
The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value.
#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value.
#define ALT_UART_CPR_SIR_LP_MOD_RESET 0x0 |
The reset value of the ALT_UART_CPR_SIR_LP_MOD register field.
#define ALT_UART_CPR_SIR_LP_MOD_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register.
#define ALT_UART_CPR_SIR_LP_MOD_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register.
#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT
Additional Features Supported
#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field.
#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field.
#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH 1 |
The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field.
#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK 0x00000100 |
The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value.
#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value.
#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET 0x1 |
The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field.
#define ALT_UART_CPR_ADDITIONAL_FEAT_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register.
#define ALT_UART_CPR_ADDITIONAL_FEAT_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register.
#define ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS
FIFO Access Supported
#define ALT_UART_CPR_FIFO_ACCESS_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field.
#define ALT_UART_CPR_FIFO_ACCESS_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field.
#define ALT_UART_CPR_FIFO_ACCESS_WIDTH 1 |
The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field.
#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK 0x00000200 |
The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value.
#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value.
#define ALT_UART_CPR_FIFO_ACCESS_RESET 0x1 |
The reset value of the ALT_UART_CPR_FIFO_ACCESS register field.
#define ALT_UART_CPR_FIFO_ACCESS_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register.
#define ALT_UART_CPR_FIFO_ACCESS_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register.
#define ALT_UART_CPR_FIFO_STAT_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_FIFO_STAT
FIFO Stat Supported
#define ALT_UART_CPR_FIFO_STAT_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field.
#define ALT_UART_CPR_FIFO_STAT_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field.
#define ALT_UART_CPR_FIFO_STAT_WIDTH 1 |
The width in bits of the ALT_UART_CPR_FIFO_STAT register field.
#define ALT_UART_CPR_FIFO_STAT_SET_MSK 0x00000400 |
The mask used to set the ALT_UART_CPR_FIFO_STAT register field value.
#define ALT_UART_CPR_FIFO_STAT_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value.
#define ALT_UART_CPR_FIFO_STAT_RESET 0x1 |
The reset value of the ALT_UART_CPR_FIFO_STAT register field.
#define ALT_UART_CPR_FIFO_STAT_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_UART_CPR_FIFO_STAT field value from a register.
#define ALT_UART_CPR_FIFO_STAT_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register.
#define ALT_UART_CPR_SHADOW_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_SHADOW
Shadow Supported
#define ALT_UART_CPR_SHADOW_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field.
#define ALT_UART_CPR_SHADOW_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field.
#define ALT_UART_CPR_SHADOW_WIDTH 1 |
The width in bits of the ALT_UART_CPR_SHADOW register field.
#define ALT_UART_CPR_SHADOW_SET_MSK 0x00000800 |
The mask used to set the ALT_UART_CPR_SHADOW register field value.
#define ALT_UART_CPR_SHADOW_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_UART_CPR_SHADOW register field value.
#define ALT_UART_CPR_SHADOW_RESET 0x1 |
The reset value of the ALT_UART_CPR_SHADOW register field.
#define ALT_UART_CPR_SHADOW_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_UART_CPR_SHADOW field value from a register.
#define ALT_UART_CPR_SHADOW_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM
ID register present
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH 1 |
The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK 0x00001000 |
The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK 0xffffefff |
The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET 0x1 |
The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register.
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register.
#define ALT_UART_CPR_DMA_EXTRA_E_END 0x1 |
Enumerated value for register field ALT_UART_CPR_DMA_EXTRA
DMA Extra Supported
#define ALT_UART_CPR_DMA_EXTRA_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field.
#define ALT_UART_CPR_DMA_EXTRA_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field.
#define ALT_UART_CPR_DMA_EXTRA_WIDTH 1 |
The width in bits of the ALT_UART_CPR_DMA_EXTRA register field.
#define ALT_UART_CPR_DMA_EXTRA_SET_MSK 0x00002000 |
The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value.
#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value.
#define ALT_UART_CPR_DMA_EXTRA_RESET 0x1 |
The reset value of the ALT_UART_CPR_DMA_EXTRA register field.
#define ALT_UART_CPR_DMA_EXTRA_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register.
#define ALT_UART_CPR_DMA_EXTRA_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register.
#define ALT_UART_CPR_RSVD_CPR_15TO14_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field.
#define ALT_UART_CPR_RSVD_CPR_15TO14_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_15TO14 register field.
#define ALT_UART_CPR_RSVD_CPR_15TO14_WIDTH 2 |
The width in bits of the ALT_UART_CPR_RSVD_CPR_15TO14 register field.
#define ALT_UART_CPR_RSVD_CPR_15TO14_SET_MSK 0x0000c000 |
The mask used to set the ALT_UART_CPR_RSVD_CPR_15TO14 register field value.
#define ALT_UART_CPR_RSVD_CPR_15TO14_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_UART_CPR_RSVD_CPR_15TO14 register field value.
#define ALT_UART_CPR_RSVD_CPR_15TO14_RESET 0x0 |
The reset value of the ALT_UART_CPR_RSVD_CPR_15TO14 register field.
#define ALT_UART_CPR_RSVD_CPR_15TO14_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_UART_CPR_RSVD_CPR_15TO14 field value from a register.
#define ALT_UART_CPR_RSVD_CPR_15TO14_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_UART_CPR_RSVD_CPR_15TO14 register field value suitable for setting the register.
#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 |
Enumerated value for register field ALT_UART_CPR_FIFO_MOD
FIFO Depth 128 bytes
#define ALT_UART_CPR_FIFO_MOD_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field.
#define ALT_UART_CPR_FIFO_MOD_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field.
#define ALT_UART_CPR_FIFO_MOD_WIDTH 8 |
The width in bits of the ALT_UART_CPR_FIFO_MOD register field.
#define ALT_UART_CPR_FIFO_MOD_SET_MSK 0x00ff0000 |
The mask used to set the ALT_UART_CPR_FIFO_MOD register field value.
#define ALT_UART_CPR_FIFO_MOD_CLR_MSK 0xff00ffff |
The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value.
#define ALT_UART_CPR_FIFO_MOD_RESET 0x8 |
The reset value of the ALT_UART_CPR_FIFO_MOD register field.
#define ALT_UART_CPR_FIFO_MOD_GET | ( | value | ) | (((value) & 0x00ff0000) >> 16) |
Extracts the ALT_UART_CPR_FIFO_MOD field value from a register.
#define ALT_UART_CPR_FIFO_MOD_SET | ( | value | ) | (((value) << 16) & 0x00ff0000) |
Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register.
#define ALT_UART_CPR_RSVD_CPR_31TO24_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field.
#define ALT_UART_CPR_RSVD_CPR_31TO24_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_UART_CPR_RSVD_CPR_31TO24 register field.
#define ALT_UART_CPR_RSVD_CPR_31TO24_WIDTH 8 |
The width in bits of the ALT_UART_CPR_RSVD_CPR_31TO24 register field.
#define ALT_UART_CPR_RSVD_CPR_31TO24_SET_MSK 0xff000000 |
The mask used to set the ALT_UART_CPR_RSVD_CPR_31TO24 register field value.
#define ALT_UART_CPR_RSVD_CPR_31TO24_CLR_MSK 0x00ffffff |
The mask used to clear the ALT_UART_CPR_RSVD_CPR_31TO24 register field value.
#define ALT_UART_CPR_RSVD_CPR_31TO24_RESET 0x0 |
The reset value of the ALT_UART_CPR_RSVD_CPR_31TO24 register field.
#define ALT_UART_CPR_RSVD_CPR_31TO24_GET | ( | value | ) | (((value) & 0xff000000) >> 24) |
Extracts the ALT_UART_CPR_RSVD_CPR_31TO24 field value from a register.
#define ALT_UART_CPR_RSVD_CPR_31TO24_SET | ( | value | ) | (((value) << 24) & 0xff000000) |
Produces a ALT_UART_CPR_RSVD_CPR_31TO24 register field value suitable for setting the register.
#define ALT_UART_CPR_RESET 0x00083f32 |
The reset value of the ALT_UART_CPR register.
#define ALT_UART_CPR_OFST 0xf4 |
The byte offset of the ALT_UART_CPR register from the beginning of the component.
#define ALT_UART_CPR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST)) |
The address of the ALT_UART_CPR register.
typedef struct ALT_UART_CPR_s ALT_UART_CPR_t |
The typedef declaration for register ALT_UART_CPR.