Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ic_tar

Description

Name: I2C Target Address Register

Size: 12 bits or 13 bits; 13 bits only when I2C_DYNAMIC_TAR_UPDATE = 1

Address Offset: 0x04

Read/Write Access: Read/Write

If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0),

this register is 12 bits wide, and bits 31:12 are reserved. This register

can be written to only when IC_ENABLE[0] is set to 0.

However, if I2C_DYNAMIC_TAR_UPDATE = 1, then the register becomes 13 bits wide.

All bits can be dynamically updated as long as any set of the following

conditions are true:

or

AND

DW_apb_i2c is NOT engaged in any Master (tx, rx) operation (IC_STATUS[5]=0);

AND

DW_apb_i2c is enabled to operate in Master mode (IC_CON[0]=1);

AND

there are NO entries in the TX FIFO (IC_STATUS[2]=1)

Register Layout

Bits Access Reset Description
[9:0] RW 0x55 ALT_I2C_TAR_IC_TAR
[10] RW 0x0 ALT_I2C_TAR_GC_OR_START
[11] RW 0x0 ALT_I2C_TAR_SPECIAL
[12] RW 0x1 ALT_I2C_TAR_IC_10BITADDR_MST
[31:13] ??? 0x0 UNDEFINED

Field : ic_tar

This is the target address for any master transaction. When

transmitting a General Call, these bits are ignored. To generate a

START BYTE, the CPU needs to write only once into these bits.

Reset value: IC_DEFAULT_TAR_SLAVE_ADDR configuration

parameter

If the IC_TAR and IC_SAR are the same, loopback exists but the

FIFOs are shared between master and slave, so full loopback is

not feasible. Only one direction loopback mode is supported

(simplex), not duplex. A master cannot transmit to itself; it can

transmit to only a slave.

Field Access Macros:

#define ALT_I2C_TAR_IC_TAR_LSB   0
 
#define ALT_I2C_TAR_IC_TAR_MSB   9
 
#define ALT_I2C_TAR_IC_TAR_WIDTH   10
 
#define ALT_I2C_TAR_IC_TAR_SET_MSK   0x000003ff
 
#define ALT_I2C_TAR_IC_TAR_CLR_MSK   0xfffffc00
 
#define ALT_I2C_TAR_IC_TAR_RESET   0x55
 
#define ALT_I2C_TAR_IC_TAR_GET(value)   (((value) & 0x000003ff) >> 0)
 
#define ALT_I2C_TAR_IC_TAR_SET(value)   (((value) << 0) & 0x000003ff)
 

Field : gc_or_start

If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a

General Call or START byte command is to be performed by the

DW_apb_i2c.

0: General Call Address after issuing a General Call, only writes

may be performed. Attempting to issue a read command results in

setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.

The DW_apb_i2c remains in General Call mode until the

SPECIAL bit value (bit 11) is cleared.

1: START BYTE

Reset value: 0x0

Field Enumeration Values:

Enum Value Description
ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0 General Call
ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1 START Byte

Field Access Macros:

#define ALT_I2C_TAR_GC_OR_START_E_GENCALL   0x0
 
#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE   0x1
 
#define ALT_I2C_TAR_GC_OR_START_LSB   10
 
#define ALT_I2C_TAR_GC_OR_START_MSB   10
 
#define ALT_I2C_TAR_GC_OR_START_WIDTH   1
 
#define ALT_I2C_TAR_GC_OR_START_SET_MSK   0x00000400
 
#define ALT_I2C_TAR_GC_OR_START_CLR_MSK   0xfffffbff
 
#define ALT_I2C_TAR_GC_OR_START_RESET   0x0
 
#define ALT_I2C_TAR_GC_OR_START_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_I2C_TAR_GC_OR_START_SET(value)   (((value) << 10) & 0x00000400)
 

Field : special

This bit indicates whether software performs a General Call or

START BYTE command.

0: ignore bit 10 GC_OR_START and use IC_TAR normally

1: perform special I2C command as specified in GC_OR_START

bit

Reset value: 0x0

Field Enumeration Values:

Enum Value Description
ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0 Ignore bit 10 gc_or_start and use ic_tar
: normally
ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1 Perform special I2C command as specified in
: gc_or_start

Field Access Macros:

#define ALT_I2C_TAR_SPECIAL_E_GENCALL   0x0
 
#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE   0x1
 
#define ALT_I2C_TAR_SPECIAL_LSB   11
 
#define ALT_I2C_TAR_SPECIAL_MSB   11
 
#define ALT_I2C_TAR_SPECIAL_WIDTH   1
 
#define ALT_I2C_TAR_SPECIAL_SET_MSK   0x00000800
 
#define ALT_I2C_TAR_SPECIAL_CLR_MSK   0xfffff7ff
 
#define ALT_I2C_TAR_SPECIAL_RESET   0x0
 
#define ALT_I2C_TAR_SPECIAL_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_I2C_TAR_SPECIAL_SET(value)   (((value) << 11) & 0x00000800)
 

Field : ic_10bitaddr_master

This bit controls whether the DW_apb_i2c starts its transfers in 7-

or 10-bit addressing mode when acting as a master.

0: 7-bit addressing

1: 10-bit addressing

Dependencies: This bit exists in this register only if the

I2C_DYNAMIC_TAR_UPDATE configuration parameter is set

to 'Yes' (1).

Reset value: IC_10BITADDR_MASTER configuration

parameter

Field Enumeration Values:

Enum Value Description
ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0 Master Address, 7bit
ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1 Master Address, 10bit

Field Access Macros:

#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7   0x0
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10   0x1
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB   12
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB   12
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH   1
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK   0x00001000
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK   0xffffefff
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET   0x1
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value)   (((value) << 12) & 0x00001000)
 

Data Structures

struct  ALT_I2C_TAR_s
 

Macros

#define ALT_I2C_TAR_RESET   0x00001055
 
#define ALT_I2C_TAR_OFST   0x4
 
#define ALT_I2C_TAR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
 

Typedefs

typedef struct ALT_I2C_TAR_s ALT_I2C_TAR_t
 

Data Structure Documentation

struct ALT_I2C_TAR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_I2C_TAR.

Data Fields
uint32_t ic_tar: 10 ALT_I2C_TAR_IC_TAR
uint32_t gc_or_start: 1 ALT_I2C_TAR_GC_OR_START
uint32_t special: 1 ALT_I2C_TAR_SPECIAL
uint32_t ic_10bitaddr_master: 1 ALT_I2C_TAR_IC_10BITADDR_MST
uint32_t __pad0__: 19 UNDEFINED

Macro Definitions

#define ALT_I2C_TAR_IC_TAR_LSB   0

The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_TAR register field.

#define ALT_I2C_TAR_IC_TAR_MSB   9

The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_TAR register field.

#define ALT_I2C_TAR_IC_TAR_WIDTH   10

The width in bits of the ALT_I2C_TAR_IC_TAR register field.

#define ALT_I2C_TAR_IC_TAR_SET_MSK   0x000003ff

The mask used to set the ALT_I2C_TAR_IC_TAR register field value.

#define ALT_I2C_TAR_IC_TAR_CLR_MSK   0xfffffc00

The mask used to clear the ALT_I2C_TAR_IC_TAR register field value.

#define ALT_I2C_TAR_IC_TAR_RESET   0x55

The reset value of the ALT_I2C_TAR_IC_TAR register field.

#define ALT_I2C_TAR_IC_TAR_GET (   value)    (((value) & 0x000003ff) >> 0)

Extracts the ALT_I2C_TAR_IC_TAR field value from a register.

#define ALT_I2C_TAR_IC_TAR_SET (   value)    (((value) << 0) & 0x000003ff)

Produces a ALT_I2C_TAR_IC_TAR register field value suitable for setting the register.

#define ALT_I2C_TAR_GC_OR_START_E_GENCALL   0x0

Enumerated value for register field ALT_I2C_TAR_GC_OR_START

General Call

#define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE   0x1

Enumerated value for register field ALT_I2C_TAR_GC_OR_START

START Byte

#define ALT_I2C_TAR_GC_OR_START_LSB   10

The Least Significant Bit (LSB) position of the ALT_I2C_TAR_GC_OR_START register field.

#define ALT_I2C_TAR_GC_OR_START_MSB   10

The Most Significant Bit (MSB) position of the ALT_I2C_TAR_GC_OR_START register field.

#define ALT_I2C_TAR_GC_OR_START_WIDTH   1

The width in bits of the ALT_I2C_TAR_GC_OR_START register field.

#define ALT_I2C_TAR_GC_OR_START_SET_MSK   0x00000400

The mask used to set the ALT_I2C_TAR_GC_OR_START register field value.

#define ALT_I2C_TAR_GC_OR_START_CLR_MSK   0xfffffbff

The mask used to clear the ALT_I2C_TAR_GC_OR_START register field value.

#define ALT_I2C_TAR_GC_OR_START_RESET   0x0

The reset value of the ALT_I2C_TAR_GC_OR_START register field.

#define ALT_I2C_TAR_GC_OR_START_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_I2C_TAR_GC_OR_START field value from a register.

#define ALT_I2C_TAR_GC_OR_START_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_I2C_TAR_GC_OR_START register field value suitable for setting the register.

#define ALT_I2C_TAR_SPECIAL_E_GENCALL   0x0

Enumerated value for register field ALT_I2C_TAR_SPECIAL

Ignore bit 10 gc_or_start and use ic_tar normally

#define ALT_I2C_TAR_SPECIAL_E_STARTBYTE   0x1

Enumerated value for register field ALT_I2C_TAR_SPECIAL

Perform special I2C command as specified in gc_or_start

#define ALT_I2C_TAR_SPECIAL_LSB   11

The Least Significant Bit (LSB) position of the ALT_I2C_TAR_SPECIAL register field.

#define ALT_I2C_TAR_SPECIAL_MSB   11

The Most Significant Bit (MSB) position of the ALT_I2C_TAR_SPECIAL register field.

#define ALT_I2C_TAR_SPECIAL_WIDTH   1

The width in bits of the ALT_I2C_TAR_SPECIAL register field.

#define ALT_I2C_TAR_SPECIAL_SET_MSK   0x00000800

The mask used to set the ALT_I2C_TAR_SPECIAL register field value.

#define ALT_I2C_TAR_SPECIAL_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_I2C_TAR_SPECIAL register field value.

#define ALT_I2C_TAR_SPECIAL_RESET   0x0

The reset value of the ALT_I2C_TAR_SPECIAL register field.

#define ALT_I2C_TAR_SPECIAL_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_I2C_TAR_SPECIAL field value from a register.

#define ALT_I2C_TAR_SPECIAL_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_I2C_TAR_SPECIAL register field value suitable for setting the register.

#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7   0x0

Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST

Master Address, 7bit

#define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10   0x1

Enumerated value for register field ALT_I2C_TAR_IC_10BITADDR_MST

Master Address, 10bit

#define ALT_I2C_TAR_IC_10BITADDR_MST_LSB   12

The Least Significant Bit (LSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field.

#define ALT_I2C_TAR_IC_10BITADDR_MST_MSB   12

The Most Significant Bit (MSB) position of the ALT_I2C_TAR_IC_10BITADDR_MST register field.

#define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH   1

The width in bits of the ALT_I2C_TAR_IC_10BITADDR_MST register field.

#define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK   0x00001000

The mask used to set the ALT_I2C_TAR_IC_10BITADDR_MST register field value.

#define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK   0xffffefff

The mask used to clear the ALT_I2C_TAR_IC_10BITADDR_MST register field value.

#define ALT_I2C_TAR_IC_10BITADDR_MST_RESET   0x1

The reset value of the ALT_I2C_TAR_IC_10BITADDR_MST register field.

#define ALT_I2C_TAR_IC_10BITADDR_MST_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_I2C_TAR_IC_10BITADDR_MST field value from a register.

#define ALT_I2C_TAR_IC_10BITADDR_MST_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_I2C_TAR_IC_10BITADDR_MST register field value suitable for setting the register.

#define ALT_I2C_TAR_RESET   0x00001055

The reset value of the ALT_I2C_TAR register.

#define ALT_I2C_TAR_OFST   0x4

The byte offset of the ALT_I2C_TAR register from the beginning of the component.

#define ALT_I2C_TAR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))

The address of the ALT_I2C_TAR register.

Typedef Documentation

typedef struct ALT_I2C_TAR_s ALT_I2C_TAR_t

The typedef declaration for register ALT_I2C_TAR.