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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Attached device has only 2 ROW address cycles
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG |
[3:1] | ??? | Unknown | UNDEFINED |
[4] | RW | 0x0 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR |
[31:5] | ??? | Unknown | UNDEFINED |
Field : flag | |
This flag must be set for devices which allow for 2 ROW address cycles instead of the usual 3. Alternatively, bootstrap_two_row_addr_cycles when asserted will set this flag. Field Access Macros: | |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET(value) (((value) << 0) & 0x00000001) |
Field : four | |
This flag must be set for devices which allow for 4 ROW address cycles instead of the usual 3. Field Access Macros: | |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET(value) (((value) << 4) & 0x00000010) |
Data Structures | |
struct | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s |
Macros | |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000 |
#define | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190 |
Typedefs | |
typedef struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_t |
struct ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES.
Data Fields | ||
---|---|---|
uint32_t | flag: 1 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG |
uint32_t | __pad0__: 3 | UNDEFINED |
uint32_t | four: 1 | ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR |
uint32_t | __pad1__: 27 | UNDEFINED |
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET_MSK 0x00000001 |
The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_RESET 0x0 |
The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG field value from a register.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FLAG register field value suitable for setting the register.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_WIDTH 1 |
The width in bits of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET_MSK 0x00000010 |
The mask used to set the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_CLR_MSK 0xffffffef |
The mask used to clear the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_RESET 0x0 |
The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR field value from a register.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_FOUR register field value suitable for setting the register.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_RESET 0x00000000 |
The reset value of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register.
#define ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES_OFST 0x190 |
The byte offset of the ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES register from the beginning of the component.
The typedef declaration for register ALT_NAND_CFG_TWO_ROW_ADDR_CYCLES.