Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 22 (HW Feature Register) - HW_Feature

Description

This register indicates the presence of the optional features or functions of the gmac. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks.

Register Layout

Bits Access Reset Description
[0] R 0x1 MII Selection
[1] R 0x1 GMII Selection
[2] R 0x1 Half Duplex Selection
[3] ??? 0x0 UNDEFINED
[4] R 0x1 Hash Filter
[5] R 0x1 Multiple MAC Address Register
[6] R 0x0 PCS Select
[7] ??? 0x0 UNDEFINED
[8] R 0x1 SMA Select
[9] R 0x1 RWK Select
[10] R 0x1 MGK Select
[11] R 0x1 MMC Select
[12] R 0x1 TS Version1 Select
[13] R 0x1 TS Version2 Select
[14] R 0x1 Energy Efficient Ethernet
[15] R 0x0 AV Select
[16] R 0x1 Tx Offload Checksum
[17] R 0x0 Rx Type 1 Checksum Offload
[18] R 0x1 Rx Type 2 Checksum Offload
[19] R 0x1 Rx FIFO Size
[21:20] R 0x0 Rx Channel Count
[23:22] R 0x0 Tx Channel Count
[24] R 0x1 Enhanced Descriptor Select
[27:25] ??? 0x0 UNDEFINED
[30:28] R 0x0 Selected PHY Interface
[31] ??? 0x0 UNDEFINED

Field : MII Selection - miisel

10/100 Mbps support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD 0x0 10 Mbps or 100 Mbps disabled
ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END 0x1 10 Mbps or 100 Mbps enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB   0
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB   0
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET(value)   (((value) << 0) & 0x00000001)
 

Field : GMII Selection - gmiisel

1000 Mbps support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD 0x0 1000 Mbps disabled
ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END 0x1 1000 Mbps enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB   1
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB   1
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK   0x00000002
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Half Duplex Selection - hdsel

Half-Duplex support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD 0x0 Half Duplex disabled
ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END 0x1 Half Duplex enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB   2
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB   2
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK   0x00000004
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Hash Filter - hashsel

HASH Filter support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD 0x0 Hash Filter disabled
ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END 0x1 Hash Filter enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB   4
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB   4
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK   0x00000010
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK   0xffffffef
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Multiple MAC Address Register - addmacadrsel

Multiple MAC Address Registers support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD 0x0 Multiple MAC Address registers disabled
ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END 0x1 Multiple MAC Address registers enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB   5
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB   5
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK   0x00000020
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET(value)   (((value) << 5) & 0x00000020)
 

Field : PCS Select - pcssel

TBI/SGMII/RTBI PHY interface support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD 0x0 PCS Support disabled
ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END 0x1 PCS Support enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB   6
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB   6
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK   0x00000040
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET(value)   (((value) << 6) & 0x00000040)
 

Field : SMA Select - smasel

SMA (MDIO) Interface support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD 0x0 SMA Interface Support disabled
ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END 0x1 SMA Interface Support enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB   8
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB   8
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK   0x00000100
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET(value)   (((value) << 8) & 0x00000100)
 

Field : RWK Select - rwksel

PMT Remote Wakeup support

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD 0x0 PMT Remote Wake Up disabled
ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END 0x1 PMT Remote Wake Up enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB   9
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB   9
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK   0x00000200
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET(value)   (((value) << 9) & 0x00000200)
 

Field : MGK Select - mgksel

PMT Magic Packet

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD 0x0 PMT Magic Packet disabled
ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END 0x1 PMT Magic Packet enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB   10
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB   10
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK   0x00000400
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MMC Select - mmcsel

RMON block

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD 0x0 Rmon block disabled
ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END 0x1 Rmon block enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB   11
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB   11
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK   0x00000800
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET(value)   (((value) << 11) & 0x00000800)
 

Field : TS Version1 Select - tsver1sel

Only IEEE 1588-2002 Timestamp

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD 0x0 TS Version1 Select disabled
ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END 0x1 TS Version1 Select enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB   12
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB   12
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK   0x00001000
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK   0xffffefff
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET(value)   (((value) << 12) & 0x00001000)
 

Field : TS Version2 Select - tsver2sel

IEEE 1588-2008 Advanced Timestamp

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD 0x0 TS Version2 Select disabled
ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END 0x1 TS Version2 Select enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB   13
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB   13
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK   0x00002000
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Energy Efficient Ethernet - eeesel

Energy Efficient Ethernet Feature

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD 0x0 Energy Efficient Ethernet disabled
ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END 0x1 Energy Efficient Ethernet enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB   14
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB   14
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK   0x00004000
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET(value)   (((value) << 14) & 0x00004000)
 

Field : AV Select - avsel

AV Feature

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD 0x0 AV Select disabled
ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END 0x1 AV Select enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB   15
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB   15
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK   0x00008000
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Tx Offload Checksum - txoesel

Checksum Offload in Tx

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD 0x0 Tx Offload Checksum disabled
ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END 0x1 Tx Offload Checksum enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB   16
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB   16
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK   0x00010000
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Rx Type 1 Checksum Offload - rxtyp1coe

IP Checksum Offload (Type 1) in Rx

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD 0x0 Rx Type 1 Checksum Offload disabled
ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END 0x1 Rx Type 1 Checksum Offload enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB   17
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB   17
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK   0x00020000
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK   0xfffdffff
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET(value)   (((value) << 17) & 0x00020000)
 

Field : Rx Type 2 Checksum Offload - rxtyp2coe

IP Checksum Offload (Type 2) in Rx

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD 0x0 Rx Type 2 Checksum Offload disabled
ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END 0x1 Rx Type 2 Checksum Offload enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB   18
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB   18
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK   0x00040000
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET(value)   (((value) << 18) & 0x00040000)
 

Field : Rx FIFO Size - rxfifosize

RxFIFO > 2048 Bytes

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD 0x0 RxFIFO > 2048 bytes disabled
ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END 0x1 RxFIFO > 2048 bytes enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB   19
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB   19
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK   0x00080000
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET(value)   (((value) << 19) & 0x00080000)
 

Field : Rx Channel Count - rxchcnt

Number of additional Rx channels

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD 0x0 Rx Channel Count disabled
ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END 0x1 Rx Channel Count enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB   20
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB   21
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH   2
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK   0x00300000
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK   0xffcfffff
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET(value)   (((value) & 0x00300000) >> 20)
 
#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET(value)   (((value) << 20) & 0x00300000)
 

Field : Tx Channel Count - txchcnt

Number of additional Tx channels

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD 0x0 Tx Channel Count disabled
ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END 0x1 Tx Channel Count enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB   22
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB   23
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH   2
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK   0x00c00000
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK   0xff3fffff
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET(value)   (((value) & 0x00c00000) >> 22)
 
#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET(value)   (((value) << 22) & 0x00c00000)
 

Field : Enhanced Descriptor Select - enhdessel

Alternate (Enhanced Descriptor)

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD 0x0 Enhanced Descriptor Select disabled
ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END 0x1 Enhanced Descriptor Select enabled

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB   24
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB   24
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH   1
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK   0x01000000
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET(value)   (((value) << 24) & 0x01000000)
 

Field : Selected PHY Interface - actphyif

When you have multiple PHY interfaces in your configuration, this field indicates the sampled value of emacx_phy_if_selduring reset de-assertion.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0 0x0 Sampled Value GMII or MII
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1 0x1 Sampled Value RGMII
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2 0x2 Sampled Value SGMII
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3 0x3 Sampled Value TBI
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4 0x4 Sampled Value RMII
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5 0x5 Sampled Value RTBI
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6 0x6 Sampled Value SMII
ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7 0x7 Sampled Value RevMII

Field Access Macros:

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1   0x1
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2   0x2
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3   0x3
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4   0x4
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5   0x5
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6   0x6
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7   0x7
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB   28
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB   30
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH   3
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK   0x70000000
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK   0x8fffffff
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET   0x0
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET(value)   (((value) & 0x70000000) >> 28)
 
#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET(value)   (((value) << 28) & 0x70000000)
 

Data Structures

struct  ALT_EMAC_DMA_HW_FEATURE_s
 

Macros

#define ALT_EMAC_DMA_HW_FEATURE_OFST   0x58
 
#define ALT_EMAC_DMA_HW_FEATURE_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_HW_FEATURE_s 
ALT_EMAC_DMA_HW_FEATURE_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_HW_FEATURE_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_HW_FEATURE.

Data Fields
const uint32_t miisel: 1 MII Selection
const uint32_t gmiisel: 1 GMII Selection
const uint32_t hdsel: 1 Half Duplex Selection
uint32_t __pad0__: 1 UNDEFINED
const uint32_t hashsel: 1 Hash Filter
const uint32_t addmacadrsel: 1 Multiple MAC Address Register
const uint32_t pcssel: 1 PCS Select
uint32_t __pad1__: 1 UNDEFINED
const uint32_t smasel: 1 SMA Select
const uint32_t rwksel: 1 RWK Select
const uint32_t mgksel: 1 MGK Select
const uint32_t mmcsel: 1 MMC Select
const uint32_t tsver1sel: 1 TS Version1 Select
const uint32_t tsver2sel: 1 TS Version2 Select
const uint32_t eeesel: 1 Energy Efficient Ethernet
const uint32_t avsel: 1 AV Select
const uint32_t txoesel: 1 Tx Offload Checksum
const uint32_t rxtyp1coe: 1 Rx Type 1 Checksum Offload
const uint32_t rxtyp2coe: 1 Rx Type 2 Checksum Offload
const uint32_t rxfifosize: 1 Rx FIFO Size
const uint32_t rxchcnt: 2 Rx Channel Count
const uint32_t txchcnt: 2 Tx Channel Count
const uint32_t enhdessel: 1 Enhanced Descriptor Select
uint32_t __pad2__: 3 UNDEFINED
const uint32_t actphyif: 3 Selected PHY Interface
uint32_t __pad3__: 1 UNDEFINED

Macro Definitions

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL

10 Mbps or 100 Mbps disabled

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MIISEL

10 Mbps or 100 Mbps enabled

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_MIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_HW_FEATURE_MIISEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_MIISEL_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_HW_FEATURE_MIISEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL

1000 Mbps disabled

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_GMIISEL

1000 Mbps enabled

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_DMA_HW_FEATURE_GMIISEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_GMIISEL_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_DMA_HW_FEATURE_GMIISEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL

Half Duplex disabled

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HDSEL

Half Duplex enabled

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_HDSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_DMA_HW_FEATURE_HDSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_HDSEL_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_DMA_HW_FEATURE_HDSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL

Hash Filter disabled

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_HASHSEL

Hash Filter enabled

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_DMA_HW_FEATURE_HASHSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_HASHSEL_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_DMA_HW_FEATURE_HASHSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL

Multiple MAC Address registers disabled

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL

Multiple MAC Address registers enabled

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_DMA_HW_FEATURE_ADDMACADRSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL

PCS Support disabled

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_PCSSEL

PCS Support enabled

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_DMA_HW_FEATURE_PCSSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_PCSSEL_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_DMA_HW_FEATURE_PCSSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL

SMA Interface Support disabled

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_SMASEL

SMA Interface Support enabled

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_SMASEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_DMA_HW_FEATURE_SMASEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_SMASEL_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_DMA_HW_FEATURE_SMASEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL

PMT Remote Wake Up disabled

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RWKSEL

PMT Remote Wake Up enabled

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_DMA_HW_FEATURE_RWKSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_RWKSEL_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_DMA_HW_FEATURE_RWKSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL

PMT Magic Packet disabled

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MGKSEL

PMT Magic Packet enabled

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_DMA_HW_FEATURE_MGKSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_MGKSEL_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_DMA_HW_FEATURE_MGKSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL

Rmon block disabled

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_MMCSEL

Rmon block enabled

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_DMA_HW_FEATURE_MMCSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_MMCSEL_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_DMA_HW_FEATURE_MMCSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL

TS Version1 Select disabled

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL

TS Version1 Select enabled

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER1SEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL

TS Version2 Select disabled

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL

TS Version2 Select enabled

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_DMA_HW_FEATURE_TSVER2SEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL

Energy Efficient Ethernet disabled

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_EEESEL

Energy Efficient Ethernet enabled

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_EEESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_DMA_HW_FEATURE_EEESEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_EEESEL_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_DMA_HW_FEATURE_EEESEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL

AV Select disabled

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_AVSEL

AV Select enabled

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_AVSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_DMA_HW_FEATURE_AVSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_AVSEL_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_DMA_HW_FEATURE_AVSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL

Tx Offload Checksum disabled

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXOESEL

Tx Offload Checksum enabled

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_DMA_HW_FEATURE_TXOESEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_TXOESEL_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_DMA_HW_FEATURE_TXOESEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE

Rx Type 1 Checksum Offload disabled

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE

Rx Type 1 Checksum Offload enabled

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET_MSK   0x00020000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_CLR_MSK   0xfffdffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP1COE register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE

Rx Type 2 Checksum Offload disabled

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE

Rx Type 2 Checksum Offload enabled

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_DMA_HW_FEATURE_RXTYP2COE register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE

RxFIFO > 2048 bytes disabled

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE

RxFIFO > 2048 bytes enabled

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_DMA_HW_FEATURE_RXFIFOSIZE register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT

Rx Channel Count disabled

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_RXCHCNT

Rx Channel Count enabled

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_WIDTH   2

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET_MSK   0x00300000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_CLR_MSK   0xffcfffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_GET (   value)    (((value) & 0x00300000) >> 20)

Extracts the ALT_EMAC_DMA_HW_FEATURE_RXCHCNT field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_RXCHCNT_SET (   value)    (((value) << 20) & 0x00300000)

Produces a ALT_EMAC_DMA_HW_FEATURE_RXCHCNT register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT

Tx Channel Count disabled

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_TXCHCNT

Tx Channel Count enabled

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_WIDTH   2

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET_MSK   0x00c00000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_CLR_MSK   0xff3fffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_GET (   value)    (((value) & 0x00c00000) >> 22)

Extracts the ALT_EMAC_DMA_HW_FEATURE_TXCHCNT field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_TXCHCNT_SET (   value)    (((value) << 22) & 0x00c00000)

Produces a ALT_EMAC_DMA_HW_FEATURE_TXCHCNT register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL

Enhanced Descriptor Select disabled

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL

Enhanced Descriptor Select enabled

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_RESET   0x1

The reset value of the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_DMA_HW_FEATURE_ENHDESSEL register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_GMIIMII0   0x0

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value GMII or MII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RGMII1   0x1

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value RGMII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SGMII2   0x2

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value SGMII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_TBI3   0x3

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value TBI

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RMII4   0x4

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value RMII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_RTBI5   0x5

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value RTBI

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_SMII6   0x6

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value SMII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_E_REVMII7   0x7

Enumerated value for register field ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF

Sampled Value RevMII

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_LSB   28

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_MSB   30

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_WIDTH   3

The width in bits of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET_MSK   0x70000000

The mask used to set the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_CLR_MSK   0x8fffffff

The mask used to clear the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_RESET   0x0

The reset value of the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_GET (   value)    (((value) & 0x70000000) >> 28)

Extracts the ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF field value from a register.

#define ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF_SET (   value)    (((value) << 28) & 0x70000000)

Produces a ALT_EMAC_DMA_HW_FEATURE_ACTPHYIF register field value suitable for setting the register.

#define ALT_EMAC_DMA_HW_FEATURE_OFST   0x58

The byte offset of the ALT_EMAC_DMA_HW_FEATURE register from the beginning of the component.

#define ALT_EMAC_DMA_HW_FEATURE_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_HW_FEATURE_OFST))

The address of the ALT_EMAC_DMA_HW_FEATURE register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_HW_FEATURE.