Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Enable Register - en

Description

Contains fields that control the SDRAM Clock Group enables generated from the SDRAM PLL clock outputs.

1: The clock is enabled.

0: The clock is disabled.

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[0] RW 0x1 ddr_dqs_clk Enable
[1] RW 0x1 ddr_2x_dqs_clk Enable
[2] RW 0x1 ddr_dq_clk Enable
[3] RW 0x1 s2f_user2_clk Enable
[31:4] ??? 0x0 UNDEFINED

Field : ddr_dqs_clk Enable - ddrdqsclk

Enables clock ddr_dqs_clk output

Field Access Macros:

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB   0
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB   0
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH   1
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK   0x00000001
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK   0xfffffffe
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET   0x1
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET(value)   (((value) << 0) & 0x00000001)
 

Field : ddr_2x_dqs_clk Enable - ddr2xdqsclk

Enables clock ddr_2x_dqs_clk output

Field Access Macros:

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB   1
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB   1
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH   1
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK   0x00000002
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK   0xfffffffd
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET   0x1
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET(value)   (((value) << 1) & 0x00000002)
 

Field : ddr_dq_clk Enable - ddrdqclk

Enables clock ddr_dq_clk output

Field Access Macros:

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB   2
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB   2
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH   1
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK   0x00000004
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK   0xfffffffb
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET   0x1
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET(value)   (((value) << 2) & 0x00000004)
 

Field : s2f_user2_clk Enable - s2fuser2clk

Enables clock s2f_user2_clk output.

Qsys and user documenation refer to s2f_user2_clk as h2f_user2_clk.

Field Access Macros:

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB   3
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB   3
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH   1
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK   0x00000008
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK   0xfffffff7
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET   0x1
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET(value)   (((value) << 3) & 0x00000008)
 

Data Structures

struct  ALT_CLKMGR_SDRPLL_EN_s
 

Macros

#define ALT_CLKMGR_SDRPLL_EN_OFST   0x18
 

Typedefs

typedef struct
ALT_CLKMGR_SDRPLL_EN_s 
ALT_CLKMGR_SDRPLL_EN_t
 

Data Structure Documentation

struct ALT_CLKMGR_SDRPLL_EN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_SDRPLL_EN.

Data Fields
uint32_t ddrdqsclk: 1 ddr_dqs_clk Enable
uint32_t ddr2xdqsclk: 1 ddr_2x_dqs_clk Enable
uint32_t ddrdqclk: 1 ddr_dq_clk Enable
uint32_t s2fuser2clk: 1 s2f_user2_clk Enable
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_MSB   0

The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_WIDTH   1

The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET_MSK   0x00000001

The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_CLR_MSK   0xfffffffe

The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_RESET   0x1

The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK field value from a register.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQSCLK register field value suitable for setting the register.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_LSB   1

The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_MSB   1

The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_WIDTH   1

The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET_MSK   0x00000002

The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_CLR_MSK   0xfffffffd

The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_RESET   0x1

The reset value of the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK field value from a register.

#define ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_CLKMGR_SDRPLL_EN_DDR2XDQSCLK register field value suitable for setting the register.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_LSB   2

The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_MSB   2

The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_WIDTH   1

The width in bits of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET_MSK   0x00000004

The mask used to set the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_CLR_MSK   0xfffffffb

The mask used to clear the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_RESET   0x1

The reset value of the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_CLKMGR_SDRPLL_EN_DDRDQCLK field value from a register.

#define ALT_CLKMGR_SDRPLL_EN_DDRDQCLK_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_CLKMGR_SDRPLL_EN_DDRDQCLK register field value suitable for setting the register.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_LSB   3

The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_MSB   3

The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_WIDTH   1

The width in bits of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET_MSK   0x00000008

The mask used to set the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_CLR_MSK   0xfffffff7

The mask used to clear the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_RESET   0x1

The reset value of the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK field value from a register.

#define ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_CLKMGR_SDRPLL_EN_S2FUSER2CLK register field value suitable for setting the register.

#define ALT_CLKMGR_SDRPLL_EN_OFST   0x18

The byte offset of the ALT_CLKMGR_SDRPLL_EN register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_SDRPLL_EN.