Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 68 (MMC Transmit Interrupt Mask Register) - MMC_Transmit_Interrupt_Mask

Description

The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach half of their maximum value or maximum value. This register is 32-bits wide.

Register Layout

Bits Access Reset Description
[0] RW 0x0 MMC Transmit Good Bad Octet Counter Interrupt Mask
[1] RW 0x0 MMC Transmit Good Bad Frame Counter Interrupt Mask
[2] RW 0x0 MMC Transmit Broadcast Good Frame Counter Interrupt Mask
[3] RW 0x0 MMC Transmit Multicast Good Frame Counter Interrupt Mask
[4] RW 0x0 MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
[5] RW 0x0 MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
[6] RW 0x0 MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
[7] RW 0x0 MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
[8] RW 0x0 MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
[9] RW 0x0 MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
[10] RW 0x0 MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask
[11] RW 0x0 MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
[12] RW 0x0 MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
[13] RW 0x0 MMC Transmit Underflow Error Frame Counter Interrupt Mask
[14] RW 0x0 MMC Transmit Single Collision Good Frame Counter Interrupt Mask
[15] RW 0x0 MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
[16] RW 0x0 MMC Transmit Deferred Frame Counter Interrupt Mask
[17] RW 0x0 MMC Transmit Late Collision Frame Counter Interrupt Mask
[18] RW 0x0 MMC Transmit Excessive Collision Frame Counter Interrupt Mask
[19] RW 0x0 MMC Transmit Carrier Error Frame Counter Interrupt Mask
[20] RW 0x0 MMC Transmit Good Octet Counter Interrupt Mask
[21] RW 0x0 MMC Transmit Good Frame Counter Interrupt Mask
[22] RW 0x0 MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
[23] RW 0x0 MMC Transmit Pause Frame Counter Interrupt Mask
[24] RW 0x0 MMC Transmit VLAN Good Frame Counter Interrupt Mask
[25] RW 0x0 MMC Transmit Oversize Good Frame Counter Interrupt Mask
[31:26] ??? 0x0 UNDEFINED

Field : MMC Transmit Good Bad Octet Counter Interrupt Mask - txgboctim

Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB   0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB   0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET(value)   (((value) << 0) & 0x00000001)
 

Field : MMC Transmit Good Bad Frame Counter Interrupt Mask - txgbfrmim

Setting this bit masks the interrupt when the txframecount_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET(value)   (((value) << 1) & 0x00000002)
 

Field : MMC Transmit Broadcast Good Frame Counter Interrupt Mask - txbcgfim

Setting this bit masks the interrupt when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB   2
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB   2
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET(value)   (((value) << 2) & 0x00000004)
 

Field : MMC Transmit Multicast Good Frame Counter Interrupt Mask - txmcgfim

Setting this bit masks the interrupt when the txmulticastframes_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB   3
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB   3
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET(value)   (((value) << 3) & 0x00000008)
 

Field : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask - tx64octgbfim

Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB   4
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB   4
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET(value)   (((value) << 4) & 0x00000010)
 

Field : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask - tx65t127octgbfim

Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB   5
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB   5
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET(value)   (((value) << 5) & 0x00000020)
 

Field : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask - tx128t255octgbfim

Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB   6
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB   6
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK   0x00000040
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET(value)   (((value) << 6) & 0x00000040)
 

Field : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask - tx256t511octgbfim

Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB   7
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB   7
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET(value)   (((value) << 7) & 0x00000080)
 

Field : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask - tx512t1023octgbfim

Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB   8
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB   8
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET(value)   (((value) << 8) & 0x00000100)
 

Field : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask - tx1024tmaxoctgbfim

Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB   9
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB   9
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET(value)   (((value) << 9) & 0x00000200)
 

Field : MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask - txucgbfim

Setting this bit masks the interrupt when the txunicastframes_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB   10
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB   10
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask - txmcgbfim

Setting this bit masks the interrupt when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB   11
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB   11
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET(value)   (((value) << 11) & 0x00000800)
 

Field : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask - txbcgbfim

Setting this bit masks the interrupt when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB   12
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB   12
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET(value)   (((value) << 12) & 0x00001000)
 

Field : MMC Transmit Underflow Error Frame Counter Interrupt Mask - txuflowerfim

Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB   13
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB   13
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET(value)   (((value) << 13) & 0x00002000)
 

Field : MMC Transmit Single Collision Good Frame Counter Interrupt Mask - txscolgfim

Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB   14
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB   14
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK   0x00004000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET(value)   (((value) << 14) & 0x00004000)
 

Field : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask - txmcolgfim

Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB   15
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB   15
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK   0x00008000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET(value)   (((value) << 15) & 0x00008000)
 

Field : MMC Transmit Deferred Frame Counter Interrupt Mask - txdeffim

Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB   16
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB   16
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET(value)   (((value) << 16) & 0x00010000)
 

Field : MMC Transmit Late Collision Frame Counter Interrupt Mask - txlatcolfim

Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB   17
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB   17
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK   0x00020000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK   0xfffdffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET(value)   (((value) << 17) & 0x00020000)
 

Field : MMC Transmit Excessive Collision Frame Counter Interrupt Mask - txexcolfim

Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB   18
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB   18
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET(value)   (((value) << 18) & 0x00040000)
 

Field : MMC Transmit Carrier Error Frame Counter Interrupt Mask - txcarerfim

Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB   19
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB   19
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET(value)   (((value) << 19) & 0x00080000)
 

Field : MMC Transmit Good Octet Counter Interrupt Mask - txgoctim

Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB   20
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB   20
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET(value)   (((value) << 20) & 0x00100000)
 

Field : MMC Transmit Good Frame Counter Interrupt Mask - txgfrmim

Setting this bit masks the interrupt when the txframecount_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB   21
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB   21
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET(value)   (((value) << 21) & 0x00200000)
 

Field : MMC Transmit Excessive Deferral Frame Counter Interrupt Mask - txexdeffim

Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB   22
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB   22
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK   0x00400000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET(value)   (((value) << 22) & 0x00400000)
 

Field : MMC Transmit Pause Frame Counter Interrupt Mask - txpausfim

Setting this bit masks the interrupt when the txpauseframes counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB   23
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB   23
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK   0x00800000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET(value)   (((value) << 23) & 0x00800000)
 

Field : MMC Transmit VLAN Good Frame Counter Interrupt Mask - txvlangfim

Setting this bit masks the interrupt when the txvlanframes_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB   24
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB   24
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET(value)   (((value) << 24) & 0x01000000)
 

Field : MMC Transmit Oversize Good Frame Counter Interrupt Mask - txosizegfim

Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB   25
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB   25
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET(value)   (((value) << 25) & 0x02000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MMC_TX_INT_MSK_s
 

Macros

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST   0x110
 
#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MMC_TX_INT_MSK_s 
ALT_EMAC_GMAC_MMC_TX_INT_MSK_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MMC_TX_INT_MSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT_MSK.

Data Fields
uint32_t txgboctim: 1 MMC Transmit Good Bad Octet Counter Interrupt Mask
uint32_t txgbfrmim: 1 MMC Transmit Good Bad Frame Counter Interrupt Mask
uint32_t txbcgfim: 1 MMC Transmit Broadcast Good Frame Counter Interrupt Mask
uint32_t txmcgfim: 1 MMC Transmit Multicast Good Frame Counter Interrupt Mask
uint32_t tx64octgbfim: 1 MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
uint32_t tx65t127octgbfim: 1 MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
uint32_t tx128t255octgbfim: 1 MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
uint32_t tx256t511octgbfim: 1 MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
uint32_t tx512t1023octgbfim: 1 MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
uint32_t tx1024tmaxoctgbfim: 1 MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
uint32_t txucgbfim: 1 MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask
uint32_t txmcgbfim: 1 MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
uint32_t txbcgbfim: 1 MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
uint32_t txuflowerfim: 1 MMC Transmit Underflow Error Frame Counter Interrupt Mask
uint32_t txscolgfim: 1 MMC Transmit Single Collision Good Frame Counter Interrupt Mask
uint32_t txmcolgfim: 1 MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
uint32_t txdeffim: 1 MMC Transmit Deferred Frame Counter Interrupt Mask
uint32_t txlatcolfim: 1 MMC Transmit Late Collision Frame Counter Interrupt Mask
uint32_t txexcolfim: 1 MMC Transmit Excessive Collision Frame Counter Interrupt Mask
uint32_t txcarerfim: 1 MMC Transmit Carrier Error Frame Counter Interrupt Mask
uint32_t txgoctim: 1 MMC Transmit Good Octet Counter Interrupt Mask
uint32_t txgfrmim: 1 MMC Transmit Good Frame Counter Interrupt Mask
uint32_t txexdeffim: 1 MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
uint32_t txpausfim: 1 MMC Transmit Pause Frame Counter Interrupt Mask
uint32_t txvlangfim: 1 MMC Transmit VLAN Good Frame Counter Interrupt Mask
uint32_t txosizegfim: 1 MMC Transmit Oversize Good Frame Counter Interrupt Mask
uint32_t __pad0__: 6 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBOCTIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GBFRMIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_64OCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_65T127OCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_128T255OCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_256T511OCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_512T1023OCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_1024TMAXOCTGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UCGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_BCGBFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_UFLOWERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_SCOLGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_MCOLGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_DEFFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET_MSK   0x00020000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_CLR_MSK   0xfffdffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_LATCOLFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXCOLFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_CARERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GOCTIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_GFRMIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_EXDEFFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_PAUSFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_VLANGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_MMC_TX_INT_MSK_OSIZEGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST   0x110

The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register from the beginning of the component.

#define ALT_EMAC_GMAC_MMC_TX_INT_MSK_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_MSK_OFST))

The address of the ALT_EMAC_GMAC_MMC_TX_INT_MSK register.

Typedef Documentation