Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_sdr.h
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32 
35 #ifndef __ALTERA_ALT_SDR_H__
36 #define __ALTERA_ALT_SDR_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
96 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_LSB 0
97 
98 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_MSB 2
99 
100 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_WIDTH 3
101 
102 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET_MSK 0x00000007
103 
104 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_CLR_MSK 0xfffffff8
105 
106 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_RESET 0x0
107 
108 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_GET(value) (((value) & 0x00000007) >> 0)
109 
110 #define ALT_SDR_CTL_CTLCFG_MEMTYPE_SET(value) (((value) << 0) & 0x00000007)
111 
126 #define ALT_SDR_CTL_CTLCFG_MEMBL_LSB 3
127 
128 #define ALT_SDR_CTL_CTLCFG_MEMBL_MSB 7
129 
130 #define ALT_SDR_CTL_CTLCFG_MEMBL_WIDTH 5
131 
132 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET_MSK 0x000000f8
133 
134 #define ALT_SDR_CTL_CTLCFG_MEMBL_CLR_MSK 0xffffff07
135 
136 #define ALT_SDR_CTL_CTLCFG_MEMBL_RESET 0x0
137 
138 #define ALT_SDR_CTL_CTLCFG_MEMBL_GET(value) (((value) & 0x000000f8) >> 3)
139 
140 #define ALT_SDR_CTL_CTLCFG_MEMBL_SET(value) (((value) << 3) & 0x000000f8)
141 
155 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_LSB 8
156 
157 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_MSB 9
158 
159 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_WIDTH 2
160 
161 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET_MSK 0x00000300
162 
163 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_CLR_MSK 0xfffffcff
164 
165 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_RESET 0x0
166 
167 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_GET(value) (((value) & 0x00000300) >> 8)
168 
169 #define ALT_SDR_CTL_CTLCFG_ADDRORDER_SET(value) (((value) << 8) & 0x00000300)
170 
182 #define ALT_SDR_CTL_CTLCFG_ECCEN_LSB 10
183 
184 #define ALT_SDR_CTL_CTLCFG_ECCEN_MSB 10
185 
186 #define ALT_SDR_CTL_CTLCFG_ECCEN_WIDTH 1
187 
188 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET_MSK 0x00000400
189 
190 #define ALT_SDR_CTL_CTLCFG_ECCEN_CLR_MSK 0xfffffbff
191 
192 #define ALT_SDR_CTL_CTLCFG_ECCEN_RESET 0x0
193 
194 #define ALT_SDR_CTL_CTLCFG_ECCEN_GET(value) (((value) & 0x00000400) >> 10)
195 
196 #define ALT_SDR_CTL_CTLCFG_ECCEN_SET(value) (((value) << 10) & 0x00000400)
197 
208 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_LSB 11
209 
210 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_MSB 11
211 
212 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_WIDTH 1
213 
214 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET_MSK 0x00000800
215 
216 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_CLR_MSK 0xfffff7ff
217 
218 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_RESET 0x0
219 
220 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_GET(value) (((value) & 0x00000800) >> 11)
221 
222 #define ALT_SDR_CTL_CTLCFG_ECCCORREN_SET(value) (((value) << 11) & 0x00000800)
223 
235 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_LSB 12
236 
237 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_MSB 12
238 
239 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_WIDTH 1
240 
241 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET_MSK 0x00001000
242 
243 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_CLR_MSK 0xffffefff
244 
245 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_RESET 0x0
246 
247 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_GET(value) (((value) & 0x00001000) >> 12)
248 
249 #define ALT_SDR_CTL_CTLCFG_CFG_EN_ECC_CODE_OVERWRS_SET(value) (((value) << 12) & 0x00001000)
250 
261 #define ALT_SDR_CTL_CTLCFG_GENSBE_LSB 13
262 
263 #define ALT_SDR_CTL_CTLCFG_GENSBE_MSB 13
264 
265 #define ALT_SDR_CTL_CTLCFG_GENSBE_WIDTH 1
266 
267 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET_MSK 0x00002000
268 
269 #define ALT_SDR_CTL_CTLCFG_GENSBE_CLR_MSK 0xffffdfff
270 
271 #define ALT_SDR_CTL_CTLCFG_GENSBE_RESET 0x0
272 
273 #define ALT_SDR_CTL_CTLCFG_GENSBE_GET(value) (((value) & 0x00002000) >> 13)
274 
275 #define ALT_SDR_CTL_CTLCFG_GENSBE_SET(value) (((value) << 13) & 0x00002000)
276 
287 #define ALT_SDR_CTL_CTLCFG_GENDBE_LSB 14
288 
289 #define ALT_SDR_CTL_CTLCFG_GENDBE_MSB 14
290 
291 #define ALT_SDR_CTL_CTLCFG_GENDBE_WIDTH 1
292 
293 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET_MSK 0x00004000
294 
295 #define ALT_SDR_CTL_CTLCFG_GENDBE_CLR_MSK 0xffffbfff
296 
297 #define ALT_SDR_CTL_CTLCFG_GENDBE_RESET 0x0
298 
299 #define ALT_SDR_CTL_CTLCFG_GENDBE_GET(value) (((value) & 0x00004000) >> 14)
300 
301 #define ALT_SDR_CTL_CTLCFG_GENDBE_SET(value) (((value) << 14) & 0x00004000)
302 
313 #define ALT_SDR_CTL_CTLCFG_REORDEREN_LSB 15
314 
315 #define ALT_SDR_CTL_CTLCFG_REORDEREN_MSB 15
316 
317 #define ALT_SDR_CTL_CTLCFG_REORDEREN_WIDTH 1
318 
319 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET_MSK 0x00008000
320 
321 #define ALT_SDR_CTL_CTLCFG_REORDEREN_CLR_MSK 0xffff7fff
322 
323 #define ALT_SDR_CTL_CTLCFG_REORDEREN_RESET 0x0
324 
325 #define ALT_SDR_CTL_CTLCFG_REORDEREN_GET(value) (((value) & 0x00008000) >> 15)
326 
327 #define ALT_SDR_CTL_CTLCFG_REORDEREN_SET(value) (((value) << 15) & 0x00008000)
328 
340 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_LSB 16
341 
342 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_MSB 21
343 
344 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_WIDTH 6
345 
346 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET_MSK 0x003f0000
347 
348 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_CLR_MSK 0xffc0ffff
349 
350 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_RESET 0x0
351 
352 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_GET(value) (((value) & 0x003f0000) >> 16)
353 
354 #define ALT_SDR_CTL_CTLCFG_STARVELIMIT_SET(value) (((value) << 16) & 0x003f0000)
355 
365 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_LSB 22
366 
367 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_MSB 22
368 
369 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_WIDTH 1
370 
371 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET_MSK 0x00400000
372 
373 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_CLR_MSK 0xffbfffff
374 
375 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_RESET 0x0
376 
377 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_GET(value) (((value) & 0x00400000) >> 22)
378 
379 #define ALT_SDR_CTL_CTLCFG_DQSTRKEN_SET(value) (((value) << 22) & 0x00400000)
380 
390 #define ALT_SDR_CTL_CTLCFG_NODMPINS_LSB 23
391 
392 #define ALT_SDR_CTL_CTLCFG_NODMPINS_MSB 23
393 
394 #define ALT_SDR_CTL_CTLCFG_NODMPINS_WIDTH 1
395 
396 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET_MSK 0x00800000
397 
398 #define ALT_SDR_CTL_CTLCFG_NODMPINS_CLR_MSK 0xff7fffff
399 
400 #define ALT_SDR_CTL_CTLCFG_NODMPINS_RESET 0x0
401 
402 #define ALT_SDR_CTL_CTLCFG_NODMPINS_GET(value) (((value) & 0x00800000) >> 23)
403 
404 #define ALT_SDR_CTL_CTLCFG_NODMPINS_SET(value) (((value) << 23) & 0x00800000)
405 
416 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_LSB 24
417 
418 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_MSB 24
419 
420 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_WIDTH 1
421 
422 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET_MSK 0x01000000
423 
424 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_CLR_MSK 0xfeffffff
425 
426 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_RESET 0x0
427 
428 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_GET(value) (((value) & 0x01000000) >> 24)
429 
430 #define ALT_SDR_CTL_CTLCFG_BURSTINTREN_SET(value) (((value) << 24) & 0x01000000)
431 
442 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_LSB 25
443 
444 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_MSB 25
445 
446 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_WIDTH 1
447 
448 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET_MSK 0x02000000
449 
450 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_CLR_MSK 0xfdffffff
451 
452 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_RESET 0x0
453 
454 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_GET(value) (((value) & 0x02000000) >> 25)
455 
456 #define ALT_SDR_CTL_CTLCFG_BURSTTERMEN_SET(value) (((value) << 25) & 0x02000000)
457 
458 #ifndef __ASSEMBLY__
459 
470 {
471  uint32_t memtype : 3;
472  uint32_t membl : 5;
473  uint32_t addrorder : 2;
474  uint32_t eccen : 1;
475  uint32_t ecccorren : 1;
477  uint32_t gensbe : 1;
478  uint32_t gendbe : 1;
479  uint32_t reorderen : 1;
480  uint32_t starvelimit : 6;
481  uint32_t dqstrken : 1;
482  uint32_t nodmpins : 1;
483  uint32_t burstintren : 1;
484  uint32_t bursttermen : 1;
485  uint32_t : 6;
486 };
487 
490 #endif /* __ASSEMBLY__ */
491 
493 #define ALT_SDR_CTL_CTLCFG_OFST 0x0
494 
522 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_LSB 0
523 
524 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_MSB 3
525 
526 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_WIDTH 4
527 
528 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET_MSK 0x0000000f
529 
530 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_CLR_MSK 0xfffffff0
531 
532 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_RESET 0x0
533 
534 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_GET(value) (((value) & 0x0000000f) >> 0)
535 
536 #define ALT_SDR_CTL_DRAMTIMING1_TCWL_SET(value) (((value) << 0) & 0x0000000f)
537 
547 #define ALT_SDR_CTL_DRAMTIMING1_TAL_LSB 4
548 
549 #define ALT_SDR_CTL_DRAMTIMING1_TAL_MSB 8
550 
551 #define ALT_SDR_CTL_DRAMTIMING1_TAL_WIDTH 5
552 
553 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET_MSK 0x000001f0
554 
555 #define ALT_SDR_CTL_DRAMTIMING1_TAL_CLR_MSK 0xfffffe0f
556 
557 #define ALT_SDR_CTL_DRAMTIMING1_TAL_RESET 0x0
558 
559 #define ALT_SDR_CTL_DRAMTIMING1_TAL_GET(value) (((value) & 0x000001f0) >> 4)
560 
561 #define ALT_SDR_CTL_DRAMTIMING1_TAL_SET(value) (((value) << 4) & 0x000001f0)
562 
572 #define ALT_SDR_CTL_DRAMTIMING1_TCL_LSB 9
573 
574 #define ALT_SDR_CTL_DRAMTIMING1_TCL_MSB 13
575 
576 #define ALT_SDR_CTL_DRAMTIMING1_TCL_WIDTH 5
577 
578 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET_MSK 0x00003e00
579 
580 #define ALT_SDR_CTL_DRAMTIMING1_TCL_CLR_MSK 0xffffc1ff
581 
582 #define ALT_SDR_CTL_DRAMTIMING1_TCL_RESET 0x0
583 
584 #define ALT_SDR_CTL_DRAMTIMING1_TCL_GET(value) (((value) & 0x00003e00) >> 9)
585 
586 #define ALT_SDR_CTL_DRAMTIMING1_TCL_SET(value) (((value) << 9) & 0x00003e00)
587 
597 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_LSB 14
598 
599 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_MSB 17
600 
601 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_WIDTH 4
602 
603 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET_MSK 0x0003c000
604 
605 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_CLR_MSK 0xfffc3fff
606 
607 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_RESET 0x0
608 
609 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_GET(value) (((value) & 0x0003c000) >> 14)
610 
611 #define ALT_SDR_CTL_DRAMTIMING1_TRRD_SET(value) (((value) << 14) & 0x0003c000)
612 
622 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_LSB 18
623 
624 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_MSB 23
625 
626 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_WIDTH 6
627 
628 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET_MSK 0x00fc0000
629 
630 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_CLR_MSK 0xff03ffff
631 
632 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_RESET 0x0
633 
634 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_GET(value) (((value) & 0x00fc0000) >> 18)
635 
636 #define ALT_SDR_CTL_DRAMTIMING1_TFAW_SET(value) (((value) << 18) & 0x00fc0000)
637 
647 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_LSB 24
648 
649 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_MSB 31
650 
651 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_WIDTH 8
652 
653 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET_MSK 0xff000000
654 
655 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_CLR_MSK 0x00ffffff
656 
657 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_RESET 0x0
658 
659 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_GET(value) (((value) & 0xff000000) >> 24)
660 
661 #define ALT_SDR_CTL_DRAMTIMING1_TRFC_SET(value) (((value) << 24) & 0xff000000)
662 
663 #ifndef __ASSEMBLY__
664 
675 {
676  uint32_t tcwl : 4;
677  uint32_t tal : 5;
678  uint32_t tcl : 5;
679  uint32_t trrd : 4;
680  uint32_t tfaw : 6;
681  uint32_t trfc : 8;
682 };
683 
686 #endif /* __ASSEMBLY__ */
687 
689 #define ALT_SDR_CTL_DRAMTIMING1_OFST 0x4
690 
718 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0
719 
720 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12
721 
722 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13
723 
724 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff
725 
726 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000
727 
728 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0
729 
730 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0)
731 
732 #define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff)
733 
743 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13
744 
745 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16
746 
747 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4
748 
749 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000
750 
751 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff
752 
753 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0
754 
755 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13)
756 
757 #define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000)
758 
768 #define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17
769 
770 #define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20
771 
772 #define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4
773 
774 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000
775 
776 #define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff
777 
778 #define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0
779 
780 #define ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17)
781 
782 #define ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000)
783 
793 #define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21
794 
795 #define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24
796 
797 #define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4
798 
799 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000
800 
801 #define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff
802 
803 #define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0
804 
805 #define ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21)
806 
807 #define ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000)
808 
818 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25
819 
820 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28
821 
822 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4
823 
824 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000
825 
826 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff
827 
828 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0
829 
830 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25)
831 
832 #define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000)
833 
834 #ifndef __ASSEMBLY__
835 
846 {
847  uint32_t trefi : 13;
848  uint32_t trcd : 4;
849  uint32_t trp : 4;
850  uint32_t twr : 4;
851  uint32_t twtr : 4;
852  uint32_t : 3;
853 };
854 
857 #endif /* __ASSEMBLY__ */
858 
860 #define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8
861 
889 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_LSB 0
890 
891 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_MSB 3
892 
893 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_WIDTH 4
894 
895 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET_MSK 0x0000000f
896 
897 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_CLR_MSK 0xfffffff0
898 
899 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_RESET 0x0
900 
901 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_GET(value) (((value) & 0x0000000f) >> 0)
902 
903 #define ALT_SDR_CTL_DRAMTIMING3_TRTP_SET(value) (((value) << 0) & 0x0000000f)
904 
914 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_LSB 4
915 
916 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_MSB 8
917 
918 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_WIDTH 5
919 
920 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET_MSK 0x000001f0
921 
922 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_CLR_MSK 0xfffffe0f
923 
924 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_RESET 0x0
925 
926 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_GET(value) (((value) & 0x000001f0) >> 4)
927 
928 #define ALT_SDR_CTL_DRAMTIMING3_TRAS_SET(value) (((value) << 4) & 0x000001f0)
929 
939 #define ALT_SDR_CTL_DRAMTIMING3_TRC_LSB 9
940 
941 #define ALT_SDR_CTL_DRAMTIMING3_TRC_MSB 14
942 
943 #define ALT_SDR_CTL_DRAMTIMING3_TRC_WIDTH 6
944 
945 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET_MSK 0x00007e00
946 
947 #define ALT_SDR_CTL_DRAMTIMING3_TRC_CLR_MSK 0xffff81ff
948 
949 #define ALT_SDR_CTL_DRAMTIMING3_TRC_RESET 0x0
950 
951 #define ALT_SDR_CTL_DRAMTIMING3_TRC_GET(value) (((value) & 0x00007e00) >> 9)
952 
953 #define ALT_SDR_CTL_DRAMTIMING3_TRC_SET(value) (((value) << 9) & 0x00007e00)
954 
964 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_LSB 15
965 
966 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_MSB 18
967 
968 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_WIDTH 4
969 
970 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET_MSK 0x00078000
971 
972 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_CLR_MSK 0xfff87fff
973 
974 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_RESET 0x0
975 
976 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_GET(value) (((value) & 0x00078000) >> 15)
977 
978 #define ALT_SDR_CTL_DRAMTIMING3_TMRD_SET(value) (((value) << 15) & 0x00078000)
979 
989 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_LSB 19
990 
991 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_MSB 22
992 
993 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_WIDTH 4
994 
995 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET_MSK 0x00780000
996 
997 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_CLR_MSK 0xff87ffff
998 
999 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_RESET 0x0
1000 
1001 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_GET(value) (((value) & 0x00780000) >> 19)
1002 
1003 #define ALT_SDR_CTL_DRAMTIMING3_TCCD_SET(value) (((value) << 19) & 0x00780000)
1004 
1005 #ifndef __ASSEMBLY__
1006 
1017 {
1018  uint32_t trtp : 4;
1019  uint32_t tras : 5;
1020  uint32_t trc : 6;
1021  uint32_t tmrd : 4;
1022  uint32_t tccd : 4;
1023  uint32_t : 9;
1024 };
1025 
1028 #endif /* __ASSEMBLY__ */
1029 
1031 #define ALT_SDR_CTL_DRAMTIMING3_OFST 0xc
1032 
1058 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB 0
1059 
1060 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB 9
1061 
1062 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH 10
1063 
1064 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK 0x000003ff
1065 
1066 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK 0xfffffc00
1067 
1068 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET 0x0
1069 
1070 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value) (((value) & 0x000003ff) >> 0)
1071 
1072 #define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value) (((value) << 0) & 0x000003ff)
1073 
1083 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB 10
1084 
1085 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB 19
1086 
1087 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH 10
1088 
1089 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK 0x000ffc00
1090 
1091 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK 0xfff003ff
1092 
1093 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET 0x0
1094 
1095 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value) (((value) & 0x000ffc00) >> 10)
1096 
1097 #define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value) (((value) << 10) & 0x000ffc00)
1098 
1109 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20
1110 
1111 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB 23
1112 
1113 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH 4
1114 
1115 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK 0x00f00000
1116 
1117 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK 0xff0fffff
1118 
1119 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET 0x0
1120 
1121 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value) (((value) & 0x00f00000) >> 20)
1122 
1123 #define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value) (((value) << 20) & 0x00f00000)
1124 
1125 #ifndef __ASSEMBLY__
1126 
1137 {
1138  uint32_t selfrfshexit : 10;
1139  uint32_t pwrdownexit : 10;
1140  uint32_t minpwrsavecycles : 4;
1141  uint32_t : 8;
1142 };
1143 
1146 #endif /* __ASSEMBLY__ */
1147 
1149 #define ALT_SDR_CTL_DRAMTIMING4_OFST 0x10
1150 
1175 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB 0
1176 
1177 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB 15
1178 
1179 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH 16
1180 
1181 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK 0x0000ffff
1182 
1183 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK 0xffff0000
1184 
1185 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET 0x0
1186 
1187 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value) (((value) & 0x0000ffff) >> 0)
1188 
1189 #define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value) (((value) << 0) & 0x0000ffff)
1190 
1202 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB 16
1203 
1204 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB 19
1205 
1206 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH 4
1207 
1208 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK 0x000f0000
1209 
1210 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK 0xfff0ffff
1211 
1212 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET 0x0
1213 
1214 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value) (((value) & 0x000f0000) >> 16)
1215 
1216 #define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value) (((value) << 16) & 0x000f0000)
1217 
1218 #ifndef __ASSEMBLY__
1219 
1230 {
1231  uint32_t autopdcycles : 16;
1232  uint32_t clkdisablecycles : 4;
1233  uint32_t : 12;
1234 };
1235 
1238 #endif /* __ASSEMBLY__ */
1239 
1241 #define ALT_SDR_CTL_LOWPWRTIMING_OFST 0x14
1242 
1271 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_LSB 0
1272 
1273 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_MSB 3
1274 
1275 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_WIDTH 4
1276 
1277 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET_MSK 0x0000000f
1278 
1279 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_CLR_MSK 0xfffffff0
1280 
1281 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_RESET 0x0
1282 
1283 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_GET(value) (((value) & 0x0000000f) >> 0)
1284 
1285 #define ALT_SDR_CTL_DRAMODT_CFG_WR_ODT_CHIP_SET(value) (((value) << 0) & 0x0000000f)
1286 
1296 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_LSB 4
1297 
1298 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_MSB 7
1299 
1300 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_WIDTH 4
1301 
1302 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET_MSK 0x000000f0
1303 
1304 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_CLR_MSK 0xffffff0f
1305 
1306 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_RESET 0x0
1307 
1308 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_GET(value) (((value) & 0x000000f0) >> 4)
1309 
1310 #define ALT_SDR_CTL_DRAMODT_CFG_RD_ODT_CHIP_SET(value) (((value) << 4) & 0x000000f0)
1311 
1312 #ifndef __ASSEMBLY__
1313 
1324 {
1325  uint32_t cfg_write_odt_chip : 4;
1326  uint32_t cfg_read_odt_chip : 4;
1327  uint32_t : 24;
1328 };
1329 
1332 #endif /* __ASSEMBLY__ */
1333 
1335 #define ALT_SDR_CTL_DRAMODT_OFST 0x18
1336 
1364 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_LSB 0
1365 
1366 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_MSB 4
1367 
1368 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_WIDTH 5
1369 
1370 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET_MSK 0x0000001f
1371 
1372 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_CLR_MSK 0xffffffe0
1373 
1374 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_RESET 0x0
1375 
1376 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_GET(value) (((value) & 0x0000001f) >> 0)
1377 
1378 #define ALT_SDR_CTL_DRAMADDRW_COLBITS_SET(value) (((value) << 0) & 0x0000001f)
1379 
1389 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_LSB 5
1390 
1391 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_MSB 9
1392 
1393 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_WIDTH 5
1394 
1395 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET_MSK 0x000003e0
1396 
1397 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_CLR_MSK 0xfffffc1f
1398 
1399 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_RESET 0x0
1400 
1401 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_GET(value) (((value) & 0x000003e0) >> 5)
1402 
1403 #define ALT_SDR_CTL_DRAMADDRW_ROWBITS_SET(value) (((value) << 5) & 0x000003e0)
1404 
1414 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_LSB 10
1415 
1416 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_MSB 12
1417 
1418 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_WIDTH 3
1419 
1420 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET_MSK 0x00001c00
1421 
1422 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_CLR_MSK 0xffffe3ff
1423 
1424 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_RESET 0x0
1425 
1426 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_GET(value) (((value) & 0x00001c00) >> 10)
1427 
1428 #define ALT_SDR_CTL_DRAMADDRW_BANKBITS_SET(value) (((value) << 10) & 0x00001c00)
1429 
1440 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_LSB 13
1441 
1442 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_MSB 15
1443 
1444 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_WIDTH 3
1445 
1446 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET_MSK 0x0000e000
1447 
1448 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_CLR_MSK 0xffff1fff
1449 
1450 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_RESET 0x0
1451 
1452 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_GET(value) (((value) & 0x0000e000) >> 13)
1453 
1454 #define ALT_SDR_CTL_DRAMADDRW_CSBITS_SET(value) (((value) << 13) & 0x0000e000)
1455 
1456 #ifndef __ASSEMBLY__
1457 
1468 {
1469  uint32_t colbits : 5;
1470  uint32_t rowbits : 5;
1471  uint32_t bankbits : 3;
1472  uint32_t csbits : 3;
1473  uint32_t : 16;
1474 };
1475 
1478 #endif /* __ASSEMBLY__ */
1479 
1481 #define ALT_SDR_CTL_DRAMADDRW_OFST 0x2c
1482 
1506 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_LSB 0
1507 
1508 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_MSB 7
1509 
1510 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_WIDTH 8
1511 
1512 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET_MSK 0x000000ff
1513 
1514 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_CLR_MSK 0xffffff00
1515 
1516 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_RESET 0x0
1517 
1518 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_GET(value) (((value) & 0x000000ff) >> 0)
1519 
1520 #define ALT_SDR_CTL_DRAMIFWIDTH_IFWIDTH_SET(value) (((value) << 0) & 0x000000ff)
1521 
1522 #ifndef __ASSEMBLY__
1523 
1534 {
1535  uint32_t ifwidth : 8;
1536  uint32_t : 24;
1537 };
1538 
1541 #endif /* __ASSEMBLY__ */
1542 
1544 #define ALT_SDR_CTL_DRAMIFWIDTH_OFST 0x30
1545 
1568 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_LSB 0
1569 
1570 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_MSB 3
1571 
1572 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_WIDTH 4
1573 
1574 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET_MSK 0x0000000f
1575 
1576 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_CLR_MSK 0xfffffff0
1577 
1578 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_RESET 0x0
1579 
1580 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_GET(value) (((value) & 0x0000000f) >> 0)
1581 
1582 #define ALT_SDR_CTL_DRAMDEVWIDTH_DEVWIDTH_SET(value) (((value) << 0) & 0x0000000f)
1583 
1584 #ifndef __ASSEMBLY__
1585 
1596 {
1597  uint32_t devwidth : 4;
1598  uint32_t : 28;
1599 };
1600 
1603 #endif /* __ASSEMBLY__ */
1604 
1606 #define ALT_SDR_CTL_DRAMDEVWIDTH_OFST 0x34
1607 
1634 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_LSB 0
1635 
1636 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_MSB 0
1637 
1638 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_WIDTH 1
1639 
1640 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET_MSK 0x00000001
1641 
1642 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_CLR_MSK 0xfffffffe
1643 
1644 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_RESET 0x0
1645 
1646 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_GET(value) (((value) & 0x00000001) >> 0)
1647 
1648 #define ALT_SDR_CTL_DRAMSTS_CALSUCCESS_SET(value) (((value) << 0) & 0x00000001)
1649 
1659 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_LSB 1
1660 
1661 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_MSB 1
1662 
1663 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_WIDTH 1
1664 
1665 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET_MSK 0x00000002
1666 
1667 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_CLR_MSK 0xfffffffd
1668 
1669 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_RESET 0x0
1670 
1671 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_GET(value) (((value) & 0x00000002) >> 1)
1672 
1673 #define ALT_SDR_CTL_DRAMSTS_CALFAIL_SET(value) (((value) << 1) & 0x00000002)
1674 
1684 #define ALT_SDR_CTL_DRAMSTS_SBEERR_LSB 2
1685 
1686 #define ALT_SDR_CTL_DRAMSTS_SBEERR_MSB 2
1687 
1688 #define ALT_SDR_CTL_DRAMSTS_SBEERR_WIDTH 1
1689 
1690 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET_MSK 0x00000004
1691 
1692 #define ALT_SDR_CTL_DRAMSTS_SBEERR_CLR_MSK 0xfffffffb
1693 
1694 #define ALT_SDR_CTL_DRAMSTS_SBEERR_RESET 0x0
1695 
1696 #define ALT_SDR_CTL_DRAMSTS_SBEERR_GET(value) (((value) & 0x00000004) >> 2)
1697 
1698 #define ALT_SDR_CTL_DRAMSTS_SBEERR_SET(value) (((value) << 2) & 0x00000004)
1699 
1709 #define ALT_SDR_CTL_DRAMSTS_DBEERR_LSB 3
1710 
1711 #define ALT_SDR_CTL_DRAMSTS_DBEERR_MSB 3
1712 
1713 #define ALT_SDR_CTL_DRAMSTS_DBEERR_WIDTH 1
1714 
1715 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET_MSK 0x00000008
1716 
1717 #define ALT_SDR_CTL_DRAMSTS_DBEERR_CLR_MSK 0xfffffff7
1718 
1719 #define ALT_SDR_CTL_DRAMSTS_DBEERR_RESET 0x0
1720 
1721 #define ALT_SDR_CTL_DRAMSTS_DBEERR_GET(value) (((value) & 0x00000008) >> 3)
1722 
1723 #define ALT_SDR_CTL_DRAMSTS_DBEERR_SET(value) (((value) << 3) & 0x00000008)
1724 
1734 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_LSB 4
1735 
1736 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_MSB 4
1737 
1738 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_WIDTH 1
1739 
1740 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET_MSK 0x00000010
1741 
1742 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_CLR_MSK 0xffffffef
1743 
1744 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_RESET 0x0
1745 
1746 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_GET(value) (((value) & 0x00000010) >> 4)
1747 
1748 #define ALT_SDR_CTL_DRAMSTS_CORRDROP_SET(value) (((value) << 4) & 0x00000010)
1749 
1750 #ifndef __ASSEMBLY__
1751 
1762 {
1763  uint32_t calsuccess : 1;
1764  uint32_t calfail : 1;
1765  uint32_t sbeerr : 1;
1766  uint32_t dbeerr : 1;
1767  uint32_t corrdrop : 1;
1768  uint32_t : 27;
1769 };
1770 
1773 #endif /* __ASSEMBLY__ */
1774 
1776 #define ALT_SDR_CTL_DRAMSTS_OFST 0x38
1777 
1803 #define ALT_SDR_CTL_DRAMINTR_INTREN_LSB 0
1804 
1805 #define ALT_SDR_CTL_DRAMINTR_INTREN_MSB 0
1806 
1807 #define ALT_SDR_CTL_DRAMINTR_INTREN_WIDTH 1
1808 
1809 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET_MSK 0x00000001
1810 
1811 #define ALT_SDR_CTL_DRAMINTR_INTREN_CLR_MSK 0xfffffffe
1812 
1813 #define ALT_SDR_CTL_DRAMINTR_INTREN_RESET 0x0
1814 
1815 #define ALT_SDR_CTL_DRAMINTR_INTREN_GET(value) (((value) & 0x00000001) >> 0)
1816 
1817 #define ALT_SDR_CTL_DRAMINTR_INTREN_SET(value) (((value) << 0) & 0x00000001)
1818 
1828 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_LSB 1
1829 
1830 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_MSB 1
1831 
1832 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_WIDTH 1
1833 
1834 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET_MSK 0x00000002
1835 
1836 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_CLR_MSK 0xfffffffd
1837 
1838 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_RESET 0x0
1839 
1840 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_GET(value) (((value) & 0x00000002) >> 1)
1841 
1842 #define ALT_SDR_CTL_DRAMINTR_SBEMSK_SET(value) (((value) << 1) & 0x00000002)
1843 
1853 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_LSB 2
1854 
1855 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_MSB 2
1856 
1857 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_WIDTH 1
1858 
1859 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET_MSK 0x00000004
1860 
1861 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_CLR_MSK 0xfffffffb
1862 
1863 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_RESET 0x0
1864 
1865 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_GET(value) (((value) & 0x00000004) >> 2)
1866 
1867 #define ALT_SDR_CTL_DRAMINTR_DBEMSK_SET(value) (((value) << 2) & 0x00000004)
1868 
1880 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_LSB 3
1881 
1882 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_MSB 3
1883 
1884 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_WIDTH 1
1885 
1886 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET_MSK 0x00000008
1887 
1888 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_CLR_MSK 0xfffffff7
1889 
1890 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_RESET 0x0
1891 
1892 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_GET(value) (((value) & 0x00000008) >> 3)
1893 
1894 #define ALT_SDR_CTL_DRAMINTR_CORRDROPMSK_SET(value) (((value) << 3) & 0x00000008)
1895 
1906 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_LSB 4
1907 
1908 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_MSB 4
1909 
1910 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_WIDTH 1
1911 
1912 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET_MSK 0x00000010
1913 
1914 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_CLR_MSK 0xffffffef
1915 
1916 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_RESET 0x0
1917 
1918 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_GET(value) (((value) & 0x00000010) >> 4)
1919 
1920 #define ALT_SDR_CTL_DRAMINTR_INTRCLR_SET(value) (((value) << 4) & 0x00000010)
1921 
1922 #ifndef __ASSEMBLY__
1923 
1934 {
1935  uint32_t intren : 1;
1936  uint32_t sbemask : 1;
1937  uint32_t dbemask : 1;
1938  uint32_t corrdropmask : 1;
1939  uint32_t intrclr : 1;
1940  uint32_t : 27;
1941 };
1942 
1945 #endif /* __ASSEMBLY__ */
1946 
1948 #define ALT_SDR_CTL_DRAMINTR_OFST 0x3c
1949 
1972 #define ALT_SDR_CTL_SBECOUNT_COUNT_LSB 0
1973 
1974 #define ALT_SDR_CTL_SBECOUNT_COUNT_MSB 7
1975 
1976 #define ALT_SDR_CTL_SBECOUNT_COUNT_WIDTH 8
1977 
1978 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET_MSK 0x000000ff
1979 
1980 #define ALT_SDR_CTL_SBECOUNT_COUNT_CLR_MSK 0xffffff00
1981 
1982 #define ALT_SDR_CTL_SBECOUNT_COUNT_RESET 0x0
1983 
1984 #define ALT_SDR_CTL_SBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
1985 
1986 #define ALT_SDR_CTL_SBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
1987 
1988 #ifndef __ASSEMBLY__
1989 
2000 {
2001  uint32_t count : 8;
2002  uint32_t : 24;
2003 };
2004 
2007 #endif /* __ASSEMBLY__ */
2008 
2010 #define ALT_SDR_CTL_SBECOUNT_OFST 0x40
2011 
2034 #define ALT_SDR_CTL_DBECOUNT_COUNT_LSB 0
2035 
2036 #define ALT_SDR_CTL_DBECOUNT_COUNT_MSB 7
2037 
2038 #define ALT_SDR_CTL_DBECOUNT_COUNT_WIDTH 8
2039 
2040 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET_MSK 0x000000ff
2041 
2042 #define ALT_SDR_CTL_DBECOUNT_COUNT_CLR_MSK 0xffffff00
2043 
2044 #define ALT_SDR_CTL_DBECOUNT_COUNT_RESET 0x0
2045 
2046 #define ALT_SDR_CTL_DBECOUNT_COUNT_GET(value) (((value) & 0x000000ff) >> 0)
2047 
2048 #define ALT_SDR_CTL_DBECOUNT_COUNT_SET(value) (((value) << 0) & 0x000000ff)
2049 
2050 #ifndef __ASSEMBLY__
2051 
2062 {
2063  uint32_t count : 8;
2064  uint32_t : 24;
2065 };
2066 
2069 #endif /* __ASSEMBLY__ */
2070 
2072 #define ALT_SDR_CTL_DBECOUNT_OFST 0x44
2073 
2094 #define ALT_SDR_CTL_ERRADDR_ADDR_LSB 0
2095 
2096 #define ALT_SDR_CTL_ERRADDR_ADDR_MSB 31
2097 
2098 #define ALT_SDR_CTL_ERRADDR_ADDR_WIDTH 32
2099 
2100 #define ALT_SDR_CTL_ERRADDR_ADDR_SET_MSK 0xffffffff
2101 
2102 #define ALT_SDR_CTL_ERRADDR_ADDR_CLR_MSK 0x00000000
2103 
2104 #define ALT_SDR_CTL_ERRADDR_ADDR_RESET 0x0
2105 
2106 #define ALT_SDR_CTL_ERRADDR_ADDR_GET(value) (((value) & 0xffffffff) >> 0)
2107 
2108 #define ALT_SDR_CTL_ERRADDR_ADDR_SET(value) (((value) << 0) & 0xffffffff)
2109 
2110 #ifndef __ASSEMBLY__
2111 
2122 {
2123  uint32_t addr : 32;
2124 };
2125 
2128 #endif /* __ASSEMBLY__ */
2129 
2131 #define ALT_SDR_CTL_ERRADDR_OFST 0x48
2132 
2155 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_LSB 0
2156 
2157 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_MSB 7
2158 
2159 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_WIDTH 8
2160 
2161 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET_MSK 0x000000ff
2162 
2163 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_CLR_MSK 0xffffff00
2164 
2165 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_RESET 0x0
2166 
2167 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_GET(value) (((value) & 0x000000ff) >> 0)
2168 
2169 #define ALT_SDR_CTL_DROPCOUNT_CORRDROPCOUNT_SET(value) (((value) << 0) & 0x000000ff)
2170 
2171 #ifndef __ASSEMBLY__
2172 
2183 {
2184  uint32_t corrdropcount : 8;
2185  uint32_t : 24;
2186 };
2187 
2190 #endif /* __ASSEMBLY__ */
2191 
2193 #define ALT_SDR_CTL_DROPCOUNT_OFST 0x4c
2194 
2215 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_LSB 0
2216 
2217 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_MSB 31
2218 
2219 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_WIDTH 32
2220 
2221 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET_MSK 0xffffffff
2222 
2223 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_CLR_MSK 0x00000000
2224 
2225 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_RESET 0x0
2226 
2227 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_GET(value) (((value) & 0xffffffff) >> 0)
2228 
2229 #define ALT_SDR_CTL_DROPADDR_CORRDROPADDR_SET(value) (((value) << 0) & 0xffffffff)
2230 
2231 #ifndef __ASSEMBLY__
2232 
2243 {
2244  uint32_t corrdropaddr : 32;
2245 };
2246 
2249 #endif /* __ASSEMBLY__ */
2250 
2252 #define ALT_SDR_CTL_DROPADDR_OFST 0x50
2253 
2281 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0
2282 
2283 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0
2284 
2285 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1
2286 
2287 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001
2288 
2289 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe
2290 
2291 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0
2292 
2293 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0)
2294 
2295 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001)
2296 
2309 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1
2310 
2311 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2
2312 
2313 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2
2314 
2315 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006
2316 
2317 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9
2318 
2319 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0
2320 
2321 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1)
2322 
2323 #define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006)
2324 
2337 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3
2338 
2339 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3
2340 
2341 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1
2342 
2343 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008
2344 
2345 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7
2346 
2347 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0
2348 
2349 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3)
2350 
2351 #define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008)
2352 
2363 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4
2364 
2365 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5
2366 
2367 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2
2368 
2369 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030
2370 
2371 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf
2372 
2373 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0
2374 
2375 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4)
2376 
2377 #define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030)
2378 
2379 #ifndef __ASSEMBLY__
2380 
2391 {
2392  uint32_t deeppwrdnreq : 1;
2393  uint32_t deeppwrdnmask : 2;
2394  uint32_t selfrshreq : 1;
2395  uint32_t selfrfshmask : 2;
2396  uint32_t : 26;
2397 };
2398 
2401 #endif /* __ASSEMBLY__ */
2402 
2404 #define ALT_SDR_CTL_LOWPWREQ_OFST 0x54
2405 
2430 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_LSB 0
2431 
2432 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_MSB 0
2433 
2434 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_WIDTH 1
2435 
2436 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET_MSK 0x00000001
2437 
2438 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_CLR_MSK 0xfffffffe
2439 
2440 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_RESET 0x0
2441 
2442 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_GET(value) (((value) & 0x00000001) >> 0)
2443 
2444 #define ALT_SDR_CTL_LOWPWRACK_DEEPPWRDNACK_SET(value) (((value) << 0) & 0x00000001)
2445 
2455 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_LSB 1
2456 
2457 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_MSB 1
2458 
2459 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_WIDTH 1
2460 
2461 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET_MSK 0x00000002
2462 
2463 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_CLR_MSK 0xfffffffd
2464 
2465 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_RESET 0x0
2466 
2467 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_GET(value) (((value) & 0x00000002) >> 1)
2468 
2469 #define ALT_SDR_CTL_LOWPWRACK_SELFRFSHACK_SET(value) (((value) << 1) & 0x00000002)
2470 
2471 #ifndef __ASSEMBLY__
2472 
2483 {
2484  uint32_t deeppwrdnack : 1;
2485  uint32_t selfrfshack : 1;
2486  uint32_t : 30;
2487 };
2488 
2491 #endif /* __ASSEMBLY__ */
2492 
2494 #define ALT_SDR_CTL_LOWPWRACK_OFST 0x58
2495 
2529 #define ALT_SDR_CTL_STATICCFG_MEMBL_LSB 0
2530 
2531 #define ALT_SDR_CTL_STATICCFG_MEMBL_MSB 1
2532 
2533 #define ALT_SDR_CTL_STATICCFG_MEMBL_WIDTH 2
2534 
2535 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET_MSK 0x00000003
2536 
2537 #define ALT_SDR_CTL_STATICCFG_MEMBL_CLR_MSK 0xfffffffc
2538 
2539 #define ALT_SDR_CTL_STATICCFG_MEMBL_RESET 0x0
2540 
2541 #define ALT_SDR_CTL_STATICCFG_MEMBL_GET(value) (((value) & 0x00000003) >> 0)
2542 
2543 #define ALT_SDR_CTL_STATICCFG_MEMBL_SET(value) (((value) << 0) & 0x00000003)
2544 
2557 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_LSB 2
2558 
2559 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_MSB 2
2560 
2561 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_WIDTH 1
2562 
2563 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET_MSK 0x00000004
2564 
2565 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_CLR_MSK 0xfffffffb
2566 
2567 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_RESET 0x0
2568 
2569 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_GET(value) (((value) & 0x00000004) >> 2)
2570 
2571 #define ALT_SDR_CTL_STATICCFG_USEECCASDATA_SET(value) (((value) << 2) & 0x00000004)
2572 
2583 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_LSB 3
2584 
2585 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_MSB 3
2586 
2587 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_WIDTH 1
2588 
2589 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET_MSK 0x00000008
2590 
2591 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_CLR_MSK 0xfffffff7
2592 
2593 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_RESET 0x0
2594 
2595 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_GET(value) (((value) & 0x00000008) >> 3)
2596 
2597 #define ALT_SDR_CTL_STATICCFG_APPLYCFG_SET(value) (((value) << 3) & 0x00000008)
2598 
2599 #ifndef __ASSEMBLY__
2600 
2611 {
2612  uint32_t membl : 2;
2613  uint32_t useeccasdata : 1;
2614  uint32_t applycfg : 1;
2615  uint32_t : 28;
2616 };
2617 
2620 #endif /* __ASSEMBLY__ */
2621 
2623 #define ALT_SDR_CTL_STATICCFG_OFST 0x5c
2624 
2650 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_LSB 0
2651 
2652 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_MSB 1
2653 
2654 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_WIDTH 2
2655 
2656 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET_MSK 0x00000003
2657 
2658 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_CLR_MSK 0xfffffffc
2659 
2660 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_RESET 0x0
2661 
2662 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_GET(value) (((value) & 0x00000003) >> 0)
2663 
2664 #define ALT_SDR_CTL_CTLWIDTH_CTLWIDTH_SET(value) (((value) << 0) & 0x00000003)
2665 
2666 #ifndef __ASSEMBLY__
2667 
2678 {
2679  uint32_t ctrlwidth : 2;
2680  uint32_t : 30;
2681 };
2682 
2685 #endif /* __ASSEMBLY__ */
2686 
2688 #define ALT_SDR_CTL_CTLWIDTH_OFST 0x60
2689 
2719 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_LSB 10
2720 
2721 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_MSB 19
2722 
2723 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_WIDTH 10
2724 
2725 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET_MSK 0x000ffc00
2726 
2727 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_CLR_MSK 0xfff003ff
2728 
2729 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_RESET 0x0
2730 
2731 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_GET(value) (((value) & 0x000ffc00) >> 10)
2732 
2733 #define ALT_SDR_CTL_PORTCFG_AUTOPCHEN_SET(value) (((value) << 10) & 0x000ffc00)
2734 
2735 #ifndef __ASSEMBLY__
2736 
2747 {
2748  uint32_t : 10;
2749  uint32_t autopchen : 10;
2750  uint32_t : 12;
2751 };
2752 
2755 #endif /* __ASSEMBLY__ */
2756 
2758 #define ALT_SDR_CTL_PORTCFG_OFST 0x7c
2759 
2790 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB 0
2791 
2792 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB 13
2793 
2794 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH 14
2795 
2796 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK 0x00003fff
2797 
2798 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK 0xffffc000
2799 
2800 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET 0x0
2801 
2802 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value) (((value) & 0x00003fff) >> 0)
2803 
2804 #define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value) (((value) << 0) & 0x00003fff)
2805 
2806 #ifndef __ASSEMBLY__
2807 
2818 {
2819  uint32_t portrstn : 14;
2820  uint32_t : 18;
2821 };
2822 
2825 #endif /* __ASSEMBLY__ */
2826 
2828 #define ALT_SDR_CTL_FPGAPORTRST_OFST 0x80
2829 
2859 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_LSB 0
2860 
2861 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_MSB 9
2862 
2863 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_WIDTH 10
2864 
2865 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET_MSK 0x000003ff
2866 
2867 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_CLR_MSK 0xfffffc00
2868 
2869 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_RESET 0x0
2870 
2871 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_GET(value) (((value) & 0x000003ff) >> 0)
2872 
2873 #define ALT_SDR_CTL_PROTPORTDEFAULT_PORTDEFAULT_SET(value) (((value) << 0) & 0x000003ff)
2874 
2875 #ifndef __ASSEMBLY__
2876 
2887 {
2888  uint32_t portdefault : 10;
2889  uint32_t : 22;
2890 };
2891 
2894 #endif /* __ASSEMBLY__ */
2895 
2897 #define ALT_SDR_CTL_PROTPORTDEFAULT_OFST 0x8c
2898 
2931 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_LSB 0
2932 
2933 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_MSB 11
2934 
2935 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_WIDTH 12
2936 
2937 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET_MSK 0x00000fff
2938 
2939 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_CLR_MSK 0xfffff000
2940 
2941 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_RESET 0x0
2942 
2943 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_GET(value) (((value) & 0x00000fff) >> 0)
2944 
2945 #define ALT_SDR_CTL_PROTRULEADDR_LOWADDR_SET(value) (((value) << 0) & 0x00000fff)
2946 
2960 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_LSB 12
2961 
2962 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_MSB 23
2963 
2964 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_WIDTH 12
2965 
2966 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET_MSK 0x00fff000
2967 
2968 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_CLR_MSK 0xff000fff
2969 
2970 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_RESET 0x0
2971 
2972 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_GET(value) (((value) & 0x00fff000) >> 12)
2973 
2974 #define ALT_SDR_CTL_PROTRULEADDR_HIGHADDR_SET(value) (((value) << 12) & 0x00fff000)
2975 
2976 #ifndef __ASSEMBLY__
2977 
2988 {
2989  uint32_t lowaddr : 12;
2990  uint32_t highaddr : 12;
2991  uint32_t : 8;
2992 };
2993 
2996 #endif /* __ASSEMBLY__ */
2997 
2999 #define ALT_SDR_CTL_PROTRULEADDR_OFST 0x90
3000 
3025 #define ALT_SDR_CTL_PROTRULEID_LOWID_LSB 0
3026 
3027 #define ALT_SDR_CTL_PROTRULEID_LOWID_MSB 11
3028 
3029 #define ALT_SDR_CTL_PROTRULEID_LOWID_WIDTH 12
3030 
3031 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET_MSK 0x00000fff
3032 
3033 #define ALT_SDR_CTL_PROTRULEID_LOWID_CLR_MSK 0xfffff000
3034 
3035 #define ALT_SDR_CTL_PROTRULEID_LOWID_RESET 0x0
3036 
3037 #define ALT_SDR_CTL_PROTRULEID_LOWID_GET(value) (((value) & 0x00000fff) >> 0)
3038 
3039 #define ALT_SDR_CTL_PROTRULEID_LOWID_SET(value) (((value) << 0) & 0x00000fff)
3040 
3052 #define ALT_SDR_CTL_PROTRULEID_HIGHID_LSB 12
3053 
3054 #define ALT_SDR_CTL_PROTRULEID_HIGHID_MSB 23
3055 
3056 #define ALT_SDR_CTL_PROTRULEID_HIGHID_WIDTH 12
3057 
3058 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET_MSK 0x00fff000
3059 
3060 #define ALT_SDR_CTL_PROTRULEID_HIGHID_CLR_MSK 0xff000fff
3061 
3062 #define ALT_SDR_CTL_PROTRULEID_HIGHID_RESET 0x0
3063 
3064 #define ALT_SDR_CTL_PROTRULEID_HIGHID_GET(value) (((value) & 0x00fff000) >> 12)
3065 
3066 #define ALT_SDR_CTL_PROTRULEID_HIGHID_SET(value) (((value) << 12) & 0x00fff000)
3067 
3068 #ifndef __ASSEMBLY__
3069 
3080 {
3081  uint32_t lowid : 12;
3082  uint32_t highid : 12;
3083  uint32_t : 8;
3084 };
3085 
3088 #endif /* __ASSEMBLY__ */
3089 
3091 #define ALT_SDR_CTL_PROTRULEID_OFST 0x94
3092 
3122 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_LSB 0
3123 
3124 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_MSB 1
3125 
3126 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_WIDTH 2
3127 
3128 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET_MSK 0x00000003
3129 
3130 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_CLR_MSK 0xfffffffc
3131 
3132 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_RESET 0x0
3133 
3134 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_GET(value) (((value) & 0x00000003) >> 0)
3135 
3136 #define ALT_SDR_CTL_PROTRULEDATA_SECURITY_SET(value) (((value) << 0) & 0x00000003)
3137 
3147 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_LSB 2
3148 
3149 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_MSB 2
3150 
3151 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_WIDTH 1
3152 
3153 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET_MSK 0x00000004
3154 
3155 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_CLR_MSK 0xfffffffb
3156 
3157 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_RESET 0x0
3158 
3159 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_GET(value) (((value) & 0x00000004) >> 2)
3160 
3161 #define ALT_SDR_CTL_PROTRULEDATA_VALIDRULE_SET(value) (((value) << 2) & 0x00000004)
3162 
3175 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_LSB 3
3176 
3177 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_MSB 12
3178 
3179 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_WIDTH 10
3180 
3181 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET_MSK 0x00001ff8
3182 
3183 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_CLR_MSK 0xffffe007
3184 
3185 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_RESET 0x0
3186 
3187 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_GET(value) (((value) & 0x00001ff8) >> 3)
3188 
3189 #define ALT_SDR_CTL_PROTRULEDATA_PORTMSK_SET(value) (((value) << 3) & 0x00001ff8)
3190 
3201 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_LSB 13
3202 
3203 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_MSB 13
3204 
3205 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_WIDTH 1
3206 
3207 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET_MSK 0x00002000
3208 
3209 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_CLR_MSK 0xffffdfff
3210 
3211 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_RESET 0x0
3212 
3213 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_GET(value) (((value) & 0x00002000) >> 13)
3214 
3215 #define ALT_SDR_CTL_PROTRULEDATA_RULERESULT_SET(value) (((value) << 13) & 0x00002000)
3216 
3217 #ifndef __ASSEMBLY__
3218 
3229 {
3230  uint32_t security : 2;
3231  uint32_t validrule : 1;
3232  uint32_t portmask : 10;
3233  uint32_t ruleresult : 1;
3234  uint32_t : 18;
3235 };
3236 
3239 #endif /* __ASSEMBLY__ */
3240 
3242 #define ALT_SDR_CTL_PROTRULEDATA_OFST 0x98
3243 
3270 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_LSB 0
3271 
3272 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_MSB 4
3273 
3274 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_WIDTH 5
3275 
3276 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET_MSK 0x0000001f
3277 
3278 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_CLR_MSK 0xffffffe0
3279 
3280 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_RESET 0x0
3281 
3282 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_GET(value) (((value) & 0x0000001f) >> 0)
3283 
3284 #define ALT_SDR_CTL_PROTRULERDWR_RULEOFFSET_SET(value) (((value) << 0) & 0x0000001f)
3285 
3297 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_LSB 5
3298 
3299 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_MSB 5
3300 
3301 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_WIDTH 1
3302 
3303 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET_MSK 0x00000020
3304 
3305 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_CLR_MSK 0xffffffdf
3306 
3307 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_RESET 0x0
3308 
3309 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_GET(value) (((value) & 0x00000020) >> 5)
3310 
3311 #define ALT_SDR_CTL_PROTRULERDWR_WRRULE_SET(value) (((value) << 5) & 0x00000020)
3312 
3325 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_LSB 6
3326 
3327 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_MSB 6
3328 
3329 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_WIDTH 1
3330 
3331 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET_MSK 0x00000040
3332 
3333 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_CLR_MSK 0xffffffbf
3334 
3335 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_RESET 0x0
3336 
3337 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_GET(value) (((value) & 0x00000040) >> 6)
3338 
3339 #define ALT_SDR_CTL_PROTRULERDWR_RDRULE_SET(value) (((value) << 6) & 0x00000040)
3340 
3341 #ifndef __ASSEMBLY__
3342 
3353 {
3354  uint32_t ruleoffset : 5;
3355  uint32_t writerule : 1;
3356  uint32_t readrule : 1;
3357  uint32_t : 25;
3358 };
3359 
3362 #endif /* __ASSEMBLY__ */
3363 
3365 #define ALT_SDR_CTL_PROTRULERDWR_OFST 0x9c
3366 
3391 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_LSB 0
3392 
3393 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_MSB 19
3394 
3395 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_WIDTH 20
3396 
3397 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET_MSK 0x000fffff
3398 
3399 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_CLR_MSK 0xfff00000
3400 
3401 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_RESET 0x0
3402 
3403 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3404 
3405 #define ALT_SDR_CTL_QOSLOWPRI_LOWPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3406 
3407 #ifndef __ASSEMBLY__
3408 
3419 {
3420  uint32_t lowpriorityval : 20;
3421  uint32_t : 12;
3422 };
3423 
3426 #endif /* __ASSEMBLY__ */
3427 
3429 #define ALT_SDR_CTL_QOSLOWPRI_OFST 0xa0
3430 
3453 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_LSB 0
3454 
3455 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_MSB 19
3456 
3457 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_WIDTH 20
3458 
3459 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET_MSK 0x000fffff
3460 
3461 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_CLR_MSK 0xfff00000
3462 
3463 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_RESET 0x0
3464 
3465 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_GET(value) (((value) & 0x000fffff) >> 0)
3466 
3467 #define ALT_SDR_CTL_QOSHIGHPRI_HIGHPRIORITYVAL_SET(value) (((value) << 0) & 0x000fffff)
3468 
3469 #ifndef __ASSEMBLY__
3470 
3481 {
3482  uint32_t highpriorityval : 20;
3483  uint32_t : 12;
3484 };
3485 
3488 #endif /* __ASSEMBLY__ */
3489 
3491 #define ALT_SDR_CTL_QOSHIGHPRI_OFST 0xa4
3492 
3514 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_LSB 0
3515 
3516 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_MSB 9
3517 
3518 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_WIDTH 10
3519 
3520 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET_MSK 0x000003ff
3521 
3522 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_CLR_MSK 0xfffffc00
3523 
3524 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_RESET 0x0
3525 
3526 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_GET(value) (((value) & 0x000003ff) >> 0)
3527 
3528 #define ALT_SDR_CTL_QOSPRIORITYEN_PRIORITYEN_SET(value) (((value) << 0) & 0x000003ff)
3529 
3530 #ifndef __ASSEMBLY__
3531 
3542 {
3543  uint32_t priorityen : 10;
3544  uint32_t : 22;
3545 };
3546 
3549 #endif /* __ASSEMBLY__ */
3550 
3552 #define ALT_SDR_CTL_QOSPRIORITYEN_OFST 0xa8
3553 
3578 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_LSB 0
3579 
3580 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_MSB 29
3581 
3582 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_WIDTH 30
3583 
3584 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET_MSK 0x3fffffff
3585 
3586 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_CLR_MSK 0xc0000000
3587 
3588 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_RESET 0x0
3589 
3590 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_GET(value) (((value) & 0x3fffffff) >> 0)
3591 
3592 #define ALT_SDR_CTL_MPPRIORITY_USERPRIORITY_SET(value) (((value) << 0) & 0x3fffffff)
3593 
3594 #ifndef __ASSEMBLY__
3595 
3606 {
3607  uint32_t userpriority : 30;
3608  uint32_t : 2;
3609 };
3610 
3613 #endif /* __ASSEMBLY__ */
3614 
3616 #define ALT_SDR_CTL_MPPRIORITY_OFST 0xac
3617 
3642 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_LSB 0
3643 
3644 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_MSB 7
3645 
3646 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_WIDTH 8
3647 
3648 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET_MSK 0x000000ff
3649 
3650 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_CLR_MSK 0xffffff00
3651 
3652 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_RESET 0x0
3653 
3654 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_GET(value) (((value) & 0x000000ff) >> 0)
3655 
3656 #define ALT_SDR_CTL_REMAPPRIORITY_PRIORITYREMAP_SET(value) (((value) << 0) & 0x000000ff)
3657 
3658 #ifndef __ASSEMBLY__
3659 
3670 {
3671  uint32_t priorityremap : 8;
3672  uint32_t : 24;
3673 };
3674 
3677 #endif /* __ASSEMBLY__ */
3678 
3680 #define ALT_SDR_CTL_REMAPPRIORITY_OFST 0xe0
3681 
3711 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_LSB 0
3712 
3713 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_MSB 31
3714 
3715 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_WIDTH 32
3716 
3717 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET_MSK 0xffffffff
3718 
3719 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_CLR_MSK 0x00000000
3720 
3721 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_RESET 0x0
3722 
3723 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_GET(value) (((value) & 0xffffffff) >> 0)
3724 
3725 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_STATICWEIGHT_31_0_SET(value) (((value) << 0) & 0xffffffff)
3726 
3727 #ifndef __ASSEMBLY__
3728 
3739 {
3740  uint32_t staticweight_31_0 : 32;
3741 };
3742 
3745 #endif /* __ASSEMBLY__ */
3746 
3748 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST 0x0
3749 
3750 #define ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_0_4_OFST))
3751 
3775 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_LSB 0
3776 
3777 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_MSB 17
3778 
3779 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_WIDTH 18
3780 
3781 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET_MSK 0x0003ffff
3782 
3783 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_CLR_MSK 0xfffc0000
3784 
3785 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_RESET 0x0
3786 
3787 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_GET(value) (((value) & 0x0003ffff) >> 0)
3788 
3789 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_STATICWEIGHT_49_32_SET(value) (((value) << 0) & 0x0003ffff)
3790 
3802 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_LSB 18
3803 
3804 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_MSB 31
3805 
3806 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_WIDTH 14
3807 
3808 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET_MSK 0xfffc0000
3809 
3810 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_CLR_MSK 0x0003ffff
3811 
3812 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_RESET 0x0
3813 
3814 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_GET(value) (((value) & 0xfffc0000) >> 18)
3815 
3816 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_SUMOFWEIGHTS_13_0_SET(value) (((value) << 18) & 0xfffc0000)
3817 
3818 #ifndef __ASSEMBLY__
3819 
3830 {
3831  uint32_t staticweight_49_32 : 18;
3832  uint32_t sumofweights_13_0 : 14;
3833 };
3834 
3837 #endif /* __ASSEMBLY__ */
3838 
3840 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST 0x4
3841 
3842 #define ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_1_4_OFST))
3843 
3867 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_LSB 0
3868 
3869 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_MSB 31
3870 
3871 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_WIDTH 32
3872 
3873 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET_MSK 0xffffffff
3874 
3875 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_CLR_MSK 0x00000000
3876 
3877 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_RESET 0x0
3878 
3879 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_GET(value) (((value) & 0xffffffff) >> 0)
3880 
3881 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_SUMOFWEIGHTS_45_14_SET(value) (((value) << 0) & 0xffffffff)
3882 
3883 #ifndef __ASSEMBLY__
3884 
3895 {
3896  uint32_t sumofweights_45_14 : 32;
3897 };
3898 
3901 #endif /* __ASSEMBLY__ */
3902 
3904 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST 0x8
3905 
3906 #define ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_2_4_OFST))
3907 
3932 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_LSB 0
3933 
3934 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_MSB 17
3935 
3936 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_WIDTH 18
3937 
3938 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET_MSK 0x0003ffff
3939 
3940 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_CLR_MSK 0xfffc0000
3941 
3942 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_RESET 0x0
3943 
3944 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_GET(value) (((value) & 0x0003ffff) >> 0)
3945 
3946 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_SUMOFWEIGHTS_63_46_SET(value) (((value) << 0) & 0x0003ffff)
3947 
3948 #ifndef __ASSEMBLY__
3949 
3960 {
3961  uint32_t sumofweights_63_46 : 18;
3962  uint32_t : 14;
3963 };
3964 
3967 #endif /* __ASSEMBLY__ */
3968 
3970 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST 0xc
3971 
3972 #define ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SDR_CTL_MPWT_MPWEIGHT_3_4_OFST))
3973 
3974 #ifndef __ASSEMBLY__
3975 
3986 {
3991 };
3992 
3994 typedef volatile struct ALT_SDR_CTL_MPWT_s ALT_SDR_CTL_MPWT_t;
3997 {
3998  volatile uint32_t mpweight_0_4;
3999  volatile uint32_t mpweight_1_4;
4000  volatile uint32_t mpweight_2_4;
4001  volatile uint32_t mpweight_3_4;
4002 };
4003 
4006 #endif /* __ASSEMBLY__ */
4007 
4009 #ifndef __ASSEMBLY__
4010 
4021 {
4029  volatile uint32_t _pad_0x1c_0x2b[4];
4044  volatile uint32_t _pad_0x64_0x7b[6];
4047  volatile uint32_t _pad_0x84_0x8b[2];
4058  volatile uint32_t _pad_0xc0_0xdf[8];
4060  volatile uint32_t _pad_0xe4_0x1000[967];
4061 };
4062 
4064 typedef volatile struct ALT_SDR_CTL_s ALT_SDR_CTL_t;
4067 {
4068  volatile uint32_t ctrlcfg;
4069  volatile uint32_t dramtiming1;
4070  volatile uint32_t dramtiming2;
4071  volatile uint32_t dramtiming3;
4072  volatile uint32_t dramtiming4;
4073  volatile uint32_t lowpwrtiming;
4074  volatile uint32_t dramodt;
4075  volatile uint32_t _pad_0x1c_0x2b[4];
4076  volatile uint32_t dramaddrw;
4077  volatile uint32_t dramifwidth;
4078  volatile uint32_t dramdevwidth;
4079  volatile uint32_t dramsts;
4080  volatile uint32_t dramintr;
4081  volatile uint32_t sbecount;
4082  volatile uint32_t dbecount;
4083  volatile uint32_t erraddr;
4084  volatile uint32_t dropcount;
4085  volatile uint32_t dropaddr;
4086  volatile uint32_t lowpwreq;
4087  volatile uint32_t lowpwrack;
4088  volatile uint32_t staticcfg;
4089  volatile uint32_t ctrlwidth;
4090  volatile uint32_t _pad_0x64_0x7b[6];
4091  volatile uint32_t portcfg;
4092  volatile uint32_t fpgaportrst;
4093  volatile uint32_t _pad_0x84_0x8b[2];
4094  volatile uint32_t protportdefault;
4095  volatile uint32_t protruleaddr;
4096  volatile uint32_t protruleid;
4097  volatile uint32_t protruledata;
4098  volatile uint32_t protrulerdwr;
4099  volatile uint32_t qoslowpri;
4100  volatile uint32_t qoshighpri;
4101  volatile uint32_t qospriorityen;
4102  volatile uint32_t mppriority;
4104  volatile uint32_t _pad_0xc0_0xdf[8];
4105  volatile uint32_t remappriority;
4106  volatile uint32_t _pad_0xe4_0x1000[967];
4107 };
4108 
4110 typedef volatile struct ALT_SDR_CTL_raw_s ALT_SDR_CTL_raw_t;
4111 #endif /* __ASSEMBLY__ */
4112 
4114 #ifndef __ASSEMBLY__
4115 
4126 {
4127  volatile uint32_t _pad_0x0_0x4fff[5120];
4129  volatile uint32_t _pad_0x6000_0x20000[26624];
4130 };
4131 
4133 typedef volatile struct ALT_SDR_s ALT_SDR_t;
4136 {
4137  volatile uint32_t _pad_0x0_0x4fff[5120];
4139  volatile uint32_t _pad_0x6000_0x20000[26624];
4140 };
4141 
4143 typedef volatile struct ALT_SDR_raw_s ALT_SDR_raw_t;
4144 #endif /* __ASSEMBLY__ */
4145 
4147 #ifdef __cplusplus
4148 }
4149 #endif /* __cplusplus */
4150 #endif /* __ALTERA_ALT_SDR_H__ */
4151