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alt_noc_fw_ddr_mpu_f2sdr_ddr_scr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__
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#define __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_LSB 0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_MSB 0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_SET_MSK 0x00000001
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_LSB 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_MSB 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_SET_MSK 0x00000002
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_CLR_MSK 0xfffffffd
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_LSB 2
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_MSB 2
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_SET_MSK 0x00000004
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_CLR_MSK 0xfffffffb
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_LSB 3
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_MSB 3
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_SET_MSK 0x00000008
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_CLR_MSK 0xfffffff7
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_LSB 4
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_MSB 4
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_SET_MSK 0x00000010
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_CLR_MSK 0xffffffef
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_LSB 5
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_MSB 5
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_SET_MSK 0x00000020
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_CLR_MSK 0xffffffdf
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_LSB 6
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_MSB 6
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_SET_MSK 0x00000040
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_CLR_MSK 0xffffffbf
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_LSB 7
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_MSB 7
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_SET_MSK 0x00000080
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_CLR_MSK 0xffffff7f
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_LSB 8
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_MSB 8
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_SET_MSK 0x00000100
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_LSB 9
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_MSB 9
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_SET_MSK 0x00000200
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_CLR_MSK 0xfffffdff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_LSB 10
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_MSB 10
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_SET_MSK 0x00000400
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_CLR_MSK 0xfffffbff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_LSB 11
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_MSB 11
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_SET_MSK 0x00000800
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_LSB 12
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_MSB 12
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_SET_MSK 0x00001000
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_CLR_MSK 0xffffefff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_LSB 13
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_MSB 13
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_SET_MSK 0x00002000
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_CLR_MSK 0xffffdfff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_LSB 14
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_MSB 14
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_SET_MSK 0x00004000
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_CLR_MSK 0xffffbfff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_LSB 15
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_MSB 15
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_WIDTH 1
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_SET_MSK 0x00008000
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_CLR_MSK 0xffff7fff
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_RESET 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_s
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{
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uint32_t
mpuregion0enable
: 1;
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uint32_t
mpuregion1enable
: 1;
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uint32_t
mpuregion2enable
: 1;
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uint32_t
mpuregion3enable
: 1;
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uint32_t
fpga2sdram0region0enable
: 1;
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uint32_t
fpga2sdram0region1enable
: 1;
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uint32_t
fpga2sdram0region2enable
: 1;
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uint32_t
fpga2sdram0region3enable
: 1;
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uint32_t
fpga2sdram1region0enable
: 1;
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uint32_t
fpga2sdram1region1enable
: 1;
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uint32_t
fpga2sdram1region2enable
: 1;
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uint32_t
fpga2sdram1region3enable
: 1;
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uint32_t
fpga2sdram2region0enable
: 1;
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uint32_t
fpga2sdram2region1enable
: 1;
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uint32_t
fpga2sdram2region2enable
: 1;
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uint32_t
fpga2sdram2region3enable
: 1;
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uint32_t : 16;
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};
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typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_RESET 0x00000000
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_OFST 0x0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_LSB 0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_MSB 0
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#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_WIDTH 1
583
584
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET_MSK 0x00000001
585
586
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_CLR_MSK 0xfffffffe
587
588
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_RESET 0x0
589
590
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
591
592
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
593
607
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_LSB 1
608
609
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_MSB 1
610
611
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_WIDTH 1
612
613
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET_MSK 0x00000002
614
615
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_CLR_MSK 0xfffffffd
616
617
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_RESET 0x0
618
619
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
620
621
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
622
636
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_LSB 2
637
638
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_MSB 2
639
640
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_WIDTH 1
641
642
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET_MSK 0x00000004
643
644
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_CLR_MSK 0xfffffffb
645
646
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_RESET 0x0
647
648
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
649
650
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
651
665
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_LSB 3
666
667
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_MSB 3
668
669
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_WIDTH 1
670
671
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET_MSK 0x00000008
672
673
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_CLR_MSK 0xfffffff7
674
675
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_RESET 0x0
676
677
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
678
679
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
680
694
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_LSB 4
695
696
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_MSB 4
697
698
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_WIDTH 1
699
700
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET_MSK 0x00000010
701
702
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_CLR_MSK 0xffffffef
703
704
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_RESET 0x0
705
706
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
707
708
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
709
723
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_LSB 5
724
725
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_MSB 5
726
727
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_WIDTH 1
728
729
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET_MSK 0x00000020
730
731
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_CLR_MSK 0xffffffdf
732
733
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_RESET 0x0
734
735
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
736
737
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
738
752
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_LSB 6
753
754
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_MSB 6
755
756
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_WIDTH 1
757
758
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET_MSK 0x00000040
759
760
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_CLR_MSK 0xffffffbf
761
762
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_RESET 0x0
763
764
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
765
766
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
767
781
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_LSB 7
782
783
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_MSB 7
784
785
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_WIDTH 1
786
787
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET_MSK 0x00000080
788
789
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_CLR_MSK 0xffffff7f
790
791
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_RESET 0x0
792
793
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
794
795
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
796
810
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_LSB 8
811
812
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_MSB 8
813
814
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_WIDTH 1
815
816
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET_MSK 0x00000100
817
818
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_CLR_MSK 0xfffffeff
819
820
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_RESET 0x0
821
822
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
823
824
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
825
839
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_LSB 9
840
841
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_MSB 9
842
843
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_WIDTH 1
844
845
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET_MSK 0x00000200
846
847
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_CLR_MSK 0xfffffdff
848
849
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_RESET 0x0
850
851
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
852
853
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
854
868
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_LSB 10
869
870
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_MSB 10
871
872
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_WIDTH 1
873
874
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET_MSK 0x00000400
875
876
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_CLR_MSK 0xfffffbff
877
878
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_RESET 0x0
879
880
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
881
882
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
883
897
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_LSB 11
898
899
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_MSB 11
900
901
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_WIDTH 1
902
903
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET_MSK 0x00000800
904
905
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
906
907
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_RESET 0x0
908
909
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
910
911
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
912
926
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_LSB 12
927
928
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_MSB 12
929
930
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_WIDTH 1
931
932
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET_MSK 0x00001000
933
934
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_CLR_MSK 0xffffefff
935
936
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_RESET 0x0
937
938
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
939
940
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
941
955
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_LSB 13
956
957
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_MSB 13
958
959
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_WIDTH 1
960
961
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET_MSK 0x00002000
962
963
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_CLR_MSK 0xffffdfff
964
965
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_RESET 0x0
966
967
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
968
969
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
970
984
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_LSB 14
985
986
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_MSB 14
987
988
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_WIDTH 1
989
990
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET_MSK 0x00004000
991
992
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_CLR_MSK 0xffffbfff
993
994
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_RESET 0x0
995
996
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
997
998
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
999
1013
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_LSB 15
1014
1015
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_MSB 15
1016
1017
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_WIDTH 1
1018
1019
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET_MSK 0x00008000
1020
1021
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_CLR_MSK 0xffff7fff
1022
1023
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_RESET 0x0
1024
1025
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
1026
1027
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
1028
1029
#ifndef __ASSEMBLY__
1030
1040
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s
1041
{
1042
uint32_t
mpuregion0enable
: 1;
1043
uint32_t
mpuregion1enable
: 1;
1044
uint32_t
mpuregion2enable
: 1;
1045
uint32_t
mpuregion3enable
: 1;
1046
uint32_t
fpga2sdram0region0enable
: 1;
1047
uint32_t
fpga2sdram0region1enable
: 1;
1048
uint32_t
fpga2sdram0region2enable
: 1;
1049
uint32_t
fpga2sdram0region3enable
: 1;
1050
uint32_t
fpga2sdram1region0enable
: 1;
1051
uint32_t
fpga2sdram1region1enable
: 1;
1052
uint32_t
fpga2sdram1region2enable
: 1;
1053
uint32_t
fpga2sdram1region3enable
: 1;
1054
uint32_t
fpga2sdram2region0enable
: 1;
1055
uint32_t
fpga2sdram2region1enable
: 1;
1056
uint32_t
fpga2sdram2region2enable
: 1;
1057
uint32_t
fpga2sdram2region3enable
: 1;
1058
uint32_t : 16;
1059
};
1060
1062
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_t
;
1063
#endif
/* __ASSEMBLY__ */
1064
1066
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_RESET 0x00000000
1067
1068
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_OFST 0x4
1069
1111
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_LSB 0
1112
1113
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_MSB 0
1114
1115
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_WIDTH 1
1116
1117
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_SET_MSK 0x00000001
1118
1119
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_CLR_MSK 0xfffffffe
1120
1121
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_RESET 0x0
1122
1123
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0)
1124
1125
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001)
1126
1140
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_LSB 1
1141
1142
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_MSB 1
1143
1144
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_WIDTH 1
1145
1146
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_SET_MSK 0x00000002
1147
1148
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_CLR_MSK 0xfffffffd
1149
1150
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_RESET 0x0
1151
1152
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1)
1153
1154
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002)
1155
1169
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_LSB 2
1170
1171
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_MSB 2
1172
1173
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_WIDTH 1
1174
1175
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_SET_MSK 0x00000004
1176
1177
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_CLR_MSK 0xfffffffb
1178
1179
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_RESET 0x0
1180
1181
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2)
1182
1183
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004)
1184
1198
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_LSB 3
1199
1200
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_MSB 3
1201
1202
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_WIDTH 1
1203
1204
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_SET_MSK 0x00000008
1205
1206
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_CLR_MSK 0xfffffff7
1207
1208
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_RESET 0x0
1209
1210
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3)
1211
1212
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008)
1213
1227
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_LSB 4
1228
1229
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_MSB 4
1230
1231
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_WIDTH 1
1232
1233
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_SET_MSK 0x00000010
1234
1235
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_CLR_MSK 0xffffffef
1236
1237
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_RESET 0x0
1238
1239
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4)
1240
1241
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010)
1242
1256
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_LSB 5
1257
1258
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_MSB 5
1259
1260
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_WIDTH 1
1261
1262
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_SET_MSK 0x00000020
1263
1264
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_CLR_MSK 0xffffffdf
1265
1266
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_RESET 0x0
1267
1268
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5)
1269
1270
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020)
1271
1285
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_LSB 6
1286
1287
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_MSB 6
1288
1289
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_WIDTH 1
1290
1291
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_SET_MSK 0x00000040
1292
1293
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_CLR_MSK 0xffffffbf
1294
1295
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_RESET 0x0
1296
1297
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6)
1298
1299
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040)
1300
1314
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_LSB 7
1315
1316
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_MSB 7
1317
1318
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_WIDTH 1
1319
1320
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_SET_MSK 0x00000080
1321
1322
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_CLR_MSK 0xffffff7f
1323
1324
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_RESET 0x0
1325
1326
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7)
1327
1328
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080)
1329
1343
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_LSB 8
1344
1345
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_MSB 8
1346
1347
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_WIDTH 1
1348
1349
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_SET_MSK 0x00000100
1350
1351
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_CLR_MSK 0xfffffeff
1352
1353
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_RESET 0x0
1354
1355
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8)
1356
1357
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100)
1358
1372
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_LSB 9
1373
1374
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_MSB 9
1375
1376
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_WIDTH 1
1377
1378
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_SET_MSK 0x00000200
1379
1380
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_CLR_MSK 0xfffffdff
1381
1382
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_RESET 0x0
1383
1384
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9)
1385
1386
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200)
1387
1401
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_LSB 10
1402
1403
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_MSB 10
1404
1405
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_WIDTH 1
1406
1407
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_SET_MSK 0x00000400
1408
1409
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_CLR_MSK 0xfffffbff
1410
1411
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_RESET 0x0
1412
1413
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10)
1414
1415
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400)
1416
1430
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_LSB 11
1431
1432
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_MSB 11
1433
1434
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_WIDTH 1
1435
1436
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_SET_MSK 0x00000800
1437
1438
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_CLR_MSK 0xfffff7ff
1439
1440
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_RESET 0x0
1441
1442
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11)
1443
1444
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800)
1445
1459
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_LSB 12
1460
1461
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_MSB 12
1462
1463
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_WIDTH 1
1464
1465
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_SET_MSK 0x00001000
1466
1467
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_CLR_MSK 0xffffefff
1468
1469
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_RESET 0x0
1470
1471
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12)
1472
1473
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000)
1474
1488
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_LSB 13
1489
1490
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_MSB 13
1491
1492
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_WIDTH 1
1493
1494
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_SET_MSK 0x00002000
1495
1496
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_CLR_MSK 0xffffdfff
1497
1498
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_RESET 0x0
1499
1500
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13)
1501
1502
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000)
1503
1517
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_LSB 14
1518
1519
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_MSB 14
1520
1521
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_WIDTH 1
1522
1523
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_SET_MSK 0x00004000
1524
1525
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_CLR_MSK 0xffffbfff
1526
1527
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_RESET 0x0
1528
1529
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14)
1530
1531
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000)
1532
1546
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_LSB 15
1547
1548
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_MSB 15
1549
1550
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_WIDTH 1
1551
1552
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_SET_MSK 0x00008000
1553
1554
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_CLR_MSK 0xffff7fff
1555
1556
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_RESET 0x0
1557
1558
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15)
1559
1560
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000)
1561
1562
#ifndef __ASSEMBLY__
1563
1573
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_s
1574
{
1575
uint32_t
mpuregion0enable
: 1;
1576
uint32_t
mpuregion1enable
: 1;
1577
uint32_t
mpuregion2enable
: 1;
1578
uint32_t
mpuregion3enable
: 1;
1579
uint32_t
fpga2sdram0region0enable
: 1;
1580
uint32_t
fpga2sdram0region1enable
: 1;
1581
uint32_t
fpga2sdram0region2enable
: 1;
1582
uint32_t
fpga2sdram0region3enable
: 1;
1583
uint32_t
fpga2sdram1region0enable
: 1;
1584
uint32_t
fpga2sdram1region1enable
: 1;
1585
uint32_t
fpga2sdram1region2enable
: 1;
1586
uint32_t
fpga2sdram1region3enable
: 1;
1587
uint32_t
fpga2sdram2region0enable
: 1;
1588
uint32_t
fpga2sdram2region1enable
: 1;
1589
uint32_t
fpga2sdram2region2enable
: 1;
1590
uint32_t
fpga2sdram2region3enable
: 1;
1591
uint32_t : 16;
1592
};
1593
1595
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_t
;
1596
#endif
/* __ASSEMBLY__ */
1597
1599
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_RESET 0x00000000
1600
1601
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_OFST 0x8
1602
1626
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_LSB 0
1627
1628
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_MSB 15
1629
1630
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_WIDTH 16
1631
1632
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_SET_MSK 0x0000ffff
1633
1634
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_CLR_MSK 0xffff0000
1635
1636
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_RESET 0x0
1637
1638
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1639
1640
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1641
1652
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_LSB 16
1653
1654
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_MSB 31
1655
1656
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_WIDTH 16
1657
1658
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_SET_MSK 0xffff0000
1659
1660
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_CLR_MSK 0x0000ffff
1661
1662
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_RESET 0x0
1663
1664
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1665
1666
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1667
1668
#ifndef __ASSEMBLY__
1669
1679
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_s
1680
{
1681
uint32_t
base
: 16;
1682
uint32_t
limit
: 16;
1683
};
1684
1686
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_t
;
1687
#endif
/* __ASSEMBLY__ */
1688
1690
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_RESET 0x00000000
1691
1692
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_OFST 0x10
1693
1717
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_LSB 0
1718
1719
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_MSB 15
1720
1721
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_WIDTH 16
1722
1723
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_SET_MSK 0x0000ffff
1724
1725
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_CLR_MSK 0xffff0000
1726
1727
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_RESET 0x0
1728
1729
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1730
1731
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1732
1743
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_LSB 16
1744
1745
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_MSB 31
1746
1747
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_WIDTH 16
1748
1749
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_SET_MSK 0xffff0000
1750
1751
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_CLR_MSK 0x0000ffff
1752
1753
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_RESET 0x0
1754
1755
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1756
1757
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1758
1759
#ifndef __ASSEMBLY__
1760
1770
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_s
1771
{
1772
uint32_t
base
: 16;
1773
uint32_t
limit
: 16;
1774
};
1775
1777
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_t
;
1778
#endif
/* __ASSEMBLY__ */
1779
1781
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_RESET 0x00000000
1782
1783
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_OFST 0x14
1784
1808
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_LSB 0
1809
1810
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_MSB 15
1811
1812
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_WIDTH 16
1813
1814
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_SET_MSK 0x0000ffff
1815
1816
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_CLR_MSK 0xffff0000
1817
1818
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_RESET 0x0
1819
1820
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1821
1822
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1823
1834
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_LSB 16
1835
1836
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_MSB 31
1837
1838
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_WIDTH 16
1839
1840
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_SET_MSK 0xffff0000
1841
1842
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_CLR_MSK 0x0000ffff
1843
1844
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_RESET 0x0
1845
1846
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1847
1848
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1849
1850
#ifndef __ASSEMBLY__
1851
1861
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_s
1862
{
1863
uint32_t
base
: 16;
1864
uint32_t
limit
: 16;
1865
};
1866
1868
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_t
;
1869
#endif
/* __ASSEMBLY__ */
1870
1872
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_RESET 0x00000000
1873
1874
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_OFST 0x18
1875
1899
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_LSB 0
1900
1901
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_MSB 15
1902
1903
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_WIDTH 16
1904
1905
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_SET_MSK 0x0000ffff
1906
1907
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_CLR_MSK 0xffff0000
1908
1909
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_RESET 0x0
1910
1911
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
1912
1913
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
1914
1925
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_LSB 16
1926
1927
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_MSB 31
1928
1929
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_WIDTH 16
1930
1931
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_SET_MSK 0xffff0000
1932
1933
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_CLR_MSK 0x0000ffff
1934
1935
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_RESET 0x0
1936
1937
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
1938
1939
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
1940
1941
#ifndef __ASSEMBLY__
1942
1952
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_s
1953
{
1954
uint32_t
base
: 16;
1955
uint32_t
limit
: 16;
1956
};
1957
1959
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_t
;
1960
#endif
/* __ASSEMBLY__ */
1961
1963
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_RESET 0x00000000
1964
1965
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_OFST 0x1c
1966
1990
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_LSB 0
1991
1992
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_MSB 15
1993
1994
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_WIDTH 16
1995
1996
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_SET_MSK 0x0000ffff
1997
1998
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_CLR_MSK 0xffff0000
1999
2000
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_RESET 0x0
2001
2002
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2003
2004
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2005
2016
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_LSB 16
2017
2018
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_MSB 31
2019
2020
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_WIDTH 16
2021
2022
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_SET_MSK 0xffff0000
2023
2024
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2025
2026
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_RESET 0x0
2027
2028
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2029
2030
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2031
2032
#ifndef __ASSEMBLY__
2033
2043
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_s
2044
{
2045
uint32_t
base
: 16;
2046
uint32_t
limit
: 16;
2047
};
2048
2050
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_t
;
2051
#endif
/* __ASSEMBLY__ */
2052
2054
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_RESET 0x00000000
2055
2056
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_OFST 0x20
2057
2081
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_LSB 0
2082
2083
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_MSB 15
2084
2085
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_WIDTH 16
2086
2087
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_SET_MSK 0x0000ffff
2088
2089
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_CLR_MSK 0xffff0000
2090
2091
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_RESET 0x0
2092
2093
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2094
2095
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2096
2107
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_LSB 16
2108
2109
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_MSB 31
2110
2111
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_WIDTH 16
2112
2113
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_SET_MSK 0xffff0000
2114
2115
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2116
2117
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_RESET 0x0
2118
2119
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2120
2121
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2122
2123
#ifndef __ASSEMBLY__
2124
2134
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_s
2135
{
2136
uint32_t
base
: 16;
2137
uint32_t
limit
: 16;
2138
};
2139
2141
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_t
;
2142
#endif
/* __ASSEMBLY__ */
2143
2145
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_RESET 0x00000000
2146
2147
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_OFST 0x24
2148
2172
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_LSB 0
2173
2174
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_MSB 15
2175
2176
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_WIDTH 16
2177
2178
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_SET_MSK 0x0000ffff
2179
2180
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_CLR_MSK 0xffff0000
2181
2182
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_RESET 0x0
2183
2184
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2185
2186
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2187
2198
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_LSB 16
2199
2200
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_MSB 31
2201
2202
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_WIDTH 16
2203
2204
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_SET_MSK 0xffff0000
2205
2206
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2207
2208
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_RESET 0x0
2209
2210
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2211
2212
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2213
2214
#ifndef __ASSEMBLY__
2215
2225
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_s
2226
{
2227
uint32_t
base
: 16;
2228
uint32_t
limit
: 16;
2229
};
2230
2232
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_t
;
2233
#endif
/* __ASSEMBLY__ */
2234
2236
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_RESET 0x00000000
2237
2238
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_OFST 0x28
2239
2263
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_LSB 0
2264
2265
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_MSB 15
2266
2267
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_WIDTH 16
2268
2269
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_SET_MSK 0x0000ffff
2270
2271
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_CLR_MSK 0xffff0000
2272
2273
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_RESET 0x0
2274
2275
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2276
2277
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2278
2289
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_LSB 16
2290
2291
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_MSB 31
2292
2293
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_WIDTH 16
2294
2295
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_SET_MSK 0xffff0000
2296
2297
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
2298
2299
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_RESET 0x0
2300
2301
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2302
2303
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2304
2305
#ifndef __ASSEMBLY__
2306
2316
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_s
2317
{
2318
uint32_t
base
: 16;
2319
uint32_t
limit
: 16;
2320
};
2321
2323
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_t
;
2324
#endif
/* __ASSEMBLY__ */
2325
2327
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_RESET 0x00000000
2328
2329
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_OFST 0x2c
2330
2354
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_LSB 0
2355
2356
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_MSB 15
2357
2358
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_WIDTH 16
2359
2360
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_SET_MSK 0x0000ffff
2361
2362
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_CLR_MSK 0xffff0000
2363
2364
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_RESET 0x0
2365
2366
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2367
2368
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2369
2380
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_LSB 16
2381
2382
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_MSB 31
2383
2384
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_WIDTH 16
2385
2386
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_SET_MSK 0xffff0000
2387
2388
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2389
2390
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_RESET 0x0
2391
2392
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2393
2394
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2395
2396
#ifndef __ASSEMBLY__
2397
2407
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_s
2408
{
2409
uint32_t
base
: 16;
2410
uint32_t
limit
: 16;
2411
};
2412
2414
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_t
;
2415
#endif
/* __ASSEMBLY__ */
2416
2418
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_RESET 0x00000000
2419
2420
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_OFST 0x30
2421
2445
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_LSB 0
2446
2447
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_MSB 15
2448
2449
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_WIDTH 16
2450
2451
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_SET_MSK 0x0000ffff
2452
2453
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_CLR_MSK 0xffff0000
2454
2455
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_RESET 0x0
2456
2457
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2458
2459
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2460
2471
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_LSB 16
2472
2473
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_MSB 31
2474
2475
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_WIDTH 16
2476
2477
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_SET_MSK 0xffff0000
2478
2479
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2480
2481
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_RESET 0x0
2482
2483
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2484
2485
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2486
2487
#ifndef __ASSEMBLY__
2488
2498
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_s
2499
{
2500
uint32_t
base
: 16;
2501
uint32_t
limit
: 16;
2502
};
2503
2505
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_t
;
2506
#endif
/* __ASSEMBLY__ */
2507
2509
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_RESET 0x00000000
2510
2511
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_OFST 0x34
2512
2536
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_LSB 0
2537
2538
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_MSB 15
2539
2540
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_WIDTH 16
2541
2542
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_SET_MSK 0x0000ffff
2543
2544
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_CLR_MSK 0xffff0000
2545
2546
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_RESET 0x0
2547
2548
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2549
2550
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2551
2562
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_LSB 16
2563
2564
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_MSB 31
2565
2566
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_WIDTH 16
2567
2568
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_SET_MSK 0xffff0000
2569
2570
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2571
2572
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_RESET 0x0
2573
2574
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2575
2576
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2577
2578
#ifndef __ASSEMBLY__
2579
2589
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_s
2590
{
2591
uint32_t
base
: 16;
2592
uint32_t
limit
: 16;
2593
};
2594
2596
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_t
;
2597
#endif
/* __ASSEMBLY__ */
2598
2600
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_RESET 0x00000000
2601
2602
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_OFST 0x38
2603
2627
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_LSB 0
2628
2629
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_MSB 15
2630
2631
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_WIDTH 16
2632
2633
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_SET_MSK 0x0000ffff
2634
2635
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_CLR_MSK 0xffff0000
2636
2637
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_RESET 0x0
2638
2639
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2640
2641
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2642
2653
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_LSB 16
2654
2655
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_MSB 31
2656
2657
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_WIDTH 16
2658
2659
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_SET_MSK 0xffff0000
2660
2661
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
2662
2663
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_RESET 0x0
2664
2665
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2666
2667
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2668
2669
#ifndef __ASSEMBLY__
2670
2680
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_s
2681
{
2682
uint32_t
base
: 16;
2683
uint32_t
limit
: 16;
2684
};
2685
2687
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_t
;
2688
#endif
/* __ASSEMBLY__ */
2689
2691
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_RESET 0x00000000
2692
2693
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_OFST 0x3c
2694
2718
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_LSB 0
2719
2720
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_MSB 15
2721
2722
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_WIDTH 16
2723
2724
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_SET_MSK 0x0000ffff
2725
2726
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_CLR_MSK 0xffff0000
2727
2728
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_RESET 0x0
2729
2730
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2731
2732
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2733
2744
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_LSB 16
2745
2746
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_MSB 31
2747
2748
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_WIDTH 16
2749
2750
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_SET_MSK 0xffff0000
2751
2752
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_CLR_MSK 0x0000ffff
2753
2754
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_RESET 0x0
2755
2756
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2757
2758
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2759
2760
#ifndef __ASSEMBLY__
2761
2771
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_s
2772
{
2773
uint32_t
base
: 16;
2774
uint32_t
limit
: 16;
2775
};
2776
2778
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_t
;
2779
#endif
/* __ASSEMBLY__ */
2780
2782
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_RESET 0x00000000
2783
2784
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_OFST 0x40
2785
2809
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_LSB 0
2810
2811
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_MSB 15
2812
2813
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_WIDTH 16
2814
2815
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_SET_MSK 0x0000ffff
2816
2817
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_CLR_MSK 0xffff0000
2818
2819
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_RESET 0x0
2820
2821
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2822
2823
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2824
2835
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_LSB 16
2836
2837
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_MSB 31
2838
2839
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_WIDTH 16
2840
2841
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_SET_MSK 0xffff0000
2842
2843
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_CLR_MSK 0x0000ffff
2844
2845
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_RESET 0x0
2846
2847
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2848
2849
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2850
2851
#ifndef __ASSEMBLY__
2852
2862
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_s
2863
{
2864
uint32_t
base
: 16;
2865
uint32_t
limit
: 16;
2866
};
2867
2869
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_t
;
2870
#endif
/* __ASSEMBLY__ */
2871
2873
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_RESET 0x00000000
2874
2875
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_OFST 0x44
2876
2900
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_LSB 0
2901
2902
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_MSB 15
2903
2904
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_WIDTH 16
2905
2906
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_SET_MSK 0x0000ffff
2907
2908
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_CLR_MSK 0xffff0000
2909
2910
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_RESET 0x0
2911
2912
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
2913
2914
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
2915
2926
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_LSB 16
2927
2928
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_MSB 31
2929
2930
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_WIDTH 16
2931
2932
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_SET_MSK 0xffff0000
2933
2934
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_CLR_MSK 0x0000ffff
2935
2936
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_RESET 0x0
2937
2938
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
2939
2940
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
2941
2942
#ifndef __ASSEMBLY__
2943
2953
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_s
2954
{
2955
uint32_t
base
: 16;
2956
uint32_t
limit
: 16;
2957
};
2958
2960
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_t
;
2961
#endif
/* __ASSEMBLY__ */
2962
2964
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_RESET 0x00000000
2965
2966
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_OFST 0x48
2967
2991
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_LSB 0
2992
2993
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_MSB 15
2994
2995
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_WIDTH 16
2996
2997
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_SET_MSK 0x0000ffff
2998
2999
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_CLR_MSK 0xffff0000
3000
3001
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_RESET 0x0
3002
3003
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0)
3004
3005
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff)
3006
3017
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_LSB 16
3018
3019
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_MSB 31
3020
3021
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_WIDTH 16
3022
3023
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_SET_MSK 0xffff0000
3024
3025
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_CLR_MSK 0x0000ffff
3026
3027
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_RESET 0x0
3028
3029
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16)
3030
3031
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000)
3032
3033
#ifndef __ASSEMBLY__
3034
3044
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_s
3045
{
3046
uint32_t
base
: 16;
3047
uint32_t
limit
: 16;
3048
};
3049
3051
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_t
;
3052
#endif
/* __ASSEMBLY__ */
3053
3055
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_RESET 0x00000000
3056
3057
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_OFST 0x4c
3058
3059
#ifndef __ASSEMBLY__
3060
3070
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_s
3071
{
3072
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_t
enable
;
3073
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_t
enable_set
;
3074
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_CLR_t
enable_clear
;
3075
volatile
uint32_t
_pad_0xc_0xf
;
3076
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG0ADDR_t
mpuregion0addr
;
3077
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG1ADDR_t
mpuregion1addr
;
3078
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG2ADDR_t
mpuregion2addr
;
3079
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_MPUREG3ADDR_t
mpuregion3addr
;
3080
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG0ADDR_t
fpga2sdram0region0addr
;
3081
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG1ADDR_t
fpga2sdram0region1addr
;
3082
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG2ADDR_t
fpga2sdram0region2addr
;
3083
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR0REG3ADDR_t
fpga2sdram0region3addr
;
3084
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG0ADDR_t
fpga2sdram1region0addr
;
3085
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG1ADDR_t
fpga2sdram1region1addr
;
3086
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG2ADDR_t
fpga2sdram1region2addr
;
3087
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR1REG3ADDR_t
fpga2sdram1region3addr
;
3088
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG0ADDR_t
fpga2sdram2region0addr
;
3089
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG1ADDR_t
fpga2sdram2region1addr
;
3090
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG2ADDR_t
fpga2sdram2region2addr
;
3091
volatile
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_F2SDR2REG3ADDR_t
fpga2sdram2region3addr
;
3092
volatile
uint32_t
_pad_0x50_0x100
[44];
3093
};
3094
3096
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_t
;
3098
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_s
3099
{
3100
volatile
uint32_t
enable
;
3101
volatile
uint32_t
enable_set
;
3102
volatile
uint32_t
enable_clear
;
3103
volatile
uint32_t
_pad_0xc_0xf
;
3104
volatile
uint32_t
mpuregion0addr
;
3105
volatile
uint32_t
mpuregion1addr
;
3106
volatile
uint32_t
mpuregion2addr
;
3107
volatile
uint32_t
mpuregion3addr
;
3108
volatile
uint32_t
fpga2sdram0region0addr
;
3109
volatile
uint32_t
fpga2sdram0region1addr
;
3110
volatile
uint32_t
fpga2sdram0region2addr
;
3111
volatile
uint32_t
fpga2sdram0region3addr
;
3112
volatile
uint32_t
fpga2sdram1region0addr
;
3113
volatile
uint32_t
fpga2sdram1region1addr
;
3114
volatile
uint32_t
fpga2sdram1region2addr
;
3115
volatile
uint32_t
fpga2sdram1region3addr
;
3116
volatile
uint32_t
fpga2sdram2region0addr
;
3117
volatile
uint32_t
fpga2sdram2region1addr
;
3118
volatile
uint32_t
fpga2sdram2region2addr
;
3119
volatile
uint32_t
fpga2sdram2region3addr
;
3120
volatile
uint32_t
_pad_0x50_0x100
[44];
3121
};
3122
3124
typedef
volatile
struct
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_s
ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_raw_t
;
3125
#endif
/* __ASSEMBLY__ */
3126
3128
#ifdef __cplusplus
3129
}
3130
#endif
/* __cplusplus */
3131
#endif
/* __ALT_SOCAL_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_H__ */
3132
include
soc_a10
socal
alt_noc_fw_ddr_mpu_f2sdr_ddr_scr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
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