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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Registers used by the DMA Controller. All fields are reset by a cold or warm reset.
These register bits should be updated during system initialization prior to removing the DMA controller from reset. They may not be changed dynamically during DMA operation.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Channel Select I2C |
[3:1] | ??? | 0x0 | UNDEFINED |
[4] | RW | 0x0 | Channel Select I2C |
[7:5] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x1 | Channel Select Security Manager |
[15:9] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | Manager Thread Security |
[23:17] | ??? | 0x0 | UNDEFINED |
[31:24] | RW | 0x0 | IRQ Security |
Field : Channel Select I2C - chansel_0 | |
Select between FPGA interface 6 and I2C4_Tx to be mapped to DMA peripheral request index 6 Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA | 0x0 | ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA 0x0 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX 0x1 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_LSB 0 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_MSB 0 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_WIDTH 1 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_SET_MSK 0x00000001 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_CLR_MSK 0xfffffffe |
#define | ALT_SYSMGR_DMA_CHANSEL_0_RESET 0x0 |
#define | ALT_SYSMGR_DMA_CHANSEL_0_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SYSMGR_DMA_CHANSEL_0_SET(value) (((value) << 0) & 0x00000001) |
Field : Channel Select I2C - chansel_1 | |
select between FPGA interface 7 and I2C4_Rx to be mapped to DMA peripheral request index 7 Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA | 0x0 | ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA 0x0 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX 0x1 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_LSB 4 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_MSB 4 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_WIDTH 1 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_SET_MSK 0x00000010 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_CLR_MSK 0xffffffef |
#define | ALT_SYSMGR_DMA_CHANSEL_1_RESET 0x0 |
#define | ALT_SYSMGR_DMA_CHANSEL_1_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_SYSMGR_DMA_CHANSEL_1_SET(value) (((value) << 4) & 0x00000010) |
Field : Channel Select Security Manager - chansel_2 | |
select between FPGA interface 5 and Security Manager to be mapped to DMA peripheral request index 5 Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA | 0x0 | ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA 0x0 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR 0x1 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_LSB 8 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_MSB 8 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_WIDTH 1 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_SET_MSK 0x00000100 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_CLR_MSK 0xfffffeff |
#define | ALT_SYSMGR_DMA_CHANSEL_2_RESET 0x1 |
#define | ALT_SYSMGR_DMA_CHANSEL_2_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_SYSMGR_DMA_CHANSEL_2_SET(value) (((value) << 8) & 0x00000100) |
Field : Manager Thread Security - mgr_ns | |
Specifies the security state of the DMA manager thread. 0 = assigns DMA manager to the Secure state. 1 = assigns DMA manager to the Non-secure state. Sampled by the DMA controller when it exits from reset. Field Access Macros: | |
#define | ALT_SYSMGR_DMA_MGR_NS_LSB 16 |
#define | ALT_SYSMGR_DMA_MGR_NS_MSB 16 |
#define | ALT_SYSMGR_DMA_MGR_NS_WIDTH 1 |
#define | ALT_SYSMGR_DMA_MGR_NS_SET_MSK 0x00010000 |
#define | ALT_SYSMGR_DMA_MGR_NS_CLR_MSK 0xfffeffff |
#define | ALT_SYSMGR_DMA_MGR_NS_RESET 0x0 |
#define | ALT_SYSMGR_DMA_MGR_NS_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_SYSMGR_DMA_MGR_NS_SET(value) (((value) << 16) & 0x00010000) |
Field : IRQ Security - irq_ns | |
Specifies the security state of an event-interrupt resource. If bit index [x] is 0, the DMAC assigns event<x> or irq[x] to the Secure state. If bit index [x] is 1, the DMAC assigns event<x> or irq[x] to the Non-secure state. Field Access Macros: | |
#define | ALT_SYSMGR_DMA_IRQ_NS_LSB 24 |
#define | ALT_SYSMGR_DMA_IRQ_NS_MSB 31 |
#define | ALT_SYSMGR_DMA_IRQ_NS_WIDTH 8 |
#define | ALT_SYSMGR_DMA_IRQ_NS_SET_MSK 0xff000000 |
#define | ALT_SYSMGR_DMA_IRQ_NS_CLR_MSK 0x00ffffff |
#define | ALT_SYSMGR_DMA_IRQ_NS_RESET 0x0 |
#define | ALT_SYSMGR_DMA_IRQ_NS_GET(value) (((value) & 0xff000000) >> 24) |
#define | ALT_SYSMGR_DMA_IRQ_NS_SET(value) (((value) << 24) & 0xff000000) |
Data Structures | |
struct | ALT_SYSMGR_DMA_s |
Macros | |
#define | ALT_SYSMGR_DMA_RESET 0x00000100 |
#define | ALT_SYSMGR_DMA_OFST 0x20 |
Typedefs | |
typedef struct ALT_SYSMGR_DMA_s | ALT_SYSMGR_DMA_t |
struct ALT_SYSMGR_DMA_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_DMA.
Data Fields | ||
---|---|---|
uint32_t | chansel_0: 1 | Channel Select I2C |
uint32_t | __pad0__: 3 | UNDEFINED |
uint32_t | chansel_1: 1 | Channel Select I2C |
uint32_t | __pad1__: 3 | UNDEFINED |
uint32_t | chansel_2: 1 | Channel Select Security Manager |
uint32_t | __pad2__: 7 | UNDEFINED |
uint32_t | mgr_ns: 1 | Manager Thread Security |
uint32_t | __pad3__: 7 | UNDEFINED |
uint32_t | irq_ns: 8 | IRQ Security |
#define ALT_SYSMGR_DMA_CHANSEL_0_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_0
#define ALT_SYSMGR_DMA_CHANSEL_0_E_I2C4_TX 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_0
#define ALT_SYSMGR_DMA_CHANSEL_0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CHANSEL_0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CHANSEL_0_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CHANSEL_0_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_DMA_CHANSEL_0 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_0 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_0_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CHANSEL_0 register field.
#define ALT_SYSMGR_DMA_CHANSEL_0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_DMA_CHANSEL_0 field value from a register.
#define ALT_SYSMGR_DMA_CHANSEL_0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_DMA_CHANSEL_0 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CHANSEL_1_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_1
#define ALT_SYSMGR_DMA_CHANSEL_1_E_I2C4_RX 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_1
#define ALT_SYSMGR_DMA_CHANSEL_1_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CHANSEL_1_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CHANSEL_1_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CHANSEL_1_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_DMA_CHANSEL_1 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_1_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_1 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_1_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_CHANSEL_1 register field.
#define ALT_SYSMGR_DMA_CHANSEL_1_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_DMA_CHANSEL_1 field value from a register.
#define ALT_SYSMGR_DMA_CHANSEL_1_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_DMA_CHANSEL_1 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_CHANSEL_2_E_FPGA 0x0 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_2
#define ALT_SYSMGR_DMA_CHANSEL_2_E_SECMGR 0x1 |
Enumerated value for register field ALT_SYSMGR_DMA_CHANSEL_2
#define ALT_SYSMGR_DMA_CHANSEL_2_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CHANSEL_2_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CHANSEL_2_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CHANSEL_2_SET_MSK 0x00000100 |
The mask used to set the ALT_SYSMGR_DMA_CHANSEL_2 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_2_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SYSMGR_DMA_CHANSEL_2 register field value.
#define ALT_SYSMGR_DMA_CHANSEL_2_RESET 0x1 |
The reset value of the ALT_SYSMGR_DMA_CHANSEL_2 register field.
#define ALT_SYSMGR_DMA_CHANSEL_2_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SYSMGR_DMA_CHANSEL_2 field value from a register.
#define ALT_SYSMGR_DMA_CHANSEL_2_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SYSMGR_DMA_CHANSEL_2 register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_MGR_NS_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_MGR_NS register field.
#define ALT_SYSMGR_DMA_MGR_NS_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_MGR_NS register field.
#define ALT_SYSMGR_DMA_MGR_NS_WIDTH 1 |
The width in bits of the ALT_SYSMGR_DMA_MGR_NS register field.
#define ALT_SYSMGR_DMA_MGR_NS_SET_MSK 0x00010000 |
The mask used to set the ALT_SYSMGR_DMA_MGR_NS register field value.
#define ALT_SYSMGR_DMA_MGR_NS_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_SYSMGR_DMA_MGR_NS register field value.
#define ALT_SYSMGR_DMA_MGR_NS_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_MGR_NS register field.
#define ALT_SYSMGR_DMA_MGR_NS_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_SYSMGR_DMA_MGR_NS field value from a register.
#define ALT_SYSMGR_DMA_MGR_NS_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_SYSMGR_DMA_MGR_NS register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_IRQ_NS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_DMA_IRQ_NS register field.
#define ALT_SYSMGR_DMA_IRQ_NS_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_DMA_IRQ_NS register field.
#define ALT_SYSMGR_DMA_IRQ_NS_WIDTH 8 |
The width in bits of the ALT_SYSMGR_DMA_IRQ_NS register field.
#define ALT_SYSMGR_DMA_IRQ_NS_SET_MSK 0xff000000 |
The mask used to set the ALT_SYSMGR_DMA_IRQ_NS register field value.
#define ALT_SYSMGR_DMA_IRQ_NS_CLR_MSK 0x00ffffff |
The mask used to clear the ALT_SYSMGR_DMA_IRQ_NS register field value.
#define ALT_SYSMGR_DMA_IRQ_NS_RESET 0x0 |
The reset value of the ALT_SYSMGR_DMA_IRQ_NS register field.
#define ALT_SYSMGR_DMA_IRQ_NS_GET | ( | value | ) | (((value) & 0xff000000) >> 24) |
Extracts the ALT_SYSMGR_DMA_IRQ_NS field value from a register.
#define ALT_SYSMGR_DMA_IRQ_NS_SET | ( | value | ) | (((value) << 24) & 0xff000000) |
Produces a ALT_SYSMGR_DMA_IRQ_NS register field value suitable for setting the register.
#define ALT_SYSMGR_DMA_RESET 0x00000100 |
The reset value of the ALT_SYSMGR_DMA register.
#define ALT_SYSMGR_DMA_OFST 0x20 |
The byte offset of the ALT_SYSMGR_DMA register from the beginning of the component.
typedef struct ALT_SYSMGR_DMA_s ALT_SYSMGR_DMA_t |
The typedef declaration for register ALT_SYSMGR_DMA.