Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gmacgrp_layer3_addr0_reg0

Description

Register 260 (Layer 3 Address 0 Register 0)

For IPv4 frames, the Layer 3 Address 0 Register 0 contains the 32-bit IP Source Address field. For IPv6 frames, it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field.

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00

Field : l3a00

Layer 3 Address 0 Field

When Bit 0 (L3PEN0) and Bit 2 (L3SAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 frames.

When Bit 0 (L3PEN0) and Bit 4 (L3DAM0) are set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with Bits [31:0] of the IP Destination Address field in the IPv6 frames.

When Bit 0 (L3PEN0) is reset and Bit 2 (L3SAM0) is set in Register 256 (Layer 3 and Layer 4 Control Register 0), this field contains the value to be matched with the IP Source Address field in the IPv4 frames.

Field Access Macros:

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB   0
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB   31
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH   32
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK   0xffffffff
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK   0x00000000
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET   0x0
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s
 

Macros

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_RESET   0x00000000
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST   0x410
 
#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s 
ALT_EMAC_GMAC_LYR3_ADDR0_REG0_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_LYR3_ADDR0_REG0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_LYR3_ADDR0_REG0.

Data Fields
uint32_t l3a00: 32 ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00

Macro Definitions

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_WIDTH   32

The width in bits of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET_MSK   0xffffffff

The mask used to set the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_CLR_MSK   0x00000000

The mask used to clear the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 field value from a register.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_EMAC_GMAC_LYR3_ADDR0_REG0_L3A00 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST   0x410

The byte offset of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register from the beginning of the component.

#define ALT_EMAC_GMAC_LYR3_ADDR0_REG0_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LYR3_ADDR0_REG0_OFST))

The address of the ALT_EMAC_GMAC_LYR3_ADDR0_REG0 register.

Typedef Documentation