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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Start Indirect Write |
[1] | RW | 0x0 | Cancel Indirect Write |
[2] | R | Unknown | Indirect Write Status |
[3] | R | 0x0 | Reserved |
[4] | R | Unknown | Queued Indirect Write Operations |
[5] | RW | Unknown | Indirect Completion Status |
[7:6] | R | Unknown | Completed Indirect Operations |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : Start Indirect Write - start | ||||||||||
Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDWR_START_E_END 0x1 | |||||||||
#define | ALT_QSPI_INDWR_START_E_DISD 0x0 | |||||||||
#define | ALT_QSPI_INDWR_START_LSB 0 | |||||||||
#define | ALT_QSPI_INDWR_START_MSB 0 | |||||||||
#define | ALT_QSPI_INDWR_START_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDWR_START_SET_MSK 0x00000001 | |||||||||
#define | ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_QSPI_INDWR_START_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDWR_START_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_QSPI_INDWR_START_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : Cancel Indirect Write - cancel | ||||||||||
Writing a 1 to this bit will cancel all ongoing indirect write operations. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_LSB 1 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_MSB 1 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_QSPI_INDWR_CANCEL_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Indirect Write Status - rdstat | ||||||||||
Indirect write operation in progress (status) Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_LSB 2 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_MSB 2 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_QSPI_INDWR_RDSTAT_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : Reserved - sramfull | |
Field Access Macros: | |
#define | ALT_QSPI_INDWR_SRAMFULL_LSB 3 |
#define | ALT_QSPI_INDWR_SRAMFULL_MSB 3 |
#define | ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 |
#define | ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 |
#define | ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 |
#define | ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 |
#define | ALT_QSPI_INDWR_SRAMFULL_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_QSPI_INDWR_SRAMFULL_SET(value) (((value) << 3) & 0x00000008) |
Field : Queued Indirect Write Operations - rdqueued | ||||||||||
Two indirect write operations have been queued Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_LSB 4 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_MSB 4 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_QSPI_INDWR_RDQUEUED_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : Indirect Completion Status - inddone | ||||||||||
This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_LSB 5 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_MSB 5 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_QSPI_INDWR_INDDONE_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : Completed Indirect Operations - indcnt | |
This field contains the count of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). Field Access Macros: | |
#define | ALT_QSPI_INDWR_INDCNT_LSB 6 |
#define | ALT_QSPI_INDWR_INDCNT_MSB 7 |
#define | ALT_QSPI_INDWR_INDCNT_WIDTH 2 |
#define | ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 |
#define | ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f |
#define | ALT_QSPI_INDWR_INDCNT_RESET 0x0 |
#define | ALT_QSPI_INDWR_INDCNT_GET(value) (((value) & 0x000000c0) >> 6) |
#define | ALT_QSPI_INDWR_INDCNT_SET(value) (((value) << 6) & 0x000000c0) |
Data Structures | |
struct | ALT_QSPI_INDWR_s |
Macros | |
#define | ALT_QSPI_INDWR_OFST 0x70 |
Typedefs | |
typedef struct ALT_QSPI_INDWR_s | ALT_QSPI_INDWR_t |
struct ALT_QSPI_INDWR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_INDWR.
Data Fields | ||
---|---|---|
uint32_t | start: 1 | Start Indirect Write |
uint32_t | cancel: 1 | Cancel Indirect Write |
const uint32_t | rdstat: 1 | Indirect Write Status |
const uint32_t | sramfull: 1 | Reserved |
const uint32_t | rdqueued: 1 | Queued Indirect Write Operations |
uint32_t | inddone: 1 | Indirect Completion Status |
const uint32_t | indcnt: 2 | Completed Indirect Operations |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_QSPI_INDWR_START_E_END 0x1 |
Enumerated value for register field ALT_QSPI_INDWR_START
Trigger indirect write operation
#define ALT_QSPI_INDWR_START_E_DISD 0x0 |
Enumerated value for register field ALT_QSPI_INDWR_START
No Action
#define ALT_QSPI_INDWR_START_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_START register field.
#define ALT_QSPI_INDWR_START_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_START register field.
#define ALT_QSPI_INDWR_START_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_START register field.
#define ALT_QSPI_INDWR_START_SET_MSK 0x00000001 |
The mask used to set the ALT_QSPI_INDWR_START register field value.
#define ALT_QSPI_INDWR_START_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_QSPI_INDWR_START register field value.
#define ALT_QSPI_INDWR_START_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_START register field.
#define ALT_QSPI_INDWR_START_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_QSPI_INDWR_START field value from a register.
#define ALT_QSPI_INDWR_START_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_QSPI_INDWR_START register field value suitable for setting the register.
#define ALT_QSPI_INDWR_CANCEL_E_CANCEINDWR 0x1 |
Enumerated value for register field ALT_QSPI_INDWR_CANCEL
Cancel Indirect write operation
#define ALT_QSPI_INDWR_CANCEL_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDWR_CANCEL
No Action
#define ALT_QSPI_INDWR_CANCEL_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_CANCEL register field.
#define ALT_QSPI_INDWR_CANCEL_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_CANCEL register field.
#define ALT_QSPI_INDWR_CANCEL_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_CANCEL register field.
#define ALT_QSPI_INDWR_CANCEL_SET_MSK 0x00000002 |
The mask used to set the ALT_QSPI_INDWR_CANCEL register field value.
#define ALT_QSPI_INDWR_CANCEL_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_QSPI_INDWR_CANCEL register field value.
#define ALT_QSPI_INDWR_CANCEL_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_CANCEL register field.
#define ALT_QSPI_INDWR_CANCEL_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_QSPI_INDWR_CANCEL field value from a register.
#define ALT_QSPI_INDWR_CANCEL_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_QSPI_INDWR_CANCEL register field value suitable for setting the register.
#define ALT_QSPI_INDWR_RDSTAT_E_INDWRSTAT 0x1 |
Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
Indirect write operation
#define ALT_QSPI_INDWR_RDSTAT_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDWR_RDSTAT
No Action
#define ALT_QSPI_INDWR_RDSTAT_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDSTAT register field.
#define ALT_QSPI_INDWR_RDSTAT_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDSTAT register field.
#define ALT_QSPI_INDWR_RDSTAT_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_RDSTAT register field.
#define ALT_QSPI_INDWR_RDSTAT_SET_MSK 0x00000004 |
The mask used to set the ALT_QSPI_INDWR_RDSTAT register field value.
#define ALT_QSPI_INDWR_RDSTAT_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_QSPI_INDWR_RDSTAT register field value.
#define ALT_QSPI_INDWR_RDSTAT_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_RDSTAT register field is UNKNOWN.
#define ALT_QSPI_INDWR_RDSTAT_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_QSPI_INDWR_RDSTAT field value from a register.
#define ALT_QSPI_INDWR_RDSTAT_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_QSPI_INDWR_RDSTAT register field value suitable for setting the register.
#define ALT_QSPI_INDWR_SRAMFULL_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_SRAMFULL register field.
#define ALT_QSPI_INDWR_SRAMFULL_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_SRAMFULL register field.
#define ALT_QSPI_INDWR_SRAMFULL_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_SRAMFULL register field.
#define ALT_QSPI_INDWR_SRAMFULL_SET_MSK 0x00000008 |
The mask used to set the ALT_QSPI_INDWR_SRAMFULL register field value.
#define ALT_QSPI_INDWR_SRAMFULL_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_QSPI_INDWR_SRAMFULL register field value.
#define ALT_QSPI_INDWR_SRAMFULL_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_SRAMFULL register field.
#define ALT_QSPI_INDWR_SRAMFULL_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_QSPI_INDWR_SRAMFULL field value from a register.
#define ALT_QSPI_INDWR_SRAMFULL_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_QSPI_INDWR_SRAMFULL register field value suitable for setting the register.
#define ALT_QSPI_INDWR_RDQUEUED_E_INDWROP 0x1 |
Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
Two Indirect write operation
#define ALT_QSPI_INDWR_RDQUEUED_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDWR_RDQUEUED
No Action
#define ALT_QSPI_INDWR_RDQUEUED_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_RDQUEUED register field.
#define ALT_QSPI_INDWR_RDQUEUED_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_RDQUEUED register field.
#define ALT_QSPI_INDWR_RDQUEUED_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_RDQUEUED register field.
#define ALT_QSPI_INDWR_RDQUEUED_SET_MSK 0x00000010 |
The mask used to set the ALT_QSPI_INDWR_RDQUEUED register field value.
#define ALT_QSPI_INDWR_RDQUEUED_CLR_MSK 0xffffffef |
The mask used to clear the ALT_QSPI_INDWR_RDQUEUED register field value.
#define ALT_QSPI_INDWR_RDQUEUED_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_RDQUEUED register field is UNKNOWN.
#define ALT_QSPI_INDWR_RDQUEUED_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_QSPI_INDWR_RDQUEUED field value from a register.
#define ALT_QSPI_INDWR_RDQUEUED_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_QSPI_INDWR_RDQUEUED register field value suitable for setting the register.
#define ALT_QSPI_INDWR_INDDONE_E_INDCOMPST 0x1 |
Enumerated value for register field ALT_QSPI_INDWR_INDDONE
Indirect operation completed
#define ALT_QSPI_INDWR_INDDONE_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDWR_INDDONE
No Action
#define ALT_QSPI_INDWR_INDDONE_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDDONE register field.
#define ALT_QSPI_INDWR_INDDONE_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDDONE register field.
#define ALT_QSPI_INDWR_INDDONE_WIDTH 1 |
The width in bits of the ALT_QSPI_INDWR_INDDONE register field.
#define ALT_QSPI_INDWR_INDDONE_SET_MSK 0x00000020 |
The mask used to set the ALT_QSPI_INDWR_INDDONE register field value.
#define ALT_QSPI_INDWR_INDDONE_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_QSPI_INDWR_INDDONE register field value.
#define ALT_QSPI_INDWR_INDDONE_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_INDDONE register field is UNKNOWN.
#define ALT_QSPI_INDWR_INDDONE_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_QSPI_INDWR_INDDONE field value from a register.
#define ALT_QSPI_INDWR_INDDONE_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_QSPI_INDWR_INDDONE register field value suitable for setting the register.
#define ALT_QSPI_INDWR_INDCNT_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDWR_INDCNT register field.
#define ALT_QSPI_INDWR_INDCNT_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDWR_INDCNT register field.
#define ALT_QSPI_INDWR_INDCNT_WIDTH 2 |
The width in bits of the ALT_QSPI_INDWR_INDCNT register field.
#define ALT_QSPI_INDWR_INDCNT_SET_MSK 0x000000c0 |
The mask used to set the ALT_QSPI_INDWR_INDCNT register field value.
#define ALT_QSPI_INDWR_INDCNT_CLR_MSK 0xffffff3f |
The mask used to clear the ALT_QSPI_INDWR_INDCNT register field value.
#define ALT_QSPI_INDWR_INDCNT_RESET 0x0 |
The reset value of the ALT_QSPI_INDWR_INDCNT register field is UNKNOWN.
#define ALT_QSPI_INDWR_INDCNT_GET | ( | value | ) | (((value) & 0x000000c0) >> 6) |
Extracts the ALT_QSPI_INDWR_INDCNT field value from a register.
#define ALT_QSPI_INDWR_INDCNT_SET | ( | value | ) | (((value) << 6) & 0x000000c0) |
Produces a ALT_QSPI_INDWR_INDCNT register field value suitable for setting the register.
#define ALT_QSPI_INDWR_OFST 0x70 |
The byte offset of the ALT_QSPI_INDWR register from the beginning of the component.
typedef struct ALT_QSPI_INDWR_s ALT_QSPI_INDWR_t |
The typedef declaration for register ALT_QSPI_INDWR.