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Register : FPGA Ports Reset Control Register - fpgaportrst

Description

This register implements functionality to allow the CPU to control when the MPFE will enable the ports to the FPGA fabric.

Register Layout

Bits Access Reset Description
[13:0] RW Unknown Port Reset Control
[31:14] ??? 0x0 UNDEFINED

Field : Port Reset Control - portrstn

This register should be written to with a 1 to enable the selected FPGA port to exit reset. Writing a bit to a zero will stretch the port reset until the register is written. Read data ports are connected to bits 3:0, with read data port 0 at bit 0 to read data port 3 at bit 3. Write data ports 0 to 3 are mapped to 4 to 7, with write data port 0 connected to bit 4 to write data port 3 at bit

  1. Command ports are connected to bits 8 to 13, with command port 0 at bit 8 to command port 5 at bit 13. Expected usage would be to set all the bits at the same time but setting some bits to a zero and others to a one is supported.

Field Access Macros:

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB   0
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB   13
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH   14
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK   0x00003fff
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK   0xffffc000
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET   0x0
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET(value)   (((value) & 0x00003fff) >> 0)
 
#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET(value)   (((value) << 0) & 0x00003fff)
 

Data Structures

struct  ALT_SDR_CTL_FPGAPORTRST_s
 

Macros

#define ALT_SDR_CTL_FPGAPORTRST_OFST   0x80
 

Typedefs

typedef struct
ALT_SDR_CTL_FPGAPORTRST_s 
ALT_SDR_CTL_FPGAPORTRST_t
 

Data Structure Documentation

struct ALT_SDR_CTL_FPGAPORTRST_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDR_CTL_FPGAPORTRST.

Data Fields
uint32_t portrstn: 14 Port Reset Control
uint32_t __pad0__: 18 UNDEFINED

Macro Definitions

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_MSB   13

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_WIDTH   14

The width in bits of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET_MSK   0x00003fff

The mask used to set the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_CLR_MSK   0xffffc000

The mask used to clear the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_RESET   0x0

The reset value of the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field is UNKNOWN.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_GET (   value)    (((value) & 0x00003fff) >> 0)

Extracts the ALT_SDR_CTL_FPGAPORTRST_PORTRSTN field value from a register.

#define ALT_SDR_CTL_FPGAPORTRST_PORTRSTN_SET (   value)    (((value) << 0) & 0x00003fff)

Produces a ALT_SDR_CTL_FPGAPORTRST_PORTRSTN register field value suitable for setting the register.

#define ALT_SDR_CTL_FPGAPORTRST_OFST   0x80

The byte offset of the ALT_SDR_CTL_FPGAPORTRST register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDR_CTL_FPGAPORTRST.