Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ctrlcfg5

Description

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT
[7:4] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT
[8] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN
[9] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN
[10] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN
[11] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN
[12] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN
[31:13] ??? 0x0 UNDEFINED

Field : cfg_col_cmd_slot

Specify the col cmd slot. One hot encoding.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_LSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_MSB   3
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET_MSK   0x0000000f
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_CLR_MSK   0xfffffff0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : cfg_row_cmd_slot

Specify the row cmd slot. One hot encoding.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_LSB   4
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_MSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET_MSK   0x000000f0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK   0xffffff0f
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_GET(value)   (((value) & 0x000000f0) >> 4)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET(value)   (((value) << 4) & 0x000000f0)
 

Field : cfg_ctrl_rc_en

Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_LSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_MSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET_MSK   0x00000100
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_CLR_MSK   0xfffffeff
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : cfg_dbc0_rc_en

Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_LSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_MSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET_MSK   0x00000200
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_CLR_MSK   0xfffffdff
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET(value)   (((value) << 9) & 0x00000200)
 

Field : cfg_dbc1_rc_en

Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_LSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_MSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET_MSK   0x00000400
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_CLR_MSK   0xfffffbff
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET(value)   (((value) << 10) & 0x00000400)
 

Field : cfg_dbc2_rc_en

Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_LSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_MSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET_MSK   0x00000800
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_CLR_MSK   0xfffff7ff
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET(value)   (((value) << 11) & 0x00000800)
 

Field : cfg_dbc3_rc_en

Set to 1 to enable the rate conversion. It converts QR input from core to HR inside HMC

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_LSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_MSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET_MSK   0x00001000
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_CLR_MSK   0xffffefff
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET(value)   (((value) << 12) & 0x00001000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CTLCFG5_s
 

Macros

#define ALT_IO48_HMC_MMR_CTLCFG5_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CTLCFG5_OFST   0x3c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CTLCFG5_s 
ALT_IO48_HMC_MMR_CTLCFG5_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CTLCFG5_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG5.

Data Fields
uint32_t cfg_col_cmd_slot: 4 ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT
uint32_t cfg_row_cmd_slot: 4 ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT
uint32_t cfg_ctrl_rc_en: 1 ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN
uint32_t cfg_dbc0_rc_en: 1 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN
uint32_t cfg_dbc1_rc_en: 1 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN
uint32_t cfg_dbc2_rc_en: 1 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN
uint32_t cfg_dbc3_rc_en: 1 ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN
uint32_t __pad0__: 19 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_MSB   3

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET_MSK   0x0000000f

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_CLR_MSK   0xfffffff0

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_COL_CMD_SLOT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_LSB   4

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_MSB   7

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET_MSK   0x000000f0

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_CLR_MSK   0xffffff0f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_GET (   value)    (((value) & 0x000000f0) >> 4)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT_SET (   value)    (((value) << 4) & 0x000000f0)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_ROW_CMD_SLOT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_LSB   8

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET_MSK   0x00000100

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_CTL_RC_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_MSB   9

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET_MSK   0x00000200

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_CLR_MSK   0xfffffdff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC0_RC_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_LSB   10

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_MSB   10

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET_MSK   0x00000400

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_CLR_MSK   0xfffffbff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC1_RC_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_LSB   11

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_MSB   11

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET_MSK   0x00000800

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC2_RC_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_LSB   12

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_MSB   12

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET_MSK   0x00001000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_CLR_MSK   0xffffefff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_IO48_HMC_MMR_CTLCFG5_CFG_DBC3_RC_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG5_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CTLCFG5 register.

#define ALT_IO48_HMC_MMR_CTLCFG5_OFST   0x3c

The byte offset of the ALT_IO48_HMC_MMR_CTLCFG5 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG5.