Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 280 (Layer 3 and Layer 4 Control Register 2) - gmacgrp_l3_l4_control2

Description

This register controls the operations of the filter 2 of Layer 3 and Layer 4.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Layer 3 Protocol Enable
[1] ??? 0x0 UNDEFINED
[2] RW 0x0 Layer 3 IP SA Match Enable
[3] RW 0x0 Layer 3 IP SA Inverse Match Enable
[4] RW 0x0 Layer 3 IP DA Match Enable
[5] RW 0x0 Layer 3 IP DA Inverse Match Enable
[10:6] RW 0x0 ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2
[15:11] RW 0x0 Layer 3 IP DA Higher Bits Match
[16] RW 0x0 Layer 4 Protocol Enable
[17] ??? 0x0 UNDEFINED
[18] RW 0x0 Layer 4 Source Port Match Enable
[19] RW 0x0 Layer 4 Source Port Inverse Match Enable
[20] RW 0x0 Layer 4 Destination Port Match Enable
[21] RW 0x0 Layer 4 Destination Port Inverse Match Enable
[31:22] ??? 0x0 UNDEFINED

Field : Layer 3 Protocol Enable - l3pen2

When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames.

The Layer 3 matching is done only when either L3SAM2 or L3DAM2 bit is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB   0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB   0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Layer 3 IP SA Match Enable - l3sam2

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching.

Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 4 (L3DAM2) because either IPv6 SA or DA can be checked for filtering.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB   2
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB   2
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Layer 3 IP SA Inverse Match Enable - l3saim2

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 2 (L3SAM2) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB   3
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB   3
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Layer 3 IP DA Match Enable - l3dam2

When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching.

Note: When Bit 0 (L3PEN2) is set, you should set either this bit or Bit 2 (L3SAM2) because either IPv6 DA or SA can be checked for filtering.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB   4
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB   4
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Layer 3 IP DA Inverse Match Enable - l3daim2

When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 4 (L3DAM2) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET(value)   (((value) << 5) & 0x00000020)
 

Field : l3hsbm2

Layer 3 IP SA Higher Bits Match

IPv4 Frames:

This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 31: All bits except MSb are masked.

IPv6 Frames:

This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames.

This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB   6
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB   10
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK   0x000007c0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK   0xfffff83f
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET(value)   (((value) & 0x000007c0) >> 6)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET(value)   (((value) << 6) & 0x000007c0)
 

Field : Layer 3 IP DA Higher Bits Match - l3hdbm2

IPv4 Frames:

This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 31: All bits except MSb are masked.

IPv6 Frames:

Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM2, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM2[1:0] and L3HSBM2 bits:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 127: All bits except MSb are masked.

This field is valid and applicable only if L3DAM2 or L3SAM2 is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB   11
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB   15
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK   0x0000f800
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK   0xffff07ff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET(value)   (((value) & 0x0000f800) >> 11)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET(value)   (((value) << 11) & 0x0000f800)
 

Field : Layer 4 Protocol Enable - l4pen2

When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching.

The Layer 4 matching is done only when either L4SPM2 or L4DPM2 bit is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB   16
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB   16
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Layer 4 Source Port Match Enable - l4spm2

When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB   18
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB   18
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET(value)   (((value) << 18) & 0x00040000)
 

Field : Layer 4 Source Port Inverse Match Enable - l4spim2

When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 18 (L4SPM2) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB   19
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB   19
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET(value)   (((value) << 19) & 0x00080000)
 

Field : Layer 4 Destination Port Match Enable - l4dpm2

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB   20
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB   20
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET(value)   (((value) << 20) & 0x00100000)
 

Field : Layer 4 Destination Port Inverse Match Enable - l4dpim2

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 20 (L4DPM0) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB   21
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB   21
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET(value)   (((value) << 21) & 0x00200000)
 

Data Structures

struct  ALT_EMAC_GMAC_L3_L4_CTL2_s
 

Macros

#define ALT_EMAC_GMAC_L3_L4_CTL2_RESET   0x00000000
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_OFST   0x460
 
#define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_L3_L4_CTL2_s 
ALT_EMAC_GMAC_L3_L4_CTL2_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_L3_L4_CTL2_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL2.

Data Fields
uint32_t l3pen2: 1 Layer 3 Protocol Enable
uint32_t __pad0__: 1 UNDEFINED
uint32_t l3sam2: 1 Layer 3 IP SA Match Enable
uint32_t l3saim2: 1 Layer 3 IP SA Inverse Match Enable
uint32_t l3dam2: 1 Layer 3 IP DA Match Enable
uint32_t l3daim2: 1 Layer 3 IP DA Inverse Match Enable
uint32_t l3hsbm2: 5 ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2
uint32_t l3hdbm2: 5 Layer 3 IP DA Higher Bits Match
uint32_t l4pen2: 1 Layer 4 Protocol Enable
uint32_t __pad1__: 1 UNDEFINED
uint32_t l4spm2: 1 Layer 4 Source Port Match Enable
uint32_t l4spim2: 1 Layer 4 Source Port Inverse Match Enable
uint32_t l4dpm2: 1 Layer 4 Destination Port Match Enable
uint32_t l4dpim2: 1 Layer 4 Destination Port Inverse Match Enable
uint32_t __pad2__: 10 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3PEN2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3SAIM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3DAIM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET_MSK   0x000007c0

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_CLR_MSK   0xfffff83f

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_GET (   value)    (((value) & 0x000007c0) >> 6)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2_SET (   value)    (((value) << 6) & 0x000007c0)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HSBM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET_MSK   0x0000f800

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_CLR_MSK   0xffff07ff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_GET (   value)    (((value) & 0x0000f800) >> 11)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2_SET (   value)    (((value) << 11) & 0x0000f800)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L3HDBM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4PEN2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4SPIM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL2_L4DPIM2 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL2 register.

#define ALT_EMAC_GMAC_L3_L4_CTL2_OFST   0x460

The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL2 register from the beginning of the component.

#define ALT_EMAC_GMAC_L3_L4_CTL2_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL2_OFST))

The address of the ALT_EMAC_GMAC_L3_L4_CTL2 register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL2.