Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 320 (Hash Table Register 0) - gmacgrp_hash_table_reg0

Description

This register contains the first 32 bits of the hash table.

The 256-bit Hash table is used for group address filtering. For hash filtering, the content of the destination address in the incoming frame is passed through the CRC logic and the upper eight bits of the CRC register are used to index the content of the Hash table. The most significant bits determines the register to be used (Hash Table Register X), and the least significant five bits determine the bit within the register. For example, a hash value of 8b'10111111 selects Bit 31 of the Hash Table Register 5.

The hash value of the destination address is calculated in the following way:

  1. Calculate the 32-bit CRC for the DA (See IEEE 802.3, Section 3.2.8 for the steps to calculate CRC32).
  1. Perform bitwise reversal for the value obtained in Step 1.
  1. Take the upper 8 bits from the value obtained in Step 2.

If the corresponding bit value of the register is 1'b1, the frame is accepted. Otherwise, it is rejected. If the Bit 1 (Pass All Multicast) is set in Register 1 (MAC Frame Filter), then all multicast frames are accepted regardless of the multicast hash values.

Because the Hash Table register is double-synchronized to the (G)MII clock domain, the synchronization is triggered only when Bits[31:24] (in little-endian mode) or Bits[7:0] (in big-endian mode) of the Hash Table Register X registers are written.

Note: Because of double-synchronization, consecutive writes to this register should be performed after at least four clock cycles in the destination clock domain.

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 First 32 bits of Hash Table

Field : First 32 bits of Hash Table - ht31t0

This field contains the first 32 Bits (31:0) of the Hash table.

Field Access Macros:

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB   0
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB   31
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH   32
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK   0xffffffff
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK   0x00000000
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET   0x0
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_EMAC_GMAC_HASH_TABLE_REG0_s
 

Macros

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_RESET   0x00000000
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST   0x500
 
#define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_HASH_TABLE_REG0_s 
ALT_EMAC_GMAC_HASH_TABLE_REG0_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_HASH_TABLE_REG0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_HASH_TABLE_REG0.

Data Fields
uint32_t ht31t0: 32 First 32 bits of Hash Table

Macro Definitions

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_WIDTH   32

The width in bits of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET_MSK   0xffffffff

The mask used to set the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_CLR_MSK   0x00000000

The mask used to clear the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 field value from a register.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_EMAC_GMAC_HASH_TABLE_REG0_HT31T0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST   0x500

The byte offset of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register from the beginning of the component.

#define ALT_EMAC_GMAC_HASH_TABLE_REG0_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_HASH_TABLE_REG0_OFST))

The address of the ALT_EMAC_GMAC_HASH_TABLE_REG0 register.

Typedef Documentation