Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ddr_T_main_Scheduler_ReadLatency

Description

Register Layout

Bits Access Reset Description
[7:0] RW 0x13 ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY
[31:8] ??? Unknown UNDEFINED

Field : READLATENCY

Maximun delay between a read request and the first data response.

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_LSB   0
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_MSB   7
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_WIDTH   8
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET_MSK   0x000000ff
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_CLR_MSK   0xffffff00
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_RESET   0x13
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET(value)   (((value) << 0) & 0x000000ff)
 

Data Structures

struct  ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s
 

Macros

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RESET   0x00000013
 
#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_OFST   0x14
 

Typedefs

typedef struct
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s 
ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_t
 

Data Structure Documentation

struct ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY.

Data Fields
uint32_t READLATENCY: 8 ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_MSB   7

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_WIDTH   8

The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET_MSK   0x000000ff

The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_CLR_MSK   0xffffff00

The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_RESET   0x13

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY field value from a register.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RDLATENCY register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_RESET   0x00000013

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY register.

#define ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY_OFST   0x14

The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_RDLATENCY register from the beginning of the component.

Typedef Documentation