Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : RAM Status Register - ramstat

Description

The RAMSTAT register contains bits that indicate the security RAM clearing event during cold or warm reset for each RAM.

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

For MPU, there are seperate bits for L1 invalidate only or full security clearing.

There is another bit for L1 invalidate timeout error only. The security RAM clearing does not have a timeout.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Onchip RAM RAMSTATUS bit during cold/warm reset
[1] RW 0x0 USB0 RAM RAMSTATUS bit during cold/warm reset
[2] RW 0x0 USB1 RAM RAMSTATUS bit during cold/warm reset
[3] RW 0x0 SDMMC RAM RAMSTATUS bit during cold/warm reset
[4] RW 0x0 DMA RAM RAMSTATUS bit during cold/warm reset
[5] RW 0x0 NAND Write RAM RAMSTATUS bit during cold/warm reset
[6] RW 0x0 NAND Read RAM RAMSTATUS bit during cold/warm reset
[7] RW 0x0 NAND ECC RAM RAMSTATUS bit during cold/warm reset
[8] RW 0x0 EMAC0 RX RAM RAMSTATUS bit during cold/warm reset
[9] RW 0x0 EMAC0 TX RAM RAMSTATUS bit during cold/warm reset
[10] RW 0x0 EMAC1 RX RAM RAMSTATUS bit during cold/warm reset
[11] RW 0x0 EMAC1 TX RAM RAMSTATUS bit during cold/warm reset
[12] RW 0x0 EMAC2 TX RAM RAMSTATUS bit during cold/warm reset
[13] RW 0x0 EMAC2 RX RAM RAMSTATUS bit during cold/warm reset
[14] RW 0x0 QSPI RAM RAMSTATUS bit during cold/warm reset
[15] RW 0x0 MWP RAM RAMSTATUS bit during cold/warm reset
[16] RW 0x0 MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset
[17] RW 0x0 MPU l1 RAM clearing timeout during cold/warm reset
[31:18] ??? 0x0 UNDEFINED

Field : Onchip RAM RAMSTATUS bit during cold/warm reset - onchipramclr

RAMSTATUS bit to indicate Onchip RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_LSB   0
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_MSB   0
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET_MSK   0x00000001
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : USB0 RAM RAMSTATUS bit during cold/warm reset - otg0ramclr

RAMSTATUS bit to indicate USB0 RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_LSB   1
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_MSB   1
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET_MSK   0x00000002
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET(value)   (((value) << 1) & 0x00000002)
 

Field : USB1 RAM RAMSTATUS bit during cold/warm reset - otg1ramclr

RAMSTATUS bit to indicate USB1 RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_LSB   2
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_MSB   2
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET_MSK   0x00000004
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET(value)   (((value) << 2) & 0x00000004)
 

Field : SDMMC RAM RAMSTATUS bit during cold/warm reset - sdmmcramclr

RAMSTATUS bit to indicate SDMMC RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_LSB   3
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_MSB   3
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET_MSK   0x00000008
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET(value)   (((value) << 3) & 0x00000008)
 

Field : DMA RAM RAMSTATUS bit during cold/warm reset - dmaramclr

RAMSTATUS bit to indicate DMA RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_LSB   4
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_MSB   4
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET_MSK   0x00000010
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_CLR_MSK   0xffffffef
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET(value)   (((value) << 4) & 0x00000010)
 

Field : NAND Write RAM RAMSTATUS bit during cold/warm reset - nandwramclr

RAMSTATUS bit to indicate NAND Write RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_LSB   5
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_MSB   5
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET_MSK   0x00000020
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_CLR_MSK   0xffffffdf
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET(value)   (((value) << 5) & 0x00000020)
 

Field : NAND Read RAM RAMSTATUS bit during cold/warm reset - nandrramclr

RAMSTATUS bit to indicate NAND Read RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_LSB   6
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_MSB   6
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET_MSK   0x00000040
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_CLR_MSK   0xffffffbf
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET(value)   (((value) << 6) & 0x00000040)
 

Field : NAND ECC RAM RAMSTATUS bit during cold/warm reset - nanderamclr

RAMSTATUS bit to indicate NAND ECC RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_LSB   7
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_MSB   7
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET_MSK   0x00000080
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_CLR_MSK   0xffffff7f
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET(value)   (((value) << 7) & 0x00000080)
 

Field : EMAC0 RX RAM RAMSTATUS bit during cold/warm reset - emac0rxramclr

RAMSTATUS bit to indicate EMAC0 RX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_LSB   8
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_MSB   8
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET_MSK   0x00000100
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_CLR_MSK   0xfffffeff
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET(value)   (((value) << 8) & 0x00000100)
 

Field : EMAC0 TX RAM RAMSTATUS bit during cold/warm reset - emac0txramclr

RAMSTATUS bit to indicate EMAC0 TX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_LSB   9
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_MSB   9
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET_MSK   0x00000200
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_CLR_MSK   0xfffffdff
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET(value)   (((value) << 9) & 0x00000200)
 

Field : EMAC1 RX RAM RAMSTATUS bit during cold/warm reset - emac1rxramclr

RAMSTATUS bit to indicate EMAC1 RX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_LSB   10
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_MSB   10
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET_MSK   0x00000400
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_CLR_MSK   0xfffffbff
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET(value)   (((value) << 10) & 0x00000400)
 

Field : EMAC1 TX RAM RAMSTATUS bit during cold/warm reset - emac1txramclr

RAMSTATUS bit to indicate EMAC1 TX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_LSB   11
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_MSB   11
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET_MSK   0x00000800
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_CLR_MSK   0xfffff7ff
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET(value)   (((value) << 11) & 0x00000800)
 

Field : EMAC2 TX RAM RAMSTATUS bit during cold/warm reset - emac2txramclr

RAMSTATUS bit to indicate EMAC2 TX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_LSB   12
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_MSB   12
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET_MSK   0x00001000
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_CLR_MSK   0xffffefff
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET(value)   (((value) << 12) & 0x00001000)
 

Field : EMAC2 RX RAM RAMSTATUS bit during cold/warm reset - emac2rxramclr

RAMSTATUS bit to indicate EMAC2 RX RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_LSB   13
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_MSB   13
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET_MSK   0x00002000
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_CLR_MSK   0xffffdfff
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET(value)   (((value) << 13) & 0x00002000)
 

Field : QSPI RAM RAMSTATUS bit during cold/warm reset - qspiramclr

RAMSTATUS bit to indicate QSPI RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_LSB   14
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_MSB   14
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET_MSK   0x00004000
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_CLR_MSK   0xffffbfff
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET(value)   (((value) << 14) & 0x00004000)
 

Field : MWP RAM RAMSTATUS bit during cold/warm reset - mwpramclr

RAMSTATUS bit to indicate MWP RAM is cleared during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_LSB   15
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_MSB   15
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET_MSK   0x00008000
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_CLR_MSK   0xffff7fff
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET(value)   (((value) << 15) & 0x00008000)
 

Field : MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset - mpul1ramclr

RAMSTATUS bit to indicate MPU L1 invalidate clearing only or full security clearing during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_LSB   16
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_MSB   16
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET_MSK   0x00010000
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_CLR_MSK   0xfffeffff
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET(value)   (((value) << 16) & 0x00010000)
 

Field : MPU l1 RAM clearing timeout during cold/warm reset - mpul1timeout

RAMSTATUS bit to indicate MPU l1 RAM cleared timeout during cold/warm reset

Field Access Macros:

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_LSB   17
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_MSB   17
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_WIDTH   1
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET_MSK   0x00020000
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_CLR_MSK   0xfffdffff
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_RESET   0x0
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET(value)   (((value) << 17) & 0x00020000)
 

Data Structures

struct  ALT_RSTMGR_RAMSTAT_s
 

Macros

#define ALT_RSTMGR_RAMSTAT_RESET   0x00000000
 
#define ALT_RSTMGR_RAMSTAT_OFST   0x4
 

Typedefs

typedef struct ALT_RSTMGR_RAMSTAT_s ALT_RSTMGR_RAMSTAT_t
 

Data Structure Documentation

struct ALT_RSTMGR_RAMSTAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_RAMSTAT.

Data Fields
uint32_t onchipramclr: 1 Onchip RAM RAMSTATUS bit during cold/warm reset
uint32_t otg0ramclr: 1 USB0 RAM RAMSTATUS bit during cold/warm reset
uint32_t otg1ramclr: 1 USB1 RAM RAMSTATUS bit during cold/warm reset
uint32_t sdmmcramclr: 1 SDMMC RAM RAMSTATUS bit during cold/warm reset
uint32_t dmaramclr: 1 DMA RAM RAMSTATUS bit during cold/warm reset
uint32_t nandwramclr: 1 NAND Write RAM RAMSTATUS bit during cold/warm reset
uint32_t nandrramclr: 1 NAND Read RAM RAMSTATUS bit during cold/warm reset
uint32_t nanderamclr: 1 NAND ECC RAM RAMSTATUS bit during cold/warm reset
uint32_t emac0rxramclr: 1 EMAC0 RX RAM RAMSTATUS bit during cold/warm reset
uint32_t emac0txramclr: 1 EMAC0 TX RAM RAMSTATUS bit during cold/warm reset
uint32_t emac1rxramclr: 1 EMAC1 RX RAM RAMSTATUS bit during cold/warm reset
uint32_t emac1txramclr: 1 EMAC1 TX RAM RAMSTATUS bit during cold/warm reset
uint32_t emac2txramclr: 1 EMAC2 TX RAM RAMSTATUS bit during cold/warm reset
uint32_t emac2rxramclr: 1 EMAC2 RX RAM RAMSTATUS bit during cold/warm reset
uint32_t qspiramclr: 1 QSPI RAM RAMSTATUS bit during cold/warm reset
uint32_t mwpramclr: 1 MWP RAM RAMSTATUS bit during cold/warm reset
uint32_t mpul1ramclr: 1 MPU L1 invalidate clearing only RAMSTATUS bit during cold/warm reset
uint32_t mpul1timeout: 1 MPU l1 RAM clearing timeout during cold/warm reset
uint32_t __pad0__: 14 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_RAMSTAT_ONCHIPRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_RAMSTAT_OTG0RAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_OTG0RAMCLR_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_RAMSTAT_OTG0RAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_RAMSTAT_OTG1RAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_OTG1RAMCLR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_RAMSTAT_OTG1RAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_RAMSTAT_SDMMCRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_LSB   4

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_MSB   4

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET_MSK   0x00000010

The mask used to set the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_CLR_MSK   0xffffffef

The mask used to clear the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_DMARAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_RSTMGR_RAMSTAT_DMARAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_DMARAMCLR_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_RSTMGR_RAMSTAT_DMARAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_LSB   5

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_MSB   5

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET_MSK   0x00000020

The mask used to set the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_CLR_MSK   0xffffffdf

The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_RSTMGR_RAMSTAT_NANDWRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_NANDWRAMCLR_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_RSTMGR_RAMSTAT_NANDWRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_LSB   6

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_MSB   6

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET_MSK   0x00000040

The mask used to set the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_CLR_MSK   0xffffffbf

The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_RSTMGR_RAMSTAT_NANDRRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_NANDRRAMCLR_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_RSTMGR_RAMSTAT_NANDRRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_LSB   7

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_MSB   7

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET_MSK   0x00000080

The mask used to set the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_CLR_MSK   0xffffff7f

The mask used to clear the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_RSTMGR_RAMSTAT_NANDERAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_NANDERAMCLR_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_RSTMGR_RAMSTAT_NANDERAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_LSB   8

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_MSB   8

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET_MSK   0x00000100

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_CLR_MSK   0xfffffeff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_RSTMGR_RAMSTAT_EMAC0RXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_LSB   9

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_MSB   9

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET_MSK   0x00000200

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_CLR_MSK   0xfffffdff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_RSTMGR_RAMSTAT_EMAC0TXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_LSB   10

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_MSB   10

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET_MSK   0x00000400

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_CLR_MSK   0xfffffbff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_RSTMGR_RAMSTAT_EMAC1RXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_LSB   11

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_MSB   11

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET_MSK   0x00000800

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_RSTMGR_RAMSTAT_EMAC1TXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_LSB   12

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_MSB   12

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET_MSK   0x00001000

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_CLR_MSK   0xffffefff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_RSTMGR_RAMSTAT_EMAC2TXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_LSB   13

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_MSB   13

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET_MSK   0x00002000

The mask used to set the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_CLR_MSK   0xffffdfff

The mask used to clear the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_RSTMGR_RAMSTAT_EMAC2RXRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_LSB   14

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_MSB   14

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET_MSK   0x00004000

The mask used to set the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_CLR_MSK   0xffffbfff

The mask used to clear the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_RSTMGR_RAMSTAT_QSPIRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_QSPIRAMCLR_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_RSTMGR_RAMSTAT_QSPIRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_LSB   15

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_MSB   15

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET_MSK   0x00008000

The mask used to set the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_CLR_MSK   0xffff7fff

The mask used to clear the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_RSTMGR_RAMSTAT_MWPRAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_MWPRAMCLR_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_RSTMGR_RAMSTAT_MWPRAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_LSB   16

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_MSB   16

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET_MSK   0x00010000

The mask used to set the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_CLR_MSK   0xfffeffff

The mask used to clear the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR field value from a register.

#define ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_RSTMGR_RAMSTAT_MPUL1RAMCLR register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_LSB   17

The Least Significant Bit (LSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_MSB   17

The Most Significant Bit (MSB) position of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_WIDTH   1

The width in bits of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET_MSK   0x00020000

The mask used to set the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_CLR_MSK   0xfffdffff

The mask used to clear the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_RESET   0x0

The reset value of the ALT_RSTMGR_RAMSTAT_MPUL1TMO register field.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_RSTMGR_RAMSTAT_MPUL1TMO field value from a register.

#define ALT_RSTMGR_RAMSTAT_MPUL1TMO_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_RSTMGR_RAMSTAT_MPUL1TMO register field value suitable for setting the register.

#define ALT_RSTMGR_RAMSTAT_RESET   0x00000000

The reset value of the ALT_RSTMGR_RAMSTAT register.

#define ALT_RSTMGR_RAMSTAT_OFST   0x4

The byte offset of the ALT_RSTMGR_RAMSTAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_RAMSTAT.