Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Source Register - src

Description

Contains register field to choose between software state machine (vioctrl array index [1] register) or hardware state machine in the Freeze Controller as the freeze signal source for VIO channel 1.

All fields are only reset by a cold reset (ignore warm reset).

Register Layout

Bits Access Reset Description
[0] RW 0x0 VIO1 Freeze Signal Source
[31:1] ??? 0x0 UNDEFINED

Field : VIO1 Freeze Signal Source - vio1

The freeze signal source for VIO channel 1 (VIO bank 2 and bank 3).

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW 0x0 VIO1 freeze signals are driven by software
: writing to the VIOCTRL[1] register. The
: VIO1-related fields in the hwctrl register are
: active but don't effect the VIO1 freeze signals.
ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW 0x1 VIO1 freeze signals are driven by the hardware
: state machine in the Freeze Controller. The
: VIO1-related fields in the hwctrl register are
: active and effect the VIO1 freeze signals.

Field Access Macros:

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW   0x0
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW   0x1
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB   0
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB   0
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH   1
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK   0x00000001
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET   0x0
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET(value)   (((value) << 0) & 0x00000001)
 

Data Structures

struct  ALT_SYSMGR_FRZCTL_SRC_s
 

Macros

#define ALT_SYSMGR_FRZCTL_SRC_OFST   0x14
 

Typedefs

typedef struct
ALT_SYSMGR_FRZCTL_SRC_s 
ALT_SYSMGR_FRZCTL_SRC_t
 

Data Structure Documentation

struct ALT_SYSMGR_FRZCTL_SRC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_FRZCTL_SRC.

Data Fields
uint32_t vio1: 1 VIO1 Freeze Signal Source
uint32_t __pad0__: 31 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_SW   0x0

Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1

VIO1 freeze signals are driven by software writing to the VIOCTRL[1] register. The VIO1-related fields in the hwctrl register are active but don't effect the VIO1 freeze signals.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_E_HW   0x1

Enumerated value for register field ALT_SYSMGR_FRZCTL_SRC_VIO1

VIO1 freeze signals are driven by the hardware state machine in the Freeze Controller. The VIO1-related fields in the hwctrl register are active and effect the VIO1 freeze signals.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_WIDTH   1

The width in bits of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_RESET   0x0

The reset value of the ALT_SYSMGR_FRZCTL_SRC_VIO1 register field.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_FRZCTL_SRC_VIO1 field value from a register.

#define ALT_SYSMGR_FRZCTL_SRC_VIO1_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_FRZCTL_SRC_VIO1 register field value suitable for setting the register.

#define ALT_SYSMGR_FRZCTL_SRC_OFST   0x14

The byte offset of the ALT_SYSMGR_FRZCTL_SRC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_FRZCTL_SRC.