Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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The Watchdog Timer Manager API

Description

This module defines the Watchdog Timer Manager API for accessing, configuring, and controlling the HPS Watchdog Timer resources.

A typical initialization might be:

ALT_STATUS_CODE ret;
ret = alt_wdog_int_clear(ALT_CPU_WATCHDOG);
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_counter_set(ALT_CPU_WATCHDOG, 0x7FFFFFFF); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_core_prescaler_set(0x80); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_response_mode_set(ALT_CPU_WATCHDOG, ALT_WDOG_TIMER_MODE_FREERUN); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_int_enable(ALT_CPU_WATCHDOG); }
if (ret == ALT_E_SUCCESS) {ret = alt_wdog_start(ALT_CPU_WATCHDOG); }

Then periodically (before it runs out) call this function to restart the watchdog:

alt_wdog_reset(ALT_CPU_WATCHDOG);

If the interrupt is enabled in the interrupt manager and is triggered, it can be cleared like this:

alt_wdog_int_clear(ALT_CPU_WATCHDOG);

If the interrupt is not enabled in the interrupt manager, you can still poll to see if it hit zero and clear any pending interrupts like this:

alt_wdog_int_if_pending_clear(ALT_CPU_WATCHDOG);

Members

 Watchdog Timer Enable, Disable, Restart, Status
 
 Watchdog Timer Counter Configuration
 
 Watchdog Timer Interrupt Management
 
 Watchdog Timer Miscellaneous Configuration
 

Typedefs

typedef enum ALT_WDOG_TIMER_e ALT_WDOG_TIMER_t
 
typedef enum ALT_WDOG_TIMEOUT_e ALT_WDOG_TIMEOUT_t
 
typedef enum ALT_WDOG_RESET_TYPE_e ALT_WDOG_RESET_TYPE_t
 

ENUMS

enum  ALT_WDOG_TIMER_e {
  ALT_WDOG_CPU, ALT_WDOG0, ALT_WDOG1, ALT_WDOG0_INIT,
  ALT_WDOG1_INIT
}
 
enum  ALT_WDOG_TIMEOUT_e {
  ALT_WDOG_TIMEOUT64K, ALT_WDOG_TIMEOUT128K, ALT_WDOG_TIMEOUT256K, ALT_WDOG_TIMEOUT512K,
  ALT_WDOG_TIMEOUT1M, ALT_WDOG_TIMEOUT2M, ALT_WDOG_TIMEOUT4M, ALT_WDOG_TIMEOUT8M,
  ALT_WDOG_TIMEOUT16M, ALT_WDOG_TIMEOUT32M, ALT_WDOG_TIMEOUT64M, ALT_WDOG_TIMEOUT128M,
  ALT_WDOG_TIMEOUT256M, ALT_WDOG_TIMEOUT512M, ALT_WDOG_TIMEOUT1G, ALT_WDOG_TIMEOUT2G
}
 
enum  ALT_WDOG_RESET_TYPE_e { ALT_WDOG_WARM_RESET, ALT_WDOG_INT_THEN_RESET, ALT_WDOG_TIMER_MODE_ONESHOT, ALT_WDOG_TIMER_MODE_FREERUN }
 

Typedef Documentation

This type definition enumerates the names of the timers managed by the Watchdog Timers Manager.

This type definition enumerates the encoded countdown values that ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL can be set to use.

This type definition enumerates the reset types that the watchdog timers can be set to trigger.

Enumeration Type Documentation

This type definition enumerates the names of the timers managed by the Watchdog Timers Manager.

Enumerator:
ALT_WDOG_CPU 

ALT_CPU_WATCHDOG - Each CPU core has its own watchdog timer, which is clocked by PERIPHCLK. Can be loaded with any 32-bit counter value, not limited to powers of two, and it has an 8-bit prescaler. This timer also has a pause-enable input that can allow other HW to freeze the countdown.

ALT_WDOG0 

watchdog_timer0 - Connected to the L4_OSC1 bus clocked by osc1_clk. Counter values are limited to powers of two between 15 and 31 and there is no prescaler.

ALT_WDOG1 

watchdog_timer1 - Connected to the L4_OSC1 bus clocked by osc1_clk. Counter values are limited to powers of two between 15 and 31 and there is no prescaler.

ALT_WDOG0_INIT 

watchdog_init_timer0 - This is for the initial timout only (not necessarily immediately after system restart), watchdog_timer0 is then used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked by osc1_clk. Counter values are limited to powers of two between 15 and 31 and there is no prescaler.

ALT_WDOG1_INIT 

watchdog_init_timer1 - This is for the initial timout only (not necessarily immediately after system restart), watchdog_timer1 is then used for all subsequent timeouts. Connected to the L4_OSC1 bus clocked by osc1_clk. Counter values are limited to powers of two between 15 and 31 and there is no prescaler.

This type definition enumerates the encoded countdown values that ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL can be set to use.

Enumerator:
ALT_WDOG_TIMEOUT64K 

ALT_WDOG_TIMEOUT64K - Timeout = 65,536 osc1_clk periods.

ALT_WDOG_TIMEOUT128K 

ALT_WDOG_TIMEOUT128K - Timeout = 131,072 osc1_clk periods.

ALT_WDOG_TIMEOUT256K 

ALT_WDOG_TIMEOUT256K - Timeout = 262,144 osc1_clk periods.

ALT_WDOG_TIMEOUT512K 

ALT_WDOG_TIMEOUT512K - Timeout = 524,288 osc1_clk periods.

ALT_WDOG_TIMEOUT1M 

ALT_WDOG_TIMEOUT1M - Timeout = 1,048,576 osc1_clk periods.

ALT_WDOG_TIMEOUT2M 

ALT_WDOG_TIMEOUT2M - Timeout = 2,097,152 osc1_clk periods.

ALT_WDOG_TIMEOUT4M 

ALT_WDOG_TIMEOUT4M - Timeout = 4,194,304 osc1_clk periods.

ALT_WDOG_TIMEOUT8M 

ALT_WDOG_TIMEOUT8M - Timeout = 8,388,608 osc1_clk periods.

ALT_WDOG_TIMEOUT16M 

ALT_WDOG_TIMEOUT16M - Timeout = 16,777,216 osc1_clk periods.

ALT_WDOG_TIMEOUT32M 

ALT_WDOG_TIMEOUT32M - Timeout = 33,554,432 osc1_clk periods.

ALT_WDOG_TIMEOUT64M 

ALT_WDOG_TIMEOUT64M - Timeout = 67,108,864 osc1_clk periods.

ALT_WDOG_TIMEOUT128M 

ALT_WDOG_TIMEOUT128M - Timeout = 134,217,728 osc1_clk periods.

ALT_WDOG_TIMEOUT256M 

ALT_WDOG_TIMEOUT256M - Timeout = 268,435,456 osc1_clk periods.

ALT_WDOG_TIMEOUT512M 

ALT_WDOG_TIMEOUT512M - Timeout = 536,870,912 osc1_clk periods.

ALT_WDOG_TIMEOUT1G 

ALT_WDOG_TIMEOUT1G - Timeout = 1,073,741,824 osc1_clk periods.

ALT_WDOG_TIMEOUT2G 

ALT_WDOG_TIMEOUT2G - Timeout = 2,147,483,648 osc1_clk periods.

This type definition enumerates the reset types that the watchdog timers can be set to trigger.

Enumerator:
ALT_WDOG_WARM_RESET 

Reset - For ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL, if the counter reaches zero without being reset, generate a system-wide warm reset request. This is the default mode out of reset.
For ALT_CPU_WATCHDOG, no interrupt is triggered and a reset request is asserted. The response to the reset request is set in the reset controller block and may not automatically trigger a system reset.

ALT_WDOG_INT_THEN_RESET 

Interrupt_First - When the counter reaches zero without being reset, generate an interrupt. For ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL, if the interrupt is not cleared by the time a second timeout occurs, then generate a system warm reset request.
For ALT_CPU_WATCHDOG, the interrupt is triggered and a WDRESETREQ reset request is asserted. The response to the interrupt and the reset request is set in the interrupt and reset controller blocks and may not automatically trigger a system reset.

ALT_WDOG_TIMER_MODE_ONESHOT 

Timer_mode_oneshot - The ALT_CPU_WATCHDOG timer has the capability to not only operate as a watchdog timer, but also to operate as a general-purpose countdown timer. This selection specifies the ALT_CPU_WATCHDOG runs in one-shot timer mode, and can optionally trigger an interrupt when the counter reaches zero without being reset. This is the default selection for ALT_CPU_WATCHDOG out of reset.
This selection has no meaning for ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL.

ALT_WDOG_TIMER_MODE_FREERUN 

Timer_mode_freerun - The ALT_CPU_WATCHDOG timer has the capability to not only operate as a watchdog timer, but also to operate as a general-purpose countdown timer. This selection specifies the ALT_CPU_WATCHDOG in free-run or wraparound timer mode, and can optionally trigger an interrupt when the counter reaches zero without being reset.
This selection has no meaning for ALT_WATCHDOG0, ALT_WATCHDOG1, ALT_WATCHDOG0_INITIAL, and ALT_WATCHDOG1_INITIAL.