Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Global Disable Register - gbl

Description

Used to disable all interfaces between the FPGA and HPS.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Global Interface
[31:1] ??? 0x0 UNDEFINED

Field : Global Interface - intf

Used to disable all interfaces between the FPGA and HPS. Software must ensure that all interfaces between the FPGA and HPS are inactive before disabling them.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS 0x0 All interfaces between FPGA and HPS are
: disabled.
ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN 0x1 Interfaces between FPGA and HPS are not all
: disabled. Interfaces can be indivdually disabled
: by putting the HPS module associated with the
: interface in reset using registers in the Reset
: Manager or by using registers in this register
: group of the System Manager for interfaces
: without an associated module.

Field Access Macros:

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS   0x0
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN   0x1
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB   0
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB   0
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH   1
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK   0x00000001
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET   0x1
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET(value)   (((value) << 0) & 0x00000001)
 

Data Structures

struct  ALT_SYSMGR_FPGAINTF_GBL_s
 

Macros

#define ALT_SYSMGR_FPGAINTF_GBL_OFST   0x0
 

Typedefs

typedef struct
ALT_SYSMGR_FPGAINTF_GBL_s 
ALT_SYSMGR_FPGAINTF_GBL_t
 

Data Structure Documentation

struct ALT_SYSMGR_FPGAINTF_GBL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_FPGAINTF_GBL.

Data Fields
uint32_t intf: 1 Global Interface
uint32_t __pad0__: 31 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_DIS   0x0

Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF

All interfaces between FPGA and HPS are disabled.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_E_EN   0x1

Enumerated value for register field ALT_SYSMGR_FPGAINTF_GBL_INTF

Interfaces between FPGA and HPS are not all disabled. Interfaces can be indivdually disabled by putting the HPS module associated with the interface in reset using registers in the Reset Manager or by using registers in this register group of the System Manager for interfaces without an associated module.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_WIDTH   1

The width in bits of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_FPGAINTF_GBL_INTF register field value.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_RESET   0x1

The reset value of the ALT_SYSMGR_FPGAINTF_GBL_INTF register field.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_FPGAINTF_GBL_INTF field value from a register.

#define ALT_SYSMGR_FPGAINTF_GBL_INTF_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_FPGAINTF_GBL_INTF register field value suitable for setting the register.

#define ALT_SYSMGR_FPGAINTF_GBL_OFST   0x0

The byte offset of the ALT_SYSMGR_FPGAINTF_GBL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_FPGAINTF_GBL.