Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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alt_ecc_sdmmc.h
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32 
35 #ifndef __ALT_SOCAL_ECC_SDMMC_H__
36 #define __ALT_SOCAL_ECC_SDMMC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
74 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_LSB 0
75 
76 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_MSB 15
77 
78 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_WIDTH 16
79 
80 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 
82 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 
84 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_RESET 0x0
85 
86 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 
88 #define ALT_ECC_SDMMC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 
102 {
103  const uint32_t SIREV : 16;
104  uint32_t : 16;
105 };
106 
109 #endif /* __ASSEMBLY__ */
110 
112 #define ALT_ECC_SDMMC_IP_REV_ID_RESET 0x00000000
113 
114 #define ALT_ECC_SDMMC_IP_REV_ID_OFST 0x0
115 
145 #define ALT_ECC_SDMMC_CTL_ECC_EN_LSB 0
146 
147 #define ALT_ECC_SDMMC_CTL_ECC_EN_MSB 0
148 
149 #define ALT_ECC_SDMMC_CTL_ECC_EN_WIDTH 1
150 
151 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET_MSK 0x00000001
152 
153 #define ALT_ECC_SDMMC_CTL_ECC_EN_CLR_MSK 0xfffffffe
154 
155 #define ALT_ECC_SDMMC_CTL_ECC_EN_RESET 0x0
156 
157 #define ALT_ECC_SDMMC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
158 
159 #define ALT_ECC_SDMMC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
160 
170 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_LSB 8
171 
172 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_MSB 8
173 
174 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_WIDTH 1
175 
176 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET_MSK 0x00000100
177 
178 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
179 
180 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_RESET 0x0
181 
182 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
183 
184 #define ALT_ECC_SDMMC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
185 
195 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_LSB 9
196 
197 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_MSB 9
198 
199 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_WIDTH 1
200 
201 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET_MSK 0x00000200
202 
203 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_CLR_MSK 0xfffffdff
204 
205 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_RESET 0x0
206 
207 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_GET(value) (((value) & 0x00000200) >> 9)
208 
209 #define ALT_ECC_SDMMC_CTL_CNT_RSTB_SET(value) (((value) << 9) & 0x00000200)
210 
220 #define ALT_ECC_SDMMC_CTL_INITA_LSB 16
221 
222 #define ALT_ECC_SDMMC_CTL_INITA_MSB 16
223 
224 #define ALT_ECC_SDMMC_CTL_INITA_WIDTH 1
225 
226 #define ALT_ECC_SDMMC_CTL_INITA_SET_MSK 0x00010000
227 
228 #define ALT_ECC_SDMMC_CTL_INITA_CLR_MSK 0xfffeffff
229 
230 #define ALT_ECC_SDMMC_CTL_INITA_RESET 0x0
231 
232 #define ALT_ECC_SDMMC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
233 
234 #define ALT_ECC_SDMMC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
235 
245 #define ALT_ECC_SDMMC_CTL_INITB_LSB 24
246 
247 #define ALT_ECC_SDMMC_CTL_INITB_MSB 24
248 
249 #define ALT_ECC_SDMMC_CTL_INITB_WIDTH 1
250 
251 #define ALT_ECC_SDMMC_CTL_INITB_SET_MSK 0x01000000
252 
253 #define ALT_ECC_SDMMC_CTL_INITB_CLR_MSK 0xfeffffff
254 
255 #define ALT_ECC_SDMMC_CTL_INITB_RESET 0x0
256 
257 #define ALT_ECC_SDMMC_CTL_INITB_GET(value) (((value) & 0x01000000) >> 24)
258 
259 #define ALT_ECC_SDMMC_CTL_INITB_SET(value) (((value) << 24) & 0x01000000)
260 
261 #ifndef __ASSEMBLY__
262 
273 {
274  uint32_t ECC_EN : 1;
275  uint32_t : 7;
276  uint32_t CNT_RSTA : 1;
277  uint32_t CNT_RSTB : 1;
278  uint32_t : 6;
279  uint32_t INITA : 1;
280  uint32_t : 7;
281  uint32_t INITB : 1;
282  uint32_t : 7;
283 };
284 
286 typedef volatile struct ALT_ECC_SDMMC_CTL_s ALT_ECC_SDMMC_CTL_t;
287 #endif /* __ASSEMBLY__ */
288 
290 #define ALT_ECC_SDMMC_CTL_RESET 0x00000000
291 
292 #define ALT_ECC_SDMMC_CTL_OFST 0x8
293 
319 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_LSB 0
320 
321 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_MSB 0
322 
323 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_WIDTH 1
324 
325 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
326 
327 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
328 
329 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_RESET 0x0
330 
331 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
332 
333 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
334 
345 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_LSB 8
346 
347 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_MSB 8
348 
349 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_WIDTH 1
350 
351 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET_MSK 0x00000100
352 
353 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_CLR_MSK 0xfffffeff
354 
355 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_RESET 0x0
356 
357 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_GET(value) (((value) & 0x00000100) >> 8)
358 
359 #define ALT_ECC_SDMMC_INITSTAT_INITCOMPLETEB_SET(value) (((value) << 8) & 0x00000100)
360 
361 #ifndef __ASSEMBLY__
362 
373 {
374  uint32_t INITCOMPLETEA : 1;
375  uint32_t : 7;
376  uint32_t INITCOMPLETEB : 1;
377  uint32_t : 23;
378 };
379 
382 #endif /* __ASSEMBLY__ */
383 
385 #define ALT_ECC_SDMMC_INITSTAT_RESET 0x00000000
386 
387 #define ALT_ECC_SDMMC_INITSTAT_OFST 0xc
388 
411 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_LSB 0
412 
413 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_MSB 0
414 
415 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_WIDTH 1
416 
417 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
418 
419 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
420 
421 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_RESET 0x0
422 
423 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
424 
425 #define ALT_ECC_SDMMC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
426 
427 #ifndef __ASSEMBLY__
428 
439 {
440  uint32_t SERRINTEN : 1;
441  uint32_t : 31;
442 };
443 
446 #endif /* __ASSEMBLY__ */
447 
449 #define ALT_ECC_SDMMC_ERRINTEN_RESET 0x00000000
450 
451 #define ALT_ECC_SDMMC_ERRINTEN_OFST 0x10
452 
475 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_LSB 0
476 
477 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_MSB 0
478 
479 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_WIDTH 1
480 
481 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
482 
483 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
484 
485 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_RESET 0x0
486 
487 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
488 
489 #define ALT_ECC_SDMMC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
490 
491 #ifndef __ASSEMBLY__
492 
503 {
504  uint32_t SERRINTS : 1;
505  uint32_t : 31;
506 };
507 
510 #endif /* __ASSEMBLY__ */
511 
513 #define ALT_ECC_SDMMC_ERRINTENS_RESET 0x00000000
514 
515 #define ALT_ECC_SDMMC_ERRINTENS_OFST 0x14
516 
546 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_LSB 0
547 
548 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_MSB 0
549 
550 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_WIDTH 1
551 
552 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
553 
554 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
555 
556 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_RESET 0x0
557 
558 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
559 
560 #define ALT_ECC_SDMMC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
561 
562 #ifndef __ASSEMBLY__
563 
574 {
575  uint32_t SERRINTR : 1;
576  uint32_t : 31;
577 };
578 
581 #endif /* __ASSEMBLY__ */
582 
584 #define ALT_ECC_SDMMC_ERRINTENR_RESET 0x00000000
585 
586 #define ALT_ECC_SDMMC_ERRINTENR_OFST 0x18
587 
614 #define ALT_ECC_SDMMC_INTMOD_INTMOD_LSB 0
615 
616 #define ALT_ECC_SDMMC_INTMOD_INTMOD_MSB 0
617 
618 #define ALT_ECC_SDMMC_INTMOD_INTMOD_WIDTH 1
619 
620 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET_MSK 0x00000001
621 
622 #define ALT_ECC_SDMMC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
623 
624 #define ALT_ECC_SDMMC_INTMOD_INTMOD_RESET 0x0
625 
626 #define ALT_ECC_SDMMC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
627 
628 #define ALT_ECC_SDMMC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
629 
639 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_LSB 8
640 
641 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_MSB 8
642 
643 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_WIDTH 1
644 
645 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET_MSK 0x00000100
646 
647 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
648 
649 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_RESET 0x0
650 
651 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
652 
653 #define ALT_ECC_SDMMC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
654 
664 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_LSB 16
665 
666 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_MSB 16
667 
668 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_WIDTH 1
669 
670 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET_MSK 0x00010000
671 
672 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
673 
674 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_RESET 0x0
675 
676 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
677 
678 #define ALT_ECC_SDMMC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
679 
680 #ifndef __ASSEMBLY__
681 
692 {
693  uint32_t INTMODE : 1;
694  uint32_t : 7;
695  uint32_t INTONOVF : 1;
696  uint32_t : 7;
697  uint32_t INTONCMP : 1;
698  uint32_t : 15;
699 };
700 
703 #endif /* __ASSEMBLY__ */
704 
706 #define ALT_ECC_SDMMC_INTMOD_RESET 0x00000000
707 
708 #define ALT_ECC_SDMMC_INTMOD_OFST 0x1c
709 
740 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_LSB 0
741 
742 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_MSB 0
743 
744 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_WIDTH 1
745 
746 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET_MSK 0x00000001
747 
748 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
749 
750 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_RESET 0x0
751 
752 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
753 
754 #define ALT_ECC_SDMMC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
755 
765 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_LSB 8
766 
767 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_MSB 8
768 
769 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_WIDTH 1
770 
771 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET_MSK 0x00000100
772 
773 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
774 
775 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_RESET 0x0
776 
777 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
778 
779 #define ALT_ECC_SDMMC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
780 
790 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_LSB 16
791 
792 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_MSB 16
793 
794 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_WIDTH 1
795 
796 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET_MSK 0x00010000
797 
798 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_CLR_MSK 0xfffeffff
799 
800 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_RESET 0x0
801 
802 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_GET(value) (((value) & 0x00010000) >> 16)
803 
804 #define ALT_ECC_SDMMC_INTSTAT_SERRPENB_SET(value) (((value) << 16) & 0x00010000)
805 
815 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_LSB 24
816 
817 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_MSB 24
818 
819 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_WIDTH 1
820 
821 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET_MSK 0x01000000
822 
823 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_CLR_MSK 0xfeffffff
824 
825 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_RESET 0x0
826 
827 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_GET(value) (((value) & 0x01000000) >> 24)
828 
829 #define ALT_ECC_SDMMC_INTSTAT_DERRPENB_SET(value) (((value) << 24) & 0x01000000)
830 
831 #ifndef __ASSEMBLY__
832 
843 {
844  uint32_t SERRPENA : 1;
845  uint32_t : 7;
846  uint32_t DERRPENA : 1;
847  uint32_t : 7;
848  uint32_t SERRPENB : 1;
849  uint32_t : 7;
850  uint32_t DERRPENB : 1;
851  uint32_t : 7;
852 };
853 
856 #endif /* __ASSEMBLY__ */
857 
859 #define ALT_ECC_SDMMC_INTSTAT_RESET 0x00000000
860 
861 #define ALT_ECC_SDMMC_INTSTAT_OFST 0x20
862 
891 #define ALT_ECC_SDMMC_INTTEST_TSERRA_LSB 0
892 
893 #define ALT_ECC_SDMMC_INTTEST_TSERRA_MSB 0
894 
895 #define ALT_ECC_SDMMC_INTTEST_TSERRA_WIDTH 1
896 
897 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET_MSK 0x00000001
898 
899 #define ALT_ECC_SDMMC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
900 
901 #define ALT_ECC_SDMMC_INTTEST_TSERRA_RESET 0x0
902 
903 #define ALT_ECC_SDMMC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
904 
905 #define ALT_ECC_SDMMC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
906 
916 #define ALT_ECC_SDMMC_INTTEST_TDERRA_LSB 8
917 
918 #define ALT_ECC_SDMMC_INTTEST_TDERRA_MSB 8
919 
920 #define ALT_ECC_SDMMC_INTTEST_TDERRA_WIDTH 1
921 
922 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET_MSK 0x00000100
923 
924 #define ALT_ECC_SDMMC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
925 
926 #define ALT_ECC_SDMMC_INTTEST_TDERRA_RESET 0x0
927 
928 #define ALT_ECC_SDMMC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
929 
930 #define ALT_ECC_SDMMC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
931 
941 #define ALT_ECC_SDMMC_INTTEST_TSERRB_LSB 16
942 
943 #define ALT_ECC_SDMMC_INTTEST_TSERRB_MSB 16
944 
945 #define ALT_ECC_SDMMC_INTTEST_TSERRB_WIDTH 1
946 
947 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET_MSK 0x00010000
948 
949 #define ALT_ECC_SDMMC_INTTEST_TSERRB_CLR_MSK 0xfffeffff
950 
951 #define ALT_ECC_SDMMC_INTTEST_TSERRB_RESET 0x0
952 
953 #define ALT_ECC_SDMMC_INTTEST_TSERRB_GET(value) (((value) & 0x00010000) >> 16)
954 
955 #define ALT_ECC_SDMMC_INTTEST_TSERRB_SET(value) (((value) << 16) & 0x00010000)
956 
966 #define ALT_ECC_SDMMC_INTTEST_TDERRB_LSB 24
967 
968 #define ALT_ECC_SDMMC_INTTEST_TDERRB_MSB 24
969 
970 #define ALT_ECC_SDMMC_INTTEST_TDERRB_WIDTH 1
971 
972 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET_MSK 0x01000000
973 
974 #define ALT_ECC_SDMMC_INTTEST_TDERRB_CLR_MSK 0xfeffffff
975 
976 #define ALT_ECC_SDMMC_INTTEST_TDERRB_RESET 0x0
977 
978 #define ALT_ECC_SDMMC_INTTEST_TDERRB_GET(value) (((value) & 0x01000000) >> 24)
979 
980 #define ALT_ECC_SDMMC_INTTEST_TDERRB_SET(value) (((value) << 24) & 0x01000000)
981 
982 #ifndef __ASSEMBLY__
983 
994 {
995  uint32_t TSERRA : 1;
996  uint32_t : 7;
997  uint32_t TDERRA : 1;
998  uint32_t : 7;
999  uint32_t TSERRB : 1;
1000  uint32_t : 7;
1001  uint32_t TDERRB : 1;
1002  uint32_t : 7;
1003 };
1004 
1007 #endif /* __ASSEMBLY__ */
1008 
1010 #define ALT_ECC_SDMMC_INTTEST_RESET 0x00000000
1011 
1012 #define ALT_ECC_SDMMC_INTTEST_OFST 0x24
1013 
1037 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_LSB 0
1038 
1039 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_MSB 0
1040 
1041 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_WIDTH 1
1042 
1043 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
1044 
1045 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
1046 
1047 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_RESET 0x0
1048 
1049 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
1050 
1051 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
1052 
1062 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_LSB 1
1063 
1064 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_MSB 1
1065 
1066 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_WIDTH 1
1067 
1068 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET_MSK 0x00000002
1069 
1070 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_CLR_MSK 0xfffffffd
1071 
1072 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_RESET 0x0
1073 
1074 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_GET(value) (((value) & 0x00000002) >> 1)
1075 
1076 #define ALT_ECC_SDMMC_MODSTAT_CMPFLGB_SET(value) (((value) << 1) & 0x00000002)
1077 
1078 #ifndef __ASSEMBLY__
1079 
1090 {
1091  uint32_t CMPFLGA : 1;
1092  uint32_t CMPFLGB : 1;
1093  uint32_t : 30;
1094 };
1095 
1098 #endif /* __ASSEMBLY__ */
1099 
1101 #define ALT_ECC_SDMMC_MODSTAT_RESET 0x00000000
1102 
1103 #define ALT_ECC_SDMMC_MODSTAT_OFST 0x28
1104 
1128 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_LSB 0
1129 
1130 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_MSB 9
1131 
1132 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_WIDTH 10
1133 
1134 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET_MSK 0x000003ff
1135 
1136 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
1137 
1138 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_RESET 0x0
1139 
1140 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1141 
1142 #define ALT_ECC_SDMMC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1143 
1144 #ifndef __ASSEMBLY__
1145 
1156 {
1157  uint32_t Address : 10;
1158  uint32_t : 22;
1159 };
1160 
1163 #endif /* __ASSEMBLY__ */
1164 
1166 #define ALT_ECC_SDMMC_DERRADDRA_RESET 0x00000000
1167 
1168 #define ALT_ECC_SDMMC_DERRADDRA_OFST 0x2c
1169 
1193 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_LSB 0
1194 
1195 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_MSB 9
1196 
1197 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_WIDTH 10
1198 
1199 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET_MSK 0x000003ff
1200 
1201 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
1202 
1203 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_RESET 0x0
1204 
1205 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1206 
1207 #define ALT_ECC_SDMMC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1208 
1209 #ifndef __ASSEMBLY__
1210 
1221 {
1222  uint32_t Address : 10;
1223  uint32_t : 22;
1224 };
1225 
1228 #endif /* __ASSEMBLY__ */
1229 
1231 #define ALT_ECC_SDMMC_SERRADDRA_RESET 0x00000000
1232 
1233 #define ALT_ECC_SDMMC_SERRADDRA_OFST 0x30
1234 
1258 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_LSB 0
1259 
1260 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_MSB 9
1261 
1262 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_WIDTH 10
1263 
1264 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET_MSK 0x000003ff
1265 
1266 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_CLR_MSK 0xfffffc00
1267 
1268 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_RESET 0x0
1269 
1270 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1271 
1272 #define ALT_ECC_SDMMC_DERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1273 
1274 #ifndef __ASSEMBLY__
1275 
1286 {
1287  uint32_t Address : 10;
1288  uint32_t : 22;
1289 };
1290 
1293 #endif /* __ASSEMBLY__ */
1294 
1296 #define ALT_ECC_SDMMC_DERRADDRB_RESET 0x00000000
1297 
1298 #define ALT_ECC_SDMMC_DERRADDRB_OFST 0x34
1299 
1323 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_LSB 0
1324 
1325 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_MSB 9
1326 
1327 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_WIDTH 10
1328 
1329 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET_MSK 0x000003ff
1330 
1331 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_CLR_MSK 0xfffffc00
1332 
1333 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_RESET 0x0
1334 
1335 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
1336 
1337 #define ALT_ECC_SDMMC_SERRADDRB_ADDR_SET(value) (((value) << 0) & 0x000003ff)
1338 
1339 #ifndef __ASSEMBLY__
1340 
1351 {
1352  uint32_t Address : 10;
1353  uint32_t : 22;
1354 };
1355 
1358 #endif /* __ASSEMBLY__ */
1359 
1361 #define ALT_ECC_SDMMC_SERRADDRB_RESET 0x00000000
1362 
1363 #define ALT_ECC_SDMMC_SERRADDRB_OFST 0x38
1364 
1386 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_LSB 0
1387 
1388 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_MSB 31
1389 
1390 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_WIDTH 32
1391 
1392 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1393 
1394 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1395 
1396 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_RESET 0x0
1397 
1398 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1399 
1400 #define ALT_ECC_SDMMC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1401 
1402 #ifndef __ASSEMBLY__
1403 
1414 {
1415  uint32_t SERRCNT : 32;
1416 };
1417 
1420 #endif /* __ASSEMBLY__ */
1421 
1423 #define ALT_ECC_SDMMC_SERRCNTREG_RESET 0x00000000
1424 
1425 #define ALT_ECC_SDMMC_SERRCNTREG_OFST 0x3c
1426 
1450 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_LSB 0
1451 
1452 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_MSB 9
1453 
1454 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1455 
1456 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1457 
1458 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1459 
1460 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1461 
1462 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1463 
1464 #define ALT_ECC_SDMMC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1465 
1466 #ifndef __ASSEMBLY__
1467 
1478 {
1479  uint32_t ECC_AddrBUS : 10;
1480  uint32_t : 22;
1481 };
1482 
1485 #endif /* __ASSEMBLY__ */
1486 
1488 #define ALT_ECC_SDMMC_ADDRBUS_RESET 0x00000000
1489 
1490 #define ALT_ECC_SDMMC_ADDRBUS_OFST 0x40
1491 
1492 #define ALT_ECC_SDMMC_ADDRBUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ADDRBUS_OFST))
1493 
1515 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_LSB 0
1516 
1517 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_MSB 31
1518 
1519 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1520 
1521 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1522 
1523 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1524 
1525 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1526 
1527 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1528 
1529 #define ALT_ECC_SDMMC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1530 
1531 #ifndef __ASSEMBLY__
1532 
1543 {
1544  uint32_t ECC_RDataBUS : 32;
1545 };
1546 
1549 #endif /* __ASSEMBLY__ */
1550 
1552 #define ALT_ECC_SDMMC_RDATA0BUS_RESET 0x00000000
1553 
1554 #define ALT_ECC_SDMMC_RDATA0BUS_OFST 0x44
1555 
1556 #define ALT_ECC_SDMMC_RDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA0BUS_OFST))
1557 
1579 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_LSB 0
1580 
1581 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_MSB 31
1582 
1583 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1584 
1585 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1586 
1587 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1588 
1589 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1590 
1591 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1592 
1593 #define ALT_ECC_SDMMC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1594 
1595 #ifndef __ASSEMBLY__
1596 
1607 {
1608  uint32_t ECC_RDataBUS : 32;
1609 };
1610 
1613 #endif /* __ASSEMBLY__ */
1614 
1616 #define ALT_ECC_SDMMC_RDATA1BUS_RESET 0x00000000
1617 
1618 #define ALT_ECC_SDMMC_RDATA1BUS_OFST 0x48
1619 
1620 #define ALT_ECC_SDMMC_RDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA1BUS_OFST))
1621 
1643 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_LSB 0
1644 
1645 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_MSB 31
1646 
1647 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1648 
1649 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1650 
1651 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1652 
1653 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1654 
1655 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1656 
1657 #define ALT_ECC_SDMMC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1658 
1659 #ifndef __ASSEMBLY__
1660 
1671 {
1672  uint32_t ECC_RDataBUS : 32;
1673 };
1674 
1677 #endif /* __ASSEMBLY__ */
1678 
1680 #define ALT_ECC_SDMMC_RDATA2BUS_RESET 0x00000000
1681 
1682 #define ALT_ECC_SDMMC_RDATA2BUS_OFST 0x4c
1683 
1684 #define ALT_ECC_SDMMC_RDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA2BUS_OFST))
1685 
1707 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_LSB 0
1708 
1709 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_MSB 31
1710 
1711 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1712 
1713 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1714 
1715 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1716 
1717 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1718 
1719 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1720 
1721 #define ALT_ECC_SDMMC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1722 
1723 #ifndef __ASSEMBLY__
1724 
1735 {
1736  uint32_t ECC_RDataBUS : 32;
1737 };
1738 
1741 #endif /* __ASSEMBLY__ */
1742 
1744 #define ALT_ECC_SDMMC_RDATA3BUS_RESET 0x00000000
1745 
1746 #define ALT_ECC_SDMMC_RDATA3BUS_OFST 0x50
1747 
1748 #define ALT_ECC_SDMMC_RDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATA3BUS_OFST))
1749 
1771 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_LSB 0
1772 
1773 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_MSB 31
1774 
1775 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1776 
1777 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1778 
1779 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1780 
1781 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1782 
1783 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1784 
1785 #define ALT_ECC_SDMMC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1786 
1787 #ifndef __ASSEMBLY__
1788 
1799 {
1800  uint32_t ECC_WDataBUS : 32;
1801 };
1802 
1805 #endif /* __ASSEMBLY__ */
1806 
1808 #define ALT_ECC_SDMMC_WDATA0BUS_RESET 0x00000000
1809 
1810 #define ALT_ECC_SDMMC_WDATA0BUS_OFST 0x54
1811 
1812 #define ALT_ECC_SDMMC_WDATA0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA0BUS_OFST))
1813 
1835 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_LSB 0
1836 
1837 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_MSB 31
1838 
1839 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1840 
1841 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1842 
1843 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1844 
1845 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1846 
1847 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1848 
1849 #define ALT_ECC_SDMMC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1850 
1851 #ifndef __ASSEMBLY__
1852 
1863 {
1864  uint32_t ECC_WDataBUS : 32;
1865 };
1866 
1869 #endif /* __ASSEMBLY__ */
1870 
1872 #define ALT_ECC_SDMMC_WDATA1BUS_RESET 0x00000000
1873 
1874 #define ALT_ECC_SDMMC_WDATA1BUS_OFST 0x58
1875 
1876 #define ALT_ECC_SDMMC_WDATA1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA1BUS_OFST))
1877 
1899 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_LSB 0
1900 
1901 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_MSB 31
1902 
1903 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1904 
1905 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1906 
1907 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1908 
1909 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1910 
1911 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1912 
1913 #define ALT_ECC_SDMMC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1914 
1915 #ifndef __ASSEMBLY__
1916 
1927 {
1928  uint32_t ECC_WDataBUS : 32;
1929 };
1930 
1933 #endif /* __ASSEMBLY__ */
1934 
1936 #define ALT_ECC_SDMMC_WDATA2BUS_RESET 0x00000000
1937 
1938 #define ALT_ECC_SDMMC_WDATA2BUS_OFST 0x5c
1939 
1940 #define ALT_ECC_SDMMC_WDATA2BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA2BUS_OFST))
1941 
1963 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_LSB 0
1964 
1965 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_MSB 31
1966 
1967 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1968 
1969 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1970 
1971 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1972 
1973 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1974 
1975 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1976 
1977 #define ALT_ECC_SDMMC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1978 
1979 #ifndef __ASSEMBLY__
1980 
1991 {
1992  uint32_t ECC_WDataBUS : 32;
1993 };
1994 
1997 #endif /* __ASSEMBLY__ */
1998 
2000 #define ALT_ECC_SDMMC_WDATA3BUS_RESET 0x00000000
2001 
2002 #define ALT_ECC_SDMMC_WDATA3BUS_OFST 0x60
2003 
2004 #define ALT_ECC_SDMMC_WDATA3BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATA3BUS_OFST))
2005 
2035 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
2036 
2037 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
2038 
2039 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
2040 
2041 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
2042 
2043 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
2044 
2045 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
2046 
2047 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2048 
2049 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2050 
2060 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
2061 
2062 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
2063 
2064 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
2065 
2066 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
2067 
2068 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
2069 
2070 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
2071 
2072 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2073 
2074 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2075 
2085 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
2086 
2087 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
2088 
2089 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
2090 
2091 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
2092 
2093 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
2094 
2095 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
2096 
2097 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2098 
2099 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2100 
2110 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
2111 
2112 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
2113 
2114 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
2115 
2116 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
2117 
2118 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
2119 
2120 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
2121 
2122 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2123 
2124 #define ALT_ECC_SDMMC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2125 
2126 #ifndef __ASSEMBLY__
2127 
2138 {
2139  uint32_t ECC_RDataecc0BUS : 7;
2140  uint32_t : 1;
2141  uint32_t ECC_RDataecc1BUS : 7;
2142  uint32_t : 1;
2143  uint32_t ECC_RDataecc2BUS : 7;
2144  uint32_t : 1;
2145  uint32_t ECC_RDataecc3BUS : 7;
2146  uint32_t : 1;
2147 };
2148 
2151 #endif /* __ASSEMBLY__ */
2152 
2154 #define ALT_ECC_SDMMC_RDATAECC0BUS_RESET 0x00000000
2155 
2156 #define ALT_ECC_SDMMC_RDATAECC0BUS_OFST 0x64
2157 
2158 #define ALT_ECC_SDMMC_RDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC0BUS_OFST))
2159 
2189 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
2190 
2191 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
2192 
2193 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
2194 
2195 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
2196 
2197 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
2198 
2199 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
2200 
2201 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2202 
2203 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2204 
2214 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
2215 
2216 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
2217 
2218 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
2219 
2220 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
2221 
2222 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
2223 
2224 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
2225 
2226 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2227 
2228 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2229 
2239 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
2240 
2241 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
2242 
2243 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
2244 
2245 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
2246 
2247 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
2248 
2249 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
2250 
2251 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2252 
2253 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2254 
2264 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
2265 
2266 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
2267 
2268 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
2269 
2270 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
2271 
2272 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
2273 
2274 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
2275 
2276 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2277 
2278 #define ALT_ECC_SDMMC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2279 
2280 #ifndef __ASSEMBLY__
2281 
2292 {
2293  uint32_t ECC_RDataecc4BUS : 7;
2294  uint32_t : 1;
2295  uint32_t ECC_RDataecc5BUS : 7;
2296  uint32_t : 1;
2297  uint32_t ECC_RDataecc6BUS : 7;
2298  uint32_t : 1;
2299  uint32_t ECC_RDataecc7BUS : 7;
2300  uint32_t : 1;
2301 };
2302 
2305 #endif /* __ASSEMBLY__ */
2306 
2308 #define ALT_ECC_SDMMC_RDATAECC1BUS_RESET 0x00000000
2309 
2310 #define ALT_ECC_SDMMC_RDATAECC1BUS_OFST 0x68
2311 
2312 #define ALT_ECC_SDMMC_RDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_RDATAECC1BUS_OFST))
2313 
2343 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
2344 
2345 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
2346 
2347 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
2348 
2349 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
2350 
2351 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
2352 
2353 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2354 
2355 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
2356 
2357 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
2358 
2368 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2369 
2370 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
2371 
2372 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
2373 
2374 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
2375 
2376 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2377 
2378 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2379 
2380 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2381 
2382 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2383 
2393 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2394 
2395 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2396 
2397 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2398 
2399 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2400 
2401 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2402 
2403 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2404 
2405 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2406 
2407 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2408 
2418 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2419 
2420 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2421 
2422 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2423 
2424 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2425 
2426 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2427 
2428 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2429 
2430 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2431 
2432 #define ALT_ECC_SDMMC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2433 
2434 #ifndef __ASSEMBLY__
2435 
2446 {
2447  uint32_t ECC_WDataecc0BUS : 7;
2448  uint32_t : 1;
2449  uint32_t ECC_WDataecc1BUS : 7;
2450  uint32_t : 1;
2451  uint32_t ECC_WDataecc2BUS : 7;
2452  uint32_t : 1;
2453  uint32_t ECC_WDataecc3BUS : 7;
2454  uint32_t : 1;
2455 };
2456 
2459 #endif /* __ASSEMBLY__ */
2460 
2462 #define ALT_ECC_SDMMC_WDATAECC0BUS_RESET 0x00000000
2463 
2464 #define ALT_ECC_SDMMC_WDATAECC0BUS_OFST 0x6c
2465 
2466 #define ALT_ECC_SDMMC_WDATAECC0BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC0BUS_OFST))
2467 
2497 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2498 
2499 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2500 
2501 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2502 
2503 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2504 
2505 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2506 
2507 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2508 
2509 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2510 
2511 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2512 
2522 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2523 
2524 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2525 
2526 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2527 
2528 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2529 
2530 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2531 
2532 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2533 
2534 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2535 
2536 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2537 
2547 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2548 
2549 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2550 
2551 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2552 
2553 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2554 
2555 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2556 
2557 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2558 
2559 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2560 
2561 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2562 
2572 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2573 
2574 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2575 
2576 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2577 
2578 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2579 
2580 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2581 
2582 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2583 
2584 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2585 
2586 #define ALT_ECC_SDMMC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2587 
2588 #ifndef __ASSEMBLY__
2589 
2600 {
2601  uint32_t ECC_WDataecc4BUS : 7;
2602  uint32_t : 1;
2603  uint32_t ECC_WDataecc5BUS : 7;
2604  uint32_t : 1;
2605  uint32_t ECC_WDataecc6BUS : 7;
2606  uint32_t : 1;
2607  uint32_t ECC_WDataecc7BUS : 7;
2608  uint32_t : 1;
2609 };
2610 
2613 #endif /* __ASSEMBLY__ */
2614 
2616 #define ALT_ECC_SDMMC_WDATAECC1BUS_RESET 0x00000000
2617 
2618 #define ALT_ECC_SDMMC_WDATAECC1BUS_OFST 0x70
2619 
2620 #define ALT_ECC_SDMMC_WDATAECC1BUS_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDATAECC1BUS_OFST))
2621 
2644 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_LSB 0
2645 
2646 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_MSB 0
2647 
2648 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_WIDTH 1
2649 
2650 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET_MSK 0x00000001
2651 
2652 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2653 
2654 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_RESET 0x0
2655 
2656 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2657 
2658 #define ALT_ECC_SDMMC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2659 
2660 #ifndef __ASSEMBLY__
2661 
2672 {
2673  uint32_t DBEN : 1;
2674  uint32_t : 31;
2675 };
2676 
2679 #endif /* __ASSEMBLY__ */
2680 
2682 #define ALT_ECC_SDMMC_DBYTECTL_RESET 0x00000000
2683 
2684 #define ALT_ECC_SDMMC_DBYTECTL_OFST 0x74
2685 
2686 #define ALT_ECC_SDMMC_DBYTECTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_DBYTECTL_OFST))
2687 
2718 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_LSB 0
2719 
2720 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_MSB 0
2721 
2722 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_WIDTH 1
2723 
2724 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2725 
2726 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2727 
2728 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_RESET 0x0
2729 
2730 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2731 
2732 #define ALT_ECC_SDMMC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2733 
2743 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_LSB 1
2744 
2745 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_MSB 1
2746 
2747 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_WIDTH 1
2748 
2749 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2750 
2751 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2752 
2753 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_RESET 0x0
2754 
2755 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2756 
2757 #define ALT_ECC_SDMMC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2758 
2768 #define ALT_ECC_SDMMC_ACCCTL_RDWR_LSB 8
2769 
2770 #define ALT_ECC_SDMMC_ACCCTL_RDWR_MSB 8
2771 
2772 #define ALT_ECC_SDMMC_ACCCTL_RDWR_WIDTH 1
2773 
2774 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET_MSK 0x00000100
2775 
2776 #define ALT_ECC_SDMMC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2777 
2778 #define ALT_ECC_SDMMC_ACCCTL_RDWR_RESET 0x0
2779 
2780 #define ALT_ECC_SDMMC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2781 
2782 #define ALT_ECC_SDMMC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2783 
2784 #ifndef __ASSEMBLY__
2785 
2796 {
2797  uint32_t DATAOVR : 1;
2798  uint32_t ECCOVR : 1;
2799  uint32_t : 6;
2800  uint32_t RDWR : 1;
2801  uint32_t : 23;
2802 };
2803 
2806 #endif /* __ASSEMBLY__ */
2807 
2809 #define ALT_ECC_SDMMC_ACCCTL_RESET 0x00000000
2810 
2811 #define ALT_ECC_SDMMC_ACCCTL_OFST 0x78
2812 
2813 #define ALT_ECC_SDMMC_ACCCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_ACCCTL_OFST))
2814 
2839 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_LSB 0
2840 
2841 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_MSB 0
2842 
2843 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_WIDTH 1
2844 
2845 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET_MSK 0x00000001
2846 
2847 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_CLR_MSK 0xfffffffe
2848 
2849 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_RESET 0x0
2850 
2851 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_GET(value) (((value) & 0x00000001) >> 0)
2852 
2853 #define ALT_ECC_SDMMC_STARTACC_ENBUSB_SET(value) (((value) << 0) & 0x00000001)
2854 
2864 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_LSB 16
2865 
2866 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_MSB 16
2867 
2868 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_WIDTH 1
2869 
2870 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET_MSK 0x00010000
2871 
2872 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2873 
2874 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_RESET 0x0
2875 
2876 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2877 
2878 #define ALT_ECC_SDMMC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2879 
2880 #ifndef __ASSEMBLY__
2881 
2892 {
2893  uint32_t ENBUSB : 1;
2894  uint32_t : 15;
2895  uint32_t ENBUSA : 1;
2896  uint32_t : 15;
2897 };
2898 
2901 #endif /* __ASSEMBLY__ */
2902 
2904 #define ALT_ECC_SDMMC_STARTACC_RESET 0x00000000
2905 
2906 #define ALT_ECC_SDMMC_STARTACC_OFST 0x7c
2907 
2908 #define ALT_ECC_SDMMC_STARTACC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_STARTACC_OFST))
2909 
2932 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_LSB 0
2933 
2934 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_MSB 0
2935 
2936 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_WIDTH 1
2937 
2938 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2939 
2940 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2941 
2942 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_RESET 0x0
2943 
2944 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2945 
2946 #define ALT_ECC_SDMMC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2947 
2948 #ifndef __ASSEMBLY__
2949 
2960 {
2961  uint32_t WDEN_RAM : 1;
2962  uint32_t : 31;
2963 };
2964 
2967 #endif /* __ASSEMBLY__ */
2968 
2970 #define ALT_ECC_SDMMC_WDCTL_RESET 0x00000000
2971 
2972 #define ALT_ECC_SDMMC_WDCTL_OFST 0x80
2973 
2974 #define ALT_ECC_SDMMC_WDCTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_ECC_SDMMC_WDCTL_OFST))
2975 
3003 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_LSB 0
3004 
3005 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_MSB 9
3006 
3007 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_WIDTH 10
3008 
3009 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
3010 
3011 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
3012 
3013 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_RESET 0x0
3014 
3015 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3016 
3017 #define ALT_ECC_SDMMC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3018 
3029 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_LSB 31
3030 
3031 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_MSB 31
3032 
3033 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_WIDTH 1
3034 
3035 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET_MSK 0x80000000
3036 
3037 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
3038 
3039 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_RESET 0x0
3040 
3041 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3042 
3043 #define ALT_ECC_SDMMC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
3044 
3045 #ifndef __ASSEMBLY__
3046 
3057 {
3058  const uint32_t Address : 10;
3059  uint32_t : 21;
3060  uint32_t VALID : 1;
3061 };
3062 
3065 #endif /* __ASSEMBLY__ */
3066 
3068 #define ALT_ECC_SDMMC_SERRLKUPA0_RESET 0x00000000
3069 
3070 #define ALT_ECC_SDMMC_SERRLKUPA0_OFST 0x90
3071 
3099 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_LSB 0
3100 
3101 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_MSB 9
3102 
3103 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_WIDTH 10
3104 
3105 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET_MSK 0x000003ff
3106 
3107 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_CLR_MSK 0xfffffc00
3108 
3109 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_RESET 0x0
3110 
3111 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
3112 
3113 #define ALT_ECC_SDMMC_SERRLKUPB0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
3114 
3125 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_LSB 31
3126 
3127 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_MSB 31
3128 
3129 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_WIDTH 1
3130 
3131 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET_MSK 0x80000000
3132 
3133 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_CLR_MSK 0x7fffffff
3134 
3135 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_RESET 0x0
3136 
3137 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_GET(value) (((value) & 0x80000000) >> 31)
3138 
3139 #define ALT_ECC_SDMMC_SERRLKUPB0_VALID_SET(value) (((value) << 31) & 0x80000000)
3140 
3141 #ifndef __ASSEMBLY__
3142 
3153 {
3154  const uint32_t Address : 10;
3155  uint32_t : 21;
3156  uint32_t VALID : 1;
3157 };
3158 
3161 #endif /* __ASSEMBLY__ */
3162 
3164 #define ALT_ECC_SDMMC_SERRLKUPB0_RESET 0x00000000
3165 
3166 #define ALT_ECC_SDMMC_SERRLKUPB0_OFST 0xd0
3167 
3168 #ifndef __ASSEMBLY__
3169 
3180 {
3182  volatile uint32_t _pad_0x4_0x7;
3214  volatile uint32_t _pad_0x84_0x8f[3];
3216  volatile uint32_t _pad_0x94_0xcf[15];
3218  volatile uint32_t _pad_0xd4_0x400[203];
3219 };
3220 
3222 typedef volatile struct ALT_ECC_SDMMC_s ALT_ECC_SDMMC_t;
3225 {
3226  volatile uint32_t IP_REV_ID;
3227  volatile uint32_t _pad_0x4_0x7;
3228  volatile uint32_t CTRL;
3229  volatile uint32_t INITSTAT;
3230  volatile uint32_t ERRINTEN;
3231  volatile uint32_t ERRINTENS;
3232  volatile uint32_t ERRINTENR;
3233  volatile uint32_t INTMODE;
3234  volatile uint32_t INTSTAT;
3235  volatile uint32_t INTTEST;
3236  volatile uint32_t MODSTAT;
3237  volatile uint32_t DERRADDRA;
3238  volatile uint32_t SERRADDRA;
3239  volatile uint32_t DERRADDRB;
3240  volatile uint32_t SERRADDRB;
3241  volatile uint32_t SERRCNTREG;
3242  volatile uint32_t ECC_Addrbus;
3243  volatile uint32_t ECC_RData0bus;
3244  volatile uint32_t ECC_RData1bus;
3245  volatile uint32_t ECC_RData2bus;
3246  volatile uint32_t ECC_RData3bus;
3247  volatile uint32_t ECC_WData0bus;
3248  volatile uint32_t ECC_WData1bus;
3249  volatile uint32_t ECC_WData2bus;
3250  volatile uint32_t ECC_WData3bus;
3251  volatile uint32_t ECC_RDataecc0bus;
3252  volatile uint32_t ECC_RDataecc1bus;
3253  volatile uint32_t ECC_WDataecc0bus;
3254  volatile uint32_t ECC_WDataecc1bus;
3255  volatile uint32_t ECC_dbytectrl;
3256  volatile uint32_t ECC_accctrl;
3257  volatile uint32_t ECC_startacc;
3258  volatile uint32_t ECC_wdctrl;
3259  volatile uint32_t _pad_0x84_0x8f[3];
3260  volatile uint32_t SERRLKUPA0;
3261  volatile uint32_t _pad_0x94_0xcf[15];
3262  volatile uint32_t SERRLKUPB0;
3263  volatile uint32_t _pad_0xd4_0x400[203];
3264 };
3265 
3268 #endif /* __ASSEMBLY__ */
3269 
3271 #ifdef __cplusplus
3272 }
3273 #endif /* __cplusplus */
3274 #endif /* __ALT_SOCAL_ECC_SDMMC_H__ */
3275