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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains settings that control clock ddr_dq_clk generated from the C2 output of the SDRAM PLL.
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[8:0] | RW | 0x1 | Counter |
[20:9] | RW | 0x0 | Phase Shift |
[31:21] | ??? | 0x0 | UNDEFINED |
Field : Counter - cnt | |
Divides the VCO frequency by the value+1 in this field. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET(value) (((value) & 0x000001ff) >> 0) |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET(value) (((value) << 0) & 0x000001ff) |
Field : Phase Shift - phase | |
Increment the phase of the VCO output by the value in this field multiplied by 45 degrees. The accumulated phase shift is the total shifted amount since the last assertion of the 'SDRAM All Output Divider Reset' bit in the SDRAM vco control register. In order to guarantee the phase shift to a known value, 'SDRAM clocks output phase align' bit should be asserted before programming this field. This field is only writeable by SW when it is zero. HW updates this field in real time as the phase adjustment is being made. SW may poll this field waiting for zero indicating the phase adjustment has completed by HW. Field Access Macros: | |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET(value) (((value) & 0x001ffe00) >> 9) |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET(value) (((value) << 9) & 0x001ffe00) |
Data Structures | |
struct | ALT_CLKMGR_SDRPLL_DDRDQCLK_s |
Macros | |
#define | ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 |
Typedefs | |
typedef struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s | ALT_CLKMGR_SDRPLL_DDRDQCLK_t |
struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK.
Data Fields | ||
---|---|---|
uint32_t | cnt: 9 | Counter |
uint32_t | phase: 12 | Phase Shift |
uint32_t | __pad0__: 11 | UNDEFINED |
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_WIDTH 9 |
The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET_MSK 0x000001ff |
The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_CLR_MSK 0xfffffe00 |
The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_RESET 0x1 |
The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_GET | ( | value | ) | (((value) & 0x000001ff) >> 0) |
Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT field value from a register.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT_SET | ( | value | ) | (((value) << 0) & 0x000001ff) |
Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_CNT register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_WIDTH 12 |
The width in bits of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET_MSK 0x001ffe00 |
The mask used to set the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_CLR_MSK 0xffe001ff |
The mask used to clear the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_RESET 0x0 |
The reset value of the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_GET | ( | value | ) | (((value) & 0x001ffe00) >> 9) |
Extracts the ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE field value from a register.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE_SET | ( | value | ) | (((value) << 9) & 0x001ffe00) |
Produces a ALT_CLKMGR_SDRPLL_DDRDQCLK_PHASE register field value suitable for setting the register.
#define ALT_CLKMGR_SDRPLL_DDRDQCLK_OFST 0x10 |
The byte offset of the ALT_CLKMGR_SDRPLL_DDRDQCLK register from the beginning of the component.
typedef struct ALT_CLKMGR_SDRPLL_DDRDQCLK_s ALT_CLKMGR_SDRPLL_DDRDQCLK_t |
The typedef declaration for register ALT_CLKMGR_SDRPLL_DDRDQCLK.