Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 449 (Sub-Second Increment Register) - gmacgrp_sub_second_increment

Description

In the Coarse Update mode (TSCFUPDT bit in Register 448), the value in this register is added to the system time every clock cycle of clk_ptp_ref_i. In the Fine Update mode, the value in this register is added to the system time whenever the Accumulator gets an overflow.

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 Sub-second Increment Value
[31:8] ??? 0x0 UNDEFINED

Field : Sub-second Increment Value - ssinc

The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example, when PTP clock is 50 MHz (period is 20 ns), you should program 20 (0x14) when the System Time-Nanoseconds register has an accuracy of 1 ns (TSCTRLSSR bit is set). When TSCTRLSSR is clear, the Nanoseconds register has a resolution of ~0.465ns. In this case, you should program a value of 43 (0x2B) that is derived by 20ns/0.465.

Field Access Macros:

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB   0
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB   7
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH   8
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK   0x000000ff
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK   0xffffff00
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET   0x0
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET(value)   (((value) << 0) & 0x000000ff)
 

Data Structures

struct  ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s
 

Macros

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_RESET   0x00000000
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST   0x704
 
#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s 
ALT_EMAC_GMAC_SUB_SEC_INCREMENT_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_SUB_SEC_INCREMENT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_SUB_SEC_INCREMENT.

Data Fields
uint32_t ssinc: 8 Sub-second Increment Value
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_WIDTH   8

The width in bits of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET_MSK   0x000000ff

The mask used to set the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_CLR_MSK   0xffffff00

The mask used to clear the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC field value from a register.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_EMAC_GMAC_SUB_SEC_INCREMENT_SSINC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST   0x704

The byte offset of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register from the beginning of the component.

#define ALT_EMAC_GMAC_SUB_SEC_INCREMENT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_SUB_SEC_INCREMENT_OFST))

The address of the ALT_EMAC_GMAC_SUB_SEC_INCREMENT register.

Typedef Documentation