Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ctrlcfg2

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD
[1] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD
[2] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD
[3] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD
[4] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD
[6:5] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0
[8:7] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1
[9] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL
[10] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL
[11] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL
[12] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL
[14:13] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL
[17:15] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT
[20:18] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT
[23:21] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT
[26:24] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT
[31:27] ??? 0x0 UNDEFINED

Field : cfg_ctrl_output_regd

Set to one to register the HMC command output. Set to 0 to disable it.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_LSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_MSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET_MSK   0x00000001
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_CLR_MSK   0xfffffffe
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : cfg_dbc0_output_regd

Set to one to register the HMC command output. Set to 0 to disable it.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_LSB   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_MSB   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK   0x00000002
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK   0xfffffffd
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET(value)   (((value) << 1) & 0x00000002)
 

Field : cfg_dbc1_output_regd

Set to one to register the HMC command output. Set to 0 to disable it.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_LSB   2
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_MSB   2
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK   0x00000004
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK   0xfffffffb
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET(value)   (((value) << 2) & 0x00000004)
 

Field : cfg_dbc2_output_regd

Set to one to register the HMC command output. Set to 0 to disable it.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_LSB   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_MSB   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK   0x00000008
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK   0xfffffff7
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET(value)   (((value) << 3) & 0x00000008)
 

Field : cfg_dbc3_output_regd

Set to one to register the HMC command output. Set to 0 to disable it.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_LSB   4
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_MSB   4
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK   0x00000010
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK   0xffffffef
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET(value)   (((value) << 4) & 0x00000010)
 

Field : cfg_ctrl2dbc_switch0

Select of the MUX ctrl2dbc_switch0. 2

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_LSB   5
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_MSB   6
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_WIDTH   2
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET_MSK   0x00000060
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_CLR_MSK   0xffffff9f
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_GET(value)   (((value) & 0x00000060) >> 5)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET(value)   (((value) << 5) & 0x00000060)
 

Field : cfg_ctrl2dbc_switch1

Select of the MUX ctrl2dbc_switch1. 2

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_LSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_MSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_WIDTH   2
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET_MSK   0x00000180
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_CLR_MSK   0xfffffe7f
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_GET(value)   (((value) & 0x00000180) >> 7)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET(value)   (((value) << 7) & 0x00000180)
 

Field : cfg_dbc0_ctrl_sel

DBC0 - control path select. 1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_LSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_MSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET_MSK   0x00000200
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_CLR_MSK   0xfffffdff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET(value)   (((value) << 9) & 0x00000200)
 

Field : cfg_dbc1_ctrl_sel

DBC1 - control path select. 1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_LSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_MSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET_MSK   0x00000400
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_CLR_MSK   0xfffffbff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET(value)   (((value) << 10) & 0x00000400)
 

Field : cfg_dbc2_ctrl_sel

DBC2 - control path select. 1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_LSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_MSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET_MSK   0x00000800
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_CLR_MSK   0xfffff7ff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET(value)   (((value) << 11) & 0x00000800)
 

Field : cfg_dbc3_ctrl_sel

DBC3 - control path select. 1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_LSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_MSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET_MSK   0x00001000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_CLR_MSK   0xffffefff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET(value)   (((value) << 12) & 0x00001000)
 

Field : cfg_dbc2ctrl_sel

Specifies which DBC is driven by the local control path. 2

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_LSB   13
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_MSB   14
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_WIDTH   2
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET_MSK   0x00006000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_CLR_MSK   0xffff9fff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_GET(value)   (((value) & 0x00006000) >> 13)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET(value)   (((value) << 13) & 0x00006000)
 

Field : cfg_dbc0_pipe_lat

Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC0

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_LSB   15
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_MSB   17
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK   0x00038000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK   0xfffc7fff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_GET(value)   (((value) & 0x00038000) >> 15)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET(value)   (((value) << 15) & 0x00038000)
 

Field : cfg_dbc1_pipe_lat

Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_LSB   18
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_MSB   20
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK   0x001c0000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK   0xffe3ffff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_GET(value)   (((value) & 0x001c0000) >> 18)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET(value)   (((value) << 18) & 0x001c0000)
 

Field : cfg_dbc2_pipe_lat

Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC2

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_LSB   21
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_MSB   23
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK   0x00e00000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK   0xff1fffff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_GET(value)   (((value) & 0x00e00000) >> 21)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET(value)   (((value) << 21) & 0x00e00000)
 

Field : cfg_dbc3_pipe_lat

Specifies in number of controller clock cycles the latency of pipelining the signals from control path to DBC3

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_LSB   24
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_MSB   26
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK   0x07000000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK   0xf8ffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_GET(value)   (((value) & 0x07000000) >> 24)
 
#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET(value)   (((value) << 24) & 0x07000000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CTLCFG2_s
 

Macros

#define ALT_IO48_HMC_MMR_CTLCFG2_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CTLCFG2_OFST   0x30
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CTLCFG2_s 
ALT_IO48_HMC_MMR_CTLCFG2_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CTLCFG2_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG2.

Data Fields
uint32_t cfg_ctrl_output_regd: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD
uint32_t cfg_dbc0_output_regd: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD
uint32_t cfg_dbc1_output_regd: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD
uint32_t cfg_dbc2_output_regd: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD
uint32_t cfg_dbc3_output_regd: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD
uint32_t cfg_ctrl2dbc_switch0: 2 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0
uint32_t cfg_ctrl2dbc_switch1: 2 ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1
uint32_t cfg_dbc0_ctrl_sel: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL
uint32_t cfg_dbc1_ctrl_sel: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL
uint32_t cfg_dbc2_ctrl_sel: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL
uint32_t cfg_dbc3_ctrl_sel: 1 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL
uint32_t cfg_dbc2ctrl_sel: 2 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL
uint32_t cfg_dbc0_pipe_lat: 3 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT
uint32_t cfg_dbc1_pipe_lat: 3 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT
uint32_t cfg_dbc2_pipe_lat: 3 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT
uint32_t cfg_dbc3_pipe_lat: 3 ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT
uint32_t __pad0__: 5 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_MSB   0

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET_MSK   0x00000001

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL_OUTPUT_REGD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_LSB   1

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_MSB   1

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET_MSK   0x00000002

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_CLR_MSK   0xfffffffd

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_OUTPUT_REGD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_LSB   2

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_MSB   2

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET_MSK   0x00000004

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_CLR_MSK   0xfffffffb

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_OUTPUT_REGD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_LSB   3

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_MSB   3

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET_MSK   0x00000008

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_CLR_MSK   0xfffffff7

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_OUTPUT_REGD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_LSB   4

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_MSB   4

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET_MSK   0x00000010

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_CLR_MSK   0xffffffef

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_OUTPUT_REGD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_LSB   5

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_MSB   6

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET_MSK   0x00000060

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_CLR_MSK   0xffffff9f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_GET (   value)    (((value) & 0x00000060) >> 5)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0_SET (   value)    (((value) << 5) & 0x00000060)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH0 register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_LSB   7

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET_MSK   0x00000180

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_CLR_MSK   0xfffffe7f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_GET (   value)    (((value) & 0x00000180) >> 7)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1_SET (   value)    (((value) << 7) & 0x00000180)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_CTL2DBC_SWITCH1 register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_MSB   9

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET_MSK   0x00000200

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_CLR_MSK   0xfffffdff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_LSB   10

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_MSB   10

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET_MSK   0x00000400

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_CLR_MSK   0xfffffbff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_LSB   11

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_MSB   11

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET_MSK   0x00000800

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_LSB   12

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_MSB   12

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET_MSK   0x00001000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_CLR_MSK   0xffffefff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_LSB   13

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_MSB   14

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET_MSK   0x00006000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_CLR_MSK   0xffff9fff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_GET (   value)    (((value) & 0x00006000) >> 13)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL_SET (   value)    (((value) << 13) & 0x00006000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_LSB   15

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_MSB   17

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET_MSK   0x00038000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_CLR_MSK   0xfffc7fff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_GET (   value)    (((value) & 0x00038000) >> 15)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT_SET (   value)    (((value) << 15) & 0x00038000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC0_PIPE_LAT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_LSB   18

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_MSB   20

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET_MSK   0x001c0000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_CLR_MSK   0xffe3ffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_GET (   value)    (((value) & 0x001c0000) >> 18)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT_SET (   value)    (((value) << 18) & 0x001c0000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC1_PIPE_LAT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_LSB   21

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_MSB   23

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET_MSK   0x00e00000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_CLR_MSK   0xff1fffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_GET (   value)    (((value) & 0x00e00000) >> 21)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT_SET (   value)    (((value) << 21) & 0x00e00000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC2_PIPE_LAT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_LSB   24

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_MSB   26

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET_MSK   0x07000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_CLR_MSK   0xf8ffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_GET (   value)    (((value) & 0x07000000) >> 24)

Extracts the ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT_SET (   value)    (((value) << 24) & 0x07000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG2_CFG_DBC3_PIPE_LAT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG2_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CTLCFG2 register.

#define ALT_IO48_HMC_MMR_CTLCFG2_OFST   0x30

The byte offset of the ALT_IO48_HMC_MMR_CTLCFG2 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG2.