Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ERRINTEN

Description

Error Interrupt enable

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN
[1] RW 0x0 ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN
[2] RW 0x0 ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN
[31:3] ??? 0x0 UNDEFINED

Field : SERRINTEN

This bit is used to enable the single bit error to system manager. It enables the interrupt modes (sbe request,compare match)

1'b0: SBE interrupt generation logic is disabled.

1'b1: SBE interrupt generation logic is enabled,

Field Access Macros:

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_LSB   0
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_MSB   0
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK   0x00000001
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_CLR_MSK   0xfffffffe
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : DERRINTEN

This bit is used to enable the double bit error interrupt to system

manager.When dbe error occurs, bus error is always generated with the transaction.DERR interrupt (derr_req)will be generated when this bit is enabled.

1'b0: DBE interrupt generation logic is disabled.

1'b1: DBE interrupt generation logic is enabled,

Field Access Macros:

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_LSB   1
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_MSB   1
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK   0x00000002
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_CLR_MSK   0xfffffffd
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET(value)   (((value) << 1) & 0x00000002)
 

Field : HMI_INTREN

Enables GP HMI interrupt.

This bit is used to enable the general purpose HMI interrupt error interrupt to system manager. When this bit is enabled along with autoWB_drop_en, it compares the internal counter with autoWB_drop_cntreg value. If the value is greater than or equal to, then the interrupt will be asserted..

1'b0: hmi interrupt generation logic is disabled.

1'b1: hmi interrupt generation logic is enabled.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_LSB   2
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_MSB   2
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_WIDTH   1
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET_MSK   0x00000004
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_CLR_MSK   0xfffffffb
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET(value)   (((value) << 2) & 0x00000004)
 

Data Structures

struct  ALT_ECC_HMC_OCP_ERRINTEN_s
 

Macros

#define ALT_ECC_HMC_OCP_ERRINTEN_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_ERRINTEN_OFST   0x110
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_ERRINTEN_s 
ALT_ECC_HMC_OCP_ERRINTEN_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_ERRINTEN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_ERRINTEN.

Data Fields
uint32_t SERRINTEN: 1 ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN
uint32_t DERRINTEN: 1 ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN
uint32_t HMI_INTREN: 1 ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN
uint32_t __pad0__: 29 UNDEFINED

Macro Definitions

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET_MSK   0x00000001

The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN field value from a register.

#define ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_HMC_OCP_ERRINTEN_SERRINTEN register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_LSB   1

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_MSB   1

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET_MSK   0x00000002

The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_CLR_MSK   0xfffffffd

The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN field value from a register.

#define ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_ECC_HMC_OCP_ERRINTEN_DERRINTEN register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_LSB   2

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_MSB   2

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET_MSK   0x00000004

The mask used to set the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_CLR_MSK   0xfffffffb

The mask used to clear the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN field value from a register.

#define ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_ECC_HMC_OCP_ERRINTEN_HMI_INTREN register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ERRINTEN_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_ERRINTEN register.

#define ALT_ECC_HMC_OCP_ERRINTEN_OFST   0x110

The byte offset of the ALT_ECC_HMC_OCP_ERRINTEN register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_ECC_HMC_OCP_ERRINTEN.