Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 15 (Interrupt Mask Register) - Interrupt_Mask

Description

The Interrupt Mask Register bits enable you to mask the interrupt signal because of the corresponding event in the Interrupt Status Register. The interrupt signal is sbd_intr_o.

Register Layout

Bits Access Reset Description
[0] RW 0x0 RGMII or SMII Interrupt Mask
[1] R 0x0 PCS Link Status Interrupt Mask
[2] R 0x0 PCS AN Completion Interrupt Mask
[8:3] ??? 0x0 UNDEFINED
[9] RW 0x0 Timestamp Interrupt Mask
[10] RW 0x0 LPI Interrupt Mask
[31:11] ??? 0x0 UNDEFINED

Field : RGMII or SMII Interrupt Mask - rgsmiiim

When set, this bit disables the assertion of the interrupt signal because of the setting of the RGMII or SMII Interrupt Status bit in Register 14 (Interrupt Status Register).

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD 0x0 RGMII or SMII Interrupt Mask Disable
ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END 0x1 RGMII or SMII Interrupt Mask Enable

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB   0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB   0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET(value)   (((value) << 0) & 0x00000001)
 

Field : PCS Link Status Interrupt Mask - pcslchgim

When set, this bit disables the assertion of the interrupt signal because of the setting of the PCS Link-status changed bit in Register 14 (Interrupt Status Register).

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET(value)   (((value) << 1) & 0x00000002)
 

Field : PCS AN Completion Interrupt Mask - pcsancim

When set, this bit disables the assertion of the interrupt signal because of the setting of PCS Auto-negotiation complete bit in Register 14 (Interrupt Status Register).

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB   2
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB   2
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Timestamp Interrupt Mask - tsim

When set, this bit disables the assertion of the interrupt signal because of the setting of Timestamp Interrupt Status bit in Register 14 (Interrupt Status Register).

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD 0x0 Timestamp Interrupt Mask Disabled
ALT_EMAC_GMAC_INT_MSK_TSIM_E_END 0x1 Timestamp Interrupt Mask Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB   9
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB   9
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET(value)   (((value) << 9) & 0x00000200)
 

Field : LPI Interrupt Mask - lpiim

When set, this bit disables the assertion of the interrupt signal because of the setting of the LPI Interrupt Status bit in Register 14 (Interrupt Status Register).

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD 0x0 LPI Interrupt Mask Disabled
ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END 0x1 LPI Interrupt Mask Enabled

Field Access Macros:

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END   0x1
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB   10
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB   10
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH   1
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET   0x0
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET(value)   (((value) << 10) & 0x00000400)
 

Data Structures

struct  ALT_EMAC_GMAC_INT_MSK_s
 

Macros

#define ALT_EMAC_GMAC_INT_MSK_OFST   0x3c
 
#define ALT_EMAC_GMAC_INT_MSK_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_INT_MSK_s 
ALT_EMAC_GMAC_INT_MSK_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_INT_MSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_INT_MSK.

Data Fields
uint32_t rgsmiiim: 1 RGMII or SMII Interrupt Mask
const uint32_t pcslchgim: 1 PCS Link Status Interrupt Mask
const uint32_t pcsancim: 1 PCS AN Completion Interrupt Mask
uint32_t __pad0__: 6 UNDEFINED
uint32_t tsim: 1 Timestamp Interrupt Mask
uint32_t lpiim: 1 LPI Interrupt Mask
uint32_t __pad1__: 21 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM

RGMII or SMII Interrupt Mask Disable

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_RGSMIIIM

RGMII or SMII Interrupt Mask Enable

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_INT_MSK_RGSMIIIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_RGSMIIIM_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_INT_MSK_RGSMIIIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_INT_MSK_PCSLCHGIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_INT_MSK_PCSANCIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_PCSANCIM_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_INT_MSK_PCSANCIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM

Timestamp Interrupt Mask Disabled

#define ALT_EMAC_GMAC_INT_MSK_TSIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_TSIM

Timestamp Interrupt Mask Enabled

#define ALT_EMAC_GMAC_INT_MSK_TSIM_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_INT_MSK_TSIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_TSIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_TSIM register field.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_INT_MSK_TSIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_TSIM_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_INT_MSK_TSIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM

LPI Interrupt Mask Disabled

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_INT_MSK_LPIIM

LPI Interrupt Mask Enabled

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_INT_MSK_LPIIM register field value.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_INT_MSK_LPIIM register field.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_INT_MSK_LPIIM field value from a register.

#define ALT_EMAC_GMAC_INT_MSK_LPIIM_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_INT_MSK_LPIIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_INT_MSK_OFST   0x3c

The byte offset of the ALT_EMAC_GMAC_INT_MSK register from the beginning of the component.

#define ALT_EMAC_GMAC_INT_MSK_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_INT_MSK_OFST))

The address of the ALT_EMAC_GMAC_INT_MSK register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_INT_MSK.