Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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FPGA Manager Status and Control

Description

This group provides functions for controlling and determining status of the FPGA Manager.

Typedefs

typedef enum ALT_FPGA_STATE_e ALT_FPGA_STATE_t
 
typedef enum ALT_FPGA_MON_STATUS_e ALT_FPGA_MON_STATUS_t
 

ENUMS

enum  ALT_FPGA_STATE_e {
  ALT_FPGA_STATE_POWER_UP = 0x0, ALT_FPGA_STATE_RESET = 0x1, ALT_FPGA_STATE_CFG = 0x2, ALT_FPGA_STATE_INIT = 0x3,
  ALT_FPGA_STATE_USER_MODE = 0x4, ALT_FPGA_STATE_UNKNOWN = 0x5, ALT_FPGA_STATE_POWER_OFF = 0xF
}
 
enum  ALT_FPGA_MON_STATUS_e {
  ALT_FPGA_MON_nSTATUS = 0x0001, ALT_FPGA_MON_CONF_DONE = 0x0002, ALT_FPGA_MON_INIT_DONE = 0x0004, ALT_FPGA_MON_CRC_ERROR = 0x0008,
  ALT_FPGA_MON_CVP_CONF_DONE = 0x0010, ALT_FPGA_MON_PR_READY = 0x0020, ALT_FPGA_MON_PR_ERROR = 0x0040, ALT_FPGA_MON_PR_DONE = 0x0080,
  ALT_FPGA_MON_nCONFIG_PIN = 0x0100, ALT_FPGA_MON_nSTATUS_PIN = 0x0200, ALT_FPGA_MON_CONF_DONE_PIN = 0x0400, ALT_FPGA_MON_FPGA_POWER_ON = 0x0800
}
 

Functions

ALT_STATUS_CODE alt_fpga_control_enable (void)
 
ALT_STATUS_CODE alt_fpga_control_disable (void)
 
bool alt_fpga_control_is_enabled (void)
 
ALT_FPGA_STATE_t alt_fpga_state_get (void)
 
uint32_t alt_fpga_mon_status_get (void)
 
ALT_STATUS_CODE alt_fgpa_reset_assert (void)
 
ALT_STATUS_CODE alt_fgpa_reset_deassert (void)
 

Typedef Documentation

This type definition enumerates the possible states the FPGA can be in at any one time.

This type definition enumerates the monitored status conditions for the FPGA Control Block (CB).

Enumeration Type Documentation

This type definition enumerates the possible states the FPGA can be in at any one time.

Enumerator:
ALT_FPGA_STATE_POWER_UP 

FPGA in Power Up Phase. This is the state of the FPGA just after powering up.

ALT_FPGA_STATE_RESET 

FPGA in Reset Phase. In this phase, the FPGA resets, clears the FPGA configuration RAM bits, tri-states all FPGA user I/O pins, pulls the nSTATUS and CONF_DONE pins low, and determines the configuration mode by reading the value of the MSEL pins.

ALT_FPGA_STATE_CFG 

FPGA in Configuration Phase. This state represents the phase when the configuration bitstream is loaded into the FPGA fabric. The configuration phase is complete after the FPGA has received all the configuration data.

ALT_FPGA_STATE_INIT 

FPGA in Initialization Phase. In this state the FPGA prepares to enter User Mode. In Configuration via PCI Express (CVP), this state indicates I/O configuration has completed.

ALT_FPGA_STATE_USER_MODE 

FPGA in User Mode. In this state, the FPGA performs the function loaded during the configuration phase. The FPGA user I/O are functional as determined at design time.

ALT_FPGA_STATE_UNKNOWN 

FPGA state has not yet been determined. This only occurs briefly after reset.

ALT_FPGA_STATE_POWER_OFF 

FPGA is powered off.

This type definition enumerates the monitored status conditions for the FPGA Control Block (CB).

Enumerator:
ALT_FPGA_MON_nSTATUS 

0 if the FPGA is in Reset Phase or if the FPGA detected an error during the Configuration Phase.

ALT_FPGA_MON_CONF_DONE 

0 during the FPGA Reset Phase and 1 when the FPGA Configuration Phase is done.

ALT_FPGA_MON_INIT_DONE 

0 during the FPGA Configuration Phase and 1 when the FPGA Initialization Phase is done.

ALT_FPGA_MON_CRC_ERROR 

CRC error indicator. A 1 indicates that the FPGA detected a CRC error while in User Mode.

ALT_FPGA_MON_CVP_CONF_DONE 

Configuration via PCIe (CVP) Done indicator. A 1 indicates that CVP is done.

ALT_FPGA_MON_PR_READY 

Partial Reconfiguration ready indicator. A 1 indicates that the FPGA is ready to receive partial reconfiguration or external scrubbing data.

ALT_FPGA_MON_PR_ERROR 

Partial Reconfiguration error indicator. A 1 indicates that the FPGA detected an error during partial reconfiguration or external scrubbing.

ALT_FPGA_MON_PR_DONE 

Partial Reconfiguration done indicator. A 1 indicates partial reconfiguration or external scrubbing is done.

ALT_FPGA_MON_nCONFIG_PIN 

Value of the nCONFIG pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the nCONFIG pin. See the description of the nCONFIG field in this register to understand when the FPGA in this device pulls-down the nCONFIG pin. Logic external to this device pulls-down the nCONFIG pin to put the FPGA into the Reset Phase.

ALT_FPGA_MON_nSTATUS_PIN 

Value of the nSTATUS pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the nSTATUS pin. See the description of the nSTATUS field in this register to understand when the FPGA in this device pulls-down the nSTATUS pin. Logic external to this device pulls-down the nSTATUS pin during Configuration Phase or Initialization Phase if it detected an error.

ALT_FPGA_MON_CONF_DONE_PIN 

Value of the CONF_DONE pin. This can be pulled-down by the FPGA in this device or logic external to this device connected to the CONF_DONE pin. See the description of the CONF_DONE field in this register to understand when the FPGA in this device pulls-down the CONF_DONE pin. See FPGA documentation to determine how logic external to this device drives CONF_DONE.

ALT_FPGA_MON_FPGA_POWER_ON 

FPGA powered on indicator.

Function Documentation

ALT_STATUS_CODE alt_fpga_control_enable ( void  )

Instructs the CPU core to acquire control of the FPGA control block. This must API must be called before any other API is issued.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORError acquiring control of the FPGA control block. This is likely due to another device on the system controlling the FPGA control block or a repeat call to this API without first being released.
ALT_STATUS_CODE alt_fpga_control_disable ( void  )

Instructs the CPU core to release control of the FPGA control block. This API should be called after all FPGA related operations are completed. This will allow another device on the system to configure the FPGA.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_ERRORFailure status.
bool alt_fpga_control_is_enabled ( void  )

Returns true if the HPS currently has control of the FPGA control block and false otherwise.

Return values
trueHPS has control of the FPGA control block.
falseHPS does not have control of the FPGA control block.
ALT_FPGA_STATE_t alt_fpga_state_get ( void  )

Returns the current operational state of the FPGA fabric.

Returns
The current operational state of the FPGA.
uint32_t alt_fpga_mon_status_get ( void  )

Returns the FPGA Control Block monitor status conditions.

This function returns the current value of the FPGA Control Block monitor status conditions.

Returns
The current values of the FPGA Control Block monitor status conditions as defined by the ALT_FPGA_MON_STATUS_t mask bits. If the corresponding bit is set then the condition is asserted.
ALT_STATUS_CODE alt_fgpa_reset_assert ( void  )

Assert and hold the FPGA in reset.

This function asserts and holds the FPGA in reset. Any FPGA configuration is cleared. The FPGA must be reconfigured to resume operation.

The FPGA is reset by the assertion of the nCONFIG signal. The signal remains asserted until alt_fgpa_reset_deassert() is called.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_FPGA_PWR_OFFFPGA is not powered on.
ALT_E_FPGA_NO_SOC_CTRLSoC software is not in control of the FPGA. Use alt_fpga_control_enable() to gain control.
ALT_STATUS_CODE alt_fgpa_reset_deassert ( void  )

Deassert and release the FPGA from reset.

This function deasserts the FPGA from reset. The FPGA must be reconfigured to resume operation.

The FPGA is reset by the deassertion of the nCONFIG signal.

Return values
ALT_E_SUCCESSSuccessful status.
ALT_E_FPGA_PWR_OFFFPGA is not powered on.
ALT_E_FPGA_NO_SOC_CTRLSoC software is not in control of the FPGA. Use alt_fpga_control_enable() to gain control.