Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dmagrp_receive_interrupt_watchdog_timer

Description

Register 9 (Receive Interrupt Watchdog Timer Register)

This register, when written with non-zero value, enables the watchdog timer for the Receive Interrupt (Bit 6) of Register 5 (Status Register)

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 ALT_EMAC_DMA_RX_INT_WDT_RIWT
[31:8] R 0x0 ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8

Field : riwt

RI Watchdog Timer Count

This bit indicates the number of system clock cycles multiplied by 256 for which the watchdog timer is set. The watchdog timer gets triggered with the programmed value after the Rx DMA completes the transfer of a frame for which the RI status bit is not set because of the setting in the corresponding descriptor RDES1[31]. When the watchdog timer runs out, the RI bit is set and the timer is stopped. The watchdog timer is reset when the RI bit is set high because of automatic setting of RI as per RDES1[31] of any received frame.

Field Access Macros:

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB   0
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB   7
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH   8
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK   0x000000ff
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK   0xffffff00
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET   0x0
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : reserved_31_8

Reserved

Field Access Macros:

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_LSB   8
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_MSB   31
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_WIDTH   24
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET_MSK   0xffffff00
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_CLR_MSK   0x000000ff
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_RESET   0x0
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_GET(value)   (((value) & 0xffffff00) >> 8)
 
#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET(value)   (((value) << 8) & 0xffffff00)
 

Data Structures

struct  ALT_EMAC_DMA_RX_INT_WDT_s
 

Macros

#define ALT_EMAC_DMA_RX_INT_WDT_RESET   0x00000000
 
#define ALT_EMAC_DMA_RX_INT_WDT_OFST   0x1024
 
#define ALT_EMAC_DMA_RX_INT_WDT_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_RX_INT_WDT_s 
ALT_EMAC_DMA_RX_INT_WDT_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_RX_INT_WDT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_RX_INT_WDT.

Data Fields
uint32_t riwt: 8 ALT_EMAC_DMA_RX_INT_WDT_RIWT
const uint32_t reserved_31_8: 24 ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8

Macro Definitions

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_WIDTH   8

The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET_MSK   0x000000ff

The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_CLR_MSK   0xffffff00

The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_RESET   0x0

The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RIWT register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_EMAC_DMA_RX_INT_WDT_RIWT field value from a register.

#define ALT_EMAC_DMA_RX_INT_WDT_RIWT_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_EMAC_DMA_RX_INT_WDT_RIWT register field value suitable for setting the register.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_WIDTH   24

The width in bits of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET_MSK   0xffffff00

The mask used to set the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_CLR_MSK   0x000000ff

The mask used to clear the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_RESET   0x0

The reset value of the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_GET (   value)    (((value) & 0xffffff00) >> 8)

Extracts the ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 field value from a register.

#define ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8_SET (   value)    (((value) << 8) & 0xffffff00)

Produces a ALT_EMAC_DMA_RX_INT_WDT_RSVD_31_8 register field value suitable for setting the register.

#define ALT_EMAC_DMA_RX_INT_WDT_RESET   0x00000000

The reset value of the ALT_EMAC_DMA_RX_INT_WDT register.

#define ALT_EMAC_DMA_RX_INT_WDT_OFST   0x1024

The byte offset of the ALT_EMAC_DMA_RX_INT_WDT register from the beginning of the component.

#define ALT_EMAC_DMA_RX_INT_WDT_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_RX_INT_WDT_OFST))

The address of the ALT_EMAC_DMA_RX_INT_WDT register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_RX_INT_WDT.