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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register issues various commands.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x0 | Cmd Index |
[6] | RW | 0x0 | Response Expect |
[7] | RW | 0x0 | Response Length |
[8] | RW | 0x0 | Check Response Crc |
[9] | RW | 0x0 | Data Transfer Expected |
[10] | RW | 0x0 | Read Write |
[11] | RW | 0x0 | Transfer Mode |
[12] | RW | 0x0 | Send Auto Stop |
[13] | RW | 0x0 | Wait Previous Data Complete |
[14] | RW | 0x0 | Stop Abort Cmd |
[15] | RW | 0x0 | Send Initialization |
[20:16] | RW | 0x0 | Card Number |
[21] | RW | 0x0 | Update Clock Registers Only |
[22] | RW | 0x0 | Read CE-ATA Device |
[23] | RW | 0x0 | Command Completion Signal Expected |
[24] | RW | 0x0 | Enable Boot |
[25] | RW | 0x0 | Expect Boot Ack |
[26] | RW | 0x0 | Disable Boot |
[27] | RW | 0x0 | Boot Mode |
[28] | RW | 0x0 | Volt Switch |
[29] | RW | 0x1 | Use Hold Reg |
[30] | ??? | 0x0 | UNDEFINED |
[31] | RW | 0x0 | Start Cmd |
Field : Cmd Index - cmd_index | |
Tracks the command index number. Values from 0-31. Field Access Macros: | |
#define | ALT_SDMMC_CMD_CMD_INDEX_LSB 0 |
#define | ALT_SDMMC_CMD_CMD_INDEX_MSB 5 |
#define | ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6 |
#define | ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f |
#define | ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0 |
#define | ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0 |
#define | ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f) |
Field : Response Expect - response_expect | ||||||||||
Response expected from card. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x1 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : Response Length - response_length | ||||||||||
Provides long and short response Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : Check Response Crc - check_response_crc | ||||||||||
Some of command responses do not return valid CRC bits. Software should disable CRC checks for those commands in order to disable CRC checking by controller. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : Data Transfer Expected - data_expected | ||||||||||
Set decision on data transfer expecetd or not. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9) | |||||||||
#define | ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200) | |||||||||
Field : Read Write - read_write | ||||||||||
Read/Write from card. Don't care if no data transfer expected. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_RD_WR_E_RD 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_E_WR 0x1 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_LSB 10 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_MSB 10 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10) | |||||||||
#define | ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400) | |||||||||
Field : Transfer Mode - transfer_mode | ||||||||||
Block transfer command. Don't care if no data expected Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_LSB 11 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_MSB 11 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11) | |||||||||
#define | ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800) | |||||||||
Field : Send Auto Stop - send_auto_stop | ||||||||||
When set, SD/MMC sends stop command to SD_MMC_CEATA cards at end of data transfer. Determine the following:
Additionally, when resume is sent to resume- suspended memory access of SD-Combo card, bit should be set correctly if suspended data transfer needs send_auto_stop. Don't care if no data expected from card. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12) | |||||||||
#define | ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000) | |||||||||
Field : Wait Previous Data Complete - wait_prvdata_complete | ||||||||||
Determines when command is sent. The send command at once option is typically used to query status of card during data transfer or to stop current data transfer. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13) | |||||||||
#define | ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000) | |||||||||
Field : Stop Abort Cmd - stop_abort_cmd | ||||||||||||||||
When open-ended or predefined data transfer is in progress, and host issues stop or abort command to stop data transfer, bit should be set so that command/data state-machines of CIU can return correctly to idle state. This is also applicable for Boot mode transfers. To Abort boot mode, this bit should be set along with CMD[26] = disable_boot. Note: If abort is sent to function-number currently selected or not in data- transfer mode, then bit should be set to 0. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14) | |||||||||||||||
#define | ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000) | |||||||||||||||
Field : Send Initialization - send_initialization | ||||||||||||||||
After power on, 80 clocks must be sent to the card for initialization before sending any commands to card. Bit should be set while sending first command to card so that controller will initialize clocks before sending command to card. This bit should not be set for either of the boot modes (alternate or mandatory). Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15) | |||||||||||||||
#define | ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000) | |||||||||||||||
Field : Card Number - card_number | |
Card number in use must always be 0. Field Access Macros: | |
#define | ALT_SDMMC_CMD_CARD_NUMBER_LSB 16 |
#define | ALT_SDMMC_CMD_CARD_NUMBER_MSB 20 |
#define | ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5 |
#define | ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000 |
#define | ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff |
#define | ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0 |
#define | ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16) |
#define | ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000) |
Field : Update Clock Registers Only - update_clock_registers_only | |||||||||||||
Following register values transferred into card clock domain: CLKDIV, CLRSRC, CLKENA. Changes card clocks (change frequency, truncate off or on, and set low-frequency mode); provided in order to change clock frequency or stop clock without having to send command to cards. During normal command sequence, when update_clock_registers_only = 0, following control registers are transferred from BIU to CIU: CMD, CMDARG, TMOUT, CTYPE, BLKSIZ, BYTCNT. CIU uses new register values for new command sequence to card(s). When bit is set, there are no Command Done interrupts because no command is sent to SD_MMC_CEATA cards. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0 | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21) | ||||||||||||
#define | ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000) | ||||||||||||
Field : Read CE-ATA Device - read_ceata_device | ||||||||||||||||
Software should set this bit to indicate that CE-ATA device is being accessed for read transfer. This bit is used to disable read data timeout indication while performing CE-ATA read transfers. Maximum value of I/O transmission delay can be no less than 10 seconds. SD/MMC should not indicate read data timeout while waiting for data from CE-ATA device. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22) | |||||||||||||||
#define | ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000) | |||||||||||||||
Field : Command Completion Signal Expected - ccs_expected | ||||||||||||||||||||||
If the command expects Command Completion Signal (CCS) from the CE-ATA device, the software should set this control bit. SD/MMC sets Data Transfer Over (DTO) bit in RINTSTS register and generates interrupt to host if Data Transfer Over interrupt is not masked. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0 | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23) | |||||||||||||||||||||
#define | ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000) | |||||||||||||||||||||
Field : Enable Boot - enable_boot | ||||||||||
This bit should be set only for mandatory boot mode. When Software sets this bit along with start_cmd, CIU starts the boot sequence for the corresponding card by asserting the CMD line low. Do NOT set disable_boot and enable_boot together Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_E_END 0x1 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_LSB 24 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_MSB 24 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24) | |||||||||
#define | ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000) | |||||||||
Field : Expect Boot Ack - expect_boot_ack | ||||||||||
When Software sets this bit along with enable_boot, CIU expects a boot acknowledge start pattern of 0-1-0 from the selected card. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25) | |||||||||
#define | ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000) | |||||||||
Field : Disable Boot - disable_boot | ||||||||||
When software sets this bit along with start_cmd, CIU terminates the boot operation. Do NOT set disable_boot and enable_boot together. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_LSB 26 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_MSB 26 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26) | |||||||||
#define | ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000) | |||||||||
Field : Boot Mode - boot_mode | ||||||||||
Type of Boot Mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_LSB 27 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_MSB 27 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27) | |||||||||
#define | ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000) | |||||||||
Field : Volt Switch - volt_switch | ||||||||||
Voltage switch bit. When set must be set for CMD11 only. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28) | |||||||||
#define | ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000) | |||||||||
Field : Use Hold Reg - use_hold_reg | ||||||||||||||||
Set to one for SDR12 and SDR25 (with non-zero phase-shifted cclk_in_drv); zero phase shift is not allowed in these modes.
Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1 | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29) | |||||||||||||||
#define | ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000) | |||||||||||||||
Field : Start Cmd - start_cmd | ||||||||||
Once command is taken by CIU, bit is cleared. If Start Cmd issued host should not attempt to write to any command registers. If write is attempted, hardware lock error is set in raw interrupt register. Once command is sent and response is received from SD_MMC_CEATA cards, Command Done bit is set in raw interrupt register. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_E_START 0x1 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_LSB 31 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_MSB 31 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31) | |||||||||
#define | ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000) | |||||||||
Data Structures | |
struct | ALT_SDMMC_CMD_s |
Macros | |
#define | ALT_SDMMC_CMD_OFST 0x2c |
Typedefs | |
typedef struct ALT_SDMMC_CMD_s | ALT_SDMMC_CMD_t |
struct ALT_SDMMC_CMD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_CMD.
Data Fields | ||
---|---|---|
uint32_t | cmd_index: 6 | Cmd Index |
uint32_t | response_expect: 1 | Response Expect |
uint32_t | response_length: 1 | Response Length |
uint32_t | check_response_crc: 1 | Check Response Crc |
uint32_t | data_expected: 1 | Data Transfer Expected |
uint32_t | read_write: 1 | Read Write |
uint32_t | transfer_mode: 1 | Transfer Mode |
uint32_t | send_auto_stop: 1 | Send Auto Stop |
uint32_t | wait_prvdata_complete: 1 | Wait Previous Data Complete |
uint32_t | stop_abort_cmd: 1 | Stop Abort Cmd |
uint32_t | send_initialization: 1 | Send Initialization |
uint32_t | card_number: 5 | Card Number |
uint32_t | update_clock_registers_only: 1 | Update Clock Registers Only |
uint32_t | read_ceata_device: 1 | Read CE-ATA Device |
uint32_t | ccs_expected: 1 | Command Completion Signal Expected |
uint32_t | enable_boot: 1 | Enable Boot |
uint32_t | expect_boot_ack: 1 | Expect Boot Ack |
uint32_t | disable_boot: 1 | Disable Boot |
uint32_t | boot_mode: 1 | Boot Mode |
uint32_t | volt_switch: 1 | Volt Switch |
uint32_t | use_hold_reg: 1 | Use Hold Reg |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | start_cmd: 1 | Start Cmd |
#define ALT_SDMMC_CMD_CMD_INDEX_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field.
#define ALT_SDMMC_CMD_CMD_INDEX_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CMD_INDEX register field.
#define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6 |
The width in bits of the ALT_SDMMC_CMD_CMD_INDEX register field.
#define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f |
The mask used to set the ALT_SDMMC_CMD_CMD_INDEX register field value.
#define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_SDMMC_CMD_CMD_INDEX register field value.
#define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_CMD_INDEX register field.
#define ALT_SDMMC_CMD_CMD_INDEX_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_SDMMC_CMD_CMD_INDEX field value from a register.
#define ALT_SDMMC_CMD_CMD_INDEX_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_SDMMC_CMD_CMD_INDEX register field value suitable for setting the register.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
No response expected from card
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_EXPECT
Response expected from card
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040 |
The mask used to set the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_SDMMC_CMD_RESPONSE_EXPECT register field value.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_RESPONSE_EXPECT register field.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_SDMMC_CMD_RESPONSE_EXPECT field value from a register.
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_SDMMC_CMD_RESPONSE_EXPECT register field value suitable for setting the register.
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
Short response expected from card
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_RESPONSE_LEN
Long response expected from card
#define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field.
#define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RESPONSE_LEN register field.
#define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_RESPONSE_LEN register field.
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080 |
The mask used to set the ALT_SDMMC_CMD_RESPONSE_LEN register field value.
#define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_SDMMC_CMD_RESPONSE_LEN register field value.
#define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_RESPONSE_LEN register field.
#define ALT_SDMMC_CMD_RESPONSE_LEN_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_SDMMC_CMD_RESPONSE_LEN field value from a register.
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_SDMMC_CMD_RESPONSE_LEN register field value suitable for setting the register.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
Do not check response CRC
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_CHECK_RESPONSE_CRC
Check Response CRC
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100 |
The mask used to set the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SDMMC_CMD_CHECK_RESPONSE_CRC field value from a register.
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SDMMC_CMD_CHECK_RESPONSE_CRC register field value suitable for setting the register.
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
No data transfer expected (read/write)
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_DATA_EXPECTED
Data transfer expected (read/write)
#define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field.
#define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DATA_EXPECTED register field.
#define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_DATA_EXPECTED register field.
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200 |
The mask used to set the ALT_SDMMC_CMD_DATA_EXPECTED register field value.
#define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_SDMMC_CMD_DATA_EXPECTED register field value.
#define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_DATA_EXPECTED register field.
#define ALT_SDMMC_CMD_DATA_EXPECTED_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_SDMMC_CMD_DATA_EXPECTED field value from a register.
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_SDMMC_CMD_DATA_EXPECTED register field value suitable for setting the register.
#define ALT_SDMMC_CMD_RD_WR_E_RD 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_RD_WR
Read from card
#define ALT_SDMMC_CMD_RD_WR_E_WR 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_RD_WR
Write to card
#define ALT_SDMMC_CMD_RD_WR_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_WR register field.
#define ALT_SDMMC_CMD_RD_WR_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_WR register field.
#define ALT_SDMMC_CMD_RD_WR_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_RD_WR register field.
#define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400 |
The mask used to set the ALT_SDMMC_CMD_RD_WR register field value.
#define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_SDMMC_CMD_RD_WR register field value.
#define ALT_SDMMC_CMD_RD_WR_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_RD_WR register field.
#define ALT_SDMMC_CMD_RD_WR_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_SDMMC_CMD_RD_WR field value from a register.
#define ALT_SDMMC_CMD_RD_WR_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_SDMMC_CMD_RD_WR register field value suitable for setting the register.
#define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
Block data transfer command
#define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_TFR_MOD
Stream data transfer command
#define ALT_SDMMC_CMD_TFR_MOD_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_TFR_MOD register field.
#define ALT_SDMMC_CMD_TFR_MOD_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_TFR_MOD register field.
#define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_TFR_MOD register field.
#define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800 |
The mask used to set the ALT_SDMMC_CMD_TFR_MOD register field value.
#define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_SDMMC_CMD_TFR_MOD register field value.
#define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_TFR_MOD register field.
#define ALT_SDMMC_CMD_TFR_MOD_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_SDMMC_CMD_TFR_MOD field value from a register.
#define ALT_SDMMC_CMD_TFR_MOD_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_SDMMC_CMD_TFR_MOD register field value suitable for setting the register.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
No stop command sent at end of data transfer
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_SEND_AUTO_STOP
Send stop command at end of data transfer
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000 |
The mask used to set the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff |
The mask used to clear the ALT_SDMMC_CMD_SEND_AUTO_STOP register field value.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_SEND_AUTO_STOP register field.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_SDMMC_CMD_SEND_AUTO_STOP field value from a register.
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_SDMMC_CMD_SEND_AUTO_STOP register field value suitable for setting the register.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
Send command at once
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE
Wait for previous data transfer completion
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000 |
The mask used to set the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE field value from a register.
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE register field value suitable for setting the register.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
Don't stop or abort command to stop current data transfer in progress
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_STOP_ABT_CMD
Stop or Abort command, intended to stop current data transfer in progress
#define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_STOP_ABT_CMD register field.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_STOP_ABT_CMD register field.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000 |
The mask used to set the ALT_SDMMC_CMD_STOP_ABT_CMD register field value.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_SDMMC_CMD_STOP_ABT_CMD register field value.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_STOP_ABT_CMD register field.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_SDMMC_CMD_STOP_ABT_CMD field value from a register.
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_SDMMC_CMD_STOP_ABT_CMD register field value suitable for setting the register.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
Do not send initialization sequence (80 clocks of 1) before sending this command
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_SEND_INITIALIZATION
Send initialization sequence before sending this command
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000 |
The mask used to set the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_SDMMC_CMD_SEND_INITIALIZATION register field value.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_SEND_INITIALIZATION register field.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_SDMMC_CMD_SEND_INITIALIZATION field value from a register.
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_SDMMC_CMD_SEND_INITIALIZATION register field value suitable for setting the register.
#define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field.
#define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CARD_NUMBER register field.
#define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5 |
The width in bits of the ALT_SDMMC_CMD_CARD_NUMBER register field.
#define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000 |
The mask used to set the ALT_SDMMC_CMD_CARD_NUMBER register field value.
#define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff |
The mask used to clear the ALT_SDMMC_CMD_CARD_NUMBER register field value.
#define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_CARD_NUMBER register field.
#define ALT_SDMMC_CMD_CARD_NUMBER_GET | ( | value | ) | (((value) & 0x001f0000) >> 16) |
Extracts the ALT_SDMMC_CMD_CARD_NUMBER field value from a register.
#define ALT_SDMMC_CMD_CARD_NUMBER_SET | ( | value | ) | (((value) << 16) & 0x001f0000) |
Produces a ALT_SDMMC_CMD_CARD_NUMBER register field value suitable for setting the register.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
Normal command sequence
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY
Do not send commands, just update clock register value into card clock domain
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000 |
The mask used to set the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY field value from a register.
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY register field value suitable for setting the register.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
Host is not performing read access (RW_REG or RW_BLK) towards CE-ATA device
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_RD_CEATA_DEVICE
Host is performing read access (RW_REG or RW_BLK) towards CE-ATA device
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000 |
The mask used to set the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_RD_CEATA_DEVICE register field.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_SDMMC_CMD_RD_CEATA_DEVICE field value from a register.
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_SDMMC_CMD_RD_CEATA_DEVICE register field value suitable for setting the register.
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
Interrupts are not enabled in CE-ATA device (nIEN = 1 in ATA control register), or command does not expect CCS from device
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_CCS_EXPECTED
Interrupts are enabled in CE-ATA device (nIEN = 0), and RW_BLK command expects command completion signal from CE-ATA device
#define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field.
#define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_CCS_EXPECTED register field.
#define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_CCS_EXPECTED register field.
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000 |
The mask used to set the ALT_SDMMC_CMD_CCS_EXPECTED register field value.
#define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_SDMMC_CMD_CCS_EXPECTED register field value.
#define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_CCS_EXPECTED register field.
#define ALT_SDMMC_CMD_CCS_EXPECTED_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_SDMMC_CMD_CCS_EXPECTED field value from a register.
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_SDMMC_CMD_CCS_EXPECTED register field value suitable for setting the register.
#define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
Disable Boot
#define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_EN_BOOT
Enable Boot
#define ALT_SDMMC_CMD_EN_BOOT_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EN_BOOT register field.
#define ALT_SDMMC_CMD_EN_BOOT_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EN_BOOT register field.
#define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_EN_BOOT register field.
#define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000 |
The mask used to set the ALT_SDMMC_CMD_EN_BOOT register field value.
#define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_SDMMC_CMD_EN_BOOT register field value.
#define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_EN_BOOT register field.
#define ALT_SDMMC_CMD_EN_BOOT_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_SDMMC_CMD_EN_BOOT field value from a register.
#define ALT_SDMMC_CMD_EN_BOOT_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_SDMMC_CMD_EN_BOOT register field value suitable for setting the register.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
No Boot ACK
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_EXPECT_BOOT_ACK
Expect Boot ACK
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000 |
The mask used to set the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_SDMMC_CMD_EXPECT_BOOT_ACK field value from a register.
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_SDMMC_CMD_EXPECT_BOOT_ACK register field value suitable for setting the register.
#define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
Boot not Terminated
#define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_DIS_BOOT
Terminate Boot
#define ALT_SDMMC_CMD_DIS_BOOT_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field.
#define ALT_SDMMC_CMD_DIS_BOOT_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_DIS_BOOT register field.
#define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_DIS_BOOT register field.
#define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000 |
The mask used to set the ALT_SDMMC_CMD_DIS_BOOT register field value.
#define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_SDMMC_CMD_DIS_BOOT register field value.
#define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_DIS_BOOT register field.
#define ALT_SDMMC_CMD_DIS_BOOT_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_SDMMC_CMD_DIS_BOOT field value from a register.
#define ALT_SDMMC_CMD_DIS_BOOT_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_SDMMC_CMD_DIS_BOOT register field value suitable for setting the register.
#define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
Mandatory Boot Operation
#define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_BOOT_MOD
Alternate Boot Operation
#define ALT_SDMMC_CMD_BOOT_MOD_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field.
#define ALT_SDMMC_CMD_BOOT_MOD_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_BOOT_MOD register field.
#define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_BOOT_MOD register field.
#define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000 |
The mask used to set the ALT_SDMMC_CMD_BOOT_MOD register field value.
#define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_SDMMC_CMD_BOOT_MOD register field value.
#define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_BOOT_MOD register field.
#define ALT_SDMMC_CMD_BOOT_MOD_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_SDMMC_CMD_BOOT_MOD field value from a register.
#define ALT_SDMMC_CMD_BOOT_MOD_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_SDMMC_CMD_BOOT_MOD register field value suitable for setting the register.
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
No voltage switching - default
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_VOLT_SWITCH
Voltage switching enabled
#define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field.
#define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_VOLT_SWITCH register field.
#define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_VOLT_SWITCH register field.
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000 |
The mask used to set the ALT_SDMMC_CMD_VOLT_SWITCH register field value.
#define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff |
The mask used to clear the ALT_SDMMC_CMD_VOLT_SWITCH register field value.
#define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_VOLT_SWITCH register field.
#define ALT_SDMMC_CMD_VOLT_SWITCH_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_SDMMC_CMD_VOLT_SWITCH field value from a register.
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_SDMMC_CMD_VOLT_SWITCH register field value suitable for setting the register.
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
CMD and DATA sent to card bypassing HOLD Register
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_USE_HOLD_REG
CMD and DATA sent to card through the HOLD Register
#define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field.
#define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_USE_HOLD_REG register field.
#define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_USE_HOLD_REG register field.
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000 |
The mask used to set the ALT_SDMMC_CMD_USE_HOLD_REG register field value.
#define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff |
The mask used to clear the ALT_SDMMC_CMD_USE_HOLD_REG register field value.
#define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1 |
The reset value of the ALT_SDMMC_CMD_USE_HOLD_REG register field.
#define ALT_SDMMC_CMD_USE_HOLD_REG_GET | ( | value | ) | (((value) & 0x20000000) >> 29) |
Extracts the ALT_SDMMC_CMD_USE_HOLD_REG field value from a register.
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET | ( | value | ) | (((value) << 29) & 0x20000000) |
Produces a ALT_SDMMC_CMD_USE_HOLD_REG register field value suitable for setting the register.
#define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0 |
Enumerated value for register field ALT_SDMMC_CMD_START_CMD
No Start Cmd
#define ALT_SDMMC_CMD_START_CMD_E_START 0x1 |
Enumerated value for register field ALT_SDMMC_CMD_START_CMD
Start Cmd Issued
#define ALT_SDMMC_CMD_START_CMD_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CMD_START_CMD register field.
#define ALT_SDMMC_CMD_START_CMD_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CMD_START_CMD register field.
#define ALT_SDMMC_CMD_START_CMD_WIDTH 1 |
The width in bits of the ALT_SDMMC_CMD_START_CMD register field.
#define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000 |
The mask used to set the ALT_SDMMC_CMD_START_CMD register field value.
#define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_SDMMC_CMD_START_CMD register field value.
#define ALT_SDMMC_CMD_START_CMD_RESET 0x0 |
The reset value of the ALT_SDMMC_CMD_START_CMD register field.
#define ALT_SDMMC_CMD_START_CMD_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_SDMMC_CMD_START_CMD field value from a register.
#define ALT_SDMMC_CMD_START_CMD_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_SDMMC_CMD_START_CMD register field value suitable for setting the register.
#define ALT_SDMMC_CMD_OFST 0x2c |
The byte offset of the ALT_SDMMC_CMD register from the beginning of the component.
typedef struct ALT_SDMMC_CMD_s ALT_SDMMC_CMD_t |
The typedef declaration for register ALT_SDMMC_CMD.