Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dbgreset

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST
[1] RW 0x0 ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST
[31:2] ??? 0x0 UNDEFINED

Field : counter_zero_reset

Used for performance monitoring. Writing to this register resets the first counter. Note that this bit auto-clears after one clock cycle.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_LSB   0
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_MSB   0
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET_MSK   0x00000001
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_CLR_MSK   0xfffffffe
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET(value)   (((value) << 0) & 0x00000001)
 

Field : counter_one_reset

Used for performance monitoring. Writing to this register resets the second counter. Note that this bit auto-clears after one clock cycle.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_LSB   1
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_MSB   1
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET_MSK   0x00000002
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_CLR_MSK   0xfffffffd
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET(value)   (((value) << 1) & 0x00000002)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DBGRST_s
 

Macros

#define ALT_IO48_HMC_MMR_DBGRST_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DBGRST_OFST   0xf8
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DBGRST_s 
ALT_IO48_HMC_MMR_DBGRST_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DBGRST_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DBGRST.

Data Fields
uint32_t counter_zero_reset: 1 ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST
uint32_t counter_one_reset: 1 ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_MSB   0

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET_MSK   0x00000001

The mask used to set the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_CLR_MSK   0xfffffffe

The mask used to clear the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST field value from a register.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_IO48_HMC_MMR_DBGRST_CNTR_ZERO_RST register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_LSB   1

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_MSB   1

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET_MSK   0x00000002

The mask used to set the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_CLR_MSK   0xfffffffd

The mask used to clear the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST field value from a register.

#define ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_IO48_HMC_MMR_DBGRST_CNTR_ONE_RST register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGRST_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DBGRST register.

#define ALT_IO48_HMC_MMR_DBGRST_OFST   0xf8

The byte offset of the ALT_IO48_HMC_MMR_DBGRST register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DBGRST.