![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Hardware Configuration Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x1 | Card Type |
[5:1] | R | 0x0 | Number of Cards |
[6] | R | 0x0 | Slave Bus Type |
[9:7] | R | 0x1 | Slave Bus Data Width |
[15:10] | R | 0xc | Slave Bus Address Width |
[17:16] | R | 0x0 | DMA Interface Type |
[20:18] | R | 0x1 | Generic DMA Data Width |
[21] | R | 0x0 | FIFO RAM Location |
[22] | R | 0x1 | Implement Hold Register |
[23] | R | 0x1 | Clock False Path |
[25:24] | R | 0x0 | Number of Clock Dividers |
[26] | R | 0x0 | Area Optimized |
[27] | R | 0x0 | ALT_SDMMC_HCON_AC |
[31:28] | ??? | 0x0 | UNDEFINED |
Field : Card Type - ct | |||||||
Supported card types Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_CT_E_SDMMC 0x1 | ||||||
#define | ALT_SDMMC_HCON_CT_LSB 0 | ||||||
#define | ALT_SDMMC_HCON_CT_MSB 0 | ||||||
#define | ALT_SDMMC_HCON_CT_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_CT_SET_MSK 0x00000001 | ||||||
#define | ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe | ||||||
#define | ALT_SDMMC_HCON_CT_RESET 0x1 | ||||||
#define | ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0) | ||||||
#define | ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001) | ||||||
Field : Number of Cards - nc | |||||||
Maximum number of cards less one Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_NC_E_NUMCARD 0x0 | ||||||
#define | ALT_SDMMC_HCON_NC_LSB 1 | ||||||
#define | ALT_SDMMC_HCON_NC_MSB 5 | ||||||
#define | ALT_SDMMC_HCON_NC_WIDTH 5 | ||||||
#define | ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e | ||||||
#define | ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1 | ||||||
#define | ALT_SDMMC_HCON_NC_RESET 0x0 | ||||||
#define | ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1) | ||||||
#define | ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e) | ||||||
Field : Slave Bus Type - hbus | |||||||
Slave bus type. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_HBUS_E_APB 0x0 | ||||||
#define | ALT_SDMMC_HCON_HBUS_LSB 6 | ||||||
#define | ALT_SDMMC_HCON_HBUS_MSB 6 | ||||||
#define | ALT_SDMMC_HCON_HBUS_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040 | ||||||
#define | ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf | ||||||
#define | ALT_SDMMC_HCON_HBUS_RESET 0x0 | ||||||
#define | ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6) | ||||||
#define | ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040) | ||||||
Field : Slave Bus Data Width - hdatawidth | |||||||
Slave bus data width Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_LSB 7 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_MSB 9 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1 | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7) | ||||||
#define | ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380) | ||||||
Field : Slave Bus Address Width - haddrwidth | |||||||
Slave bus address width less one Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_LSB 10 | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_MSB 15 | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6 | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00 | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10) | ||||||
#define | ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00) | ||||||
Field : DMA Interface Type - dmaintf | ||||||||||
DMA interface type Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_LSB 16 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_MSB 17 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_WIDTH 2 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_RESET 0x0 | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16) | |||||||||
#define | ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000) | |||||||||
Field : Generic DMA Data Width - dmadatawidth | |||||||
Encodes bit width of external DMA controller interface. Doesn't apply to the SD/MMC because it has no external DMA controller interface. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1 | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18) | ||||||
#define | ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000) | ||||||
Field : FIFO RAM Location - rios | |||||||
FIFO RAM location Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0 | ||||||
#define | ALT_SDMMC_HCON_RIOS_LSB 21 | ||||||
#define | ALT_SDMMC_HCON_RIOS_MSB 21 | ||||||
#define | ALT_SDMMC_HCON_RIOS_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000 | ||||||
#define | ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff | ||||||
#define | ALT_SDMMC_HCON_RIOS_RESET 0x0 | ||||||
#define | ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21) | ||||||
#define | ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000) | ||||||
Field : Implement Hold Register - ihr | |||||||
Implement hold register Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1 | ||||||
#define | ALT_SDMMC_HCON_IHR_LSB 22 | ||||||
#define | ALT_SDMMC_HCON_IHR_MSB 22 | ||||||
#define | ALT_SDMMC_HCON_IHR_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000 | ||||||
#define | ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff | ||||||
#define | ALT_SDMMC_HCON_IHR_RESET 0x1 | ||||||
#define | ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22) | ||||||
#define | ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000) | ||||||
Field : Clock False Path - scfp | |||||||
Clock False Path Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_SCFP_E_SET 0x1 | ||||||
#define | ALT_SDMMC_HCON_SCFP_LSB 23 | ||||||
#define | ALT_SDMMC_HCON_SCFP_MSB 23 | ||||||
#define | ALT_SDMMC_HCON_SCFP_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000 | ||||||
#define | ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff | ||||||
#define | ALT_SDMMC_HCON_SCFP_RESET 0x1 | ||||||
#define | ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23) | ||||||
#define | ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000) | ||||||
Field : Number of Clock Dividers - ncd | |||||||
Number of clock dividers less one Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0 | ||||||
#define | ALT_SDMMC_HCON_NCD_LSB 24 | ||||||
#define | ALT_SDMMC_HCON_NCD_MSB 25 | ||||||
#define | ALT_SDMMC_HCON_NCD_WIDTH 2 | ||||||
#define | ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000 | ||||||
#define | ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff | ||||||
#define | ALT_SDMMC_HCON_NCD_RESET 0x0 | ||||||
#define | ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24) | ||||||
#define | ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000) | ||||||
Field : Area Optimized - aro | |||||||
Area optimized Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0 | ||||||
#define | ALT_SDMMC_HCON_ARO_LSB 26 | ||||||
#define | ALT_SDMMC_HCON_ARO_MSB 26 | ||||||
#define | ALT_SDMMC_HCON_ARO_WIDTH 1 | ||||||
#define | ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000 | ||||||
#define | ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff | ||||||
#define | ALT_SDMMC_HCON_ARO_RESET 0x0 | ||||||
#define | ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26) | ||||||
#define | ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000) | ||||||
Field : ac | |
For 64-bit Address Configuration Only - bit 27 0 - 32 bit addressing supported 1 - 64 bit address supported Field Access Macros: | |
#define | ALT_SDMMC_HCON_AC_LSB 27 |
#define | ALT_SDMMC_HCON_AC_MSB 27 |
#define | ALT_SDMMC_HCON_AC_WIDTH 1 |
#define | ALT_SDMMC_HCON_AC_SET_MSK 0x08000000 |
#define | ALT_SDMMC_HCON_AC_CLR_MSK 0xf7ffffff |
#define | ALT_SDMMC_HCON_AC_RESET 0x0 |
#define | ALT_SDMMC_HCON_AC_GET(value) (((value) & 0x08000000) >> 27) |
#define | ALT_SDMMC_HCON_AC_SET(value) (((value) << 27) & 0x08000000) |
Data Structures | |
struct | ALT_SDMMC_HCON_s |
Macros | |
#define | ALT_SDMMC_HCON_RESET 0x00c43081 |
#define | ALT_SDMMC_HCON_OFST 0x70 |
Typedefs | |
typedef struct ALT_SDMMC_HCON_s | ALT_SDMMC_HCON_t |
struct ALT_SDMMC_HCON_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_HCON.
Data Fields | ||
---|---|---|
const uint32_t | ct: 1 | Card Type |
const uint32_t | nc: 5 | Number of Cards |
const uint32_t | hbus: 1 | Slave Bus Type |
const uint32_t | hdatawidth: 3 | Slave Bus Data Width |
const uint32_t | haddrwidth: 6 | Slave Bus Address Width |
const uint32_t | dmaintf: 2 | DMA Interface Type |
const uint32_t | dmadatawidth: 3 | Generic DMA Data Width |
const uint32_t | rios: 1 | FIFO RAM Location |
const uint32_t | ihr: 1 | Implement Hold Register |
const uint32_t | scfp: 1 | Clock False Path |
const uint32_t | ncd: 2 | Number of Clock Dividers |
const uint32_t | aro: 1 | Area Optimized |
const uint32_t | ac: 1 | ALT_SDMMC_HCON_AC |
uint32_t | __pad0__: 4 | UNDEFINED |
#define ALT_SDMMC_HCON_CT_E_SDMMC 0x1 |
Enumerated value for register field ALT_SDMMC_HCON_CT
Card Type SD/MMC
#define ALT_SDMMC_HCON_CT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_CT register field.
#define ALT_SDMMC_HCON_CT_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_CT register field.
#define ALT_SDMMC_HCON_CT_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_CT register field.
#define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001 |
The mask used to set the ALT_SDMMC_HCON_CT register field value.
#define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDMMC_HCON_CT register field value.
#define ALT_SDMMC_HCON_CT_RESET 0x1 |
The reset value of the ALT_SDMMC_HCON_CT register field.
#define ALT_SDMMC_HCON_CT_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDMMC_HCON_CT field value from a register.
#define ALT_SDMMC_HCON_CT_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDMMC_HCON_CT register field value suitable for setting the register.
#define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_NC
1 Card
#define ALT_SDMMC_HCON_NC_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NC register field.
#define ALT_SDMMC_HCON_NC_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NC register field.
#define ALT_SDMMC_HCON_NC_WIDTH 5 |
The width in bits of the ALT_SDMMC_HCON_NC register field.
#define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e |
The mask used to set the ALT_SDMMC_HCON_NC register field value.
#define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1 |
The mask used to clear the ALT_SDMMC_HCON_NC register field value.
#define ALT_SDMMC_HCON_NC_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_NC register field.
#define ALT_SDMMC_HCON_NC_GET | ( | value | ) | (((value) & 0x0000003e) >> 1) |
Extracts the ALT_SDMMC_HCON_NC field value from a register.
#define ALT_SDMMC_HCON_NC_SET | ( | value | ) | (((value) << 1) & 0x0000003e) |
Produces a ALT_SDMMC_HCON_NC register field value suitable for setting the register.
#define ALT_SDMMC_HCON_HBUS_E_APB 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_HBUS
APB Bus
#define ALT_SDMMC_HCON_HBUS_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HBUS register field.
#define ALT_SDMMC_HCON_HBUS_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HBUS register field.
#define ALT_SDMMC_HCON_HBUS_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_HBUS register field.
#define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040 |
The mask used to set the ALT_SDMMC_HCON_HBUS register field value.
#define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_SDMMC_HCON_HBUS register field value.
#define ALT_SDMMC_HCON_HBUS_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_HBUS register field.
#define ALT_SDMMC_HCON_HBUS_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_SDMMC_HCON_HBUS field value from a register.
#define ALT_SDMMC_HCON_HBUS_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_SDMMC_HCON_HBUS register field value suitable for setting the register.
#define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1 |
Enumerated value for register field ALT_SDMMC_HCON_HDATAWIDTH
Width 32 Bits
#define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field.
#define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HDATAWIDTH register field.
#define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3 |
The width in bits of the ALT_SDMMC_HCON_HDATAWIDTH register field.
#define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380 |
The mask used to set the ALT_SDMMC_HCON_HDATAWIDTH register field value.
#define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f |
The mask used to clear the ALT_SDMMC_HCON_HDATAWIDTH register field value.
#define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1 |
The reset value of the ALT_SDMMC_HCON_HDATAWIDTH register field.
#define ALT_SDMMC_HCON_HDATAWIDTH_GET | ( | value | ) | (((value) & 0x00000380) >> 7) |
Extracts the ALT_SDMMC_HCON_HDATAWIDTH field value from a register.
#define ALT_SDMMC_HCON_HDATAWIDTH_SET | ( | value | ) | (((value) << 7) & 0x00000380) |
Produces a ALT_SDMMC_HCON_HDATAWIDTH register field value suitable for setting the register.
#define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc |
Enumerated value for register field ALT_SDMMC_HCON_HADDRWIDTH
Width 13 Bits
#define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field.
#define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_HADDRWIDTH register field.
#define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6 |
The width in bits of the ALT_SDMMC_HCON_HADDRWIDTH register field.
#define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00 |
The mask used to set the ALT_SDMMC_HCON_HADDRWIDTH register field value.
#define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff |
The mask used to clear the ALT_SDMMC_HCON_HADDRWIDTH register field value.
#define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc |
The reset value of the ALT_SDMMC_HCON_HADDRWIDTH register field.
#define ALT_SDMMC_HCON_HADDRWIDTH_GET | ( | value | ) | (((value) & 0x0000fc00) >> 10) |
Extracts the ALT_SDMMC_HCON_HADDRWIDTH field value from a register.
#define ALT_SDMMC_HCON_HADDRWIDTH_SET | ( | value | ) | (((value) << 10) & 0x0000fc00) |
Produces a ALT_SDMMC_HCON_HADDRWIDTH register field value suitable for setting the register.
#define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_DMAINTF
No External DMA Controller Interface (SD/MMC has its own internal DMA Controller
#define ALT_SDMMC_HCON_DMAINTF_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMAINTF register field.
#define ALT_SDMMC_HCON_DMAINTF_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMAINTF register field.
#define ALT_SDMMC_HCON_DMAINTF_WIDTH 2 |
The width in bits of the ALT_SDMMC_HCON_DMAINTF register field.
#define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000 |
The mask used to set the ALT_SDMMC_HCON_DMAINTF register field value.
#define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_SDMMC_HCON_DMAINTF register field value.
#define ALT_SDMMC_HCON_DMAINTF_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_DMAINTF register field.
#define ALT_SDMMC_HCON_DMAINTF_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_SDMMC_HCON_DMAINTF field value from a register.
#define ALT_SDMMC_HCON_DMAINTF_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_SDMMC_HCON_DMAINTF register field value suitable for setting the register.
#define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1 |
Enumerated value for register field ALT_SDMMC_HCON_DMADATAWIDTH
32-bits wide
#define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field.
#define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_DMADATAWIDTH register field.
#define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3 |
The width in bits of the ALT_SDMMC_HCON_DMADATAWIDTH register field.
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000 |
The mask used to set the ALT_SDMMC_HCON_DMADATAWIDTH register field value.
#define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff |
The mask used to clear the ALT_SDMMC_HCON_DMADATAWIDTH register field value.
#define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1 |
The reset value of the ALT_SDMMC_HCON_DMADATAWIDTH register field.
#define ALT_SDMMC_HCON_DMADATAWIDTH_GET | ( | value | ) | (((value) & 0x001c0000) >> 18) |
Extracts the ALT_SDMMC_HCON_DMADATAWIDTH field value from a register.
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET | ( | value | ) | (((value) << 18) & 0x001c0000) |
Produces a ALT_SDMMC_HCON_DMADATAWIDTH register field value suitable for setting the register.
#define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_RIOS
FIFO RAM Outside IP Core
#define ALT_SDMMC_HCON_RIOS_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_RIOS register field.
#define ALT_SDMMC_HCON_RIOS_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_RIOS register field.
#define ALT_SDMMC_HCON_RIOS_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_RIOS register field.
#define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000 |
The mask used to set the ALT_SDMMC_HCON_RIOS register field value.
#define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_SDMMC_HCON_RIOS register field value.
#define ALT_SDMMC_HCON_RIOS_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_RIOS register field.
#define ALT_SDMMC_HCON_RIOS_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_SDMMC_HCON_RIOS field value from a register.
#define ALT_SDMMC_HCON_RIOS_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_SDMMC_HCON_RIOS register field value suitable for setting the register.
#define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1 |
Enumerated value for register field ALT_SDMMC_HCON_IHR
Implements Hold Register
#define ALT_SDMMC_HCON_IHR_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_IHR register field.
#define ALT_SDMMC_HCON_IHR_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_IHR register field.
#define ALT_SDMMC_HCON_IHR_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_IHR register field.
#define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000 |
The mask used to set the ALT_SDMMC_HCON_IHR register field value.
#define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_SDMMC_HCON_IHR register field value.
#define ALT_SDMMC_HCON_IHR_RESET 0x1 |
The reset value of the ALT_SDMMC_HCON_IHR register field.
#define ALT_SDMMC_HCON_IHR_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_SDMMC_HCON_IHR field value from a register.
#define ALT_SDMMC_HCON_IHR_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_SDMMC_HCON_IHR register field value suitable for setting the register.
#define ALT_SDMMC_HCON_SCFP_E_SET 0x1 |
Enumerated value for register field ALT_SDMMC_HCON_SCFP
Clock False Path Set
#define ALT_SDMMC_HCON_SCFP_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_SCFP register field.
#define ALT_SDMMC_HCON_SCFP_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_SCFP register field.
#define ALT_SDMMC_HCON_SCFP_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_SCFP register field.
#define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000 |
The mask used to set the ALT_SDMMC_HCON_SCFP register field value.
#define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_SDMMC_HCON_SCFP register field value.
#define ALT_SDMMC_HCON_SCFP_RESET 0x1 |
The reset value of the ALT_SDMMC_HCON_SCFP register field.
#define ALT_SDMMC_HCON_SCFP_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_SDMMC_HCON_SCFP field value from a register.
#define ALT_SDMMC_HCON_SCFP_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_SDMMC_HCON_SCFP register field value suitable for setting the register.
#define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_NCD
One Clock Divider
#define ALT_SDMMC_HCON_NCD_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_NCD register field.
#define ALT_SDMMC_HCON_NCD_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_NCD register field.
#define ALT_SDMMC_HCON_NCD_WIDTH 2 |
The width in bits of the ALT_SDMMC_HCON_NCD register field.
#define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000 |
The mask used to set the ALT_SDMMC_HCON_NCD register field value.
#define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff |
The mask used to clear the ALT_SDMMC_HCON_NCD register field value.
#define ALT_SDMMC_HCON_NCD_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_NCD register field.
#define ALT_SDMMC_HCON_NCD_GET | ( | value | ) | (((value) & 0x03000000) >> 24) |
Extracts the ALT_SDMMC_HCON_NCD field value from a register.
#define ALT_SDMMC_HCON_NCD_SET | ( | value | ) | (((value) << 24) & 0x03000000) |
Produces a ALT_SDMMC_HCON_NCD register field value suitable for setting the register.
#define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0 |
Enumerated value for register field ALT_SDMMC_HCON_ARO
Not Optimized For Area
#define ALT_SDMMC_HCON_ARO_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_ARO register field.
#define ALT_SDMMC_HCON_ARO_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_ARO register field.
#define ALT_SDMMC_HCON_ARO_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_ARO register field.
#define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000 |
The mask used to set the ALT_SDMMC_HCON_ARO register field value.
#define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_SDMMC_HCON_ARO register field value.
#define ALT_SDMMC_HCON_ARO_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_ARO register field.
#define ALT_SDMMC_HCON_ARO_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_SDMMC_HCON_ARO field value from a register.
#define ALT_SDMMC_HCON_ARO_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_SDMMC_HCON_ARO register field value suitable for setting the register.
#define ALT_SDMMC_HCON_AC_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_HCON_AC register field.
#define ALT_SDMMC_HCON_AC_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_HCON_AC register field.
#define ALT_SDMMC_HCON_AC_WIDTH 1 |
The width in bits of the ALT_SDMMC_HCON_AC register field.
#define ALT_SDMMC_HCON_AC_SET_MSK 0x08000000 |
The mask used to set the ALT_SDMMC_HCON_AC register field value.
#define ALT_SDMMC_HCON_AC_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_SDMMC_HCON_AC register field value.
#define ALT_SDMMC_HCON_AC_RESET 0x0 |
The reset value of the ALT_SDMMC_HCON_AC register field.
#define ALT_SDMMC_HCON_AC_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_SDMMC_HCON_AC field value from a register.
#define ALT_SDMMC_HCON_AC_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_SDMMC_HCON_AC register field value suitable for setting the register.
#define ALT_SDMMC_HCON_RESET 0x00c43081 |
The reset value of the ALT_SDMMC_HCON register.
#define ALT_SDMMC_HCON_OFST 0x70 |
The byte offset of the ALT_SDMMC_HCON register from the beginning of the component.
typedef struct ALT_SDMMC_HCON_s ALT_SDMMC_HCON_t |
The typedef declaration for register ALT_SDMMC_HCON.