Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
Main Page
Address Space
Data Structures
Files
File List
All
Data Structures
Variables
Typedefs
Groups
alt_sdmmc.h
1
/***********************************************************************************
2
* *
3
* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
4
* *
5
* Redistribution and use in source and binary forms, with or without *
6
* modification, are permitted provided that the following conditions are met: *
7
* *
8
* 1. Redistributions of source code must retain the above copyright notice, *
9
* this list of conditions and the following disclaimer. *
10
* *
11
* 2. Redistributions in binary form must reproduce the above copyright notice, *
12
* this list of conditions and the following disclaimer in the documentation *
13
* and/or other materials provided with the distribution. *
14
* *
15
* 3. Neither the name of the copyright holder nor the names of its contributors *
16
* may be used to endorse or promote products derived from this software without *
17
* specific prior written permission. *
18
* *
19
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
20
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
21
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
22
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
23
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
24
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
25
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
26
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
27
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
28
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
29
* POSSIBILITY OF SUCH DAMAGE. *
30
* *
31
***********************************************************************************/
32
35
#ifndef __ALT_SOCAL_SDMMC_H__
36
#define __ALT_SOCAL_SDMMC_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
43
#else
/* __cplusplus */
44
#include <stdint.h>
45
#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
47
120
#define ALT_SDMMC_CTL_CTLLER_RST_E_NOCHANGE 0x0
121
126
#define ALT_SDMMC_CTL_CTLLER_RST_E_ACTIVATE 0x1
127
129
#define ALT_SDMMC_CTL_CTLLER_RST_LSB 0
130
131
#define ALT_SDMMC_CTL_CTLLER_RST_MSB 0
132
133
#define ALT_SDMMC_CTL_CTLLER_RST_WIDTH 1
134
135
#define ALT_SDMMC_CTL_CTLLER_RST_SET_MSK 0x00000001
136
137
#define ALT_SDMMC_CTL_CTLLER_RST_CLR_MSK 0xfffffffe
138
139
#define ALT_SDMMC_CTL_CTLLER_RST_RESET 0x0
140
141
#define ALT_SDMMC_CTL_CTLLER_RST_GET(value) (((value) & 0x00000001) >> 0)
142
143
#define ALT_SDMMC_CTL_CTLLER_RST_SET(value) (((value) << 0) & 0x00000001)
144
170
#define ALT_SDMMC_CTL_FIFO_RST_E_NOCHANGE 0x0
171
176
#define ALT_SDMMC_CTL_FIFO_RST_E_ACTIVATE 0x1
177
179
#define ALT_SDMMC_CTL_FIFO_RST_LSB 1
180
181
#define ALT_SDMMC_CTL_FIFO_RST_MSB 1
182
183
#define ALT_SDMMC_CTL_FIFO_RST_WIDTH 1
184
185
#define ALT_SDMMC_CTL_FIFO_RST_SET_MSK 0x00000002
186
187
#define ALT_SDMMC_CTL_FIFO_RST_CLR_MSK 0xfffffffd
188
189
#define ALT_SDMMC_CTL_FIFO_RST_RESET 0x0
190
191
#define ALT_SDMMC_CTL_FIFO_RST_GET(value) (((value) & 0x00000002) >> 1)
192
193
#define ALT_SDMMC_CTL_FIFO_RST_SET(value) (((value) << 1) & 0x00000002)
194
221
#define ALT_SDMMC_CTL_DMA_RST_E_NOCHANGE 0x0
222
227
#define ALT_SDMMC_CTL_DMA_RST_E_ACTIVATE 0x1
228
230
#define ALT_SDMMC_CTL_DMA_RST_LSB 2
231
232
#define ALT_SDMMC_CTL_DMA_RST_MSB 2
233
234
#define ALT_SDMMC_CTL_DMA_RST_WIDTH 1
235
236
#define ALT_SDMMC_CTL_DMA_RST_SET_MSK 0x00000004
237
238
#define ALT_SDMMC_CTL_DMA_RST_CLR_MSK 0xfffffffb
239
240
#define ALT_SDMMC_CTL_DMA_RST_RESET 0x0
241
242
#define ALT_SDMMC_CTL_DMA_RST_GET(value) (((value) & 0x00000004) >> 2)
243
244
#define ALT_SDMMC_CTL_DMA_RST_SET(value) (((value) << 2) & 0x00000004)
245
274
#define ALT_SDMMC_CTL_INT_EN_E_DISD 0x0
275
280
#define ALT_SDMMC_CTL_INT_EN_E_END 0x1
281
283
#define ALT_SDMMC_CTL_INT_EN_LSB 4
284
285
#define ALT_SDMMC_CTL_INT_EN_MSB 4
286
287
#define ALT_SDMMC_CTL_INT_EN_WIDTH 1
288
289
#define ALT_SDMMC_CTL_INT_EN_SET_MSK 0x00000010
290
291
#define ALT_SDMMC_CTL_INT_EN_CLR_MSK 0xffffffef
292
293
#define ALT_SDMMC_CTL_INT_EN_RESET 0x0
294
295
#define ALT_SDMMC_CTL_INT_EN_GET(value) (((value) & 0x00000010) >> 4)
296
297
#define ALT_SDMMC_CTL_INT_EN_SET(value) (((value) << 4) & 0x00000010)
298
312
#define ALT_SDMMC_CTL_DMA_EN_LSB 5
313
314
#define ALT_SDMMC_CTL_DMA_EN_MSB 5
315
316
#define ALT_SDMMC_CTL_DMA_EN_WIDTH 1
317
318
#define ALT_SDMMC_CTL_DMA_EN_SET_MSK 0x00000020
319
320
#define ALT_SDMMC_CTL_DMA_EN_CLR_MSK 0xffffffdf
321
322
#define ALT_SDMMC_CTL_DMA_EN_RESET 0x0
323
324
#define ALT_SDMMC_CTL_DMA_EN_GET(value) (((value) & 0x00000020) >> 5)
325
326
#define ALT_SDMMC_CTL_DMA_EN_SET(value) (((value) << 5) & 0x00000020)
327
352
#define ALT_SDMMC_CTL_RD_WAIT_E_DEASSERT 0x0
353
358
#define ALT_SDMMC_CTL_RD_WAIT_E_ASSERT 0x1
359
361
#define ALT_SDMMC_CTL_RD_WAIT_LSB 6
362
363
#define ALT_SDMMC_CTL_RD_WAIT_MSB 6
364
365
#define ALT_SDMMC_CTL_RD_WAIT_WIDTH 1
366
367
#define ALT_SDMMC_CTL_RD_WAIT_SET_MSK 0x00000040
368
369
#define ALT_SDMMC_CTL_RD_WAIT_CLR_MSK 0xffffffbf
370
371
#define ALT_SDMMC_CTL_RD_WAIT_RESET 0x0
372
373
#define ALT_SDMMC_CTL_RD_WAIT_GET(value) (((value) & 0x00000040) >> 6)
374
375
#define ALT_SDMMC_CTL_RD_WAIT_SET(value) (((value) << 6) & 0x00000040)
376
407
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_NOCHANGE 0x0
408
413
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_E_ACTIVATE 0x1
414
416
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_LSB 7
417
418
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_MSB 7
419
420
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_WIDTH 1
421
422
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET_MSK 0x00000080
423
424
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_CLR_MSK 0xffffff7f
425
426
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_RESET 0x0
427
428
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_GET(value) (((value) & 0x00000080) >> 7)
429
430
#define ALT_SDMMC_CTL_SEND_IRQ_RESPONSE_SET(value) (((value) << 7) & 0x00000080)
431
460
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_NOCHANGE 0x0
461
466
#define ALT_SDMMC_CTL_ABT_RD_DATA_E_ACTIVATE 0x1
467
469
#define ALT_SDMMC_CTL_ABT_RD_DATA_LSB 8
470
471
#define ALT_SDMMC_CTL_ABT_RD_DATA_MSB 8
472
473
#define ALT_SDMMC_CTL_ABT_RD_DATA_WIDTH 1
474
475
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET_MSK 0x00000100
476
477
#define ALT_SDMMC_CTL_ABT_RD_DATA_CLR_MSK 0xfffffeff
478
479
#define ALT_SDMMC_CTL_ABT_RD_DATA_RESET 0x0
480
481
#define ALT_SDMMC_CTL_ABT_RD_DATA_GET(value) (((value) & 0x00000100) >> 8)
482
483
#define ALT_SDMMC_CTL_ABT_RD_DATA_SET(value) (((value) << 8) & 0x00000100)
484
509
#define ALT_SDMMC_CTL_SEND_CCSD_E_DEASSERT 0x0
510
515
#define ALT_SDMMC_CTL_SEND_CCSD_E_ASSERT 0x1
516
518
#define ALT_SDMMC_CTL_SEND_CCSD_LSB 9
519
520
#define ALT_SDMMC_CTL_SEND_CCSD_MSB 9
521
522
#define ALT_SDMMC_CTL_SEND_CCSD_WIDTH 1
523
524
#define ALT_SDMMC_CTL_SEND_CCSD_SET_MSK 0x00000200
525
526
#define ALT_SDMMC_CTL_SEND_CCSD_CLR_MSK 0xfffffdff
527
528
#define ALT_SDMMC_CTL_SEND_CCSD_RESET 0x0
529
530
#define ALT_SDMMC_CTL_SEND_CCSD_GET(value) (((value) & 0x00000200) >> 9)
531
532
#define ALT_SDMMC_CTL_SEND_CCSD_SET(value) (((value) << 9) & 0x00000200)
533
558
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_DEASSERT 0x0
559
564
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_E_ASSERT 0x1
565
567
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_LSB 10
568
569
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_MSB 10
570
571
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_WIDTH 1
572
573
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET_MSK 0x00000400
574
575
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_CLR_MSK 0xfffffbff
576
577
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_RESET 0x0
578
579
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_GET(value) (((value) & 0x00000400) >> 10)
580
581
#define ALT_SDMMC_CTL_SEND_AUTO_STOP_CCSD_SET(value) (((value) << 10) & 0x00000400)
582
605
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_DISD 0x0
606
611
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_E_END 0x1
612
614
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_LSB 11
615
616
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_MSB 11
617
618
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_WIDTH 1
619
620
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET_MSK 0x00000800
621
622
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_CLR_MSK 0xfffff7ff
623
624
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_RESET 0x0
625
626
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_GET(value) (((value) & 0x00000800) >> 11)
627
628
#define ALT_SDMMC_CTL_CEATA_DEVICE_INT_STAT_SET(value) (((value) << 11) & 0x00000800)
629
641
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_LSB 16
642
643
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_MSB 19
644
645
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_WIDTH 4
646
647
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET_MSK 0x000f0000
648
649
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_CLR_MSK 0xfff0ffff
650
651
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_RESET 0x0
652
653
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_GET(value) (((value) & 0x000f0000) >> 16)
654
655
#define ALT_SDMMC_CTL_CARD_VOLTAGE_A_SET(value) (((value) << 16) & 0x000f0000)
656
668
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_LSB 20
669
670
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_MSB 23
671
672
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_WIDTH 4
673
674
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET_MSK 0x00f00000
675
676
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_CLR_MSK 0xff0fffff
677
678
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_RESET 0x0
679
680
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_GET(value) (((value) & 0x00f00000) >> 20)
681
682
#define ALT_SDMMC_CTL_CARD_VOLTAGE_B_SET(value) (((value) << 20) & 0x00f00000)
683
702
#define ALT_SDMMC_CTL_EN_OD_PULLUP_LSB 24
703
704
#define ALT_SDMMC_CTL_EN_OD_PULLUP_MSB 24
705
706
#define ALT_SDMMC_CTL_EN_OD_PULLUP_WIDTH 1
707
708
#define ALT_SDMMC_CTL_EN_OD_PULLUP_SET_MSK 0x01000000
709
710
#define ALT_SDMMC_CTL_EN_OD_PULLUP_CLR_MSK 0xfeffffff
711
712
#define ALT_SDMMC_CTL_EN_OD_PULLUP_RESET 0x0
713
714
#define ALT_SDMMC_CTL_EN_OD_PULLUP_GET(value) (((value) & 0x01000000) >> 24)
715
716
#define ALT_SDMMC_CTL_EN_OD_PULLUP_SET(value) (((value) << 24) & 0x01000000)
717
743
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_DISD 0x0
744
749
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_E_END 0x1
750
752
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_LSB 25
753
754
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_MSB 25
755
756
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_WIDTH 1
757
758
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET_MSK 0x02000000
759
760
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_CLR_MSK 0xfdffffff
761
762
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_RESET 0x0
763
764
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_GET(value) (((value) & 0x02000000) >> 25)
765
766
#define ALT_SDMMC_CTL_USE_INTERNAL_DMAC_SET(value) (((value) << 25) & 0x02000000)
767
768
#ifndef __ASSEMBLY__
769
779
struct
ALT_SDMMC_CTL_s
780
{
781
uint32_t
controller_reset
: 1;
782
uint32_t
fifo_reset
: 1;
783
uint32_t
dma_reset
: 1;
784
uint32_t : 1;
785
uint32_t
int_enable
: 1;
786
uint32_t
dma_enable
: 1;
787
uint32_t
read_wait
: 1;
788
uint32_t
send_irq_response
: 1;
789
uint32_t
abort_read_data
: 1;
790
uint32_t
send_ccsd
: 1;
791
uint32_t
send_auto_stop_ccsd
: 1;
792
uint32_t
ceata_device_interrupt_status
: 1;
793
uint32_t : 4;
794
uint32_t
card_voltage_a
: 4;
795
uint32_t
card_voltage_b
: 4;
796
uint32_t
enable_od_pullup
: 1;
797
uint32_t
use_internal_dmac
: 1;
798
uint32_t : 6;
799
};
800
802
typedef
volatile
struct
ALT_SDMMC_CTL_s
ALT_SDMMC_CTL_t
;
803
#endif
/* __ASSEMBLY__ */
804
806
#define ALT_SDMMC_CTL_RESET 0x00000000
807
808
#define ALT_SDMMC_CTL_OFST 0x0
809
852
#define ALT_SDMMC_PWREN_POWER_EN_E_OFF 0x0
853
858
#define ALT_SDMMC_PWREN_POWER_EN_E_ON 0x1
859
861
#define ALT_SDMMC_PWREN_POWER_EN_LSB 0
862
863
#define ALT_SDMMC_PWREN_POWER_EN_MSB 0
864
865
#define ALT_SDMMC_PWREN_POWER_EN_WIDTH 1
866
867
#define ALT_SDMMC_PWREN_POWER_EN_SET_MSK 0x00000001
868
869
#define ALT_SDMMC_PWREN_POWER_EN_CLR_MSK 0xfffffffe
870
871
#define ALT_SDMMC_PWREN_POWER_EN_RESET 0x0
872
873
#define ALT_SDMMC_PWREN_POWER_EN_GET(value) (((value) & 0x00000001) >> 0)
874
875
#define ALT_SDMMC_PWREN_POWER_EN_SET(value) (((value) << 0) & 0x00000001)
876
877
#ifndef __ASSEMBLY__
878
888
struct
ALT_SDMMC_PWREN_s
889
{
890
uint32_t
power_enable
: 1;
891
uint32_t : 31;
892
};
893
895
typedef
volatile
struct
ALT_SDMMC_PWREN_s
ALT_SDMMC_PWREN_t
;
896
#endif
/* __ASSEMBLY__ */
897
899
#define ALT_SDMMC_PWREN_RESET 0x00000000
900
901
#define ALT_SDMMC_PWREN_OFST 0x4
902
929
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB 0
930
931
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB 7
932
933
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH 8
934
935
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK 0x000000ff
936
937
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK 0xffffff00
938
939
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET 0x0
940
941
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value) (((value) & 0x000000ff) >> 0)
942
943
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value) (((value) << 0) & 0x000000ff)
944
957
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_LSB 8
958
959
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_MSB 15
960
961
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_WIDTH 8
962
963
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET_MSK 0x0000ff00
964
965
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_CLR_MSK 0xffff00ff
966
967
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_RESET 0x0
968
969
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_GET(value) (((value) & 0x0000ff00) >> 8)
970
971
#define ALT_SDMMC_CLKDIV_CLK_DIVR1_SET(value) (((value) << 8) & 0x0000ff00)
972
985
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_LSB 16
986
987
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_MSB 23
988
989
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_WIDTH 8
990
991
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET_MSK 0x00ff0000
992
993
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_CLR_MSK 0xff00ffff
994
995
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_RESET 0x0
996
997
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_GET(value) (((value) & 0x00ff0000) >> 16)
998
999
#define ALT_SDMMC_CLKDIV_CLK_DIVR2_SET(value) (((value) << 16) & 0x00ff0000)
1000
1013
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_LSB 24
1014
1015
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_MSB 31
1016
1017
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_WIDTH 8
1018
1019
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET_MSK 0xff000000
1020
1021
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_CLR_MSK 0x00ffffff
1022
1023
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_RESET 0x0
1024
1025
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_GET(value) (((value) & 0xff000000) >> 24)
1026
1027
#define ALT_SDMMC_CLKDIV_CLK_DIVR3_SET(value) (((value) << 24) & 0xff000000)
1028
1029
#ifndef __ASSEMBLY__
1030
1040
struct
ALT_SDMMC_CLKDIV_s
1041
{
1042
uint32_t
clk_divider0
: 8;
1043
const
uint32_t
clk_divider1
: 8;
1044
const
uint32_t
clk_divider2
: 8;
1045
const
uint32_t
clk_divider3
: 8;
1046
};
1047
1049
typedef
volatile
struct
ALT_SDMMC_CLKDIV_s
ALT_SDMMC_CLKDIV_t
;
1050
#endif
/* __ASSEMBLY__ */
1051
1053
#define ALT_SDMMC_CLKDIV_RESET 0x00000000
1054
1055
#define ALT_SDMMC_CLKDIV_OFST 0x8
1056
1102
#define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0
1103
1105
#define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0
1106
1107
#define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 31
1108
1109
#define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 32
1110
1111
#define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0xffffffff
1112
1113
#define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0x00000000
1114
1115
#define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0
1116
1117
#define ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0xffffffff) >> 0)
1118
1119
#define ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0xffffffff)
1120
1121
#ifndef __ASSEMBLY__
1122
1132
struct
ALT_SDMMC_CLKSRC_s
1133
{
1134
const
uint32_t
clk_source
: 32;
1135
};
1136
1138
typedef
volatile
struct
ALT_SDMMC_CLKSRC_s
ALT_SDMMC_CLKSRC_t
;
1139
#endif
/* __ASSEMBLY__ */
1140
1142
#define ALT_SDMMC_CLKSRC_RESET 0x00000000
1143
1144
#define ALT_SDMMC_CLKSRC_OFST 0xc
1145
1189
#define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0
1190
1195
#define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1
1196
1198
#define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0
1199
1200
#define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0
1201
1202
#define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1
1203
1204
#define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001
1205
1206
#define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe
1207
1208
#define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0
1209
1210
#define ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0)
1211
1212
#define ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001)
1213
1243
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0
1244
1249
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1
1250
1252
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16
1253
1254
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16
1255
1256
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1
1257
1258
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000
1259
1260
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff
1261
1262
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0
1263
1264
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16)
1265
1266
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000)
1267
1268
#ifndef __ASSEMBLY__
1269
1279
struct
ALT_SDMMC_CLKENA_s
1280
{
1281
uint32_t
cclk_enable
: 1;
1282
uint32_t : 15;
1283
uint32_t
cclk_low_power
: 1;
1284
uint32_t : 15;
1285
};
1286
1288
typedef
volatile
struct
ALT_SDMMC_CLKENA_s
ALT_SDMMC_CLKENA_t
;
1289
#endif
/* __ASSEMBLY__ */
1290
1292
#define ALT_SDMMC_CLKENA_RESET 0x00000000
1293
1294
#define ALT_SDMMC_CLKENA_OFST 0x10
1295
1320
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_LSB 0
1321
1322
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_MSB 7
1323
1324
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_WIDTH 8
1325
1326
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET_MSK 0x000000ff
1327
1328
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_CLR_MSK 0xffffff00
1329
1330
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_RESET 0x40
1331
1332
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_GET(value) (((value) & 0x000000ff) >> 0)
1333
1334
#define ALT_SDMMC_TMOUT_RESPONSE_TMO_SET(value) (((value) << 0) & 0x000000ff)
1335
1353
#define ALT_SDMMC_TMOUT_DATA_TMO_LSB 8
1354
1355
#define ALT_SDMMC_TMOUT_DATA_TMO_MSB 31
1356
1357
#define ALT_SDMMC_TMOUT_DATA_TMO_WIDTH 24
1358
1359
#define ALT_SDMMC_TMOUT_DATA_TMO_SET_MSK 0xffffff00
1360
1361
#define ALT_SDMMC_TMOUT_DATA_TMO_CLR_MSK 0x000000ff
1362
1363
#define ALT_SDMMC_TMOUT_DATA_TMO_RESET 0xffffff
1364
1365
#define ALT_SDMMC_TMOUT_DATA_TMO_GET(value) (((value) & 0xffffff00) >> 8)
1366
1367
#define ALT_SDMMC_TMOUT_DATA_TMO_SET(value) (((value) << 8) & 0xffffff00)
1368
1369
#ifndef __ASSEMBLY__
1370
1380
struct
ALT_SDMMC_TMOUT_s
1381
{
1382
uint32_t
response_timeout
: 8;
1383
uint32_t
data_timeout
: 24;
1384
};
1385
1387
typedef
volatile
struct
ALT_SDMMC_TMOUT_s
ALT_SDMMC_TMOUT_t
;
1388
#endif
/* __ASSEMBLY__ */
1389
1391
#define ALT_SDMMC_TMOUT_RESET 0xffffff40
1392
1393
#define ALT_SDMMC_TMOUT_OFST 0x14
1394
1438
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD1BIT 0x0
1439
1444
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_E_MOD4BIT 0x1
1445
1447
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_LSB 0
1448
1449
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_MSB 0
1450
1451
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_WIDTH 1
1452
1453
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET_MSK 0x00000001
1454
1455
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_CLR_MSK 0xfffffffe
1456
1457
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_RESET 0x0
1458
1459
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_GET(value) (((value) & 0x00000001) >> 0)
1460
1461
#define ALT_SDMMC_CTYPE_CARD_WIDTH2_SET(value) (((value) << 0) & 0x00000001)
1462
1489
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_NON8BIT 0x0
1490
1495
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_E_MOD8BIT 0x1
1496
1498
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_LSB 16
1499
1500
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_MSB 16
1501
1502
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_WIDTH 1
1503
1504
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET_MSK 0x00010000
1505
1506
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_CLR_MSK 0xfffeffff
1507
1508
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_RESET 0x0
1509
1510
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_GET(value) (((value) & 0x00010000) >> 16)
1511
1512
#define ALT_SDMMC_CTYPE_CARD_WIDTH1_SET(value) (((value) << 16) & 0x00010000)
1513
1514
#ifndef __ASSEMBLY__
1515
1525
struct
ALT_SDMMC_CTYPE_s
1526
{
1527
uint32_t
card_width2
: 1;
1528
uint32_t : 15;
1529
uint32_t
card_width1
: 1;
1530
uint32_t : 15;
1531
};
1532
1534
typedef
volatile
struct
ALT_SDMMC_CTYPE_s
ALT_SDMMC_CTYPE_t
;
1535
#endif
/* __ASSEMBLY__ */
1536
1538
#define ALT_SDMMC_CTYPE_RESET 0x00000000
1539
1540
#define ALT_SDMMC_CTYPE_OFST 0x18
1541
1564
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_LSB 0
1565
1566
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_MSB 15
1567
1568
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_WIDTH 16
1569
1570
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET_MSK 0x0000ffff
1571
1572
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_CLR_MSK 0xffff0000
1573
1574
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_RESET 0x200
1575
1576
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_GET(value) (((value) & 0x0000ffff) >> 0)
1577
1578
#define ALT_SDMMC_BLKSIZ_BLOCK_SIZE_SET(value) (((value) << 0) & 0x0000ffff)
1579
1580
#ifndef __ASSEMBLY__
1581
1591
struct
ALT_SDMMC_BLKSIZ_s
1592
{
1593
uint32_t
block_size
: 16;
1594
uint32_t : 16;
1595
};
1596
1598
typedef
volatile
struct
ALT_SDMMC_BLKSIZ_s
ALT_SDMMC_BLKSIZ_t
;
1599
#endif
/* __ASSEMBLY__ */
1600
1602
#define ALT_SDMMC_BLKSIZ_RESET 0x00000200
1603
1604
#define ALT_SDMMC_BLKSIZ_OFST 0x1c
1605
1632
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_LSB 0
1633
1634
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_MSB 31
1635
1636
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_WIDTH 32
1637
1638
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET_MSK 0xffffffff
1639
1640
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_CLR_MSK 0x00000000
1641
1642
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_RESET 0x200
1643
1644
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
1645
1646
#define ALT_SDMMC_BYTCNT_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
1647
1648
#ifndef __ASSEMBLY__
1649
1659
struct
ALT_SDMMC_BYTCNT_s
1660
{
1661
uint32_t
byte_count
: 32;
1662
};
1663
1665
typedef
volatile
struct
ALT_SDMMC_BYTCNT_s
ALT_SDMMC_BYTCNT_t
;
1666
#endif
/* __ASSEMBLY__ */
1667
1669
#define ALT_SDMMC_BYTCNT_RESET 0x00000200
1670
1671
#define ALT_SDMMC_BYTCNT_OFST 0x20
1672
1722
#define ALT_SDMMC_INTMSK_CD_E_MSK 0x0
1723
1728
#define ALT_SDMMC_INTMSK_CD_E_NOMSK 0x1
1729
1731
#define ALT_SDMMC_INTMSK_CD_LSB 0
1732
1733
#define ALT_SDMMC_INTMSK_CD_MSB 0
1734
1735
#define ALT_SDMMC_INTMSK_CD_WIDTH 1
1736
1737
#define ALT_SDMMC_INTMSK_CD_SET_MSK 0x00000001
1738
1739
#define ALT_SDMMC_INTMSK_CD_CLR_MSK 0xfffffffe
1740
1741
#define ALT_SDMMC_INTMSK_CD_RESET 0x0
1742
1743
#define ALT_SDMMC_INTMSK_CD_GET(value) (((value) & 0x00000001) >> 0)
1744
1745
#define ALT_SDMMC_INTMSK_CD_SET(value) (((value) << 0) & 0x00000001)
1746
1768
#define ALT_SDMMC_INTMSK_RE_E_MSK 0x0
1769
1774
#define ALT_SDMMC_INTMSK_RE_E_NOMSK 0x1
1775
1777
#define ALT_SDMMC_INTMSK_RE_LSB 1
1778
1779
#define ALT_SDMMC_INTMSK_RE_MSB 1
1780
1781
#define ALT_SDMMC_INTMSK_RE_WIDTH 1
1782
1783
#define ALT_SDMMC_INTMSK_RE_SET_MSK 0x00000002
1784
1785
#define ALT_SDMMC_INTMSK_RE_CLR_MSK 0xfffffffd
1786
1787
#define ALT_SDMMC_INTMSK_RE_RESET 0x0
1788
1789
#define ALT_SDMMC_INTMSK_RE_GET(value) (((value) & 0x00000002) >> 1)
1790
1791
#define ALT_SDMMC_INTMSK_RE_SET(value) (((value) << 1) & 0x00000002)
1792
1814
#define ALT_SDMMC_INTMSK_CMD_E_MSK 0x0
1815
1820
#define ALT_SDMMC_INTMSK_CMD_E_NOMSK 0x1
1821
1823
#define ALT_SDMMC_INTMSK_CMD_LSB 2
1824
1825
#define ALT_SDMMC_INTMSK_CMD_MSB 2
1826
1827
#define ALT_SDMMC_INTMSK_CMD_WIDTH 1
1828
1829
#define ALT_SDMMC_INTMSK_CMD_SET_MSK 0x00000004
1830
1831
#define ALT_SDMMC_INTMSK_CMD_CLR_MSK 0xfffffffb
1832
1833
#define ALT_SDMMC_INTMSK_CMD_RESET 0x0
1834
1835
#define ALT_SDMMC_INTMSK_CMD_GET(value) (((value) & 0x00000004) >> 2)
1836
1837
#define ALT_SDMMC_INTMSK_CMD_SET(value) (((value) << 2) & 0x00000004)
1838
1860
#define ALT_SDMMC_INTMSK_DTO_E_MSK 0x0
1861
1866
#define ALT_SDMMC_INTMSK_DTO_E_NOMSK 0x1
1867
1869
#define ALT_SDMMC_INTMSK_DTO_LSB 3
1870
1871
#define ALT_SDMMC_INTMSK_DTO_MSB 3
1872
1873
#define ALT_SDMMC_INTMSK_DTO_WIDTH 1
1874
1875
#define ALT_SDMMC_INTMSK_DTO_SET_MSK 0x00000008
1876
1877
#define ALT_SDMMC_INTMSK_DTO_CLR_MSK 0xfffffff7
1878
1879
#define ALT_SDMMC_INTMSK_DTO_RESET 0x0
1880
1881
#define ALT_SDMMC_INTMSK_DTO_GET(value) (((value) & 0x00000008) >> 3)
1882
1883
#define ALT_SDMMC_INTMSK_DTO_SET(value) (((value) << 3) & 0x00000008)
1884
1906
#define ALT_SDMMC_INTMSK_TXDR_E_MSK 0x0
1907
1912
#define ALT_SDMMC_INTMSK_TXDR_E_NOMSK 0x1
1913
1915
#define ALT_SDMMC_INTMSK_TXDR_LSB 4
1916
1917
#define ALT_SDMMC_INTMSK_TXDR_MSB 4
1918
1919
#define ALT_SDMMC_INTMSK_TXDR_WIDTH 1
1920
1921
#define ALT_SDMMC_INTMSK_TXDR_SET_MSK 0x00000010
1922
1923
#define ALT_SDMMC_INTMSK_TXDR_CLR_MSK 0xffffffef
1924
1925
#define ALT_SDMMC_INTMSK_TXDR_RESET 0x0
1926
1927
#define ALT_SDMMC_INTMSK_TXDR_GET(value) (((value) & 0x00000010) >> 4)
1928
1929
#define ALT_SDMMC_INTMSK_TXDR_SET(value) (((value) << 4) & 0x00000010)
1930
1952
#define ALT_SDMMC_INTMSK_RXDR_E_MSK 0x0
1953
1958
#define ALT_SDMMC_INTMSK_RXDR_E_NOMSK 0x1
1959
1961
#define ALT_SDMMC_INTMSK_RXDR_LSB 5
1962
1963
#define ALT_SDMMC_INTMSK_RXDR_MSB 5
1964
1965
#define ALT_SDMMC_INTMSK_RXDR_WIDTH 1
1966
1967
#define ALT_SDMMC_INTMSK_RXDR_SET_MSK 0x00000020
1968
1969
#define ALT_SDMMC_INTMSK_RXDR_CLR_MSK 0xffffffdf
1970
1971
#define ALT_SDMMC_INTMSK_RXDR_RESET 0x0
1972
1973
#define ALT_SDMMC_INTMSK_RXDR_GET(value) (((value) & 0x00000020) >> 5)
1974
1975
#define ALT_SDMMC_INTMSK_RXDR_SET(value) (((value) << 5) & 0x00000020)
1976
1998
#define ALT_SDMMC_INTMSK_RCRC_E_MSK 0x0
1999
2004
#define ALT_SDMMC_INTMSK_RCRC_E_NOMSK 0x1
2005
2007
#define ALT_SDMMC_INTMSK_RCRC_LSB 6
2008
2009
#define ALT_SDMMC_INTMSK_RCRC_MSB 6
2010
2011
#define ALT_SDMMC_INTMSK_RCRC_WIDTH 1
2012
2013
#define ALT_SDMMC_INTMSK_RCRC_SET_MSK 0x00000040
2014
2015
#define ALT_SDMMC_INTMSK_RCRC_CLR_MSK 0xffffffbf
2016
2017
#define ALT_SDMMC_INTMSK_RCRC_RESET 0x0
2018
2019
#define ALT_SDMMC_INTMSK_RCRC_GET(value) (((value) & 0x00000040) >> 6)
2020
2021
#define ALT_SDMMC_INTMSK_RCRC_SET(value) (((value) << 6) & 0x00000040)
2022
2044
#define ALT_SDMMC_INTMSK_DCRC_E_MSK 0x0
2045
2050
#define ALT_SDMMC_INTMSK_DCRC_E_NOMSK 0x1
2051
2053
#define ALT_SDMMC_INTMSK_DCRC_LSB 7
2054
2055
#define ALT_SDMMC_INTMSK_DCRC_MSB 7
2056
2057
#define ALT_SDMMC_INTMSK_DCRC_WIDTH 1
2058
2059
#define ALT_SDMMC_INTMSK_DCRC_SET_MSK 0x00000080
2060
2061
#define ALT_SDMMC_INTMSK_DCRC_CLR_MSK 0xffffff7f
2062
2063
#define ALT_SDMMC_INTMSK_DCRC_RESET 0x0
2064
2065
#define ALT_SDMMC_INTMSK_DCRC_GET(value) (((value) & 0x00000080) >> 7)
2066
2067
#define ALT_SDMMC_INTMSK_DCRC_SET(value) (((value) << 7) & 0x00000080)
2068
2090
#define ALT_SDMMC_INTMSK_RTO_E_MSK 0x0
2091
2096
#define ALT_SDMMC_INTMSK_RTO_E_NOMSK 0x1
2097
2099
#define ALT_SDMMC_INTMSK_RTO_LSB 8
2100
2101
#define ALT_SDMMC_INTMSK_RTO_MSB 8
2102
2103
#define ALT_SDMMC_INTMSK_RTO_WIDTH 1
2104
2105
#define ALT_SDMMC_INTMSK_RTO_SET_MSK 0x00000100
2106
2107
#define ALT_SDMMC_INTMSK_RTO_CLR_MSK 0xfffffeff
2108
2109
#define ALT_SDMMC_INTMSK_RTO_RESET 0x0
2110
2111
#define ALT_SDMMC_INTMSK_RTO_GET(value) (((value) & 0x00000100) >> 8)
2112
2113
#define ALT_SDMMC_INTMSK_RTO_SET(value) (((value) << 8) & 0x00000100)
2114
2136
#define ALT_SDMMC_INTMSK_DRT_E_MSK 0x0
2137
2142
#define ALT_SDMMC_INTMSK_DRT_E_NOMSK 0x1
2143
2145
#define ALT_SDMMC_INTMSK_DRT_LSB 9
2146
2147
#define ALT_SDMMC_INTMSK_DRT_MSB 9
2148
2149
#define ALT_SDMMC_INTMSK_DRT_WIDTH 1
2150
2151
#define ALT_SDMMC_INTMSK_DRT_SET_MSK 0x00000200
2152
2153
#define ALT_SDMMC_INTMSK_DRT_CLR_MSK 0xfffffdff
2154
2155
#define ALT_SDMMC_INTMSK_DRT_RESET 0x0
2156
2157
#define ALT_SDMMC_INTMSK_DRT_GET(value) (((value) & 0x00000200) >> 9)
2158
2159
#define ALT_SDMMC_INTMSK_DRT_SET(value) (((value) << 9) & 0x00000200)
2160
2182
#define ALT_SDMMC_INTMSK_HTO_E_MSK 0x0
2183
2188
#define ALT_SDMMC_INTMSK_HTO_E_NOMSK 0x1
2189
2191
#define ALT_SDMMC_INTMSK_HTO_LSB 10
2192
2193
#define ALT_SDMMC_INTMSK_HTO_MSB 10
2194
2195
#define ALT_SDMMC_INTMSK_HTO_WIDTH 1
2196
2197
#define ALT_SDMMC_INTMSK_HTO_SET_MSK 0x00000400
2198
2199
#define ALT_SDMMC_INTMSK_HTO_CLR_MSK 0xfffffbff
2200
2201
#define ALT_SDMMC_INTMSK_HTO_RESET 0x0
2202
2203
#define ALT_SDMMC_INTMSK_HTO_GET(value) (((value) & 0x00000400) >> 10)
2204
2205
#define ALT_SDMMC_INTMSK_HTO_SET(value) (((value) << 10) & 0x00000400)
2206
2228
#define ALT_SDMMC_INTMSK_FRUN_E_MSK 0x0
2229
2234
#define ALT_SDMMC_INTMSK_FRUN_E_NOMSK 0x1
2235
2237
#define ALT_SDMMC_INTMSK_FRUN_LSB 11
2238
2239
#define ALT_SDMMC_INTMSK_FRUN_MSB 11
2240
2241
#define ALT_SDMMC_INTMSK_FRUN_WIDTH 1
2242
2243
#define ALT_SDMMC_INTMSK_FRUN_SET_MSK 0x00000800
2244
2245
#define ALT_SDMMC_INTMSK_FRUN_CLR_MSK 0xfffff7ff
2246
2247
#define ALT_SDMMC_INTMSK_FRUN_RESET 0x0
2248
2249
#define ALT_SDMMC_INTMSK_FRUN_GET(value) (((value) & 0x00000800) >> 11)
2250
2251
#define ALT_SDMMC_INTMSK_FRUN_SET(value) (((value) << 11) & 0x00000800)
2252
2274
#define ALT_SDMMC_INTMSK_HLE_E_MSK 0x0
2275
2280
#define ALT_SDMMC_INTMSK_HLE_E_NOMSK 0x1
2281
2283
#define ALT_SDMMC_INTMSK_HLE_LSB 12
2284
2285
#define ALT_SDMMC_INTMSK_HLE_MSB 12
2286
2287
#define ALT_SDMMC_INTMSK_HLE_WIDTH 1
2288
2289
#define ALT_SDMMC_INTMSK_HLE_SET_MSK 0x00001000
2290
2291
#define ALT_SDMMC_INTMSK_HLE_CLR_MSK 0xffffefff
2292
2293
#define ALT_SDMMC_INTMSK_HLE_RESET 0x0
2294
2295
#define ALT_SDMMC_INTMSK_HLE_GET(value) (((value) & 0x00001000) >> 12)
2296
2297
#define ALT_SDMMC_INTMSK_HLE_SET(value) (((value) << 12) & 0x00001000)
2298
2320
#define ALT_SDMMC_INTMSK_SBE_E_MSK 0x0
2321
2326
#define ALT_SDMMC_INTMSK_SBE_E_NOMSK 0x1
2327
2329
#define ALT_SDMMC_INTMSK_SBE_LSB 13
2330
2331
#define ALT_SDMMC_INTMSK_SBE_MSB 13
2332
2333
#define ALT_SDMMC_INTMSK_SBE_WIDTH 1
2334
2335
#define ALT_SDMMC_INTMSK_SBE_SET_MSK 0x00002000
2336
2337
#define ALT_SDMMC_INTMSK_SBE_CLR_MSK 0xffffdfff
2338
2339
#define ALT_SDMMC_INTMSK_SBE_RESET 0x0
2340
2341
#define ALT_SDMMC_INTMSK_SBE_GET(value) (((value) & 0x00002000) >> 13)
2342
2343
#define ALT_SDMMC_INTMSK_SBE_SET(value) (((value) << 13) & 0x00002000)
2344
2366
#define ALT_SDMMC_INTMSK_ACD_E_MSK 0x0
2367
2372
#define ALT_SDMMC_INTMSK_ACD_E_NOMSK 0x1
2373
2375
#define ALT_SDMMC_INTMSK_ACD_LSB 14
2376
2377
#define ALT_SDMMC_INTMSK_ACD_MSB 14
2378
2379
#define ALT_SDMMC_INTMSK_ACD_WIDTH 1
2380
2381
#define ALT_SDMMC_INTMSK_ACD_SET_MSK 0x00004000
2382
2383
#define ALT_SDMMC_INTMSK_ACD_CLR_MSK 0xffffbfff
2384
2385
#define ALT_SDMMC_INTMSK_ACD_RESET 0x0
2386
2387
#define ALT_SDMMC_INTMSK_ACD_GET(value) (((value) & 0x00004000) >> 14)
2388
2389
#define ALT_SDMMC_INTMSK_ACD_SET(value) (((value) << 14) & 0x00004000)
2390
2412
#define ALT_SDMMC_INTMSK_EBE_E_MSK 0x0
2413
2418
#define ALT_SDMMC_INTMSK_EBE_E_NOMSK 0x1
2419
2421
#define ALT_SDMMC_INTMSK_EBE_LSB 15
2422
2423
#define ALT_SDMMC_INTMSK_EBE_MSB 15
2424
2425
#define ALT_SDMMC_INTMSK_EBE_WIDTH 1
2426
2427
#define ALT_SDMMC_INTMSK_EBE_SET_MSK 0x00008000
2428
2429
#define ALT_SDMMC_INTMSK_EBE_CLR_MSK 0xffff7fff
2430
2431
#define ALT_SDMMC_INTMSK_EBE_RESET 0x0
2432
2433
#define ALT_SDMMC_INTMSK_EBE_GET(value) (((value) & 0x00008000) >> 15)
2434
2435
#define ALT_SDMMC_INTMSK_EBE_SET(value) (((value) << 15) & 0x00008000)
2436
2463
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_DISD 0x0
2464
2469
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_E_END 0x1
2470
2472
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_LSB 16
2473
2474
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_MSB 31
2475
2476
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_WIDTH 16
2477
2478
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET_MSK 0xffff0000
2479
2480
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_CLR_MSK 0x0000ffff
2481
2482
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_RESET 0x0
2483
2484
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_GET(value) (((value) & 0xffff0000) >> 16)
2485
2486
#define ALT_SDMMC_INTMSK_SDIO_INT_MSK_SET(value) (((value) << 16) & 0xffff0000)
2487
2488
#ifndef __ASSEMBLY__
2489
2499
struct
ALT_SDMMC_INTMSK_s
2500
{
2501
uint32_t
cd
: 1;
2502
uint32_t
re
: 1;
2503
uint32_t
cmd
: 1;
2504
uint32_t
dto
: 1;
2505
uint32_t
txdr
: 1;
2506
uint32_t
rxdr
: 1;
2507
uint32_t
rcrc
: 1;
2508
uint32_t
dcrc
: 1;
2509
uint32_t
rto
: 1;
2510
uint32_t
drt
: 1;
2511
uint32_t
hto
: 1;
2512
uint32_t
frun
: 1;
2513
uint32_t
hle
: 1;
2514
uint32_t
sbe
: 1;
2515
uint32_t
acd
: 1;
2516
uint32_t
ebe
: 1;
2517
uint32_t
sdio_int_mask
: 16;
2518
};
2519
2521
typedef
volatile
struct
ALT_SDMMC_INTMSK_s
ALT_SDMMC_INTMSK_t
;
2522
#endif
/* __ASSEMBLY__ */
2523
2525
#define ALT_SDMMC_INTMSK_RESET 0x00000000
2526
2527
#define ALT_SDMMC_INTMSK_OFST 0x24
2528
2550
#define ALT_SDMMC_CMDARG_CMD_ARG_LSB 0
2551
2552
#define ALT_SDMMC_CMDARG_CMD_ARG_MSB 31
2553
2554
#define ALT_SDMMC_CMDARG_CMD_ARG_WIDTH 32
2555
2556
#define ALT_SDMMC_CMDARG_CMD_ARG_SET_MSK 0xffffffff
2557
2558
#define ALT_SDMMC_CMDARG_CMD_ARG_CLR_MSK 0x00000000
2559
2560
#define ALT_SDMMC_CMDARG_CMD_ARG_RESET 0x0
2561
2562
#define ALT_SDMMC_CMDARG_CMD_ARG_GET(value) (((value) & 0xffffffff) >> 0)
2563
2564
#define ALT_SDMMC_CMDARG_CMD_ARG_SET(value) (((value) << 0) & 0xffffffff)
2565
2566
#ifndef __ASSEMBLY__
2567
2577
struct
ALT_SDMMC_CMDARG_s
2578
{
2579
uint32_t
cmd_arg
: 32;
2580
};
2581
2583
typedef
volatile
struct
ALT_SDMMC_CMDARG_s
ALT_SDMMC_CMDARG_t
;
2584
#endif
/* __ASSEMBLY__ */
2585
2587
#define ALT_SDMMC_CMDARG_RESET 0x00000000
2588
2589
#define ALT_SDMMC_CMDARG_OFST 0x28
2590
2634
#define ALT_SDMMC_CMD_CMD_INDEX_LSB 0
2635
2636
#define ALT_SDMMC_CMD_CMD_INDEX_MSB 5
2637
2638
#define ALT_SDMMC_CMD_CMD_INDEX_WIDTH 6
2639
2640
#define ALT_SDMMC_CMD_CMD_INDEX_SET_MSK 0x0000003f
2641
2642
#define ALT_SDMMC_CMD_CMD_INDEX_CLR_MSK 0xffffffc0
2643
2644
#define ALT_SDMMC_CMD_CMD_INDEX_RESET 0x0
2645
2646
#define ALT_SDMMC_CMD_CMD_INDEX_GET(value) (((value) & 0x0000003f) >> 0)
2647
2648
#define ALT_SDMMC_CMD_CMD_INDEX_SET(value) (((value) << 0) & 0x0000003f)
2649
2672
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_RESP 0x0
2673
2678
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_E_NORESP 0x1
2679
2681
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_LSB 6
2682
2683
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_MSB 6
2684
2685
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_WIDTH 1
2686
2687
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET_MSK 0x00000040
2688
2689
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_CLR_MSK 0xffffffbf
2690
2691
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_RESET 0x0
2692
2693
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_GET(value) (((value) & 0x00000040) >> 6)
2694
2695
#define ALT_SDMMC_CMD_RESPONSE_EXPECT_SET(value) (((value) << 6) & 0x00000040)
2696
2719
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_SHORT 0x0
2720
2725
#define ALT_SDMMC_CMD_RESPONSE_LEN_E_LONG 0x1
2726
2728
#define ALT_SDMMC_CMD_RESPONSE_LEN_LSB 7
2729
2730
#define ALT_SDMMC_CMD_RESPONSE_LEN_MSB 7
2731
2732
#define ALT_SDMMC_CMD_RESPONSE_LEN_WIDTH 1
2733
2734
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET_MSK 0x00000080
2735
2736
#define ALT_SDMMC_CMD_RESPONSE_LEN_CLR_MSK 0xffffff7f
2737
2738
#define ALT_SDMMC_CMD_RESPONSE_LEN_RESET 0x0
2739
2740
#define ALT_SDMMC_CMD_RESPONSE_LEN_GET(value) (((value) & 0x00000080) >> 7)
2741
2742
#define ALT_SDMMC_CMD_RESPONSE_LEN_SET(value) (((value) << 7) & 0x00000080)
2743
2769
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_NOCHK 0x0
2770
2775
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_E_CHK 0x1
2776
2778
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_LSB 8
2779
2780
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_MSB 8
2781
2782
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_WIDTH 1
2783
2784
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET_MSK 0x00000100
2785
2786
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_CLR_MSK 0xfffffeff
2787
2788
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_RESET 0x0
2789
2790
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_GET(value) (((value) & 0x00000100) >> 8)
2791
2792
#define ALT_SDMMC_CMD_CHECK_RESPONSE_CRC_SET(value) (((value) << 8) & 0x00000100)
2793
2816
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_NODATXFEREXP 0x0
2817
2822
#define ALT_SDMMC_CMD_DATA_EXPECTED_E_DATAXFEREXP 0x1
2823
2825
#define ALT_SDMMC_CMD_DATA_EXPECTED_LSB 9
2826
2827
#define ALT_SDMMC_CMD_DATA_EXPECTED_MSB 9
2828
2829
#define ALT_SDMMC_CMD_DATA_EXPECTED_WIDTH 1
2830
2831
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET_MSK 0x00000200
2832
2833
#define ALT_SDMMC_CMD_DATA_EXPECTED_CLR_MSK 0xfffffdff
2834
2835
#define ALT_SDMMC_CMD_DATA_EXPECTED_RESET 0x0
2836
2837
#define ALT_SDMMC_CMD_DATA_EXPECTED_GET(value) (((value) & 0x00000200) >> 9)
2838
2839
#define ALT_SDMMC_CMD_DATA_EXPECTED_SET(value) (((value) << 9) & 0x00000200)
2840
2865
#define ALT_SDMMC_CMD_RD_WR_E_RD 0x0
2866
2871
#define ALT_SDMMC_CMD_RD_WR_E_WR 0x1
2872
2874
#define ALT_SDMMC_CMD_RD_WR_LSB 10
2875
2876
#define ALT_SDMMC_CMD_RD_WR_MSB 10
2877
2878
#define ALT_SDMMC_CMD_RD_WR_WIDTH 1
2879
2880
#define ALT_SDMMC_CMD_RD_WR_SET_MSK 0x00000400
2881
2882
#define ALT_SDMMC_CMD_RD_WR_CLR_MSK 0xfffffbff
2883
2884
#define ALT_SDMMC_CMD_RD_WR_RESET 0x0
2885
2886
#define ALT_SDMMC_CMD_RD_WR_GET(value) (((value) & 0x00000400) >> 10)
2887
2888
#define ALT_SDMMC_CMD_RD_WR_SET(value) (((value) << 10) & 0x00000400)
2889
2914
#define ALT_SDMMC_CMD_TFR_MOD_E_BLK 0x0
2915
2920
#define ALT_SDMMC_CMD_TFR_MOD_E_STR 0x1
2921
2923
#define ALT_SDMMC_CMD_TFR_MOD_LSB 11
2924
2925
#define ALT_SDMMC_CMD_TFR_MOD_MSB 11
2926
2927
#define ALT_SDMMC_CMD_TFR_MOD_WIDTH 1
2928
2929
#define ALT_SDMMC_CMD_TFR_MOD_SET_MSK 0x00000800
2930
2931
#define ALT_SDMMC_CMD_TFR_MOD_CLR_MSK 0xfffff7ff
2932
2933
#define ALT_SDMMC_CMD_TFR_MOD_RESET 0x0
2934
2935
#define ALT_SDMMC_CMD_TFR_MOD_GET(value) (((value) & 0x00000800) >> 11)
2936
2937
#define ALT_SDMMC_CMD_TFR_MOD_SET(value) (((value) << 11) & 0x00000800)
2938
2976
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_NOSEND 0x0
2977
2982
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_E_SEND 0x1
2983
2985
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_LSB 12
2986
2987
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_MSB 12
2988
2989
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_WIDTH 1
2990
2991
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET_MSK 0x00001000
2992
2993
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_CLR_MSK 0xffffefff
2994
2995
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_RESET 0x0
2996
2997
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_GET(value) (((value) & 0x00001000) >> 12)
2998
2999
#define ALT_SDMMC_CMD_SEND_AUTO_STOP_SET(value) (((value) << 12) & 0x00001000)
3000
3031
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_NOWAIT 0x0
3032
3037
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_E_WAIT 0x1
3038
3040
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_LSB 13
3041
3042
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_MSB 13
3043
3044
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_WIDTH 1
3045
3046
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET_MSK 0x00002000
3047
3048
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_CLR_MSK 0xffffdfff
3049
3050
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_RESET 0x0
3051
3052
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_GET(value) (((value) & 0x00002000) >> 13)
3053
3054
#define ALT_SDMMC_CMD_WAIT_PRVDATA_COMPLETE_SET(value) (((value) << 13) & 0x00002000)
3055
3094
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_NOSTOPABRT 0x0
3095
3100
#define ALT_SDMMC_CMD_STOP_ABT_CMD_E_STOPABRT 0x1
3101
3103
#define ALT_SDMMC_CMD_STOP_ABT_CMD_LSB 14
3104
3105
#define ALT_SDMMC_CMD_STOP_ABT_CMD_MSB 14
3106
3107
#define ALT_SDMMC_CMD_STOP_ABT_CMD_WIDTH 1
3108
3109
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET_MSK 0x00004000
3110
3111
#define ALT_SDMMC_CMD_STOP_ABT_CMD_CLR_MSK 0xffffbfff
3112
3113
#define ALT_SDMMC_CMD_STOP_ABT_CMD_RESET 0x0
3114
3115
#define ALT_SDMMC_CMD_STOP_ABT_CMD_GET(value) (((value) & 0x00004000) >> 14)
3116
3117
#define ALT_SDMMC_CMD_STOP_ABT_CMD_SET(value) (((value) << 14) & 0x00004000)
3118
3150
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_NOINIT 0x0
3151
3156
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_E_INIT 0x1
3157
3159
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_LSB 15
3160
3161
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_MSB 15
3162
3163
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_WIDTH 1
3164
3165
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET_MSK 0x00008000
3166
3167
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_CLR_MSK 0xffff7fff
3168
3169
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_RESET 0x0
3170
3171
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_GET(value) (((value) & 0x00008000) >> 15)
3172
3173
#define ALT_SDMMC_CMD_SEND_INITIALIZATION_SET(value) (((value) << 15) & 0x00008000)
3174
3194
#define ALT_SDMMC_CMD_CARD_NUMBER_LSB 16
3195
3196
#define ALT_SDMMC_CMD_CARD_NUMBER_MSB 20
3197
3198
#define ALT_SDMMC_CMD_CARD_NUMBER_WIDTH 5
3199
3200
#define ALT_SDMMC_CMD_CARD_NUMBER_SET_MSK 0x001f0000
3201
3202
#define ALT_SDMMC_CMD_CARD_NUMBER_CLR_MSK 0xffe0ffff
3203
3204
#define ALT_SDMMC_CMD_CARD_NUMBER_RESET 0x0
3205
3206
#define ALT_SDMMC_CMD_CARD_NUMBER_GET(value) (((value) & 0x001f0000) >> 16)
3207
3208
#define ALT_SDMMC_CMD_CARD_NUMBER_SET(value) (((value) << 16) & 0x001f0000)
3209
3246
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_NORMCMD 0x0
3247
3252
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_E_UPDATCLKREG 0x1
3253
3255
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_LSB 21
3256
3257
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_MSB 21
3258
3259
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_WIDTH 1
3260
3261
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET_MSK 0x00200000
3262
3263
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_CLR_MSK 0xffdfffff
3264
3265
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_RESET 0x0
3266
3267
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_GET(value) (((value) & 0x00200000) >> 21)
3268
3269
#define ALT_SDMMC_CMD_UPDATE_CLK_REGS_ONLY_SET(value) (((value) << 21) & 0x00200000)
3270
3305
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_NORD 0x0
3306
3311
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_E_RD 0x1
3312
3314
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_LSB 22
3315
3316
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_MSB 22
3317
3318
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_WIDTH 1
3319
3320
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET_MSK 0x00400000
3321
3322
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_CLR_MSK 0xffbfffff
3323
3324
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_RESET 0x0
3325
3326
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_GET(value) (((value) & 0x00400000) >> 22)
3327
3328
#define ALT_SDMMC_CMD_RD_CEATA_DEVICE_SET(value) (((value) << 22) & 0x00400000)
3329
3368
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_DISD 0x0
3369
3375
#define ALT_SDMMC_CMD_CCS_EXPECTED_E_END 0x1
3376
3378
#define ALT_SDMMC_CMD_CCS_EXPECTED_LSB 23
3379
3380
#define ALT_SDMMC_CMD_CCS_EXPECTED_MSB 23
3381
3382
#define ALT_SDMMC_CMD_CCS_EXPECTED_WIDTH 1
3383
3384
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET_MSK 0x00800000
3385
3386
#define ALT_SDMMC_CMD_CCS_EXPECTED_CLR_MSK 0xff7fffff
3387
3388
#define ALT_SDMMC_CMD_CCS_EXPECTED_RESET 0x0
3389
3390
#define ALT_SDMMC_CMD_CCS_EXPECTED_GET(value) (((value) & 0x00800000) >> 23)
3391
3392
#define ALT_SDMMC_CMD_CCS_EXPECTED_SET(value) (((value) << 23) & 0x00800000)
3393
3418
#define ALT_SDMMC_CMD_EN_BOOT_E_DISD 0x0
3419
3424
#define ALT_SDMMC_CMD_EN_BOOT_E_END 0x1
3425
3427
#define ALT_SDMMC_CMD_EN_BOOT_LSB 24
3428
3429
#define ALT_SDMMC_CMD_EN_BOOT_MSB 24
3430
3431
#define ALT_SDMMC_CMD_EN_BOOT_WIDTH 1
3432
3433
#define ALT_SDMMC_CMD_EN_BOOT_SET_MSK 0x01000000
3434
3435
#define ALT_SDMMC_CMD_EN_BOOT_CLR_MSK 0xfeffffff
3436
3437
#define ALT_SDMMC_CMD_EN_BOOT_RESET 0x0
3438
3439
#define ALT_SDMMC_CMD_EN_BOOT_GET(value) (((value) & 0x01000000) >> 24)
3440
3441
#define ALT_SDMMC_CMD_EN_BOOT_SET(value) (((value) << 24) & 0x01000000)
3442
3466
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_NOBOOTACK 0x0
3467
3472
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_E_BOOTACK 0x1
3473
3475
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_LSB 25
3476
3477
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_MSB 25
3478
3479
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_WIDTH 1
3480
3481
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET_MSK 0x02000000
3482
3483
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_CLR_MSK 0xfdffffff
3484
3485
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_RESET 0x0
3486
3487
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_GET(value) (((value) & 0x02000000) >> 25)
3488
3489
#define ALT_SDMMC_CMD_EXPECT_BOOT_ACK_SET(value) (((value) << 25) & 0x02000000)
3490
3512
#define ALT_SDMMC_CMD_DIS_BOOT_E_NOTERMBOOT 0x0
3513
3518
#define ALT_SDMMC_CMD_DIS_BOOT_E_TERMBOOT 0x1
3519
3521
#define ALT_SDMMC_CMD_DIS_BOOT_LSB 26
3522
3523
#define ALT_SDMMC_CMD_DIS_BOOT_MSB 26
3524
3525
#define ALT_SDMMC_CMD_DIS_BOOT_WIDTH 1
3526
3527
#define ALT_SDMMC_CMD_DIS_BOOT_SET_MSK 0x04000000
3528
3529
#define ALT_SDMMC_CMD_DIS_BOOT_CLR_MSK 0xfbffffff
3530
3531
#define ALT_SDMMC_CMD_DIS_BOOT_RESET 0x0
3532
3533
#define ALT_SDMMC_CMD_DIS_BOOT_GET(value) (((value) & 0x04000000) >> 26)
3534
3535
#define ALT_SDMMC_CMD_DIS_BOOT_SET(value) (((value) << 26) & 0x04000000)
3536
3561
#define ALT_SDMMC_CMD_BOOT_MOD_E_MANDATORY 0x0
3562
3567
#define ALT_SDMMC_CMD_BOOT_MOD_E_ALTERNATE 0x1
3568
3570
#define ALT_SDMMC_CMD_BOOT_MOD_LSB 27
3571
3572
#define ALT_SDMMC_CMD_BOOT_MOD_MSB 27
3573
3574
#define ALT_SDMMC_CMD_BOOT_MOD_WIDTH 1
3575
3576
#define ALT_SDMMC_CMD_BOOT_MOD_SET_MSK 0x08000000
3577
3578
#define ALT_SDMMC_CMD_BOOT_MOD_CLR_MSK 0xf7ffffff
3579
3580
#define ALT_SDMMC_CMD_BOOT_MOD_RESET 0x0
3581
3582
#define ALT_SDMMC_CMD_BOOT_MOD_GET(value) (((value) & 0x08000000) >> 27)
3583
3584
#define ALT_SDMMC_CMD_BOOT_MOD_SET(value) (((value) << 27) & 0x08000000)
3585
3610
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_NOVOLTSW 0x0
3611
3616
#define ALT_SDMMC_CMD_VOLT_SWITCH_E_VOLTSW 0x1
3617
3619
#define ALT_SDMMC_CMD_VOLT_SWITCH_LSB 28
3620
3621
#define ALT_SDMMC_CMD_VOLT_SWITCH_MSB 28
3622
3623
#define ALT_SDMMC_CMD_VOLT_SWITCH_WIDTH 1
3624
3625
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET_MSK 0x10000000
3626
3627
#define ALT_SDMMC_CMD_VOLT_SWITCH_CLR_MSK 0xefffffff
3628
3629
#define ALT_SDMMC_CMD_VOLT_SWITCH_RESET 0x0
3630
3631
#define ALT_SDMMC_CMD_VOLT_SWITCH_GET(value) (((value) & 0x10000000) >> 28)
3632
3633
#define ALT_SDMMC_CMD_VOLT_SWITCH_SET(value) (((value) << 28) & 0x10000000)
3634
3661
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_BYPASS 0x0
3662
3667
#define ALT_SDMMC_CMD_USE_HOLD_REG_E_NOBYPASS 0x1
3668
3670
#define ALT_SDMMC_CMD_USE_HOLD_REG_LSB 29
3671
3672
#define ALT_SDMMC_CMD_USE_HOLD_REG_MSB 29
3673
3674
#define ALT_SDMMC_CMD_USE_HOLD_REG_WIDTH 1
3675
3676
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET_MSK 0x20000000
3677
3678
#define ALT_SDMMC_CMD_USE_HOLD_REG_CLR_MSK 0xdfffffff
3679
3680
#define ALT_SDMMC_CMD_USE_HOLD_REG_RESET 0x1
3681
3682
#define ALT_SDMMC_CMD_USE_HOLD_REG_GET(value) (((value) & 0x20000000) >> 29)
3683
3684
#define ALT_SDMMC_CMD_USE_HOLD_REG_SET(value) (((value) << 29) & 0x20000000)
3685
3714
#define ALT_SDMMC_CMD_START_CMD_E_NOSTART 0x0
3715
3720
#define ALT_SDMMC_CMD_START_CMD_E_START 0x1
3721
3723
#define ALT_SDMMC_CMD_START_CMD_LSB 31
3724
3725
#define ALT_SDMMC_CMD_START_CMD_MSB 31
3726
3727
#define ALT_SDMMC_CMD_START_CMD_WIDTH 1
3728
3729
#define ALT_SDMMC_CMD_START_CMD_SET_MSK 0x80000000
3730
3731
#define ALT_SDMMC_CMD_START_CMD_CLR_MSK 0x7fffffff
3732
3733
#define ALT_SDMMC_CMD_START_CMD_RESET 0x0
3734
3735
#define ALT_SDMMC_CMD_START_CMD_GET(value) (((value) & 0x80000000) >> 31)
3736
3737
#define ALT_SDMMC_CMD_START_CMD_SET(value) (((value) << 31) & 0x80000000)
3738
3739
#ifndef __ASSEMBLY__
3740
3750
struct
ALT_SDMMC_CMD_s
3751
{
3752
uint32_t
cmd_index
: 6;
3753
uint32_t
response_expect
: 1;
3754
uint32_t
response_length
: 1;
3755
uint32_t
check_response_crc
: 1;
3756
uint32_t
data_expected
: 1;
3757
uint32_t
read_write
: 1;
3758
uint32_t
transfer_mode
: 1;
3759
uint32_t
send_auto_stop
: 1;
3760
uint32_t
wait_prvdata_complete
: 1;
3761
uint32_t
stop_abort_cmd
: 1;
3762
uint32_t
send_initialization
: 1;
3763
uint32_t
card_number
: 5;
3764
uint32_t
update_clock_registers_only
: 1;
3765
uint32_t
read_ceata_device
: 1;
3766
uint32_t
ccs_expected
: 1;
3767
uint32_t
enable_boot
: 1;
3768
uint32_t
expect_boot_ack
: 1;
3769
uint32_t
disable_boot
: 1;
3770
uint32_t
boot_mode
: 1;
3771
uint32_t
volt_switch
: 1;
3772
uint32_t
use_hold_reg
: 1;
3773
uint32_t : 1;
3774
uint32_t
start_cmd
: 1;
3775
};
3776
3778
typedef
volatile
struct
ALT_SDMMC_CMD_s
ALT_SDMMC_CMD_t
;
3779
#endif
/* __ASSEMBLY__ */
3780
3782
#define ALT_SDMMC_CMD_RESET 0x20000000
3783
3784
#define ALT_SDMMC_CMD_OFST 0x2c
3785
3807
#define ALT_SDMMC_RESP0_RESPONSE0_LSB 0
3808
3809
#define ALT_SDMMC_RESP0_RESPONSE0_MSB 31
3810
3811
#define ALT_SDMMC_RESP0_RESPONSE0_WIDTH 32
3812
3813
#define ALT_SDMMC_RESP0_RESPONSE0_SET_MSK 0xffffffff
3814
3815
#define ALT_SDMMC_RESP0_RESPONSE0_CLR_MSK 0x00000000
3816
3817
#define ALT_SDMMC_RESP0_RESPONSE0_RESET 0x0
3818
3819
#define ALT_SDMMC_RESP0_RESPONSE0_GET(value) (((value) & 0xffffffff) >> 0)
3820
3821
#define ALT_SDMMC_RESP0_RESPONSE0_SET(value) (((value) << 0) & 0xffffffff)
3822
3823
#ifndef __ASSEMBLY__
3824
3834
struct
ALT_SDMMC_RESP0_s
3835
{
3836
const
uint32_t
response0
: 32;
3837
};
3838
3840
typedef
volatile
struct
ALT_SDMMC_RESP0_s
ALT_SDMMC_RESP0_t
;
3841
#endif
/* __ASSEMBLY__ */
3842
3844
#define ALT_SDMMC_RESP0_RESET 0x00000000
3845
3846
#define ALT_SDMMC_RESP0_OFST 0x30
3847
3874
#define ALT_SDMMC_RESP1_RESPONSE1_LSB 0
3875
3876
#define ALT_SDMMC_RESP1_RESPONSE1_MSB 31
3877
3878
#define ALT_SDMMC_RESP1_RESPONSE1_WIDTH 32
3879
3880
#define ALT_SDMMC_RESP1_RESPONSE1_SET_MSK 0xffffffff
3881
3882
#define ALT_SDMMC_RESP1_RESPONSE1_CLR_MSK 0x00000000
3883
3884
#define ALT_SDMMC_RESP1_RESPONSE1_RESET 0x0
3885
3886
#define ALT_SDMMC_RESP1_RESPONSE1_GET(value) (((value) & 0xffffffff) >> 0)
3887
3888
#define ALT_SDMMC_RESP1_RESPONSE1_SET(value) (((value) << 0) & 0xffffffff)
3889
3890
#ifndef __ASSEMBLY__
3891
3901
struct
ALT_SDMMC_RESP1_s
3902
{
3903
const
uint32_t
response1
: 32;
3904
};
3905
3907
typedef
volatile
struct
ALT_SDMMC_RESP1_s
ALT_SDMMC_RESP1_t
;
3908
#endif
/* __ASSEMBLY__ */
3909
3911
#define ALT_SDMMC_RESP1_RESET 0x00000000
3912
3913
#define ALT_SDMMC_RESP1_OFST 0x34
3914
3936
#define ALT_SDMMC_RESP2_RESPONSE2_LSB 0
3937
3938
#define ALT_SDMMC_RESP2_RESPONSE2_MSB 31
3939
3940
#define ALT_SDMMC_RESP2_RESPONSE2_WIDTH 32
3941
3942
#define ALT_SDMMC_RESP2_RESPONSE2_SET_MSK 0xffffffff
3943
3944
#define ALT_SDMMC_RESP2_RESPONSE2_CLR_MSK 0x00000000
3945
3946
#define ALT_SDMMC_RESP2_RESPONSE2_RESET 0x0
3947
3948
#define ALT_SDMMC_RESP2_RESPONSE2_GET(value) (((value) & 0xffffffff) >> 0)
3949
3950
#define ALT_SDMMC_RESP2_RESPONSE2_SET(value) (((value) << 0) & 0xffffffff)
3951
3952
#ifndef __ASSEMBLY__
3953
3963
struct
ALT_SDMMC_RESP2_s
3964
{
3965
const
uint32_t
response2
: 32;
3966
};
3967
3969
typedef
volatile
struct
ALT_SDMMC_RESP2_s
ALT_SDMMC_RESP2_t
;
3970
#endif
/* __ASSEMBLY__ */
3971
3973
#define ALT_SDMMC_RESP2_RESET 0x00000000
3974
3975
#define ALT_SDMMC_RESP2_OFST 0x38
3976
3998
#define ALT_SDMMC_RESP3_RESPONSE3_LSB 0
3999
4000
#define ALT_SDMMC_RESP3_RESPONSE3_MSB 31
4001
4002
#define ALT_SDMMC_RESP3_RESPONSE3_WIDTH 32
4003
4004
#define ALT_SDMMC_RESP3_RESPONSE3_SET_MSK 0xffffffff
4005
4006
#define ALT_SDMMC_RESP3_RESPONSE3_CLR_MSK 0x00000000
4007
4008
#define ALT_SDMMC_RESP3_RESPONSE3_RESET 0x0
4009
4010
#define ALT_SDMMC_RESP3_RESPONSE3_GET(value) (((value) & 0xffffffff) >> 0)
4011
4012
#define ALT_SDMMC_RESP3_RESPONSE3_SET(value) (((value) << 0) & 0xffffffff)
4013
4014
#ifndef __ASSEMBLY__
4015
4025
struct
ALT_SDMMC_RESP3_s
4026
{
4027
const
uint32_t
response3
: 32;
4028
};
4029
4031
typedef
volatile
struct
ALT_SDMMC_RESP3_s
ALT_SDMMC_RESP3_t
;
4032
#endif
/* __ASSEMBLY__ */
4033
4035
#define ALT_SDMMC_RESP3_RESET 0x00000000
4036
4037
#define ALT_SDMMC_RESP3_OFST 0x3c
4038
4087
#define ALT_SDMMC_MINTSTS_CD_E_MSK 0x0
4088
4093
#define ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1
4094
4096
#define ALT_SDMMC_MINTSTS_CD_LSB 0
4097
4098
#define ALT_SDMMC_MINTSTS_CD_MSB 0
4099
4100
#define ALT_SDMMC_MINTSTS_CD_WIDTH 1
4101
4102
#define ALT_SDMMC_MINTSTS_CD_SET_MSK 0x00000001
4103
4104
#define ALT_SDMMC_MINTSTS_CD_CLR_MSK 0xfffffffe
4105
4106
#define ALT_SDMMC_MINTSTS_CD_RESET 0x0
4107
4108
#define ALT_SDMMC_MINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4109
4110
#define ALT_SDMMC_MINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4111
4132
#define ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0
4133
4138
#define ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1
4139
4141
#define ALT_SDMMC_MINTSTS_RESP_LSB 1
4142
4143
#define ALT_SDMMC_MINTSTS_RESP_MSB 1
4144
4145
#define ALT_SDMMC_MINTSTS_RESP_WIDTH 1
4146
4147
#define ALT_SDMMC_MINTSTS_RESP_SET_MSK 0x00000002
4148
4149
#define ALT_SDMMC_MINTSTS_RESP_CLR_MSK 0xfffffffd
4150
4151
#define ALT_SDMMC_MINTSTS_RESP_RESET 0x0
4152
4153
#define ALT_SDMMC_MINTSTS_RESP_GET(value) (((value) & 0x00000002) >> 1)
4154
4155
#define ALT_SDMMC_MINTSTS_RESP_SET(value) (((value) << 1) & 0x00000002)
4156
4177
#define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0
4178
4183
#define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1
4184
4186
#define ALT_SDMMC_MINTSTS_CMD_DONE_LSB 2
4187
4188
#define ALT_SDMMC_MINTSTS_CMD_DONE_MSB 2
4189
4190
#define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH 1
4191
4192
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK 0x00000004
4193
4194
#define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK 0xfffffffb
4195
4196
#define ALT_SDMMC_MINTSTS_CMD_DONE_RESET 0x0
4197
4198
#define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value) (((value) & 0x00000004) >> 2)
4199
4200
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value) (((value) << 2) & 0x00000004)
4201
4222
#define ALT_SDMMC_MINTSTS_DT_E_MSK 0x0
4223
4228
#define ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1
4229
4231
#define ALT_SDMMC_MINTSTS_DT_LSB 3
4232
4233
#define ALT_SDMMC_MINTSTS_DT_MSB 3
4234
4235
#define ALT_SDMMC_MINTSTS_DT_WIDTH 1
4236
4237
#define ALT_SDMMC_MINTSTS_DT_SET_MSK 0x00000008
4238
4239
#define ALT_SDMMC_MINTSTS_DT_CLR_MSK 0xfffffff7
4240
4241
#define ALT_SDMMC_MINTSTS_DT_RESET 0x0
4242
4243
#define ALT_SDMMC_MINTSTS_DT_GET(value) (((value) & 0x00000008) >> 3)
4244
4245
#define ALT_SDMMC_MINTSTS_DT_SET(value) (((value) << 3) & 0x00000008)
4246
4267
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0
4268
4273
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1
4274
4276
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB 4
4277
4278
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB 4
4279
4280
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH 1
4281
4282
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK 0x00000010
4283
4284
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK 0xffffffef
4285
4286
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET 0x0
4287
4288
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value) (((value) & 0x00000010) >> 4)
4289
4290
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value) (((value) << 4) & 0x00000010)
4291
4312
#define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0
4313
4318
#define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1
4319
4321
#define ALT_SDMMC_MINTSTS_RXFIFODR_LSB 5
4322
4323
#define ALT_SDMMC_MINTSTS_RXFIFODR_MSB 5
4324
4325
#define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH 1
4326
4327
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK 0x00000020
4328
4329
#define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK 0xffffffdf
4330
4331
#define ALT_SDMMC_MINTSTS_RXFIFODR_RESET 0x0
4332
4333
#define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value) (((value) & 0x00000020) >> 5)
4334
4335
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value) (((value) << 5) & 0x00000020)
4336
4357
#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0
4358
4363
#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1
4364
4366
#define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB 6
4367
4368
#define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB 6
4369
4370
#define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH 1
4371
4372
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK 0x00000040
4373
4374
#define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK 0xffffffbf
4375
4376
#define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET 0x0
4377
4378
#define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value) (((value) & 0x00000040) >> 6)
4379
4380
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value) (((value) << 6) & 0x00000040)
4381
4402
#define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0
4403
4408
#define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1
4409
4411
#define ALT_SDMMC_MINTSTS_DATACRCERR_LSB 7
4412
4413
#define ALT_SDMMC_MINTSTS_DATACRCERR_MSB 7
4414
4415
#define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH 1
4416
4417
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK 0x00000080
4418
4419
#define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK 0xffffff7f
4420
4421
#define ALT_SDMMC_MINTSTS_DATACRCERR_RESET 0x0
4422
4423
#define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value) (((value) & 0x00000080) >> 7)
4424
4425
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value) (((value) << 7) & 0x00000080)
4426
4447
#define ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0
4448
4453
#define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1
4454
4456
#define ALT_SDMMC_MINTSTS_RESPTO_LSB 8
4457
4458
#define ALT_SDMMC_MINTSTS_RESPTO_MSB 8
4459
4460
#define ALT_SDMMC_MINTSTS_RESPTO_WIDTH 1
4461
4462
#define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK 0x00000100
4463
4464
#define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK 0xfffffeff
4465
4466
#define ALT_SDMMC_MINTSTS_RESPTO_RESET 0x0
4467
4468
#define ALT_SDMMC_MINTSTS_RESPTO_GET(value) (((value) & 0x00000100) >> 8)
4469
4470
#define ALT_SDMMC_MINTSTS_RESPTO_SET(value) (((value) << 8) & 0x00000100)
4471
4492
#define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0
4493
4498
#define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1
4499
4501
#define ALT_SDMMC_MINTSTS_DATARDTO_LSB 9
4502
4503
#define ALT_SDMMC_MINTSTS_DATARDTO_MSB 9
4504
4505
#define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH 1
4506
4507
#define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK 0x00000200
4508
4509
#define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK 0xfffffdff
4510
4511
#define ALT_SDMMC_MINTSTS_DATARDTO_RESET 0x0
4512
4513
#define ALT_SDMMC_MINTSTS_DATARDTO_GET(value) (((value) & 0x00000200) >> 9)
4514
4515
#define ALT_SDMMC_MINTSTS_DATARDTO_SET(value) (((value) << 9) & 0x00000200)
4516
4537
#define ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0
4538
4543
#define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1
4544
4546
#define ALT_SDMMC_MINTSTS_DSHTO_LSB 10
4547
4548
#define ALT_SDMMC_MINTSTS_DSHTO_MSB 10
4549
4550
#define ALT_SDMMC_MINTSTS_DSHTO_WIDTH 1
4551
4552
#define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK 0x00000400
4553
4554
#define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK 0xfffffbff
4555
4556
#define ALT_SDMMC_MINTSTS_DSHTO_RESET 0x0
4557
4558
#define ALT_SDMMC_MINTSTS_DSHTO_GET(value) (((value) & 0x00000400) >> 10)
4559
4560
#define ALT_SDMMC_MINTSTS_DSHTO_SET(value) (((value) << 10) & 0x00000400)
4561
4582
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0
4583
4588
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1
4589
4591
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB 11
4592
4593
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB 11
4594
4595
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH 1
4596
4597
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK 0x00000800
4598
4599
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK 0xfffff7ff
4600
4601
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET 0x0
4602
4603
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value) (((value) & 0x00000800) >> 11)
4604
4605
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value) (((value) << 11) & 0x00000800)
4606
4627
#define ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0
4628
4633
#define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1
4634
4636
#define ALT_SDMMC_MINTSTS_HLWERR_LSB 12
4637
4638
#define ALT_SDMMC_MINTSTS_HLWERR_MSB 12
4639
4640
#define ALT_SDMMC_MINTSTS_HLWERR_WIDTH 1
4641
4642
#define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK 0x00001000
4643
4644
#define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK 0xffffefff
4645
4646
#define ALT_SDMMC_MINTSTS_HLWERR_RESET 0x0
4647
4648
#define ALT_SDMMC_MINTSTS_HLWERR_GET(value) (((value) & 0x00001000) >> 12)
4649
4650
#define ALT_SDMMC_MINTSTS_HLWERR_SET(value) (((value) << 12) & 0x00001000)
4651
4672
#define ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0
4673
4678
#define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1
4679
4681
#define ALT_SDMMC_MINTSTS_STRERR_LSB 13
4682
4683
#define ALT_SDMMC_MINTSTS_STRERR_MSB 13
4684
4685
#define ALT_SDMMC_MINTSTS_STRERR_WIDTH 1
4686
4687
#define ALT_SDMMC_MINTSTS_STRERR_SET_MSK 0x00002000
4688
4689
#define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK 0xffffdfff
4690
4691
#define ALT_SDMMC_MINTSTS_STRERR_RESET 0x0
4692
4693
#define ALT_SDMMC_MINTSTS_STRERR_GET(value) (((value) & 0x00002000) >> 13)
4694
4695
#define ALT_SDMMC_MINTSTS_STRERR_SET(value) (((value) << 13) & 0x00002000)
4696
4717
#define ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0
4718
4723
#define ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1
4724
4726
#define ALT_SDMMC_MINTSTS_ACD_LSB 14
4727
4728
#define ALT_SDMMC_MINTSTS_ACD_MSB 14
4729
4730
#define ALT_SDMMC_MINTSTS_ACD_WIDTH 1
4731
4732
#define ALT_SDMMC_MINTSTS_ACD_SET_MSK 0x00004000
4733
4734
#define ALT_SDMMC_MINTSTS_ACD_CLR_MSK 0xffffbfff
4735
4736
#define ALT_SDMMC_MINTSTS_ACD_RESET 0x0
4737
4738
#define ALT_SDMMC_MINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
4739
4740
#define ALT_SDMMC_MINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
4741
4762
#define ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0
4763
4768
#define ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1
4769
4771
#define ALT_SDMMC_MINTSTS_EBE_LSB 15
4772
4773
#define ALT_SDMMC_MINTSTS_EBE_MSB 15
4774
4775
#define ALT_SDMMC_MINTSTS_EBE_WIDTH 1
4776
4777
#define ALT_SDMMC_MINTSTS_EBE_SET_MSK 0x00008000
4778
4779
#define ALT_SDMMC_MINTSTS_EBE_CLR_MSK 0xffff7fff
4780
4781
#define ALT_SDMMC_MINTSTS_EBE_RESET 0x0
4782
4783
#define ALT_SDMMC_MINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
4784
4785
#define ALT_SDMMC_MINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
4786
4816
#define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0
4817
4822
#define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1
4823
4825
#define ALT_SDMMC_MINTSTS_SDIO_INT_LSB 16
4826
4827
#define ALT_SDMMC_MINTSTS_SDIO_INT_MSB 31
4828
4829
#define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH 16
4830
4831
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK 0xffff0000
4832
4833
#define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
4834
4835
#define ALT_SDMMC_MINTSTS_SDIO_INT_RESET 0x0
4836
4837
#define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
4838
4839
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
4840
4841
#ifndef __ASSEMBLY__
4842
4852
struct
ALT_SDMMC_MINTSTS_s
4853
{
4854
const
uint32_t
cd
: 1;
4855
const
uint32_t
resp
: 1;
4856
const
uint32_t
cmd_done
: 1;
4857
const
uint32_t
dt
: 1;
4858
const
uint32_t
dttxfifodr
: 1;
4859
const
uint32_t
rxfifodr
: 1;
4860
const
uint32_t
respcrcerr
: 1;
4861
const
uint32_t
datacrcerr
: 1;
4862
const
uint32_t
respto
: 1;
4863
const
uint32_t
datardto
: 1;
4864
const
uint32_t
dshto
: 1;
4865
const
uint32_t
fifoovunerr
: 1;
4866
const
uint32_t
hlwerr
: 1;
4867
const
uint32_t
strerr
: 1;
4868
const
uint32_t
acd
: 1;
4869
const
uint32_t
ebe
: 1;
4870
const
uint32_t
sdio_interrupt
: 16;
4871
};
4872
4874
typedef
volatile
struct
ALT_SDMMC_MINTSTS_s
ALT_SDMMC_MINTSTS_t
;
4875
#endif
/* __ASSEMBLY__ */
4876
4878
#define ALT_SDMMC_MINTSTS_RESET 0x00000000
4879
4880
#define ALT_SDMMC_MINTSTS_OFST 0x40
4881
4931
#define ALT_SDMMC_RINTSTS_CD_E_INACT 0x0
4932
4937
#define ALT_SDMMC_RINTSTS_CD_E_ACT 0x1
4938
4940
#define ALT_SDMMC_RINTSTS_CD_LSB 0
4941
4942
#define ALT_SDMMC_RINTSTS_CD_MSB 0
4943
4944
#define ALT_SDMMC_RINTSTS_CD_WIDTH 1
4945
4946
#define ALT_SDMMC_RINTSTS_CD_SET_MSK 0x00000001
4947
4948
#define ALT_SDMMC_RINTSTS_CD_CLR_MSK 0xfffffffe
4949
4950
#define ALT_SDMMC_RINTSTS_CD_RESET 0x0
4951
4952
#define ALT_SDMMC_RINTSTS_CD_GET(value) (((value) & 0x00000001) >> 0)
4953
4954
#define ALT_SDMMC_RINTSTS_CD_SET(value) (((value) << 0) & 0x00000001)
4955
4977
#define ALT_SDMMC_RINTSTS_RE_E_INACT 0x0
4978
4983
#define ALT_SDMMC_RINTSTS_RE_E_ACT 0x1
4984
4986
#define ALT_SDMMC_RINTSTS_RE_LSB 1
4987
4988
#define ALT_SDMMC_RINTSTS_RE_MSB 1
4989
4990
#define ALT_SDMMC_RINTSTS_RE_WIDTH 1
4991
4992
#define ALT_SDMMC_RINTSTS_RE_SET_MSK 0x00000002
4993
4994
#define ALT_SDMMC_RINTSTS_RE_CLR_MSK 0xfffffffd
4995
4996
#define ALT_SDMMC_RINTSTS_RE_RESET 0x0
4997
4998
#define ALT_SDMMC_RINTSTS_RE_GET(value) (((value) & 0x00000002) >> 1)
4999
5000
#define ALT_SDMMC_RINTSTS_RE_SET(value) (((value) << 1) & 0x00000002)
5001
5023
#define ALT_SDMMC_RINTSTS_CMD_E_INACT 0x0
5024
5029
#define ALT_SDMMC_RINTSTS_CMD_E_ACT 0x1
5030
5032
#define ALT_SDMMC_RINTSTS_CMD_LSB 2
5033
5034
#define ALT_SDMMC_RINTSTS_CMD_MSB 2
5035
5036
#define ALT_SDMMC_RINTSTS_CMD_WIDTH 1
5037
5038
#define ALT_SDMMC_RINTSTS_CMD_SET_MSK 0x00000004
5039
5040
#define ALT_SDMMC_RINTSTS_CMD_CLR_MSK 0xfffffffb
5041
5042
#define ALT_SDMMC_RINTSTS_CMD_RESET 0x0
5043
5044
#define ALT_SDMMC_RINTSTS_CMD_GET(value) (((value) & 0x00000004) >> 2)
5045
5046
#define ALT_SDMMC_RINTSTS_CMD_SET(value) (((value) << 2) & 0x00000004)
5047
5069
#define ALT_SDMMC_RINTSTS_DTO_E_INACT 0x0
5070
5075
#define ALT_SDMMC_RINTSTS_DTO_E_ACT 0x1
5076
5078
#define ALT_SDMMC_RINTSTS_DTO_LSB 3
5079
5080
#define ALT_SDMMC_RINTSTS_DTO_MSB 3
5081
5082
#define ALT_SDMMC_RINTSTS_DTO_WIDTH 1
5083
5084
#define ALT_SDMMC_RINTSTS_DTO_SET_MSK 0x00000008
5085
5086
#define ALT_SDMMC_RINTSTS_DTO_CLR_MSK 0xfffffff7
5087
5088
#define ALT_SDMMC_RINTSTS_DTO_RESET 0x0
5089
5090
#define ALT_SDMMC_RINTSTS_DTO_GET(value) (((value) & 0x00000008) >> 3)
5091
5092
#define ALT_SDMMC_RINTSTS_DTO_SET(value) (((value) << 3) & 0x00000008)
5093
5115
#define ALT_SDMMC_RINTSTS_TXDR_E_INACT 0x0
5116
5121
#define ALT_SDMMC_RINTSTS_TXDR_E_ACT 0x1
5122
5124
#define ALT_SDMMC_RINTSTS_TXDR_LSB 4
5125
5126
#define ALT_SDMMC_RINTSTS_TXDR_MSB 4
5127
5128
#define ALT_SDMMC_RINTSTS_TXDR_WIDTH 1
5129
5130
#define ALT_SDMMC_RINTSTS_TXDR_SET_MSK 0x00000010
5131
5132
#define ALT_SDMMC_RINTSTS_TXDR_CLR_MSK 0xffffffef
5133
5134
#define ALT_SDMMC_RINTSTS_TXDR_RESET 0x0
5135
5136
#define ALT_SDMMC_RINTSTS_TXDR_GET(value) (((value) & 0x00000010) >> 4)
5137
5138
#define ALT_SDMMC_RINTSTS_TXDR_SET(value) (((value) << 4) & 0x00000010)
5139
5161
#define ALT_SDMMC_RINTSTS_RXDR_E_INACT 0x0
5162
5167
#define ALT_SDMMC_RINTSTS_RXDR_E_ACT 0x1
5168
5170
#define ALT_SDMMC_RINTSTS_RXDR_LSB 5
5171
5172
#define ALT_SDMMC_RINTSTS_RXDR_MSB 5
5173
5174
#define ALT_SDMMC_RINTSTS_RXDR_WIDTH 1
5175
5176
#define ALT_SDMMC_RINTSTS_RXDR_SET_MSK 0x00000020
5177
5178
#define ALT_SDMMC_RINTSTS_RXDR_CLR_MSK 0xffffffdf
5179
5180
#define ALT_SDMMC_RINTSTS_RXDR_RESET 0x0
5181
5182
#define ALT_SDMMC_RINTSTS_RXDR_GET(value) (((value) & 0x00000020) >> 5)
5183
5184
#define ALT_SDMMC_RINTSTS_RXDR_SET(value) (((value) << 5) & 0x00000020)
5185
5207
#define ALT_SDMMC_RINTSTS_RCRC_E_INACT 0x0
5208
5213
#define ALT_SDMMC_RINTSTS_RCRC_E_ACT 0x1
5214
5216
#define ALT_SDMMC_RINTSTS_RCRC_LSB 6
5217
5218
#define ALT_SDMMC_RINTSTS_RCRC_MSB 6
5219
5220
#define ALT_SDMMC_RINTSTS_RCRC_WIDTH 1
5221
5222
#define ALT_SDMMC_RINTSTS_RCRC_SET_MSK 0x00000040
5223
5224
#define ALT_SDMMC_RINTSTS_RCRC_CLR_MSK 0xffffffbf
5225
5226
#define ALT_SDMMC_RINTSTS_RCRC_RESET 0x0
5227
5228
#define ALT_SDMMC_RINTSTS_RCRC_GET(value) (((value) & 0x00000040) >> 6)
5229
5230
#define ALT_SDMMC_RINTSTS_RCRC_SET(value) (((value) << 6) & 0x00000040)
5231
5253
#define ALT_SDMMC_RINTSTS_DCRC_E_INACT 0x0
5254
5259
#define ALT_SDMMC_RINTSTS_DCRC_E_ACT 0x1
5260
5262
#define ALT_SDMMC_RINTSTS_DCRC_LSB 7
5263
5264
#define ALT_SDMMC_RINTSTS_DCRC_MSB 7
5265
5266
#define ALT_SDMMC_RINTSTS_DCRC_WIDTH 1
5267
5268
#define ALT_SDMMC_RINTSTS_DCRC_SET_MSK 0x00000080
5269
5270
#define ALT_SDMMC_RINTSTS_DCRC_CLR_MSK 0xffffff7f
5271
5272
#define ALT_SDMMC_RINTSTS_DCRC_RESET 0x0
5273
5274
#define ALT_SDMMC_RINTSTS_DCRC_GET(value) (((value) & 0x00000080) >> 7)
5275
5276
#define ALT_SDMMC_RINTSTS_DCRC_SET(value) (((value) << 7) & 0x00000080)
5277
5300
#define ALT_SDMMC_RINTSTS_BAR_E_INACT 0x0
5301
5306
#define ALT_SDMMC_RINTSTS_BAR_E_ACT 0x1
5307
5309
#define ALT_SDMMC_RINTSTS_BAR_LSB 8
5310
5311
#define ALT_SDMMC_RINTSTS_BAR_MSB 8
5312
5313
#define ALT_SDMMC_RINTSTS_BAR_WIDTH 1
5314
5315
#define ALT_SDMMC_RINTSTS_BAR_SET_MSK 0x00000100
5316
5317
#define ALT_SDMMC_RINTSTS_BAR_CLR_MSK 0xfffffeff
5318
5319
#define ALT_SDMMC_RINTSTS_BAR_RESET 0x0
5320
5321
#define ALT_SDMMC_RINTSTS_BAR_GET(value) (((value) & 0x00000100) >> 8)
5322
5323
#define ALT_SDMMC_RINTSTS_BAR_SET(value) (((value) << 8) & 0x00000100)
5324
5347
#define ALT_SDMMC_RINTSTS_BDS_E_INACT 0x0
5348
5353
#define ALT_SDMMC_RINTSTS_BDS_E_ACT 0x1
5354
5356
#define ALT_SDMMC_RINTSTS_BDS_LSB 9
5357
5358
#define ALT_SDMMC_RINTSTS_BDS_MSB 9
5359
5360
#define ALT_SDMMC_RINTSTS_BDS_WIDTH 1
5361
5362
#define ALT_SDMMC_RINTSTS_BDS_SET_MSK 0x00000200
5363
5364
#define ALT_SDMMC_RINTSTS_BDS_CLR_MSK 0xfffffdff
5365
5366
#define ALT_SDMMC_RINTSTS_BDS_RESET 0x0
5367
5368
#define ALT_SDMMC_RINTSTS_BDS_GET(value) (((value) & 0x00000200) >> 9)
5369
5370
#define ALT_SDMMC_RINTSTS_BDS_SET(value) (((value) << 9) & 0x00000200)
5371
5395
#define ALT_SDMMC_RINTSTS_HTO_E_INACT 0x0
5396
5401
#define ALT_SDMMC_RINTSTS_HTO_E_ACT 0x1
5402
5404
#define ALT_SDMMC_RINTSTS_HTO_LSB 10
5405
5406
#define ALT_SDMMC_RINTSTS_HTO_MSB 10
5407
5408
#define ALT_SDMMC_RINTSTS_HTO_WIDTH 1
5409
5410
#define ALT_SDMMC_RINTSTS_HTO_SET_MSK 0x00000400
5411
5412
#define ALT_SDMMC_RINTSTS_HTO_CLR_MSK 0xfffffbff
5413
5414
#define ALT_SDMMC_RINTSTS_HTO_RESET 0x0
5415
5416
#define ALT_SDMMC_RINTSTS_HTO_GET(value) (((value) & 0x00000400) >> 10)
5417
5418
#define ALT_SDMMC_RINTSTS_HTO_SET(value) (((value) << 10) & 0x00000400)
5419
5441
#define ALT_SDMMC_RINTSTS_FRUN_E_INACT 0x0
5442
5447
#define ALT_SDMMC_RINTSTS_FRUN_E_ACT 0x1
5448
5450
#define ALT_SDMMC_RINTSTS_FRUN_LSB 11
5451
5452
#define ALT_SDMMC_RINTSTS_FRUN_MSB 11
5453
5454
#define ALT_SDMMC_RINTSTS_FRUN_WIDTH 1
5455
5456
#define ALT_SDMMC_RINTSTS_FRUN_SET_MSK 0x00000800
5457
5458
#define ALT_SDMMC_RINTSTS_FRUN_CLR_MSK 0xfffff7ff
5459
5460
#define ALT_SDMMC_RINTSTS_FRUN_RESET 0x0
5461
5462
#define ALT_SDMMC_RINTSTS_FRUN_GET(value) (((value) & 0x00000800) >> 11)
5463
5464
#define ALT_SDMMC_RINTSTS_FRUN_SET(value) (((value) << 11) & 0x00000800)
5465
5487
#define ALT_SDMMC_RINTSTS_HLE_E_INACT 0x0
5488
5493
#define ALT_SDMMC_RINTSTS_HLE_E_ACT 0x1
5494
5496
#define ALT_SDMMC_RINTSTS_HLE_LSB 12
5497
5498
#define ALT_SDMMC_RINTSTS_HLE_MSB 12
5499
5500
#define ALT_SDMMC_RINTSTS_HLE_WIDTH 1
5501
5502
#define ALT_SDMMC_RINTSTS_HLE_SET_MSK 0x00001000
5503
5504
#define ALT_SDMMC_RINTSTS_HLE_CLR_MSK 0xffffefff
5505
5506
#define ALT_SDMMC_RINTSTS_HLE_RESET 0x0
5507
5508
#define ALT_SDMMC_RINTSTS_HLE_GET(value) (((value) & 0x00001000) >> 12)
5509
5510
#define ALT_SDMMC_RINTSTS_HLE_SET(value) (((value) << 12) & 0x00001000)
5511
5533
#define ALT_SDMMC_RINTSTS_SBE_E_INACT 0x0
5534
5539
#define ALT_SDMMC_RINTSTS_SBE_E_ACT 0x1
5540
5542
#define ALT_SDMMC_RINTSTS_SBE_LSB 13
5543
5544
#define ALT_SDMMC_RINTSTS_SBE_MSB 13
5545
5546
#define ALT_SDMMC_RINTSTS_SBE_WIDTH 1
5547
5548
#define ALT_SDMMC_RINTSTS_SBE_SET_MSK 0x00002000
5549
5550
#define ALT_SDMMC_RINTSTS_SBE_CLR_MSK 0xffffdfff
5551
5552
#define ALT_SDMMC_RINTSTS_SBE_RESET 0x0
5553
5554
#define ALT_SDMMC_RINTSTS_SBE_GET(value) (((value) & 0x00002000) >> 13)
5555
5556
#define ALT_SDMMC_RINTSTS_SBE_SET(value) (((value) << 13) & 0x00002000)
5557
5579
#define ALT_SDMMC_RINTSTS_ACD_E_INACT 0x0
5580
5585
#define ALT_SDMMC_RINTSTS_ACD_E_ACT 0x1
5586
5588
#define ALT_SDMMC_RINTSTS_ACD_LSB 14
5589
5590
#define ALT_SDMMC_RINTSTS_ACD_MSB 14
5591
5592
#define ALT_SDMMC_RINTSTS_ACD_WIDTH 1
5593
5594
#define ALT_SDMMC_RINTSTS_ACD_SET_MSK 0x00004000
5595
5596
#define ALT_SDMMC_RINTSTS_ACD_CLR_MSK 0xffffbfff
5597
5598
#define ALT_SDMMC_RINTSTS_ACD_RESET 0x0
5599
5600
#define ALT_SDMMC_RINTSTS_ACD_GET(value) (((value) & 0x00004000) >> 14)
5601
5602
#define ALT_SDMMC_RINTSTS_ACD_SET(value) (((value) << 14) & 0x00004000)
5603
5625
#define ALT_SDMMC_RINTSTS_EBE_E_INACT 0x0
5626
5631
#define ALT_SDMMC_RINTSTS_EBE_E_ACT 0x1
5632
5634
#define ALT_SDMMC_RINTSTS_EBE_LSB 15
5635
5636
#define ALT_SDMMC_RINTSTS_EBE_MSB 15
5637
5638
#define ALT_SDMMC_RINTSTS_EBE_WIDTH 1
5639
5640
#define ALT_SDMMC_RINTSTS_EBE_SET_MSK 0x00008000
5641
5642
#define ALT_SDMMC_RINTSTS_EBE_CLR_MSK 0xffff7fff
5643
5644
#define ALT_SDMMC_RINTSTS_EBE_RESET 0x0
5645
5646
#define ALT_SDMMC_RINTSTS_EBE_GET(value) (((value) & 0x00008000) >> 15)
5647
5648
#define ALT_SDMMC_RINTSTS_EBE_SET(value) (((value) << 15) & 0x00008000)
5649
5680
#define ALT_SDMMC_RINTSTS_SDIO_INT_E_INACT 0x0
5681
5686
#define ALT_SDMMC_RINTSTS_SDIO_INT_E_ACT 0x1
5687
5689
#define ALT_SDMMC_RINTSTS_SDIO_INT_LSB 16
5690
5691
#define ALT_SDMMC_RINTSTS_SDIO_INT_MSB 31
5692
5693
#define ALT_SDMMC_RINTSTS_SDIO_INT_WIDTH 16
5694
5695
#define ALT_SDMMC_RINTSTS_SDIO_INT_SET_MSK 0xffff0000
5696
5697
#define ALT_SDMMC_RINTSTS_SDIO_INT_CLR_MSK 0x0000ffff
5698
5699
#define ALT_SDMMC_RINTSTS_SDIO_INT_RESET 0x0
5700
5701
#define ALT_SDMMC_RINTSTS_SDIO_INT_GET(value) (((value) & 0xffff0000) >> 16)
5702
5703
#define ALT_SDMMC_RINTSTS_SDIO_INT_SET(value) (((value) << 16) & 0xffff0000)
5704
5705
#ifndef __ASSEMBLY__
5706
5716
struct
ALT_SDMMC_RINTSTS_s
5717
{
5718
uint32_t
cd
: 1;
5719
uint32_t
re
: 1;
5720
uint32_t
cmd
: 1;
5721
uint32_t
dto
: 1;
5722
uint32_t
txdr
: 1;
5723
uint32_t
rxdr
: 1;
5724
uint32_t
rcrc
: 1;
5725
uint32_t
dcrc
: 1;
5726
uint32_t
bar
: 1;
5727
uint32_t
bds
: 1;
5728
uint32_t
hto
: 1;
5729
uint32_t
frun
: 1;
5730
uint32_t
hle
: 1;
5731
uint32_t
sbe
: 1;
5732
uint32_t
acd
: 1;
5733
uint32_t
ebe
: 1;
5734
uint32_t
sdio_interrupt
: 16;
5735
};
5736
5738
typedef
volatile
struct
ALT_SDMMC_RINTSTS_s
ALT_SDMMC_RINTSTS_t
;
5739
#endif
/* __ASSEMBLY__ */
5740
5742
#define ALT_SDMMC_RINTSTS_RESET 0x00000000
5743
5744
#define ALT_SDMMC_RINTSTS_OFST 0x44
5745
5792
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_RXWATERMARK 0x0
5793
5798
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_E_NORXWATERMARK 0x1
5799
5801
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_LSB 0
5802
5803
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_MSB 0
5804
5805
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_WIDTH 1
5806
5807
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET_MSK 0x00000001
5808
5809
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_CLR_MSK 0xfffffffe
5810
5811
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_RESET 0x0
5812
5813
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_GET(value) (((value) & 0x00000001) >> 0)
5814
5815
#define ALT_SDMMC_STAT_FIFO_RX_WATERMARK_SET(value) (((value) << 0) & 0x00000001)
5816
5840
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_NOTXWATERMARK 0x0
5841
5846
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_E_TXWATERMARK 0x1
5847
5849
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_LSB 1
5850
5851
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_MSB 1
5852
5853
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_WIDTH 1
5854
5855
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET_MSK 0x00000002
5856
5857
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_CLR_MSK 0xfffffffd
5858
5859
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_RESET 0x1
5860
5861
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_GET(value) (((value) & 0x00000002) >> 1)
5862
5863
#define ALT_SDMMC_STAT_FIFO_TX_WATERMARK_SET(value) (((value) << 1) & 0x00000002)
5864
5885
#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFONOTEMPTY 0x0
5886
5891
#define ALT_SDMMC_STAT_FIFO_EMPTY_E_FIFOEMPTY 0x1
5892
5894
#define ALT_SDMMC_STAT_FIFO_EMPTY_LSB 2
5895
5896
#define ALT_SDMMC_STAT_FIFO_EMPTY_MSB 2
5897
5898
#define ALT_SDMMC_STAT_FIFO_EMPTY_WIDTH 1
5899
5900
#define ALT_SDMMC_STAT_FIFO_EMPTY_SET_MSK 0x00000004
5901
5902
#define ALT_SDMMC_STAT_FIFO_EMPTY_CLR_MSK 0xfffffffb
5903
5904
#define ALT_SDMMC_STAT_FIFO_EMPTY_RESET 0x1
5905
5906
#define ALT_SDMMC_STAT_FIFO_EMPTY_GET(value) (((value) & 0x00000004) >> 2)
5907
5908
#define ALT_SDMMC_STAT_FIFO_EMPTY_SET(value) (((value) << 2) & 0x00000004)
5909
5930
#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFONOTFULL 0x0
5931
5936
#define ALT_SDMMC_STAT_FIFO_FULL_E_FIFOFULL 0x1
5937
5939
#define ALT_SDMMC_STAT_FIFO_FULL_LSB 3
5940
5941
#define ALT_SDMMC_STAT_FIFO_FULL_MSB 3
5942
5943
#define ALT_SDMMC_STAT_FIFO_FULL_WIDTH 1
5944
5945
#define ALT_SDMMC_STAT_FIFO_FULL_SET_MSK 0x00000008
5946
5947
#define ALT_SDMMC_STAT_FIFO_FULL_CLR_MSK 0xfffffff7
5948
5949
#define ALT_SDMMC_STAT_FIFO_FULL_RESET 0x0
5950
5951
#define ALT_SDMMC_STAT_FIFO_FULL_GET(value) (((value) & 0x00000008) >> 3)
5952
5953
#define ALT_SDMMC_STAT_FIFO_FULL_SET(value) (((value) << 3) & 0x00000008)
5954
6037
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_IDLEANDOTHERS 0x0
6038
6043
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_SENDINITSEQ 0x1
6044
6049
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDSTART 0x2
6050
6055
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDTXBIT 0x3
6056
6061
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDINDXARG 0x4
6062
6067
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDCRC7 0x5
6068
6073
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_TXCMDEND 0x6
6074
6079
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPSTART 0x7
6080
6085
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPIRQ 0x8
6086
6091
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPTX 0x9
6092
6097
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCMDIDX 0xa
6098
6103
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPDATA 0xb
6104
6109
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPCRC7 0xc
6110
6115
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_RXRESPEND 0xd
6116
6121
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_CMDPATHWAIT 0xe
6122
6127
#define ALT_SDMMC_STAT_CMD_FSM_STATES_E_WAITCMDTURN 0xf
6128
6130
#define ALT_SDMMC_STAT_CMD_FSM_STATES_LSB 4
6131
6132
#define ALT_SDMMC_STAT_CMD_FSM_STATES_MSB 7
6133
6134
#define ALT_SDMMC_STAT_CMD_FSM_STATES_WIDTH 4
6135
6136
#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET_MSK 0x000000f0
6137
6138
#define ALT_SDMMC_STAT_CMD_FSM_STATES_CLR_MSK 0xffffff0f
6139
6140
#define ALT_SDMMC_STAT_CMD_FSM_STATES_RESET 0x0
6141
6142
#define ALT_SDMMC_STAT_CMD_FSM_STATES_GET(value) (((value) & 0x000000f0) >> 4)
6143
6144
#define ALT_SDMMC_STAT_CMD_FSM_STATES_SET(value) (((value) << 4) & 0x000000f0)
6145
6170
#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDNOTPRESENT 0x0
6171
6176
#define ALT_SDMMC_STAT_DATA_3_STAT_E_CARDPRESENT 0x1
6177
6179
#define ALT_SDMMC_STAT_DATA_3_STAT_LSB 8
6180
6181
#define ALT_SDMMC_STAT_DATA_3_STAT_MSB 8
6182
6183
#define ALT_SDMMC_STAT_DATA_3_STAT_WIDTH 1
6184
6185
#define ALT_SDMMC_STAT_DATA_3_STAT_SET_MSK 0x00000100
6186
6187
#define ALT_SDMMC_STAT_DATA_3_STAT_CLR_MSK 0xfffffeff
6188
6189
#define ALT_SDMMC_STAT_DATA_3_STAT_RESET 0x1
6190
6191
#define ALT_SDMMC_STAT_DATA_3_STAT_GET(value) (((value) & 0x00000100) >> 8)
6192
6193
#define ALT_SDMMC_STAT_DATA_3_STAT_SET(value) (((value) << 8) & 0x00000100)
6194
6219
#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDNOTBUSY 0x0
6220
6225
#define ALT_SDMMC_STAT_DATA_BUSY_E_CARDBUSY 0x1
6226
6228
#define ALT_SDMMC_STAT_DATA_BUSY_LSB 9
6229
6230
#define ALT_SDMMC_STAT_DATA_BUSY_MSB 9
6231
6232
#define ALT_SDMMC_STAT_DATA_BUSY_WIDTH 1
6233
6234
#define ALT_SDMMC_STAT_DATA_BUSY_SET_MSK 0x00000200
6235
6236
#define ALT_SDMMC_STAT_DATA_BUSY_CLR_MSK 0xfffffdff
6237
6238
#define ALT_SDMMC_STAT_DATA_BUSY_RESET 0x0
6239
6240
#define ALT_SDMMC_STAT_DATA_BUSY_GET(value) (((value) & 0x00000200) >> 9)
6241
6242
#define ALT_SDMMC_STAT_DATA_BUSY_SET(value) (((value) << 9) & 0x00000200)
6243
6264
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATENOTBSY 0x0
6265
6270
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_E_DATASTATEBSY 0x1
6271
6273
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_LSB 10
6274
6275
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_MSB 10
6276
6277
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_WIDTH 1
6278
6279
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET_MSK 0x00000400
6280
6281
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_CLR_MSK 0xfffffbff
6282
6283
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_RESET 0x0
6284
6285
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_GET(value) (((value) & 0x00000400) >> 10)
6286
6287
#define ALT_SDMMC_STAT_DATA_STATE_MC_BUSY_SET(value) (((value) << 10) & 0x00000400)
6288
6298
#define ALT_SDMMC_STAT_RESPONSE_INDEX_LSB 11
6299
6300
#define ALT_SDMMC_STAT_RESPONSE_INDEX_MSB 16
6301
6302
#define ALT_SDMMC_STAT_RESPONSE_INDEX_WIDTH 6
6303
6304
#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET_MSK 0x0001f800
6305
6306
#define ALT_SDMMC_STAT_RESPONSE_INDEX_CLR_MSK 0xfffe07ff
6307
6308
#define ALT_SDMMC_STAT_RESPONSE_INDEX_RESET 0x0
6309
6310
#define ALT_SDMMC_STAT_RESPONSE_INDEX_GET(value) (((value) & 0x0001f800) >> 11)
6311
6312
#define ALT_SDMMC_STAT_RESPONSE_INDEX_SET(value) (((value) << 11) & 0x0001f800)
6313
6323
#define ALT_SDMMC_STAT_FIFO_COUNT_LSB 17
6324
6325
#define ALT_SDMMC_STAT_FIFO_COUNT_MSB 29
6326
6327
#define ALT_SDMMC_STAT_FIFO_COUNT_WIDTH 13
6328
6329
#define ALT_SDMMC_STAT_FIFO_COUNT_SET_MSK 0x3ffe0000
6330
6331
#define ALT_SDMMC_STAT_FIFO_COUNT_CLR_MSK 0xc001ffff
6332
6333
#define ALT_SDMMC_STAT_FIFO_COUNT_RESET 0x0
6334
6335
#define ALT_SDMMC_STAT_FIFO_COUNT_GET(value) (((value) & 0x3ffe0000) >> 17)
6336
6337
#define ALT_SDMMC_STAT_FIFO_COUNT_SET(value) (((value) << 17) & 0x3ffe0000)
6338
6350
#define ALT_SDMMC_STAT_DMA_ACK_LSB 30
6351
6352
#define ALT_SDMMC_STAT_DMA_ACK_MSB 30
6353
6354
#define ALT_SDMMC_STAT_DMA_ACK_WIDTH 1
6355
6356
#define ALT_SDMMC_STAT_DMA_ACK_SET_MSK 0x40000000
6357
6358
#define ALT_SDMMC_STAT_DMA_ACK_CLR_MSK 0xbfffffff
6359
6360
#define ALT_SDMMC_STAT_DMA_ACK_RESET 0x0
6361
6362
#define ALT_SDMMC_STAT_DMA_ACK_GET(value) (((value) & 0x40000000) >> 30)
6363
6364
#define ALT_SDMMC_STAT_DMA_ACK_SET(value) (((value) << 30) & 0x40000000)
6365
6377
#define ALT_SDMMC_STAT_DMA_REQ_LSB 31
6378
6379
#define ALT_SDMMC_STAT_DMA_REQ_MSB 31
6380
6381
#define ALT_SDMMC_STAT_DMA_REQ_WIDTH 1
6382
6383
#define ALT_SDMMC_STAT_DMA_REQ_SET_MSK 0x80000000
6384
6385
#define ALT_SDMMC_STAT_DMA_REQ_CLR_MSK 0x7fffffff
6386
6387
#define ALT_SDMMC_STAT_DMA_REQ_RESET 0x0
6388
6389
#define ALT_SDMMC_STAT_DMA_REQ_GET(value) (((value) & 0x80000000) >> 31)
6390
6391
#define ALT_SDMMC_STAT_DMA_REQ_SET(value) (((value) << 31) & 0x80000000)
6392
6393
#ifndef __ASSEMBLY__
6394
6404
struct
ALT_SDMMC_STAT_s
6405
{
6406
const
uint32_t
fifo_rx_watermark
: 1;
6407
const
uint32_t
fifo_tx_watermark
: 1;
6408
const
uint32_t
fifo_empty
: 1;
6409
const
uint32_t
fifo_full
: 1;
6410
const
uint32_t
command_fsm_states
: 4;
6411
const
uint32_t
data_3_status
: 1;
6412
const
uint32_t
data_busy
: 1;
6413
const
uint32_t
data_state_mc_busy
: 1;
6414
const
uint32_t
response_index
: 6;
6415
const
uint32_t
fifo_count
: 13;
6416
const
uint32_t
dma_ack
: 1;
6417
const
uint32_t
dma_req
: 1;
6418
};
6419
6421
typedef
volatile
struct
ALT_SDMMC_STAT_s
ALT_SDMMC_STAT_t
;
6422
#endif
/* __ASSEMBLY__ */
6423
6425
#define ALT_SDMMC_STAT_RESET 0x00000106
6426
6427
#define ALT_SDMMC_STAT_OFST 0x48
6428
6473
#define ALT_SDMMC_FIFOTH_TX_WMARK_LSB 0
6474
6475
#define ALT_SDMMC_FIFOTH_TX_WMARK_MSB 11
6476
6477
#define ALT_SDMMC_FIFOTH_TX_WMARK_WIDTH 12
6478
6479
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET_MSK 0x00000fff
6480
6481
#define ALT_SDMMC_FIFOTH_TX_WMARK_CLR_MSK 0xfffff000
6482
6483
#define ALT_SDMMC_FIFOTH_TX_WMARK_RESET 0x0
6484
6485
#define ALT_SDMMC_FIFOTH_TX_WMARK_GET(value) (((value) & 0x00000fff) >> 0)
6486
6487
#define ALT_SDMMC_FIFOTH_TX_WMARK_SET(value) (((value) << 0) & 0x00000fff)
6488
6526
#define ALT_SDMMC_FIFOTH_RX_WMARK_LSB 16
6527
6528
#define ALT_SDMMC_FIFOTH_RX_WMARK_MSB 27
6529
6530
#define ALT_SDMMC_FIFOTH_RX_WMARK_WIDTH 12
6531
6532
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET_MSK 0x0fff0000
6533
6534
#define ALT_SDMMC_FIFOTH_RX_WMARK_CLR_MSK 0xf000ffff
6535
6536
#define ALT_SDMMC_FIFOTH_RX_WMARK_RESET 0x3ff
6537
6538
#define ALT_SDMMC_FIFOTH_RX_WMARK_GET(value) (((value) & 0x0fff0000) >> 16)
6539
6540
#define ALT_SDMMC_FIFOTH_RX_WMARK_SET(value) (((value) << 16) & 0x0fff0000)
6541
6627
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE1 0x0
6628
6633
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZE4 0x1
6634
6639
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK8 0x2
6640
6645
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_TXMSIZEK16 0x3
6646
6651
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK1 0x5
6652
6657
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZEK4 0x6
6658
6663
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_E_RXMSIZE8 0x7
6664
6666
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_LSB 28
6667
6668
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_MSB 30
6669
6670
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_WIDTH 3
6671
6672
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET_MSK 0x70000000
6673
6674
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_CLR_MSK 0x8fffffff
6675
6676
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_RESET 0x0
6677
6678
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_GET(value) (((value) & 0x70000000) >> 28)
6679
6680
#define ALT_SDMMC_FIFOTH_DW_DMA_MULT_TRANSACTION_SIZE_SET(value) (((value) << 28) & 0x70000000)
6681
6682
#ifndef __ASSEMBLY__
6683
6693
struct
ALT_SDMMC_FIFOTH_s
6694
{
6695
uint32_t
tx_wmark
: 12;
6696
uint32_t : 4;
6697
uint32_t
rx_wmark
: 12;
6698
uint32_t
dw_dma_multiple_transaction_size
: 3;
6699
uint32_t : 1;
6700
};
6701
6703
typedef
volatile
struct
ALT_SDMMC_FIFOTH_s
ALT_SDMMC_FIFOTH_t
;
6704
#endif
/* __ASSEMBLY__ */
6705
6707
#define ALT_SDMMC_FIFOTH_RESET 0x03ff0000
6708
6709
#define ALT_SDMMC_FIFOTH_OFST 0x4c
6710
6745
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_DETECTED 0x0
6746
6751
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_E_NOTDETECTED 0x1
6752
6754
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_LSB 0
6755
6756
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_MSB 0
6757
6758
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_WIDTH 1
6759
6760
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET_MSK 0x00000001
6761
6762
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_CLR_MSK 0xfffffffe
6763
6764
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_RESET 0x1
6765
6766
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_GET(value) (((value) & 0x00000001) >> 0)
6767
6768
#define ALT_SDMMC_CDETECT_CARD_DETECT_N_SET(value) (((value) << 0) & 0x00000001)
6769
6770
#ifndef __ASSEMBLY__
6771
6781
struct
ALT_SDMMC_CDETECT_s
6782
{
6783
const
uint32_t
card_detect_n
: 1;
6784
uint32_t : 31;
6785
};
6786
6788
typedef
volatile
struct
ALT_SDMMC_CDETECT_s
ALT_SDMMC_CDETECT_t
;
6789
#endif
/* __ASSEMBLY__ */
6790
6792
#define ALT_SDMMC_CDETECT_RESET 0x00000001
6793
6794
#define ALT_SDMMC_CDETECT_OFST 0x50
6795
6831
#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_DISD 0x0
6832
6837
#define ALT_SDMMC_WRTPRT_WR_PROTECT_E_END 0x1
6838
6840
#define ALT_SDMMC_WRTPRT_WR_PROTECT_LSB 0
6841
6842
#define ALT_SDMMC_WRTPRT_WR_PROTECT_MSB 0
6843
6844
#define ALT_SDMMC_WRTPRT_WR_PROTECT_WIDTH 1
6845
6846
#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET_MSK 0x00000001
6847
6848
#define ALT_SDMMC_WRTPRT_WR_PROTECT_CLR_MSK 0xfffffffe
6849
6850
#define ALT_SDMMC_WRTPRT_WR_PROTECT_RESET 0x1
6851
6852
#define ALT_SDMMC_WRTPRT_WR_PROTECT_GET(value) (((value) & 0x00000001) >> 0)
6853
6854
#define ALT_SDMMC_WRTPRT_WR_PROTECT_SET(value) (((value) << 0) & 0x00000001)
6855
6856
#ifndef __ASSEMBLY__
6857
6867
struct
ALT_SDMMC_WRTPRT_s
6868
{
6869
const
uint32_t
write_protect
: 1;
6870
uint32_t : 31;
6871
};
6872
6874
typedef
volatile
struct
ALT_SDMMC_WRTPRT_s
ALT_SDMMC_WRTPRT_t
;
6875
#endif
/* __ASSEMBLY__ */
6876
6878
#define ALT_SDMMC_WRTPRT_RESET 0x00000001
6879
6880
#define ALT_SDMMC_WRTPRT_OFST 0x54
6881
6906
#define ALT_SDMMC_GPIO_GPI_LSB 0
6907
6908
#define ALT_SDMMC_GPIO_GPI_MSB 7
6909
6910
#define ALT_SDMMC_GPIO_GPI_WIDTH 8
6911
6912
#define ALT_SDMMC_GPIO_GPI_SET_MSK 0x000000ff
6913
6914
#define ALT_SDMMC_GPIO_GPI_CLR_MSK 0xffffff00
6915
6916
#define ALT_SDMMC_GPIO_GPI_RESET 0x0
6917
6918
#define ALT_SDMMC_GPIO_GPI_GET(value) (((value) & 0x000000ff) >> 0)
6919
6920
#define ALT_SDMMC_GPIO_GPI_SET(value) (((value) << 0) & 0x000000ff)
6921
6932
#define ALT_SDMMC_GPIO_GPO_LSB 8
6933
6934
#define ALT_SDMMC_GPIO_GPO_MSB 23
6935
6936
#define ALT_SDMMC_GPIO_GPO_WIDTH 16
6937
6938
#define ALT_SDMMC_GPIO_GPO_SET_MSK 0x00ffff00
6939
6940
#define ALT_SDMMC_GPIO_GPO_CLR_MSK 0xff0000ff
6941
6942
#define ALT_SDMMC_GPIO_GPO_RESET 0x0
6943
6944
#define ALT_SDMMC_GPIO_GPO_GET(value) (((value) & 0x00ffff00) >> 8)
6945
6946
#define ALT_SDMMC_GPIO_GPO_SET(value) (((value) << 8) & 0x00ffff00)
6947
6948
#ifndef __ASSEMBLY__
6949
6959
struct
ALT_SDMMC_GPIO_s
6960
{
6961
const
uint32_t
gpi
: 8;
6962
uint32_t
gpo
: 16;
6963
uint32_t : 8;
6964
};
6965
6967
typedef
volatile
struct
ALT_SDMMC_GPIO_s
ALT_SDMMC_GPIO_t
;
6968
#endif
/* __ASSEMBLY__ */
6969
6971
#define ALT_SDMMC_GPIO_RESET 0x00000000
6972
6973
#define ALT_SDMMC_GPIO_OFST 0x58
6974
7005
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_LSB 0
7006
7007
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_MSB 31
7008
7009
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_WIDTH 32
7010
7011
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET_MSK 0xffffffff
7012
7013
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_CLR_MSK 0x00000000
7014
7015
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_RESET 0x0
7016
7017
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7018
7019
#define ALT_SDMMC_TCBCNT_TRANS_CARD_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7020
7021
#ifndef __ASSEMBLY__
7022
7032
struct
ALT_SDMMC_TCBCNT_s
7033
{
7034
const
uint32_t
trans_card_byte_count
: 32;
7035
};
7036
7038
typedef
volatile
struct
ALT_SDMMC_TCBCNT_s
ALT_SDMMC_TCBCNT_t
;
7039
#endif
/* __ASSEMBLY__ */
7040
7042
#define ALT_SDMMC_TCBCNT_RESET 0x00000000
7043
7044
#define ALT_SDMMC_TCBCNT_OFST 0x5c
7045
7076
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_LSB 0
7077
7078
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_MSB 31
7079
7080
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_WIDTH 32
7081
7082
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET_MSK 0xffffffff
7083
7084
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_CLR_MSK 0x00000000
7085
7086
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_RESET 0x0
7087
7088
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_GET(value) (((value) & 0xffffffff) >> 0)
7089
7090
#define ALT_SDMMC_TBBCNT_TRANS_FIFO_BYTE_COUNT_SET(value) (((value) << 0) & 0xffffffff)
7091
7092
#ifndef __ASSEMBLY__
7093
7103
struct
ALT_SDMMC_TBBCNT_s
7104
{
7105
const
uint32_t
trans_fifo_byte_count
: 32;
7106
};
7107
7109
typedef
volatile
struct
ALT_SDMMC_TBBCNT_s
ALT_SDMMC_TBBCNT_t
;
7110
#endif
/* __ASSEMBLY__ */
7111
7113
#define ALT_SDMMC_TBBCNT_RESET 0x00000000
7114
7115
#define ALT_SDMMC_TBBCNT_OFST 0x60
7116
7141
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_LSB 0
7142
7143
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_MSB 23
7144
7145
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_WIDTH 24
7146
7147
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET_MSK 0x00ffffff
7148
7149
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_CLR_MSK 0xff000000
7150
7151
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_RESET 0xffffff
7152
7153
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_GET(value) (((value) & 0x00ffffff) >> 0)
7154
7155
#define ALT_SDMMC_DEBNCE_DEBOUNCE_COUNT_SET(value) (((value) << 0) & 0x00ffffff)
7156
7157
#ifndef __ASSEMBLY__
7158
7168
struct
ALT_SDMMC_DEBNCE_s
7169
{
7170
uint32_t
debounce_count
: 24;
7171
uint32_t : 8;
7172
};
7173
7175
typedef
volatile
struct
ALT_SDMMC_DEBNCE_s
ALT_SDMMC_DEBNCE_t
;
7176
#endif
/* __ASSEMBLY__ */
7177
7179
#define ALT_SDMMC_DEBNCE_RESET 0x00ffffff
7180
7181
#define ALT_SDMMC_DEBNCE_OFST 0x64
7182
7207
#define ALT_SDMMC_USRID_USR_ID_LSB 0
7208
7209
#define ALT_SDMMC_USRID_USR_ID_MSB 31
7210
7211
#define ALT_SDMMC_USRID_USR_ID_WIDTH 32
7212
7213
#define ALT_SDMMC_USRID_USR_ID_SET_MSK 0xffffffff
7214
7215
#define ALT_SDMMC_USRID_USR_ID_CLR_MSK 0x00000000
7216
7217
#define ALT_SDMMC_USRID_USR_ID_RESET 0x7967797
7218
7219
#define ALT_SDMMC_USRID_USR_ID_GET(value) (((value) & 0xffffffff) >> 0)
7220
7221
#define ALT_SDMMC_USRID_USR_ID_SET(value) (((value) << 0) & 0xffffffff)
7222
7223
#ifndef __ASSEMBLY__
7224
7234
struct
ALT_SDMMC_USRID_s
7235
{
7236
uint32_t
usr_id
: 32;
7237
};
7238
7240
typedef
volatile
struct
ALT_SDMMC_USRID_s
ALT_SDMMC_USRID_t
;
7241
#endif
/* __ASSEMBLY__ */
7242
7244
#define ALT_SDMMC_USRID_RESET 0x07967797
7245
7246
#define ALT_SDMMC_USRID_OFST 0x68
7247
7270
#define ALT_SDMMC_VERID_VER_ID_LSB 0
7271
7272
#define ALT_SDMMC_VERID_VER_ID_MSB 31
7273
7274
#define ALT_SDMMC_VERID_VER_ID_WIDTH 32
7275
7276
#define ALT_SDMMC_VERID_VER_ID_SET_MSK 0xffffffff
7277
7278
#define ALT_SDMMC_VERID_VER_ID_CLR_MSK 0x00000000
7279
7280
#define ALT_SDMMC_VERID_VER_ID_RESET 0x5342270a
7281
7282
#define ALT_SDMMC_VERID_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
7283
7284
#define ALT_SDMMC_VERID_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
7285
7286
#ifndef __ASSEMBLY__
7287
7297
struct
ALT_SDMMC_VERID_s
7298
{
7299
const
uint32_t
ver_id
: 32;
7300
};
7301
7303
typedef
volatile
struct
ALT_SDMMC_VERID_s
ALT_SDMMC_VERID_t
;
7304
#endif
/* __ASSEMBLY__ */
7305
7307
#define ALT_SDMMC_VERID_RESET 0x5342270a
7308
7309
#define ALT_SDMMC_VERID_OFST 0x6c
7310
7355
#define ALT_SDMMC_HCON_CT_E_SDMMC 0x1
7356
7358
#define ALT_SDMMC_HCON_CT_LSB 0
7359
7360
#define ALT_SDMMC_HCON_CT_MSB 0
7361
7362
#define ALT_SDMMC_HCON_CT_WIDTH 1
7363
7364
#define ALT_SDMMC_HCON_CT_SET_MSK 0x00000001
7365
7366
#define ALT_SDMMC_HCON_CT_CLR_MSK 0xfffffffe
7367
7368
#define ALT_SDMMC_HCON_CT_RESET 0x1
7369
7370
#define ALT_SDMMC_HCON_CT_GET(value) (((value) & 0x00000001) >> 0)
7371
7372
#define ALT_SDMMC_HCON_CT_SET(value) (((value) << 0) & 0x00000001)
7373
7393
#define ALT_SDMMC_HCON_NC_E_NUMCARD 0x0
7394
7396
#define ALT_SDMMC_HCON_NC_LSB 1
7397
7398
#define ALT_SDMMC_HCON_NC_MSB 5
7399
7400
#define ALT_SDMMC_HCON_NC_WIDTH 5
7401
7402
#define ALT_SDMMC_HCON_NC_SET_MSK 0x0000003e
7403
7404
#define ALT_SDMMC_HCON_NC_CLR_MSK 0xffffffc1
7405
7406
#define ALT_SDMMC_HCON_NC_RESET 0x0
7407
7408
#define ALT_SDMMC_HCON_NC_GET(value) (((value) & 0x0000003e) >> 1)
7409
7410
#define ALT_SDMMC_HCON_NC_SET(value) (((value) << 1) & 0x0000003e)
7411
7431
#define ALT_SDMMC_HCON_HBUS_E_APB 0x0
7432
7434
#define ALT_SDMMC_HCON_HBUS_LSB 6
7435
7436
#define ALT_SDMMC_HCON_HBUS_MSB 6
7437
7438
#define ALT_SDMMC_HCON_HBUS_WIDTH 1
7439
7440
#define ALT_SDMMC_HCON_HBUS_SET_MSK 0x00000040
7441
7442
#define ALT_SDMMC_HCON_HBUS_CLR_MSK 0xffffffbf
7443
7444
#define ALT_SDMMC_HCON_HBUS_RESET 0x0
7445
7446
#define ALT_SDMMC_HCON_HBUS_GET(value) (((value) & 0x00000040) >> 6)
7447
7448
#define ALT_SDMMC_HCON_HBUS_SET(value) (((value) << 6) & 0x00000040)
7449
7469
#define ALT_SDMMC_HCON_HDATAWIDTH_E_WIDTH32BITS 0x1
7470
7472
#define ALT_SDMMC_HCON_HDATAWIDTH_LSB 7
7473
7474
#define ALT_SDMMC_HCON_HDATAWIDTH_MSB 9
7475
7476
#define ALT_SDMMC_HCON_HDATAWIDTH_WIDTH 3
7477
7478
#define ALT_SDMMC_HCON_HDATAWIDTH_SET_MSK 0x00000380
7479
7480
#define ALT_SDMMC_HCON_HDATAWIDTH_CLR_MSK 0xfffffc7f
7481
7482
#define ALT_SDMMC_HCON_HDATAWIDTH_RESET 0x1
7483
7484
#define ALT_SDMMC_HCON_HDATAWIDTH_GET(value) (((value) & 0x00000380) >> 7)
7485
7486
#define ALT_SDMMC_HCON_HDATAWIDTH_SET(value) (((value) << 7) & 0x00000380)
7487
7507
#define ALT_SDMMC_HCON_HADDRWIDTH_E_WIDTH13BITS 0xc
7508
7510
#define ALT_SDMMC_HCON_HADDRWIDTH_LSB 10
7511
7512
#define ALT_SDMMC_HCON_HADDRWIDTH_MSB 15
7513
7514
#define ALT_SDMMC_HCON_HADDRWIDTH_WIDTH 6
7515
7516
#define ALT_SDMMC_HCON_HADDRWIDTH_SET_MSK 0x0000fc00
7517
7518
#define ALT_SDMMC_HCON_HADDRWIDTH_CLR_MSK 0xffff03ff
7519
7520
#define ALT_SDMMC_HCON_HADDRWIDTH_RESET 0xc
7521
7522
#define ALT_SDMMC_HCON_HADDRWIDTH_GET(value) (((value) & 0x0000fc00) >> 10)
7523
7524
#define ALT_SDMMC_HCON_HADDRWIDTH_SET(value) (((value) << 10) & 0x0000fc00)
7525
7546
#define ALT_SDMMC_HCON_DMAINTF_E_NONE 0x0
7547
7549
#define ALT_SDMMC_HCON_DMAINTF_LSB 16
7550
7551
#define ALT_SDMMC_HCON_DMAINTF_MSB 17
7552
7553
#define ALT_SDMMC_HCON_DMAINTF_WIDTH 2
7554
7555
#define ALT_SDMMC_HCON_DMAINTF_SET_MSK 0x00030000
7556
7557
#define ALT_SDMMC_HCON_DMAINTF_CLR_MSK 0xfffcffff
7558
7559
#define ALT_SDMMC_HCON_DMAINTF_RESET 0x0
7560
7561
#define ALT_SDMMC_HCON_DMAINTF_GET(value) (((value) & 0x00030000) >> 16)
7562
7563
#define ALT_SDMMC_HCON_DMAINTF_SET(value) (((value) << 16) & 0x00030000)
7564
7585
#define ALT_SDMMC_HCON_DMADATAWIDTH_E_WIDTH32BITS 0x1
7586
7588
#define ALT_SDMMC_HCON_DMADATAWIDTH_LSB 18
7589
7590
#define ALT_SDMMC_HCON_DMADATAWIDTH_MSB 20
7591
7592
#define ALT_SDMMC_HCON_DMADATAWIDTH_WIDTH 3
7593
7594
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET_MSK 0x001c0000
7595
7596
#define ALT_SDMMC_HCON_DMADATAWIDTH_CLR_MSK 0xffe3ffff
7597
7598
#define ALT_SDMMC_HCON_DMADATAWIDTH_RESET 0x1
7599
7600
#define ALT_SDMMC_HCON_DMADATAWIDTH_GET(value) (((value) & 0x001c0000) >> 18)
7601
7602
#define ALT_SDMMC_HCON_DMADATAWIDTH_SET(value) (((value) << 18) & 0x001c0000)
7603
7623
#define ALT_SDMMC_HCON_RIOS_E_OUTSIDE 0x0
7624
7626
#define ALT_SDMMC_HCON_RIOS_LSB 21
7627
7628
#define ALT_SDMMC_HCON_RIOS_MSB 21
7629
7630
#define ALT_SDMMC_HCON_RIOS_WIDTH 1
7631
7632
#define ALT_SDMMC_HCON_RIOS_SET_MSK 0x00200000
7633
7634
#define ALT_SDMMC_HCON_RIOS_CLR_MSK 0xffdfffff
7635
7636
#define ALT_SDMMC_HCON_RIOS_RESET 0x0
7637
7638
#define ALT_SDMMC_HCON_RIOS_GET(value) (((value) & 0x00200000) >> 21)
7639
7640
#define ALT_SDMMC_HCON_RIOS_SET(value) (((value) << 21) & 0x00200000)
7641
7661
#define ALT_SDMMC_HCON_IHR_E_IMPLEMENTED 0x1
7662
7664
#define ALT_SDMMC_HCON_IHR_LSB 22
7665
7666
#define ALT_SDMMC_HCON_IHR_MSB 22
7667
7668
#define ALT_SDMMC_HCON_IHR_WIDTH 1
7669
7670
#define ALT_SDMMC_HCON_IHR_SET_MSK 0x00400000
7671
7672
#define ALT_SDMMC_HCON_IHR_CLR_MSK 0xffbfffff
7673
7674
#define ALT_SDMMC_HCON_IHR_RESET 0x1
7675
7676
#define ALT_SDMMC_HCON_IHR_GET(value) (((value) & 0x00400000) >> 22)
7677
7678
#define ALT_SDMMC_HCON_IHR_SET(value) (((value) << 22) & 0x00400000)
7679
7699
#define ALT_SDMMC_HCON_SCFP_E_SET 0x1
7700
7702
#define ALT_SDMMC_HCON_SCFP_LSB 23
7703
7704
#define ALT_SDMMC_HCON_SCFP_MSB 23
7705
7706
#define ALT_SDMMC_HCON_SCFP_WIDTH 1
7707
7708
#define ALT_SDMMC_HCON_SCFP_SET_MSK 0x00800000
7709
7710
#define ALT_SDMMC_HCON_SCFP_CLR_MSK 0xff7fffff
7711
7712
#define ALT_SDMMC_HCON_SCFP_RESET 0x1
7713
7714
#define ALT_SDMMC_HCON_SCFP_GET(value) (((value) & 0x00800000) >> 23)
7715
7716
#define ALT_SDMMC_HCON_SCFP_SET(value) (((value) << 23) & 0x00800000)
7717
7737
#define ALT_SDMMC_HCON_NCD_E_ONEDIV 0x0
7738
7740
#define ALT_SDMMC_HCON_NCD_LSB 24
7741
7742
#define ALT_SDMMC_HCON_NCD_MSB 25
7743
7744
#define ALT_SDMMC_HCON_NCD_WIDTH 2
7745
7746
#define ALT_SDMMC_HCON_NCD_SET_MSK 0x03000000
7747
7748
#define ALT_SDMMC_HCON_NCD_CLR_MSK 0xfcffffff
7749
7750
#define ALT_SDMMC_HCON_NCD_RESET 0x0
7751
7752
#define ALT_SDMMC_HCON_NCD_GET(value) (((value) & 0x03000000) >> 24)
7753
7754
#define ALT_SDMMC_HCON_NCD_SET(value) (((value) << 24) & 0x03000000)
7755
7775
#define ALT_SDMMC_HCON_ARO_E_NOTOPTFORAREA 0x0
7776
7778
#define ALT_SDMMC_HCON_ARO_LSB 26
7779
7780
#define ALT_SDMMC_HCON_ARO_MSB 26
7781
7782
#define ALT_SDMMC_HCON_ARO_WIDTH 1
7783
7784
#define ALT_SDMMC_HCON_ARO_SET_MSK 0x04000000
7785
7786
#define ALT_SDMMC_HCON_ARO_CLR_MSK 0xfbffffff
7787
7788
#define ALT_SDMMC_HCON_ARO_RESET 0x0
7789
7790
#define ALT_SDMMC_HCON_ARO_GET(value) (((value) & 0x04000000) >> 26)
7791
7792
#define ALT_SDMMC_HCON_ARO_SET(value) (((value) << 26) & 0x04000000)
7793
7807
#define ALT_SDMMC_HCON_AC_LSB 27
7808
7809
#define ALT_SDMMC_HCON_AC_MSB 27
7810
7811
#define ALT_SDMMC_HCON_AC_WIDTH 1
7812
7813
#define ALT_SDMMC_HCON_AC_SET_MSK 0x08000000
7814
7815
#define ALT_SDMMC_HCON_AC_CLR_MSK 0xf7ffffff
7816
7817
#define ALT_SDMMC_HCON_AC_RESET 0x0
7818
7819
#define ALT_SDMMC_HCON_AC_GET(value) (((value) & 0x08000000) >> 27)
7820
7821
#define ALT_SDMMC_HCON_AC_SET(value) (((value) << 27) & 0x08000000)
7822
7823
#ifndef __ASSEMBLY__
7824
7834
struct
ALT_SDMMC_HCON_s
7835
{
7836
const
uint32_t
ct
: 1;
7837
const
uint32_t
nc
: 5;
7838
const
uint32_t
hbus
: 1;
7839
const
uint32_t
hdatawidth
: 3;
7840
const
uint32_t
haddrwidth
: 6;
7841
const
uint32_t
dmaintf
: 2;
7842
const
uint32_t
dmadatawidth
: 3;
7843
const
uint32_t
rios
: 1;
7844
const
uint32_t
ihr
: 1;
7845
const
uint32_t
scfp
: 1;
7846
const
uint32_t
ncd
: 2;
7847
const
uint32_t
aro
: 1;
7848
const
uint32_t
ac
: 1;
7849
uint32_t : 4;
7850
};
7851
7853
typedef
volatile
struct
ALT_SDMMC_HCON_s
ALT_SDMMC_HCON_t
;
7854
#endif
/* __ASSEMBLY__ */
7855
7857
#define ALT_SDMMC_HCON_RESET 0x00c43081
7858
7859
#define ALT_SDMMC_HCON_OFST 0x70
7860
7910
#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF33V 0x0
7911
7916
#define ALT_SDMMC_UHS_REG_VOLT_REG_E_BUF18V 0x1
7917
7919
#define ALT_SDMMC_UHS_REG_VOLT_REG_LSB 0
7920
7921
#define ALT_SDMMC_UHS_REG_VOLT_REG_MSB 15
7922
7923
#define ALT_SDMMC_UHS_REG_VOLT_REG_WIDTH 16
7924
7925
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET_MSK 0x0000ffff
7926
7927
#define ALT_SDMMC_UHS_REG_VOLT_REG_CLR_MSK 0xffff0000
7928
7929
#define ALT_SDMMC_UHS_REG_VOLT_REG_RESET 0x0
7930
7931
#define ALT_SDMMC_UHS_REG_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
7932
7933
#define ALT_SDMMC_UHS_REG_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
7934
7963
#define ALT_SDMMC_UHS_REG_DDR_REG_E_NONDDR 0x0
7964
7969
#define ALT_SDMMC_UHS_REG_DDR_REG_E_DDR 0x1
7970
7972
#define ALT_SDMMC_UHS_REG_DDR_REG_LSB 16
7973
7974
#define ALT_SDMMC_UHS_REG_DDR_REG_MSB 31
7975
7976
#define ALT_SDMMC_UHS_REG_DDR_REG_WIDTH 16
7977
7978
#define ALT_SDMMC_UHS_REG_DDR_REG_SET_MSK 0xffff0000
7979
7980
#define ALT_SDMMC_UHS_REG_DDR_REG_CLR_MSK 0x0000ffff
7981
7982
#define ALT_SDMMC_UHS_REG_DDR_REG_RESET 0x0
7983
7984
#define ALT_SDMMC_UHS_REG_DDR_REG_GET(value) (((value) & 0xffff0000) >> 16)
7985
7986
#define ALT_SDMMC_UHS_REG_DDR_REG_SET(value) (((value) << 16) & 0xffff0000)
7987
7988
#ifndef __ASSEMBLY__
7989
7999
struct
ALT_SDMMC_UHS_REG_s
8000
{
8001
uint32_t
volt_reg
: 16;
8002
uint32_t
ddr_reg
: 16;
8003
};
8004
8006
typedef
volatile
struct
ALT_SDMMC_UHS_REG_s
ALT_SDMMC_UHS_REG_t
;
8007
#endif
/* __ASSEMBLY__ */
8008
8010
#define ALT_SDMMC_UHS_REG_RESET 0x00000000
8011
8012
#define ALT_SDMMC_UHS_REG_OFST 0x74
8013
8060
#define ALT_SDMMC_RST_N_CARD_RST_E_DEASSERT 0x0
8061
8066
#define ALT_SDMMC_RST_N_CARD_RST_E_ASSERT 0x1
8067
8069
#define ALT_SDMMC_RST_N_CARD_RST_LSB 0
8070
8071
#define ALT_SDMMC_RST_N_CARD_RST_MSB 0
8072
8073
#define ALT_SDMMC_RST_N_CARD_RST_WIDTH 1
8074
8075
#define ALT_SDMMC_RST_N_CARD_RST_SET_MSK 0x00000001
8076
8077
#define ALT_SDMMC_RST_N_CARD_RST_CLR_MSK 0xfffffffe
8078
8079
#define ALT_SDMMC_RST_N_CARD_RST_RESET 0x1
8080
8081
#define ALT_SDMMC_RST_N_CARD_RST_GET(value) (((value) & 0x00000001) >> 0)
8082
8083
#define ALT_SDMMC_RST_N_CARD_RST_SET(value) (((value) << 0) & 0x00000001)
8084
8085
#ifndef __ASSEMBLY__
8086
8096
struct
ALT_SDMMC_RST_N_s
8097
{
8098
uint32_t
card_reset
: 1;
8099
uint32_t : 31;
8100
};
8101
8103
typedef
volatile
struct
ALT_SDMMC_RST_N_s
ALT_SDMMC_RST_N_t
;
8104
#endif
/* __ASSEMBLY__ */
8105
8107
#define ALT_SDMMC_RST_N_RESET 0x00000001
8108
8109
#define ALT_SDMMC_RST_N_OFST 0x78
8110
8150
#define ALT_SDMMC_BMOD_SWR_E_NOSFTRST 0x0
8151
8156
#define ALT_SDMMC_BMOD_SWR_E_SFTRST 0x1
8157
8159
#define ALT_SDMMC_BMOD_SWR_LSB 0
8160
8161
#define ALT_SDMMC_BMOD_SWR_MSB 0
8162
8163
#define ALT_SDMMC_BMOD_SWR_WIDTH 1
8164
8165
#define ALT_SDMMC_BMOD_SWR_SET_MSK 0x00000001
8166
8167
#define ALT_SDMMC_BMOD_SWR_CLR_MSK 0xfffffffe
8168
8169
#define ALT_SDMMC_BMOD_SWR_RESET 0x0
8170
8171
#define ALT_SDMMC_BMOD_SWR_GET(value) (((value) & 0x00000001) >> 0)
8172
8173
#define ALT_SDMMC_BMOD_SWR_SET(value) (((value) << 0) & 0x00000001)
8174
8201
#define ALT_SDMMC_BMOD_FB_E_NOFIXEDBRST 0x0
8202
8207
#define ALT_SDMMC_BMOD_FB_E_FIXEDBRST 0x1
8208
8210
#define ALT_SDMMC_BMOD_FB_LSB 1
8211
8212
#define ALT_SDMMC_BMOD_FB_MSB 1
8213
8214
#define ALT_SDMMC_BMOD_FB_WIDTH 1
8215
8216
#define ALT_SDMMC_BMOD_FB_SET_MSK 0x00000002
8217
8218
#define ALT_SDMMC_BMOD_FB_CLR_MSK 0xfffffffd
8219
8220
#define ALT_SDMMC_BMOD_FB_RESET 0x0
8221
8222
#define ALT_SDMMC_BMOD_FB_GET(value) (((value) & 0x00000002) >> 1)
8223
8224
#define ALT_SDMMC_BMOD_FB_SET(value) (((value) << 1) & 0x00000002)
8225
8239
#define ALT_SDMMC_BMOD_DSL_LSB 2
8240
8241
#define ALT_SDMMC_BMOD_DSL_MSB 6
8242
8243
#define ALT_SDMMC_BMOD_DSL_WIDTH 5
8244
8245
#define ALT_SDMMC_BMOD_DSL_SET_MSK 0x0000007c
8246
8247
#define ALT_SDMMC_BMOD_DSL_CLR_MSK 0xffffff83
8248
8249
#define ALT_SDMMC_BMOD_DSL_RESET 0x0
8250
8251
#define ALT_SDMMC_BMOD_DSL_GET(value) (((value) & 0x0000007c) >> 2)
8252
8253
#define ALT_SDMMC_BMOD_DSL_SET(value) (((value) << 2) & 0x0000007c)
8254
8277
#define ALT_SDMMC_BMOD_DE_E_DISD 0x0
8278
8283
#define ALT_SDMMC_BMOD_DE_E_END 0x1
8284
8286
#define ALT_SDMMC_BMOD_DE_LSB 7
8287
8288
#define ALT_SDMMC_BMOD_DE_MSB 7
8289
8290
#define ALT_SDMMC_BMOD_DE_WIDTH 1
8291
8292
#define ALT_SDMMC_BMOD_DE_SET_MSK 0x00000080
8293
8294
#define ALT_SDMMC_BMOD_DE_CLR_MSK 0xffffff7f
8295
8296
#define ALT_SDMMC_BMOD_DE_RESET 0x0
8297
8298
#define ALT_SDMMC_BMOD_DE_GET(value) (((value) & 0x00000080) >> 7)
8299
8300
#define ALT_SDMMC_BMOD_DE_SET(value) (((value) << 7) & 0x00000080)
8301
8356
#define ALT_SDMMC_BMOD_PBL_E_TRANS1 0x0
8357
8362
#define ALT_SDMMC_BMOD_PBL_E_TRANS4 0x1
8363
8368
#define ALT_SDMMC_BMOD_PBL_E_TRANS8 0x2
8369
8374
#define ALT_SDMMC_BMOD_PBL_E_TRANS16 0x3
8375
8380
#define ALT_SDMMC_BMOD_PBL_E_TRANS32 0x4
8381
8386
#define ALT_SDMMC_BMOD_PBL_E_TRANS64 0x5
8387
8392
#define ALT_SDMMC_BMOD_PBL_E_TRANS128 0x6
8393
8398
#define ALT_SDMMC_BMOD_PBL_E_TRANS256 0x7
8399
8401
#define ALT_SDMMC_BMOD_PBL_LSB 8
8402
8403
#define ALT_SDMMC_BMOD_PBL_MSB 10
8404
8405
#define ALT_SDMMC_BMOD_PBL_WIDTH 3
8406
8407
#define ALT_SDMMC_BMOD_PBL_SET_MSK 0x00000700
8408
8409
#define ALT_SDMMC_BMOD_PBL_CLR_MSK 0xfffff8ff
8410
8411
#define ALT_SDMMC_BMOD_PBL_RESET 0x0
8412
8413
#define ALT_SDMMC_BMOD_PBL_GET(value) (((value) & 0x00000700) >> 8)
8414
8415
#define ALT_SDMMC_BMOD_PBL_SET(value) (((value) << 8) & 0x00000700)
8416
8417
#ifndef __ASSEMBLY__
8418
8428
struct
ALT_SDMMC_BMOD_s
8429
{
8430
uint32_t
swr
: 1;
8431
uint32_t
fb
: 1;
8432
uint32_t
dsl
: 5;
8433
uint32_t
de
: 1;
8434
const
uint32_t
pbl
: 3;
8435
uint32_t : 21;
8436
};
8437
8439
typedef
volatile
struct
ALT_SDMMC_BMOD_s
ALT_SDMMC_BMOD_t
;
8440
#endif
/* __ASSEMBLY__ */
8441
8443
#define ALT_SDMMC_BMOD_RESET 0x00000000
8444
8445
#define ALT_SDMMC_BMOD_OFST 0x80
8446
8474
#define ALT_SDMMC_PLDMND_PD_LSB 0
8475
8476
#define ALT_SDMMC_PLDMND_PD_MSB 31
8477
8478
#define ALT_SDMMC_PLDMND_PD_WIDTH 32
8479
8480
#define ALT_SDMMC_PLDMND_PD_SET_MSK 0xffffffff
8481
8482
#define ALT_SDMMC_PLDMND_PD_CLR_MSK 0x00000000
8483
8484
#define ALT_SDMMC_PLDMND_PD_RESET 0x0
8485
8486
#define ALT_SDMMC_PLDMND_PD_GET(value) (((value) & 0xffffffff) >> 0)
8487
8488
#define ALT_SDMMC_PLDMND_PD_SET(value) (((value) << 0) & 0xffffffff)
8489
8490
#ifndef __ASSEMBLY__
8491
8501
struct
ALT_SDMMC_PLDMND_s
8502
{
8503
uint32_t
pd
: 32;
8504
};
8505
8507
typedef
volatile
struct
ALT_SDMMC_PLDMND_s
ALT_SDMMC_PLDMND_t
;
8508
#endif
/* __ASSEMBLY__ */
8509
8511
#define ALT_SDMMC_PLDMND_RESET 0x00000000
8512
8513
#define ALT_SDMMC_PLDMND_OFST 0x84
8514
8539
#define ALT_SDMMC_DBADDR_SDL_LSB 0
8540
8541
#define ALT_SDMMC_DBADDR_SDL_MSB 31
8542
8543
#define ALT_SDMMC_DBADDR_SDL_WIDTH 32
8544
8545
#define ALT_SDMMC_DBADDR_SDL_SET_MSK 0xffffffff
8546
8547
#define ALT_SDMMC_DBADDR_SDL_CLR_MSK 0x00000000
8548
8549
#define ALT_SDMMC_DBADDR_SDL_RESET 0x0
8550
8551
#define ALT_SDMMC_DBADDR_SDL_GET(value) (((value) & 0xffffffff) >> 0)
8552
8553
#define ALT_SDMMC_DBADDR_SDL_SET(value) (((value) << 0) & 0xffffffff)
8554
8555
#ifndef __ASSEMBLY__
8556
8566
struct
ALT_SDMMC_DBADDR_s
8567
{
8568
uint32_t
sdl
: 32;
8569
};
8570
8572
typedef
volatile
struct
ALT_SDMMC_DBADDR_s
ALT_SDMMC_DBADDR_t
;
8573
#endif
/* __ASSEMBLY__ */
8574
8576
#define ALT_SDMMC_DBADDR_RESET 0x00000000
8577
8578
#define ALT_SDMMC_DBADDR_OFST 0x88
8579
8624
#define ALT_SDMMC_IDSTS_TI_E_NOCLR 0x0
8625
8630
#define ALT_SDMMC_IDSTS_TI_E_CLR 0x1
8631
8633
#define ALT_SDMMC_IDSTS_TI_LSB 0
8634
8635
#define ALT_SDMMC_IDSTS_TI_MSB 0
8636
8637
#define ALT_SDMMC_IDSTS_TI_WIDTH 1
8638
8639
#define ALT_SDMMC_IDSTS_TI_SET_MSK 0x00000001
8640
8641
#define ALT_SDMMC_IDSTS_TI_CLR_MSK 0xfffffffe
8642
8643
#define ALT_SDMMC_IDSTS_TI_RESET 0x0
8644
8645
#define ALT_SDMMC_IDSTS_TI_GET(value) (((value) & 0x00000001) >> 0)
8646
8647
#define ALT_SDMMC_IDSTS_TI_SET(value) (((value) << 0) & 0x00000001)
8648
8670
#define ALT_SDMMC_IDSTS_RI_E_NOCLR 0x0
8671
8676
#define ALT_SDMMC_IDSTS_RI_E_CLR 0x1
8677
8679
#define ALT_SDMMC_IDSTS_RI_LSB 1
8680
8681
#define ALT_SDMMC_IDSTS_RI_MSB 1
8682
8683
#define ALT_SDMMC_IDSTS_RI_WIDTH 1
8684
8685
#define ALT_SDMMC_IDSTS_RI_SET_MSK 0x00000002
8686
8687
#define ALT_SDMMC_IDSTS_RI_CLR_MSK 0xfffffffd
8688
8689
#define ALT_SDMMC_IDSTS_RI_RESET 0x0
8690
8691
#define ALT_SDMMC_IDSTS_RI_GET(value) (((value) & 0x00000002) >> 1)
8692
8693
#define ALT_SDMMC_IDSTS_RI_SET(value) (((value) << 1) & 0x00000002)
8694
8717
#define ALT_SDMMC_IDSTS_FBE_E_NOCLR 0x0
8718
8723
#define ALT_SDMMC_IDSTS_FBE_E_CLR 0x1
8724
8726
#define ALT_SDMMC_IDSTS_FBE_LSB 2
8727
8728
#define ALT_SDMMC_IDSTS_FBE_MSB 2
8729
8730
#define ALT_SDMMC_IDSTS_FBE_WIDTH 1
8731
8732
#define ALT_SDMMC_IDSTS_FBE_SET_MSK 0x00000004
8733
8734
#define ALT_SDMMC_IDSTS_FBE_CLR_MSK 0xfffffffb
8735
8736
#define ALT_SDMMC_IDSTS_FBE_RESET 0x0
8737
8738
#define ALT_SDMMC_IDSTS_FBE_GET(value) (((value) & 0x00000004) >> 2)
8739
8740
#define ALT_SDMMC_IDSTS_FBE_SET(value) (((value) << 2) & 0x00000004)
8741
8765
#define ALT_SDMMC_IDSTS_DU_E_NOCLR 0x0
8766
8771
#define ALT_SDMMC_IDSTS_DU_E_CLR 0x1
8772
8774
#define ALT_SDMMC_IDSTS_DU_LSB 4
8775
8776
#define ALT_SDMMC_IDSTS_DU_MSB 4
8777
8778
#define ALT_SDMMC_IDSTS_DU_WIDTH 1
8779
8780
#define ALT_SDMMC_IDSTS_DU_SET_MSK 0x00000010
8781
8782
#define ALT_SDMMC_IDSTS_DU_CLR_MSK 0xffffffef
8783
8784
#define ALT_SDMMC_IDSTS_DU_RESET 0x0
8785
8786
#define ALT_SDMMC_IDSTS_DU_GET(value) (((value) & 0x00000010) >> 4)
8787
8788
#define ALT_SDMMC_IDSTS_DU_SET(value) (((value) << 4) & 0x00000010)
8789
8835
#define ALT_SDMMC_IDSTS_CES_E_NOCLR 0x0
8836
8841
#define ALT_SDMMC_IDSTS_CES_E_CLR 0x1
8842
8844
#define ALT_SDMMC_IDSTS_CES_LSB 5
8845
8846
#define ALT_SDMMC_IDSTS_CES_MSB 5
8847
8848
#define ALT_SDMMC_IDSTS_CES_WIDTH 1
8849
8850
#define ALT_SDMMC_IDSTS_CES_SET_MSK 0x00000020
8851
8852
#define ALT_SDMMC_IDSTS_CES_CLR_MSK 0xffffffdf
8853
8854
#define ALT_SDMMC_IDSTS_CES_RESET 0x0
8855
8856
#define ALT_SDMMC_IDSTS_CES_GET(value) (((value) & 0x00000020) >> 5)
8857
8858
#define ALT_SDMMC_IDSTS_CES_SET(value) (((value) << 5) & 0x00000020)
8859
8891
#define ALT_SDMMC_IDSTS_NIS_E_NOCLR 0x0
8892
8897
#define ALT_SDMMC_IDSTS_NIS_E_CLR 0x1
8898
8900
#define ALT_SDMMC_IDSTS_NIS_LSB 8
8901
8902
#define ALT_SDMMC_IDSTS_NIS_MSB 8
8903
8904
#define ALT_SDMMC_IDSTS_NIS_WIDTH 1
8905
8906
#define ALT_SDMMC_IDSTS_NIS_SET_MSK 0x00000100
8907
8908
#define ALT_SDMMC_IDSTS_NIS_CLR_MSK 0xfffffeff
8909
8910
#define ALT_SDMMC_IDSTS_NIS_RESET 0x0
8911
8912
#define ALT_SDMMC_IDSTS_NIS_GET(value) (((value) & 0x00000100) >> 8)
8913
8914
#define ALT_SDMMC_IDSTS_NIS_SET(value) (((value) << 8) & 0x00000100)
8915
8947
#define ALT_SDMMC_IDSTS_AIS_E_NOCLR 0x0
8948
8953
#define ALT_SDMMC_IDSTS_AIS_E_CLR 0x1
8954
8956
#define ALT_SDMMC_IDSTS_AIS_LSB 9
8957
8958
#define ALT_SDMMC_IDSTS_AIS_MSB 9
8959
8960
#define ALT_SDMMC_IDSTS_AIS_WIDTH 1
8961
8962
#define ALT_SDMMC_IDSTS_AIS_SET_MSK 0x00000200
8963
8964
#define ALT_SDMMC_IDSTS_AIS_CLR_MSK 0xfffffdff
8965
8966
#define ALT_SDMMC_IDSTS_AIS_RESET 0x0
8967
8968
#define ALT_SDMMC_IDSTS_AIS_GET(value) (((value) & 0x00000200) >> 9)
8969
8970
#define ALT_SDMMC_IDSTS_AIS_SET(value) (((value) << 9) & 0x00000200)
8971
9004
#define ALT_SDMMC_IDSTS_EB_E_HOSTARBTTX 0x1
9005
9010
#define ALT_SDMMC_IDSTS_EB_E_HOSTARBRX 0x2
9011
9013
#define ALT_SDMMC_IDSTS_EB_LSB 10
9014
9015
#define ALT_SDMMC_IDSTS_EB_MSB 12
9016
9017
#define ALT_SDMMC_IDSTS_EB_WIDTH 3
9018
9019
#define ALT_SDMMC_IDSTS_EB_SET_MSK 0x00001c00
9020
9021
#define ALT_SDMMC_IDSTS_EB_CLR_MSK 0xffffe3ff
9022
9023
#define ALT_SDMMC_IDSTS_EB_RESET 0x0
9024
9025
#define ALT_SDMMC_IDSTS_EB_GET(value) (((value) & 0x00001c00) >> 10)
9026
9027
#define ALT_SDMMC_IDSTS_EB_SET(value) (((value) << 10) & 0x00001c00)
9028
9076
#define ALT_SDMMC_IDSTS_FSM_E_DMAIDLE 0x0
9077
9082
#define ALT_SDMMC_IDSTS_FSM_E_DMASUSPEND 0x1
9083
9088
#define ALT_SDMMC_IDSTS_FSM_E_DESCRD 0x2
9089
9094
#define ALT_SDMMC_IDSTS_FSM_E_DESCCHK 0x3
9095
9100
#define ALT_SDMMC_IDSTS_FSM_E_DMARDREQWAIT 0x4
9101
9106
#define ALT_SDMMC_IDSTS_FSM_E_DMAWRREQWAIT 0x5
9107
9112
#define ALT_SDMMC_IDSTS_FSM_E_DMARD 0x6
9113
9118
#define ALT_SDMMC_IDSTS_FSM_E_DMAWR 0x7
9119
9124
#define ALT_SDMMC_IDSTS_FSM_E_DECCLOSE 0x8
9125
9127
#define ALT_SDMMC_IDSTS_FSM_LSB 13
9128
9129
#define ALT_SDMMC_IDSTS_FSM_MSB 16
9130
9131
#define ALT_SDMMC_IDSTS_FSM_WIDTH 4
9132
9133
#define ALT_SDMMC_IDSTS_FSM_SET_MSK 0x0001e000
9134
9135
#define ALT_SDMMC_IDSTS_FSM_CLR_MSK 0xfffe1fff
9136
9137
#define ALT_SDMMC_IDSTS_FSM_RESET 0x0
9138
9139
#define ALT_SDMMC_IDSTS_FSM_GET(value) (((value) & 0x0001e000) >> 13)
9140
9141
#define ALT_SDMMC_IDSTS_FSM_SET(value) (((value) << 13) & 0x0001e000)
9142
9143
#ifndef __ASSEMBLY__
9144
9154
struct
ALT_SDMMC_IDSTS_s
9155
{
9156
uint32_t
ti
: 1;
9157
uint32_t
ri
: 1;
9158
uint32_t
fbe
: 1;
9159
uint32_t : 1;
9160
uint32_t
du
: 1;
9161
uint32_t
ces
: 1;
9162
uint32_t : 2;
9163
uint32_t
nis
: 1;
9164
uint32_t
ais
: 1;
9165
const
uint32_t
eb
: 3;
9166
const
uint32_t
fsm
: 4;
9167
uint32_t : 15;
9168
};
9169
9171
typedef
volatile
struct
ALT_SDMMC_IDSTS_s
ALT_SDMMC_IDSTS_t
;
9172
#endif
/* __ASSEMBLY__ */
9173
9175
#define ALT_SDMMC_IDSTS_RESET 0x00000000
9176
9177
#define ALT_SDMMC_IDSTS_OFST 0x8c
9178
9221
#define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0
9222
9227
#define ALT_SDMMC_IDINTEN_TI_E_END 0x1
9228
9230
#define ALT_SDMMC_IDINTEN_TI_LSB 0
9231
9232
#define ALT_SDMMC_IDINTEN_TI_MSB 0
9233
9234
#define ALT_SDMMC_IDINTEN_TI_WIDTH 1
9235
9236
#define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001
9237
9238
#define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe
9239
9240
#define ALT_SDMMC_IDINTEN_TI_RESET 0x0
9241
9242
#define ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0)
9243
9244
#define ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001)
9245
9267
#define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0
9268
9273
#define ALT_SDMMC_IDINTEN_RI_E_END 0x1
9274
9276
#define ALT_SDMMC_IDINTEN_RI_LSB 1
9277
9278
#define ALT_SDMMC_IDINTEN_RI_MSB 1
9279
9280
#define ALT_SDMMC_IDINTEN_RI_WIDTH 1
9281
9282
#define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002
9283
9284
#define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd
9285
9286
#define ALT_SDMMC_IDINTEN_RI_RESET 0x0
9287
9288
#define ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1)
9289
9290
#define ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002)
9291
9314
#define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0
9315
9320
#define ALT_SDMMC_IDINTEN_FBE_E_END 0x1
9321
9323
#define ALT_SDMMC_IDINTEN_FBE_LSB 2
9324
9325
#define ALT_SDMMC_IDINTEN_FBE_MSB 2
9326
9327
#define ALT_SDMMC_IDINTEN_FBE_WIDTH 1
9328
9329
#define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004
9330
9331
#define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb
9332
9333
#define ALT_SDMMC_IDINTEN_FBE_RESET 0x0
9334
9335
#define ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2)
9336
9337
#define ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004)
9338
9360
#define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0
9361
9366
#define ALT_SDMMC_IDINTEN_DU_E_END 0x1
9367
9369
#define ALT_SDMMC_IDINTEN_DU_LSB 4
9370
9371
#define ALT_SDMMC_IDINTEN_DU_MSB 4
9372
9373
#define ALT_SDMMC_IDINTEN_DU_WIDTH 1
9374
9375
#define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010
9376
9377
#define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef
9378
9379
#define ALT_SDMMC_IDINTEN_DU_RESET 0x0
9380
9381
#define ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4)
9382
9383
#define ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010)
9384
9406
#define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0
9407
9412
#define ALT_SDMMC_IDINTEN_CES_E_END 0x1
9413
9415
#define ALT_SDMMC_IDINTEN_CES_LSB 5
9416
9417
#define ALT_SDMMC_IDINTEN_CES_MSB 5
9418
9419
#define ALT_SDMMC_IDINTEN_CES_WIDTH 1
9420
9421
#define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020
9422
9423
#define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf
9424
9425
#define ALT_SDMMC_IDINTEN_CES_RESET 0x0
9426
9427
#define ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5)
9428
9429
#define ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020)
9430
9456
#define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0
9457
9462
#define ALT_SDMMC_IDINTEN_NI_E_END 0x1
9463
9465
#define ALT_SDMMC_IDINTEN_NI_LSB 8
9466
9467
#define ALT_SDMMC_IDINTEN_NI_MSB 8
9468
9469
#define ALT_SDMMC_IDINTEN_NI_WIDTH 1
9470
9471
#define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100
9472
9473
#define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff
9474
9475
#define ALT_SDMMC_IDINTEN_NI_RESET 0x0
9476
9477
#define ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8)
9478
9479
#define ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100)
9480
9506
#define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0
9507
9512
#define ALT_SDMMC_IDINTEN_AI_E_END 0x1
9513
9515
#define ALT_SDMMC_IDINTEN_AI_LSB 9
9516
9517
#define ALT_SDMMC_IDINTEN_AI_MSB 9
9518
9519
#define ALT_SDMMC_IDINTEN_AI_WIDTH 1
9520
9521
#define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200
9522
9523
#define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff
9524
9525
#define ALT_SDMMC_IDINTEN_AI_RESET 0x0
9526
9527
#define ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9)
9528
9529
#define ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200)
9530
9531
#ifndef __ASSEMBLY__
9532
9542
struct
ALT_SDMMC_IDINTEN_s
9543
{
9544
uint32_t
ti
: 1;
9545
uint32_t
ri
: 1;
9546
uint32_t
fbe
: 1;
9547
uint32_t : 1;
9548
uint32_t
du
: 1;
9549
uint32_t
ces
: 1;
9550
uint32_t : 2;
9551
uint32_t
ni
: 1;
9552
uint32_t
ai
: 1;
9553
uint32_t : 22;
9554
};
9555
9557
typedef
volatile
struct
ALT_SDMMC_IDINTEN_s
ALT_SDMMC_IDINTEN_t
;
9558
#endif
/* __ASSEMBLY__ */
9559
9561
#define ALT_SDMMC_IDINTEN_RESET 0x00000000
9562
9563
#define ALT_SDMMC_IDINTEN_OFST 0x90
9564
9588
#define ALT_SDMMC_DSCADDR_HDA_LSB 0
9589
9590
#define ALT_SDMMC_DSCADDR_HDA_MSB 31
9591
9592
#define ALT_SDMMC_DSCADDR_HDA_WIDTH 32
9593
9594
#define ALT_SDMMC_DSCADDR_HDA_SET_MSK 0xffffffff
9595
9596
#define ALT_SDMMC_DSCADDR_HDA_CLR_MSK 0x00000000
9597
9598
#define ALT_SDMMC_DSCADDR_HDA_RESET 0x0
9599
9600
#define ALT_SDMMC_DSCADDR_HDA_GET(value) (((value) & 0xffffffff) >> 0)
9601
9602
#define ALT_SDMMC_DSCADDR_HDA_SET(value) (((value) << 0) & 0xffffffff)
9603
9604
#ifndef __ASSEMBLY__
9605
9615
struct
ALT_SDMMC_DSCADDR_s
9616
{
9617
const
uint32_t
hda
: 32;
9618
};
9619
9621
typedef
volatile
struct
ALT_SDMMC_DSCADDR_s
ALT_SDMMC_DSCADDR_t
;
9622
#endif
/* __ASSEMBLY__ */
9623
9625
#define ALT_SDMMC_DSCADDR_RESET 0x00000000
9626
9627
#define ALT_SDMMC_DSCADDR_OFST 0x94
9628
9652
#define ALT_SDMMC_BUFADDR_HBA_LSB 0
9653
9654
#define ALT_SDMMC_BUFADDR_HBA_MSB 31
9655
9656
#define ALT_SDMMC_BUFADDR_HBA_WIDTH 32
9657
9658
#define ALT_SDMMC_BUFADDR_HBA_SET_MSK 0xffffffff
9659
9660
#define ALT_SDMMC_BUFADDR_HBA_CLR_MSK 0x00000000
9661
9662
#define ALT_SDMMC_BUFADDR_HBA_RESET 0x0
9663
9664
#define ALT_SDMMC_BUFADDR_HBA_GET(value) (((value) & 0xffffffff) >> 0)
9665
9666
#define ALT_SDMMC_BUFADDR_HBA_SET(value) (((value) << 0) & 0xffffffff)
9667
9668
#ifndef __ASSEMBLY__
9669
9679
struct
ALT_SDMMC_BUFADDR_s
9680
{
9681
const
uint32_t
hba
: 32;
9682
};
9683
9685
typedef
volatile
struct
ALT_SDMMC_BUFADDR_s
ALT_SDMMC_BUFADDR_t
;
9686
#endif
/* __ASSEMBLY__ */
9687
9689
#define ALT_SDMMC_BUFADDR_RESET 0x00000000
9690
9691
#define ALT_SDMMC_BUFADDR_OFST 0x98
9692
9737
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_DISD 0x0
9738
9743
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_E_END 0x1
9744
9746
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_LSB 0
9747
9748
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_MSB 0
9749
9750
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_WIDTH 1
9751
9752
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET_MSK 0x00000001
9753
9754
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_CLR_MSK 0xfffffffe
9755
9756
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_RESET 0x0
9757
9758
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_GET(value) (((value) & 0x00000001) >> 0)
9759
9760
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHREN_SET(value) (((value) << 0) & 0x00000001)
9761
9782
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_LSB 1
9783
9784
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_MSB 1
9785
9786
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_WIDTH 1
9787
9788
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET_MSK 0x00000002
9789
9790
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_CLR_MSK 0xfffffffd
9791
9792
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_RESET 0x0
9793
9794
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_GET(value) (((value) & 0x00000002) >> 1)
9795
9796
#define ALT_SDMMC_CARDTHRCTL_BUSY_CLR_INT_EN_SET(value) (((value) << 1) & 0x00000002)
9797
9819
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_LSB 16
9820
9821
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_MSB 28
9822
9823
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_WIDTH 13
9824
9825
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET_MSK 0x1fff0000
9826
9827
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_CLR_MSK 0xe000ffff
9828
9829
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_RESET 0x0
9830
9831
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_GET(value) (((value) & 0x1fff0000) >> 16)
9832
9833
#define ALT_SDMMC_CARDTHRCTL_CARDRDTHRESHOLD_SET(value) (((value) << 16) & 0x1fff0000)
9834
9835
#ifndef __ASSEMBLY__
9836
9846
struct
ALT_SDMMC_CARDTHRCTL_s
9847
{
9848
uint32_t
cardrdthren
: 1;
9849
uint32_t
busy_clr_int_en
: 1;
9850
uint32_t : 14;
9851
uint32_t
cardrdthreshold
: 13;
9852
uint32_t : 3;
9853
};
9854
9856
typedef
volatile
struct
ALT_SDMMC_CARDTHRCTL_s
ALT_SDMMC_CARDTHRCTL_t
;
9857
#endif
/* __ASSEMBLY__ */
9858
9860
#define ALT_SDMMC_CARDTHRCTL_RESET 0x00000000
9861
9862
#define ALT_SDMMC_CARDTHRCTL_OFST 0x100
9863
9903
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND0 0x0
9904
9909
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_E_BACKEND1 0x1
9910
9912
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_LSB 0
9913
9914
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_MSB 15
9915
9916
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_WIDTH 16
9917
9918
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET_MSK 0x0000ffff
9919
9920
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_CLR_MSK 0xffff0000
9921
9922
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_RESET 0x0
9923
9924
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_GET(value) (((value) & 0x0000ffff) >> 0)
9925
9926
#define ALT_SDMMC_BACK_END_POWER_R_BACK_END_POWER_SET(value) (((value) << 0) & 0x0000ffff)
9927
9928
#ifndef __ASSEMBLY__
9929
9939
struct
ALT_SDMMC_BACK_END_POWER_R_s
9940
{
9941
uint32_t
back_end_power
: 16;
9942
uint32_t : 16;
9943
};
9944
9946
typedef
volatile
struct
ALT_SDMMC_BACK_END_POWER_R_s
ALT_SDMMC_BACK_END_POWER_R_t
;
9947
#endif
/* __ASSEMBLY__ */
9948
9950
#define ALT_SDMMC_BACK_END_POWER_R_RESET 0x00000000
9951
9952
#define ALT_SDMMC_BACK_END_POWER_R_OFST 0x104
9953
9989
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_LSB 0
9990
9991
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_MSB 15
9992
9993
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_WIDTH 16
9994
9995
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET_MSK 0x0000ffff
9996
9997
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_CLR_MSK 0xffff0000
9998
9999
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_RESET 0x0
10000
10001
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_GET(value) (((value) & 0x0000ffff) >> 0)
10002
10003
#define ALT_SDMMC_UHS_REG_EXT_MMC_VOLT_REG_SET(value) (((value) << 0) & 0x0000ffff)
10004
10016
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_LSB 16
10017
10018
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_MSB 22
10019
10020
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_WIDTH 7
10021
10022
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET_MSK 0x007f0000
10023
10024
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_CLR_MSK 0xff80ffff
10025
10026
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_RESET 0x0
10027
10028
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_GET(value) (((value) & 0x007f0000) >> 16)
10029
10030
#define ALT_SDMMC_UHS_REG_EXT_CLK_SMPL_PHASE_CTL_SET(value) (((value) << 16) & 0x007f0000)
10031
10043
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_LSB 23
10044
10045
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_MSB 29
10046
10047
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_WIDTH 7
10048
10049
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET_MSK 0x3f800000
10050
10051
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_CLR_MSK 0xc07fffff
10052
10053
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_RESET 0x0
10054
10055
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_GET(value) (((value) & 0x3f800000) >> 23)
10056
10057
#define ALT_SDMMC_UHS_REG_EXT_CLK_DRV_PHASE_CTL_SET(value) (((value) << 23) & 0x3f800000)
10058
10069
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_LSB 30
10070
10071
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_MSB 31
10072
10073
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_WIDTH 2
10074
10075
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET_MSK 0xc0000000
10076
10077
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_CLR_MSK 0x3fffffff
10078
10079
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_RESET 0x0
10080
10081
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_GET(value) (((value) & 0xc0000000) >> 30)
10082
10083
#define ALT_SDMMC_UHS_REG_EXT_EXT_CLK_MUX_CTL_SET(value) (((value) << 30) & 0xc0000000)
10084
10085
#ifndef __ASSEMBLY__
10086
10096
struct
ALT_SDMMC_UHS_REG_EXT_s
10097
{
10098
uint32_t
mmc_volt_reg
: 16;
10099
uint32_t
clk_smpl_phase_ctrl
: 7;
10100
uint32_t
clk_drv_phase_ctrl
: 7;
10101
uint32_t
ext_clk_mux_ctrl
: 2;
10102
};
10103
10105
typedef
volatile
struct
ALT_SDMMC_UHS_REG_EXT_s
ALT_SDMMC_UHS_REG_EXT_t
;
10106
#endif
/* __ASSEMBLY__ */
10107
10109
#define ALT_SDMMC_UHS_REG_EXT_RESET 0x00000000
10110
10111
#define ALT_SDMMC_UHS_REG_EXT_OFST 0x108
10112
10146
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_LSB 0
10147
10148
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_MSB 0
10149
10150
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_WIDTH 1
10151
10152
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET_MSK 0x00000001
10153
10154
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_CLR_MSK 0xfffffffe
10155
10156
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_RESET 0x0
10157
10158
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_GET(value) (((value) & 0x00000001) >> 0)
10159
10160
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET(value) (((value) << 0) & 0x00000001)
10161
10162
#ifndef __ASSEMBLY__
10163
10173
struct
ALT_SDMMC_EMMC_DDR_REG_s
10174
{
10175
uint32_t
half_start_bit
: 1;
10176
uint32_t : 31;
10177
};
10178
10180
typedef
volatile
struct
ALT_SDMMC_EMMC_DDR_REG_s
ALT_SDMMC_EMMC_DDR_REG_t
;
10181
#endif
/* __ASSEMBLY__ */
10182
10184
#define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000
10185
10186
#define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c
10187
10221
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_LSB 0
10222
10223
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_MSB 1
10224
10225
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_WIDTH 2
10226
10227
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET_MSK 0x00000003
10228
10229
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_CLR_MSK 0xfffffffc
10230
10231
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_RESET 0x0
10232
10233
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_GET(value) (((value) & 0x00000003) >> 0)
10234
10235
#define ALT_SDMMC_EN_SHIFT_EN_SHIFT_CARD_SET(value) (((value) << 0) & 0x00000003)
10236
10237
#ifndef __ASSEMBLY__
10238
10248
struct
ALT_SDMMC_EN_SHIFT_s
10249
{
10250
uint32_t
enable_shift_card
: 2;
10251
uint32_t : 30;
10252
};
10253
10255
typedef
volatile
struct
ALT_SDMMC_EN_SHIFT_s
ALT_SDMMC_EN_SHIFT_t
;
10256
#endif
/* __ASSEMBLY__ */
10257
10259
#define ALT_SDMMC_EN_SHIFT_RESET 0x00000000
10260
10261
#define ALT_SDMMC_EN_SHIFT_OFST 0x110
10262
10286
#define ALT_SDMMC_DATA_VALUE_LSB 0
10287
10288
#define ALT_SDMMC_DATA_VALUE_MSB 31
10289
10290
#define ALT_SDMMC_DATA_VALUE_WIDTH 32
10291
10292
#define ALT_SDMMC_DATA_VALUE_SET_MSK 0xffffffff
10293
10294
#define ALT_SDMMC_DATA_VALUE_CLR_MSK 0x00000000
10295
10296
#define ALT_SDMMC_DATA_VALUE_RESET 0x0
10297
10298
#define ALT_SDMMC_DATA_VALUE_GET(value) (((value) & 0xffffffff) >> 0)
10299
10300
#define ALT_SDMMC_DATA_VALUE_SET(value) (((value) << 0) & 0xffffffff)
10301
10302
#ifndef __ASSEMBLY__
10303
10313
struct
ALT_SDMMC_DATA_s
10314
{
10315
uint32_t
value
: 32;
10316
};
10317
10319
typedef
volatile
struct
ALT_SDMMC_DATA_s
ALT_SDMMC_DATA_t
;
10320
#endif
/* __ASSEMBLY__ */
10321
10323
#define ALT_SDMMC_DATA_RESET 0x00000000
10324
10325
#define ALT_SDMMC_DATA_OFST 0x200
10326
10327
#ifndef __ASSEMBLY__
10328
10338
struct
ALT_SDMMC_s
10339
{
10340
volatile
ALT_SDMMC_CTL_t
ctrl
;
10341
volatile
ALT_SDMMC_PWREN_t
pwren
;
10342
volatile
ALT_SDMMC_CLKDIV_t
clkdiv
;
10343
volatile
ALT_SDMMC_CLKSRC_t
clksrc
;
10344
volatile
ALT_SDMMC_CLKENA_t
clkena
;
10345
volatile
ALT_SDMMC_TMOUT_t
tmout
;
10346
volatile
ALT_SDMMC_CTYPE_t
ctype
;
10347
volatile
ALT_SDMMC_BLKSIZ_t
blksiz
;
10348
volatile
ALT_SDMMC_BYTCNT_t
bytcnt
;
10349
volatile
ALT_SDMMC_INTMSK_t
intmask
;
10350
volatile
ALT_SDMMC_CMDARG_t
cmdarg
;
10351
volatile
ALT_SDMMC_CMD_t
cmd
;
10352
volatile
ALT_SDMMC_RESP0_t
resp0
;
10353
volatile
ALT_SDMMC_RESP1_t
resp1
;
10354
volatile
ALT_SDMMC_RESP2_t
resp2
;
10355
volatile
ALT_SDMMC_RESP3_t
resp3
;
10356
volatile
ALT_SDMMC_MINTSTS_t
mintsts
;
10357
volatile
ALT_SDMMC_RINTSTS_t
rintsts
;
10358
volatile
ALT_SDMMC_STAT_t
status
;
10359
volatile
ALT_SDMMC_FIFOTH_t
fifoth
;
10360
volatile
ALT_SDMMC_CDETECT_t
cdetect
;
10361
volatile
ALT_SDMMC_WRTPRT_t
wrtprt
;
10362
volatile
ALT_SDMMC_GPIO_t
gpio
;
10363
volatile
ALT_SDMMC_TCBCNT_t
tcbcnt
;
10364
volatile
ALT_SDMMC_TBBCNT_t
tbbcnt
;
10365
volatile
ALT_SDMMC_DEBNCE_t
debnce
;
10366
volatile
ALT_SDMMC_USRID_t
usrid
;
10367
volatile
ALT_SDMMC_VERID_t
verid
;
10368
volatile
ALT_SDMMC_HCON_t
hcon
;
10369
volatile
ALT_SDMMC_UHS_REG_t
uhs_reg
;
10370
volatile
ALT_SDMMC_RST_N_t
rst_n
;
10371
volatile
uint32_t
_pad_0x7c_0x7f
;
10372
volatile
ALT_SDMMC_BMOD_t
bmod
;
10373
volatile
ALT_SDMMC_PLDMND_t
pldmnd
;
10374
volatile
ALT_SDMMC_DBADDR_t
dbaddr
;
10375
volatile
ALT_SDMMC_IDSTS_t
idsts
;
10376
volatile
ALT_SDMMC_IDINTEN_t
idinten
;
10377
volatile
ALT_SDMMC_DSCADDR_t
dscaddr
;
10378
volatile
ALT_SDMMC_BUFADDR_t
bufaddr
;
10379
volatile
uint32_t
_pad_0x9c_0xff
[25];
10380
volatile
ALT_SDMMC_CARDTHRCTL_t
cardthrctl
;
10381
volatile
ALT_SDMMC_BACK_END_POWER_R_t
back_end_power_r
;
10382
volatile
ALT_SDMMC_UHS_REG_EXT_t
uhs_reg_ext
;
10383
volatile
ALT_SDMMC_EMMC_DDR_REG_t
emmc_ddr_reg
;
10384
volatile
ALT_SDMMC_EN_SHIFT_t
enable_shift
;
10385
volatile
uint32_t
_pad_0x114_0x1ff
[59];
10386
volatile
ALT_SDMMC_DATA_t
data
;
10387
volatile
uint32_t
_pad_0x204_0x400
[127];
10388
};
10389
10391
typedef
volatile
struct
ALT_SDMMC_s
ALT_SDMMC_t
;
10393
struct
ALT_SDMMC_raw_s
10394
{
10395
volatile
uint32_t
ctrl
;
10396
volatile
uint32_t
pwren
;
10397
volatile
uint32_t
clkdiv
;
10398
volatile
uint32_t
clksrc
;
10399
volatile
uint32_t
clkena
;
10400
volatile
uint32_t
tmout
;
10401
volatile
uint32_t
ctype
;
10402
volatile
uint32_t
blksiz
;
10403
volatile
uint32_t
bytcnt
;
10404
volatile
uint32_t
intmask
;
10405
volatile
uint32_t
cmdarg
;
10406
volatile
uint32_t
cmd
;
10407
volatile
uint32_t
resp0
;
10408
volatile
uint32_t
resp1
;
10409
volatile
uint32_t
resp2
;
10410
volatile
uint32_t
resp3
;
10411
volatile
uint32_t
mintsts
;
10412
volatile
uint32_t
rintsts
;
10413
volatile
uint32_t
status
;
10414
volatile
uint32_t
fifoth
;
10415
volatile
uint32_t
cdetect
;
10416
volatile
uint32_t
wrtprt
;
10417
volatile
uint32_t
gpio
;
10418
volatile
uint32_t
tcbcnt
;
10419
volatile
uint32_t
tbbcnt
;
10420
volatile
uint32_t
debnce
;
10421
volatile
uint32_t
usrid
;
10422
volatile
uint32_t
verid
;
10423
volatile
uint32_t
hcon
;
10424
volatile
uint32_t
uhs_reg
;
10425
volatile
uint32_t
rst_n
;
10426
volatile
uint32_t
_pad_0x7c_0x7f
;
10427
volatile
uint32_t
bmod
;
10428
volatile
uint32_t
pldmnd
;
10429
volatile
uint32_t
dbaddr
;
10430
volatile
uint32_t
idsts
;
10431
volatile
uint32_t
idinten
;
10432
volatile
uint32_t
dscaddr
;
10433
volatile
uint32_t
bufaddr
;
10434
volatile
uint32_t
_pad_0x9c_0xff
[25];
10435
volatile
uint32_t
cardthrctl
;
10436
volatile
uint32_t
back_end_power_r
;
10437
volatile
uint32_t
uhs_reg_ext
;
10438
volatile
uint32_t
emmc_ddr_reg
;
10439
volatile
uint32_t
enable_shift
;
10440
volatile
uint32_t
_pad_0x114_0x1ff
[59];
10441
volatile
uint32_t
data
;
10442
volatile
uint32_t
_pad_0x204_0x400
[127];
10443
};
10444
10446
typedef
volatile
struct
ALT_SDMMC_raw_s
ALT_SDMMC_raw_t
;
10447
#endif
/* __ASSEMBLY__ */
10448
10450
#ifdef __cplusplus
10451
}
10452
#endif
/* __cplusplus */
10453
#endif
/* __ALT_SOCAL_SDMMC_H__ */
10454
include
soc_a10
socal
alt_sdmmc.h
Generated on Tue Sep 8 2015 13:33:04 for Altera SoCAL by
1.8.2