Altera SoCAL  16.0
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alt_ecc_ocram_ecc.h
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32 
35 #ifndef __ALT_SOCAL_ECC_OCRAM_ECC_H__
36 #define __ALT_SOCAL_ECC_OCRAM_ECC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
74 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_LSB 0
75 
76 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_MSB 15
77 
78 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_WIDTH 16
79 
80 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 
82 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 
84 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_RESET 0x0
85 
86 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 
88 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 
102 {
103  const uint32_t SIREV : 16;
104  uint32_t : 16;
105 };
106 
109 #endif /* __ASSEMBLY__ */
110 
112 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_RESET 0x00000000
113 
114 #define ALT_ECC_OCRAM_ECC_IP_REV_ID_OFST 0x0
115 
143 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_LSB 0
144 
145 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_MSB 0
146 
147 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_WIDTH 1
148 
149 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET_MSK 0x00000001
150 
151 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
152 
153 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_RESET 0x0
154 
155 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
156 
157 #define ALT_ECC_OCRAM_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
158 
173 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_LSB 1
174 
175 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_MSB 1
176 
177 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_WIDTH 1
178 
179 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET_MSK 0x00000002
180 
181 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_CLR_MSK 0xfffffffd
182 
183 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_RESET 0x1
184 
185 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_GET(value) (((value) & 0x00000002) >> 1)
186 
187 #define ALT_ECC_OCRAM_ECC_CTL_ECC_SLVERR_DIS_SET(value) (((value) << 1) & 0x00000002)
188 
198 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_LSB 8
199 
200 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_MSB 8
201 
202 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_WIDTH 1
203 
204 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
205 
206 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
207 
208 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_RESET 0x0
209 
210 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
211 
212 #define ALT_ECC_OCRAM_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
213 
223 #define ALT_ECC_OCRAM_ECC_CTL_INITA_LSB 16
224 
225 #define ALT_ECC_OCRAM_ECC_CTL_INITA_MSB 16
226 
227 #define ALT_ECC_OCRAM_ECC_CTL_INITA_WIDTH 1
228 
229 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET_MSK 0x00010000
230 
231 #define ALT_ECC_OCRAM_ECC_CTL_INITA_CLR_MSK 0xfffeffff
232 
233 #define ALT_ECC_OCRAM_ECC_CTL_INITA_RESET 0x0
234 
235 #define ALT_ECC_OCRAM_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
236 
237 #define ALT_ECC_OCRAM_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
238 
239 #ifndef __ASSEMBLY__
240 
251 {
252  uint32_t ECC_EN : 1;
253  uint32_t ECC_SLVERR_DIS : 1;
254  uint32_t : 6;
255  uint32_t CNT_RSTA : 1;
256  uint32_t : 7;
257  uint32_t INITA : 1;
258  uint32_t : 15;
259 };
260 
263 #endif /* __ASSEMBLY__ */
264 
266 #define ALT_ECC_OCRAM_ECC_CTL_RESET 0x00000002
267 
268 #define ALT_ECC_OCRAM_ECC_CTL_OFST 0x8
269 
293 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_LSB 0
294 
295 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_MSB 0
296 
297 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
298 
299 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
300 
301 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
302 
303 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
304 
305 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
306 
307 #define ALT_ECC_OCRAM_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
308 
309 #ifndef __ASSEMBLY__
310 
321 {
322  uint32_t INITCOMPLETEA : 1;
323  uint32_t : 31;
324 };
325 
328 #endif /* __ASSEMBLY__ */
329 
331 #define ALT_ECC_OCRAM_ECC_INITSTAT_RESET 0x00000000
332 
333 #define ALT_ECC_OCRAM_ECC_INITSTAT_OFST 0xc
334 
357 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_LSB 0
358 
359 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_MSB 0
360 
361 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_WIDTH 1
362 
363 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
364 
365 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
366 
367 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_RESET 0x0
368 
369 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
370 
371 #define ALT_ECC_OCRAM_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
372 
373 #ifndef __ASSEMBLY__
374 
385 {
386  uint32_t SERRINTEN : 1;
387  uint32_t : 31;
388 };
389 
392 #endif /* __ASSEMBLY__ */
393 
395 #define ALT_ECC_OCRAM_ECC_ERRINTEN_RESET 0x00000000
396 
397 #define ALT_ECC_OCRAM_ECC_ERRINTEN_OFST 0x10
398 
421 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_LSB 0
422 
423 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_MSB 0
424 
425 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_WIDTH 1
426 
427 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
428 
429 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
430 
431 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_RESET 0x0
432 
433 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
434 
435 #define ALT_ECC_OCRAM_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
436 
437 #ifndef __ASSEMBLY__
438 
449 {
450  uint32_t SERRINTS : 1;
451  uint32_t : 31;
452 };
453 
456 #endif /* __ASSEMBLY__ */
457 
459 #define ALT_ECC_OCRAM_ECC_ERRINTENS_RESET 0x00000000
460 
461 #define ALT_ECC_OCRAM_ECC_ERRINTENS_OFST 0x14
462 
492 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_LSB 0
493 
494 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_MSB 0
495 
496 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_WIDTH 1
497 
498 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
499 
500 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
501 
502 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_RESET 0x0
503 
504 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
505 
506 #define ALT_ECC_OCRAM_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
507 
508 #ifndef __ASSEMBLY__
509 
520 {
521  uint32_t SERRINTR : 1;
522  uint32_t : 31;
523 };
524 
527 #endif /* __ASSEMBLY__ */
528 
530 #define ALT_ECC_OCRAM_ECC_ERRINTENR_RESET 0x00000000
531 
532 #define ALT_ECC_OCRAM_ECC_ERRINTENR_OFST 0x18
533 
560 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_LSB 0
561 
562 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_MSB 0
563 
564 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_WIDTH 1
565 
566 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
567 
568 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
569 
570 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_RESET 0x0
571 
572 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
573 
574 #define ALT_ECC_OCRAM_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
575 
585 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_LSB 8
586 
587 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_MSB 8
588 
589 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_WIDTH 1
590 
591 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
592 
593 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
594 
595 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_RESET 0x0
596 
597 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
598 
599 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
600 
610 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_LSB 16
611 
612 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_MSB 16
613 
614 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_WIDTH 1
615 
616 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
617 
618 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
619 
620 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_RESET 0x0
621 
622 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
623 
624 #define ALT_ECC_OCRAM_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
625 
626 #ifndef __ASSEMBLY__
627 
638 {
639  uint32_t INTMODE : 1;
640  uint32_t : 7;
641  uint32_t INTONOVF : 1;
642  uint32_t : 7;
643  uint32_t INTONCMP : 1;
644  uint32_t : 15;
645 };
646 
649 #endif /* __ASSEMBLY__ */
650 
652 #define ALT_ECC_OCRAM_ECC_INTMOD_RESET 0x00000000
653 
654 #define ALT_ECC_OCRAM_ECC_INTMOD_OFST 0x1c
655 
682 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_LSB 0
683 
684 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_MSB 0
685 
686 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_WIDTH 1
687 
688 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
689 
690 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
691 
692 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_RESET 0x0
693 
694 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
695 
696 #define ALT_ECC_OCRAM_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
697 
707 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_LSB 8
708 
709 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_MSB 8
710 
711 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_WIDTH 1
712 
713 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
714 
715 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
716 
717 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_RESET 0x0
718 
719 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
720 
721 #define ALT_ECC_OCRAM_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
722 
723 #ifndef __ASSEMBLY__
724 
735 {
736  uint32_t SERRPENA : 1;
737  uint32_t : 7;
738  uint32_t DERRPENA : 1;
739  uint32_t : 23;
740 };
741 
744 #endif /* __ASSEMBLY__ */
745 
747 #define ALT_ECC_OCRAM_ECC_INTSTAT_RESET 0x00000000
748 
749 #define ALT_ECC_OCRAM_ECC_INTSTAT_OFST 0x20
750 
775 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_LSB 0
776 
777 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_MSB 0
778 
779 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_WIDTH 1
780 
781 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
782 
783 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
784 
785 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_RESET 0x0
786 
787 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
788 
789 #define ALT_ECC_OCRAM_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
790 
800 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_LSB 8
801 
802 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_MSB 8
803 
804 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_WIDTH 1
805 
806 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
807 
808 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
809 
810 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_RESET 0x0
811 
812 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
813 
814 #define ALT_ECC_OCRAM_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
815 
816 #ifndef __ASSEMBLY__
817 
828 {
829  uint32_t TSERRA : 1;
830  uint32_t : 7;
831  uint32_t TDERRA : 1;
832  uint32_t : 23;
833 };
834 
837 #endif /* __ASSEMBLY__ */
838 
840 #define ALT_ECC_OCRAM_ECC_INTTEST_RESET 0x00000000
841 
842 #define ALT_ECC_OCRAM_ECC_INTTEST_OFST 0x24
843 
866 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_LSB 0
867 
868 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_MSB 0
869 
870 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_WIDTH 1
871 
872 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
873 
874 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
875 
876 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_RESET 0x0
877 
878 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
879 
880 #define ALT_ECC_OCRAM_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
881 
882 #ifndef __ASSEMBLY__
883 
894 {
895  uint32_t CMPFLGA : 1;
896  uint32_t : 31;
897 };
898 
901 #endif /* __ASSEMBLY__ */
902 
904 #define ALT_ECC_OCRAM_ECC_MODSTAT_RESET 0x00000000
905 
906 #define ALT_ECC_OCRAM_ECC_MODSTAT_OFST 0x28
907 
931 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_LSB 0
932 
933 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_MSB 14
934 
935 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_WIDTH 15
936 
937 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET_MSK 0x00007fff
938 
939 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_CLR_MSK 0xffff8000
940 
941 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_RESET 0x0
942 
943 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
944 
945 #define ALT_ECC_OCRAM_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
946 
947 #ifndef __ASSEMBLY__
948 
959 {
960  uint32_t Address : 15;
961  uint32_t : 17;
962 };
963 
966 #endif /* __ASSEMBLY__ */
967 
969 #define ALT_ECC_OCRAM_ECC_DERRADDRA_RESET 0x00000000
970 
971 #define ALT_ECC_OCRAM_ECC_DERRADDRA_OFST 0x2c
972 
996 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_LSB 0
997 
998 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_MSB 14
999 
1000 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_WIDTH 15
1001 
1002 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET_MSK 0x00007fff
1003 
1004 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_CLR_MSK 0xffff8000
1005 
1006 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_RESET 0x0
1007 
1008 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
1009 
1010 #define ALT_ECC_OCRAM_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00007fff)
1011 
1012 #ifndef __ASSEMBLY__
1013 
1024 {
1025  uint32_t Address : 15;
1026  uint32_t : 17;
1027 };
1028 
1031 #endif /* __ASSEMBLY__ */
1032 
1034 #define ALT_ECC_OCRAM_ECC_SERRADDRA_RESET 0x00000000
1035 
1036 #define ALT_ECC_OCRAM_ECC_SERRADDRA_OFST 0x30
1037 
1059 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_LSB 0
1060 
1061 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_MSB 31
1062 
1063 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1064 
1065 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1066 
1067 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1068 
1069 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1070 
1071 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1072 
1073 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1074 
1075 #ifndef __ASSEMBLY__
1076 
1087 {
1088  uint32_t SERRCNT : 32;
1089 };
1090 
1093 #endif /* __ASSEMBLY__ */
1094 
1096 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_RESET 0x00000000
1097 
1098 #define ALT_ECC_OCRAM_ECC_SERRCNTREG_OFST 0x3c
1099 
1123 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1124 
1125 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 14
1126 
1127 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 15
1128 
1129 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x00007fff
1130 
1131 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xffff8000
1132 
1133 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1134 
1135 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x00007fff) >> 0)
1136 
1137 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x00007fff)
1138 
1139 #ifndef __ASSEMBLY__
1140 
1151 {
1152  uint32_t ECC_AddrBUS : 15;
1153  uint32_t : 17;
1154 };
1155 
1158 #endif /* __ASSEMBLY__ */
1159 
1161 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_RESET 0x00000000
1162 
1163 #define ALT_ECC_OCRAM_ECC_ECC_ADDRBUS_OFST 0x40
1164 
1186 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1187 
1188 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1189 
1190 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1191 
1192 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1193 
1194 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1195 
1196 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1197 
1198 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1199 
1200 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1201 
1202 #ifndef __ASSEMBLY__
1203 
1214 {
1215  uint32_t ECC_RDataBUS : 32;
1216 };
1217 
1220 #endif /* __ASSEMBLY__ */
1221 
1223 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_RESET 0x00000000
1224 
1225 #define ALT_ECC_OCRAM_ECC_ECC_RDATA0BUS_OFST 0x44
1226 
1248 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1249 
1250 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 31
1251 
1252 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 32
1253 
1254 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1255 
1256 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1257 
1258 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1259 
1260 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1261 
1262 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1263 
1264 #ifndef __ASSEMBLY__
1265 
1276 {
1277  uint32_t ECC_RDataBUS : 32;
1278 };
1279 
1282 #endif /* __ASSEMBLY__ */
1283 
1285 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_RESET 0x00000000
1286 
1287 #define ALT_ECC_OCRAM_ECC_ECC_RDATA1BUS_OFST 0x48
1288 
1310 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1311 
1312 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1313 
1314 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1315 
1316 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1317 
1318 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1319 
1320 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1321 
1322 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1323 
1324 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1325 
1326 #ifndef __ASSEMBLY__
1327 
1338 {
1339  uint32_t ECC_RDataBUS : 32;
1340 };
1341 
1344 #endif /* __ASSEMBLY__ */
1345 
1347 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_RESET 0x00000000
1348 
1349 #define ALT_ECC_OCRAM_ECC_ECC_RDATA2BUS_OFST 0x4c
1350 
1372 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1373 
1374 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1375 
1376 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1377 
1378 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1379 
1380 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1381 
1382 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1383 
1384 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1385 
1386 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1387 
1388 #ifndef __ASSEMBLY__
1389 
1400 {
1401  uint32_t ECC_RDataBUS : 32;
1402 };
1403 
1406 #endif /* __ASSEMBLY__ */
1407 
1409 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_RESET 0x00000000
1410 
1411 #define ALT_ECC_OCRAM_ECC_ECC_RDATA3BUS_OFST 0x50
1412 
1434 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1435 
1436 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1437 
1438 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1439 
1440 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1441 
1442 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1443 
1444 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1445 
1446 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1447 
1448 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1449 
1450 #ifndef __ASSEMBLY__
1451 
1462 {
1463  uint32_t ECC_WDataBUS : 32;
1464 };
1465 
1468 #endif /* __ASSEMBLY__ */
1469 
1471 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_RESET 0x00000000
1472 
1473 #define ALT_ECC_OCRAM_ECC_ECC_WDATA0BUS_OFST 0x54
1474 
1496 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1497 
1498 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 31
1499 
1500 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 32
1501 
1502 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1503 
1504 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1505 
1506 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1507 
1508 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1509 
1510 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1511 
1512 #ifndef __ASSEMBLY__
1513 
1524 {
1525  uint32_t ECC_WDataBUS : 32;
1526 };
1527 
1530 #endif /* __ASSEMBLY__ */
1531 
1533 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_RESET 0x00000000
1534 
1535 #define ALT_ECC_OCRAM_ECC_ECC_WDATA1BUS_OFST 0x58
1536 
1558 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1559 
1560 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1561 
1562 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1563 
1564 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1565 
1566 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1567 
1568 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1569 
1570 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1571 
1572 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1573 
1574 #ifndef __ASSEMBLY__
1575 
1586 {
1587  uint32_t ECC_WDataBUS : 32;
1588 };
1589 
1592 #endif /* __ASSEMBLY__ */
1593 
1595 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_RESET 0x00000000
1596 
1597 #define ALT_ECC_OCRAM_ECC_ECC_WDATA2BUS_OFST 0x5c
1598 
1620 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1621 
1622 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1623 
1624 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1625 
1626 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1627 
1628 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1629 
1630 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1631 
1632 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1633 
1634 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1635 
1636 #ifndef __ASSEMBLY__
1637 
1648 {
1649  uint32_t ECC_WDataBUS : 32;
1650 };
1651 
1654 #endif /* __ASSEMBLY__ */
1655 
1657 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_RESET 0x00000000
1658 
1659 #define ALT_ECC_OCRAM_ECC_ECC_WDATA3BUS_OFST 0x60
1660 
1690 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1691 
1692 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 4
1693 
1694 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 5
1695 
1696 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000001f
1697 
1698 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffffe0
1699 
1700 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1701 
1702 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
1703 
1704 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
1705 
1715 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1716 
1717 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 12
1718 
1719 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 5
1720 
1721 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00001f00
1722 
1723 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffffe0ff
1724 
1725 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1726 
1727 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
1728 
1729 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
1730 
1740 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1741 
1742 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 20
1743 
1744 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 5
1745 
1746 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x001f0000
1747 
1748 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xffe0ffff
1749 
1750 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1751 
1752 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
1753 
1754 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
1755 
1765 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1766 
1767 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 28
1768 
1769 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 5
1770 
1771 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x1f000000
1772 
1773 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0xe0ffffff
1774 
1775 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1776 
1777 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
1778 
1779 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
1780 
1781 #ifndef __ASSEMBLY__
1782 
1793 {
1794  uint32_t ECC_RDataecc0BUS : 5;
1795  uint32_t : 3;
1796  uint32_t ECC_RDataecc1BUS : 5;
1797  uint32_t : 3;
1798  uint32_t ECC_RDataecc2BUS : 5;
1799  uint32_t : 3;
1800  uint32_t ECC_RDataecc3BUS : 5;
1801  uint32_t : 3;
1802 };
1803 
1806 #endif /* __ASSEMBLY__ */
1807 
1809 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1810 
1811 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC0BUS_OFST 0x64
1812 
1842 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1843 
1844 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 4
1845 
1846 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 5
1847 
1848 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000001f
1849 
1850 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffffe0
1851 
1852 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1853 
1854 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
1855 
1856 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
1857 
1867 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1868 
1869 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 12
1870 
1871 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 5
1872 
1873 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00001f00
1874 
1875 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffffe0ff
1876 
1877 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1878 
1879 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
1880 
1881 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
1882 
1892 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1893 
1894 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 20
1895 
1896 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 5
1897 
1898 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x001f0000
1899 
1900 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xffe0ffff
1901 
1902 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1903 
1904 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
1905 
1906 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
1907 
1917 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1918 
1919 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 28
1920 
1921 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 5
1922 
1923 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x1f000000
1924 
1925 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0xe0ffffff
1926 
1927 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1928 
1929 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
1930 
1931 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
1932 
1933 #ifndef __ASSEMBLY__
1934 
1945 {
1946  uint32_t ECC_RDataecc4BUS : 5;
1947  uint32_t : 3;
1948  uint32_t ECC_RDataecc5BUS : 5;
1949  uint32_t : 3;
1950  uint32_t ECC_RDataecc6BUS : 5;
1951  uint32_t : 3;
1952  uint32_t ECC_RDataecc7BUS : 5;
1953  uint32_t : 3;
1954 };
1955 
1958 #endif /* __ASSEMBLY__ */
1959 
1961 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1962 
1963 #define ALT_ECC_OCRAM_ECC_ECC_RDATAECC1BUS_OFST 0x68
1964 
1994 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1995 
1996 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 4
1997 
1998 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 5
1999 
2000 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000001f
2001 
2002 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffffe0
2003 
2004 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
2005 
2006 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000001f) >> 0)
2007 
2008 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000001f)
2009 
2019 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
2020 
2021 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 12
2022 
2023 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 5
2024 
2025 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00001f00
2026 
2027 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffffe0ff
2028 
2029 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2030 
2031 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00001f00) >> 8)
2032 
2033 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00001f00)
2034 
2044 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2045 
2046 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 20
2047 
2048 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 5
2049 
2050 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x001f0000
2051 
2052 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xffe0ffff
2053 
2054 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2055 
2056 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x001f0000) >> 16)
2057 
2058 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x001f0000)
2059 
2069 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2070 
2071 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 28
2072 
2073 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 5
2074 
2075 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x1f000000
2076 
2077 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0xe0ffffff
2078 
2079 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2080 
2081 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x1f000000) >> 24)
2082 
2083 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x1f000000)
2084 
2085 #ifndef __ASSEMBLY__
2086 
2097 {
2098  uint32_t ECC_WDataecc0BUS : 5;
2099  uint32_t : 3;
2100  uint32_t ECC_WDataecc1BUS : 5;
2101  uint32_t : 3;
2102  uint32_t ECC_WDataecc2BUS : 5;
2103  uint32_t : 3;
2104  uint32_t ECC_WDataecc3BUS : 5;
2105  uint32_t : 3;
2106 };
2107 
2110 #endif /* __ASSEMBLY__ */
2111 
2113 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2114 
2115 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2116 
2146 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2147 
2148 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 4
2149 
2150 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 5
2151 
2152 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000001f
2153 
2154 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffffe0
2155 
2156 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2157 
2158 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000001f) >> 0)
2159 
2160 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000001f)
2161 
2171 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2172 
2173 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 12
2174 
2175 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 5
2176 
2177 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00001f00
2178 
2179 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffffe0ff
2180 
2181 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2182 
2183 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00001f00) >> 8)
2184 
2185 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00001f00)
2186 
2196 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2197 
2198 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 20
2199 
2200 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 5
2201 
2202 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x001f0000
2203 
2204 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xffe0ffff
2205 
2206 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2207 
2208 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x001f0000) >> 16)
2209 
2210 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x001f0000)
2211 
2221 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2222 
2223 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 28
2224 
2225 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 5
2226 
2227 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x1f000000
2228 
2229 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0xe0ffffff
2230 
2231 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2232 
2233 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x1f000000) >> 24)
2234 
2235 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x1f000000)
2236 
2237 #ifndef __ASSEMBLY__
2238 
2249 {
2250  uint32_t ECC_WDataecc4BUS : 5;
2251  uint32_t : 3;
2252  uint32_t ECC_WDataecc5BUS : 5;
2253  uint32_t : 3;
2254  uint32_t ECC_WDataecc6BUS : 5;
2255  uint32_t : 3;
2256  uint32_t ECC_WDataecc7BUS : 5;
2257  uint32_t : 3;
2258 };
2259 
2262 #endif /* __ASSEMBLY__ */
2263 
2265 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2266 
2267 #define ALT_ECC_OCRAM_ECC_ECC_WDATAECC1BUS_OFST 0x70
2268 
2291 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_LSB 0
2292 
2293 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_MSB 7
2294 
2295 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_WIDTH 8
2296 
2297 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x000000ff
2298 
2299 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xffffff00
2300 
2301 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2302 
2303 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x000000ff) >> 0)
2304 
2305 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x000000ff)
2306 
2307 #ifndef __ASSEMBLY__
2308 
2319 {
2320  uint32_t DBEN : 8;
2321  uint32_t : 24;
2322 };
2323 
2326 #endif /* __ASSEMBLY__ */
2327 
2329 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_RESET 0x00000000
2330 
2331 #define ALT_ECC_OCRAM_ECC_ECC_DBYTECTL_OFST 0x74
2332 
2363 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2364 
2365 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2366 
2367 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2368 
2369 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2370 
2371 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2372 
2373 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2374 
2375 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2376 
2377 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2378 
2388 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2389 
2390 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2391 
2392 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2393 
2394 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2395 
2396 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2397 
2398 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2399 
2400 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2401 
2402 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2403 
2413 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_LSB 8
2414 
2415 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_MSB 8
2416 
2417 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2418 
2419 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2420 
2421 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2422 
2423 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2424 
2425 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2426 
2427 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2428 
2429 #ifndef __ASSEMBLY__
2430 
2441 {
2442  uint32_t DATAOVR : 1;
2443  uint32_t ECCOVR : 1;
2444  uint32_t : 6;
2445  uint32_t RDWR : 1;
2446  uint32_t : 23;
2447 };
2448 
2451 #endif /* __ASSEMBLY__ */
2452 
2454 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_RESET 0x00000000
2455 
2456 #define ALT_ECC_OCRAM_ECC_ECC_ACCCTL_OFST 0x78
2457 
2481 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_LSB 16
2482 
2483 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_MSB 16
2484 
2485 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2486 
2487 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2488 
2489 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2490 
2491 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2492 
2493 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2494 
2495 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2496 
2497 #ifndef __ASSEMBLY__
2498 
2509 {
2510  uint32_t : 16;
2511  uint32_t ENBUSA : 1;
2512  uint32_t : 15;
2513 };
2514 
2517 #endif /* __ASSEMBLY__ */
2518 
2520 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_RESET 0x00000000
2521 
2522 #define ALT_ECC_OCRAM_ECC_ECC_STARTACC_OFST 0x7c
2523 
2546 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2547 
2548 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2549 
2550 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2551 
2552 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2553 
2554 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2555 
2556 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2557 
2558 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2559 
2560 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2561 
2562 #ifndef __ASSEMBLY__
2563 
2574 {
2575  uint32_t WDEN_RAM : 1;
2576  uint32_t : 31;
2577 };
2578 
2581 #endif /* __ASSEMBLY__ */
2582 
2584 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_RESET 0x00000000
2585 
2586 #define ALT_ECC_OCRAM_ECC_ECC_WDCTL_OFST 0x80
2587 
2615 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_LSB 0
2616 
2617 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_MSB 14
2618 
2619 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_WIDTH 15
2620 
2621 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET_MSK 0x00007fff
2622 
2623 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xffff8000
2624 
2625 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_RESET 0x0
2626 
2627 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x00007fff) >> 0)
2628 
2629 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x00007fff)
2630 
2641 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_LSB 31
2642 
2643 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_MSB 31
2644 
2645 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_WIDTH 1
2646 
2647 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2648 
2649 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2650 
2651 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_RESET 0x0
2652 
2653 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2654 
2655 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2656 
2657 #ifndef __ASSEMBLY__
2658 
2669 {
2670  const uint32_t Address : 15;
2671  uint32_t : 16;
2672  uint32_t VALID : 1;
2673 };
2674 
2677 #endif /* __ASSEMBLY__ */
2678 
2680 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_RESET 0x00000000
2681 
2682 #define ALT_ECC_OCRAM_ECC_SERRLKUPA0_OFST 0x90
2683 
2684 #ifndef __ASSEMBLY__
2685 
2696 {
2698  volatile uint32_t _pad_0x4_0x7;
2710  volatile uint32_t _pad_0x34_0x3b[2];
2729  volatile uint32_t _pad_0x84_0x8f[3];
2731  volatile uint32_t _pad_0x94_0x400[219];
2732 };
2733 
2738 {
2739  volatile uint32_t IP_REV_ID;
2740  volatile uint32_t _pad_0x4_0x7;
2741  volatile uint32_t CTRL;
2742  volatile uint32_t INITSTAT;
2743  volatile uint32_t ERRINTEN;
2744  volatile uint32_t ERRINTENS;
2745  volatile uint32_t ERRINTENR;
2746  volatile uint32_t INTMODE;
2747  volatile uint32_t INTSTAT;
2748  volatile uint32_t INTTEST;
2749  volatile uint32_t MODSTAT;
2750  volatile uint32_t DERRADDRA;
2751  volatile uint32_t SERRADDRA;
2752  volatile uint32_t _pad_0x34_0x3b[2];
2753  volatile uint32_t SERRCNTREG;
2754  volatile uint32_t ECC_Addrbus;
2755  volatile uint32_t ECC_RData0bus;
2756  volatile uint32_t ECC_RData1bus;
2757  volatile uint32_t ECC_RData2bus;
2758  volatile uint32_t ECC_RData3bus;
2759  volatile uint32_t ECC_WData0bus;
2760  volatile uint32_t ECC_WData1bus;
2761  volatile uint32_t ECC_WData2bus;
2762  volatile uint32_t ECC_WData3bus;
2763  volatile uint32_t ECC_RDataecc0bus;
2764  volatile uint32_t ECC_RDataecc1bus;
2765  volatile uint32_t ECC_WDataecc0bus;
2766  volatile uint32_t ECC_WDataecc1bus;
2767  volatile uint32_t ECC_dbytectrl;
2768  volatile uint32_t ECC_accctrl;
2769  volatile uint32_t ECC_startacc;
2770  volatile uint32_t ECC_wdctrl;
2771  volatile uint32_t _pad_0x84_0x8f[3];
2772  volatile uint32_t SERRLKUPA0;
2773  volatile uint32_t _pad_0x94_0x400[219];
2774 };
2775 
2778 #endif /* __ASSEMBLY__ */
2779 
2781 #ifdef __cplusplus
2782 }
2783 #endif /* __cplusplus */
2784 #endif /* __ALT_SOCAL_ECC_OCRAM_ECC_H__ */
2785