Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dramaddrw

Description

Register Layout

Bits Access Reset Description
[4:0] RW 0x0 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH
[9:5] RW 0x0 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH
[13:10] RW 0x0 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH
[15:14] RW 0x0 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH
[18:16] RW 0x0 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH
[31:19] ??? 0x0 UNDEFINED

Field : cfg_col_addr_width

The number of column address bits for the memory devices in your memory interface.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB   0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB   4
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH   5
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK   0x0000001f
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK   0xffffffe0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET(value)   (((value) & 0x0000001f) >> 0)
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET(value)   (((value) << 0) & 0x0000001f)
 

Field : cfg_row_addr_width

The number of row address bits for the memory devices in your memory interface.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB   5
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB   9
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH   5
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK   0x000003e0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK   0xfffffc1f
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET(value)   (((value) & 0x000003e0) >> 5)
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET(value)   (((value) << 5) & 0x000003e0)
 

Field : cfg_bank_addr_width

The number of bank address bits for the memory devices in your memory interface.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB   10
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB   13
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH   4
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK   0x00003c00
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK   0xffffc3ff
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET(value)   (((value) & 0x00003c00) >> 10)
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET(value)   (((value) << 10) & 0x00003c00)
 

Field : cfg_bank_group_addr_width

The number of bank group address bits for the memory devices in your memory interface.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB   14
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB   15
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH   2
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK   0x0000c000
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK   0xffff3fff
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET(value)   (((value) & 0x0000c000) >> 14)
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET(value)   (((value) << 14) & 0x0000c000)
 

Field : cfg_cs_addr_width

The number of chip select address bits for the memory devices in your memory interface.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB   16
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB   18
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH   3
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK   0x00070000
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK   0xfff8ffff
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET(value)   (((value) & 0x00070000) >> 16)
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET(value)   (((value) << 16) & 0x00070000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DRAMADDRW_s
 

Macros

#define ALT_IO48_HMC_MMR_DRAMADDRW_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DRAMADDRW_OFST   0xa8
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DRAMADDRW_s 
ALT_IO48_HMC_MMR_DRAMADDRW_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DRAMADDRW_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DRAMADDRW.

Data Fields
uint32_t cfg_col_addr_width: 5 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH
uint32_t cfg_row_addr_width: 5 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH
uint32_t cfg_bank_addr_width: 4 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH
uint32_t cfg_bank_group_addr_width: 2 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH
uint32_t cfg_cs_addr_width: 3 ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH
uint32_t __pad0__: 13 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_MSB   4

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET_MSK   0x0000001f

The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_CLR_MSK   0xffffffe0

The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_GET (   value)    (((value) & 0x0000001f) >> 0)

Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH field value from a register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH_SET (   value)    (((value) << 0) & 0x0000001f)

Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_COL_ADDR_WIDTH register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_LSB   5

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_MSB   9

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET_MSK   0x000003e0

The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_CLR_MSK   0xfffffc1f

The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_GET (   value)    (((value) & 0x000003e0) >> 5)

Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH field value from a register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH_SET (   value)    (((value) << 5) & 0x000003e0)

Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_ROW_ADDR_WIDTH register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_LSB   10

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_MSB   13

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET_MSK   0x00003c00

The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_CLR_MSK   0xffffc3ff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_GET (   value)    (((value) & 0x00003c00) >> 10)

Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH field value from a register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH_SET (   value)    (((value) << 10) & 0x00003c00)

Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_ADDR_WIDTH register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_LSB   14

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET_MSK   0x0000c000

The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_CLR_MSK   0xffff3fff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_GET (   value)    (((value) & 0x0000c000) >> 14)

Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH field value from a register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH_SET (   value)    (((value) << 14) & 0x0000c000)

Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_BANK_GROUP_ADDR_WIDTH register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_MSB   18

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET_MSK   0x00070000

The mask used to set the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_CLR_MSK   0xfff8ffff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_GET (   value)    (((value) & 0x00070000) >> 16)

Extracts the ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH field value from a register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH_SET (   value)    (((value) << 16) & 0x00070000)

Produces a ALT_IO48_HMC_MMR_DRAMADDRW_CFG_CS_ADDR_WIDTH register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DRAMADDRW register.

#define ALT_IO48_HMC_MMR_DRAMADDRW_OFST   0xa8

The byte offset of the ALT_IO48_HMC_MMR_DRAMADDRW register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DRAMADDRW.