Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : mpu_status_l2_ecc

Description

This is a read only register which reads the current mpu L2 ecc interrupt status.

A write to this register should return an error.

Register Layout

Bits Access Reset Description
[11:0] RW Unknown ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO
[14:12] ??? Unknown UNDEFINED
[15] RW Unknown ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING
[27:16] RW Unknown ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO
[30:28] ??? Unknown UNDEFINED
[31] RW Unknown ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING

Field : serr_info

12 bit Serr Info field.

In Baum this will be the index and way information where the ECC error occured.

Field Access Macros:

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_LSB   0
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_MSB   11
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_WIDTH   12
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET_MSK   0x00000fff
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_CLR_MSK   0xfffff000
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_RESET   0x0
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_GET(value)   (((value) & 0x00000fff) >> 0)
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET(value)   (((value) << 0) & 0x00000fff)
 

Field : serr_pending

Unmaksed value of a pending single bit ECC error status.

Field Access Macros:

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_LSB   15
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_MSB   15
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_WIDTH   1
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET_MSK   0x00008000
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_CLR_MSK   0xffff7fff
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_RESET   0x0
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET(value)   (((value) << 15) & 0x00008000)
 

Field : merr_info

12 bit Serr Info field.

In Baum this will be the index and way information where the ECC error occured.

Field Access Macros:

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_LSB   16
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_MSB   27
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_WIDTH   12
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET_MSK   0x0fff0000
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_CLR_MSK   0xf000ffff
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_RESET   0x0
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_GET(value)   (((value) & 0x0fff0000) >> 16)
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET(value)   (((value) << 16) & 0x0fff0000)
 

Field : merr_pending

Unmaksed value of a pending multiple bits ECC error status.

Field Access Macros:

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_LSB   31
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_MSB   31
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_WIDTH   1
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET_MSK   0x80000000
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_CLR_MSK   0x7fffffff
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_RESET   0x0
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_SYSMGR_MPU_STAT_L2_ECC_s
 

Macros

#define ALT_SYSMGR_MPU_STAT_L2_ECC_RESET   0x00000000
 
#define ALT_SYSMGR_MPU_STAT_L2_ECC_OFST   0xa4
 

Typedefs

typedef struct
ALT_SYSMGR_MPU_STAT_L2_ECC_s 
ALT_SYSMGR_MPU_STAT_L2_ECC_t
 

Data Structure Documentation

struct ALT_SYSMGR_MPU_STAT_L2_ECC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_MPU_STAT_L2_ECC.

Data Fields
uint32_t serr_info: 12 ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO
uint32_t __pad0__: 3 UNDEFINED
uint32_t serr_pending: 1 ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING
uint32_t merr_info: 12 ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO
uint32_t __pad1__: 3 UNDEFINED
uint32_t merr_pending: 1 ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING

Macro Definitions

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_MSB   11

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_WIDTH   12

The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET_MSK   0x00000fff

The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_CLR_MSK   0xfffff000

The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field is UNKNOWN.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_GET (   value)    (((value) & 0x00000fff) >> 0)

Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO field value from a register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO_SET (   value)    (((value) << 0) & 0x00000fff)

Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_INFO register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_LSB   15

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_MSB   15

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET_MSK   0x00008000

The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_CLR_MSK   0xffff7fff

The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field is UNKNOWN.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING field value from a register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_SERR_PENDING register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_LSB   16

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_MSB   27

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_WIDTH   12

The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET_MSK   0x0fff0000

The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_CLR_MSK   0xf000ffff

The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field is UNKNOWN.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_GET (   value)    (((value) & 0x0fff0000) >> 16)

Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO field value from a register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO_SET (   value)    (((value) << 16) & 0x0fff0000)

Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_INFO register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_LSB   31

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_MSB   31

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET_MSK   0x80000000

The mask used to set the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_CLR_MSK   0x7fffffff

The mask used to clear the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field is UNKNOWN.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING field value from a register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_SYSMGR_MPU_STAT_L2_ECC_MERR_PENDING register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_RESET   0x00000000

The reset value of the ALT_SYSMGR_MPU_STAT_L2_ECC register.

#define ALT_SYSMGR_MPU_STAT_L2_ECC_OFST   0xa4

The byte offset of the ALT_SYSMGR_MPU_STAT_L2_ECC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_MPU_STAT_L2_ECC.