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alt_ecc_emac1_rx_ecc.h
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32 
35 #ifndef __ALT_SOCAL_ECC_EMAC1_RX_ECC_H__
36 #define __ALT_SOCAL_ECC_EMAC1_RX_ECC_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
74 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_LSB 0
75 
76 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_MSB 15
77 
78 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_WIDTH 16
79 
80 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
81 
82 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
83 
84 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_RESET 0x0
85 
86 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
87 
88 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89 
90 #ifndef __ASSEMBLY__
91 
102 {
103  const uint32_t SIREV : 16;
104  uint32_t : 16;
105 };
106 
109 #endif /* __ASSEMBLY__ */
110 
112 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_RESET 0x00000000
113 
114 #define ALT_ECC_EMAC1_RX_ECC_IP_REV_ID_OFST 0x0
115 
142 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_LSB 0
143 
144 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_MSB 0
145 
146 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_WIDTH 1
147 
148 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_SET_MSK 0x00000001
149 
150 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
151 
152 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_RESET 0x0
153 
154 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
155 
156 #define ALT_ECC_EMAC1_RX_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
157 
167 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_LSB 8
168 
169 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_MSB 8
170 
171 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_WIDTH 1
172 
173 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
174 
175 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
176 
177 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_RESET 0x0
178 
179 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
180 
181 #define ALT_ECC_EMAC1_RX_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
182 
192 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_LSB 16
193 
194 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_MSB 16
195 
196 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_WIDTH 1
197 
198 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_SET_MSK 0x00010000
199 
200 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_CLR_MSK 0xfffeffff
201 
202 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_RESET 0x0
203 
204 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
205 
206 #define ALT_ECC_EMAC1_RX_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
207 
208 #ifndef __ASSEMBLY__
209 
220 {
221  uint32_t ECC_EN : 1;
222  uint32_t : 7;
223  uint32_t CNT_RSTA : 1;
224  uint32_t : 7;
225  uint32_t INITA : 1;
226  uint32_t : 15;
227 };
228 
231 #endif /* __ASSEMBLY__ */
232 
234 #define ALT_ECC_EMAC1_RX_ECC_CTL_RESET 0x00000000
235 
236 #define ALT_ECC_EMAC1_RX_ECC_CTL_OFST 0x8
237 
261 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_LSB 0
262 
263 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_MSB 0
264 
265 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
266 
267 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
268 
269 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
270 
271 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
272 
273 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
274 
275 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
276 
277 #ifndef __ASSEMBLY__
278 
289 {
290  uint32_t INITCOMPLETEA : 1;
291  uint32_t : 31;
292 };
293 
296 #endif /* __ASSEMBLY__ */
297 
299 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_RESET 0x00000000
300 
301 #define ALT_ECC_EMAC1_RX_ECC_INITSTAT_OFST 0xc
302 
325 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_LSB 0
326 
327 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_MSB 0
328 
329 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_WIDTH 1
330 
331 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
332 
333 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
334 
335 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_RESET 0x0
336 
337 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
338 
339 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
340 
341 #ifndef __ASSEMBLY__
342 
353 {
354  uint32_t SERRINTEN : 1;
355  uint32_t : 31;
356 };
357 
360 #endif /* __ASSEMBLY__ */
361 
363 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_RESET 0x00000000
364 
365 #define ALT_ECC_EMAC1_RX_ECC_ERRINTEN_OFST 0x10
366 
389 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_LSB 0
390 
391 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_MSB 0
392 
393 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_WIDTH 1
394 
395 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
396 
397 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
398 
399 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_RESET 0x0
400 
401 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
402 
403 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
404 
405 #ifndef __ASSEMBLY__
406 
417 {
418  uint32_t SERRINTS : 1;
419  uint32_t : 31;
420 };
421 
424 #endif /* __ASSEMBLY__ */
425 
427 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_RESET 0x00000000
428 
429 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENS_OFST 0x14
430 
460 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_LSB 0
461 
462 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_MSB 0
463 
464 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_WIDTH 1
465 
466 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
467 
468 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
469 
470 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_RESET 0x0
471 
472 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
473 
474 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
475 
476 #ifndef __ASSEMBLY__
477 
488 {
489  uint32_t SERRINTR : 1;
490  uint32_t : 31;
491 };
492 
495 #endif /* __ASSEMBLY__ */
496 
498 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_RESET 0x00000000
499 
500 #define ALT_ECC_EMAC1_RX_ECC_ERRINTENR_OFST 0x18
501 
528 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_LSB 0
529 
530 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_MSB 0
531 
532 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_WIDTH 1
533 
534 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
535 
536 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
537 
538 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_RESET 0x0
539 
540 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
541 
542 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
543 
553 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_LSB 8
554 
555 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_MSB 8
556 
557 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_WIDTH 1
558 
559 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
560 
561 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
562 
563 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_RESET 0x0
564 
565 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
566 
567 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
568 
578 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_LSB 16
579 
580 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_MSB 16
581 
582 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_WIDTH 1
583 
584 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
585 
586 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
587 
588 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_RESET 0x0
589 
590 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
591 
592 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
593 
594 #ifndef __ASSEMBLY__
595 
606 {
607  uint32_t INTMODE : 1;
608  uint32_t : 7;
609  uint32_t INTONOVF : 1;
610  uint32_t : 7;
611  uint32_t INTONCMP : 1;
612  uint32_t : 15;
613 };
614 
617 #endif /* __ASSEMBLY__ */
618 
620 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_RESET 0x00000000
621 
622 #define ALT_ECC_EMAC1_RX_ECC_INTMOD_OFST 0x1c
623 
650 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_LSB 0
651 
652 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_MSB 0
653 
654 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_WIDTH 1
655 
656 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
657 
658 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
659 
660 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_RESET 0x0
661 
662 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
663 
664 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
665 
675 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_LSB 8
676 
677 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_MSB 8
678 
679 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_WIDTH 1
680 
681 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
682 
683 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
684 
685 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_RESET 0x0
686 
687 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
688 
689 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
690 
691 #ifndef __ASSEMBLY__
692 
703 {
704  uint32_t SERRPENA : 1;
705  uint32_t : 7;
706  uint32_t DERRPENA : 1;
707  uint32_t : 23;
708 };
709 
712 #endif /* __ASSEMBLY__ */
713 
715 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_RESET 0x00000000
716 
717 #define ALT_ECC_EMAC1_RX_ECC_INTSTAT_OFST 0x20
718 
743 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_LSB 0
744 
745 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_MSB 0
746 
747 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_WIDTH 1
748 
749 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
750 
751 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
752 
753 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_RESET 0x0
754 
755 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
756 
757 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
758 
768 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_LSB 8
769 
770 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_MSB 8
771 
772 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_WIDTH 1
773 
774 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
775 
776 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
777 
778 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_RESET 0x0
779 
780 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
781 
782 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
783 
784 #ifndef __ASSEMBLY__
785 
796 {
797  uint32_t TSERRA : 1;
798  uint32_t : 7;
799  uint32_t TDERRA : 1;
800  uint32_t : 23;
801 };
802 
805 #endif /* __ASSEMBLY__ */
806 
808 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_RESET 0x00000000
809 
810 #define ALT_ECC_EMAC1_RX_ECC_INTTEST_OFST 0x24
811 
834 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_LSB 0
835 
836 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_MSB 0
837 
838 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_WIDTH 1
839 
840 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
841 
842 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
843 
844 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_RESET 0x0
845 
846 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
847 
848 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
849 
850 #ifndef __ASSEMBLY__
851 
862 {
863  uint32_t CMPFLGA : 1;
864  uint32_t : 31;
865 };
866 
869 #endif /* __ASSEMBLY__ */
870 
872 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_RESET 0x00000000
873 
874 #define ALT_ECC_EMAC1_RX_ECC_MODSTAT_OFST 0x28
875 
899 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_LSB 0
900 
901 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_MSB 11
902 
903 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_WIDTH 12
904 
905 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_SET_MSK 0x00000fff
906 
907 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_CLR_MSK 0xfffff000
908 
909 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_RESET 0x0
910 
911 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x00000fff) >> 0)
912 
913 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00000fff)
914 
915 #ifndef __ASSEMBLY__
916 
927 {
928  uint32_t Address : 12;
929  uint32_t : 20;
930 };
931 
934 #endif /* __ASSEMBLY__ */
935 
937 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_RESET 0x00000000
938 
939 #define ALT_ECC_EMAC1_RX_ECC_DERRADDRA_OFST 0x2c
940 
964 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_LSB 0
965 
966 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_MSB 11
967 
968 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_WIDTH 12
969 
970 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_SET_MSK 0x00000fff
971 
972 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_CLR_MSK 0xfffff000
973 
974 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_RESET 0x0
975 
976 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x00000fff) >> 0)
977 
978 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x00000fff)
979 
980 #ifndef __ASSEMBLY__
981 
992 {
993  uint32_t Address : 12;
994  uint32_t : 20;
995 };
996 
999 #endif /* __ASSEMBLY__ */
1000 
1002 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_RESET 0x00000000
1003 
1004 #define ALT_ECC_EMAC1_RX_ECC_SERRADDRA_OFST 0x30
1005 
1027 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_LSB 0
1028 
1029 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_MSB 31
1030 
1031 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1032 
1033 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1034 
1035 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1036 
1037 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1038 
1039 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1040 
1041 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1042 
1043 #ifndef __ASSEMBLY__
1044 
1055 {
1056  uint32_t SERRCNT : 32;
1057 };
1058 
1061 #endif /* __ASSEMBLY__ */
1062 
1064 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_RESET 0x00000000
1065 
1066 #define ALT_ECC_EMAC1_RX_ECC_SERRCNTREG_OFST 0x3c
1067 
1091 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1092 
1093 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 11
1094 
1095 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 12
1096 
1097 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x00000fff
1098 
1099 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffff000
1100 
1101 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1102 
1103 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x00000fff) >> 0)
1104 
1105 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x00000fff)
1106 
1107 #ifndef __ASSEMBLY__
1108 
1119 {
1120  uint32_t ECC_AddrBUS : 12;
1121  uint32_t : 20;
1122 };
1123 
1126 #endif /* __ASSEMBLY__ */
1127 
1129 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_RESET 0x00000000
1130 
1131 #define ALT_ECC_EMAC1_RX_ECC_ECC_ADDRBUS_OFST 0x40
1132 
1154 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1155 
1156 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1157 
1158 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1159 
1160 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1161 
1162 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1163 
1164 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1165 
1166 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1167 
1168 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1169 
1170 #ifndef __ASSEMBLY__
1171 
1182 {
1183  uint32_t ECC_RDataBUS : 32;
1184 };
1185 
1188 #endif /* __ASSEMBLY__ */
1189 
1191 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_RESET 0x00000000
1192 
1193 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA0BUS_OFST 0x44
1194 
1217 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1218 
1219 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 2
1220 
1221 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 3
1222 
1223 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0x00000007
1224 
1225 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0xfffffff8
1226 
1227 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1228 
1229 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1230 
1231 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0x00000007)
1232 
1233 #ifndef __ASSEMBLY__
1234 
1245 {
1246  uint32_t ECC_RDataBUS : 3;
1247  uint32_t : 29;
1248 };
1249 
1252 #endif /* __ASSEMBLY__ */
1253 
1255 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_RESET 0x00000000
1256 
1257 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA1BUS_OFST 0x48
1258 
1280 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1281 
1282 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1283 
1284 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1285 
1286 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1287 
1288 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1289 
1290 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1291 
1292 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1293 
1294 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1295 
1296 #ifndef __ASSEMBLY__
1297 
1308 {
1309  uint32_t ECC_RDataBUS : 32;
1310 };
1311 
1314 #endif /* __ASSEMBLY__ */
1315 
1317 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_RESET 0x00000000
1318 
1319 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA2BUS_OFST 0x4c
1320 
1342 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1343 
1344 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1345 
1346 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1347 
1348 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1349 
1350 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1351 
1352 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1353 
1354 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1355 
1356 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1357 
1358 #ifndef __ASSEMBLY__
1359 
1370 {
1371  uint32_t ECC_RDataBUS : 32;
1372 };
1373 
1376 #endif /* __ASSEMBLY__ */
1377 
1379 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_RESET 0x00000000
1380 
1381 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATA3BUS_OFST 0x50
1382 
1404 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1405 
1406 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1407 
1408 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1409 
1410 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1411 
1412 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1413 
1414 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1415 
1416 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1417 
1418 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1419 
1420 #ifndef __ASSEMBLY__
1421 
1432 {
1433  uint32_t ECC_WDataBUS : 32;
1434 };
1435 
1438 #endif /* __ASSEMBLY__ */
1439 
1441 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_RESET 0x00000000
1442 
1443 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA0BUS_OFST 0x54
1444 
1467 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1468 
1469 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 2
1470 
1471 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 3
1472 
1473 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0x00000007
1474 
1475 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0xfffffff8
1476 
1477 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1478 
1479 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1480 
1481 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0x00000007)
1482 
1483 #ifndef __ASSEMBLY__
1484 
1495 {
1496  uint32_t ECC_WDataBUS : 3;
1497  uint32_t : 29;
1498 };
1499 
1502 #endif /* __ASSEMBLY__ */
1503 
1505 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_RESET 0x00000000
1506 
1507 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA1BUS_OFST 0x58
1508 
1530 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1531 
1532 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1533 
1534 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1535 
1536 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1537 
1538 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1539 
1540 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1541 
1542 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1543 
1544 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1545 
1546 #ifndef __ASSEMBLY__
1547 
1558 {
1559  uint32_t ECC_WDataBUS : 32;
1560 };
1561 
1564 #endif /* __ASSEMBLY__ */
1565 
1567 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_RESET 0x00000000
1568 
1569 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA2BUS_OFST 0x5c
1570 
1592 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1593 
1594 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1595 
1596 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1597 
1598 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1599 
1600 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1601 
1602 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1603 
1604 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1605 
1606 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1607 
1608 #ifndef __ASSEMBLY__
1609 
1620 {
1621  uint32_t ECC_WDataBUS : 32;
1622 };
1623 
1626 #endif /* __ASSEMBLY__ */
1627 
1629 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_RESET 0x00000000
1630 
1631 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATA3BUS_OFST 0x60
1632 
1662 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1663 
1664 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1665 
1666 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1667 
1668 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1669 
1670 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1671 
1672 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1673 
1674 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1675 
1676 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1677 
1687 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1688 
1689 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1690 
1691 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1692 
1693 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1694 
1695 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1696 
1697 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1698 
1699 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1700 
1701 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1702 
1712 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1713 
1714 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1715 
1716 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1717 
1718 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1719 
1720 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1721 
1722 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1723 
1724 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1725 
1726 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1727 
1737 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1738 
1739 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1740 
1741 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1742 
1743 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1744 
1745 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1746 
1747 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1748 
1749 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1750 
1751 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1752 
1753 #ifndef __ASSEMBLY__
1754 
1765 {
1766  uint32_t ECC_RDataecc0BUS : 7;
1767  uint32_t : 1;
1768  uint32_t ECC_RDataecc1BUS : 7;
1769  uint32_t : 1;
1770  uint32_t ECC_RDataecc2BUS : 7;
1771  uint32_t : 1;
1772  uint32_t ECC_RDataecc3BUS : 7;
1773  uint32_t : 1;
1774 };
1775 
1778 #endif /* __ASSEMBLY__ */
1779 
1781 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1782 
1783 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC0BUS_OFST 0x64
1784 
1814 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1815 
1816 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1817 
1818 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1819 
1820 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1821 
1822 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1823 
1824 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1825 
1826 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1827 
1828 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1829 
1839 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1840 
1841 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1842 
1843 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1844 
1845 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1846 
1847 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1848 
1849 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1850 
1851 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1852 
1853 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1854 
1864 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1865 
1866 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1867 
1868 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1869 
1870 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1871 
1872 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1873 
1874 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1875 
1876 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1877 
1878 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1879 
1889 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1890 
1891 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1892 
1893 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1894 
1895 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1896 
1897 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1898 
1899 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1900 
1901 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1902 
1903 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1904 
1905 #ifndef __ASSEMBLY__
1906 
1917 {
1918  uint32_t ECC_RDataecc4BUS : 7;
1919  uint32_t : 1;
1920  uint32_t ECC_RDataecc5BUS : 7;
1921  uint32_t : 1;
1922  uint32_t ECC_RDataecc6BUS : 7;
1923  uint32_t : 1;
1924  uint32_t ECC_RDataecc7BUS : 7;
1925  uint32_t : 1;
1926 };
1927 
1930 #endif /* __ASSEMBLY__ */
1931 
1933 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1934 
1935 #define ALT_ECC_EMAC1_RX_ECC_ECC_RDATAECC1BUS_OFST 0x68
1936 
1966 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1967 
1968 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1969 
1970 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1971 
1972 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1973 
1974 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1975 
1976 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1977 
1978 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1979 
1980 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1981 
1991 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
1992 
1993 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
1994 
1995 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
1996 
1997 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
1998 
1999 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2000 
2001 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2002 
2003 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2004 
2005 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2006 
2016 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2017 
2018 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2019 
2020 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2021 
2022 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2023 
2024 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2025 
2026 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2027 
2028 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2029 
2030 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2031 
2041 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2042 
2043 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2044 
2045 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2046 
2047 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2048 
2049 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2050 
2051 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2052 
2053 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2054 
2055 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2056 
2057 #ifndef __ASSEMBLY__
2058 
2069 {
2070  uint32_t ECC_WDataecc0BUS : 7;
2071  uint32_t : 1;
2072  uint32_t ECC_WDataecc1BUS : 7;
2073  uint32_t : 1;
2074  uint32_t ECC_WDataecc2BUS : 7;
2075  uint32_t : 1;
2076  uint32_t ECC_WDataecc3BUS : 7;
2077  uint32_t : 1;
2078 };
2079 
2082 #endif /* __ASSEMBLY__ */
2083 
2085 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2086 
2087 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2088 
2118 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2119 
2120 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2121 
2122 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2123 
2124 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2125 
2126 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2127 
2128 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2129 
2130 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2131 
2132 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2133 
2143 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2144 
2145 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2146 
2147 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2148 
2149 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2150 
2151 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2152 
2153 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2154 
2155 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2156 
2157 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2158 
2168 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2169 
2170 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2171 
2172 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2173 
2174 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2175 
2176 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2177 
2178 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2179 
2180 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2181 
2182 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2183 
2193 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2194 
2195 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2196 
2197 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2198 
2199 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2200 
2201 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2202 
2203 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2204 
2205 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2206 
2207 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2208 
2209 #ifndef __ASSEMBLY__
2210 
2221 {
2222  uint32_t ECC_WDataecc4BUS : 7;
2223  uint32_t : 1;
2224  uint32_t ECC_WDataecc5BUS : 7;
2225  uint32_t : 1;
2226  uint32_t ECC_WDataecc6BUS : 7;
2227  uint32_t : 1;
2228  uint32_t ECC_WDataecc7BUS : 7;
2229  uint32_t : 1;
2230 };
2231 
2234 #endif /* __ASSEMBLY__ */
2235 
2237 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2238 
2239 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDATAECC1BUS_OFST 0x70
2240 
2263 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_LSB 0
2264 
2265 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_MSB 0
2266 
2267 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_WIDTH 1
2268 
2269 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x00000001
2270 
2271 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2272 
2273 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2274 
2275 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2276 
2277 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2278 
2279 #ifndef __ASSEMBLY__
2280 
2291 {
2292  uint32_t DBEN : 1;
2293  uint32_t : 31;
2294 };
2295 
2298 #endif /* __ASSEMBLY__ */
2299 
2301 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_RESET 0x00000000
2302 
2303 #define ALT_ECC_EMAC1_RX_ECC_ECC_DBYTECTL_OFST 0x74
2304 
2335 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2336 
2337 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2338 
2339 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2340 
2341 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2342 
2343 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2344 
2345 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2346 
2347 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2348 
2349 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2350 
2360 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2361 
2362 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2363 
2364 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2365 
2366 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2367 
2368 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2369 
2370 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2371 
2372 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2373 
2374 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2375 
2385 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_LSB 8
2386 
2387 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_MSB 8
2388 
2389 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2390 
2391 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2392 
2393 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2394 
2395 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2396 
2397 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2398 
2399 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2400 
2401 #ifndef __ASSEMBLY__
2402 
2413 {
2414  uint32_t DATAOVR : 1;
2415  uint32_t ECCOVR : 1;
2416  uint32_t : 6;
2417  uint32_t RDWR : 1;
2418  uint32_t : 23;
2419 };
2420 
2423 #endif /* __ASSEMBLY__ */
2424 
2426 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_RESET 0x00000000
2427 
2428 #define ALT_ECC_EMAC1_RX_ECC_ECC_ACCCTL_OFST 0x78
2429 
2453 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_LSB 16
2454 
2455 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_MSB 16
2456 
2457 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2458 
2459 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2460 
2461 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2462 
2463 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2464 
2465 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2466 
2467 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2468 
2469 #ifndef __ASSEMBLY__
2470 
2481 {
2482  uint32_t : 16;
2483  uint32_t ENBUSA : 1;
2484  uint32_t : 15;
2485 };
2486 
2489 #endif /* __ASSEMBLY__ */
2490 
2492 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_RESET 0x00000000
2493 
2494 #define ALT_ECC_EMAC1_RX_ECC_ECC_STARTACC_OFST 0x7c
2495 
2518 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2519 
2520 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2521 
2522 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2523 
2524 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2525 
2526 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2527 
2528 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2529 
2530 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2531 
2532 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2533 
2534 #ifndef __ASSEMBLY__
2535 
2546 {
2547  uint32_t WDEN_RAM : 1;
2548  uint32_t : 31;
2549 };
2550 
2553 #endif /* __ASSEMBLY__ */
2554 
2556 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_RESET 0x00000000
2557 
2558 #define ALT_ECC_EMAC1_RX_ECC_ECC_WDCTL_OFST 0x80
2559 
2587 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_LSB 0
2588 
2589 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_MSB 11
2590 
2591 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_WIDTH 12
2592 
2593 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_SET_MSK 0x00000fff
2594 
2595 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xfffff000
2596 
2597 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_RESET 0x0
2598 
2599 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x00000fff) >> 0)
2600 
2601 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x00000fff)
2602 
2613 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_LSB 31
2614 
2615 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_MSB 31
2616 
2617 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_WIDTH 1
2618 
2619 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2620 
2621 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2622 
2623 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_RESET 0x0
2624 
2625 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2626 
2627 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2628 
2629 #ifndef __ASSEMBLY__
2630 
2641 {
2642  const uint32_t Address : 12;
2643  uint32_t : 19;
2644  uint32_t VALID : 1;
2645 };
2646 
2649 #endif /* __ASSEMBLY__ */
2650 
2652 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_RESET 0x00000000
2653 
2654 #define ALT_ECC_EMAC1_RX_ECC_SERRLKUPA0_OFST 0x90
2655 
2656 #ifndef __ASSEMBLY__
2657 
2668 {
2670  volatile uint32_t _pad_0x4_0x7;
2682  volatile uint32_t _pad_0x34_0x3b[2];
2701  volatile uint32_t _pad_0x84_0x8f[3];
2703  volatile uint32_t _pad_0x94_0x400[219];
2704 };
2705 
2710 {
2711  volatile uint32_t IP_REV_ID;
2712  volatile uint32_t _pad_0x4_0x7;
2713  volatile uint32_t CTRL;
2714  volatile uint32_t INITSTAT;
2715  volatile uint32_t ERRINTEN;
2716  volatile uint32_t ERRINTENS;
2717  volatile uint32_t ERRINTENR;
2718  volatile uint32_t INTMODE;
2719  volatile uint32_t INTSTAT;
2720  volatile uint32_t INTTEST;
2721  volatile uint32_t MODSTAT;
2722  volatile uint32_t DERRADDRA;
2723  volatile uint32_t SERRADDRA;
2724  volatile uint32_t _pad_0x34_0x3b[2];
2725  volatile uint32_t SERRCNTREG;
2726  volatile uint32_t ECC_Addrbus;
2727  volatile uint32_t ECC_RData0bus;
2728  volatile uint32_t ECC_RData1bus;
2729  volatile uint32_t ECC_RData2bus;
2730  volatile uint32_t ECC_RData3bus;
2731  volatile uint32_t ECC_WData0bus;
2732  volatile uint32_t ECC_WData1bus;
2733  volatile uint32_t ECC_WData2bus;
2734  volatile uint32_t ECC_WData3bus;
2735  volatile uint32_t ECC_RDataecc0bus;
2736  volatile uint32_t ECC_RDataecc1bus;
2737  volatile uint32_t ECC_WDataecc0bus;
2738  volatile uint32_t ECC_WDataecc1bus;
2739  volatile uint32_t ECC_dbytectrl;
2740  volatile uint32_t ECC_accctrl;
2741  volatile uint32_t ECC_startacc;
2742  volatile uint32_t ECC_wdctrl;
2743  volatile uint32_t _pad_0x84_0x8f[3];
2744  volatile uint32_t SERRLKUPA0;
2745  volatile uint32_t _pad_0x94_0x400[219];
2746 };
2747 
2750 #endif /* __ASSEMBLY__ */
2751 
2753 #ifdef __cplusplus
2754 }
2755 #endif /* __cplusplus */
2756 #endif /* __ALT_SOCAL_ECC_EMAC1_RX_ECC_H__ */
2757