Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : GPIO Divide Register - gpiodiv

Description

Contains a field that controls the clock divider for the GPIO De-bounce clock.

Only reset by a cold reset.

Register Layout

Bits Access Reset Description
[23:0] RW 0x1 GPIO De-bounce Clock Divider
[31:24] ??? 0x0 UNDEFINED

Field : GPIO De-bounce Clock Divider - gpiodbclk

The gpio_db_clk is divided down from the periph_base_clk by the value plus one specified in this field. The value 0 (divide by 1) is illegal. A value of 1 indicates divide by 2, 2 divide by 3, etc.

Field Access Macros:

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB   0
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB   23
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH   24
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK   0x00ffffff
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK   0xff000000
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET   0x1
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET(value)   (((value) & 0x00ffffff) >> 0)
 
#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET(value)   (((value) << 0) & 0x00ffffff)
 

Data Structures

struct  ALT_CLKMGR_PERPLL_GPIODIV_s
 

Macros

#define ALT_CLKMGR_PERPLL_GPIODIV_OFST   0x28
 

Typedefs

typedef struct
ALT_CLKMGR_PERPLL_GPIODIV_s 
ALT_CLKMGR_PERPLL_GPIODIV_t
 

Data Structure Documentation

struct ALT_CLKMGR_PERPLL_GPIODIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_PERPLL_GPIODIV.

Data Fields
uint32_t gpiodbclk: 24 GPIO De-bounce Clock Divider
uint32_t __pad0__: 8 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_MSB   23

The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_WIDTH   24

The width in bits of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET_MSK   0x00ffffff

The mask used to set the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_CLR_MSK   0xff000000

The mask used to clear the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_RESET   0x1

The reset value of the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_GET (   value)    (((value) & 0x00ffffff) >> 0)

Extracts the ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK field value from a register.

#define ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK_SET (   value)    (((value) << 0) & 0x00ffffff)

Produces a ALT_CLKMGR_PERPLL_GPIODIV_GPIODBCLK register field value suitable for setting the register.

#define ALT_CLKMGR_PERPLL_GPIODIV_OFST   0x28

The byte offset of the ALT_CLKMGR_PERPLL_GPIODIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_PERPLL_GPIODIV.