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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The MMC Control register establishes the operating mode of the management counters.
Note:
The bit 0 (Counters Reset) has higher priority than bit 4 (Counter Preset). Therefore, when the Software tries to set both bits in the same write cycle, all counters are cleared and the bit 4 is not set.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Counters Reset |
[1] | RW | 0x0 | Counters Stop Rollover |
[2] | RW | 0x0 | Reset on Read |
[3] | RW | 0x0 | MMC Counter Freeze |
[4] | RW | 0x0 | Counters Preset |
[5] | RW | 0x0 | Full-Half Preset |
[7:6] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | Update MMC Counters for Dropped Broadcast Frames |
[31:9] | ??? | 0x0 | UNDEFINED |
Field : Counters Reset - cntrst | ||||||||||
When this bit is set, all counters are reset. This bit is cleared automatically after one clock cycle. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB 0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB 0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK 0x00000001 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : Counters Stop Rollover - cntstopro | ||||||||||
When this bit is set, after reaching maximum value, the counter does not roll over to zero. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK 0x00000002 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Reset on Read - rstonrd | ||||||||||
When this bit is set, the MMC counters are reset to zero after Read (self- clearing after reset). The counters are cleared when the least significant byte lane (bits[7:0]) is read. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB 2 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB 2 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK 0x00000004 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : MMC Counter Freeze - cntfreez | ||||||||||
When this bit is set, it freezes all MMC counters to their current value. Until this bit is reset to 0, no MMC counter is updated because of any transmitted or received frame. If any MMC counter is read with the Reset on Read bit set, then that counter is also cleared in this mode. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB 3 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB 3 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK 0x00000008 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Counters Preset - cntprst | ||||||||||
When this bit is set, all counters are initialized or preset to almost full or almost half according to bit 5. This bit is cleared automatically after 1 clock cycle. This bit, along with bit 5, is useful for debugging and testing the assertion of interrupts because of MMC counter becoming half-full or full. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB 4 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB 4 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK 0x00000010 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK 0xffffffef | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : Full-Half Preset - cntprstlvl | ||||||||||
When low and bit 4 is set, all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (half - 2KBytes) and all frame-counters gets preset to 0x7FFF_FFF0 (half - 16). When this bit is high and bit 4 is set, all MMC counters get preset to almost- full value. All octet counters get preset to 0xFFFF_F800 (full - 2KBytes) and all frame-counters gets preset to 0xFFFF_FFF0 (full - 16). For 16-bit counters, the almost-half preset values are 0x7800 and 0x7FF0 for the respective octet and frame counters. Similarly, the almost-full preset values for the 16-bit counters are 0xF800 and 0xFFF0. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL 0x1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB 5 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB 5 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH 1 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK 0x00000020 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET 0x0 | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : Update MMC Counters for Dropped Broadcast Frames - ucdbc | |
When set, this bit enables MAC to update all the related MMC Counters for Broadcast frames dropped due to setting of DBF bit (Disable Broadcast Frames) of MAC Filter Register at offset 0x0004. When reset, MMC Counters are not updated for dropped Broadcast frames. Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB 8 |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB 8 |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK 0x00000100 |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK 0xfffffeff |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET(value) (((value) << 8) & 0x00000100) |
Data Structures | |
struct | ALT_EMAC_GMAC_MMC_CTL_s |
Macros | |
#define | ALT_EMAC_GMAC_MMC_CTL_OFST 0x100 |
#define | ALT_EMAC_GMAC_MMC_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_MMC_CTL_s | ALT_EMAC_GMAC_MMC_CTL_t |
struct ALT_EMAC_GMAC_MMC_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_MMC_CTL.
Data Fields | ||
---|---|---|
uint32_t | cntrst: 1 | Counters Reset |
uint32_t | cntstopro: 1 | Counters Stop Rollover |
uint32_t | rstonrd: 1 | Reset on Read |
uint32_t | cntfreez: 1 | MMC Counter Freeze |
uint32_t | cntprst: 1 | Counters Preset |
uint32_t | cntprstlvl: 1 | Full-Half Preset |
uint32_t | __pad0__: 2 | UNDEFINED |
uint32_t | ucdbc: 1 | Update MMC Counters for Dropped Broadcast Frames |
uint32_t | __pad1__: 23 | UNDEFINED |
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
Auto cleared after 1 clock cycle
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTRST
All Counters Reset
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTRST field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTRST_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_MMC_CTL_CNTRST register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
Counter Roll Over
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO
Counter does not Roll Over
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_MMC_CTL_CNTSTOPRO register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
No reset after read
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_RSTONRD
Reset after read
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_RSTONRD field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_RSTONRD_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_MMC_CTL_RSTONRD register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
Update MMC Counters
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ
Freeze MMC counters to current value
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_MMC_CTL_CNTFREEZ register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
Counters not preset
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRST
Counters preset to full or almost full
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRST field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRST_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRST register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTHALF 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
Preset All Counters to almost-half
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_E_ALMOSTFULL 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL
Present All Counters almost-full
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_MMC_CTL_CNTPRSTLVL register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_CTL_UCDBC register field.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_MMC_CTL_UCDBC field value from a register.
#define ALT_EMAC_GMAC_MMC_CTL_UCDBC_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_MMC_CTL_UCDBC register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_CTL_OFST 0x100 |
The byte offset of the ALT_EMAC_GMAC_MMC_CTL register from the beginning of the component.
#define ALT_EMAC_GMAC_MMC_CTL_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_CTL_OFST)) |
The address of the ALT_EMAC_GMAC_MMC_CTL register.
typedef struct ALT_EMAC_GMAC_MMC_CTL_s ALT_EMAC_GMAC_MMC_CTL_t |
The typedef declaration for register ALT_EMAC_GMAC_MMC_CTL.