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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Name: I2C Control Register
Size: 10 bits
Address Offset: 0x00
Read/Write Access:
If configuration parameter I2C_DYNAMIC_TAR_UPDATE = 0,
all bits are Read/Write.
If I2C_DYNAMIC_TAR_UPDATE = 1, bit 4 is Read-only.
This register can be written only when the DW_apb_i2c
is disabled, which corresponds to the IC_ENABLE[0] register
being set to 0. Writes at other times have no effect.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | ALT_I2C_CON_MST_MOD |
[2:1] | RW | 0x2 | ALT_I2C_CON_SPEED |
[3] | RW | 0x1 | ALT_I2C_CON_IC_10BITADDR_SLV |
[4] | R | 0x1 | ALT_I2C_CON_IC_10BITADDR_MST |
[5] | RW | 0x1 | ALT_I2C_CON_IC_RESTART_EN |
[6] | RW | 0x1 | ALT_I2C_CON_IC_SLV_DIS |
[7] | RW | 0x0 | ALT_I2C_CON_STOP_DET_IFADDRED |
[8] | RW | 0x0 | ALT_I2C_CON_TX_EMPTY_CTL |
[9] | RW | 0x0 | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL |
[31:10] | R | 0x0 | ALT_I2C_CON_RSVD_IC_CON_31TO10 |
Field : master_mode | ||||||||||
This bit controls whether the DW_apb_i2c master is enabled. 0: master disabled 1: master enabled Reset value: IC_MASTER_MODE configuration parameter NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_MST_MOD_E_DIS 0x0 | |||||||||
#define | ALT_I2C_CON_MST_MOD_E_EN 0x1 | |||||||||
#define | ALT_I2C_CON_MST_MOD_LSB 0 | |||||||||
#define | ALT_I2C_CON_MST_MOD_MSB 0 | |||||||||
#define | ALT_I2C_CON_MST_MOD_WIDTH 1 | |||||||||
#define | ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 | |||||||||
#define | ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_I2C_CON_MST_MOD_RESET 0x1 | |||||||||
#define | ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : speed | ||||||||||
These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE. 1: standard mode (100 kbit/s) 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s) 3: high speed mode (3.4 Mbit/s) Reset value: IC_MAX_SPEED_MODE configuration Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_SPEED_E_STANDARD 0x1 | |||||||||
#define | ALT_I2C_CON_SPEED_E_FAST 0x2 | |||||||||
#define | ALT_I2C_CON_SPEED_LSB 1 | |||||||||
#define | ALT_I2C_CON_SPEED_MSB 2 | |||||||||
#define | ALT_I2C_CON_SPEED_WIDTH 2 | |||||||||
#define | ALT_I2C_CON_SPEED_SET_MSK 0x00000006 | |||||||||
#define | ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 | |||||||||
#define | ALT_I2C_CON_SPEED_RESET 0x2 | |||||||||
#define | ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1) | |||||||||
#define | ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006) | |||||||||
Field : ic_10bitaddr_slave | ||||||||||
When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register. Reset value: IC_10BITADDR_SLAVE configuration parameter Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : ic_10bitaddr_master | ||||||||||
If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to 'No' (0), this bit is named IC_10BITADDR_MASTER and controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. If I2C_DYNAMIC_TAR_UPDATE is set to 'Yes' (1), the function of this bit is handled by bit 12 of IC_TAR register, and becomes a read-only copy called IC_10BITADDR_MASTER_rd_only. 0: 7-bit addressing 1: 10-bit addressing Dependencies: If I2C_DYNAMIC_TAR_UPDATE = 1, then this bit is read-only. If I2C_DYNAMIC_TAR_UPDATE = 0, then this bit can be read or write. Reset value: IC_10BITADDR_MASTER configuration parameter Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : ic_restart_en | ||||||||||
Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. 0: disable 1: enable When RESTART is disabled, the master is prohibited from performing the following functions:
By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. Reset value: IC_RESTART_EN configuration parameter Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_LSB 5 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_MSB 5 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : ic_slave_disable | ||||||||||
This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit takes on the value of the configuration parameter IC_SLAVE_DISABLE. You have the choice of having the slave enabled or disabled after reset is applied, which means software does not have to configure the slave. By default, the slave is always enabled (in reset state as well). If you need to disable it after reset, set this bit to 1. If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave. 0: slave is enabled 1: slave is disabled Reset value: IC_SLAVE_DISABLE configuration parameter NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_LSB 6 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_MSB 6 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : stop_det_ifaddressed | |
In slave mode: 1: issues the STOP_DET interrrupt only when it is addressed. 0: issues the STOP_DET irrespective of whether it’s addressed or not. Dependencies: This register bit value is applicable in the slave mode only (MASTER_MODE = 1’b0) Reset value: 0x0 NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). Field Access Macros: | |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_LSB 7 |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_MSB 7 |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_WIDTH 1 |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_SET_MSK 0x00000080 |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_CLR_MSK 0xffffff7f |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_RESET 0x0 |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_I2C_CON_STOP_DET_IFADDRED_SET(value) (((value) << 7) & 0x00000080) |
Field : tx_empty_ctrl | |
This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. Field Access Macros: | |
#define | ALT_I2C_CON_TX_EMPTY_CTL_LSB 8 |
#define | ALT_I2C_CON_TX_EMPTY_CTL_MSB 8 |
#define | ALT_I2C_CON_TX_EMPTY_CTL_WIDTH 1 |
#define | ALT_I2C_CON_TX_EMPTY_CTL_SET_MSK 0x00000100 |
#define | ALT_I2C_CON_TX_EMPTY_CTL_CLR_MSK 0xfffffeff |
#define | ALT_I2C_CON_TX_EMPTY_CTL_RESET 0x0 |
#define | ALT_I2C_CON_TX_EMPTY_CTL_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_I2C_CON_TX_EMPTY_CTL_SET(value) (((value) << 8) & 0x00000100) |
Field : rx_fifo_full_hld_ctrl | |
This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter. Dependencies: This register bit value is applicable only when the IC_RX_FULL_HLD_BUS_EN configuration parameter is set to 1. If IC_RX_FULL_HLD_BUS_EN = 0, then this bit is read-only. If IC_RX_FULL_HLD_BUS_EN = 1, then this bit can be read or write. Reset value: 0x0. Field Access Macros: | |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_LSB 9 |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_MSB 9 |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_WIDTH 1 |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET_MSK 0x00000200 |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_CLR_MSK 0xfffffdff |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_RESET 0x0 |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET(value) (((value) << 9) & 0x00000200) |
Field : rsvd_ic_con_31to10 | |
Reserved bits [31:1] - Read Only Field Access Macros: | |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_LSB 10 |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_MSB 31 |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_WIDTH 22 |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_SET_MSK 0xfffffc00 |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_CLR_MSK 0x000003ff |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_RESET 0x0 |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_GET(value) (((value) & 0xfffffc00) >> 10) |
#define | ALT_I2C_CON_RSVD_IC_CON_31TO10_SET(value) (((value) << 10) & 0xfffffc00) |
Data Structures | |
struct | ALT_I2C_CON_s |
Macros | |
#define | ALT_I2C_CON_RESET 0x0000007d |
#define | ALT_I2C_CON_OFST 0x0 |
#define | ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) |
Typedefs | |
typedef struct ALT_I2C_CON_s | ALT_I2C_CON_t |
struct ALT_I2C_CON_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_CON.
Data Fields | ||
---|---|---|
uint32_t | master_mode: 1 | ALT_I2C_CON_MST_MOD |
uint32_t | speed: 2 | ALT_I2C_CON_SPEED |
uint32_t | ic_10bitaddr_slave: 1 | ALT_I2C_CON_IC_10BITADDR_SLV |
const uint32_t | ic_10bitaddr_master: 1 | ALT_I2C_CON_IC_10BITADDR_MST |
uint32_t | ic_restart_en: 1 | ALT_I2C_CON_IC_RESTART_EN |
uint32_t | ic_slave_disable: 1 | ALT_I2C_CON_IC_SLV_DIS |
uint32_t | stop_det_ifaddressed: 1 | ALT_I2C_CON_STOP_DET_IFADDRED |
uint32_t | tx_empty_ctrl: 1 | ALT_I2C_CON_TX_EMPTY_CTL |
uint32_t | rx_fifo_full_hld_ctrl: 1 | ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL |
const uint32_t | rsvd_ic_con_31to10: 22 | ALT_I2C_CON_RSVD_IC_CON_31TO10 |
#define ALT_I2C_CON_MST_MOD_E_DIS 0x0 |
Enumerated value for register field ALT_I2C_CON_MST_MOD
master disabled
#define ALT_I2C_CON_MST_MOD_E_EN 0x1 |
Enumerated value for register field ALT_I2C_CON_MST_MOD
master enabled
#define ALT_I2C_CON_MST_MOD_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_MST_MOD register field.
#define ALT_I2C_CON_MST_MOD_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_MST_MOD register field.
#define ALT_I2C_CON_MST_MOD_WIDTH 1 |
The width in bits of the ALT_I2C_CON_MST_MOD register field.
#define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001 |
The mask used to set the ALT_I2C_CON_MST_MOD register field value.
#define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_I2C_CON_MST_MOD register field value.
#define ALT_I2C_CON_MST_MOD_RESET 0x1 |
The reset value of the ALT_I2C_CON_MST_MOD register field.
#define ALT_I2C_CON_MST_MOD_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_I2C_CON_MST_MOD field value from a register.
#define ALT_I2C_CON_MST_MOD_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_I2C_CON_MST_MOD register field value suitable for setting the register.
#define ALT_I2C_CON_SPEED_E_STANDARD 0x1 |
Enumerated value for register field ALT_I2C_CON_SPEED
standard mode (100 kbit/s)
#define ALT_I2C_CON_SPEED_E_FAST 0x2 |
Enumerated value for register field ALT_I2C_CON_SPEED
fast mode (400 kbit/s)
#define ALT_I2C_CON_SPEED_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_SPEED register field.
#define ALT_I2C_CON_SPEED_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_SPEED register field.
#define ALT_I2C_CON_SPEED_WIDTH 2 |
The width in bits of the ALT_I2C_CON_SPEED register field.
#define ALT_I2C_CON_SPEED_SET_MSK 0x00000006 |
The mask used to set the ALT_I2C_CON_SPEED register field value.
#define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9 |
The mask used to clear the ALT_I2C_CON_SPEED register field value.
#define ALT_I2C_CON_SPEED_RESET 0x2 |
The reset value of the ALT_I2C_CON_SPEED register field.
#define ALT_I2C_CON_SPEED_GET | ( | value | ) | (((value) & 0x00000006) >> 1) |
Extracts the ALT_I2C_CON_SPEED field value from a register.
#define ALT_I2C_CON_SPEED_SET | ( | value | ) | (((value) << 1) & 0x00000006) |
Produces a ALT_I2C_CON_SPEED register field value suitable for setting the register.
#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0 |
Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
7-bit addressing
#define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1 |
Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_SLV
10-bit addressing
#define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field.
#define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_SLV register field.
#define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1 |
The width in bits of the ALT_I2C_CON_IC_10BITADDR_SLV register field.
#define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008 |
The mask used to set the ALT_I2C_CON_IC_10BITADDR_SLV register field value.
#define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_I2C_CON_IC_10BITADDR_SLV register field value.
#define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1 |
The reset value of the ALT_I2C_CON_IC_10BITADDR_SLV register field.
#define ALT_I2C_CON_IC_10BITADDR_SLV_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_I2C_CON_IC_10BITADDR_SLV field value from a register.
#define ALT_I2C_CON_IC_10BITADDR_SLV_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_I2C_CON_IC_10BITADDR_SLV register field value suitable for setting the register.
#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0 |
Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
7-bit addressing
#define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1 |
Enumerated value for register field ALT_I2C_CON_IC_10BITADDR_MST
10-bit addressing
#define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field.
#define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_10BITADDR_MST register field.
#define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1 |
The width in bits of the ALT_I2C_CON_IC_10BITADDR_MST register field.
#define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010 |
The mask used to set the ALT_I2C_CON_IC_10BITADDR_MST register field value.
#define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef |
The mask used to clear the ALT_I2C_CON_IC_10BITADDR_MST register field value.
#define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1 |
The reset value of the ALT_I2C_CON_IC_10BITADDR_MST register field.
#define ALT_I2C_CON_IC_10BITADDR_MST_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_I2C_CON_IC_10BITADDR_MST field value from a register.
#define ALT_I2C_CON_IC_10BITADDR_MST_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_I2C_CON_IC_10BITADDR_MST register field value suitable for setting the register.
#define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0 |
Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
restart master disable
#define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1 |
Enumerated value for register field ALT_I2C_CON_IC_RESTART_EN
restart master enable
#define ALT_I2C_CON_IC_RESTART_EN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_RESTART_EN register field.
#define ALT_I2C_CON_IC_RESTART_EN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_RESTART_EN register field.
#define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1 |
The width in bits of the ALT_I2C_CON_IC_RESTART_EN register field.
#define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020 |
The mask used to set the ALT_I2C_CON_IC_RESTART_EN register field value.
#define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_I2C_CON_IC_RESTART_EN register field value.
#define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1 |
The reset value of the ALT_I2C_CON_IC_RESTART_EN register field.
#define ALT_I2C_CON_IC_RESTART_EN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_I2C_CON_IC_RESTART_EN field value from a register.
#define ALT_I2C_CON_IC_RESTART_EN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_I2C_CON_IC_RESTART_EN register field value suitable for setting the register.
#define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0 |
Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
slave enable
#define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1 |
Enumerated value for register field ALT_I2C_CON_IC_SLV_DIS
slave disable
#define ALT_I2C_CON_IC_SLV_DIS_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_IC_SLV_DIS register field.
#define ALT_I2C_CON_IC_SLV_DIS_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_IC_SLV_DIS register field.
#define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1 |
The width in bits of the ALT_I2C_CON_IC_SLV_DIS register field.
#define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040 |
The mask used to set the ALT_I2C_CON_IC_SLV_DIS register field value.
#define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_I2C_CON_IC_SLV_DIS register field value.
#define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1 |
The reset value of the ALT_I2C_CON_IC_SLV_DIS register field.
#define ALT_I2C_CON_IC_SLV_DIS_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_I2C_CON_IC_SLV_DIS field value from a register.
#define ALT_I2C_CON_IC_SLV_DIS_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_I2C_CON_IC_SLV_DIS register field value suitable for setting the register.
#define ALT_I2C_CON_STOP_DET_IFADDRED_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_STOP_DET_IFADDRED register field.
#define ALT_I2C_CON_STOP_DET_IFADDRED_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_STOP_DET_IFADDRED register field.
#define ALT_I2C_CON_STOP_DET_IFADDRED_WIDTH 1 |
The width in bits of the ALT_I2C_CON_STOP_DET_IFADDRED register field.
#define ALT_I2C_CON_STOP_DET_IFADDRED_SET_MSK 0x00000080 |
The mask used to set the ALT_I2C_CON_STOP_DET_IFADDRED register field value.
#define ALT_I2C_CON_STOP_DET_IFADDRED_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_I2C_CON_STOP_DET_IFADDRED register field value.
#define ALT_I2C_CON_STOP_DET_IFADDRED_RESET 0x0 |
The reset value of the ALT_I2C_CON_STOP_DET_IFADDRED register field.
#define ALT_I2C_CON_STOP_DET_IFADDRED_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_I2C_CON_STOP_DET_IFADDRED field value from a register.
#define ALT_I2C_CON_STOP_DET_IFADDRED_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_I2C_CON_STOP_DET_IFADDRED register field value suitable for setting the register.
#define ALT_I2C_CON_TX_EMPTY_CTL_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_TX_EMPTY_CTL register field.
#define ALT_I2C_CON_TX_EMPTY_CTL_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_TX_EMPTY_CTL register field.
#define ALT_I2C_CON_TX_EMPTY_CTL_WIDTH 1 |
The width in bits of the ALT_I2C_CON_TX_EMPTY_CTL register field.
#define ALT_I2C_CON_TX_EMPTY_CTL_SET_MSK 0x00000100 |
The mask used to set the ALT_I2C_CON_TX_EMPTY_CTL register field value.
#define ALT_I2C_CON_TX_EMPTY_CTL_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_I2C_CON_TX_EMPTY_CTL register field value.
#define ALT_I2C_CON_TX_EMPTY_CTL_RESET 0x0 |
The reset value of the ALT_I2C_CON_TX_EMPTY_CTL register field.
#define ALT_I2C_CON_TX_EMPTY_CTL_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_I2C_CON_TX_EMPTY_CTL field value from a register.
#define ALT_I2C_CON_TX_EMPTY_CTL_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_I2C_CON_TX_EMPTY_CTL register field value suitable for setting the register.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_WIDTH 1 |
The width in bits of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET_MSK 0x00000200 |
The mask used to set the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_RESET 0x0 |
The reset value of the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL field value from a register.
#define ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_I2C_CON_RX_FIFO_FULL_HLD_CTL register field value suitable for setting the register.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_WIDTH 22 |
The width in bits of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET_MSK 0xfffffc00 |
The mask used to set the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_CLR_MSK 0x000003ff |
The mask used to clear the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_RESET 0x0 |
The reset value of the ALT_I2C_CON_RSVD_IC_CON_31TO10 register field.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_GET | ( | value | ) | (((value) & 0xfffffc00) >> 10) |
Extracts the ALT_I2C_CON_RSVD_IC_CON_31TO10 field value from a register.
#define ALT_I2C_CON_RSVD_IC_CON_31TO10_SET | ( | value | ) | (((value) << 10) & 0xfffffc00) |
Produces a ALT_I2C_CON_RSVD_IC_CON_31TO10 register field value suitable for setting the register.
#define ALT_I2C_CON_RESET 0x0000007d |
The reset value of the ALT_I2C_CON register.
#define ALT_I2C_CON_OFST 0x0 |
The byte offset of the ALT_I2C_CON register from the beginning of the component.
#define ALT_I2C_CON_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST)) |
The address of the ALT_I2C_CON register.
typedef struct ALT_I2C_CON_s ALT_I2C_CON_t |
The typedef declaration for register ALT_I2C_CON.