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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Enable diagnostics access
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON |
[1] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON |
[15:2] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON |
[31:17] | ??? | 0x0 | UNDEFINED |
Field : WRDIAGON | |
Write diagnostics mux enabled. This overrides the encoder output with the register data ecc. 1'b0: Write diagnostics path via the ecc_reg2wdatabus is disabled. 1'b1: Write diagnostics path via the ecc_reg2wdatabus is enabled. Both Rddiagon and Wrdiagon bits can be enabled. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_LSB 0 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_MSB 0 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET(value) (((value) << 0) & 0x00000001) |
Field : RDDIAGON | |
Read diagnostics mux enabled. This overrides the data entering the ECC decoder. 1'b0: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is disabled. 1'b1: Read diagnostics path via the ecc_rdata2regbus or ecc_reg2rdatabus is enabled. Both Rddiagon and Wrdiagon bits can be enabled. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_LSB 1 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_MSB 1 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET(value) (((value) << 1) & 0x00000002) |
Field : ECCDIAGON | |
ECC diagnostics mode. 1'b0: ECC diagnostics logic is disabled. ECC encoder bypass is disabled. 1'b1: ECC diagnostics logic is enabled. Direction of ECC data from the register to data bus or data bus to ecc register is determined by ECC_rddiagon or ECC_wrdiagon. Field Access Macros: | |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_LSB 16 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_MSB 16 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_WIDTH 1 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_RESET 0x0 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET(value) (((value) << 16) & 0x00010000) |
Data Structures | |
struct | ALT_ECC_HMC_OCP_ECC_DIAGON_s |
Macros | |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_RESET 0x00000000 |
#define | ALT_ECC_HMC_OCP_ECC_DIAGON_OFST 0x150 |
Typedefs | |
typedef struct ALT_ECC_HMC_OCP_ECC_DIAGON_s | ALT_ECC_HMC_OCP_ECC_DIAGON_t |
struct ALT_ECC_HMC_OCP_ECC_DIAGON_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_HMC_OCP_ECC_DIAGON.
Data Fields | ||
---|---|---|
uint32_t | WRDIAGON: 1 | ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON |
uint32_t | RDDIAGON: 1 | ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON |
uint32_t | __pad0__: 14 | UNDEFINED |
uint32_t | ECCDIAGON: 1 | ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON |
uint32_t | __pad1__: 15 | UNDEFINED |
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET_MSK 0x00000001 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON field value from a register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_WRDIAGON register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET_MSK 0x00000002 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON field value from a register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_RDDIAGON register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_WIDTH 1 |
The width in bits of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET_MSK 0x00010000 |
The mask used to set the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_RESET 0x0 |
The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON field value from a register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_ECC_HMC_OCP_ECC_DIAGON_ECCDIAGON register field value suitable for setting the register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_RESET 0x00000000 |
The reset value of the ALT_ECC_HMC_OCP_ECC_DIAGON register.
#define ALT_ECC_HMC_OCP_ECC_DIAGON_OFST 0x150 |
The byte offset of the ALT_ECC_HMC_OCP_ECC_DIAGON register from the beginning of the component.
typedef struct ALT_ECC_HMC_OCP_ECC_DIAGON_s ALT_ECC_HMC_OCP_ECC_DIAGON_t |
The typedef declaration for register ALT_ECC_HMC_OCP_ECC_DIAGON.