Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Interrupt Mask - irqmask

Description

If disabled, the interrupt for the corresponding interrupt status register bit is disabled. If enabled, the interrupt for the corresponding interrupt status register bit is enabled.

Register Layout

Bits Access Reset Description
[0] ??? 0x0 UNDEFINED
[1] RW 0x0 Underflow Detected Mask
[2] RW 0x0 Mask
[3] RW 0x0 Indirect Read Reject Mask
[4] RW 0x0 Protected Area Write Attempt Mask
[5] RW 0x0 Illegal Access Detected Mask
[6] RW 0x0 Transfer Watermark Breach Mask
[7] RW 0x0 Receive Overflow Mask
[8] RW 0x0 Transmit FIFO Threshold Compare Mask
[9] RW 0x0 Transmit FIFO Full Mask
[10] RW 0x0 Receive FIFO Threshold Compare Mask
[11] RW 0x0 Receive FIFO full Mask
[12] RW 0x0 Indirect Read Partition overflow mask
[31:13] ??? 0x0 UNDEFINED

Field : Underflow Detected Mask - underflowdet

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END   0x1
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB   1
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB   1
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH   1
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK   0x00000002
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK   0xfffffffd
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET   0x0
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Mask - indopdone

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_INDOPDONE_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_INDOPDONE_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_INDOPDONE_E_END   0x1
 
#define ALT_QSPI_IRQMSK_INDOPDONE_LSB   2
 
#define ALT_QSPI_IRQMSK_INDOPDONE_MSB   2
 
#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH   1
 
#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK   0x00000004
 
#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK   0xfffffffb
 
#define ALT_QSPI_IRQMSK_INDOPDONE_RESET   0x0
 
#define ALT_QSPI_IRQMSK_INDOPDONE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_QSPI_IRQMSK_INDOPDONE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Indirect Read Reject Mask - indrdreject

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_INDRDREJECT_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END   0x1
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB   3
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB   3
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH   1
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK   0x00000008
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK   0xfffffff7
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET   0x0
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_QSPI_IRQMSK_INDRDREJECT_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Protected Area Write Attempt Mask - protwrattempt

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END   0x1
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB   4
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB   4
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH   1
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK   0x00000010
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK   0xffffffef
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET   0x0
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Illegal Access Detected Mask - illegalacc

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_ILLEGALACC_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END   0x1
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB   5
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB   5
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH   1
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK   0x00000020
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK   0xffffffdf
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET   0x0
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_QSPI_IRQMSK_ILLEGALACC_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Transfer Watermark Breach Mask - indxfrlvl

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_INDXFRLVL_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END   0x1
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB   6
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB   6
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH   1
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK   0x00000040
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK   0xffffffbf
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET   0x0
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_QSPI_IRQMSK_INDXFRLVL_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Receive Overflow Mask - rxover

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_RXOVER_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_RXOVER_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_RXOVER_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_RXOVER_E_END   0x1
 
#define ALT_QSPI_IRQMSK_RXOVER_LSB   7
 
#define ALT_QSPI_IRQMSK_RXOVER_MSB   7
 
#define ALT_QSPI_IRQMSK_RXOVER_WIDTH   1
 
#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK   0x00000080
 
#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK   0xffffff7f
 
#define ALT_QSPI_IRQMSK_RXOVER_RESET   0x0
 
#define ALT_QSPI_IRQMSK_RXOVER_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_QSPI_IRQMSK_RXOVER_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Transmit FIFO Threshold Compare Mask - txthreshcmp

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END   0x1
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB   8
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB   8
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH   1
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK   0x00000100
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK   0xfffffeff
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET   0x0
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Transmit FIFO Full Mask - txfull

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_TXFULL_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_TXFULL_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_TXFULL_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_TXFULL_E_END   0x1
 
#define ALT_QSPI_IRQMSK_TXFULL_LSB   9
 
#define ALT_QSPI_IRQMSK_TXFULL_MSB   9
 
#define ALT_QSPI_IRQMSK_TXFULL_WIDTH   1
 
#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK   0x00000200
 
#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK   0xfffffdff
 
#define ALT_QSPI_IRQMSK_TXFULL_RESET   0x0
 
#define ALT_QSPI_IRQMSK_TXFULL_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_QSPI_IRQMSK_TXFULL_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Receive FIFO Threshold Compare Mask - rxthreshcmp

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END   0x1
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB   10
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB   10
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH   1
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK   0x00000400
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK   0xfffffbff
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET   0x0
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Receive FIFO full Mask - rxfull

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_RXFULL_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_RXFULL_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_RXFULL_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_RXFULL_E_END   0x1
 
#define ALT_QSPI_IRQMSK_RXFULL_LSB   11
 
#define ALT_QSPI_IRQMSK_RXFULL_MSB   11
 
#define ALT_QSPI_IRQMSK_RXFULL_WIDTH   1
 
#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK   0x00000800
 
#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK   0xfffff7ff
 
#define ALT_QSPI_IRQMSK_RXFULL_RESET   0x0
 
#define ALT_QSPI_IRQMSK_RXFULL_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_QSPI_IRQMSK_RXFULL_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Indirect Read Partition overflow mask - indsramfull

Field Enumeration Values:

Enum Value Description
ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD 0x0 Disable Interrupt by Masking
ALT_QSPI_IRQMSK_INDSRAMFULL_E_END 0x1 Enable Interrupt

Field Access Macros:

#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD   0x0
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END   0x1
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB   12
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB   12
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH   1
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK   0x00001000
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK   0xffffefff
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET   0x0
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET(value)   (((value) << 12) & 0x00001000)
 

Data Structures

struct  ALT_QSPI_IRQMSK_s
 

Macros

#define ALT_QSPI_IRQMSK_OFST   0x44
 

Typedefs

typedef struct ALT_QSPI_IRQMSK_s ALT_QSPI_IRQMSK_t
 

Data Structure Documentation

struct ALT_QSPI_IRQMSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_QSPI_IRQMSK.

Data Fields
uint32_t __pad0__: 1 UNDEFINED
uint32_t underflowdet: 1 Underflow Detected Mask
uint32_t indopdone: 1 Mask
uint32_t indrdreject: 1 Indirect Read Reject Mask
uint32_t protwrattempt: 1 Protected Area Write Attempt Mask
uint32_t illegalacc: 1 Illegal Access Detected Mask
uint32_t indxfrlvl: 1 Transfer Watermark Breach Mask
uint32_t rxover: 1 Receive Overflow Mask
uint32_t txthreshcmp: 1 Transmit FIFO Threshold Compare Mask
uint32_t txfull: 1 Transmit FIFO Full Mask
uint32_t rxthreshcmp: 1 Receive FIFO Threshold Compare Mask
uint32_t rxfull: 1 Receive FIFO full Mask
uint32_t indsramfull: 1 Indirect Read Partition overflow mask
uint32_t __pad1__: 19 UNDEFINED

Macro Definitions

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_UNDERFLOWDET

Enable Interrupt

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_LSB   1

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_MSB   1

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET_MSK   0x00000002

The mask used to set the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_CLR_MSK   0xfffffffd

The mask used to clear the ALT_QSPI_IRQMSK_UNDERFLOWDET register field value.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_UNDERFLOWDET register field.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_QSPI_IRQMSK_UNDERFLOWDET field value from a register.

#define ALT_QSPI_IRQMSK_UNDERFLOWDET_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_QSPI_IRQMSK_UNDERFLOWDET register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_INDOPDONE_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_INDOPDONE_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_INDOPDONE

Enable Interrupt

#define ALT_QSPI_IRQMSK_INDOPDONE_LSB   2

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field.

#define ALT_QSPI_IRQMSK_INDOPDONE_MSB   2

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDOPDONE register field.

#define ALT_QSPI_IRQMSK_INDOPDONE_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_INDOPDONE register field.

#define ALT_QSPI_IRQMSK_INDOPDONE_SET_MSK   0x00000004

The mask used to set the ALT_QSPI_IRQMSK_INDOPDONE register field value.

#define ALT_QSPI_IRQMSK_INDOPDONE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_QSPI_IRQMSK_INDOPDONE register field value.

#define ALT_QSPI_IRQMSK_INDOPDONE_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_INDOPDONE register field.

#define ALT_QSPI_IRQMSK_INDOPDONE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_QSPI_IRQMSK_INDOPDONE field value from a register.

#define ALT_QSPI_IRQMSK_INDOPDONE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_QSPI_IRQMSK_INDOPDONE register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_INDRDREJECT_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_INDRDREJECT_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_INDRDREJECT

Enable Interrupt

#define ALT_QSPI_IRQMSK_INDRDREJECT_LSB   3

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field.

#define ALT_QSPI_IRQMSK_INDRDREJECT_MSB   3

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDRDREJECT register field.

#define ALT_QSPI_IRQMSK_INDRDREJECT_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_INDRDREJECT register field.

#define ALT_QSPI_IRQMSK_INDRDREJECT_SET_MSK   0x00000008

The mask used to set the ALT_QSPI_IRQMSK_INDRDREJECT register field value.

#define ALT_QSPI_IRQMSK_INDRDREJECT_CLR_MSK   0xfffffff7

The mask used to clear the ALT_QSPI_IRQMSK_INDRDREJECT register field value.

#define ALT_QSPI_IRQMSK_INDRDREJECT_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_INDRDREJECT register field.

#define ALT_QSPI_IRQMSK_INDRDREJECT_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_QSPI_IRQMSK_INDRDREJECT field value from a register.

#define ALT_QSPI_IRQMSK_INDRDREJECT_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_QSPI_IRQMSK_INDRDREJECT register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_PROTWRATTEMPT

Enable Interrupt

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_LSB   4

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_MSB   4

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET_MSK   0x00000010

The mask used to set the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_CLR_MSK   0xffffffef

The mask used to clear the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_PROTWRATTEMPT register field.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_QSPI_IRQMSK_PROTWRATTEMPT field value from a register.

#define ALT_QSPI_IRQMSK_PROTWRATTEMPT_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_QSPI_IRQMSK_PROTWRATTEMPT register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_ILLEGALACC_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_ILLEGALACC_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_ILLEGALACC

Enable Interrupt

#define ALT_QSPI_IRQMSK_ILLEGALACC_LSB   5

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field.

#define ALT_QSPI_IRQMSK_ILLEGALACC_MSB   5

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_ILLEGALACC register field.

#define ALT_QSPI_IRQMSK_ILLEGALACC_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_ILLEGALACC register field.

#define ALT_QSPI_IRQMSK_ILLEGALACC_SET_MSK   0x00000020

The mask used to set the ALT_QSPI_IRQMSK_ILLEGALACC register field value.

#define ALT_QSPI_IRQMSK_ILLEGALACC_CLR_MSK   0xffffffdf

The mask used to clear the ALT_QSPI_IRQMSK_ILLEGALACC register field value.

#define ALT_QSPI_IRQMSK_ILLEGALACC_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_ILLEGALACC register field.

#define ALT_QSPI_IRQMSK_ILLEGALACC_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_QSPI_IRQMSK_ILLEGALACC field value from a register.

#define ALT_QSPI_IRQMSK_ILLEGALACC_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_QSPI_IRQMSK_ILLEGALACC register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_INDXFRLVL_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_INDXFRLVL_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_INDXFRLVL

Enable Interrupt

#define ALT_QSPI_IRQMSK_INDXFRLVL_LSB   6

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field.

#define ALT_QSPI_IRQMSK_INDXFRLVL_MSB   6

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDXFRLVL register field.

#define ALT_QSPI_IRQMSK_INDXFRLVL_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_INDXFRLVL register field.

#define ALT_QSPI_IRQMSK_INDXFRLVL_SET_MSK   0x00000040

The mask used to set the ALT_QSPI_IRQMSK_INDXFRLVL register field value.

#define ALT_QSPI_IRQMSK_INDXFRLVL_CLR_MSK   0xffffffbf

The mask used to clear the ALT_QSPI_IRQMSK_INDXFRLVL register field value.

#define ALT_QSPI_IRQMSK_INDXFRLVL_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_INDXFRLVL register field.

#define ALT_QSPI_IRQMSK_INDXFRLVL_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_QSPI_IRQMSK_INDXFRLVL field value from a register.

#define ALT_QSPI_IRQMSK_INDXFRLVL_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_QSPI_IRQMSK_INDXFRLVL register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_RXOVER_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_RXOVER_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_RXOVER

Enable Interrupt

#define ALT_QSPI_IRQMSK_RXOVER_LSB   7

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXOVER register field.

#define ALT_QSPI_IRQMSK_RXOVER_MSB   7

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXOVER register field.

#define ALT_QSPI_IRQMSK_RXOVER_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_RXOVER register field.

#define ALT_QSPI_IRQMSK_RXOVER_SET_MSK   0x00000080

The mask used to set the ALT_QSPI_IRQMSK_RXOVER register field value.

#define ALT_QSPI_IRQMSK_RXOVER_CLR_MSK   0xffffff7f

The mask used to clear the ALT_QSPI_IRQMSK_RXOVER register field value.

#define ALT_QSPI_IRQMSK_RXOVER_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_RXOVER register field.

#define ALT_QSPI_IRQMSK_RXOVER_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_QSPI_IRQMSK_RXOVER field value from a register.

#define ALT_QSPI_IRQMSK_RXOVER_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_QSPI_IRQMSK_RXOVER register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_TXTHRESHCMP

Enable Interrupt

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_LSB   8

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_MSB   8

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET_MSK   0x00000100

The mask used to set the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_CLR_MSK   0xfffffeff

The mask used to clear the ALT_QSPI_IRQMSK_TXTHRESHCMP register field value.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_TXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_QSPI_IRQMSK_TXTHRESHCMP field value from a register.

#define ALT_QSPI_IRQMSK_TXTHRESHCMP_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_QSPI_IRQMSK_TXTHRESHCMP register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_TXFULL_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_TXFULL_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_TXFULL

Enable Interrupt

#define ALT_QSPI_IRQMSK_TXFULL_LSB   9

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_TXFULL register field.

#define ALT_QSPI_IRQMSK_TXFULL_MSB   9

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_TXFULL register field.

#define ALT_QSPI_IRQMSK_TXFULL_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_TXFULL register field.

#define ALT_QSPI_IRQMSK_TXFULL_SET_MSK   0x00000200

The mask used to set the ALT_QSPI_IRQMSK_TXFULL register field value.

#define ALT_QSPI_IRQMSK_TXFULL_CLR_MSK   0xfffffdff

The mask used to clear the ALT_QSPI_IRQMSK_TXFULL register field value.

#define ALT_QSPI_IRQMSK_TXFULL_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_TXFULL register field.

#define ALT_QSPI_IRQMSK_TXFULL_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_QSPI_IRQMSK_TXFULL field value from a register.

#define ALT_QSPI_IRQMSK_TXFULL_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_QSPI_IRQMSK_TXFULL register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_RXTHRESHCMP

Enable Interrupt

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_LSB   10

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_MSB   10

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET_MSK   0x00000400

The mask used to set the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_CLR_MSK   0xfffffbff

The mask used to clear the ALT_QSPI_IRQMSK_RXTHRESHCMP register field value.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_RXTHRESHCMP register field.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_QSPI_IRQMSK_RXTHRESHCMP field value from a register.

#define ALT_QSPI_IRQMSK_RXTHRESHCMP_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_QSPI_IRQMSK_RXTHRESHCMP register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_RXFULL_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_RXFULL_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_RXFULL

Enable Interrupt

#define ALT_QSPI_IRQMSK_RXFULL_LSB   11

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_RXFULL register field.

#define ALT_QSPI_IRQMSK_RXFULL_MSB   11

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_RXFULL register field.

#define ALT_QSPI_IRQMSK_RXFULL_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_RXFULL register field.

#define ALT_QSPI_IRQMSK_RXFULL_SET_MSK   0x00000800

The mask used to set the ALT_QSPI_IRQMSK_RXFULL register field value.

#define ALT_QSPI_IRQMSK_RXFULL_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_QSPI_IRQMSK_RXFULL register field value.

#define ALT_QSPI_IRQMSK_RXFULL_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_RXFULL register field.

#define ALT_QSPI_IRQMSK_RXFULL_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_QSPI_IRQMSK_RXFULL field value from a register.

#define ALT_QSPI_IRQMSK_RXFULL_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_QSPI_IRQMSK_RXFULL register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_DISD   0x0

Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL

Disable Interrupt by Masking

#define ALT_QSPI_IRQMSK_INDSRAMFULL_E_END   0x1

Enumerated value for register field ALT_QSPI_IRQMSK_INDSRAMFULL

Enable Interrupt

#define ALT_QSPI_IRQMSK_INDSRAMFULL_LSB   12

The Least Significant Bit (LSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_MSB   12

The Most Significant Bit (MSB) position of the ALT_QSPI_IRQMSK_INDSRAMFULL register field.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_WIDTH   1

The width in bits of the ALT_QSPI_IRQMSK_INDSRAMFULL register field.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET_MSK   0x00001000

The mask used to set the ALT_QSPI_IRQMSK_INDSRAMFULL register field value.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_CLR_MSK   0xffffefff

The mask used to clear the ALT_QSPI_IRQMSK_INDSRAMFULL register field value.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_RESET   0x0

The reset value of the ALT_QSPI_IRQMSK_INDSRAMFULL register field.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_QSPI_IRQMSK_INDSRAMFULL field value from a register.

#define ALT_QSPI_IRQMSK_INDSRAMFULL_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_QSPI_IRQMSK_INDSRAMFULL register field value suitable for setting the register.

#define ALT_QSPI_IRQMSK_OFST   0x44

The byte offset of the ALT_QSPI_IRQMSK register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_QSPI_IRQMSK.