Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : ECC_ERRGENADDR_0

Description

Error address register

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR

Field : ADDR

For decoder 0.

Address generated with SER or address mismatch logic. Address will be driven by the ECC decoder on every read latched by the RAM independent of ECCDiagon is on.

Field Access Macros:

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_LSB   0
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_MSB   31
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_WIDTH   32
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET_MSK   0xffffffff
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_CLR_MSK   0x00000000
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_RESET   0x0
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s
 

Macros

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_OFST   0x160
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s 
ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0.

Data Fields
uint32_t ADDR: 32 ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR

Macro Definitions

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_MSB   31

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_WIDTH   32

The width in bits of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET_MSK   0xffffffff

The mask used to set the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_CLR_MSK   0x00000000

The mask used to clear the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR field value from a register.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_ADDR register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 register.

#define ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0_OFST   0x160

The byte offset of the ALT_ECC_HMC_OCP_ECC_ERRGENADDR_0 register from the beginning of the component.

Typedef Documentation