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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Controls behavior of Boot ROM hardware.
All fields are only reset by a cold reset (ignore warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Wait State |
[1] | RW | 0x1 | Enable Safe Mode Warm Reset Update |
[31:2] | ??? | 0x0 | UNDEFINED |
Field : Wait State - waitstate | ||||||||||||||||
Controls the number of wait states applied to the Boot ROM's read operation. This field is cleared on a cold reset and optionally updated by hardware upon deassertion of warm reset. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET(value) (((value) & 0x00000001) >> 0) | |||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET(value) (((value) << 0) & 0x00000001) | |||||||||||||||
Field : Enable Safe Mode Warm Reset Update - ensfmdwru | |||||||||||||||||||||||||
Controls whether the wait state bit is updated upon deassertion of warm reset. This field is set on a cold reset. Field Enumeration Values:
Field Access Macros: | |||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET(value) (((value) & 0x00000002) >> 1) | ||||||||||||||||||||||||
#define | ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET(value) (((value) << 1) & 0x00000002) | ||||||||||||||||||||||||
Data Structures | |
struct | ALT_SYSMGR_ROMHW_CTL_s |
Macros | |
#define | ALT_SYSMGR_ROMHW_CTL_OFST 0x0 |
Typedefs | |
typedef struct ALT_SYSMGR_ROMHW_CTL_s | ALT_SYSMGR_ROMHW_CTL_t |
struct ALT_SYSMGR_ROMHW_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_ROMHW_CTL.
Data Fields | ||
---|---|---|
uint32_t | waitstate: 1 | Wait State |
uint32_t | ensfmdwru: 1 | Enable Safe Mode Warm Reset Update |
uint32_t | __pad0__: 30 | UNDEFINED |
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
No wait states are applied to the Boom ROM's read operation.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_WAITSTATE
A single wait state is applied to the Boot ROM's read operation.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_RESET 0x0 |
The reset value of the ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_ROMHW_CTL_WAITSTATE field value from a register.
#define ALT_SYSMGR_ROMHW_CTL_WAITSTATE_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_ROMHW_CTL_WAITSTATE register field value suitable for setting the register.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
Wait state bit is not updated upon deassertion of warm reset.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU
Wait state bit is updated upon deassertion of warm reset.
It's value is updated based on the control bit from clock manager which specifies whether clock manager will be in safe mode or not after warm reset.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_RESET 0x1 |
The reset value of the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU field value from a register.
#define ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_ROMHW_CTL_ENSFMDWRU register field value suitable for setting the register.
#define ALT_SYSMGR_ROMHW_CTL_OFST 0x0 |
The byte offset of the ALT_SYSMGR_ROMHW_CTL register from the beginning of the component.
typedef struct ALT_SYSMGR_ROMHW_CTL_s ALT_SYSMGR_ROMHW_CTL_t |
The typedef declaration for register ALT_SYSMGR_ROMHW_CTL.