Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : DRAM Timings 4 Register - dramtiming4

Description

This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.

Register Layout

Bits Access Reset Description
[9:0] RW Unknown Self-refresh Exit
[19:10] RW Unknown Power Down Exit
[23:20] RW Unknown Minimum Low Power State Cycles
[31:24] ??? 0x0 UNDEFINED

Field : Self-refresh Exit - selfrfshexit

The self refresh exit cycles, tXS.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB   0
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB   9
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH   10
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK   0x000003ff
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK   0xfffffc00
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET(value)   (((value) & 0x000003ff) >> 0)
 
#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET(value)   (((value) << 0) & 0x000003ff)
 

Field : Power Down Exit - pwrdownexit

The power down exit cycles, tXPDLL.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB   10
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB   19
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH   10
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK   0x000ffc00
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK   0xfff003ff
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET(value)   (((value) & 0x000ffc00) >> 10)
 
#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET(value)   (((value) << 10) & 0x000ffc00)
 

Field : Minimum Low Power State Cycles - minpwrsavecycles

The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR.

Field Access Macros:

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB   20
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB   23
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH   4
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK   0x00f00000
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK   0xff0fffff
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET   0x0
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET(value)   (((value) & 0x00f00000) >> 20)
 
#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET(value)   (((value) << 20) & 0x00f00000)
 

Data Structures

struct  ALT_SDR_CTL_DRAMTIMING4_s
 

Macros

#define ALT_SDR_CTL_DRAMTIMING4_OFST   0x10
 

Typedefs

typedef struct
ALT_SDR_CTL_DRAMTIMING4_s 
ALT_SDR_CTL_DRAMTIMING4_t
 

Data Structure Documentation

struct ALT_SDR_CTL_DRAMTIMING4_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDR_CTL_DRAMTIMING4.

Data Fields
uint32_t selfrfshexit: 10 Self-refresh Exit
uint32_t pwrdownexit: 10 Power Down Exit
uint32_t minpwrsavecycles: 4 Minimum Low Power State Cycles
uint32_t __pad0__: 8 UNDEFINED

Macro Definitions

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_MSB   9

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_WIDTH   10

The width in bits of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET_MSK   0x000003ff

The mask used to set the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_CLR_MSK   0xfffffc00

The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_GET (   value)    (((value) & 0x000003ff) >> 0)

Extracts the ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT field value from a register.

#define ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT_SET (   value)    (((value) << 0) & 0x000003ff)

Produces a ALT_SDR_CTL_DRAMTIMING4_SELFRFSHEXIT register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_LSB   10

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_MSB   19

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_WIDTH   10

The width in bits of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET_MSK   0x000ffc00

The mask used to set the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_CLR_MSK   0xfff003ff

The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_GET (   value)    (((value) & 0x000ffc00) >> 10)

Extracts the ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT field value from a register.

#define ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT_SET (   value)    (((value) << 10) & 0x000ffc00)

Produces a ALT_SDR_CTL_DRAMTIMING4_PWRDOWNEXIT register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_LSB   20

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_MSB   23

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_WIDTH   4

The width in bits of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET_MSK   0x00f00000

The mask used to set the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_CLR_MSK   0xff0fffff

The mask used to clear the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_RESET   0x0

The reset value of the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field is UNKNOWN.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_GET (   value)    (((value) & 0x00f00000) >> 20)

Extracts the ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES field value from a register.

#define ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES_SET (   value)    (((value) << 20) & 0x00f00000)

Produces a ALT_SDR_CTL_DRAMTIMING4_MINPWRSAVECYCLES register field value suitable for setting the register.

#define ALT_SDR_CTL_DRAMTIMING4_OFST   0x10

The byte offset of the ALT_SDR_CTL_DRAMTIMING4 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDR_CTL_DRAMTIMING4.