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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Used to drive freeze signals to HPS VIO banks.
The register array index corresponds to the freeze channel.
Freeze channel 0 provides freeze signals to VIO bank 0 and 1.
Freeze channel 1 provides freeze signals to VIO bank 2 and 3. Only drives freeze signals when SRC.VIO1 is set to SW.
Freeze channel 2 provides freeze signals to VIO bank 4.
All fields are only reset by a cold reset (ignore warm reset).
The following equation determines when the weak pullup resistor is enabled:
enabled = ~wkpullup | (CFF & cfg & tristate)
where CFF is the value of weak pullup as set by IO configuration
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | IO Configuration |
[1] | RW | 0x0 | IO Bus Hold |
[2] | RW | 0x0 | IO Tri-State |
[3] | RW | 0x0 | IO Weak Pullup |
[4] | RW | 0x0 | IO Slew-rate |
[31:5] | ??? | 0x0 | UNDEFINED |
Field : IO Configuration - cfg | ||||||||||||||||
Controls IO configuration Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) | |||||||||||||||
Field : IO Bus Hold - bushold | ||||||||||
Controls bus hold circuit Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : IO Tri-State - tristate | ||||||||||
Controls IO tri-state Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : IO Weak Pullup - wkpullup | |||||||||||||
Controls weak pullup resistor Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) | ||||||||||||
Field : IO Slew-rate - slew | ||||||||||
Controls IO slew-rate Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Data Structures | |
struct | ALT_SYSMGR_FRZCTL_VIOCTL_s |
Macros | |
#define | ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 |
Typedefs | |
typedef struct ALT_SYSMGR_FRZCTL_VIOCTL_s | ALT_SYSMGR_FRZCTL_VIOCTL_t |
struct ALT_SYSMGR_FRZCTL_VIOCTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_FRZCTL_VIOCTL.
Data Fields | ||
---|---|---|
uint32_t | cfg: 1 | IO Configuration |
uint32_t | bushold: 1 | IO Bus Hold |
uint32_t | tristate: 1 | IO Tri-State |
uint32_t | wkpullup: 1 | IO Weak Pullup |
uint32_t | slew: 1 | IO Slew-rate |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
Disable IO configuration (forced to a safe value).
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_CFG
Enables IO configuration as previously configured by software using the Scan Manager.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_CFG field value from a register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_CFG_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_FRZCTL_VIOCTL_CFG register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
Disable bus hold circuit.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD
Bus hold circuit controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD field value from a register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_FRZCTL_VIOCTL_BUSHOLD register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_EN 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
IO tri-state enabled.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE
IO tri-state controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET_MSK 0x00000004 |
The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE field value from a register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SYSMGR_FRZCTL_VIOCTL_TRISTATE register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_EN 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
Weak pullup resistor enabled.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP
Weak pullup resistor enable controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET_MSK 0x00000008 |
The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP field value from a register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SYSMGR_FRZCTL_VIOCTL_WKPULLUP register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_SLOW 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
Slew-rate forced to slow.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_VIOCTL_SLEW
Slew-rate controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_FRZCTL_VIOCTL_SLEW field value from a register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_SLEW_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_FRZCTL_VIOCTL_SLEW register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_VIOCTL_OFST 0x0 |
The byte offset of the ALT_SYSMGR_FRZCTL_VIOCTL register from the beginning of the component.
typedef struct ALT_SYSMGR_FRZCTL_VIOCTL_s ALT_SYSMGR_FRZCTL_VIOCTL_t |
The typedef declaration for register ALT_SYSMGR_FRZCTL_VIOCTL.