Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : SERRLKUPA0

Description

Single-bit error address in LOOKUP TABLE for PORTA.

Register Layout

Bits Access Reset Description
[9:0] R 0x0 ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR
[30:10] ??? 0x0 UNDEFINED
[31] RW 0x0 ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID

Field : Address

Recent Single-bit error address.

This register shows the address of the each single-bit error. RAM size will determine the maximum number of address bits. If ram size is 32 Kbytes, bit 30-16 will be reserved and read as zero.

Field Access Macros:

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_LSB   0
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_MSB   9
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_WIDTH   10
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET_MSK   0x000003ff
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_CLR_MSK   0xfffffc00
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_RESET   0x0
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_GET(value)   (((value) & 0x000003ff) >> 0)
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET(value)   (((value) << 0) & 0x000003ff)
 

Field : VALID

Valid flag bit. Valid bit indicates if the address in this register is current or stale.

Field Access Macros:

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_LSB   31
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_MSB   31
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_WIDTH   1
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET_MSK   0x80000000
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_CLR_MSK   0x7fffffff
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_RESET   0x0
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s
 

Macros

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_RESET   0x00000000
 
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_OFST   0x90
 

Typedefs

typedef struct
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s 
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_t
 

Data Structure Documentation

struct ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0.

Data Fields
const uint32_t Address: 10 ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR
uint32_t __pad0__: 21 UNDEFINED
uint32_t VALID: 1 ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID

Macro Definitions

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_MSB   9

The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_WIDTH   10

The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET_MSK   0x000003ff

The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_CLR_MSK   0xfffffc00

The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_RESET   0x0

The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_GET (   value)    (((value) & 0x000003ff) >> 0)

Extracts the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR field value from a register.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET (   value)    (((value) << 0) & 0x000003ff)

Produces a ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR register field value suitable for setting the register.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_LSB   31

The Least Significant Bit (LSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_MSB   31

The Most Significant Bit (MSB) position of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_WIDTH   1

The width in bits of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET_MSK   0x80000000

The mask used to set the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_CLR_MSK   0x7fffffff

The mask used to clear the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_RESET   0x0

The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID field value from a register.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID register field value suitable for setting the register.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_RESET   0x00000000

The reset value of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 register.

#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_OFST   0x90

The byte offset of the ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0 register from the beginning of the component.

Typedef Documentation