Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : timer1controlreg

Description

Name: Timer1 Control Register

Size: 3 bits

Address Offset: 8

Read/Write Access: Read/Write

This register controls enabling, operating mode (free-running or defined-count), and interrupt mask of

Timer1. You can program each Timer1ControlReg to enable or disable a specific timer and to control

its mode of operation.

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_TMR_TMR1CTLREG_TMR1_EN
[1] RW 0x0 ALT_TMR_TMR1CTLREG_TMR1_MOD
[2] RW 0x0 ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
[31:3] ??? 0x0 UNDEFINED

Field : timer1_enable

Timer enable bit for Timer1.

0: disable

1: enable

Field Enumeration Values:

Enum Value Description
ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD 0x0 Timer1 Disabled
ALT_TMR_TMR1CTLREG_TMR1_EN_E_END 0x1 Timer1 Enabled

Field Access Macros:

#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END   0x1
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB   0
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB   0
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH   1
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK   0x00000001
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK   0xfffffffe
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : timer1_mode

Timer mode for Timer1.

0: free-running mode

1: user-defined count mode

NOTE: You must set the Timer1LoadCount register to all 1s before

enabling the timer in free-running mode.

Field Enumeration Values:

Enum Value Description
ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN 0x0 Free-running mode
ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF 0x1 User-defined count mode

Field Access Macros:

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF   0x1
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB   1
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB   1
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH   1
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK   0x00000002
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK   0xfffffffd
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET(value)   (((value) << 1) & 0x00000002)
 

Field : timer1_interrupt_mask

Timer interrupt mask for Timer1.

0: not masked

1: masked

Field Enumeration Values:

Enum Value Description
ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED 0x0 interrupt not masked (enabled)
ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED 0x1 interrupt masked (disabled)

Field Access Macros:

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED   0x1
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB   2
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB   2
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH   1
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK   0x00000004
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK   0xfffffffb
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET   0x0
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET(value)   (((value) << 2) & 0x00000004)
 

Data Structures

struct  ALT_TMR_TMR1CTLREG_s
 

Macros

#define ALT_TMR_TMR1CTLREG_RESET   0x00000000
 
#define ALT_TMR_TMR1CTLREG_OFST   0x8
 
#define ALT_TMR_TMR1CTLREG_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST))
 

Typedefs

typedef struct ALT_TMR_TMR1CTLREG_s ALT_TMR_TMR1CTLREG_t
 

Data Structure Documentation

struct ALT_TMR_TMR1CTLREG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_TMR_TMR1CTLREG.

Data Fields
uint32_t timer1_enable: 1 ALT_TMR_TMR1CTLREG_TMR1_EN
uint32_t timer1_mode: 1 ALT_TMR_TMR1CTLREG_TMR1_MOD
uint32_t timer1_interrupt_mask: 1 ALT_TMR_TMR1CTLREG_TMR1_INT_MSK
uint32_t __pad0__: 29 UNDEFINED

Macro Definitions

#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_DISD   0x0

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN

Timer1 Disabled

#define ALT_TMR_TMR1CTLREG_TMR1_EN_E_END   0x1

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_EN

Timer1 Enabled

#define ALT_TMR_TMR1CTLREG_TMR1_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_EN register field.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_WIDTH   1

The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_EN register field.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET_MSK   0x00000001

The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_EN register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_EN register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_RESET   0x0

The reset value of the ALT_TMR_TMR1CTLREG_TMR1_EN register field.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_TMR_TMR1CTLREG_TMR1_EN field value from a register.

#define ALT_TMR_TMR1CTLREG_TMR1_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_TMR_TMR1CTLREG_TMR1_EN register field value suitable for setting the register.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_FREERUN   0x0

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD

Free-running mode

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_E_USEDEF   0x1

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_MOD

User-defined count mode

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_LSB   1

The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_MSB   1

The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_WIDTH   1

The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET_MSK   0x00000002

The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_CLR_MSK   0xfffffffd

The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_MOD register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_RESET   0x0

The reset value of the ALT_TMR_TMR1CTLREG_TMR1_MOD register field.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_TMR_TMR1CTLREG_TMR1_MOD field value from a register.

#define ALT_TMR_TMR1CTLREG_TMR1_MOD_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_TMR_TMR1CTLREG_TMR1_MOD register field value suitable for setting the register.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_NOTMSKED   0x0

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK

interrupt not masked (enabled)

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_E_MSKED   0x1

Enumerated value for register field ALT_TMR_TMR1CTLREG_TMR1_INT_MSK

interrupt masked (disabled)

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_LSB   2

The Least Significant Bit (LSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_MSB   2

The Most Significant Bit (MSB) position of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_WIDTH   1

The width in bits of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET_MSK   0x00000004

The mask used to set the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_CLR_MSK   0xfffffffb

The mask used to clear the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_RESET   0x0

The reset value of the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_TMR_TMR1CTLREG_TMR1_INT_MSK field value from a register.

#define ALT_TMR_TMR1CTLREG_TMR1_INT_MSK_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_TMR_TMR1CTLREG_TMR1_INT_MSK register field value suitable for setting the register.

#define ALT_TMR_TMR1CTLREG_RESET   0x00000000

The reset value of the ALT_TMR_TMR1CTLREG register.

#define ALT_TMR_TMR1CTLREG_OFST   0x8

The byte offset of the ALT_TMR_TMR1CTLREG register from the beginning of the component.

#define ALT_TMR_TMR1CTLREG_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_TMR_TMR1CTLREG_OFST))

The address of the ALT_TMR_TMR1CTLREG register.

Typedef Documentation

The typedef declaration for register ALT_TMR_TMR1CTLREG.