Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 0 (Bus Mode Register) - Bus_Mode

Description

The Bus Mode register establishes the bus operating modes for the DMA.

Register Layout

Bits Access Reset Description
[0] RW 0x1 Software Reset
[1] ??? 0x0 UNDEFINED
[6:2] RW 0x0 Descriptor Skip Length
[7] RW 0x0 Alternate Descriptor Size
[13:8] RW 0x1 Programmable Burst Length
[15:14] ??? 0x0 UNDEFINED
[16] RW 0x0 Fixed Burst
[22:17] RW 0x1 Rx DMA PBL
[23] RW 0x0 Use Separate PBL
[24] RW 0x0 8xPBL Mode
[25] RW 0x0 Address Aligned Beats
[31:26] ??? 0x0 UNDEFINED

Field : Software Reset - swr

When this bit is set, the MAC DMA Controller resets the logic and all internal registers of the MAC. It is cleared automatically after the reset operation has completed in all of the EMAC clock domains. Before reprogramming any register of the EMAC, you should read a zero (0) value in this bit .

Note:

  • The Software reset function is driven only by this bit. Bit 0 of Register 64 (Channel 1 Bus Mode Register) or Register 128 (Channel 2 Bus Mode Register) has no impact on the Software reset function.
  • The reset operation is completed only when all resets in all active clock domains are de-asserted. Therefore, it is essential that all the PHY inputs clocks (applicable for the selected PHY interface) are present for the software reset completion.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST 0x0 MAC DMA Controller Clears Logic
ALT_EMAC_DMA_BUS_MOD_SWR_E_RST 0x1 MAC DMA Controller Resets Logic

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_LSB   0
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_MSB   0
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_RESET   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_BUS_MOD_SWR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Descriptor Skip Length - dsl

This bit specifies the number of Word, Dword, or Lword (depending on the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of current descriptor to the start of next descriptor. When the DSL value is equal to zero, then the descriptor table is taken as contiguous by the DMA in Ring mode.

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_DSL_LSB   2
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_MSB   6
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH   5
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK   0x0000007c
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK   0xffffff83
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_GET(value)   (((value) & 0x0000007c) >> 2)
 
#define ALT_EMAC_DMA_BUS_MOD_DSL_SET(value)   (((value) << 2) & 0x0000007c)
 

Field : Alternate Descriptor Size - atds

When set, the size of the alternate descriptor increases to 32 bytes (8 DWORDS). This is required when the Advanced Timestamp feature or the IPC Full Offload Engine (Type 2) is enabled in the receiver. The enhanced descriptor is not required if the Advanced Timestamp and IPC Full Checksum Offload (Type 2) features are not enabled. In such cases, you can use the 16 bytes descriptor to save 4 bytes of memory.

When reset, the descriptor size reverts back to 4 DWORDs (16 bytes).

This bit preserves the backward compatibility for the descriptor size. In versions prior to 3.50a, the descriptor size is 16 bytes for both normal and enhanced descriptor. In version 3.50a, descriptor size is increased to 32 bytes because of the Advanced Timestamp and IPC Full Checksum Offload Engine (Type 2) features.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST 0x0 MAC DMA Controller Clears Logic
ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST 0x1 MAC DMA Controller Resets Logic

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB   7
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB   7
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK   0x00000080
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Programmable Burst Length - pbl

These bits indicate the maximum number of beats to be transferred in one DMA transaction. This is the maximum value that is used in a single block Read or Write. The DMA always attempts to burst as specified in PBL each time it starts a Burst transfer on the host bus. PBL can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior. When USP is set high, this PBL value is applicable only for Tx DMA transactions.

If the number of beats to be transferred is more than 32, then perform the following steps:

  1. Set the 8xPBL mode.
  1. Set the PBL.

For example, if the maximum number of beats to be transferred is 64, then first set 8xPBL to 1 and then set PBL to 8. The PBL values have the following limitation: The maximum number of possible beats (PBL) is limited by the size of the Tx FIFO and Rx FIFO in the MTL layer and the data bus width on the DMA. The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO, except when specified.

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_PBL_LSB   8
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_MSB   13
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH   6
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK   0x00003f00
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK   0xffffc0ff
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_RESET   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_GET(value)   (((value) & 0x00003f00) >> 8)
 
#define ALT_EMAC_DMA_BUS_MOD_PBL_SET(value)   (((value) << 8) & 0x00003f00)
 

Field : Fixed Burst - fb

This bit controls whether the AXI Master interface performs fixed burst transfers or not. When set, the AXI interface uses FIXED bursts during the start of the normal burst transfers. When reset, the AXI interface uses SINGLE and INCR burst transfer operations.

For more information, see Bit 0 (UNDEFINED) of the AXI Bus Mode register.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB 0x0 SINGLE or INCR Burst
ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16 0x1 FIXED Burst (1, 4, 8, or 16)

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_FB_LSB   16
 
#define ALT_EMAC_DMA_BUS_MOD_FB_MSB   16
 
#define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK   0x00010000
 
#define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_DMA_BUS_MOD_FB_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_FB_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_DMA_BUS_MOD_FB_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Rx DMA PBL - rpbl

This field indicates the maximum number of beats to be transferred in one Rx DMA transaction. This is the maximum value that is used in a single block Read or Write.

The Rx DMA always attempts to burst as specified in the RPBL bit each time it starts a Burst transfer on the host bus. You can program RPBL with values of 1, 2, 4, 8, 16, and 32. Any other value results in undefined behavior.

This field is valid and applicable only when USP is set high.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1 0x1 Beats Trans. in one Rx DMA Transaction
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2 0x2 Beats Trans. in one Rx DMA Transaction
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4 0x4 Beats Trans. in one Rx DMA Transaction
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8 0x8 Beats Trans. in one Rx DMA Transaction
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6 0x10 Beats Trans. in one Rx DMA Transaction
ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32 0x20 Beats Trans. in one Rx DMA Transaction

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2   0x2
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4   0x4
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8   0x8
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6   0x10
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32   0x20
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB   17
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB   22
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH   6
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK   0x007e0000
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK   0xff81ffff
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_GET(value)   (((value) & 0x007e0000) >> 17)
 
#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET(value)   (((value) << 17) & 0x007e0000)
 

Field : Use Separate PBL - usp

When set high, this bit configures the Rx DMA to use the value configured in Bits[22:17] as PBL. The PBL value in Bits[13:8] is applicable only to the Tx DMA operations.

When reset to low, the PBL value in Bits[13:8] is applicable for both DMA engines.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_USP_E_DISD 0x0 Configures TX RX DMA to PBL
ALT_EMAC_DMA_BUS_MOD_USP_E_END 0x1 Configures TX DMA to PBL

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_USP_E_END   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_USP_LSB   23
 
#define ALT_EMAC_DMA_BUS_MOD_USP_MSB   23
 
#define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK   0x00800000
 
#define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_DMA_BUS_MOD_USP_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_USP_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_DMA_BUS_MOD_USP_SET(value)   (((value) << 23) & 0x00800000)
 

Field : 8xPBL Mode - eightxpbl

When set high, this bit multiplies the programmed PBL value (Bits[22:17] and Bits[13:8]) eight times. Therefore, the DMA transfers the data in 8, 16, 32, 64, 128, and 256 beats depending on the PBL value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD 0x0 Non Multiply Mode
ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END 0x1 Multiplies PBL value by 8

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB   24
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB   24
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK   0x01000000
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET(value)   (((value) << 24) & 0x01000000)
 

Field : Address Aligned Beats - aal

When this bit is set high and the FB bit is equal to 1, the AHB or AXI interface generates all bursts aligned to the start address LS bits. If the FB bit is equal to 0, the first burst (accessing the data buffer's start address) is not aligned, but subsequent bursts are aligned to the address.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD 0x0 No Address-Aligned Beats
ALT_EMAC_DMA_BUS_MOD_AAL_E_END 0x1 Address-Aligned Beats (dependent on FB)

Field Access Macros:

#define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_E_END   0x1
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_LSB   25
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_MSB   25
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH   1
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK   0x02000000
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_RESET   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_DMA_BUS_MOD_AAL_SET(value)   (((value) << 25) & 0x02000000)
 

Data Structures

struct  ALT_EMAC_DMA_BUS_MOD_s
 

Macros

#define ALT_EMAC_DMA_BUS_MOD_OFST   0x0
 
#define ALT_EMAC_DMA_BUS_MOD_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_BUS_MOD_s 
ALT_EMAC_DMA_BUS_MOD_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_BUS_MOD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_BUS_MOD.

Data Fields
uint32_t swr: 1 Software Reset
uint32_t __pad0__: 1 UNDEFINED
uint32_t dsl: 5 Descriptor Skip Length
uint32_t atds: 1 Alternate Descriptor Size
uint32_t pbl: 6 Programmable Burst Length
uint32_t __pad1__: 2 UNDEFINED
uint32_t fb: 1 Fixed Burst
uint32_t rpbl: 6 Rx DMA PBL
uint32_t usp: 1 Use Separate PBL
uint32_t eightxpbl: 1 8xPBL Mode
uint32_t aal: 1 Address Aligned Beats
uint32_t __pad2__: 6 UNDEFINED

Macro Definitions

#define ALT_EMAC_DMA_BUS_MOD_SWR_E_CLRRST   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR

MAC DMA Controller Clears Logic

#define ALT_EMAC_DMA_BUS_MOD_SWR_E_RST   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_SWR

MAC DMA Controller Resets Logic

#define ALT_EMAC_DMA_BUS_MOD_SWR_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field.

#define ALT_EMAC_DMA_BUS_MOD_SWR_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_SWR register field.

#define ALT_EMAC_DMA_BUS_MOD_SWR_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_SWR register field.

#define ALT_EMAC_DMA_BUS_MOD_SWR_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_BUS_MOD_SWR register field value.

#define ALT_EMAC_DMA_BUS_MOD_SWR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_SWR register field value.

#define ALT_EMAC_DMA_BUS_MOD_SWR_RESET   0x1

The reset value of the ALT_EMAC_DMA_BUS_MOD_SWR register field.

#define ALT_EMAC_DMA_BUS_MOD_SWR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_BUS_MOD_SWR field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_SWR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_BUS_MOD_SWR register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_DSL_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field.

#define ALT_EMAC_DMA_BUS_MOD_DSL_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_DSL register field.

#define ALT_EMAC_DMA_BUS_MOD_DSL_WIDTH   5

The width in bits of the ALT_EMAC_DMA_BUS_MOD_DSL register field.

#define ALT_EMAC_DMA_BUS_MOD_DSL_SET_MSK   0x0000007c

The mask used to set the ALT_EMAC_DMA_BUS_MOD_DSL register field value.

#define ALT_EMAC_DMA_BUS_MOD_DSL_CLR_MSK   0xffffff83

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_DSL register field value.

#define ALT_EMAC_DMA_BUS_MOD_DSL_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_DSL register field.

#define ALT_EMAC_DMA_BUS_MOD_DSL_GET (   value)    (((value) & 0x0000007c) >> 2)

Extracts the ALT_EMAC_DMA_BUS_MOD_DSL field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_DSL_SET (   value)    (((value) << 2) & 0x0000007c)

Produces a ALT_EMAC_DMA_BUS_MOD_DSL register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_CLRRST   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS

MAC DMA Controller Clears Logic

#define ALT_EMAC_DMA_BUS_MOD_ATDS_E_RST   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_ATDS

MAC DMA Controller Resets Logic

#define ALT_EMAC_DMA_BUS_MOD_ATDS_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_DMA_BUS_MOD_ATDS register field value.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_ATDS register field value.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_ATDS register field.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_DMA_BUS_MOD_ATDS field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_ATDS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_DMA_BUS_MOD_ATDS register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_PBL_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field.

#define ALT_EMAC_DMA_BUS_MOD_PBL_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_PBL register field.

#define ALT_EMAC_DMA_BUS_MOD_PBL_WIDTH   6

The width in bits of the ALT_EMAC_DMA_BUS_MOD_PBL register field.

#define ALT_EMAC_DMA_BUS_MOD_PBL_SET_MSK   0x00003f00

The mask used to set the ALT_EMAC_DMA_BUS_MOD_PBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_PBL_CLR_MSK   0xffffc0ff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_PBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_PBL_RESET   0x1

The reset value of the ALT_EMAC_DMA_BUS_MOD_PBL register field.

#define ALT_EMAC_DMA_BUS_MOD_PBL_GET (   value)    (((value) & 0x00003f00) >> 8)

Extracts the ALT_EMAC_DMA_BUS_MOD_PBL field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_PBL_SET (   value)    (((value) << 8) & 0x00003f00)

Produces a ALT_EMAC_DMA_BUS_MOD_PBL register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_FB_E_NONFB   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB

SINGLE or INCR Burst

#define ALT_EMAC_DMA_BUS_MOD_FB_E_FB1_4_8_16   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_FB

FIXED Burst (1, 4, 8, or 16)

#define ALT_EMAC_DMA_BUS_MOD_FB_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field.

#define ALT_EMAC_DMA_BUS_MOD_FB_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_FB register field.

#define ALT_EMAC_DMA_BUS_MOD_FB_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_FB register field.

#define ALT_EMAC_DMA_BUS_MOD_FB_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_DMA_BUS_MOD_FB register field value.

#define ALT_EMAC_DMA_BUS_MOD_FB_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_FB register field value.

#define ALT_EMAC_DMA_BUS_MOD_FB_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_FB register field.

#define ALT_EMAC_DMA_BUS_MOD_FB_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_DMA_BUS_MOD_FB field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_FB_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_DMA_BUS_MOD_FB register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL1   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL2   0x2

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL4   0x4

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL8   0x8

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL6   0x10

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_E_RXDMAPBL32   0x20

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_RPBL

Beats Trans. in one Rx DMA Transaction

#define ALT_EMAC_DMA_BUS_MOD_RPBL_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_WIDTH   6

The width in bits of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET_MSK   0x007e0000

The mask used to set the ALT_EMAC_DMA_BUS_MOD_RPBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_CLR_MSK   0xff81ffff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_RPBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_RESET   0x1

The reset value of the ALT_EMAC_DMA_BUS_MOD_RPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_GET (   value)    (((value) & 0x007e0000) >> 17)

Extracts the ALT_EMAC_DMA_BUS_MOD_RPBL field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_RPBL_SET (   value)    (((value) << 17) & 0x007e0000)

Produces a ALT_EMAC_DMA_BUS_MOD_RPBL register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_USP_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP

Configures TX RX DMA to PBL

#define ALT_EMAC_DMA_BUS_MOD_USP_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_USP

Configures TX DMA to PBL

#define ALT_EMAC_DMA_BUS_MOD_USP_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field.

#define ALT_EMAC_DMA_BUS_MOD_USP_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_USP register field.

#define ALT_EMAC_DMA_BUS_MOD_USP_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_USP register field.

#define ALT_EMAC_DMA_BUS_MOD_USP_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_DMA_BUS_MOD_USP register field value.

#define ALT_EMAC_DMA_BUS_MOD_USP_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_USP register field value.

#define ALT_EMAC_DMA_BUS_MOD_USP_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_USP register field.

#define ALT_EMAC_DMA_BUS_MOD_USP_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_DMA_BUS_MOD_USP field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_USP_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_DMA_BUS_MOD_USP register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL

Non Multiply Mode

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL

Multiplies PBL value by 8

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_DMA_BUS_MOD_EIGHTXPBL register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_AAL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL

No Address-Aligned Beats

#define ALT_EMAC_DMA_BUS_MOD_AAL_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_BUS_MOD_AAL

Address-Aligned Beats (dependent on FB)

#define ALT_EMAC_DMA_BUS_MOD_AAL_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field.

#define ALT_EMAC_DMA_BUS_MOD_AAL_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_BUS_MOD_AAL register field.

#define ALT_EMAC_DMA_BUS_MOD_AAL_WIDTH   1

The width in bits of the ALT_EMAC_DMA_BUS_MOD_AAL register field.

#define ALT_EMAC_DMA_BUS_MOD_AAL_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_DMA_BUS_MOD_AAL register field value.

#define ALT_EMAC_DMA_BUS_MOD_AAL_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_DMA_BUS_MOD_AAL register field value.

#define ALT_EMAC_DMA_BUS_MOD_AAL_RESET   0x0

The reset value of the ALT_EMAC_DMA_BUS_MOD_AAL register field.

#define ALT_EMAC_DMA_BUS_MOD_AAL_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_DMA_BUS_MOD_AAL field value from a register.

#define ALT_EMAC_DMA_BUS_MOD_AAL_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_DMA_BUS_MOD_AAL register field value suitable for setting the register.

#define ALT_EMAC_DMA_BUS_MOD_OFST   0x0

The byte offset of the ALT_EMAC_DMA_BUS_MOD register from the beginning of the component.

#define ALT_EMAC_DMA_BUS_MOD_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_BUS_MOD_OFST))

The address of the ALT_EMAC_DMA_BUS_MOD register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_BUS_MOD.