Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : max_rd_delay

Description

Max round trip read data delay for data capture

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_NAND_CFG_MAX_RD_DELAY_VALUE
[31:4] ??? Unknown UNDEFINED

Field : value

Number of clk_x cycles after generation of feedback clk_x_out pulse when it is safe

to synchronize received data to clk_x domain. Data should have been registered with

clk_x_in and stable by the time max_rd_delay cycles has elapsed. Please see timing

diagram in bus interface timing section of this guide for further elaboration. A

default value of zero will mean a value of clk_x multiple minus one.

Field Access Macros:

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB   0
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB   3
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH   4
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK   0x0000000f
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK   0xfffffff0
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET   0x0
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET(value)   (((value) << 0) & 0x0000000f)
 

Data Structures

struct  ALT_NAND_CFG_MAX_RD_DELAY_s
 

Macros

#define ALT_NAND_CFG_MAX_RD_DELAY_RESET   0x00000000
 
#define ALT_NAND_CFG_MAX_RD_DELAY_OFST   0x210
 

Typedefs

typedef struct
ALT_NAND_CFG_MAX_RD_DELAY_s 
ALT_NAND_CFG_MAX_RD_DELAY_t
 

Data Structure Documentation

struct ALT_NAND_CFG_MAX_RD_DELAY_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_MAX_RD_DELAY.

Data Fields
uint32_t value: 4 ALT_NAND_CFG_MAX_RD_DELAY_VALUE
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_MSB   3

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_WIDTH   4

The width in bits of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET_MSK   0x0000000f

The mask used to set the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_CLR_MSK   0xfffffff0

The mask used to clear the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_RESET   0x0

The reset value of the ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_NAND_CFG_MAX_RD_DELAY_VALUE field value from a register.

#define ALT_NAND_CFG_MAX_RD_DELAY_VALUE_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_NAND_CFG_MAX_RD_DELAY_VALUE register field value suitable for setting the register.

#define ALT_NAND_CFG_MAX_RD_DELAY_RESET   0x00000000

The reset value of the ALT_NAND_CFG_MAX_RD_DELAY register.

#define ALT_NAND_CFG_MAX_RD_DELAY_OFST   0x210

The byte offset of the ALT_NAND_CFG_MAX_RD_DELAY register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_CFG_MAX_RD_DELAY.