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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Sets Master Region Enable field when written with 1
Register Layout
Field : mpuregion0enable | |
MPU Region 0 Enable Set. Writing zero has no effect Writing one will set the mpuregion0enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_LSB 0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_MSB 0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET_MSK 0x00000001 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_CLR_MSK 0xfffffffe |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET(value) (((value) << 0) & 0x00000001) |
Field : mpuregion1enable | |
MPU Region 1 Enable Set. Writing zero has no effect Writing one will set the mpuregion1enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_LSB 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_MSB 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET_MSK 0x00000002 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_CLR_MSK 0xfffffffd |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET(value) (((value) << 1) & 0x00000002) |
Field : mpuregion2enable | |
MPU Region 2 Enable Set. Writing zero has no effect Writing one will set the mpuregion2enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_LSB 2 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_MSB 2 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET_MSK 0x00000004 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_CLR_MSK 0xfffffffb |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET(value) (((value) << 2) & 0x00000004) |
Field : mpuregion3enable | |
MPU Region 3 Enable Set. Writing zero has no effect Writing one will set the mpuregion3enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_LSB 3 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_MSB 3 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET_MSK 0x00000008 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_CLR_MSK 0xfffffff7 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET(value) (((value) << 3) & 0x00000008) |
Field : fpga2sdram0region0enable | |
FPGA2SDRAM0 Region 0 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram0region0enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_LSB 4 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_MSB 4 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET_MSK 0x00000010 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_CLR_MSK 0xffffffef |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET(value) (((value) << 4) & 0x00000010) |
Field : fpga2sdram0region1enable | |
FPGA2SDRAM0 Region 1 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram0region1enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_LSB 5 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_MSB 5 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET_MSK 0x00000020 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_CLR_MSK 0xffffffdf |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET(value) (((value) << 5) & 0x00000020) |
Field : fpga2sdram0region2enable | |
FPGA2SDRAM0 Region 2 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram0region2enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_LSB 6 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_MSB 6 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET_MSK 0x00000040 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_CLR_MSK 0xffffffbf |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET(value) (((value) << 6) & 0x00000040) |
Field : fpga2sdram0region3enable | |
FPGA2SDRAM0 Region 3 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram0region3enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_LSB 7 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_MSB 7 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET_MSK 0x00000080 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_CLR_MSK 0xffffff7f |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET(value) (((value) << 7) & 0x00000080) |
Field : fpga2sdram1region0enable | |
FPGA2SDRAM1 Region 0 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram1region0enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_LSB 8 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_MSB 8 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET_MSK 0x00000100 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_CLR_MSK 0xfffffeff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET(value) (((value) << 8) & 0x00000100) |
Field : fpga2sdram1region1enable | |
FPGA2SDRAM1 Region 1 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram1region1enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_LSB 9 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_MSB 9 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET_MSK 0x00000200 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_CLR_MSK 0xfffffdff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET(value) (((value) << 9) & 0x00000200) |
Field : fpga2sdram1region2enable | |
FPGA2SDRAM1 Region 2 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram1region2enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_LSB 10 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_MSB 10 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET_MSK 0x00000400 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_CLR_MSK 0xfffffbff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET(value) (((value) << 10) & 0x00000400) |
Field : fpga2sdram1region3enable | |
FPGA2SDRAM1 Region 3 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram1region3enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_LSB 11 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_MSB 11 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET_MSK 0x00000800 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_CLR_MSK 0xfffff7ff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET(value) (((value) << 11) & 0x00000800) |
Field : fpga2sdram2region0enable | |
FPGA2SDRAM2 Region 0 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram2region0enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_LSB 12 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_MSB 12 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET_MSK 0x00001000 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_CLR_MSK 0xffffefff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET(value) (((value) << 12) & 0x00001000) |
Field : fpga2sdram2region1enable | |
FPGA2SDRAM2 Region 1 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram2region1enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_LSB 13 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_MSB 13 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET_MSK 0x00002000 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_CLR_MSK 0xffffdfff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET(value) (((value) << 13) & 0x00002000) |
Field : fpga2sdram2region2enable | |
FPGA2SDRAM2 Region 2 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram2region2enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_LSB 14 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_MSB 14 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET_MSK 0x00004000 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_CLR_MSK 0xffffbfff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET(value) (((value) << 14) & 0x00004000) |
Field : fpga2sdram2region3enable | |
FPGA2SDRAM2 Region 3 Enable Set. Writing zero has no effect Writing one will set the fpga2sdram2region3enable bit to one Field Access Macros: | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_LSB 15 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_MSB 15 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_WIDTH 1 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET_MSK 0x00008000 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_CLR_MSK 0xffff7fff |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_RESET 0x0 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET(value) (((value) << 15) & 0x00008000) |
Data Structures | |
struct | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s |
Macros | |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_RESET 0x00000000 |
#define | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_OFST 0x4 |
Typedefs | |
typedef struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s | ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_t |
struct ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET_MSK 0x00000001 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG0EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET_MSK 0x00000002 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG1EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET_MSK 0x00000004 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG2EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET_MSK 0x00000008 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_MPUREG3EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET_MSK 0x00000010 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_CLR_MSK 0xffffffef |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG0EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET_MSK 0x00000020 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG1EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET_MSK 0x00000040 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG2EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET_MSK 0x00000080 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR0REG3EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET_MSK 0x00000100 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG0EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET_MSK 0x00000200 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG1EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET_MSK 0x00000400 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG2EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET_MSK 0x00000800 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR1REG3EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET_MSK 0x00001000 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_CLR_MSK 0xffffefff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG0EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET_MSK 0x00002000 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG1EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET_MSK 0x00004000 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG2EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_WIDTH 1 |
The width in bits of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET_MSK 0x00008000 |
The mask used to set the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN field value from a register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_F2SDR2REG3EN register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_RESET 0x00000000 |
The reset value of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET register.
#define ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET_OFST 0x4 |
The byte offset of the ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET register from the beginning of the component.
The typedef declaration for register ALT_NOC_FW_DDR_MPU_F2SDR_DDR_SCR_EN_SET.