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alt_noc_l4_priv_flt.h
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32 
35 #ifndef __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
36 #define __ALT_SOCAL_NOC_L4_PRIV_FLT_H__
37 
38 #ifndef __ASSEMBLY__
39 #ifdef __cplusplus
40 #include <cstdint>
41 extern "C"
42 {
43 #else /* __cplusplus */
44 #include <stdint.h>
45 #endif /* __cplusplus */
46 #endif /* __ASSEMBLY__ */
47 
112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_LSB 0
113 
114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_MSB 0
115 
116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_WIDTH 1
117 
118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET_MSK 0x00000001
119 
120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_CLR_MSK 0xfffffffe
121 
122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_RESET 0x0
123 
124 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
125 
126 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
127 
139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_LSB 1
140 
141 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_MSB 1
142 
143 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_WIDTH 1
144 
145 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET_MSK 0x00000002
146 
147 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_CLR_MSK 0xfffffffd
148 
149 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_RESET 0x0
150 
151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
152 
153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
154 
166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_LSB 2
167 
168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_MSB 2
169 
170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_WIDTH 1
171 
172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET_MSK 0x00000004
173 
174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_CLR_MSK 0xfffffffb
175 
176 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_RESET 0x0
177 
178 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
179 
180 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
181 
193 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_LSB 3
194 
195 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_MSB 3
196 
197 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_WIDTH 1
198 
199 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET_MSK 0x00000008
200 
201 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_CLR_MSK 0xfffffff7
202 
203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_RESET 0x0
204 
205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
206 
207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
208 
220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_LSB 4
221 
222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_MSB 4
223 
224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_WIDTH 1
225 
226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET_MSK 0x00000010
227 
228 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_CLR_MSK 0xffffffef
229 
230 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_RESET 0x0
231 
232 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
233 
234 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
235 
247 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_LSB 5
248 
249 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_MSB 5
250 
251 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_WIDTH 1
252 
253 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET_MSK 0x00000020
254 
255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_CLR_MSK 0xffffffdf
256 
257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_RESET 0x0
258 
259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
260 
261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
262 
274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_LSB 6
275 
276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_MSB 6
277 
278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_WIDTH 1
279 
280 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET_MSK 0x00000040
281 
282 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_CLR_MSK 0xffffffbf
283 
284 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_RESET 0x0
285 
286 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
287 
288 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
289 
301 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_LSB 7
302 
303 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_MSB 7
304 
305 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_WIDTH 1
306 
307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET_MSK 0x00000080
308 
309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_CLR_MSK 0xffffff7f
310 
311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_RESET 0x0
312 
313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
314 
315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
316 
328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_LSB 8
329 
330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_MSB 8
331 
332 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_WIDTH 1
333 
334 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET_MSK 0x00000100
335 
336 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_CLR_MSK 0xfffffeff
337 
338 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_RESET 0x0
339 
340 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
341 
342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
343 
355 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_LSB 9
356 
357 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_MSB 9
358 
359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_WIDTH 1
360 
361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET_MSK 0x00000200
362 
363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_CLR_MSK 0xfffffdff
364 
365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_RESET 0x0
366 
367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
368 
369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
370 
382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_LSB 10
383 
384 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_MSB 10
385 
386 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_WIDTH 1
387 
388 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET_MSK 0x00000400
389 
390 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_CLR_MSK 0xfffffbff
391 
392 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_RESET 0x0
393 
394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
395 
396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
397 
409 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_LSB 11
410 
411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_MSB 11
412 
413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_WIDTH 1
414 
415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET_MSK 0x00000800
416 
417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_CLR_MSK 0xfffff7ff
418 
419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_RESET 0x0
420 
421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
422 
423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET(value) (((value) << 11) & 0x00000800)
424 
436 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_LSB 12
437 
438 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_MSB 12
439 
440 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_WIDTH 1
441 
442 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET_MSK 0x00001000
443 
444 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_CLR_MSK 0xffffefff
445 
446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_RESET 0x0
447 
448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
449 
450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET(value) (((value) << 12) & 0x00001000)
451 
463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_LSB 13
464 
465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_MSB 13
466 
467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_WIDTH 1
468 
469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET_MSK 0x00002000
470 
471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_CLR_MSK 0xffffdfff
472 
473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_RESET 0x0
474 
475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
476 
477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET(value) (((value) << 13) & 0x00002000)
478 
490 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_LSB 14
491 
492 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_MSB 14
493 
494 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_WIDTH 1
495 
496 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET_MSK 0x00004000
497 
498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_CLR_MSK 0xffffbfff
499 
500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_RESET 0x0
501 
502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
503 
504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET(value) (((value) << 14) & 0x00004000)
505 
517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_LSB 15
518 
519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_MSB 15
520 
521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_WIDTH 1
522 
523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET_MSK 0x00008000
524 
525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_CLR_MSK 0xffff7fff
526 
527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_RESET 0x0
528 
529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_GET(value) (((value) & 0x00008000) >> 15)
530 
531 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET(value) (((value) << 15) & 0x00008000)
532 
544 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_LSB 16
545 
546 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_MSB 16
547 
548 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_WIDTH 1
549 
550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET_MSK 0x00010000
551 
552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_CLR_MSK 0xfffeffff
553 
554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_RESET 0x0
555 
556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
557 
558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET(value) (((value) << 16) & 0x00010000)
559 
571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_LSB 17
572 
573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_MSB 17
574 
575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_WIDTH 1
576 
577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET_MSK 0x00020000
578 
579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_CLR_MSK 0xfffdffff
580 
581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_RESET 0x0
582 
583 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
584 
585 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET(value) (((value) << 17) & 0x00020000)
586 
598 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_LSB 18
599 
600 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_MSB 18
601 
602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_WIDTH 1
603 
604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET_MSK 0x00040000
605 
606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_CLR_MSK 0xfffbffff
607 
608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_RESET 0x0
609 
610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
611 
612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET(value) (((value) << 18) & 0x00040000)
613 
625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_LSB 19
626 
627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_MSB 19
628 
629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_WIDTH 1
630 
631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET_MSK 0x00080000
632 
633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_CLR_MSK 0xfff7ffff
634 
635 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_RESET 0x0
636 
637 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
638 
639 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET(value) (((value) << 19) & 0x00080000)
640 
652 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_LSB 20
653 
654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_MSB 20
655 
656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_WIDTH 1
657 
658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET_MSK 0x00100000
659 
660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_CLR_MSK 0xffefffff
661 
662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_RESET 0x0
663 
664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_GET(value) (((value) & 0x00100000) >> 20)
665 
666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET(value) (((value) << 20) & 0x00100000)
667 
679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_LSB 21
680 
681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_MSB 21
682 
683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_WIDTH 1
684 
685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET_MSK 0x00200000
686 
687 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_CLR_MSK 0xffdfffff
688 
689 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_RESET 0x0
690 
691 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_GET(value) (((value) & 0x00200000) >> 21)
692 
693 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET(value) (((value) << 21) & 0x00200000)
694 
706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_LSB 22
707 
708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_MSB 22
709 
710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_WIDTH 1
711 
712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET_MSK 0x00400000
713 
714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_CLR_MSK 0xffbfffff
715 
716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_RESET 0x0
717 
718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_GET(value) (((value) & 0x00400000) >> 22)
719 
720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET(value) (((value) << 22) & 0x00400000)
721 
733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_LSB 23
734 
735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_MSB 23
736 
737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_WIDTH 1
738 
739 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET_MSK 0x00800000
740 
741 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_CLR_MSK 0xff7fffff
742 
743 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_RESET 0x0
744 
745 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_GET(value) (((value) & 0x00800000) >> 23)
746 
747 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET(value) (((value) << 23) & 0x00800000)
748 
760 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_LSB 24
761 
762 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_MSB 24
763 
764 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_WIDTH 1
765 
766 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET_MSK 0x01000000
767 
768 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_CLR_MSK 0xfeffffff
769 
770 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_RESET 0x0
771 
772 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_GET(value) (((value) & 0x01000000) >> 24)
773 
774 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET(value) (((value) << 24) & 0x01000000)
775 
787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_LSB 25
788 
789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_MSB 25
790 
791 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_WIDTH 1
792 
793 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET_MSK 0x02000000
794 
795 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_CLR_MSK 0xfdffffff
796 
797 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_RESET 0x0
798 
799 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
800 
801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
802 
814 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_LSB 26
815 
816 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_MSB 26
817 
818 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_WIDTH 1
819 
820 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET_MSK 0x04000000
821 
822 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_CLR_MSK 0xfbffffff
823 
824 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_RESET 0x0
825 
826 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
827 
828 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
829 
841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_LSB 27
842 
843 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_MSB 27
844 
845 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_WIDTH 1
846 
847 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET_MSK 0x08000000
848 
849 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_CLR_MSK 0xf7ffffff
850 
851 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_RESET 0x0
852 
853 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_GET(value) (((value) & 0x08000000) >> 27)
854 
855 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET(value) (((value) << 27) & 0x08000000)
856 
868 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_LSB 28
869 
870 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_MSB 28
871 
872 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_WIDTH 1
873 
874 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET_MSK 0x10000000
875 
876 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_CLR_MSK 0xefffffff
877 
878 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_RESET 0x0
879 
880 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_GET(value) (((value) & 0x10000000) >> 28)
881 
882 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET(value) (((value) << 28) & 0x10000000)
883 
895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_LSB 29
896 
897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_MSB 29
898 
899 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_WIDTH 1
900 
901 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET_MSK 0x20000000
902 
903 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_CLR_MSK 0xdfffffff
904 
905 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_RESET 0x0
906 
907 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
908 
909 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET(value) (((value) << 29) & 0x20000000)
910 
922 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_LSB 30
923 
924 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_MSB 30
925 
926 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_WIDTH 1
927 
928 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET_MSK 0x40000000
929 
930 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_CLR_MSK 0xbfffffff
931 
932 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_RESET 0x0
933 
934 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_GET(value) (((value) & 0x40000000) >> 30)
935 
936 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET(value) (((value) << 30) & 0x40000000)
937 
938 #ifndef __ASSEMBLY__
939 
950 {
951  uint32_t nand_register : 1;
952  uint32_t nand_data : 1;
953  uint32_t qspi_data : 1;
954  uint32_t usb0_register : 1;
955  uint32_t usb1_register : 1;
956  uint32_t dma_nonsecure : 1;
957  uint32_t dma_secure : 1;
958  uint32_t spi_master0 : 1;
959  uint32_t spi_master1 : 1;
960  uint32_t spi_slave0 : 1;
961  uint32_t spi_slave1 : 1;
962  uint32_t emac0 : 1;
963  uint32_t emac1 : 1;
964  uint32_t emac2 : 1;
965  uint32_t emac3 : 1;
966  uint32_t qspi : 1;
967  uint32_t sdmmc : 1;
968  uint32_t gpio0 : 1;
969  uint32_t gpio1 : 1;
970  uint32_t gpio2 : 1;
971  uint32_t i2c0 : 1;
972  uint32_t i2c1 : 1;
973  uint32_t i2c2 : 1;
974  uint32_t i2c3 : 1;
975  uint32_t i2c4 : 1;
976  uint32_t sp_timer0 : 1;
977  uint32_t sp_timer1 : 1;
978  uint32_t uart0 : 1;
979  uint32_t uart1 : 1;
980  uint32_t lwsoc2fpga : 1;
981  uint32_t soc2fpga : 1;
982  uint32_t : 1;
983 };
984 
987 #endif /* __ASSEMBLY__ */
988 
990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_RESET 0x00000000
991 
992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_OFST 0x0
993 
1047 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_LSB 0
1048 
1049 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_MSB 0
1050 
1051 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_WIDTH 1
1052 
1053 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET_MSK 0x00000001
1054 
1055 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_CLR_MSK 0xfffffffe
1056 
1057 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_RESET 0x0
1058 
1059 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1060 
1061 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1062 
1073 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_LSB 1
1074 
1075 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_MSB 1
1076 
1077 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_WIDTH 1
1078 
1079 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET_MSK 0x00000002
1080 
1081 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_CLR_MSK 0xfffffffd
1082 
1083 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_RESET 0x0
1084 
1085 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1086 
1087 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1088 
1099 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_LSB 2
1100 
1101 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_MSB 2
1102 
1103 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_WIDTH 1
1104 
1105 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET_MSK 0x00000004
1106 
1107 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_CLR_MSK 0xfffffffb
1108 
1109 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_RESET 0x0
1110 
1111 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
1112 
1113 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
1114 
1125 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_LSB 3
1126 
1127 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_MSB 3
1128 
1129 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_WIDTH 1
1130 
1131 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET_MSK 0x00000008
1132 
1133 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_CLR_MSK 0xfffffff7
1134 
1135 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_RESET 0x0
1136 
1137 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
1138 
1139 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
1140 
1151 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_LSB 4
1152 
1153 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_MSB 4
1154 
1155 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_WIDTH 1
1156 
1157 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET_MSK 0x00000010
1158 
1159 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_CLR_MSK 0xffffffef
1160 
1161 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_RESET 0x0
1162 
1163 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
1164 
1165 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
1166 
1177 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_LSB 5
1178 
1179 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_MSB 5
1180 
1181 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_WIDTH 1
1182 
1183 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET_MSK 0x00000020
1184 
1185 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_CLR_MSK 0xffffffdf
1186 
1187 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_RESET 0x0
1188 
1189 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
1190 
1191 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
1192 
1203 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_LSB 6
1204 
1205 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_MSB 6
1206 
1207 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_WIDTH 1
1208 
1209 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET_MSK 0x00000040
1210 
1211 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_CLR_MSK 0xffffffbf
1212 
1213 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_RESET 0x0
1214 
1215 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
1216 
1217 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
1218 
1229 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_LSB 7
1230 
1231 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_MSB 7
1232 
1233 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_WIDTH 1
1234 
1235 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET_MSK 0x00000080
1236 
1237 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_CLR_MSK 0xffffff7f
1238 
1239 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_RESET 0x0
1240 
1241 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
1242 
1243 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
1244 
1255 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_LSB 8
1256 
1257 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_MSB 8
1258 
1259 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_WIDTH 1
1260 
1261 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET_MSK 0x00000100
1262 
1263 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_CLR_MSK 0xfffffeff
1264 
1265 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_RESET 0x0
1266 
1267 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
1268 
1269 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
1270 
1281 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_LSB 9
1282 
1283 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_MSB 9
1284 
1285 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_WIDTH 1
1286 
1287 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET_MSK 0x00000200
1288 
1289 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_CLR_MSK 0xfffffdff
1290 
1291 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_RESET 0x0
1292 
1293 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
1294 
1295 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
1296 
1307 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_LSB 10
1308 
1309 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_MSB 10
1310 
1311 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_WIDTH 1
1312 
1313 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET_MSK 0x00000400
1314 
1315 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_CLR_MSK 0xfffffbff
1316 
1317 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_RESET 0x0
1318 
1319 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
1320 
1321 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
1322 
1333 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_LSB 11
1334 
1335 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_MSB 11
1336 
1337 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_WIDTH 1
1338 
1339 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET_MSK 0x00000800
1340 
1341 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_CLR_MSK 0xfffff7ff
1342 
1343 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_RESET 0x0
1344 
1345 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
1346 
1347 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC0_SET(value) (((value) << 11) & 0x00000800)
1348 
1359 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_LSB 12
1360 
1361 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_MSB 12
1362 
1363 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_WIDTH 1
1364 
1365 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET_MSK 0x00001000
1366 
1367 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_CLR_MSK 0xffffefff
1368 
1369 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_RESET 0x0
1370 
1371 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
1372 
1373 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC1_SET(value) (((value) << 12) & 0x00001000)
1374 
1385 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_LSB 13
1386 
1387 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_MSB 13
1388 
1389 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_WIDTH 1
1390 
1391 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET_MSK 0x00002000
1392 
1393 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_CLR_MSK 0xffffdfff
1394 
1395 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_RESET 0x0
1396 
1397 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
1398 
1399 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC2_SET(value) (((value) << 13) & 0x00002000)
1400 
1411 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_LSB 14
1412 
1413 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_MSB 14
1414 
1415 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_WIDTH 1
1416 
1417 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET_MSK 0x00004000
1418 
1419 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_CLR_MSK 0xffffbfff
1420 
1421 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_RESET 0x0
1422 
1423 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
1424 
1425 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_EMAC3_SET(value) (((value) << 14) & 0x00004000)
1426 
1437 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_LSB 15
1438 
1439 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_MSB 15
1440 
1441 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_WIDTH 1
1442 
1443 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET_MSK 0x00008000
1444 
1445 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_CLR_MSK 0xffff7fff
1446 
1447 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_RESET 0x0
1448 
1449 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_GET(value) (((value) & 0x00008000) >> 15)
1450 
1451 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_QSPI_SET(value) (((value) << 15) & 0x00008000)
1452 
1463 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_LSB 16
1464 
1465 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_MSB 16
1466 
1467 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_WIDTH 1
1468 
1469 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET_MSK 0x00010000
1470 
1471 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_CLR_MSK 0xfffeffff
1472 
1473 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_RESET 0x0
1474 
1475 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
1476 
1477 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SDMMC_SET(value) (((value) << 16) & 0x00010000)
1478 
1489 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_LSB 17
1490 
1491 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_MSB 17
1492 
1493 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_WIDTH 1
1494 
1495 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET_MSK 0x00020000
1496 
1497 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_CLR_MSK 0xfffdffff
1498 
1499 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_RESET 0x0
1500 
1501 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
1502 
1503 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO0_SET(value) (((value) << 17) & 0x00020000)
1504 
1515 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_LSB 18
1516 
1517 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_MSB 18
1518 
1519 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_WIDTH 1
1520 
1521 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET_MSK 0x00040000
1522 
1523 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_CLR_MSK 0xfffbffff
1524 
1525 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_RESET 0x0
1526 
1527 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
1528 
1529 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO1_SET(value) (((value) << 18) & 0x00040000)
1530 
1541 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_LSB 19
1542 
1543 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_MSB 19
1544 
1545 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_WIDTH 1
1546 
1547 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET_MSK 0x00080000
1548 
1549 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_CLR_MSK 0xfff7ffff
1550 
1551 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_RESET 0x0
1552 
1553 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
1554 
1555 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_GPIO2_SET(value) (((value) << 19) & 0x00080000)
1556 
1567 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_LSB 20
1568 
1569 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_MSB 20
1570 
1571 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_WIDTH 1
1572 
1573 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET_MSK 0x00100000
1574 
1575 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_CLR_MSK 0xffefffff
1576 
1577 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_RESET 0x0
1578 
1579 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_GET(value) (((value) & 0x00100000) >> 20)
1580 
1581 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C0_SET(value) (((value) << 20) & 0x00100000)
1582 
1593 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_LSB 21
1594 
1595 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_MSB 21
1596 
1597 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_WIDTH 1
1598 
1599 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET_MSK 0x00200000
1600 
1601 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_CLR_MSK 0xffdfffff
1602 
1603 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_RESET 0x0
1604 
1605 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_GET(value) (((value) & 0x00200000) >> 21)
1606 
1607 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C1_SET(value) (((value) << 21) & 0x00200000)
1608 
1619 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_LSB 22
1620 
1621 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_MSB 22
1622 
1623 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_WIDTH 1
1624 
1625 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET_MSK 0x00400000
1626 
1627 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_CLR_MSK 0xffbfffff
1628 
1629 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_RESET 0x0
1630 
1631 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_GET(value) (((value) & 0x00400000) >> 22)
1632 
1633 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C2_SET(value) (((value) << 22) & 0x00400000)
1634 
1645 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_LSB 23
1646 
1647 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_MSB 23
1648 
1649 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_WIDTH 1
1650 
1651 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET_MSK 0x00800000
1652 
1653 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_CLR_MSK 0xff7fffff
1654 
1655 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_RESET 0x0
1656 
1657 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_GET(value) (((value) & 0x00800000) >> 23)
1658 
1659 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C3_SET(value) (((value) << 23) & 0x00800000)
1660 
1671 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_LSB 24
1672 
1673 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_MSB 24
1674 
1675 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_WIDTH 1
1676 
1677 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET_MSK 0x01000000
1678 
1679 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_CLR_MSK 0xfeffffff
1680 
1681 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_RESET 0x0
1682 
1683 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_GET(value) (((value) & 0x01000000) >> 24)
1684 
1685 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_I2C4_SET(value) (((value) << 24) & 0x01000000)
1686 
1697 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_LSB 25
1698 
1699 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_MSB 25
1700 
1701 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_WIDTH 1
1702 
1703 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET_MSK 0x02000000
1704 
1705 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_CLR_MSK 0xfdffffff
1706 
1707 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_RESET 0x0
1708 
1709 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
1710 
1711 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
1712 
1723 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_LSB 26
1724 
1725 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_MSB 26
1726 
1727 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_WIDTH 1
1728 
1729 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET_MSK 0x04000000
1730 
1731 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_CLR_MSK 0xfbffffff
1732 
1733 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_RESET 0x0
1734 
1735 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
1736 
1737 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
1738 
1749 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_LSB 27
1750 
1751 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_MSB 27
1752 
1753 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_WIDTH 1
1754 
1755 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET_MSK 0x08000000
1756 
1757 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_CLR_MSK 0xf7ffffff
1758 
1759 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_RESET 0x0
1760 
1761 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_GET(value) (((value) & 0x08000000) >> 27)
1762 
1763 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART0_SET(value) (((value) << 27) & 0x08000000)
1764 
1775 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_LSB 28
1776 
1777 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_MSB 28
1778 
1779 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_WIDTH 1
1780 
1781 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET_MSK 0x10000000
1782 
1783 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_CLR_MSK 0xefffffff
1784 
1785 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_RESET 0x0
1786 
1787 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_GET(value) (((value) & 0x10000000) >> 28)
1788 
1789 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_UART1_SET(value) (((value) << 28) & 0x10000000)
1790 
1801 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_LSB 29
1802 
1803 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_MSB 29
1804 
1805 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_WIDTH 1
1806 
1807 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET_MSK 0x20000000
1808 
1809 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_CLR_MSK 0xdfffffff
1810 
1811 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_RESET 0x0
1812 
1813 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
1814 
1815 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_LWH2F_SET(value) (((value) << 29) & 0x20000000)
1816 
1827 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_LSB 30
1828 
1829 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_MSB 30
1830 
1831 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_WIDTH 1
1832 
1833 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET_MSK 0x40000000
1834 
1835 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_CLR_MSK 0xbfffffff
1836 
1837 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_RESET 0x0
1838 
1839 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_GET(value) (((value) & 0x40000000) >> 30)
1840 
1841 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_H2F_SET(value) (((value) << 30) & 0x40000000)
1842 
1843 #ifndef __ASSEMBLY__
1844 
1855 {
1856  uint32_t nand_register : 1;
1857  uint32_t nand_data : 1;
1858  uint32_t qspi_data : 1;
1859  uint32_t usb0_register : 1;
1860  uint32_t usb1_register : 1;
1861  uint32_t dma_nonsecure : 1;
1862  uint32_t dma_secure : 1;
1863  uint32_t spi_master0 : 1;
1864  uint32_t spi_master1 : 1;
1865  uint32_t spi_slave0 : 1;
1866  uint32_t spi_slave1 : 1;
1867  uint32_t emac0 : 1;
1868  uint32_t emac1 : 1;
1869  uint32_t emac2 : 1;
1870  uint32_t emac3 : 1;
1871  uint32_t qspi : 1;
1872  uint32_t sdmmc : 1;
1873  uint32_t gpio0 : 1;
1874  uint32_t gpio1 : 1;
1875  uint32_t gpio2 : 1;
1876  uint32_t i2c0 : 1;
1877  uint32_t i2c1 : 1;
1878  uint32_t i2c2 : 1;
1879  uint32_t i2c3 : 1;
1880  uint32_t i2c4 : 1;
1881  uint32_t sp_timer0 : 1;
1882  uint32_t sp_timer1 : 1;
1883  uint32_t uart0 : 1;
1884  uint32_t uart1 : 1;
1885  uint32_t lwsoc2fpga : 1;
1886  uint32_t soc2fpga : 1;
1887  uint32_t : 1;
1888 };
1889 
1892 #endif /* __ASSEMBLY__ */
1893 
1895 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_RESET 0x00000000
1896 
1897 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SET_OFST 0x4
1898 
1952 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_LSB 0
1953 
1954 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_MSB 0
1955 
1956 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_WIDTH 1
1957 
1958 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET_MSK 0x00000001
1959 
1960 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_CLR_MSK 0xfffffffe
1961 
1962 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_RESET 0x0
1963 
1964 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_GET(value) (((value) & 0x00000001) >> 0)
1965 
1966 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_REG_SET(value) (((value) << 0) & 0x00000001)
1967 
1978 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_LSB 1
1979 
1980 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_MSB 1
1981 
1982 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_WIDTH 1
1983 
1984 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET_MSK 0x00000002
1985 
1986 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_CLR_MSK 0xfffffffd
1987 
1988 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_RESET 0x0
1989 
1990 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_GET(value) (((value) & 0x00000002) >> 1)
1991 
1992 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_NAND_DATA_SET(value) (((value) << 1) & 0x00000002)
1993 
2004 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_LSB 2
2005 
2006 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_MSB 2
2007 
2008 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_WIDTH 1
2009 
2010 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET_MSK 0x00000004
2011 
2012 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_CLR_MSK 0xfffffffb
2013 
2014 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_RESET 0x0
2015 
2016 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_GET(value) (((value) & 0x00000004) >> 2)
2017 
2018 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_DATA_SET(value) (((value) << 2) & 0x00000004)
2019 
2030 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_LSB 3
2031 
2032 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_MSB 3
2033 
2034 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_WIDTH 1
2035 
2036 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET_MSK 0x00000008
2037 
2038 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_CLR_MSK 0xfffffff7
2039 
2040 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_RESET 0x0
2041 
2042 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_GET(value) (((value) & 0x00000008) >> 3)
2043 
2044 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB0_REG_SET(value) (((value) << 3) & 0x00000008)
2045 
2056 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_LSB 4
2057 
2058 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_MSB 4
2059 
2060 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_WIDTH 1
2061 
2062 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET_MSK 0x00000010
2063 
2064 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_CLR_MSK 0xffffffef
2065 
2066 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_RESET 0x0
2067 
2068 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_GET(value) (((value) & 0x00000010) >> 4)
2069 
2070 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_USB1_REG_SET(value) (((value) << 4) & 0x00000010)
2071 
2082 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_LSB 5
2083 
2084 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_MSB 5
2085 
2086 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_WIDTH 1
2087 
2088 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET_MSK 0x00000020
2089 
2090 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_CLR_MSK 0xffffffdf
2091 
2092 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_RESET 0x0
2093 
2094 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_GET(value) (((value) & 0x00000020) >> 5)
2095 
2096 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_NONSECURE_SET(value) (((value) << 5) & 0x00000020)
2097 
2108 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_LSB 6
2109 
2110 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_MSB 6
2111 
2112 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_WIDTH 1
2113 
2114 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET_MSK 0x00000040
2115 
2116 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_CLR_MSK 0xffffffbf
2117 
2118 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_RESET 0x0
2119 
2120 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_GET(value) (((value) & 0x00000040) >> 6)
2121 
2122 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_DMA_SECURE_SET(value) (((value) << 6) & 0x00000040)
2123 
2134 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_LSB 7
2135 
2136 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_MSB 7
2137 
2138 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_WIDTH 1
2139 
2140 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET_MSK 0x00000080
2141 
2142 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_CLR_MSK 0xffffff7f
2143 
2144 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_RESET 0x0
2145 
2146 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_GET(value) (((value) & 0x00000080) >> 7)
2147 
2148 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST0_SET(value) (((value) << 7) & 0x00000080)
2149 
2160 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_LSB 8
2161 
2162 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_MSB 8
2163 
2164 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_WIDTH 1
2165 
2166 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET_MSK 0x00000100
2167 
2168 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_CLR_MSK 0xfffffeff
2169 
2170 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_RESET 0x0
2171 
2172 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_GET(value) (((value) & 0x00000100) >> 8)
2173 
2174 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_MST1_SET(value) (((value) << 8) & 0x00000100)
2175 
2186 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_LSB 9
2187 
2188 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_MSB 9
2189 
2190 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_WIDTH 1
2191 
2192 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET_MSK 0x00000200
2193 
2194 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_CLR_MSK 0xfffffdff
2195 
2196 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_RESET 0x0
2197 
2198 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_GET(value) (((value) & 0x00000200) >> 9)
2199 
2200 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV0_SET(value) (((value) << 9) & 0x00000200)
2201 
2212 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_LSB 10
2213 
2214 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_MSB 10
2215 
2216 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_WIDTH 1
2217 
2218 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET_MSK 0x00000400
2219 
2220 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_CLR_MSK 0xfffffbff
2221 
2222 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_RESET 0x0
2223 
2224 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_GET(value) (((value) & 0x00000400) >> 10)
2225 
2226 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SPI_SLV1_SET(value) (((value) << 10) & 0x00000400)
2227 
2238 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_LSB 11
2239 
2240 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_MSB 11
2241 
2242 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_WIDTH 1
2243 
2244 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET_MSK 0x00000800
2245 
2246 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_CLR_MSK 0xfffff7ff
2247 
2248 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_RESET 0x0
2249 
2250 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_GET(value) (((value) & 0x00000800) >> 11)
2251 
2252 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC0_SET(value) (((value) << 11) & 0x00000800)
2253 
2264 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_LSB 12
2265 
2266 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_MSB 12
2267 
2268 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_WIDTH 1
2269 
2270 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET_MSK 0x00001000
2271 
2272 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_CLR_MSK 0xffffefff
2273 
2274 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_RESET 0x0
2275 
2276 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_GET(value) (((value) & 0x00001000) >> 12)
2277 
2278 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC1_SET(value) (((value) << 12) & 0x00001000)
2279 
2290 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_LSB 13
2291 
2292 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_MSB 13
2293 
2294 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_WIDTH 1
2295 
2296 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET_MSK 0x00002000
2297 
2298 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_CLR_MSK 0xffffdfff
2299 
2300 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_RESET 0x0
2301 
2302 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_GET(value) (((value) & 0x00002000) >> 13)
2303 
2304 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC2_SET(value) (((value) << 13) & 0x00002000)
2305 
2316 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_LSB 14
2317 
2318 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_MSB 14
2319 
2320 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_WIDTH 1
2321 
2322 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET_MSK 0x00004000
2323 
2324 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_CLR_MSK 0xffffbfff
2325 
2326 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_RESET 0x0
2327 
2328 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_GET(value) (((value) & 0x00004000) >> 14)
2329 
2330 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_EMAC3_SET(value) (((value) << 14) & 0x00004000)
2331 
2342 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_LSB 15
2343 
2344 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_MSB 15
2345 
2346 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_WIDTH 1
2347 
2348 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET_MSK 0x00008000
2349 
2350 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_CLR_MSK 0xffff7fff
2351 
2352 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_RESET 0x0
2353 
2354 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_GET(value) (((value) & 0x00008000) >> 15)
2355 
2356 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_QSPI_SET(value) (((value) << 15) & 0x00008000)
2357 
2368 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_LSB 16
2369 
2370 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_MSB 16
2371 
2372 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_WIDTH 1
2373 
2374 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET_MSK 0x00010000
2375 
2376 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_CLR_MSK 0xfffeffff
2377 
2378 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_RESET 0x0
2379 
2380 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_GET(value) (((value) & 0x00010000) >> 16)
2381 
2382 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SDMMC_SET(value) (((value) << 16) & 0x00010000)
2383 
2394 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_LSB 17
2395 
2396 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_MSB 17
2397 
2398 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_WIDTH 1
2399 
2400 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET_MSK 0x00020000
2401 
2402 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_CLR_MSK 0xfffdffff
2403 
2404 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_RESET 0x0
2405 
2406 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_GET(value) (((value) & 0x00020000) >> 17)
2407 
2408 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO0_SET(value) (((value) << 17) & 0x00020000)
2409 
2420 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_LSB 18
2421 
2422 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_MSB 18
2423 
2424 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_WIDTH 1
2425 
2426 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET_MSK 0x00040000
2427 
2428 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_CLR_MSK 0xfffbffff
2429 
2430 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_RESET 0x0
2431 
2432 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_GET(value) (((value) & 0x00040000) >> 18)
2433 
2434 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO1_SET(value) (((value) << 18) & 0x00040000)
2435 
2446 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_LSB 19
2447 
2448 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_MSB 19
2449 
2450 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_WIDTH 1
2451 
2452 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET_MSK 0x00080000
2453 
2454 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_CLR_MSK 0xfff7ffff
2455 
2456 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_RESET 0x0
2457 
2458 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_GET(value) (((value) & 0x00080000) >> 19)
2459 
2460 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_GPIO2_SET(value) (((value) << 19) & 0x00080000)
2461 
2472 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_LSB 20
2473 
2474 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_MSB 20
2475 
2476 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_WIDTH 1
2477 
2478 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET_MSK 0x00100000
2479 
2480 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_CLR_MSK 0xffefffff
2481 
2482 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_RESET 0x0
2483 
2484 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_GET(value) (((value) & 0x00100000) >> 20)
2485 
2486 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C0_SET(value) (((value) << 20) & 0x00100000)
2487 
2498 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_LSB 21
2499 
2500 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_MSB 21
2501 
2502 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_WIDTH 1
2503 
2504 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET_MSK 0x00200000
2505 
2506 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_CLR_MSK 0xffdfffff
2507 
2508 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_RESET 0x0
2509 
2510 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_GET(value) (((value) & 0x00200000) >> 21)
2511 
2512 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C1_SET(value) (((value) << 21) & 0x00200000)
2513 
2524 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_LSB 22
2525 
2526 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_MSB 22
2527 
2528 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_WIDTH 1
2529 
2530 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET_MSK 0x00400000
2531 
2532 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_CLR_MSK 0xffbfffff
2533 
2534 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_RESET 0x0
2535 
2536 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_GET(value) (((value) & 0x00400000) >> 22)
2537 
2538 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C2_SET(value) (((value) << 22) & 0x00400000)
2539 
2550 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_LSB 23
2551 
2552 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_MSB 23
2553 
2554 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_WIDTH 1
2555 
2556 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET_MSK 0x00800000
2557 
2558 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_CLR_MSK 0xff7fffff
2559 
2560 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_RESET 0x0
2561 
2562 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_GET(value) (((value) & 0x00800000) >> 23)
2563 
2564 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C3_SET(value) (((value) << 23) & 0x00800000)
2565 
2576 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_LSB 24
2577 
2578 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_MSB 24
2579 
2580 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_WIDTH 1
2581 
2582 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET_MSK 0x01000000
2583 
2584 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_CLR_MSK 0xfeffffff
2585 
2586 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_RESET 0x0
2587 
2588 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_GET(value) (((value) & 0x01000000) >> 24)
2589 
2590 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_I2C4_SET(value) (((value) << 24) & 0x01000000)
2591 
2602 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_LSB 25
2603 
2604 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_MSB 25
2605 
2606 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_WIDTH 1
2607 
2608 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET_MSK 0x02000000
2609 
2610 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_CLR_MSK 0xfdffffff
2611 
2612 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_RESET 0x0
2613 
2614 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_GET(value) (((value) & 0x02000000) >> 25)
2615 
2616 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR0_SET(value) (((value) << 25) & 0x02000000)
2617 
2628 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_LSB 26
2629 
2630 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_MSB 26
2631 
2632 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_WIDTH 1
2633 
2634 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET_MSK 0x04000000
2635 
2636 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_CLR_MSK 0xfbffffff
2637 
2638 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_RESET 0x0
2639 
2640 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_GET(value) (((value) & 0x04000000) >> 26)
2641 
2642 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_SP_TMR1_SET(value) (((value) << 26) & 0x04000000)
2643 
2654 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_LSB 27
2655 
2656 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_MSB 27
2657 
2658 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_WIDTH 1
2659 
2660 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET_MSK 0x08000000
2661 
2662 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_CLR_MSK 0xf7ffffff
2663 
2664 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_RESET 0x0
2665 
2666 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_GET(value) (((value) & 0x08000000) >> 27)
2667 
2668 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART0_SET(value) (((value) << 27) & 0x08000000)
2669 
2680 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_LSB 28
2681 
2682 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_MSB 28
2683 
2684 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_WIDTH 1
2685 
2686 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET_MSK 0x10000000
2687 
2688 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_CLR_MSK 0xefffffff
2689 
2690 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_RESET 0x0
2691 
2692 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_GET(value) (((value) & 0x10000000) >> 28)
2693 
2694 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_UART1_SET(value) (((value) << 28) & 0x10000000)
2695 
2706 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_LSB 29
2707 
2708 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_MSB 29
2709 
2710 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_WIDTH 1
2711 
2712 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET_MSK 0x20000000
2713 
2714 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_CLR_MSK 0xdfffffff
2715 
2716 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_RESET 0x0
2717 
2718 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_GET(value) (((value) & 0x20000000) >> 29)
2719 
2720 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_LWH2F_SET(value) (((value) << 29) & 0x20000000)
2721 
2732 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_LSB 30
2733 
2734 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_MSB 30
2735 
2736 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_WIDTH 1
2737 
2738 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET_MSK 0x40000000
2739 
2740 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_CLR_MSK 0xbfffffff
2741 
2742 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_RESET 0x0
2743 
2744 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_GET(value) (((value) & 0x40000000) >> 30)
2745 
2746 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_H2F_SET(value) (((value) << 30) & 0x40000000)
2747 
2748 #ifndef __ASSEMBLY__
2749 
2760 {
2761  uint32_t nand_register : 1;
2762  uint32_t nand_data : 1;
2763  uint32_t qspi_data : 1;
2764  uint32_t usb0_register : 1;
2765  uint32_t usb1_register : 1;
2766  uint32_t dma_nonsecure : 1;
2767  uint32_t dma_secure : 1;
2768  uint32_t spi_master0 : 1;
2769  uint32_t spi_master1 : 1;
2770  uint32_t spi_slave0 : 1;
2771  uint32_t spi_slave1 : 1;
2772  uint32_t emac0 : 1;
2773  uint32_t emac1 : 1;
2774  uint32_t emac2 : 1;
2775  uint32_t emac3 : 1;
2776  uint32_t qspi : 1;
2777  uint32_t sdmmc : 1;
2778  uint32_t gpio0 : 1;
2779  uint32_t gpio1 : 1;
2780  uint32_t gpio2 : 1;
2781  uint32_t i2c0 : 1;
2782  uint32_t i2c1 : 1;
2783  uint32_t i2c2 : 1;
2784  uint32_t i2c3 : 1;
2785  uint32_t i2c4 : 1;
2786  uint32_t sp_timer0 : 1;
2787  uint32_t sp_timer1 : 1;
2788  uint32_t uart0 : 1;
2789  uint32_t uart1 : 1;
2790  uint32_t lwsoc2fpga : 1;
2791  uint32_t soc2fpga : 1;
2792  uint32_t : 1;
2793 };
2794 
2797 #endif /* __ASSEMBLY__ */
2798 
2800 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_RESET 0x00000000
2801 
2802 #define ALT_NOC_L4_PRIV_FLT_L4_PRIV_CLR_OFST 0x8
2803 
2804 #ifndef __ASSEMBLY__
2805 
2816 {
2820  volatile uint32_t _pad_0xc_0x100[61];
2821 };
2822 
2827 {
2828  volatile uint32_t l4_priv;
2829  volatile uint32_t l4_priv_set;
2830  volatile uint32_t l4_priv_clear;
2831  volatile uint32_t _pad_0xc_0x100[61];
2832 };
2833 
2836 #endif /* __ASSEMBLY__ */
2837 
2839 #ifdef __cplusplus
2840 }
2841 #endif /* __cplusplus */
2842 #endif /* __ALT_SOCAL_NOC_L4_PRIV_FLT_H__ */
2843