Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Lower Power Timing Register - lowpwrtiming

Description

This register controls the behavior of the low power logic in the controller.

Register Layout

Bits Access Reset Description
[15:0] RW Unknown Auto-power Down Cycles
[19:16] RW Unknown Clock Disable Delay Cycles
[31:20] ??? 0x0 UNDEFINED

Field : Auto-power Down Cycles - autopdcycles

The number of idle clock cycles after which the controller should place the memory into power-down mode.

Field Access Macros:

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB   0
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB   15
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH   16
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK   0x0000ffff
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK   0xffff0000
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET   0x0
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : Clock Disable Delay Cycles - clkdisablecycles

Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed.

Field Access Macros:

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB   16
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB   19
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH   4
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK   0x000f0000
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK   0xfff0ffff
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET   0x0
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET(value)   (((value) & 0x000f0000) >> 16)
 
#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET(value)   (((value) << 16) & 0x000f0000)
 

Data Structures

struct  ALT_SDR_CTL_LOWPWRTIMING_s
 

Macros

#define ALT_SDR_CTL_LOWPWRTIMING_OFST   0x14
 

Typedefs

typedef struct
ALT_SDR_CTL_LOWPWRTIMING_s 
ALT_SDR_CTL_LOWPWRTIMING_t
 

Data Structure Documentation

struct ALT_SDR_CTL_LOWPWRTIMING_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDR_CTL_LOWPWRTIMING.

Data Fields
uint32_t autopdcycles: 16 Auto-power Down Cycles
uint32_t clkdisablecycles: 4 Clock Disable Delay Cycles
uint32_t __pad0__: 12 UNDEFINED

Macro Definitions

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_WIDTH   16

The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET_MSK   0x0000ffff

The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_CLR_MSK   0xffff0000

The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_RESET   0x0

The reset value of the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field is UNKNOWN.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES field value from a register.

#define ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_SDR_CTL_LOWPWRTIMING_AUTOPDCYCLES register field value suitable for setting the register.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_MSB   19

The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_WIDTH   4

The width in bits of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET_MSK   0x000f0000

The mask used to set the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_CLR_MSK   0xfff0ffff

The mask used to clear the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_RESET   0x0

The reset value of the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field is UNKNOWN.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_GET (   value)    (((value) & 0x000f0000) >> 16)

Extracts the ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES field value from a register.

#define ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES_SET (   value)    (((value) << 16) & 0x000f0000)

Produces a ALT_SDR_CTL_LOWPWRTIMING_CLKDISCYCLES register field value suitable for setting the register.

#define ALT_SDR_CTL_LOWPWRTIMING_OFST   0x14

The byte offset of the ALT_SDR_CTL_LOWPWRTIMING register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDR_CTL_LOWPWRTIMING.