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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This is a constant read-only register that contains encoded information about the component's parameter settings.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | Always Enable |
[1] | R | 0x0 | Default Mode |
[2] | R | 0x1 | Dual Timeout Period |
[3] | R | 0x0 | Hardcode Response Mode |
[4] | R | 0x1 | Hardcode Reset Pulse Length |
[5] | R | 0x0 | Hardcode Timeout Period |
[6] | R | 0x1 | Use Pre-defined (Fixed) Timeout Values |
[7] | R | 0x0 | Include Pause Input |
[9:8] | R | 0x2 | APB Data Width |
[12:10] | R | 0x0 | Default Reset Pulse Length |
[15:13] | ??? | 0x0 | UNDEFINED |
[19:16] | R | 0xf | Default Timeout Period |
[23:20] | R | 0xf | Default Initial Timeout Period |
[28:24] | R | 0x10 | Counter Width in Bits |
[31:29] | ??? | 0x0 | UNDEFINED |
Field : Always Enable - cp_wdt_always_en | |||||||
Specifies whether watchdog starts after reset or not. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB 0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB 0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH 1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK 0x00000001 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET(value) (((value) & 0x00000001) >> 0) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET(value) (((value) << 0) & 0x00000001) | ||||||
Field : Default Mode - cp_wdt_dflt_rmod | ||||||||||
Specifies default output response mode after reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB 1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB 1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH 1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK 0x00000002 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET 0x0 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Dual Timeout Period - cp_wdt_dual_top | |||||||
Specifies whether a second timeout period that is used for initialization prior to the first kick is present or not. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB 2 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB 2 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH 1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK 0x00000004 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK 0xfffffffb | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET 0x1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET(value) (((value) & 0x00000004) >> 2) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET(value) (((value) << 2) & 0x00000004) | ||||||
Field : Hardcode Response Mode - cp_wdt_hc_rmod | |||||||
Specifies if response mode (when counter reaches 0) is programmable or hardcoded. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB 3 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB 3 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH 1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK 0x00000008 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK 0xfffffff7 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET(value) (((value) & 0x00000008) >> 3) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET(value) (((value) << 3) & 0x00000008) | ||||||
Field : Hardcode Reset Pulse Length - cp_wdt_hc_rpl | |||||||
Specifies if the reset pulse length is programmable or hardcoded. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB 4 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB 4 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH 1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK 0x00000010 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK 0xffffffef | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET 0x1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET(value) (((value) & 0x00000010) >> 4) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET(value) (((value) << 4) & 0x00000010) | ||||||
Field : Hardcode Timeout Period - cp_wdt_hc_top | |||||||
Specifies if the timeout period is programmable or hardcoded. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB 5 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB 5 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH 1 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK 0x00000020 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK 0xffffffdf | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET(value) (((value) & 0x00000020) >> 5) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET(value) (((value) << 5) & 0x00000020) | ||||||
Field : Use Pre-defined (Fixed) Timeout Values - cp_wdt_use_fix_top | ||||||||||
Specifies if the watchdog uses the pre-defined timeout values or if these were overriden with customer values when the watchdog was configured. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB 6 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB 6 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH 1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK 0x00000040 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET 0x1 | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : Include Pause Input - cp_wdt_pause | |
Should specify if the pause input is included or not. However, this field is always hardwired to 0 so you can't figure this out by reading this field. The pause input is included and can be used to pause the watchdog when the MPU is in debug mode. Field Access Macros: | |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB 7 |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB 7 |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH 1 |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK 0x00000080 |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK 0xffffff7f |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET 0x0 |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET(value) (((value) << 7) & 0x00000080) |
Field : APB Data Width - cp_wdt_apb_data_width | |||||||
APB Bus Width Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB 8 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB 9 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH 2 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK 0x00000300 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK 0xfffffcff | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET 0x2 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET(value) (((value) & 0x00000300) >> 8) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET(value) (((value) << 8) & 0x00000300) | ||||||
Field : Default Reset Pulse Length - cp_wdt_dflt_rpl | |||||||
Specifies the reset pulse length in cycles. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB 10 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB 12 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH 3 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK 0x00001c00 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET 0x0 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET(value) (((value) & 0x00001c00) >> 10) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET(value) (((value) << 10) & 0x00001c00) | ||||||
Field : Default Timeout Period - cp_wdt_dflt_top | |||||||
Specifies the timeout period that is available directly after reset. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB 16 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB 19 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH 4 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK 0x000f0000 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET 0xf | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET(value) (((value) & 0x000f0000) >> 16) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET(value) (((value) << 16) & 0x000f0000) | ||||||
Field : Default Initial Timeout Period - cp_wdt_dflt_top_init | |||||||
Specifies the initial timeout period that is available directly after reset. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB 20 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB 23 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH 4 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET 0xf | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET(value) (((value) & 0x00f00000) >> 20) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET(value) (((value) << 20) & 0x00f00000) | ||||||
Field : Counter Width in Bits - cp_wdt_cnt_width | |||||||
Width of counter in bits less 16. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB 24 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB 28 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH 5 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK 0x1f000000 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET 0x10 | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET(value) (((value) & 0x1f000000) >> 24) | ||||||
#define | ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET(value) (((value) << 24) & 0x1f000000) | ||||||
Data Structures | |
struct | ALT_L4WD_COMP_PARAM_1_s |
Macros | |
#define | ALT_L4WD_COMP_PARAM_1_OFST 0xf4 |
#define | ALT_L4WD_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST)) |
Typedefs | |
typedef struct ALT_L4WD_COMP_PARAM_1_s | ALT_L4WD_COMP_PARAM_1_t |
struct ALT_L4WD_COMP_PARAM_1_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_L4WD_COMP_PARAM_1.
Data Fields | ||
---|---|---|
const uint32_t | cp_wdt_always_en: 1 | Always Enable |
const uint32_t | cp_wdt_dflt_rmod: 1 | Default Mode |
const uint32_t | cp_wdt_dual_top: 1 | Dual Timeout Period |
const uint32_t | cp_wdt_hc_rmod: 1 | Hardcode Response Mode |
const uint32_t | cp_wdt_hc_rpl: 1 | Hardcode Reset Pulse Length |
const uint32_t | cp_wdt_hc_top: 1 | Hardcode Timeout Period |
const uint32_t | cp_wdt_use_fix_top: 1 | Use Pre-defined (Fixed) Timeout Values |
const uint32_t | cp_wdt_pause: 1 | Include Pause Input |
const uint32_t | cp_wdt_apb_data_width: 2 | APB Data Width |
const uint32_t | cp_wdt_dflt_rpl: 3 | Default Reset Pulse Length |
uint32_t | __pad0__: 3 | UNDEFINED |
const uint32_t | cp_wdt_dflt_top: 4 | Default Timeout Period |
const uint32_t | cp_wdt_dflt_top_init: 4 | Default Initial Timeout Period |
const uint32_t | cp_wdt_cnt_width: 5 | Counter Width in Bits |
uint32_t | __pad1__: 3 | UNDEFINED |
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_E_DISD 0x0 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN
Watchdog disabled on reset
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_ALWAYS_EN register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_E_RSTREQ 0x0 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD
Generate a warm reset request (don't generate an interrupt first)
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET_MSK 0x00000002 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RMOD register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_E_DUALTOP 0x1 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP
Second timeout period is present
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET_MSK 0x00000004 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_RESET 0x1 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DUAL_TOP register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_E_PGML 0x0 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD
Output response mode is programmable.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET_MSK 0x00000008 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RMOD register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_E_HARDCODED 0x1 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL
Reset pulse length is hardcoded.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET_MSK 0x00000010 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_CLR_MSK 0xffffffef |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_RESET 0x1 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_RPL register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_E_PGML 0x0 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP
Timeout period is programmable.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET_MSK 0x00000020 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_HC_TOP register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_E_PREDEFINED 0x1 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP
Use pre-defined (fixed) timeout values (range from 2**16 to 2**31)
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET_MSK 0x00000040 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_RESET 0x1 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_USE_FIX_TOP register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_WIDTH 1 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET_MSK 0x00000080 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_PAUSE register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH
APB Data Width is 32 Bits
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_WIDTH 2 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET_MSK 0x00000300 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_RESET 0x2 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_APB_DATA_WIDTH register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_E_PULSE2CYCLES 0x0 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL
Reset pulse length of 2 cycles.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_WIDTH 3 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET_MSK 0x00001c00 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_CLR_MSK 0xffffe3ff |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_RESET 0x0 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_GET | ( | value | ) | (((value) & 0x00001c00) >> 10) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL_SET | ( | value | ) | (((value) << 10) & 0x00001c00) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_RPL register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_E_TMO15 0xf |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP
Timeout period is 15 (2**31 cycles).
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_WIDTH 4 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET_MSK 0x000f0000 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_CLR_MSK 0xfff0ffff |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_RESET 0xf |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_GET | ( | value | ) | (((value) & 0x000f0000) >> 16) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_SET | ( | value | ) | (((value) << 16) & 0x000f0000) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_E_TMO15 0xf |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT
Initial timeout period is 15 (2**31 cycles).
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_WIDTH 4 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET_MSK 0x00f00000 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_CLR_MSK 0xff0fffff |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_RESET 0xf |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_GET | ( | value | ) | (((value) & 0x00f00000) >> 20) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT_SET | ( | value | ) | (((value) << 20) & 0x00f00000) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_DFLT_TOP_INIT register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_E_WIDTH32BITS 0x10 |
Enumerated value for register field ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH
Counter width is 32 bits
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_WIDTH 5 |
The width in bits of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET_MSK 0x1f000000 |
The mask used to set the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_CLR_MSK 0xe0ffffff |
The mask used to clear the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_RESET 0x10 |
The reset value of the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_GET | ( | value | ) | (((value) & 0x1f000000) >> 24) |
Extracts the ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH field value from a register.
#define ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH_SET | ( | value | ) | (((value) << 24) & 0x1f000000) |
Produces a ALT_L4WD_COMP_PARAM_1_CP_WDT_CNT_WIDTH register field value suitable for setting the register.
#define ALT_L4WD_COMP_PARAM_1_OFST 0xf4 |
The byte offset of the ALT_L4WD_COMP_PARAM_1 register from the beginning of the component.
#define ALT_L4WD_COMP_PARAM_1_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_COMP_PARAM_1_OFST)) |
The address of the ALT_L4WD_COMP_PARAM_1 register.
typedef struct ALT_L4WD_COMP_PARAM_1_s ALT_L4WD_COMP_PARAM_1_t |
The typedef declaration for register ALT_L4WD_COMP_PARAM_1.