Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gmacgrp_lpi_timers_control

Description

Register 13 (LPI Timers Control Register)

The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission. This register is present only when you select the Energy Efficient Ethernet feature during core configuration.

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT
[25:16] RW 0x3e8 ALT_EMAC_GMAC_LPI_TMRS_CTL_LST
[31:26] R 0x0 ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26

Field : twt

LPI TW Timer

This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this timer.

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB   0
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB   15
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH   16
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK   0x0000ffff
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK   0xffff0000
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : lst

LPI LS Timer

This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is set unless the LPI LS Timer reaches the programmed terminal count. The default value of the LPI LS Timer is 1000 (1 sec) as defined in the IEEE standard.

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB   16
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB   25
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH   10
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK   0x03ff0000
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK   0xfc00ffff
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET   0x3e8
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET(value)   (((value) & 0x03ff0000) >> 16)
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET(value)   (((value) << 16) & 0x03ff0000)
 

Field : reserved_31_26

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_LSB   26
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_MSB   31
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_WIDTH   6
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET_MSK   0xfc000000
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_CLR_MSK   0x03ffffff
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_RESET   0x0
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_GET(value)   (((value) & 0xfc000000) >> 26)
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET(value)   (((value) << 26) & 0xfc000000)
 

Data Structures

struct  ALT_EMAC_GMAC_LPI_TMRS_CTL_s
 

Macros

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RESET   0x03e80000
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST   0x34
 
#define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_LPI_TMRS_CTL_s 
ALT_EMAC_GMAC_LPI_TMRS_CTL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_LPI_TMRS_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL.

Data Fields
uint32_t twt: 16 ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT
uint32_t lst: 10 ALT_EMAC_GMAC_LPI_TMRS_CTL_LST
const uint32_t reserved_31_26: 6 ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26

Macro Definitions

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_WIDTH   16

The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET_MSK   0x0000ffff

The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_CLR_MSK   0xffff0000

The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT field value from a register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_TWT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_WIDTH   10

The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET_MSK   0x03ff0000

The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_CLR_MSK   0xfc00ffff

The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_RESET   0x3e8

The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_GET (   value)    (((value) & 0x03ff0000) >> 16)

Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_LST field value from a register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_LST_SET (   value)    (((value) << 16) & 0x03ff0000)

Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_LST register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_LSB   26

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_WIDTH   6

The width in bits of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET_MSK   0xfc000000

The mask used to set the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_CLR_MSK   0x03ffffff

The mask used to clear the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_RESET   0x0

The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_GET (   value)    (((value) & 0xfc000000) >> 26)

Extracts the ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 field value from a register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26_SET (   value)    (((value) << 26) & 0xfc000000)

Produces a ALT_EMAC_GMAC_LPI_TMRS_CTL_RSVD_31_26 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_RESET   0x03e80000

The reset value of the ALT_EMAC_GMAC_LPI_TMRS_CTL register.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST   0x34

The byte offset of the ALT_EMAC_GMAC_LPI_TMRS_CTL register from the beginning of the component.

#define ALT_EMAC_GMAC_LPI_TMRS_CTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_LPI_TMRS_CTL_OFST))

The address of the ALT_EMAC_GMAC_LPI_TMRS_CTL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_LPI_TMRS_CTL.