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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The AXI Bus Mode Register controls the behavior of the AXI master. It is mainly used to control the burst splitting and the number of outstanding requests.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x1 | AXI Undefined Burst Length |
[1] | RW | 0x0 | AXI Burst Length 4 |
[2] | RW | 0x0 | AXI Burst Length 8 |
[3] | RW | 0x0 | AXI Burst Length 16 |
[11:4] | ??? | 0x0 | UNDEFINED |
[12] | R | 0x0 | Address-Aligned Beats |
[13] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE |
[15:14] | ??? | 0x0 | UNDEFINED |
[19:16] | RW | 0x1 | AXI Maximum Read OutStanding Request Limit |
[23:20] | RW | 0x1 | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT |
[29:24] | ??? | 0x0 | UNDEFINED |
[30] | RW | 0x0 | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM |
[31] | RW | 0x0 | Enable Low Power Interface (LPI) |
Field : AXI Undefined Burst Length - undefined | ||||||||||
This bit is read-only bit and indicates the complement (invert) value of Bit 16 (FB) in Register 0 (Bus Mode Register[16]).
Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB 0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB 0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK 0x00000001 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : AXI Burst Length 4 - blen4 | ||||||||||
When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 4 on the AXI Master interface. Setting this bit has no effect when UNDEFINED is set to 1. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK 0x00000002 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : AXI Burst Length 8 - blen8 | ||||||||||
When this bit is set to 1, the GMAC-AXI is allowed to select a burst length of 8 on the AXI Master interface. Setting this bit has no effect when UNDEFINED is set to 1. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB 2 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB 2 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK 0x00000004 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : AXI Burst Length 16 - blen16 | ||||||||||
When this bit is set to 1 or UNDEFINED is set to 1, the GMAC-AXI is allowed to select a burst length of 16 on the AXI Master interface. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB 3 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB 3 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK 0x00000008 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Address-Aligned Beats - axi_aal | ||||||||||
This bit is read-only bit and reflects the Bit 25 (AAL) of Register 0 (Bus Mode Register). When this bit is set to 1, the GMAC-AXI performs address-aligned burst transfers on both read and write channels. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB 12 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB 12 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK 0x00001000 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK 0xffffefff | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET(value) (((value) & 0x00001000) >> 12) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET(value) (((value) << 12) & 0x00001000) | |||||||||
Field : onekbbe | ||||||||||
1 KB Boundary Crossing Enable for the GMAC-AXI Master When set, the GMAC-AXI Master performs burst transfers that do not cross 1 KB boundary. When reset, the GMAC-AXI Master performs burst transfers that do not cross 4 KB boundary. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB 13 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB 13 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK 0x00002000 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK 0xffffdfff | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET(value) (((value) & 0x00002000) >> 13) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET(value) (((value) << 13) & 0x00002000) | |||||||||
Field : AXI Maximum Read OutStanding Request Limit - rd_osr_lmt | |
This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT+1 Field Access Macros: | |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB 16 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB 19 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH 4 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK 0x000f0000 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK 0xfff0ffff |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET 0x1 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET(value) (((value) & 0x000f0000) >> 16) |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET(value) (((value) << 16) & 0x000f0000) |
Field : wr_osr_lmt | |
AXI Maximum Write OutStanding Request Limit Field Access Macros: | |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB 20 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB 23 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH 4 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK 0x00f00000 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK 0xff0fffff |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET 0x1 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET(value) (((value) & 0x00f00000) >> 20) |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET(value) (((value) << 20) & 0x00f00000) |
Field : lpi_xit_frm | ||||||||||
When set to 1, this bit enables the GMAC-AXI to come out of the LPI mode only when the Magic Packet or Remote Wake Up Packet is received. When set to 0, this bit enables the GMAC-AXI to come out of LPI mode when any frame is received. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB 30 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB 30 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK 0x40000000 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK 0xbfffffff | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET(value) (((value) & 0x40000000) >> 30) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET(value) (((value) << 30) & 0x40000000) | |||||||||
Field : Enable Low Power Interface (LPI) - en_lpi | ||||||||||
When set to 1, this bit enables the LPI mode supported by the AXI master and accepts the LPI request from the AXI System Clock controller. When set to 0, this bit disables the LPI mode and always denies the LPI request from the AXI System Clock controller. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END 0x1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB 31 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB 31 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH 1 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK 0x80000000 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK 0x7fffffff | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET 0x0 | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET(value) (((value) & 0x80000000) >> 31) | |||||||||
#define | ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET(value) (((value) << 31) & 0x80000000) | |||||||||
Data Structures | |
struct | ALT_EMAC_DMA_AXI_BUS_MOD_s |
Macros | |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_OFST 0x28 |
#define | ALT_EMAC_DMA_AXI_BUS_MOD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_DMA_AXI_BUS_MOD_s | ALT_EMAC_DMA_AXI_BUS_MOD_t |
struct ALT_EMAC_DMA_AXI_BUS_MOD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_DMA_AXI_BUS_MOD.
Data Fields | ||
---|---|---|
const uint32_t | undefined: 1 | AXI Undefined Burst Length |
uint32_t | blen4: 1 | AXI Burst Length 4 |
uint32_t | blen8: 1 | AXI Burst Length 8 |
uint32_t | blen16: 1 | AXI Burst Length 16 |
uint32_t | __pad0__: 8 | UNDEFINED |
const uint32_t | axi_aal: 1 | Address-Aligned Beats |
uint32_t | onekbbe: 1 | ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE |
uint32_t | __pad1__: 2 | UNDEFINED |
uint32_t | rd_osr_lmt: 4 | AXI Maximum Read OutStanding Request Limit |
uint32_t | wr_osr_lmt: 4 | ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT |
uint32_t | __pad2__: 6 | UNDEFINED |
uint32_t | lpi_xit_frm: 1 | ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM |
uint32_t | en_lpi: 1 | Enable Low Power Interface (LPI) |
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
Fixed Burst Lengths 4 to 32
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED
Any Burst Length up to max
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_UNDEFINED register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
AXI No Fixed Busrts
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4
AXI Fixed Burst BLEN = 4
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN4 register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
AXI No Fixed Busrts
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8
AXI Fixed Burst BLEN = 8
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN8 register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
AXI No Fixed Busrts
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16
AXI Fixed Burst BLEN = 16
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_BLEN16 register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
No Address-Alignment Bursts
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL
Address-Alignmnet Bursts
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET_MSK 0x00001000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_CLR_MSK 0xffffefff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_AXI_AAL register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_FOUR_K_BOUNDARY 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
4K boundary
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_E_ONE_K_BOUNDARY 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE
1K boundary
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_ONEKBBE register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_WIDTH 4 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET_MSK 0x000f0000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_CLR_MSK 0xfff0ffff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_GET | ( | value | ) | (((value) & 0x000f0000) >> 16) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT_SET | ( | value | ) | (((value) << 16) & 0x000f0000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_RD_OSR_LMT register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_WIDTH 4 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET_MSK 0x00f00000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_CLR_MSK 0xff0fffff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_RESET 0x1 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_GET | ( | value | ) | (((value) & 0x00f00000) >> 20) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT_SET | ( | value | ) | (((value) << 20) & 0x00f00000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_WR_OSR_LMT register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
Do Not exit LPI Mode with Magic Packet
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM
Exit LPI Mode with Magic Packet
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_LSB 30 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET_MSK 0x40000000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_CLR_MSK 0xbfffffff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_GET | ( | value | ) | (((value) & 0x40000000) >> 30) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM_SET | ( | value | ) | (((value) << 30) & 0x40000000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_LPI_XIT_FRM register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
Disable LPI Mode
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_E_END 0x1 |
Enumerated value for register field ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI
Enable LPI Mode
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_WIDTH 1 |
The width in bits of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET_MSK 0x80000000 |
The mask used to set the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_RESET 0x0 |
The reset value of the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI field value from a register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_EMAC_DMA_AXI_BUS_MOD_EN_LPI register field value suitable for setting the register.
#define ALT_EMAC_DMA_AXI_BUS_MOD_OFST 0x28 |
The byte offset of the ALT_EMAC_DMA_AXI_BUS_MOD register from the beginning of the component.
#define ALT_EMAC_DMA_AXI_BUS_MOD_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_AXI_BUS_MOD_OFST)) |
The address of the ALT_EMAC_DMA_AXI_BUS_MOD register.
typedef struct ALT_EMAC_DMA_AXI_BUS_MOD_s ALT_EMAC_DMA_AXI_BUS_MOD_t |
The typedef declaration for register ALT_EMAC_DMA_AXI_BUS_MOD.