![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Base and Limit definition for HPS Region 4
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[15:0] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE |
[31:16] | RW | 0x0 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT |
Field : base | |
Base defines the 16 bit MSB of the address field. Remaining LSB field is all zeros. Region start address is {base, 16'h000} Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET(value) (((value) & 0x0000ffff) >> 0) |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET(value) (((value) << 0) & 0x0000ffff) |
Field : limit | |
Limit defines the 16 bit MSB of the address field. Remaining LSB field is all ones. Region end address is {limit, 16'hFFF} Field Access Macros: | |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET(value) (((value) & 0xffff0000) >> 16) |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET(value) (((value) << 16) & 0xffff0000) |
Data Structures | |
struct | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s |
Macros | |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000 |
#define | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c |
Typedefs | |
typedef struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_t |
struct ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR.
Data Fields | ||
---|---|---|
uint32_t | base: 16 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE |
uint32_t | limit: 16 | ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT |
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_WIDTH 16 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET_MSK 0x0000ffff |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_CLR_MSK 0xffff0000 |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_GET | ( | value | ) | (((value) & 0x0000ffff) >> 0) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE_SET | ( | value | ) | (((value) << 0) & 0x0000ffff) |
Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_BASE register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_WIDTH 16 |
The width in bits of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET_MSK 0xffff0000 |
The mask used to set the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_CLR_MSK 0x0000ffff |
The mask used to clear the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_RESET 0x0 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_GET | ( | value | ) | (((value) & 0xffff0000) >> 16) |
Extracts the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT field value from a register.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT_SET | ( | value | ) | (((value) << 16) & 0xffff0000) |
Produces a ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_LIMIT register field value suitable for setting the register.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_RESET 0x00000000 |
The reset value of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR register.
#define ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR_OFST 0x1c |
The byte offset of the ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR register from the beginning of the component.
The typedef declaration for register ALT_NOC_FW_DDR_L3_SCR_HPSREG4ADDR.