![]() |
Altera HWLIB
16.0
The Altera HW Manager API Reference Manual
|
#include "hwlib.h"
Go to the source code of this file.
Altera - MMU Management API
Data Structures | |
struct | ALT_MMU_TTB1_FAULT_s |
union | ALT_MMU_TTB1_FAULT_ENTRY_u |
struct | ALT_MMU_TTB1_PAGE_TABLE_s |
union | ALT_MMU_TTB1_PAGE_TABLE_ENTRY_u |
struct | ALT_MMU_TTB1_SECTION_s |
union | ALT_MMU_TTB1_SECTION_ENTRY_u |
struct | ALT_MMU_TTB1_SUPERSECTION_s |
union | ALT_MMU_TTB1_SUPERSECTION_ENTRY_u |
struct | ALT_MMU_TTB2_FAULT_s |
union | ALT_MMU_TTB2_FAULT_ENTRY_u |
struct | ALT_MMU_TTB2_LARGE_PAGE_s |
union | ALT_MMU_TTB2_LARGE_PAGE_ENTRY_u |
struct | ALT_MMU_TTB2_SMALL_PAGE_s |
union | ALT_MMU_TTB2_SMALL_PAGE_ENTRY_u |
struct | ALT_MMU_MEM_REGION_s |
Macros | |
#define | ALT_MMU_SUPERSECTION_SIZE (1UL << 24) |
#define | ALT_MMU_SECTION_SIZE (1UL << 20) |
#define | ALT_MMU_LARGE_PAGE_SIZE (1UL << 16) |
#define | ALT_MMU_SMALL_PAGE_SIZE (1UL << 12) |
#define | ALT_MMU_TTB1_SIZE 16384 |
#define | ALT_MMU_TTB2_SIZE 1024 |
First Level Translation Table Page Table Entry [NS] | |
The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map. | |
#define | ALT_MMU_TTB1_PAGE_TBL_NS_MASK 0x00000008 |
#define | ALT_MMU_TTB1_PAGE_TBL_NS_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) >> 3) |
#define | ALT_MMU_TTB1_PAGE_TBL_NS_SET(val) (((val) << 3) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) |
First Level Translation Table Page Table Entry [DOMAIN] | |
Domain field. Page table descriptor applies to all entries in the corresponding second-level translation table. | |
#define | ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK 0x000001e0 |
#define | ALT_MMU_TTB1_PAGE_TBL_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) >> 5) |
#define | ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) |
First Level Translation Table Page Table Entry Page Table Base Address | |
#define | ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK 0xfffffc00 |
#define | ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) >> 10) |
#define | ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(val) (((val) << 10) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) |
First Level Translation Table Section Entry [B] | |
The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute. | |
#define | ALT_MMU_TTB1_SECTION_B_MASK 0x00000004 |
#define | ALT_MMU_TTB1_SECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_B_MASK) >> 2) |
#define | ALT_MMU_TTB1_SECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SECTION_B_MASK) |
First Level Translation Table Section Entry [C] | |
The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute. | |
#define | ALT_MMU_TTB1_SECTION_C_MASK 0x00000008 |
#define | ALT_MMU_TTB1_SECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_C_MASK) >> 3) |
#define | ALT_MMU_TTB1_SECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SECTION_C_MASK) |
First Level Translation Table Section Entry [XN] | |
The Execute-Never bit. Determines whether the processor can execute software from the addressed region. | |
#define | ALT_MMU_TTB1_SECTION_XN_MASK 0x00000010 |
#define | ALT_MMU_TTB1_SECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_XN_MASK) >> 4) |
#define | ALT_MMU_TTB1_SECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SECTION_XN_MASK) |
First Level Translation Table Section Entry [DOMAIN] | |
Domain field. | |
#define | ALT_MMU_TTB1_SECTION_DOMAIN_MASK 0x000001e0 |
#define | ALT_MMU_TTB1_SECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) >> 5) |
#define | ALT_MMU_TTB1_SECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) |
First Level Translation Table Section Entry [AP] | |
Access Permissions bits. | |
#define | ALT_MMU_TTB1_SECTION_AP_MASK 0x00008c00 |
#define | ALT_MMU_TTB1_SECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10)) |
#define | ALT_MMU_TTB1_SECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00)) |
First Level Translation Table Section Entry [TEX] | |
The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute. | |
#define | ALT_MMU_TTB1_SECTION_TEX_MASK 0x00007000 |
#define | ALT_MMU_TTB1_SECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_TEX_MASK) >> 12) |
#define | ALT_MMU_TTB1_SECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SECTION_TEX_MASK) |
First Level Translation Table Section Entry [S] | |
The Shareable bit. Determines whether the addressed region is shareable memory. | |
#define | ALT_MMU_TTB1_SECTION_S_MASK 0x00010000 |
#define | ALT_MMU_TTB1_SECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_S_MASK) >> 16) |
#define | ALT_MMU_TTB1_SECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SECTION_S_MASK) |
First Level Translation Table Section Entry [nG] | |
The not global bit. Determines how the translation is marked in the TLB. | |
#define | ALT_MMU_TTB1_SECTION_NG_MASK 0x00020000 |
#define | ALT_MMU_TTB1_SECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NG_MASK) >> 17) |
#define | ALT_MMU_TTB1_SECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SECTION_NG_MASK) |
First Level Translation Table Section Entry [NS] | |
The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map. | |
#define | ALT_MMU_TTB1_SECTION_NS_MASK 0x00080000 |
#define | ALT_MMU_TTB1_SECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NS_MASK) >> 19) |
#define | ALT_MMU_TTB1_SECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SECTION_NS_MASK) |
First Level Translation Table Section Entry Section Base Address | |
#define | ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK 0xfff00000 |
#define | ALT_MMU_TTB1_SECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) >> 20) |
#define | ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(val) (((val) << 20) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) |
First Level Translation Table Supersection Entry [B] | |
The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute. | |
#define | ALT_MMU_TTB1_SUPERSECTION_B_MASK 0x00000004 |
#define | ALT_MMU_TTB1_SUPERSECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) >> 2) |
#define | ALT_MMU_TTB1_SUPERSECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) |
First Level Translation Table Supersection Entry [C] | |
The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute. | |
#define | ALT_MMU_TTB1_SUPERSECTION_C_MASK 0x00000008 |
#define | ALT_MMU_TTB1_SUPERSECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) >> 3) |
#define | ALT_MMU_TTB1_SUPERSECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) |
First Level Translation Table Supersection Entry [XN] | |
The Execute-Never bit. Determines whether the processor can execute software from the addressed region. | |
#define | ALT_MMU_TTB1_SUPERSECTION_XN_MASK 0x00000010 |
#define | ALT_MMU_TTB1_SUPERSECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) >> 4) |
#define | ALT_MMU_TTB1_SUPERSECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) |
First Level Translation Table Supersection Entry [DOMAIN] | |
Domain field. | |
#define | ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK 0x000001e0 |
#define | ALT_MMU_TTB1_SUPERSECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) >> 5) |
#define | ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) |
First Level Translation Table Supersection Entry [AP] | |
Access Permissions bits. | |
#define | ALT_MMU_TTB1_SUPERSECTION_AP_MASK 0x00008c00 |
#define | ALT_MMU_TTB1_SUPERSECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10)) |
#define | ALT_MMU_TTB1_SUPERSECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00)) |
First Level Translation Table Supersection Entry [TEX] | |
The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute. | |
#define | ALT_MMU_TTB1_SUPERSECTION_TEX_MASK 0x00007000 |
#define | ALT_MMU_TTB1_SUPERSECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) >> 12) |
#define | ALT_MMU_TTB1_SUPERSECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) |
First Level Translation Table Supersection Entry [S] | |
The Shareable bit. Determines whether the addressed region is shareable memory. | |
#define | ALT_MMU_TTB1_SUPERSECTION_S_MASK 0x00010000 |
#define | ALT_MMU_TTB1_SUPERSECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) >> 16) |
#define | ALT_MMU_TTB1_SUPERSECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) |
First Level Translation Table Supersection Entry [nG] | |
The not global bit. Determines how the translation is marked in the TLB. | |
#define | ALT_MMU_TTB1_SUPERSECTION_NG_MASK 0x00020000 |
#define | ALT_MMU_TTB1_SUPERSECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) >> 17) |
#define | ALT_MMU_TTB1_SUPERSECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) |
First Level Translation Table Supersection Entry [NS] | |
The Non-Secure [NS] bit. This bit specifies whether the translated PA is in the Secure or Non-Secure address map. | |
#define | ALT_MMU_TTB1_SUPERSECTION_NS_MASK 0x00080000 |
#define | ALT_MMU_TTB1_SUPERSECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) >> 19) |
#define | ALT_MMU_TTB1_SUPERSECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) |
First Level Translation Table Supersection Entry Supersection Base Address | |
#define | ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK 0xff000000 |
#define | ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) >> 24) |
#define | ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(val) (((val) << 24) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) |
Second Level Translation Table Large Page Table Entry [B] | |
The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_B_MASK 0x00000004 |
#define | ALT_MMU_TTB2_LARGE_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) >> 2) |
#define | ALT_MMU_TTB2_LARGE_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) |
Second Level Translation Table Large Page Table Entry [C] | |
The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_C_MASK 0x00000008 |
#define | ALT_MMU_TTB2_LARGE_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) >> 3) |
#define | ALT_MMU_TTB2_LARGE_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) |
Second Level Translation Table Large Page Table Entry [AP] | |
Access Permissions bits. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_AP_MASK 0x00000230 |
#define | ALT_MMU_TTB2_LARGE_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4)) |
#define | ALT_MMU_TTB2_LARGE_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030)) |
Second Level Translation Table Large Page Table Entry [S] | |
The Shareable bit. Determines whether the addressed region is shareable memory. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_S_MASK 0x00000400 |
#define | ALT_MMU_TTB2_LARGE_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) >> 10) |
#define | ALT_MMU_TTB2_LARGE_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) |
Second Level Translation Table Large Page Table Entry [nG] | |
The not global bit. Determines how the translation is marked in the TLB. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_NG_MASK 0x00000800 |
#define | ALT_MMU_TTB2_LARGE_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) >> 11) |
#define | ALT_MMU_TTB2_LARGE_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) |
Second Level Translation Table Large Page Table Entry [TEX] | |
The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK 0x00007000 |
#define | ALT_MMU_TTB2_LARGE_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) >> 12) |
#define | ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) |
Second Level Translation Table Large Page Table Entry [XN] | |
The Execute-Never bit. Determines whether the processor can execute software from the addressed region. | |
#define | ALT_MMU_TTB2_LARGE_PAGE_XN_MASK 0x00008000 |
#define | ALT_MMU_TTB2_LARGE_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) >> 15) |
#define | ALT_MMU_TTB2_LARGE_PAGE_XN_SET(val) (((val) << 15) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) |
Second Level Translation Table Large Page Table Entry Large Page Base Address | |
#define | ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK 0xffff0000 |
#define | ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) >> 16) |
#define | ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(val) (((val) << 16) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) |
Second Level Translation Table Small Page Table Entry [XN] | |
The Execute-Never bit. Determines whether the processor can execute software from the addressed region. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_XN_MASK 0x00000001 |
#define | ALT_MMU_TTB2_SMALL_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) >> 0) |
#define | ALT_MMU_TTB2_SMALL_PAGE_XN_SET(val) (((val) << 0) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) |
Second Level Translation Table Small Page Table Entry [B] | |
The [B] field of the memory region attributes. [B] is an arcane reference to Bufferable attribute. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_B_MASK 0x00000004 |
#define | ALT_MMU_TTB2_SMALL_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) >> 2) |
#define | ALT_MMU_TTB2_SMALL_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) |
Second Level Translation Table Small Page Table Entry [C] | |
The [C] field of the memory region attributes. [C] is an arcane reference to Cacheable attribute. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_C_MASK 0x00000008 |
#define | ALT_MMU_TTB2_SMALL_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) >> 3) |
#define | ALT_MMU_TTB2_SMALL_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) |
Second Level Translation Table Small Page Table Entry [AP] | |
Access Permissions bits. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_AP_MASK 0x00000230 |
#define | ALT_MMU_TTB2_SMALL_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4)) |
#define | ALT_MMU_TTB2_SMALL_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030)) |
Second Level Translation Table Small Page Table Entry [TEX] | |
The [TEX] field of the memory region attributes. [TEX] is an arcane reference to Type EXtension attribute. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK 0x000001c0 |
#define | ALT_MMU_TTB2_SMALL_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) >> 6) |
#define | ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(val) (((val) << 6) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) |
Second Level Translation Table Small Page Table Entry [S] | |
The Shareable bit. Determines whether the addressed region is shareable memory. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_S_MASK 0x00000400 |
#define | ALT_MMU_TTB2_SMALL_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) >> 10) |
#define | ALT_MMU_TTB2_SMALL_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) |
Second Level Translation Table Small Page Table Entry [nG] | |
The not global bit. Determines how the translation is marked in the TLB. | |
#define | ALT_MMU_TTB2_SMALL_PAGE_NG_MASK 0x00000800 |
#define | ALT_MMU_TTB2_SMALL_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) >> 11) |
#define | ALT_MMU_TTB2_SMALL_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) |
Second Level Translation Table Small Page Table Entry Large Page Base Address | |
#define | ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK 0xfffff000 |
#define | ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) >> 12) |
#define | ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(val) (((val) << 12) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) |
Functions | |
ALT_STATUS_CODE | alt_mmu_init (void) |
ALT_STATUS_CODE | alt_mmu_uninit (void) |
ALT_STATUS_CODE | alt_mmu_ttb1_init (uint32_t *ttb1) |
ALT_STATUS_CODE | alt_mmu_ttb1_desc_set (uint32_t *ttb1, const void *va, const uint32_t desc) |
ALT_STATUS_CODE | alt_mmu_ttb2_desc_set (const uint32_t *ttb1, const void *va, const uint32_t desc) |
ALT_STATUS_CODE | alt_mmu_disable (void) |
ALT_STATUS_CODE | alt_mmu_enable (void) |
void * | alt_mmu_TTBR0_get (void) |
ALT_STATUS_CODE | alt_mmu_TTBR0_set (const void *addr) |
void * | alt_mmu_TTBR1_get (void) |
ALT_STATUS_CODE | alt_mmu_TTBR1_set (const void *addr) |
ALT_STATUS_CODE | alt_mmu_TTBCR_set (const bool enable_ttbr0_walk, const bool enable_ttbr1_walk, const uint32_t base_addr_width) |
ALT_STATUS_CODE | alt_mmu_DACR_set (const ALT_MMU_DAP_t domain_ap[], const size_t num_elem) |
ALT_STATUS_CODE | alt_mmu_CONTEXTIDR_set (const uint32_t procid, const uint32_t asid) |
ALT_STATUS_CODE | alt_mmu_tlb_invalidate (void) |
ALT_STATUS_CODE | alt_mmu_tlb_invalidate_is (void) |
size_t | alt_mmu_va_space_storage_required (const ALT_MMU_MEM_REGION_t *mem_regions, const size_t num_mem_regions) |
ALT_STATUS_CODE | alt_mmu_va_space_create (uint32_t **ttb1, const ALT_MMU_MEM_REGION_t *mem_regions, const size_t num_mem_regions, alt_mmu_ttb_alloc_t ttb_alloc, void *ttb_alloc_context) |
ALT_STATUS_CODE | alt_mmu_va_space_enable (const uint32_t *ttb1) |
uintptr_t | alt_mmu_va_to_pa (const void *va, uint32_t *seglength, uint32_t *dfsr) |