Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : mpu_clear_l2_ecc

Description

Write 1 to Clear register to clear the specific bit field of mpu l2 ecc interrupt pending status

Reads should not return an error, but the read value is undefined.

Register Layout

Bits Access Reset Description
[14:0] ??? 0x0 UNDEFINED
[15] RW 0x0 ALT_SYSMGR_MPU_CLR_L2_ECC_SERR
[30:16] ??? 0x0 UNDEFINED
[31] RW 0x0 ALT_SYSMGR_MPU_CLR_L2_ECC_MERR

Field : serr

Write 1 to this field to clear the MPU L2 ECC single bit Error interrupt Status and the actual Interrupt.

Field Access Macros:

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_LSB   15
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_MSB   15
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_WIDTH   1
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET_MSK   0x00008000
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_CLR_MSK   0xffff7fff
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_RESET   0x0
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET(value)   (((value) << 15) & 0x00008000)
 

Field : merr

Write 1 to this field to clear the MPU L2 ECC multiple bit Error interrupt Status and the actual Interrupt.

Field Access Macros:

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_LSB   31
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_MSB   31
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_WIDTH   1
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET_MSK   0x80000000
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_CLR_MSK   0x7fffffff
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_RESET   0x0
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_SYSMGR_MPU_CLR_L2_ECC_s
 

Macros

#define ALT_SYSMGR_MPU_CLR_L2_ECC_RESET   0x00000000
 
#define ALT_SYSMGR_MPU_CLR_L2_ECC_OFST   0xa8
 

Typedefs

typedef struct
ALT_SYSMGR_MPU_CLR_L2_ECC_s 
ALT_SYSMGR_MPU_CLR_L2_ECC_t
 

Data Structure Documentation

struct ALT_SYSMGR_MPU_CLR_L2_ECC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_MPU_CLR_L2_ECC.

Data Fields
uint32_t __pad0__: 15 UNDEFINED
uint32_t serr: 1 ALT_SYSMGR_MPU_CLR_L2_ECC_SERR
uint32_t __pad1__: 15 UNDEFINED
uint32_t merr: 1 ALT_SYSMGR_MPU_CLR_L2_ECC_MERR

Macro Definitions

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_LSB   15

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_MSB   15

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET_MSK   0x00008000

The mask used to set the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_CLR_MSK   0xffff7fff

The mask used to clear the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_SYSMGR_MPU_CLR_L2_ECC_SERR field value from a register.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_SERR_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_SYSMGR_MPU_CLR_L2_ECC_SERR register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_LSB   31

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_MSB   31

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_WIDTH   1

The width in bits of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET_MSK   0x80000000

The mask used to set the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_CLR_MSK   0x7fffffff

The mask used to clear the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_SYSMGR_MPU_CLR_L2_ECC_MERR field value from a register.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_MERR_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_SYSMGR_MPU_CLR_L2_ECC_MERR register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_RESET   0x00000000

The reset value of the ALT_SYSMGR_MPU_CLR_L2_ECC register.

#define ALT_SYSMGR_MPU_CLR_L2_ECC_OFST   0xa8

The byte offset of the ALT_SYSMGR_MPU_CLR_L2_ECC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_MPU_CLR_L2_ECC.