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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Used to disable individual interfaces between the FPGA and HPS.
This register is reset only on a cold reset (ignores warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[3:0] | ??? | 0x0 | UNDEFINED |
[4] | RW | 0x0 | NAND Flash Controller Module |
[7:5] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | SD/MMC Controller Module |
[15:9] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | SPI Master Module |
[23:17] | ??? | 0x0 | UNDEFINED |
[24] | RW | 0x0 | SPI Master Module |
[31:25] | ??? | 0x0 | UNDEFINED |
Field : NAND Flash Controller Module - nand | |
Used to disable signals from the FPGA fabric to the NAND flash controller module that could potentially interfere with its normal operation. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_LSB 4 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_MSB 4 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_RESET 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET(value) (((value) << 4) & 0x00000010) |
Field : SD/MMC Controller Module - sdmmc | |
Used to disable signals from the FPGA fabric to the SD/MMC controller module that could potentially interfere with its normal operation. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_LSB 8 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_MSB 8 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_RESET 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET(value) (((value) << 8) & 0x00000100) |
Field : SPI Master Module - spim_0 | |
Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation. The array index corresponds to the SPI master module instance. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_LSB 16 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_MSB 16 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_RESET 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET(value) (((value) << 16) & 0x00010000) |
Field : SPI Master Module - spim_1 | |
Used to disable signals from the FPGA fabric to the SPI master modules that could potentially interfere with their normal operation. The array index corresponds to the SPI master module instance. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_LSB 24 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_MSB 24 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_RESET 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET(value) (((value) << 24) & 0x01000000) |
Data Structures | |
struct | ALT_SYSMGR_FPGAINTF_EN_2_s |
Macros | |
#define | ALT_SYSMGR_FPGAINTF_EN_2_RESET 0x00000000 |
#define | ALT_SYSMGR_FPGAINTF_EN_2_OFST 0x6c |
Typedefs | |
typedef struct ALT_SYSMGR_FPGAINTF_EN_2_s | ALT_SYSMGR_FPGAINTF_EN_2_t |
struct ALT_SYSMGR_FPGAINTF_EN_2_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_2.
Data Fields | ||
---|---|---|
uint32_t | __pad0__: 4 | UNDEFINED |
uint32_t | nand: 1 | NAND Flash Controller Module |
uint32_t | __pad1__: 3 | UNDEFINED |
uint32_t | sdmmc: 1 | SD/MMC Controller Module |
uint32_t | __pad2__: 7 | UNDEFINED |
uint32_t | spim_0: 1 | SPI Master Module |
uint32_t | __pad3__: 7 | UNDEFINED |
uint32_t | spim_1: 1 | SPI Master Module |
uint32_t | __pad4__: 7 | UNDEFINED |
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_NAND
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_NAND
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_RESET 0x0 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_NAND register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_2_NAND field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_2_NAND_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_FPGAINTF_EN_2_NAND register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SDMMC
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SDMMC
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET_MSK 0x00000100 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_RESET 0x0 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SDMMC field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SDMMC_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SYSMGR_FPGAINTF_EN_2_SDMMC register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET_MSK 0x00010000 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_RESET 0x0 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_SYSMGR_FPGAINTF_EN_2_SPIM_0 register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET_MSK 0x01000000 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_RESET 0x0 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_SYSMGR_FPGAINTF_EN_2_SPIM_1 register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_2_RESET 0x00000000 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_2 register.
#define ALT_SYSMGR_FPGAINTF_EN_2_OFST 0x6c |
The byte offset of the ALT_SYSMGR_FPGAINTF_EN_2 register from the beginning of the component.
typedef struct ALT_SYSMGR_FPGAINTF_EN_2_s ALT_SYSMGR_FPGAINTF_EN_2_t |
The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_2.