Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : DIAGINTTEST

Description

Enable diagnostic errors

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA
[7:1] ??? 0x0 UNDEFINED
[8] RW 0x0 ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA
[15:9] ??? 0x0 UNDEFINED
[16] RW 0x0 ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC
[23:17] ??? 0x0 UNDEFINED
[24] RW 0x0 ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR
[31:25] ??? 0x0 UNDEFINED

Field : TSERRA

This bit is used to test a single-bit error.

1'b0: Write of zero has no effect.

1'b1: When this bit is set to 1, serr_req signal is generated to the system manager when the ECC decoder detects a single-bit error. By writing to this bit, SERRPENA bit will be pending. Write of one to SERRPENA will clear this bit.

Field Access Macros:

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_LSB   0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_MSB   0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_WIDTH   1
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET_MSK   0x00000001
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_CLR_MSK   0xfffffffe
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_RESET   0x0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET(value)   (((value) << 0) & 0x00000001)
 

Field : TDERRA

Diagnostic enable of Double-bit error.

This bit is used to test double-bit error.

1'b0: Write of zero has no effect.

1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects a double-bit error. By writing to this bit, DERRBUSFLG bit will be pending. Write of one to DERRBUSFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.

Field Access Macros:

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_LSB   8
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_MSB   8
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_WIDTH   1
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET_MSK   0x00000100
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_CLR_MSK   0xfffffeff
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_RESET   0x0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET(value)   (((value) << 8) & 0x00000100)
 

Field : TADDRMTC

Diagnostic enable of Address mismatch error.

This bit is used to flag that the last transaction was flagged with address mismatch error.

1'b0: Disables generating address match bus error as part of the transaction.

1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects a ecc address mismatch. By writing to this bit, ADDRMTCFLG bit will be pending. Write of one to ADDRMTCFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.

Field Access Macros:

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_LSB   16
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_MSB   16
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_WIDTH   1
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET_MSK   0x00010000
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_CLR_MSK   0xfffeffff
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_RESET   0x0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET(value)   (((value) << 16) & 0x00010000)
 

Field : TADDRPAR

Diagnostic of address parity of DDR4.

This bit is used to test the address parity error path.

1'b0: Disables generating address match bus error as part of the transaction.

1'b1: When this bit is set to 1, derr_req signal is generated to the system manager when the ECC decoder detects an ecc address parity error. By writing to this bit, ADDRPARFLG bit will be pending. Write of one to ADDRPARFLG will clear this bit. SW needs to explicitly write to DERRPENA to clear it.

Field Access Macros:

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_LSB   24
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_MSB   24
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_WIDTH   1
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET_MSK   0x01000000
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_CLR_MSK   0xfeffffff
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_RESET   0x0
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET(value)   (((value) << 24) & 0x01000000)
 

Data Structures

struct  ALT_ECC_HMC_OCP_DIAGINTTEST_s
 

Macros

#define ALT_ECC_HMC_OCP_DIAGINTTEST_RESET   0x00000000
 
#define ALT_ECC_HMC_OCP_DIAGINTTEST_OFST   0x124
 

Typedefs

typedef struct
ALT_ECC_HMC_OCP_DIAGINTTEST_s 
ALT_ECC_HMC_OCP_DIAGINTTEST_t
 

Data Structure Documentation

struct ALT_ECC_HMC_OCP_DIAGINTTEST_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_ECC_HMC_OCP_DIAGINTTEST.

Data Fields
uint32_t TSERRA: 1 ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA
uint32_t __pad0__: 7 UNDEFINED
uint32_t TDERRA: 1 ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA
uint32_t __pad1__: 7 UNDEFINED
uint32_t TADDRMTC: 1 ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC
uint32_t __pad2__: 7 UNDEFINED
uint32_t TADDRPAR: 1 ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR
uint32_t __pad3__: 7 UNDEFINED

Macro Definitions

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_LSB   0

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_MSB   0

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET_MSK   0x00000001

The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_CLR_MSK   0xfffffffe

The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA field value from a register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TSERRA register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_LSB   8

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_MSB   8

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET_MSK   0x00000100

The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_CLR_MSK   0xfffffeff

The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA field value from a register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TDERRA register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_LSB   16

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_MSB   16

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET_MSK   0x00010000

The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_CLR_MSK   0xfffeffff

The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC field value from a register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRMTC register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_LSB   24

The Least Significant Bit (LSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_MSB   24

The Most Significant Bit (MSB) position of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_WIDTH   1

The width in bits of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET_MSK   0x01000000

The mask used to set the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_CLR_MSK   0xfeffffff

The mask used to clear the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_RESET   0x0

The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR field value from a register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_ECC_HMC_OCP_DIAGINTTEST_TADDRPAR register field value suitable for setting the register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_RESET   0x00000000

The reset value of the ALT_ECC_HMC_OCP_DIAGINTTEST register.

#define ALT_ECC_HMC_OCP_DIAGINTTEST_OFST   0x124

The byte offset of the ALT_ECC_HMC_OCP_DIAGINTTEST register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_ECC_HMC_OCP_DIAGINTTEST.