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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The PER0MODRST register is used by software to trigger module resets for Peripheral Group and Fast Peripheral Group. Regular Peripheral Group resets are in the lower 2 bytes, and Fast Pheripheral Group resets are in the upper 2 bytes. Software explicitly asserts and de-asserts module reset signals by writing bits in the appropriate *MODRST register. It is up to software to ensure module reset signals are asserted for the appropriate length of time and are de- asserted in the correct order. It is also up to software to not assert a module reset signal that would prevent software from de-asserting the module reset signal. For example, software should not assert the module reset to the CPU executing the software.
Software writes a bit to 1 to assert the module reset signal and to 0 to de- assert the module reset signal.
All fields are reset by a cold reset.All fields are also reset by a warm reset if not masked by the corresponding PERWARMMASK field.
The reset value of all fields is 1. This holds the corresponding module in reset until software is ready to release the module from reset by writing 0 to its field.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | EMAC0 |
[1] | RW | 0x1 | EMAC1 |
[2] | RW | 0x1 | EMAC2 |
[3] | RW | 0x1 | USB0 |
[4] | RW | 0x1 | USB1 |
[5] | RW | 0x1 | NAND Flash |
[6] | RW | 0x1 | QSPI Flash |
[7] | RW | 0x1 | SD/MMC |
[8] | RW | 0x1 | EMAC0OCP |
[9] | RW | 0x1 | EMAC1OCP |
[10] | RW | 0x1 | EMAC2OCP |
[11] | RW | 0x1 | USB0OCP |
[12] | RW | 0x1 | USB1OCP |
[13] | RW | 0x1 | NANDOCP |
[14] | RW | 0x1 | QSPIOCP |
[15] | RW | 0x1 | SDMMCOCP |
[16] | RW | 0x1 | DMA Controller |
[17] | RW | 0x1 | SPIM0 |
[18] | RW | 0x1 | SPIM1 |
[19] | RW | 0x1 | SPIS0 |
[20] | RW | 0x1 | SPIS1 |
[21] | RW | 0x1 | DMAOCP |
[22] | RW | 0x1 | EMAC PTP |
[23] | ??? | 0x0 | UNDEFINED |
[24] | RW | 0x1 | FPGA DMA0 |
[25] | RW | 0x1 | FPGA DMA1 |
[26] | RW | 0x1 | FPGA DMA2 |
[27] | RW | 0x1 | FPGA DMA3 |
[28] | RW | 0x1 | FPGA DMA4 |
[29] | RW | 0x1 | FPGA DMA5 |
[30] | RW | 0x1 | FPGA DMA6 |
[31] | RW | 0x1 | FPGA DMA7 |
Field : EMAC0 - emac0 | |
Resets EMAC0 Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_RSTMGR_PER0MODRST_EMAC0_SET(value) (((value) << 0) & 0x00000001) |
Field : EMAC1 - emac1 | |
Resets EMAC1 Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_RSTMGR_PER0MODRST_EMAC1_SET(value) (((value) << 1) & 0x00000002) |
Field : EMAC2 - emac2 | |
Resets EMAC2 Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_RSTMGR_PER0MODRST_EMAC2_SET(value) (((value) << 2) & 0x00000004) |
Field : USB0 - usb0 | |
Resets USB0 Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_USB0_LSB 3 |
#define | ALT_RSTMGR_PER0MODRST_USB0_MSB 3 |
#define | ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008 |
#define | ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7 |
#define | ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_USB0_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_RSTMGR_PER0MODRST_USB0_SET(value) (((value) << 3) & 0x00000008) |
Field : USB1 - usb1 | |
Resets USB1 Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_USB1_LSB 4 |
#define | ALT_RSTMGR_PER0MODRST_USB1_MSB 4 |
#define | ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010 |
#define | ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef |
#define | ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_USB1_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_RSTMGR_PER0MODRST_USB1_SET(value) (((value) << 4) & 0x00000010) |
Field : NAND Flash - nand | |
Resets NAND flash controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_NAND_LSB 5 |
#define | ALT_RSTMGR_PER0MODRST_NAND_MSB 5 |
#define | ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020 |
#define | ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf |
#define | ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_NAND_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_RSTMGR_PER0MODRST_NAND_SET(value) (((value) << 5) & 0x00000020) |
Field : QSPI Flash - qspi | |
Resets QSPI flash controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_QSPI_LSB 6 |
#define | ALT_RSTMGR_PER0MODRST_QSPI_MSB 6 |
#define | ALT_RSTMGR_PER0MODRST_QSPI_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040 |
#define | ALT_RSTMGR_PER0MODRST_QSPI_CLR_MSK 0xffffffbf |
#define | ALT_RSTMGR_PER0MODRST_QSPI_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_QSPI_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_RSTMGR_PER0MODRST_QSPI_SET(value) (((value) << 6) & 0x00000040) |
Field : SD/MMC - sdmmc | |
Resets SD/MMC controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7 |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7 |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080 |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_RSTMGR_PER0MODRST_SDMMC_SET(value) (((value) << 7) & 0x00000080) |
Field : EMAC0OCP - emac0ocp | |
Resets EMAC0 ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET(value) (((value) << 8) & 0x00000100) |
Field : EMAC1OCP - emac1ocp | |
Resets EMAC1 ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET(value) (((value) << 9) & 0x00000200) |
Field : EMAC2OCP - emac2ocp | |
Resets EMAC0 ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET(value) (((value) << 10) & 0x00000400) |
Field : USB0OCP - usb0ocp | |
Resets USB0 ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11 |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11 |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800 |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_RSTMGR_PER0MODRST_USB0OCP_SET(value) (((value) << 11) & 0x00000800) |
Field : USB1OCP - usb1ocp | |
Resets USB1 ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12 |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12 |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000 |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_RSTMGR_PER0MODRST_USB1OCP_SET(value) (((value) << 12) & 0x00001000) |
Field : NANDOCP - nandocp | |
Resets NAND ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13 |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13 |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000 |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_RSTMGR_PER0MODRST_NANDOCP_SET(value) (((value) << 13) & 0x00002000) |
Field : QSPIOCP - qspiocp | |
Resets QSPI ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_LSB 14 |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_MSB 14 |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_SET_MSK 0x00004000 |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_CLR_MSK 0xffffbfff |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_RSTMGR_PER0MODRST_QSPIOCP_SET(value) (((value) << 14) & 0x00004000) |
Field : SDMMCOCP - sdmmcocp | |
Resets SDMMC ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15 |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15 |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000 |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET(value) (((value) << 15) & 0x00008000) |
Field : DMA Controller - dma | |
Resets DMA controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMA_LSB 16 |
#define | ALT_RSTMGR_PER0MODRST_DMA_MSB 16 |
#define | ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000 |
#define | ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff |
#define | ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMA_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_RSTMGR_PER0MODRST_DMA_SET(value) (((value) << 16) & 0x00010000) |
Field : SPIM0 - spim0 | |
Resets SPIM0 controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17 |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17 |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000 |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_RSTMGR_PER0MODRST_SPIM0_SET(value) (((value) << 17) & 0x00020000) |
Field : SPIM1 - spim1 | |
Resets SPIM1 controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18 |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18 |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000 |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_RSTMGR_PER0MODRST_SPIM1_SET(value) (((value) << 18) & 0x00040000) |
Field : SPIS0 - spis0 | |
Resets SPIS0 controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19 |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19 |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000 |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_RSTMGR_PER0MODRST_SPIS0_SET(value) (((value) << 19) & 0x00080000) |
Field : SPIS1 - spis1 | |
Resets SPIS1 controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20 |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20 |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000 |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_RSTMGR_PER0MODRST_SPIS1_SET(value) (((value) << 20) & 0x00100000) |
Field : DMAOCP - dmaocp | |
Resets DMA Controller ECC OCP DIagnostics modules. Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21 |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21 |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000 |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_RSTMGR_PER0MODRST_DMAOCP_SET(value) (((value) << 21) & 0x00200000) |
Field : EMAC PTP - emacptp | |
Resets EMAC PTP Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22 |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22 |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000 |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_RSTMGR_PER0MODRST_EMACPTP_SET(value) (((value) << 22) & 0x00400000) |
Field : FPGA DMA0 - dmaif0 | |
Resets DMA channel 0 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF0_SET(value) (((value) << 24) & 0x01000000) |
Field : FPGA DMA1 - dmaif1 | |
Resets DMA channel 1 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF1_SET(value) (((value) << 25) & 0x02000000) |
Field : FPGA DMA2 - dmaif2 | |
Resets DMA channel 2 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_GET(value) (((value) & 0x04000000) >> 26) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF2_SET(value) (((value) << 26) & 0x04000000) |
Field : FPGA DMA3 - dmaif3 | |
Resets DMA channel 3 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_GET(value) (((value) & 0x08000000) >> 27) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF3_SET(value) (((value) << 27) & 0x08000000) |
Field : FPGA DMA4 - dmaif4 | |
Resets DMA channel 4 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_GET(value) (((value) & 0x10000000) >> 28) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF4_SET(value) (((value) << 28) & 0x10000000) |
Field : FPGA DMA5 - dmaif5 | |
Resets DMA channel 5 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_GET(value) (((value) & 0x20000000) >> 29) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF5_SET(value) (((value) << 29) & 0x20000000) |
Field : FPGA DMA6 - dmaif6 | |
Resets DMA channel 6 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_GET(value) (((value) & 0x40000000) >> 30) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF6_SET(value) (((value) << 30) & 0x40000000) |
Field : FPGA DMA7 - dmaif7 | |
Resets DMA channel 7 interface adapter between FPGA Fabric and HPS DMA Controller Field Access Macros: | |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1 |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_RSTMGR_PER0MODRST_DMAIF7_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_RSTMGR_PER0MODRST_s |
Macros | |
#define | ALT_RSTMGR_PER0MODRST_RESET 0xff7fffff |
#define | ALT_RSTMGR_PER0MODRST_OFST 0x24 |
Typedefs | |
typedef struct ALT_RSTMGR_PER0MODRST_s | ALT_RSTMGR_PER0MODRST_t |
struct ALT_RSTMGR_PER0MODRST_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_RSTMGR_PER0MODRST.
Data Fields | ||
---|---|---|
uint32_t | emac0: 1 | EMAC0 |
uint32_t | emac1: 1 | EMAC1 |
uint32_t | emac2: 1 | EMAC2 |
uint32_t | usb0: 1 | USB0 |
uint32_t | usb1: 1 | USB1 |
uint32_t | nand: 1 | NAND Flash |
uint32_t | qspi: 1 | QSPI Flash |
uint32_t | sdmmc: 1 | SD/MMC |
uint32_t | emac0ocp: 1 | EMAC0OCP |
uint32_t | emac1ocp: 1 | EMAC1OCP |
uint32_t | emac2ocp: 1 | EMAC2OCP |
uint32_t | usb0ocp: 1 | USB0OCP |
uint32_t | usb1ocp: 1 | USB1OCP |
uint32_t | nandocp: 1 | NANDOCP |
uint32_t | qspiocp: 1 | QSPIOCP |
uint32_t | sdmmcocp: 1 | SDMMCOCP |
uint32_t | dma: 1 | DMA Controller |
uint32_t | spim0: 1 | SPIM0 |
uint32_t | spim1: 1 | SPIM1 |
uint32_t | spis0: 1 | SPIS0 |
uint32_t | spis1: 1 | SPIS1 |
uint32_t | dmaocp: 1 | DMAOCP |
uint32_t | emacptp: 1 | EMAC PTP |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | dmaif0: 1 | FPGA DMA0 |
uint32_t | dmaif1: 1 | FPGA DMA1 |
uint32_t | dmaif2: 1 | FPGA DMA2 |
uint32_t | dmaif3: 1 | FPGA DMA3 |
uint32_t | dmaif4: 1 | FPGA DMA4 |
uint32_t | dmaif5: 1 | FPGA DMA5 |
uint32_t | dmaif6: 1 | FPGA DMA6 |
uint32_t | dmaif7: 1 | FPGA DMA7 |
#define ALT_RSTMGR_PER0MODRST_EMAC0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK 0x00000001 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC0_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC0_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC0 field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC0_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC0 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMAC1_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK 0x00000002 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC1_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC1_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC1 field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC1_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC1 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMAC2_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK 0x00000004 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC2_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2 register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC2_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2 register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC2 field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC2_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC2 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_USB0_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field.
#define ALT_RSTMGR_PER0MODRST_USB0_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0 register field.
#define ALT_RSTMGR_PER0MODRST_USB0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_USB0 register field.
#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK 0x00000008 |
The mask used to set the ALT_RSTMGR_PER0MODRST_USB0 register field value.
#define ALT_RSTMGR_PER0MODRST_USB0_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0 register field value.
#define ALT_RSTMGR_PER0MODRST_USB0_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_USB0 register field.
#define ALT_RSTMGR_PER0MODRST_USB0_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_RSTMGR_PER0MODRST_USB0 field value from a register.
#define ALT_RSTMGR_PER0MODRST_USB0_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_RSTMGR_PER0MODRST_USB0 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_USB1_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field.
#define ALT_RSTMGR_PER0MODRST_USB1_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1 register field.
#define ALT_RSTMGR_PER0MODRST_USB1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_USB1 register field.
#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK 0x00000010 |
The mask used to set the ALT_RSTMGR_PER0MODRST_USB1 register field value.
#define ALT_RSTMGR_PER0MODRST_USB1_CLR_MSK 0xffffffef |
The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1 register field value.
#define ALT_RSTMGR_PER0MODRST_USB1_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_USB1 register field.
#define ALT_RSTMGR_PER0MODRST_USB1_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_RSTMGR_PER0MODRST_USB1 field value from a register.
#define ALT_RSTMGR_PER0MODRST_USB1_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_RSTMGR_PER0MODRST_USB1 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_NAND_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field.
#define ALT_RSTMGR_PER0MODRST_NAND_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NAND register field.
#define ALT_RSTMGR_PER0MODRST_NAND_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_NAND register field.
#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK 0x00000020 |
The mask used to set the ALT_RSTMGR_PER0MODRST_NAND register field value.
#define ALT_RSTMGR_PER0MODRST_NAND_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_RSTMGR_PER0MODRST_NAND register field value.
#define ALT_RSTMGR_PER0MODRST_NAND_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_NAND register field.
#define ALT_RSTMGR_PER0MODRST_NAND_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_RSTMGR_PER0MODRST_NAND field value from a register.
#define ALT_RSTMGR_PER0MODRST_NAND_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_RSTMGR_PER0MODRST_NAND register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_QSPI_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_QSPI register field.
#define ALT_RSTMGR_PER0MODRST_QSPI_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_QSPI register field.
#define ALT_RSTMGR_PER0MODRST_QSPI_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_QSPI register field.
#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK 0x00000040 |
The mask used to set the ALT_RSTMGR_PER0MODRST_QSPI register field value.
#define ALT_RSTMGR_PER0MODRST_QSPI_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_RSTMGR_PER0MODRST_QSPI register field value.
#define ALT_RSTMGR_PER0MODRST_QSPI_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_QSPI register field.
#define ALT_RSTMGR_PER0MODRST_QSPI_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_RSTMGR_PER0MODRST_QSPI field value from a register.
#define ALT_RSTMGR_PER0MODRST_QSPI_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_RSTMGR_PER0MODRST_QSPI register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SDMMC_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field.
#define ALT_RSTMGR_PER0MODRST_SDMMC_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMC register field.
#define ALT_RSTMGR_PER0MODRST_SDMMC_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMC register field.
#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK 0x00000080 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMC register field value.
#define ALT_RSTMGR_PER0MODRST_SDMMC_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMC register field value.
#define ALT_RSTMGR_PER0MODRST_SDMMC_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SDMMC register field.
#define ALT_RSTMGR_PER0MODRST_SDMMC_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_RSTMGR_PER0MODRST_SDMMC field value from a register.
#define ALT_RSTMGR_PER0MODRST_SDMMC_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_RSTMGR_PER0MODRST_SDMMC register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET_MSK 0x00000100 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC0OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC0OCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC0OCP_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC0OCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET_MSK 0x00000200 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC1OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC1OCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC1OCP_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC1OCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET_MSK 0x00000400 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMAC2OCP register field.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_RSTMGR_PER0MODRST_EMAC2OCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMAC2OCP_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_RSTMGR_PER0MODRST_EMAC2OCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB0OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_USB0OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_SET_MSK 0x00000800 |
The mask used to set the ALT_RSTMGR_PER0MODRST_USB0OCP register field value.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_USB0OCP register field value.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_USB0OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_RSTMGR_PER0MODRST_USB0OCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_USB0OCP_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_RSTMGR_PER0MODRST_USB0OCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_USB1OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_USB1OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_SET_MSK 0x00001000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_USB1OCP register field value.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_CLR_MSK 0xffffefff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_USB1OCP register field value.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_USB1OCP register field.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_RSTMGR_PER0MODRST_USB1OCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_USB1OCP_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_RSTMGR_PER0MODRST_USB1OCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_NANDOCP register field.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_NANDOCP register field.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_SET_MSK 0x00002000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_NANDOCP register field value.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_NANDOCP register field value.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_NANDOCP register field.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_RSTMGR_PER0MODRST_NANDOCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_NANDOCP_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_RSTMGR_PER0MODRST_NANDOCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET_MSK 0x00004000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_QSPIOCP register field value.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_QSPIOCP register field value.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_QSPIOCP register field.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_RSTMGR_PER0MODRST_QSPIOCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_QSPIOCP_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_RSTMGR_PER0MODRST_QSPIOCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET_MSK 0x00008000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SDMMCOCP register field.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_RSTMGR_PER0MODRST_SDMMCOCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_SDMMCOCP_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_RSTMGR_PER0MODRST_SDMMCOCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMA_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field.
#define ALT_RSTMGR_PER0MODRST_DMA_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMA register field.
#define ALT_RSTMGR_PER0MODRST_DMA_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMA register field.
#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK 0x00010000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMA register field value.
#define ALT_RSTMGR_PER0MODRST_DMA_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMA register field value.
#define ALT_RSTMGR_PER0MODRST_DMA_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMA register field.
#define ALT_RSTMGR_PER0MODRST_DMA_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_RSTMGR_PER0MODRST_DMA field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMA_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_RSTMGR_PER0MODRST_DMA register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SPIM0_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM0_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK 0x00020000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM0 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIM0_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM0 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIM0_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SPIM0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM0_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_RSTMGR_PER0MODRST_SPIM0 field value from a register.
#define ALT_RSTMGR_PER0MODRST_SPIM0_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_RSTMGR_PER0MODRST_SPIM0 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SPIM1_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM1_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIM1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SPIM1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK 0x00040000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SPIM1 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIM1_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIM1 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIM1_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SPIM1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIM1_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_RSTMGR_PER0MODRST_SPIM1 field value from a register.
#define ALT_RSTMGR_PER0MODRST_SPIM1_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_RSTMGR_PER0MODRST_SPIM1 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SPIS0_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS0_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK 0x00080000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS0 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIS0_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS0 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIS0_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SPIS0 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS0_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_RSTMGR_PER0MODRST_SPIS0 field value from a register.
#define ALT_RSTMGR_PER0MODRST_SPIS0_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_RSTMGR_PER0MODRST_SPIS0 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_SPIS1_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS1_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_SPIS1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_SPIS1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK 0x00100000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_SPIS1 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIS1_CLR_MSK 0xffefffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_SPIS1 register field value.
#define ALT_RSTMGR_PER0MODRST_SPIS1_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_SPIS1 register field.
#define ALT_RSTMGR_PER0MODRST_SPIS1_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_RSTMGR_PER0MODRST_SPIS1 field value from a register.
#define ALT_RSTMGR_PER0MODRST_SPIS1_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_RSTMGR_PER0MODRST_SPIS1 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAOCP register field.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAOCP register field.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_SET_MSK 0x00200000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAOCP register field value.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAOCP register field value.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAOCP register field.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAOCP field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAOCP_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAOCP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_EMACPTP register field.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_EMACPTP register field.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK 0x00400000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_EMACPTP register field value.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_EMACPTP register field value.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_EMACPTP register field.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_RSTMGR_PER0MODRST_EMACPTP field value from a register.
#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_RSTMGR_PER0MODRST_EMACPTP register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK 0x01000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF0 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF0 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF0 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF0 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK 0x02000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF1 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF1 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF1 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF1 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK 0x04000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF2 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF2 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF2 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF2 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK 0x08000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF3 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF3 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF3 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF3 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK 0x10000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_CLR_MSK 0xefffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF4 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF4 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF4 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF4 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK 0x20000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_CLR_MSK 0xdfffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF5 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF5 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_GET | ( | value | ) | (((value) & 0x20000000) >> 29) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF5 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET | ( | value | ) | (((value) << 29) & 0x20000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF5 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_LSB 30 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_MSB 30 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK 0x40000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_CLR_MSK 0xbfffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF6 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF6 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_GET | ( | value | ) | (((value) & 0x40000000) >> 30) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF6 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET | ( | value | ) | (((value) << 30) & 0x40000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF6 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_WIDTH 1 |
The width in bits of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK 0x80000000 |
The mask used to set the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_RSTMGR_PER0MODRST_DMAIF7 register field value.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_RESET 0x1 |
The reset value of the ALT_RSTMGR_PER0MODRST_DMAIF7 register field.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_RSTMGR_PER0MODRST_DMAIF7 field value from a register.
#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_RSTMGR_PER0MODRST_DMAIF7 register field value suitable for setting the register.
#define ALT_RSTMGR_PER0MODRST_RESET 0xff7fffff |
The reset value of the ALT_RSTMGR_PER0MODRST register.
#define ALT_RSTMGR_PER0MODRST_OFST 0x24 |
The byte offset of the ALT_RSTMGR_PER0MODRST register from the beginning of the component.
typedef struct ALT_RSTMGR_PER0MODRST_s ALT_RSTMGR_PER0MODRST_t |
The typedef declaration for register ALT_RSTMGR_PER0MODRST.