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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x3 | Read Opcode in non-XIP mode |
[9:8] | RW | 0x0 | Instruction Type |
[11:10] | R | 0x0 | Reserved |
[13:12] | RW | 0x0 | Address Transfer Type for Standard SPI modes |
[15:14] | R | 0x0 | Reserved |
[17:16] | RW | 0x0 | Data Transfer Type for Standard SPI modes |
[19:18] | R | 0x0 | Reserved |
[20] | RW | 0x0 | Mode Bit Enable |
[23:21] | R | 0x0 | Reserved |
[28:24] | RW | 0x0 | Dummy Read Clock Cycles |
[31:29] | R | 0x0 | Reserved |
Field : Read Opcode in non-XIP mode - rdopcode | ||||||||||
Read Opcode to use when not in XIP mode Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_LSB 0 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_MSB 7 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_GET(value) (((value) & 0x000000ff) >> 0) | |||||||||
#define | ALT_QSPI_DEVRD_RDOPCODE_SET(value) (((value) << 0) & 0x000000ff) | |||||||||
Field : Instruction Type - instwidth | ||||||||||||||||||||||||||||
0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions, Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions, Address and Data always sent on DQ0, DQ1, DQ2 and DDQ3) Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_GET(value) (((value) & 0x00000300) >> 8) | |||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_INSTWIDTH_SET(value) (((value) << 8) & 0x00000300) | |||||||||||||||||||||||||||
Field : Reserved - rd_instr_resv1_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET(value) (((value) & 0x00000c00) >> 10) |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET(value) (((value) << 10) & 0x00000c00) |
Field : Address Transfer Type for Standard SPI modes - addrwidth | ||||||||||||||||||||||||||||||||||||||||
0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0, DQ1, DQ2 and DQ3 Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_GET(value) (((value) & 0x00003000) >> 12) | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_ADDRWIDTH_SET(value) (((value) << 12) & 0x00003000) | |||||||||||||||||||||||||||||||||||||||
Field : Reserved - rd_instr_resv2_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET(value) (((value) << 14) & 0x0000c000) |
Field : Data Transfer Type for Standard SPI modes - datawidth | ||||||||||||||||||||||||||||||||||||||||
0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers, DQ0 and DQ1 are used as both inputs and outputs. 2 : Used for Quad Input/Output instructions. For data transfers, DQ0,DQ1,DQ2 and DQ3 are used as both inputs and outputs. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_GET(value) (((value) & 0x00030000) >> 16) | |||||||||||||||||||||||||||||||||||||||
#define | ALT_QSPI_DEVRD_DATAWIDTH_SET(value) (((value) << 16) & 0x00030000) | |||||||||||||||||||||||||||||||||||||||
Field : Reserved - rd_instr_resv3_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET(value) (((value) & 0x000c0000) >> 18) |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET(value) (((value) << 18) & 0x000c0000) |
Field : Mode Bit Enable - enmodebits | ||||||||||
Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_LSB 20 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_MSB 20 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_GET(value) (((value) & 0x00100000) >> 20) | |||||||||
#define | ALT_QSPI_DEVRD_ENMODBITS_SET(value) (((value) << 20) & 0x00100000) | |||||||||
Field : Reserved - rd_instr_resv4_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET(value) (((value) & 0x00e00000) >> 21) |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET(value) (((value) << 21) & 0x00e00000) |
Field : Dummy Read Clock Cycles - dummyrdclks | |
Number of dummy clock cycles required by device for read instruction. Field Access Macros: | |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_GET(value) (((value) & 0x1f000000) >> 24) |
#define | ALT_QSPI_DEVRD_DUMMYRDCLKS_SET(value) (((value) << 24) & 0x1f000000) |
Field : Reserved - rd_instr_resv5_fld | |
Field Access Macros: | |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0 |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET(value) (((value) & 0xe0000000) >> 29) |
#define | ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET(value) (((value) << 29) & 0xe0000000) |
Data Structures | |
struct | ALT_QSPI_DEVRD_s |
Macros | |
#define | ALT_QSPI_DEVRD_RESET 0x00000003 |
#define | ALT_QSPI_DEVRD_OFST 0x4 |
Typedefs | |
typedef struct ALT_QSPI_DEVRD_s | ALT_QSPI_DEVRD_t |
struct ALT_QSPI_DEVRD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_DEVRD.
Data Fields | ||
---|---|---|
uint32_t | rdopcode: 8 | Read Opcode in non-XIP mode |
uint32_t | instwidth: 2 | Instruction Type |
const uint32_t | rd_instr_resv1_fld: 2 | Reserved |
uint32_t | addrwidth: 2 | Address Transfer Type for Standard SPI modes |
const uint32_t | rd_instr_resv2_fld: 2 | Reserved |
uint32_t | datawidth: 2 | Data Transfer Type for Standard SPI modes |
const uint32_t | rd_instr_resv3_fld: 2 | Reserved |
uint32_t | enmodebits: 1 | Mode Bit Enable |
const uint32_t | rd_instr_resv4_fld: 3 | Reserved |
uint32_t | dummyrdclks: 5 | Dummy Read Clock Cycles |
const uint32_t | rd_instr_resv5_fld: 3 | Reserved |
#define ALT_QSPI_DEVRD_RDOPCODE_E_RD 0x3 |
Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
Read Opcode in Non-XIP mode
#define ALT_QSPI_DEVRD_RDOPCODE_E_FASTRD 0xb |
Enumerated value for register field ALT_QSPI_DEVRD_RDOPCODE
Fast Read in Non-XIP mode
#define ALT_QSPI_DEVRD_RDOPCODE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field.
#define ALT_QSPI_DEVRD_RDOPCODE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RDOPCODE register field.
#define ALT_QSPI_DEVRD_RDOPCODE_WIDTH 8 |
The width in bits of the ALT_QSPI_DEVRD_RDOPCODE register field.
#define ALT_QSPI_DEVRD_RDOPCODE_SET_MSK 0x000000ff |
The mask used to set the ALT_QSPI_DEVRD_RDOPCODE register field value.
#define ALT_QSPI_DEVRD_RDOPCODE_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_QSPI_DEVRD_RDOPCODE register field value.
#define ALT_QSPI_DEVRD_RDOPCODE_RESET 0x3 |
The reset value of the ALT_QSPI_DEVRD_RDOPCODE register field.
#define ALT_QSPI_DEVRD_RDOPCODE_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_QSPI_DEVRD_RDOPCODE field value from a register.
#define ALT_QSPI_DEVRD_RDOPCODE_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_QSPI_DEVRD_RDOPCODE register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_INSTWIDTH_E_SINGLE 0x0 |
Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
Instruction transferred on DQ0. Supported by all SPI flash devices.
#define ALT_QSPI_DEVRD_INSTWIDTH_E_DUAL 0x1 |
Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
Instruction transferred on DQ0 and DQ1. Supported by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_INSTWIDTH_E_QUAD 0x2 |
Enumerated value for register field ALT_QSPI_DEVRD_INSTWIDTH
Instruction transferred on DQ0, DQ1, DQ2, and DQ3. Supported by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_INSTWIDTH_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field.
#define ALT_QSPI_DEVRD_INSTWIDTH_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_INSTWIDTH register field.
#define ALT_QSPI_DEVRD_INSTWIDTH_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_INSTWIDTH register field.
#define ALT_QSPI_DEVRD_INSTWIDTH_SET_MSK 0x00000300 |
The mask used to set the ALT_QSPI_DEVRD_INSTWIDTH register field value.
#define ALT_QSPI_DEVRD_INSTWIDTH_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_QSPI_DEVRD_INSTWIDTH register field value.
#define ALT_QSPI_DEVRD_INSTWIDTH_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_INSTWIDTH register field.
#define ALT_QSPI_DEVRD_INSTWIDTH_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_QSPI_DEVRD_INSTWIDTH field value from a register.
#define ALT_QSPI_DEVRD_INSTWIDTH_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_QSPI_DEVRD_INSTWIDTH register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET_MSK 0x00000c00 |
The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_CLR_MSK 0xfffff3ff |
The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_GET | ( | value | ) | (((value) & 0x00000c00) >> 10) |
Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD field value from a register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD_SET | ( | value | ) | (((value) << 10) & 0x00000c00) |
Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV1_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_SINGLE 0x0 |
Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
Read address transferred on DQ0. Supported by all SPI flash devices
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_DUAL 0x1 |
Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
Read address transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_ADDRWIDTH_E_QUAD 0x2 |
Enumerated value for register field ALT_QSPI_DEVRD_ADDRWIDTH
Read address transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_ADDRWIDTH_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field.
#define ALT_QSPI_DEVRD_ADDRWIDTH_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ADDRWIDTH register field.
#define ALT_QSPI_DEVRD_ADDRWIDTH_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_ADDRWIDTH register field.
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET_MSK 0x00003000 |
The mask used to set the ALT_QSPI_DEVRD_ADDRWIDTH register field value.
#define ALT_QSPI_DEVRD_ADDRWIDTH_CLR_MSK 0xffffcfff |
The mask used to clear the ALT_QSPI_DEVRD_ADDRWIDTH register field value.
#define ALT_QSPI_DEVRD_ADDRWIDTH_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_ADDRWIDTH register field.
#define ALT_QSPI_DEVRD_ADDRWIDTH_GET | ( | value | ) | (((value) & 0x00003000) >> 12) |
Extracts the ALT_QSPI_DEVRD_ADDRWIDTH field value from a register.
#define ALT_QSPI_DEVRD_ADDRWIDTH_SET | ( | value | ) | (((value) << 12) & 0x00003000) |
Produces a ALT_QSPI_DEVRD_ADDRWIDTH register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET_MSK 0x0000c000 |
The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD field value from a register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV2_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_DATAWIDTH_E_SINGLE 0x0 |
Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
Read data transferred on DQ0. Supported by all SPI flash devices
#define ALT_QSPI_DEVRD_DATAWIDTH_E_DUAL 0x1 |
Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
Read data transferred on DQ0 and DQ1. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Dual SP (DIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_DATAWIDTH_E_QUAD 0x2 |
Enumerated value for register field ALT_QSPI_DEVRD_DATAWIDTH
Read data transferred on DQ0, DQ1, DQ2, and DQ3. Supported by some SPI flash devices that support the Extended SPI Protocol and by all SPI flash devices that support the Quad SP (QIO-SPI) Protocol.
#define ALT_QSPI_DEVRD_DATAWIDTH_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field.
#define ALT_QSPI_DEVRD_DATAWIDTH_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DATAWIDTH register field.
#define ALT_QSPI_DEVRD_DATAWIDTH_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_DATAWIDTH register field.
#define ALT_QSPI_DEVRD_DATAWIDTH_SET_MSK 0x00030000 |
The mask used to set the ALT_QSPI_DEVRD_DATAWIDTH register field value.
#define ALT_QSPI_DEVRD_DATAWIDTH_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_QSPI_DEVRD_DATAWIDTH register field value.
#define ALT_QSPI_DEVRD_DATAWIDTH_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_DATAWIDTH register field.
#define ALT_QSPI_DEVRD_DATAWIDTH_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_QSPI_DEVRD_DATAWIDTH field value from a register.
#define ALT_QSPI_DEVRD_DATAWIDTH_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_QSPI_DEVRD_DATAWIDTH register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_WIDTH 2 |
The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET_MSK 0x000c0000 |
The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_CLR_MSK 0xfff3ffff |
The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_GET | ( | value | ) | (((value) & 0x000c0000) >> 18) |
Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD field value from a register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD_SET | ( | value | ) | (((value) << 18) & 0x000c0000) |
Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV3_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_ENMODBITS_E_NOORDER 0x0 |
Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
No Order
#define ALT_QSPI_DEVRD_ENMODBITS_E_ORDER 0x1 |
Enumerated value for register field ALT_QSPI_DEVRD_ENMODBITS
Mode Bits follow address bytes
#define ALT_QSPI_DEVRD_ENMODBITS_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field.
#define ALT_QSPI_DEVRD_ENMODBITS_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_ENMODBITS register field.
#define ALT_QSPI_DEVRD_ENMODBITS_WIDTH 1 |
The width in bits of the ALT_QSPI_DEVRD_ENMODBITS register field.
#define ALT_QSPI_DEVRD_ENMODBITS_SET_MSK 0x00100000 |
The mask used to set the ALT_QSPI_DEVRD_ENMODBITS register field value.
#define ALT_QSPI_DEVRD_ENMODBITS_CLR_MSK 0xffefffff |
The mask used to clear the ALT_QSPI_DEVRD_ENMODBITS register field value.
#define ALT_QSPI_DEVRD_ENMODBITS_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_ENMODBITS register field.
#define ALT_QSPI_DEVRD_ENMODBITS_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_QSPI_DEVRD_ENMODBITS field value from a register.
#define ALT_QSPI_DEVRD_ENMODBITS_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_QSPI_DEVRD_ENMODBITS register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_WIDTH 3 |
The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET_MSK 0x00e00000 |
The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_CLR_MSK 0xff1fffff |
The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_GET | ( | value | ) | (((value) & 0x00e00000) >> 21) |
Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD field value from a register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD_SET | ( | value | ) | (((value) << 21) & 0x00e00000) |
Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV4_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_WIDTH 5 |
The width in bits of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET_MSK 0x1f000000 |
The mask used to set the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_CLR_MSK 0xe0ffffff |
The mask used to clear the ALT_QSPI_DEVRD_DUMMYRDCLKS register field value.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_DUMMYRDCLKS register field.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_GET | ( | value | ) | (((value) & 0x1f000000) >> 24) |
Extracts the ALT_QSPI_DEVRD_DUMMYRDCLKS field value from a register.
#define ALT_QSPI_DEVRD_DUMMYRDCLKS_SET | ( | value | ) | (((value) << 24) & 0x1f000000) |
Produces a ALT_QSPI_DEVRD_DUMMYRDCLKS register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_WIDTH 3 |
The width in bits of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET_MSK 0xe0000000 |
The mask used to set the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_CLR_MSK 0x1fffffff |
The mask used to clear the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_RESET 0x0 |
The reset value of the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_GET | ( | value | ) | (((value) & 0xe0000000) >> 29) |
Extracts the ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD field value from a register.
#define ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD_SET | ( | value | ) | (((value) << 29) & 0xe0000000) |
Produces a ALT_QSPI_DEVRD_RD_INSTR_RESV5_FLD register field value suitable for setting the register.
#define ALT_QSPI_DEVRD_RESET 0x00000003 |
The reset value of the ALT_QSPI_DEVRD register.
#define ALT_QSPI_DEVRD_OFST 0x4 |
The byte offset of the ALT_QSPI_DEVRD register from the beginning of the component.
typedef struct ALT_QSPI_DEVRD_s ALT_QSPI_DEVRD_t |
The typedef declaration for register ALT_QSPI_DEVRD.