Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Status Register - stat

Description

The STAT register contains bits that indicate the reset source or a timeout event. For reset sources, a field is 1 if its associated reset requester caused the reset. For timeout events, a field is 1 if its associated timeout occured as part of a hardware sequenced warm/debug reset.

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s) de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0.

After a warm reset is complete, the bit(s) that indicate the source of the warm reset are set to 1. A warm reset doesn't clear any of the bits in the STAT register; these bits must be cleared by software writing the STAT register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Power-On Voltage Detector Cold Reset
[1] RW 0x0 nPOR Pin Cold Reset
[2] RW 0x0 FPGA Core Cold Reset
[3] RW 0x0 CONFIG_IO Cold Reset
[4] RW 0x0 Software Cold Reset
[7:5] ??? 0x0 UNDEFINED
[8] RW 0x0 nRST Pin Warm Reset
[9] RW 0x0 FPGA Core Warm Reset
[10] RW 0x0 Software Warm Reset
[11] ??? 0x0 UNDEFINED
[12] RW 0x0 MPU Watchdog 0 Warm Reset
[13] RW 0x0 MPU Watchdog 1 Warm Reset
[14] RW 0x0 L4 Watchdog 0 Warm Reset
[15] RW 0x0 L4 Watchdog 1 Warm Reset
[17:16] ??? 0x0 UNDEFINED
[18] RW 0x0 FPGA Core Debug Reset
[19] RW 0x0 DAP Debug Reset
[23:20] ??? 0x0 UNDEFINED
[24] RW 0x0 SDRAM Self-Refresh Timeout
[25] RW 0x0 FPGA manager handshake Timeout
[26] RW 0x0 SCAN manager handshake Timeout
[27] RW 0x0 FPGA handshake Timeout
[28] RW 0x0 ETR Stall Timeout
[31:29] ??? 0x0 UNDEFINED

Field : Power-On Voltage Detector Cold Reset - porvoltrst

Built-in POR voltage detector triggered a cold reset (por_voltage_req = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_PORVOLTRST_LSB   0
 
#define ALT_RSTMGR_STAT_PORVOLTRST_MSB   0
 
#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK   0x00000001
 
#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_STAT_PORVOLTRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_PORVOLTRST_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_STAT_PORVOLTRST_SET(value)   (((value) << 0) & 0x00000001)
 

Field : nPOR Pin Cold Reset - nporpinrst

nPOR pin triggered a cold reset (por_pin_req = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_NPORPINRST_LSB   1
 
#define ALT_RSTMGR_STAT_NPORPINRST_MSB   1
 
#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK   0x00000002
 
#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_STAT_NPORPINRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_NPORPINRST_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_STAT_NPORPINRST_SET(value)   (((value) << 1) & 0x00000002)
 

Field : FPGA Core Cold Reset - fpgacoldrst

FPGA core triggered a cold reset (f2h_cold_rst_req_n = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB   2
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB   2
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK   0x00000004
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value)   (((value) << 2) & 0x00000004)
 

Field : CONFIG_IO Cold Reset - configiocoldrst

FPGA entered CONFIG_IO mode and a triggered a cold reset

Field Access Macros:

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB   3
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB   3
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK   0x00000008
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Software Cold Reset - swcoldrst

Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset

Field Access Macros:

#define ALT_RSTMGR_STAT_SWCOLDRST_LSB   4
 
#define ALT_RSTMGR_STAT_SWCOLDRST_MSB   4
 
#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK   0x00000010
 
#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK   0xffffffef
 
#define ALT_RSTMGR_STAT_SWCOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value)   (((value) << 4) & 0x00000010)
 

Field : nRST Pin Warm Reset - nrstpinrst

nRST pin triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_NRSTPINRST_LSB   8
 
#define ALT_RSTMGR_STAT_NRSTPINRST_MSB   8
 
#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK   0x00000100
 
#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK   0xfffffeff
 
#define ALT_RSTMGR_STAT_NRSTPINRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value)   (((value) << 8) & 0x00000100)
 

Field : FPGA Core Warm Reset - fpgawarmrst

FPGA core triggered a hardware sequenced warm reset (f2h_warm_rst_req_n = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB   9
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB   9
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK   0x00000200
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK   0xfffffdff
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Software Warm Reset - swwarmrst

Software wrote CTRL.SWWARMRSTREQ to 1 and triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_SWWARMRST_LSB   10
 
#define ALT_RSTMGR_STAT_SWWARMRST_MSB   10
 
#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK   0x00000400
 
#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK   0xfffffbff
 
#define ALT_RSTMGR_STAT_SWWARMRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_SWWARMRST_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_RSTMGR_STAT_SWWARMRST_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MPU Watchdog 0 Warm Reset - mpuwd0rst

MPU Watchdog 0 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_MPUWD0RST_LSB   12
 
#define ALT_RSTMGR_STAT_MPUWD0RST_MSB   12
 
#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK   0x00001000
 
#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK   0xffffefff
 
#define ALT_RSTMGR_STAT_MPUWD0RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value)   (((value) << 12) & 0x00001000)
 

Field : MPU Watchdog 1 Warm Reset - mpuwd1rst

MPU Watchdog 1 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_MPUWD1RST_LSB   13
 
#define ALT_RSTMGR_STAT_MPUWD1RST_MSB   13
 
#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK   0x00002000
 
#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK   0xffffdfff
 
#define ALT_RSTMGR_STAT_MPUWD1RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value)   (((value) << 13) & 0x00002000)
 

Field : L4 Watchdog 0 Warm Reset - l4wd0rst

L4 Watchdog 0 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_L4WD0RST_LSB   14
 
#define ALT_RSTMGR_STAT_L4WD0RST_MSB   14
 
#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK   0x00004000
 
#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK   0xffffbfff
 
#define ALT_RSTMGR_STAT_L4WD0RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_L4WD0RST_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_RSTMGR_STAT_L4WD0RST_SET(value)   (((value) << 14) & 0x00004000)
 

Field : L4 Watchdog 1 Warm Reset - l4wd1rst

L4 Watchdog 1 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_L4WD1RST_LSB   15
 
#define ALT_RSTMGR_STAT_L4WD1RST_MSB   15
 
#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK   0x00008000
 
#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK   0xffff7fff
 
#define ALT_RSTMGR_STAT_L4WD1RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_L4WD1RST_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_RSTMGR_STAT_L4WD1RST_SET(value)   (((value) << 15) & 0x00008000)
 

Field : FPGA Core Debug Reset - fpgadbgrst

FPGA triggered debug reset (f2h_dbg_rst_req_n = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGADBGRST_LSB   18
 
#define ALT_RSTMGR_STAT_FPGADBGRST_MSB   18
 
#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK   0x00040000
 
#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK   0xfffbffff
 
#define ALT_RSTMGR_STAT_FPGADBGRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value)   (((value) << 18) & 0x00040000)
 

Field : DAP Debug Reset - cdbgreqrst

DAP triggered debug reset

Field Access Macros:

#define ALT_RSTMGR_STAT_CDBGREQRST_LSB   19
 
#define ALT_RSTMGR_STAT_CDBGREQRST_MSB   19
 
#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK   0x00080000
 
#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK   0xfff7ffff
 
#define ALT_RSTMGR_STAT_CDBGREQRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value)   (((value) << 19) & 0x00080000)
 

Field : SDRAM Self-Refresh Timeout - sdrselfreftimeout

A 1 indicates that Reset Manager's request to the SDRAM Controller Subsystem to put the SDRAM devices into self-refresh mode before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB   24
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB   24
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH   1
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK   0x01000000
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK   0xfeffffff
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET   0x0
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET(value)   (((value) << 24) & 0x01000000)
 

Field : FPGA manager handshake Timeout - fpgamgrhstimeout

A 1 indicates that Reset Manager's request to the FPGA manager to stop driving configuration clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB   25
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB   25
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK   0x02000000
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK   0xfdffffff
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET(value)   (((value) << 25) & 0x02000000)
 

Field : SCAN manager handshake Timeout - scanhstimeout

A 1 indicates that Reset Manager's request to the SCAN manager to stop driving JTAG clock to FPGA CB before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_STAT_SCANHSTMO_LSB   26
 
#define ALT_RSTMGR_STAT_SCANHSTMO_MSB   26
 
#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH   1
 
#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK   0x04000000
 
#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK   0xfbffffff
 
#define ALT_RSTMGR_STAT_SCANHSTMO_RESET   0x0
 
#define ALT_RSTMGR_STAT_SCANHSTMO_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_RSTMGR_STAT_SCANHSTMO_SET(value)   (((value) << 26) & 0x04000000)
 

Field : FPGA handshake Timeout - fpgahstimeout

A 1 indicates that Reset Manager's handshake request to FPGA before starting a hardware sequenced warm reset timed-out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB   27
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB   27
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK   0x08000000
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK   0xf7ffffff
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_RSTMGR_STAT_FPGAHSTMO_SET(value)   (((value) << 27) & 0x08000000)
 

Field : ETR Stall Timeout - etrstalltimeout

A 1 indicates that Reset Manager's request to the ETR (Embedded Trace Router) to stall its AXI master port before starting a hardware sequenced warm reset timed- out and the Reset Manager had to proceed with the warm reset anyway.

Field Access Macros:

#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB   28
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB   28
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH   1
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK   0x10000000
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK   0xefffffff
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET   0x0
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET(value)   (((value) & 0x10000000) >> 28)
 
#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET(value)   (((value) << 28) & 0x10000000)
 

Data Structures

struct  ALT_RSTMGR_STAT_s
 

Macros

#define ALT_RSTMGR_STAT_OFST   0x0
 

Typedefs

typedef struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t
 

Data Structure Documentation

struct ALT_RSTMGR_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_STAT.

Data Fields
uint32_t porvoltrst: 1 Power-On Voltage Detector Cold Reset
uint32_t nporpinrst: 1 nPOR Pin Cold Reset
uint32_t fpgacoldrst: 1 FPGA Core Cold Reset
uint32_t configiocoldrst: 1 CONFIG_IO Cold Reset
uint32_t swcoldrst: 1 Software Cold Reset
uint32_t __pad0__: 3 UNDEFINED
uint32_t nrstpinrst: 1 nRST Pin Warm Reset
uint32_t fpgawarmrst: 1 FPGA Core Warm Reset
uint32_t swwarmrst: 1 Software Warm Reset
uint32_t __pad1__: 1 UNDEFINED
uint32_t mpuwd0rst: 1 MPU Watchdog 0 Warm Reset
uint32_t mpuwd1rst: 1 MPU Watchdog 1 Warm Reset
uint32_t l4wd0rst: 1 L4 Watchdog 0 Warm Reset
uint32_t l4wd1rst: 1 L4 Watchdog 1 Warm Reset
uint32_t __pad2__: 2 UNDEFINED
uint32_t fpgadbgrst: 1 FPGA Core Debug Reset
uint32_t cdbgreqrst: 1 DAP Debug Reset
uint32_t __pad3__: 4 UNDEFINED
uint32_t sdrselfreftimeout: 1 SDRAM Self-Refresh Timeout
uint32_t fpgamgrhstimeout: 1 FPGA manager handshake Timeout
uint32_t scanhstimeout: 1 SCAN manager handshake Timeout
uint32_t fpgahstimeout: 1 FPGA handshake Timeout
uint32_t etrstalltimeout: 1 ETR Stall Timeout
uint32_t __pad4__: 3 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_STAT_PORVOLTRST_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field.

#define ALT_RSTMGR_STAT_PORVOLTRST_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORVOLTRST register field.

#define ALT_RSTMGR_STAT_PORVOLTRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_PORVOLTRST register field.

#define ALT_RSTMGR_STAT_PORVOLTRST_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_STAT_PORVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORVOLTRST_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_STAT_PORVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORVOLTRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_PORVOLTRST register field.

#define ALT_RSTMGR_STAT_PORVOLTRST_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_STAT_PORVOLTRST field value from a register.

#define ALT_RSTMGR_STAT_PORVOLTRST_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_STAT_PORVOLTRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_NPORPINRST_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value.

#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value.

#define ALT_RSTMGR_STAT_NPORPINRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register.

#define ALT_RSTMGR_STAT_NPORPINRST_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value.

#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value.

#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register.

#define ALT_RSTMGR_STAT_FPGACOLDRST_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SWCOLDRST_LSB   4

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_MSB   4

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK   0x00000010

The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value.

#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK   0xffffffef

The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value.

#define ALT_RSTMGR_STAT_SWCOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register.

#define ALT_RSTMGR_STAT_SWCOLDRST_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_NRSTPINRST_LSB   8

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_MSB   8

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK   0x00000100

The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value.

#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK   0xfffffeff

The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value.

#define ALT_RSTMGR_STAT_NRSTPINRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register.

#define ALT_RSTMGR_STAT_NRSTPINRST_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB   9

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB   9

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK   0x00000200

The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value.

#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK   0xfffffdff

The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value.

#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register.

#define ALT_RSTMGR_STAT_FPGAWARMRST_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SWWARMRST_LSB   10

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_MSB   10

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK   0x00000400

The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value.

#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK   0xfffffbff

The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value.

#define ALT_RSTMGR_STAT_SWWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register.

#define ALT_RSTMGR_STAT_SWWARMRST_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_MPUWD0RST_LSB   12

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_MSB   12

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK   0x00001000

The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value.

#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK   0xffffefff

The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value.

#define ALT_RSTMGR_STAT_MPUWD0RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register.

#define ALT_RSTMGR_STAT_MPUWD0RST_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_MPUWD1RST_LSB   13

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_MSB   13

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK   0x00002000

The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value.

#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK   0xffffdfff

The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value.

#define ALT_RSTMGR_STAT_MPUWD1RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register.

#define ALT_RSTMGR_STAT_MPUWD1RST_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_L4WD0RST_LSB   14

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_MSB   14

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK   0x00004000

The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value.

#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK   0xffffbfff

The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value.

#define ALT_RSTMGR_STAT_L4WD0RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register.

#define ALT_RSTMGR_STAT_L4WD0RST_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_L4WD1RST_LSB   15

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_MSB   15

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK   0x00008000

The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value.

#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK   0xffff7fff

The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value.

#define ALT_RSTMGR_STAT_L4WD1RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register.

#define ALT_RSTMGR_STAT_L4WD1RST_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGADBGRST_LSB   18

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_MSB   18

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK   0x00040000

The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value.

#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK   0xfffbffff

The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value.

#define ALT_RSTMGR_STAT_FPGADBGRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register.

#define ALT_RSTMGR_STAT_FPGADBGRST_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_CDBGREQRST_LSB   19

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_MSB   19

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK   0x00080000

The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value.

#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value.

#define ALT_RSTMGR_STAT_CDBGREQRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register.

#define ALT_RSTMGR_STAT_CDBGREQRST_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_LSB   24

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_MSB   24

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET_MSK   0x01000000

The mask used to set the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_CLR_MSK   0xfeffffff

The mask used to clear the ALT_RSTMGR_STAT_SDRSELFREFTMO register field value.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SDRSELFREFTMO register field.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_RSTMGR_STAT_SDRSELFREFTMO field value from a register.

#define ALT_RSTMGR_STAT_SDRSELFREFTMO_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_RSTMGR_STAT_SDRSELFREFTMO register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_LSB   25

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_MSB   25

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET_MSK   0x02000000

The mask used to set the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_CLR_MSK   0xfdffffff

The mask used to clear the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGAMGRHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_RSTMGR_STAT_FPGAMGRHSTMO field value from a register.

#define ALT_RSTMGR_STAT_FPGAMGRHSTMO_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_RSTMGR_STAT_FPGAMGRHSTMO register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SCANHSTMO_LSB   26

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field.

#define ALT_RSTMGR_STAT_SCANHSTMO_MSB   26

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SCANHSTMO register field.

#define ALT_RSTMGR_STAT_SCANHSTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SCANHSTMO register field.

#define ALT_RSTMGR_STAT_SCANHSTMO_SET_MSK   0x04000000

The mask used to set the ALT_RSTMGR_STAT_SCANHSTMO register field value.

#define ALT_RSTMGR_STAT_SCANHSTMO_CLR_MSK   0xfbffffff

The mask used to clear the ALT_RSTMGR_STAT_SCANHSTMO register field value.

#define ALT_RSTMGR_STAT_SCANHSTMO_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SCANHSTMO register field.

#define ALT_RSTMGR_STAT_SCANHSTMO_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_RSTMGR_STAT_SCANHSTMO field value from a register.

#define ALT_RSTMGR_STAT_SCANHSTMO_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_RSTMGR_STAT_SCANHSTMO register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGAHSTMO_LSB   27

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAHSTMO_MSB   27

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAHSTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGAHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAHSTMO_SET_MSK   0x08000000

The mask used to set the ALT_RSTMGR_STAT_FPGAHSTMO register field value.

#define ALT_RSTMGR_STAT_FPGAHSTMO_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_RSTMGR_STAT_FPGAHSTMO register field value.

#define ALT_RSTMGR_STAT_FPGAHSTMO_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGAHSTMO register field.

#define ALT_RSTMGR_STAT_FPGAHSTMO_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_RSTMGR_STAT_FPGAHSTMO field value from a register.

#define ALT_RSTMGR_STAT_FPGAHSTMO_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_RSTMGR_STAT_FPGAHSTMO register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_LSB   28

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_MSB   28

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET_MSK   0x10000000

The mask used to set the ALT_RSTMGR_STAT_ETRSTALLTMO register field value.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_CLR_MSK   0xefffffff

The mask used to clear the ALT_RSTMGR_STAT_ETRSTALLTMO register field value.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_ETRSTALLTMO register field.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_GET (   value)    (((value) & 0x10000000) >> 28)

Extracts the ALT_RSTMGR_STAT_ETRSTALLTMO field value from a register.

#define ALT_RSTMGR_STAT_ETRSTALLTMO_SET (   value)    (((value) << 28) & 0x10000000)

Produces a ALT_RSTMGR_STAT_ETRSTALLTMO register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_OFST   0x0

The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_STAT.