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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register reports the status of the SPI Slave interrupts prior to masking.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | Transmit FIFO Empty Raw Interrupt Status |
[1] | R | 0x0 | Transmit FIFO Overflow Raw Interrupt Status |
[2] | R | 0x0 | Receive FIFO Underflow Raw Interrupt Status |
[3] | R | 0x0 | Receive FIFO Overflow Raw Interrupt Status |
[4] | R | 0x0 | Receive FIFO Full Raw Interrupt Status |
[31:5] | ??? | 0x0 | UNDEFINED |
Field : Transmit FIFO Empty Raw Interrupt Status - txeir | |||||||||||||
The interrupt is active or inactive prior to masking. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SPIS_RISR_TXEIR_E_INACT 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_E_ACT 0x1 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_LSB 0 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_MSB 0 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_WIDTH 1 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_RESET 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0) | ||||||||||||
#define | ALT_SPIS_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001) | ||||||||||||
Field : Transmit FIFO Overflow Raw Interrupt Status - txoir | |||||||||||||
The interrupt is active or inactive prior to masking. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SPIS_RISR_TXOIR_E_INACT 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_E_ACT 0x1 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_LSB 1 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_MSB 1 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_WIDTH 1 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_RESET 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1) | ||||||||||||
#define | ALT_SPIS_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002) | ||||||||||||
Field : Receive FIFO Underflow Raw Interrupt Status - rxuir | ||||||||||||||||
The interrupt is active or inactive prior to masking. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_E_INACT 0x0 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_E_ACT 0x1 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_LSB 2 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_MSB 2 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_WIDTH 1 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_RESET 0x0 | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2) | |||||||||||||||
#define | ALT_SPIS_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004) | |||||||||||||||
Field : Receive FIFO Overflow Raw Interrupt Status - rxoir | |||||||||||||
The interrupt is active or inactive prior to masking. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SPIS_RISR_RXOIR_E_INACT 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_E_ACT 0x1 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_LSB 3 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_MSB 3 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_WIDTH 1 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_RESET 0x0 | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3) | ||||||||||||
#define | ALT_SPIS_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008) | ||||||||||||
Field : Receive FIFO Full Raw Interrupt Status - rxfir | ||||||||||||||||
The interrupt is active or inactive prior to masking. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_E_INACT 0x0 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_E_ACT 0x1 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_LSB 4 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_MSB 4 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_WIDTH 1 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_RESET 0x0 | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4) | |||||||||||||||
#define | ALT_SPIS_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010) | |||||||||||||||
Data Structures | |
struct | ALT_SPIS_RISR_s |
Macros | |
#define | ALT_SPIS_RISR_OFST 0x34 |
#define | ALT_SPIS_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST)) |
Typedefs | |
typedef struct ALT_SPIS_RISR_s | ALT_SPIS_RISR_t |
struct ALT_SPIS_RISR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SPIS_RISR.
Data Fields | ||
---|---|---|
const uint32_t | txeir: 1 | Transmit FIFO Empty Raw Interrupt Status |
const uint32_t | txoir: 1 | Transmit FIFO Overflow Raw Interrupt Status |
const uint32_t | rxuir: 1 | Receive FIFO Underflow Raw Interrupt Status |
const uint32_t | rxoir: 1 | Receive FIFO Overflow Raw Interrupt Status |
const uint32_t | rxfir: 1 | Receive FIFO Full Raw Interrupt Status |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_SPIS_RISR_TXEIR_E_INACT 0x0 |
Enumerated value for register field ALT_SPIS_RISR_TXEIR
spi_txe_intr interrupt is not active prior to masking
#define ALT_SPIS_RISR_TXEIR_E_ACT 0x1 |
Enumerated value for register field ALT_SPIS_RISR_TXEIR
spi_txe_intr interrupt is active prior masking
#define ALT_SPIS_RISR_TXEIR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXEIR register field.
#define ALT_SPIS_RISR_TXEIR_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXEIR register field.
#define ALT_SPIS_RISR_TXEIR_WIDTH 1 |
The width in bits of the ALT_SPIS_RISR_TXEIR register field.
#define ALT_SPIS_RISR_TXEIR_SET_MSK 0x00000001 |
The mask used to set the ALT_SPIS_RISR_TXEIR register field value.
#define ALT_SPIS_RISR_TXEIR_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SPIS_RISR_TXEIR register field value.
#define ALT_SPIS_RISR_TXEIR_RESET 0x0 |
The reset value of the ALT_SPIS_RISR_TXEIR register field.
#define ALT_SPIS_RISR_TXEIR_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SPIS_RISR_TXEIR field value from a register.
#define ALT_SPIS_RISR_TXEIR_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SPIS_RISR_TXEIR register field value suitable for setting the register.
#define ALT_SPIS_RISR_TXOIR_E_INACT 0x0 |
Enumerated value for register field ALT_SPIS_RISR_TXOIR
spi_txo_intr interrupt is not active prior to masking
#define ALT_SPIS_RISR_TXOIR_E_ACT 0x1 |
Enumerated value for register field ALT_SPIS_RISR_TXOIR
spi_txo_intr interrupt is active prior masking
#define ALT_SPIS_RISR_TXOIR_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_TXOIR register field.
#define ALT_SPIS_RISR_TXOIR_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_TXOIR register field.
#define ALT_SPIS_RISR_TXOIR_WIDTH 1 |
The width in bits of the ALT_SPIS_RISR_TXOIR register field.
#define ALT_SPIS_RISR_TXOIR_SET_MSK 0x00000002 |
The mask used to set the ALT_SPIS_RISR_TXOIR register field value.
#define ALT_SPIS_RISR_TXOIR_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SPIS_RISR_TXOIR register field value.
#define ALT_SPIS_RISR_TXOIR_RESET 0x0 |
The reset value of the ALT_SPIS_RISR_TXOIR register field.
#define ALT_SPIS_RISR_TXOIR_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SPIS_RISR_TXOIR field value from a register.
#define ALT_SPIS_RISR_TXOIR_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SPIS_RISR_TXOIR register field value suitable for setting the register.
#define ALT_SPIS_RISR_RXUIR_E_INACT 0x0 |
Enumerated value for register field ALT_SPIS_RISR_RXUIR
spi_rxu_intr interrupt is not active prior to masking
#define ALT_SPIS_RISR_RXUIR_E_ACT 0x1 |
Enumerated value for register field ALT_SPIS_RISR_RXUIR
spi_rxu_intr interrupt is active prior to masking
#define ALT_SPIS_RISR_RXUIR_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXUIR register field.
#define ALT_SPIS_RISR_RXUIR_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXUIR register field.
#define ALT_SPIS_RISR_RXUIR_WIDTH 1 |
The width in bits of the ALT_SPIS_RISR_RXUIR register field.
#define ALT_SPIS_RISR_RXUIR_SET_MSK 0x00000004 |
The mask used to set the ALT_SPIS_RISR_RXUIR register field value.
#define ALT_SPIS_RISR_RXUIR_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SPIS_RISR_RXUIR register field value.
#define ALT_SPIS_RISR_RXUIR_RESET 0x0 |
The reset value of the ALT_SPIS_RISR_RXUIR register field.
#define ALT_SPIS_RISR_RXUIR_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SPIS_RISR_RXUIR field value from a register.
#define ALT_SPIS_RISR_RXUIR_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SPIS_RISR_RXUIR register field value suitable for setting the register.
#define ALT_SPIS_RISR_RXOIR_E_INACT 0x0 |
Enumerated value for register field ALT_SPIS_RISR_RXOIR
spi_rxo_intr interrupt is not active prior to masking
#define ALT_SPIS_RISR_RXOIR_E_ACT 0x1 |
Enumerated value for register field ALT_SPIS_RISR_RXOIR
spi_rxo_intr interrupt is active prior masking
#define ALT_SPIS_RISR_RXOIR_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXOIR register field.
#define ALT_SPIS_RISR_RXOIR_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXOIR register field.
#define ALT_SPIS_RISR_RXOIR_WIDTH 1 |
The width in bits of the ALT_SPIS_RISR_RXOIR register field.
#define ALT_SPIS_RISR_RXOIR_SET_MSK 0x00000008 |
The mask used to set the ALT_SPIS_RISR_RXOIR register field value.
#define ALT_SPIS_RISR_RXOIR_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SPIS_RISR_RXOIR register field value.
#define ALT_SPIS_RISR_RXOIR_RESET 0x0 |
The reset value of the ALT_SPIS_RISR_RXOIR register field.
#define ALT_SPIS_RISR_RXOIR_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SPIS_RISR_RXOIR field value from a register.
#define ALT_SPIS_RISR_RXOIR_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SPIS_RISR_RXOIR register field value suitable for setting the register.
#define ALT_SPIS_RISR_RXFIR_E_INACT 0x0 |
Enumerated value for register field ALT_SPIS_RISR_RXFIR
spi_rxf_intr interrupt is not active prior to masking
#define ALT_SPIS_RISR_RXFIR_E_ACT 0x1 |
Enumerated value for register field ALT_SPIS_RISR_RXFIR
spi_rxf_intr interrupt is active prior to masking
#define ALT_SPIS_RISR_RXFIR_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SPIS_RISR_RXFIR register field.
#define ALT_SPIS_RISR_RXFIR_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SPIS_RISR_RXFIR register field.
#define ALT_SPIS_RISR_RXFIR_WIDTH 1 |
The width in bits of the ALT_SPIS_RISR_RXFIR register field.
#define ALT_SPIS_RISR_RXFIR_SET_MSK 0x00000010 |
The mask used to set the ALT_SPIS_RISR_RXFIR register field value.
#define ALT_SPIS_RISR_RXFIR_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SPIS_RISR_RXFIR register field value.
#define ALT_SPIS_RISR_RXFIR_RESET 0x0 |
The reset value of the ALT_SPIS_RISR_RXFIR register field.
#define ALT_SPIS_RISR_RXFIR_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SPIS_RISR_RXFIR field value from a register.
#define ALT_SPIS_RISR_RXFIR_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SPIS_RISR_RXFIR register field value suitable for setting the register.
#define ALT_SPIS_RISR_OFST 0x34 |
The byte offset of the ALT_SPIS_RISR register from the beginning of the component.
#define ALT_SPIS_RISR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_RISR_OFST)) |
The address of the ALT_SPIS_RISR register.
typedef struct ALT_SPIS_RISR_s ALT_SPIS_RISR_t |
The typedef declaration for register ALT_SPIS_RISR.