Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Component : ALT_PINMUX_SHARED_3V_IO_GRP

Description

Members

 Register : Shared IO 48 Q1 1 Mux Selection Register - pinmux_shared_io_q1_1
 
 Register : Shared IO 48 Q1 2 Mux Selection Register - pinmux_shared_io_q1_2
 
 Register : Shared IO 48 Q1 3 Mux Selection Register - pinmux_shared_io_q1_3
 
 Register : Shared IO 48 Q1 4 Mux Selection Register - pinmux_shared_io_q1_4
 
 Register : Shared IO 48 Q1 5 Mux Selection Register - pinmux_shared_io_q1_5
 
 Register : Shared IO 48 Q1 6 Mux Selection Register - pinmux_shared_io_q1_6
 
 Register : Shared IO 48 Q1 7 Mux Selection Register - pinmux_shared_io_q1_7
 
 Register : Shared IO 48 Q1 8 Mux Selection Register - pinmux_shared_io_q1_8
 
 Register : Shared IO 48 Q1 9 Mux Selection Register - pinmux_shared_io_q1_9
 
 Register : Shared IO 48 Q1 10 Mux Selection Register - pinmux_shared_io_q1_10
 
 Register : Shared IO 48 Q1 11 Mux Selection Register - pinmux_shared_io_q1_11
 
 Register : Shared IO 48 Q1 12 Mux Selection Register - pinmux_shared_io_q1_12
 
 Register : Shared IO 48 Q2 1 Mux Selection Register - pinmux_shared_io_q2_1
 
 Register : Shared IO 48 Q2 2 Mux Selection Register - pinmux_shared_io_q2_2
 
 Register : Shared IO 48 Q2 3 Mux Selection Register - pinmux_shared_io_q2_3
 
 Register : Shared IO 48 Q2 4 Mux Selection Register - pinmux_shared_io_q2_4
 
 Register : Shared IO 48 Q2 5 Mux Selection Register - pinmux_shared_io_q2_5
 
 Register : Shared IO 48 Q2 6 Mux Selection Register - pinmux_shared_io_q2_6
 
 Register : Shared IO 48 Q2 7 Mux Selection Register - pinmux_shared_io_q2_7
 
 Register : Shared IO 48 Q2 8 Mux Selection Register - pinmux_shared_io_q2_8
 
 Register : Shared IO 48 Q2 9 Mux Selection Register - pinmux_shared_io_q2_9
 
 Register : Shared IO 48 Q2 10 Mux Selection Register - pinmux_shared_io_q2_10
 
 Register : Shared IO 48 Q2 11 Mux Selection Register - pinmux_shared_io_q2_11
 
 Register : Shared IO 48 Q2 12 Mux Selection Register - pinmux_shared_io_q2_12
 
 Register : Shared IO 48 Q3 1 Mux Selection Register - pinmux_shared_io_q3_1
 
 Register : Shared IO 48 Q3 2 Mux Selection Register - pinmux_shared_io_q3_2
 
 Register : Shared IO 48 Q3 3 Mux Selection Register - pinmux_shared_io_q3_3
 
 Register : Shared IO 48 Q3 4 Mux Selection Register - pinmux_shared_io_q3_4
 
 Register : Shared IO 48 Q3 5 Mux Selection Register - pinmux_shared_io_q3_5
 
 Register : Shared IO 48 Q3 6 Mux Selection Register - pinmux_shared_io_q3_6
 
 Register : Shared IO 48 Q3 7 Mux Selection Register - pinmux_shared_io_q3_7
 
 Register : Shared IO 48 Q3 8 Mux Selection Register - pinmux_shared_io_q3_8
 
 Register : Shared IO 48 Q3 9 Mux Selection Register - pinmux_shared_io_q3_9
 
 Register : Shared IO 48 Q3 10 Mux Selection Register - pinmux_shared_io_q3_10
 
 Register : Shared IO 48 Q3 11 Mux Selection Register - pinmux_shared_io_q3_11
 
 Register : Shared IO 48 Q3 12 Mux Selection Register - pinmux_shared_io_q3_12
 
 Register : Shared IO 48 Q4 1 Mux Selection Register - pinmux_shared_io_q4_1
 
 Register : Shared IO 48 Q4 2 Mux Selection Register - pinmux_shared_io_q4_2
 
 Register : Shared IO 48 Q4 3 Mux Selection Register - pinmux_shared_io_q4_3
 
 Register : Shared IO 48 Q4 4 Mux Selection Register - pinmux_shared_io_q4_4
 
 Register : Shared IO 48 Q4 5 Mux Selection Register - pinmux_shared_io_q4_5
 
 Register : Shared IO 48 Q4 6 Mux Selection Register - pinmux_shared_io_q4_6
 
 Register : Shared IO 48 Q4 7 Mux Selection Register - pinmux_shared_io_q4_7
 
 Register : Shared IO 48 Q4 8 Mux Selection Register - pinmux_shared_io_q4_8
 
 Register : Shared IO 48 Q4 9 Mux Selection Register - pinmux_shared_io_q4_9
 
 Register : Shared IO 48 Q4 10 Mux Selection Register - pinmux_shared_io_q4_10
 
 Register : Shared IO 48 Q4 11 Mux Selection Register - pinmux_shared_io_q4_11
 
 Register : Shared IO 48 Q4 12 Mux Selection Register - pinmux_shared_io_q4_12
 

Data Structures

struct  ALT_PINMUX_SHARED_3V_IO_GRP_s
 
struct  ALT_PINMUX_SHARED_3V_IO_GRP_raw_s
 

Typedefs

typedef struct
ALT_PINMUX_SHARED_3V_IO_GRP_s 
ALT_PINMUX_SHARED_3V_IO_GRP_t
 
typedef struct
ALT_PINMUX_SHARED_3V_IO_GRP_raw_s 
ALT_PINMUX_SHARED_3V_IO_GRP_raw_t
 

Data Structure Documentation

struct ALT_PINMUX_SHARED_3V_IO_GRP_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register group ALT_PINMUX_SHARED_3V_IO_GRP.

Data Fields
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_1_t
pinmux_shared_io_q1_1 ALT_PINMUX_SHARED_3V_IO_Q1_1
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_2_t
pinmux_shared_io_q1_2 ALT_PINMUX_SHARED_3V_IO_Q1_2
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_3_t
pinmux_shared_io_q1_3 ALT_PINMUX_SHARED_3V_IO_Q1_3
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_4_t
pinmux_shared_io_q1_4 ALT_PINMUX_SHARED_3V_IO_Q1_4
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_5_t
pinmux_shared_io_q1_5 ALT_PINMUX_SHARED_3V_IO_Q1_5
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_6_t
pinmux_shared_io_q1_6 ALT_PINMUX_SHARED_3V_IO_Q1_6
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_7_t
pinmux_shared_io_q1_7 ALT_PINMUX_SHARED_3V_IO_Q1_7
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_8_t
pinmux_shared_io_q1_8 ALT_PINMUX_SHARED_3V_IO_Q1_8
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_9_t
pinmux_shared_io_q1_9 ALT_PINMUX_SHARED_3V_IO_Q1_9
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_10_t
pinmux_shared_io_q1_10 ALT_PINMUX_SHARED_3V_IO_Q1_10
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_11_t
pinmux_shared_io_q1_11 ALT_PINMUX_SHARED_3V_IO_Q1_11
volatile
ALT_PINMUX_SHARED_3V_IO_Q1_12_t
pinmux_shared_io_q1_12 ALT_PINMUX_SHARED_3V_IO_Q1_12
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_1_t
pinmux_shared_io_q2_1 ALT_PINMUX_SHARED_3V_IO_Q2_1
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_2_t
pinmux_shared_io_q2_2 ALT_PINMUX_SHARED_3V_IO_Q2_2
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_3_t
pinmux_shared_io_q2_3 ALT_PINMUX_SHARED_3V_IO_Q2_3
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_4_t
pinmux_shared_io_q2_4 ALT_PINMUX_SHARED_3V_IO_Q2_4
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_5_t
pinmux_shared_io_q2_5 ALT_PINMUX_SHARED_3V_IO_Q2_5
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_6_t
pinmux_shared_io_q2_6 ALT_PINMUX_SHARED_3V_IO_Q2_6
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_7_t
pinmux_shared_io_q2_7 ALT_PINMUX_SHARED_3V_IO_Q2_7
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_8_t
pinmux_shared_io_q2_8 ALT_PINMUX_SHARED_3V_IO_Q2_8
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_9_t
pinmux_shared_io_q2_9 ALT_PINMUX_SHARED_3V_IO_Q2_9
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_10_t
pinmux_shared_io_q2_10 ALT_PINMUX_SHARED_3V_IO_Q2_10
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_11_t
pinmux_shared_io_q2_11 ALT_PINMUX_SHARED_3V_IO_Q2_11
volatile
ALT_PINMUX_SHARED_3V_IO_Q2_12_t
pinmux_shared_io_q2_12 ALT_PINMUX_SHARED_3V_IO_Q2_12
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_1_t
pinmux_shared_io_q3_1 ALT_PINMUX_SHARED_3V_IO_Q3_1
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_2_t
pinmux_shared_io_q3_2 ALT_PINMUX_SHARED_3V_IO_Q3_2
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_3_t
pinmux_shared_io_q3_3 ALT_PINMUX_SHARED_3V_IO_Q3_3
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_4_t
pinmux_shared_io_q3_4 ALT_PINMUX_SHARED_3V_IO_Q3_4
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_5_t
pinmux_shared_io_q3_5 ALT_PINMUX_SHARED_3V_IO_Q3_5
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_6_t
pinmux_shared_io_q3_6 ALT_PINMUX_SHARED_3V_IO_Q3_6
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_7_t
pinmux_shared_io_q3_7 ALT_PINMUX_SHARED_3V_IO_Q3_7
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_8_t
pinmux_shared_io_q3_8 ALT_PINMUX_SHARED_3V_IO_Q3_8
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_9_t
pinmux_shared_io_q3_9 ALT_PINMUX_SHARED_3V_IO_Q3_9
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_10_t
pinmux_shared_io_q3_10 ALT_PINMUX_SHARED_3V_IO_Q3_10
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_11_t
pinmux_shared_io_q3_11 ALT_PINMUX_SHARED_3V_IO_Q3_11
volatile
ALT_PINMUX_SHARED_3V_IO_Q3_12_t
pinmux_shared_io_q3_12 ALT_PINMUX_SHARED_3V_IO_Q3_12
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_1_t
pinmux_shared_io_q4_1 ALT_PINMUX_SHARED_3V_IO_Q4_1
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_2_t
pinmux_shared_io_q4_2 ALT_PINMUX_SHARED_3V_IO_Q4_2
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_3_t
pinmux_shared_io_q4_3 ALT_PINMUX_SHARED_3V_IO_Q4_3
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_4_t
pinmux_shared_io_q4_4 ALT_PINMUX_SHARED_3V_IO_Q4_4
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_5_t
pinmux_shared_io_q4_5 ALT_PINMUX_SHARED_3V_IO_Q4_5
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_6_t
pinmux_shared_io_q4_6 ALT_PINMUX_SHARED_3V_IO_Q4_6
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_7_t
pinmux_shared_io_q4_7 ALT_PINMUX_SHARED_3V_IO_Q4_7
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_8_t
pinmux_shared_io_q4_8 ALT_PINMUX_SHARED_3V_IO_Q4_8
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_9_t
pinmux_shared_io_q4_9 ALT_PINMUX_SHARED_3V_IO_Q4_9
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_10_t
pinmux_shared_io_q4_10 ALT_PINMUX_SHARED_3V_IO_Q4_10
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_11_t
pinmux_shared_io_q4_11 ALT_PINMUX_SHARED_3V_IO_Q4_11
volatile
ALT_PINMUX_SHARED_3V_IO_Q4_12_t
pinmux_shared_io_q4_12 ALT_PINMUX_SHARED_3V_IO_Q4_12
volatile uint32_t _pad_0xc0_0x200 UNDEFINED
struct ALT_PINMUX_SHARED_3V_IO_GRP_raw_s

The struct declaration for the raw register contents of register group ALT_PINMUX_SHARED_3V_IO_GRP.

Data Fields
volatile uint32_t pinmux_shared_io_q1_1 ALT_PINMUX_SHARED_3V_IO_Q1_1
volatile uint32_t pinmux_shared_io_q1_2 ALT_PINMUX_SHARED_3V_IO_Q1_2
volatile uint32_t pinmux_shared_io_q1_3 ALT_PINMUX_SHARED_3V_IO_Q1_3
volatile uint32_t pinmux_shared_io_q1_4 ALT_PINMUX_SHARED_3V_IO_Q1_4
volatile uint32_t pinmux_shared_io_q1_5 ALT_PINMUX_SHARED_3V_IO_Q1_5
volatile uint32_t pinmux_shared_io_q1_6 ALT_PINMUX_SHARED_3V_IO_Q1_6
volatile uint32_t pinmux_shared_io_q1_7 ALT_PINMUX_SHARED_3V_IO_Q1_7
volatile uint32_t pinmux_shared_io_q1_8 ALT_PINMUX_SHARED_3V_IO_Q1_8
volatile uint32_t pinmux_shared_io_q1_9 ALT_PINMUX_SHARED_3V_IO_Q1_9
volatile uint32_t pinmux_shared_io_q1_10 ALT_PINMUX_SHARED_3V_IO_Q1_10
volatile uint32_t pinmux_shared_io_q1_11 ALT_PINMUX_SHARED_3V_IO_Q1_11
volatile uint32_t pinmux_shared_io_q1_12 ALT_PINMUX_SHARED_3V_IO_Q1_12
volatile uint32_t pinmux_shared_io_q2_1 ALT_PINMUX_SHARED_3V_IO_Q2_1
volatile uint32_t pinmux_shared_io_q2_2 ALT_PINMUX_SHARED_3V_IO_Q2_2
volatile uint32_t pinmux_shared_io_q2_3 ALT_PINMUX_SHARED_3V_IO_Q2_3
volatile uint32_t pinmux_shared_io_q2_4 ALT_PINMUX_SHARED_3V_IO_Q2_4
volatile uint32_t pinmux_shared_io_q2_5 ALT_PINMUX_SHARED_3V_IO_Q2_5
volatile uint32_t pinmux_shared_io_q2_6 ALT_PINMUX_SHARED_3V_IO_Q2_6
volatile uint32_t pinmux_shared_io_q2_7 ALT_PINMUX_SHARED_3V_IO_Q2_7
volatile uint32_t pinmux_shared_io_q2_8 ALT_PINMUX_SHARED_3V_IO_Q2_8
volatile uint32_t pinmux_shared_io_q2_9 ALT_PINMUX_SHARED_3V_IO_Q2_9
volatile uint32_t pinmux_shared_io_q2_10 ALT_PINMUX_SHARED_3V_IO_Q2_10
volatile uint32_t pinmux_shared_io_q2_11 ALT_PINMUX_SHARED_3V_IO_Q2_11
volatile uint32_t pinmux_shared_io_q2_12 ALT_PINMUX_SHARED_3V_IO_Q2_12
volatile uint32_t pinmux_shared_io_q3_1 ALT_PINMUX_SHARED_3V_IO_Q3_1
volatile uint32_t pinmux_shared_io_q3_2 ALT_PINMUX_SHARED_3V_IO_Q3_2
volatile uint32_t pinmux_shared_io_q3_3 ALT_PINMUX_SHARED_3V_IO_Q3_3
volatile uint32_t pinmux_shared_io_q3_4 ALT_PINMUX_SHARED_3V_IO_Q3_4
volatile uint32_t pinmux_shared_io_q3_5 ALT_PINMUX_SHARED_3V_IO_Q3_5
volatile uint32_t pinmux_shared_io_q3_6 ALT_PINMUX_SHARED_3V_IO_Q3_6
volatile uint32_t pinmux_shared_io_q3_7 ALT_PINMUX_SHARED_3V_IO_Q3_7
volatile uint32_t pinmux_shared_io_q3_8 ALT_PINMUX_SHARED_3V_IO_Q3_8
volatile uint32_t pinmux_shared_io_q3_9 ALT_PINMUX_SHARED_3V_IO_Q3_9
volatile uint32_t pinmux_shared_io_q3_10 ALT_PINMUX_SHARED_3V_IO_Q3_10
volatile uint32_t pinmux_shared_io_q3_11 ALT_PINMUX_SHARED_3V_IO_Q3_11
volatile uint32_t pinmux_shared_io_q3_12 ALT_PINMUX_SHARED_3V_IO_Q3_12
volatile uint32_t pinmux_shared_io_q4_1 ALT_PINMUX_SHARED_3V_IO_Q4_1
volatile uint32_t pinmux_shared_io_q4_2 ALT_PINMUX_SHARED_3V_IO_Q4_2
volatile uint32_t pinmux_shared_io_q4_3 ALT_PINMUX_SHARED_3V_IO_Q4_3
volatile uint32_t pinmux_shared_io_q4_4 ALT_PINMUX_SHARED_3V_IO_Q4_4
volatile uint32_t pinmux_shared_io_q4_5 ALT_PINMUX_SHARED_3V_IO_Q4_5
volatile uint32_t pinmux_shared_io_q4_6 ALT_PINMUX_SHARED_3V_IO_Q4_6
volatile uint32_t pinmux_shared_io_q4_7 ALT_PINMUX_SHARED_3V_IO_Q4_7
volatile uint32_t pinmux_shared_io_q4_8 ALT_PINMUX_SHARED_3V_IO_Q4_8
volatile uint32_t pinmux_shared_io_q4_9 ALT_PINMUX_SHARED_3V_IO_Q4_9
volatile uint32_t pinmux_shared_io_q4_10 ALT_PINMUX_SHARED_3V_IO_Q4_10
volatile uint32_t pinmux_shared_io_q4_11 ALT_PINMUX_SHARED_3V_IO_Q4_11
volatile uint32_t pinmux_shared_io_q4_12 ALT_PINMUX_SHARED_3V_IO_Q4_12
volatile uint32_t _pad_0xc0_0x200 UNDEFINED

Typedef Documentation

The typedef declaration for register group ALT_PINMUX_SHARED_3V_IO_GRP.

The typedef declaration for the raw register contents of register group ALT_PINMUX_SHARED_3V_IO_GRP.