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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register is used to control the electrical behavior and direction of Dedicated IO 3
Only reset by a cold reset (ignores warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[4:0] | RW | 0x8 | Pull down drive strength |
[5] | RW | 0x0 | NMOS slew rate |
[7:6] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 |
[12:8] | RW | 0x0 | Pull up drive strength |
[13] | RW | 0x0 | PMOS slew rate |
[15:14] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 |
[16] | RW | 0x0 | Weak pull up signal |
[18:17] | RW | 0x2 | LVTTL input buffer enable signal |
[21:19] | RW | 0x1 | Bias trim bits |
[31:22] | R | 0x0 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 |
Field : Pull down drive strength - PD_DRV_STRG | |
Configuration bits for NMOS pull down drive strength. Pending Characterization Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_LSB 0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_MSB 4 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_WIDTH 5 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET_MSK 0x0000001f |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_CLR_MSK 0xffffffe0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_RESET 0x8 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_GET(value) (((value) & 0x0000001f) >> 0) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET(value) (((value) << 0) & 0x0000001f) |
Field : NMOS slew rate - PD_SLW_RT | |
Configuration bit for output pull down slew rate control 0 : slow N slew 1 : fast N slew Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_LSB 5 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_MSB 5 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_WIDTH 1 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET_MSK 0x00000020 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_CLR_MSK 0xffffffdf |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET(value) (((value) << 5) & 0x00000020) |
Field : Reserved_7to6 | |
Reserved Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_LSB 6 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_MSB 7 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_WIDTH 2 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET_MSK 0x000000c0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_CLR_MSK 0xffffff3f |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_GET(value) (((value) & 0x000000c0) >> 6) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET(value) (((value) << 6) & 0x000000c0) |
Field : Pull up drive strength - PU_DRV_STRG | |
Configuration bits for PMOS pull up drive strength Pending Characterization Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_LSB 8 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_MSB 12 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_WIDTH 5 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET_MSK 0x00001f00 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_CLR_MSK 0xffffe0ff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_GET(value) (((value) & 0x00001f00) >> 8) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET(value) (((value) << 8) & 0x00001f00) |
Field : PMOS slew rate - PU_SLW_RT | |
Configuration bit for output pull up slew rate control 0 : slow P slew 1 : fast P slew Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_LSB 13 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_MSB 13 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_WIDTH 1 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET_MSK 0x00002000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_CLR_MSK 0xffffdfff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET(value) (((value) << 13) & 0x00002000) |
Field : Reserved_15to14 | |
Reserved Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_LSB 14 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_MSB 15 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_WIDTH 2 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET_MSK 0x0000c000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_CLR_MSK 0xffff3fff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET(value) (((value) << 14) & 0x0000c000) |
Field : Weak pull up signal - WK_PU_EN | |
Configuration bit for weak pull up enable 0 : weak pull up disable 1 : weak pull up enable Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_LSB 16 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_MSB 16 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_WIDTH 1 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET_MSK 0x00010000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_CLR_MSK 0xfffeffff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET(value) (((value) << 16) & 0x00010000) |
Field : LVTTL input buffer enable signal - INPUT_BUF_EN | |
Configuration bits for LVTTL input buffer enable 00 : disable 01 : 1.8V TTL 10 : 2.5V/3.0V TTL 11 : 1.8V TTL Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_LSB 17 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_MSB 18 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_WIDTH 2 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET_MSK 0x00060000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_CLR_MSK 0xfff9ffff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_RESET 0x2 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_GET(value) (((value) & 0x00060000) >> 17) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET(value) (((value) << 17) & 0x00060000) |
Field : Bias trim bits - RTRIM | |
Configuration bits for bias trim 000 : disable 001 : default 010 : trim low 100 : trim high others : invalid/reserved Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_LSB 19 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_MSB 21 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_WIDTH 3 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET_MSK 0x00380000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_CLR_MSK 0xffc7ffff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_RESET 0x1 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_GET(value) (((value) & 0x00380000) >> 19) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET(value) (((value) << 19) & 0x00380000) |
Field : Reserved_31to22 | |
Reserved Field Access Macros: | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_LSB 22 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_MSB 31 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_WIDTH 10 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET_MSK 0xffc00000 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_CLR_MSK 0x003fffff |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_RESET 0x0 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_GET(value) (((value) & 0xffc00000) >> 22) |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET(value) (((value) << 22) & 0xffc00000) |
Data Structures | |
struct | ALT_PINMUX_DCTD_IO_CFG_3_s |
Macros | |
#define | ALT_PINMUX_DCTD_IO_CFG_3_RESET 0x000c0008 |
#define | ALT_PINMUX_DCTD_IO_CFG_3_OFST 0x10c |
Typedefs | |
typedef struct ALT_PINMUX_DCTD_IO_CFG_3_s | ALT_PINMUX_DCTD_IO_CFG_3_t |
struct ALT_PINMUX_DCTD_IO_CFG_3_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_PINMUX_DCTD_IO_CFG_3.
Data Fields | ||
---|---|---|
uint32_t | PD_DRV_STRG: 5 | Pull down drive strength |
uint32_t | PD_SLW_RT: 1 | NMOS slew rate |
const uint32_t | Reserved_7to6: 2 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 |
uint32_t | PU_DRV_STRG: 5 | Pull up drive strength |
uint32_t | PU_SLW_RT: 1 | PMOS slew rate |
const uint32_t | Reserved_15to14: 2 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 |
uint32_t | WK_PU_EN: 1 | Weak pull up signal |
uint32_t | INPUT_BUF_EN: 2 | LVTTL input buffer enable signal |
uint32_t | RTRIM: 3 | Bias trim bits |
const uint32_t | Reserved_31to22: 10 | ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 |
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_WIDTH 5 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET_MSK 0x0000001f |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_CLR_MSK 0xffffffe0 |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_RESET 0x8 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_GET | ( | value | ) | (((value) & 0x0000001f) >> 0) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG_SET | ( | value | ) | (((value) << 0) & 0x0000001f) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_PD_DRV_STRG register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_WIDTH 1 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET_MSK 0x00000020 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_PD_SLW_RT register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_WIDTH 2 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET_MSK 0x000000c0 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_CLR_MSK 0xffffff3f |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_GET | ( | value | ) | (((value) & 0x000000c0) >> 6) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6_SET | ( | value | ) | (((value) << 6) & 0x000000c0) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_7TO6 register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_WIDTH 5 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET_MSK 0x00001f00 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_CLR_MSK 0xffffe0ff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_GET | ( | value | ) | (((value) & 0x00001f00) >> 8) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG_SET | ( | value | ) | (((value) << 8) & 0x00001f00) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_PU_DRV_STRG register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_WIDTH 1 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET_MSK 0x00002000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_PU_SLW_RT register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_WIDTH 2 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET_MSK 0x0000c000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_15TO14 register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_WIDTH 1 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET_MSK 0x00010000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_WK_PU_EN register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_WIDTH 2 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET_MSK 0x00060000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_CLR_MSK 0xfff9ffff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_RESET 0x2 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_GET | ( | value | ) | (((value) & 0x00060000) >> 17) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN_SET | ( | value | ) | (((value) << 17) & 0x00060000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_INPUT_BUF_EN register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_WIDTH 3 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET_MSK 0x00380000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_CLR_MSK 0xffc7ffff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_RESET 0x1 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_GET | ( | value | ) | (((value) & 0x00380000) >> 19) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RTRIM field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RTRIM_SET | ( | value | ) | (((value) << 19) & 0x00380000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_RTRIM register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_WIDTH 10 |
The width in bits of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET_MSK 0xffc00000 |
The mask used to set the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_CLR_MSK 0x003fffff |
The mask used to clear the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_RESET 0x0 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_GET | ( | value | ) | (((value) & 0xffc00000) >> 22) |
Extracts the ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 field value from a register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22_SET | ( | value | ) | (((value) << 22) & 0xffc00000) |
Produces a ALT_PINMUX_DCTD_IO_CFG_3_RSVD_31TO22 register field value suitable for setting the register.
#define ALT_PINMUX_DCTD_IO_CFG_3_RESET 0x000c0008 |
The reset value of the ALT_PINMUX_DCTD_IO_CFG_3 register.
#define ALT_PINMUX_DCTD_IO_CFG_3_OFST 0x10c |
The byte offset of the ALT_PINMUX_DCTD_IO_CFG_3 register from the beginning of the component.
typedef struct ALT_PINMUX_DCTD_IO_CFG_3_s ALT_PINMUX_DCTD_IO_CFG_3_t |
The typedef declaration for register ALT_PINMUX_DCTD_IO_CFG_3.