![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Clock Source Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[31:0] | R | 0x0 | ALT_SDMMC_CLKSRC_CLK_SRC |
Field : clk_source | |||||||
Clock divider source for up to 16 SD cards supported. Each card has two bits assigned to it. For example, bits[1:0] assigned for card-0, which maps and internally routes clock divider[3:0] outputs to cclk_out[15:0] pins, depending on bit value. 00 Clock divider 0 01 Clock divider 1 10 Clock divider 2 11 Clock divider 3 In MMC-Ver3.3-only controller, only one clock divider supported. The cclk_out is always from clock divider 0, and this register is not implemented. Field Enumeration Values:
Field Access Macros: | |||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_MSB 31 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 32 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0xffffffff | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0x00000000 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0 | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_GET(value) (((value) & 0xffffffff) >> 0) | ||||||
#define | ALT_SDMMC_CLKSRC_CLK_SRC_SET(value) (((value) << 0) & 0xffffffff) | ||||||
Data Structures | |
struct | ALT_SDMMC_CLKSRC_s |
Macros | |
#define | ALT_SDMMC_CLKSRC_RESET 0x00000000 |
#define | ALT_SDMMC_CLKSRC_OFST 0xc |
Typedefs | |
typedef struct ALT_SDMMC_CLKSRC_s | ALT_SDMMC_CLKSRC_t |
struct ALT_SDMMC_CLKSRC_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_CLKSRC.
Data Fields | ||
---|---|---|
const uint32_t | clk_source: 32 | ALT_SDMMC_CLKSRC_CLK_SRC |
#define ALT_SDMMC_CLKSRC_CLK_SRC_E_CLKDIV0 0x0 |
Enumerated value for register field ALT_SDMMC_CLKSRC_CLK_SRC
Clock divider 0
#define ALT_SDMMC_CLKSRC_CLK_SRC_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field.
#define ALT_SDMMC_CLKSRC_CLK_SRC_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKSRC_CLK_SRC register field.
#define ALT_SDMMC_CLKSRC_CLK_SRC_WIDTH 32 |
The width in bits of the ALT_SDMMC_CLKSRC_CLK_SRC register field.
#define ALT_SDMMC_CLKSRC_CLK_SRC_SET_MSK 0xffffffff |
The mask used to set the ALT_SDMMC_CLKSRC_CLK_SRC register field value.
#define ALT_SDMMC_CLKSRC_CLK_SRC_CLR_MSK 0x00000000 |
The mask used to clear the ALT_SDMMC_CLKSRC_CLK_SRC register field value.
#define ALT_SDMMC_CLKSRC_CLK_SRC_RESET 0x0 |
The reset value of the ALT_SDMMC_CLKSRC_CLK_SRC register field.
#define ALT_SDMMC_CLKSRC_CLK_SRC_GET | ( | value | ) | (((value) & 0xffffffff) >> 0) |
Extracts the ALT_SDMMC_CLKSRC_CLK_SRC field value from a register.
#define ALT_SDMMC_CLKSRC_CLK_SRC_SET | ( | value | ) | (((value) << 0) & 0xffffffff) |
Produces a ALT_SDMMC_CLKSRC_CLK_SRC register field value suitable for setting the register.
#define ALT_SDMMC_CLKSRC_RESET 0x00000000 |
The reset value of the ALT_SDMMC_CLKSRC register.
#define ALT_SDMMC_CLKSRC_OFST 0xc |
The byte offset of the ALT_SDMMC_CLKSRC register from the beginning of the component.
typedef struct ALT_SDMMC_CLKSRC_s ALT_SDMMC_CLKSRC_t |
The typedef declaration for register ALT_SDMMC_CLKSRC.