Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : sideband13

Description

Register Layout

Bits Access Reset Description
[31:0] RW 0x0 ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE

Field : mr_cmd_opcode

[31:27] reserved. Register Command Opcode Information to be used for Register Command LPDDR3 [26:20] Reserved [19:10] falling edge CA. [9:0] rising edge CA DDR4 [26:24] C2:C0 [23] ACT [22:21] BG1:BG0 [20] Reserved [19:18] BA1:BA0 [17] A17 [16] RAS [15] CAS [14] WE [13:0] A13:A0 DDR3 [26:21] Reserved [20:18] BA2:BA0 [17] A17 [16] RAS [15] CAS [14] WE [13] Reserved [12:0] A12:A0 RLDRAM3 [26] Reserved [25:22] BA3:BA0 [21] REF [20] WE [19:0] A19:A0

Field Access Macros:

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_LSB   0
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_MSB   31
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_WIDTH   32
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET_MSK   0xffffffff
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK   0x00000000
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_GET(value)   (((value) & 0xffffffff) >> 0)
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET(value)   (((value) << 0) & 0xffffffff)
 

Data Structures

struct  ALT_IO48_HMC_MMR_SIDEBAND13_s
 

Macros

#define ALT_IO48_HMC_MMR_SIDEBAND13_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_SIDEBAND13_OFST   0xe0
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_SIDEBAND13_s 
ALT_IO48_HMC_MMR_SIDEBAND13_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_SIDEBAND13_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_SIDEBAND13.

Data Fields
uint32_t mr_cmd_opcode: 32 ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE

Macro Definitions

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_WIDTH   32

The width in bits of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET_MSK   0xffffffff

The mask used to set the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_CLR_MSK   0x00000000

The mask used to clear the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_GET (   value)    (((value) & 0xffffffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE field value from a register.

#define ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE_SET (   value)    (((value) << 0) & 0xffffffff)

Produces a ALT_IO48_HMC_MMR_SIDEBAND13_MR_CMD_OPCODE register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SIDEBAND13_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_SIDEBAND13 register.

#define ALT_IO48_HMC_MMR_SIDEBAND13_OFST   0xe0

The byte offset of the ALT_IO48_HMC_MMR_SIDEBAND13 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_SIDEBAND13.