Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Boot Info Register - bootinfo

Description

Provides access to boot configuration information.

Register Layout

Bits Access Reset Description
[2:0] R Unknown Boot Select
[4:3] R Unknown Clock Select
[7:5] R Unknown HPS Pin Boot Select
[9:8] R Unknown HPS Pin Clock Select
[31:10] ??? Unknown UNDEFINED

Field : Boot Select - bsel

The boot select field specifies the boot source. It is read by the Boot ROM code on a cold or warm reset to determine the boot source.

The HPS BSEL pins value are sampled upon deassertion of cold reset.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_BOOT_BSEL_E_RSVD 0x0 Reserved
ALT_SYSMGR_BOOT_BSEL_E_FPGA 0x1 FPGA (HPS2FPGA Bridge)
ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V 0x2 NAND Flash (1.8v)
ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V 0x3 NAND Flash (3.0v)
ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V 0x4 SD/MMC External Transceiver (1.8v)
ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V 0x5 SD/MMC Internal Transceiver (3.0v)
ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V 0x6 QSPI Flash (1.8v)
ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V 0x7 QSPI Flash (3.0v)

Field Access Macros:

#define ALT_SYSMGR_BOOT_BSEL_E_RSVD   0x0
 
#define ALT_SYSMGR_BOOT_BSEL_E_FPGA   0x1
 
#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V   0x2
 
#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V   0x3
 
#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4
 
#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5
 
#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V   0x6
 
#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V   0x7
 
#define ALT_SYSMGR_BOOT_BSEL_LSB   0
 
#define ALT_SYSMGR_BOOT_BSEL_MSB   2
 
#define ALT_SYSMGR_BOOT_BSEL_WIDTH   3
 
#define ALT_SYSMGR_BOOT_BSEL_SET_MSK   0x00000007
 
#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK   0xfffffff8
 
#define ALT_SYSMGR_BOOT_BSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_BSEL_GET(value)   (((value) & 0x00000007) >> 0)
 
#define ALT_SYSMGR_BOOT_BSEL_SET(value)   (((value) << 0) & 0x00000007)
 

Field : Clock Select - csel

The clock select field specifies clock information for booting. The clock select encoding is a function of the CSEL value. The clock select field is read by the Boot ROM code on a cold or warm reset when booting from a flash device to get information about how to setup the HPS clocking to boot from the specified clock device.

The encoding of the clock select field is specified by the enum associated with this field.

The HPS CSEL pins value are sampled upon deassertion of cold reset.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_BOOT_CSEL_E_CSEL_0 0x0 QSPI device clock is osc1_clk divided by 4,
: SD/MMC device clock is osc1_clk divided by 4,
: NAND device operation is osc1_clk divided by 25
ALT_SYSMGR_BOOT_CSEL_E_CSEL_1 0x1 QSPI device clock is osc1_clk divided by 2,
: SD/MMC device clock is osc1_clk divided by 1,
: NAND device operation is osc1_clk multiplied by
: 20/25
ALT_SYSMGR_BOOT_CSEL_E_CSEL_2 0x2 QSPI device clock is osc1_clk divided by 1,
: SD/MMC device clock is osc1_clk divided by 2,
: NAND device operation is osc1_clk multiplied by
: 10/25
ALT_SYSMGR_BOOT_CSEL_E_CSEL_3 0x3 QSPI device clock is osc1_clk multiplied by 2,
: SD/MMC device clock is osc1_clk divided by 4,
: NAND device operation is osc1_clk multiplied by
: 5/25

Field Access Macros:

#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0   0x0
 
#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1   0x1
 
#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2   0x2
 
#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3   0x3
 
#define ALT_SYSMGR_BOOT_CSEL_LSB   3
 
#define ALT_SYSMGR_BOOT_CSEL_MSB   4
 
#define ALT_SYSMGR_BOOT_CSEL_WIDTH   2
 
#define ALT_SYSMGR_BOOT_CSEL_SET_MSK   0x00000018
 
#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK   0xffffffe7
 
#define ALT_SYSMGR_BOOT_CSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_CSEL_GET(value)   (((value) & 0x00000018) >> 3)
 
#define ALT_SYSMGR_BOOT_CSEL_SET(value)   (((value) << 3) & 0x00000018)
 

Field : HPS Pin Boot Select - pinbsel

Specifies the sampled value of the HPS BSEL pins. The value of HPS BSEL pins are sampled upon deassertion of cold reset.

Field Access Macros:

#define ALT_SYSMGR_BOOT_PINBSEL_LSB   5
 
#define ALT_SYSMGR_BOOT_PINBSEL_MSB   7
 
#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH   3
 
#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK   0x000000e0
 
#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK   0xffffff1f
 
#define ALT_SYSMGR_BOOT_PINBSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_PINBSEL_GET(value)   (((value) & 0x000000e0) >> 5)
 
#define ALT_SYSMGR_BOOT_PINBSEL_SET(value)   (((value) << 5) & 0x000000e0)
 

Field : HPS Pin Clock Select - pincsel

Specifies the sampled value of the HPS CSEL pins. The value of HPS CSEL pins are sampled upon deassertion of cold reset.

Field Access Macros:

#define ALT_SYSMGR_BOOT_PINCSEL_LSB   8
 
#define ALT_SYSMGR_BOOT_PINCSEL_MSB   9
 
#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH   2
 
#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK   0x00000300
 
#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK   0xfffffcff
 
#define ALT_SYSMGR_BOOT_PINCSEL_RESET   0x0
 
#define ALT_SYSMGR_BOOT_PINCSEL_GET(value)   (((value) & 0x00000300) >> 8)
 
#define ALT_SYSMGR_BOOT_PINCSEL_SET(value)   (((value) << 8) & 0x00000300)
 

Data Structures

struct  ALT_SYSMGR_BOOT_s
 

Macros

#define ALT_SYSMGR_BOOT_OFST   0x14
 

Typedefs

typedef struct ALT_SYSMGR_BOOT_s ALT_SYSMGR_BOOT_t
 

Data Structure Documentation

struct ALT_SYSMGR_BOOT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_BOOT.

Data Fields
const uint32_t bsel: 3 Boot Select
const uint32_t csel: 2 Clock Select
const uint32_t pinbsel: 3 HPS Pin Boot Select
const uint32_t pincsel: 2 HPS Pin Clock Select
uint32_t __pad0__: 22 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_BOOT_BSEL_E_RSVD   0x0

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

Reserved

#define ALT_SYSMGR_BOOT_BSEL_E_FPGA   0x1

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

FPGA (HPS2FPGA Bridge)

#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_1_8V   0x2

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

NAND Flash (1.8v)

#define ALT_SYSMGR_BOOT_BSEL_E_NAND_FLSH_3_0V   0x3

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

NAND Flash (3.0v)

#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_EXTERNAL_TRANSCEIVER_1_8V   0x4

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

SD/MMC External Transceiver (1.8v)

#define ALT_SYSMGR_BOOT_BSEL_E_SD_MMC_INTERNAL_TRANSCEIVER_3_0V   0x5

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

SD/MMC Internal Transceiver (3.0v)

#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_1_8V   0x6

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

QSPI Flash (1.8v)

#define ALT_SYSMGR_BOOT_BSEL_E_QSPI_FLSH_3_0V   0x7

Enumerated value for register field ALT_SYSMGR_BOOT_BSEL

QSPI Flash (3.0v)

#define ALT_SYSMGR_BOOT_BSEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_MSB   2

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_BOOT_BSEL register field.

#define ALT_SYSMGR_BOOT_BSEL_SET_MSK   0x00000007

The mask used to set the ALT_SYSMGR_BOOT_BSEL register field value.

#define ALT_SYSMGR_BOOT_BSEL_CLR_MSK   0xfffffff8

The mask used to clear the ALT_SYSMGR_BOOT_BSEL register field value.

#define ALT_SYSMGR_BOOT_BSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_BSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_BSEL_GET (   value)    (((value) & 0x00000007) >> 0)

Extracts the ALT_SYSMGR_BOOT_BSEL field value from a register.

#define ALT_SYSMGR_BOOT_BSEL_SET (   value)    (((value) << 0) & 0x00000007)

Produces a ALT_SYSMGR_BOOT_BSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_0   0x0

Enumerated value for register field ALT_SYSMGR_BOOT_CSEL

QSPI device clock is osc1_clk divided by 4, SD/MMC device clock is osc1_clk divided by 4, NAND device operation is osc1_clk divided by 25

#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_1   0x1

Enumerated value for register field ALT_SYSMGR_BOOT_CSEL

QSPI device clock is osc1_clk divided by 2, SD/MMC device clock is osc1_clk divided by 1, NAND device operation is osc1_clk multiplied by 20/25

#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_2   0x2

Enumerated value for register field ALT_SYSMGR_BOOT_CSEL

QSPI device clock is osc1_clk divided by 1, SD/MMC device clock is osc1_clk divided by 2, NAND device operation is osc1_clk multiplied by 10/25

#define ALT_SYSMGR_BOOT_CSEL_E_CSEL_3   0x3

Enumerated value for register field ALT_SYSMGR_BOOT_CSEL

QSPI device clock is osc1_clk multiplied by 2, SD/MMC device clock is osc1_clk divided by 4, NAND device operation is osc1_clk multiplied by 5/25

#define ALT_SYSMGR_BOOT_CSEL_LSB   3

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_CSEL register field.

#define ALT_SYSMGR_BOOT_CSEL_MSB   4

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_CSEL register field.

#define ALT_SYSMGR_BOOT_CSEL_WIDTH   2

The width in bits of the ALT_SYSMGR_BOOT_CSEL register field.

#define ALT_SYSMGR_BOOT_CSEL_SET_MSK   0x00000018

The mask used to set the ALT_SYSMGR_BOOT_CSEL register field value.

#define ALT_SYSMGR_BOOT_CSEL_CLR_MSK   0xffffffe7

The mask used to clear the ALT_SYSMGR_BOOT_CSEL register field value.

#define ALT_SYSMGR_BOOT_CSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_CSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_CSEL_GET (   value)    (((value) & 0x00000018) >> 3)

Extracts the ALT_SYSMGR_BOOT_CSEL field value from a register.

#define ALT_SYSMGR_BOOT_CSEL_SET (   value)    (((value) << 3) & 0x00000018)

Produces a ALT_SYSMGR_BOOT_CSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_PINBSEL_LSB   5

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field.

#define ALT_SYSMGR_BOOT_PINBSEL_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINBSEL register field.

#define ALT_SYSMGR_BOOT_PINBSEL_WIDTH   3

The width in bits of the ALT_SYSMGR_BOOT_PINBSEL register field.

#define ALT_SYSMGR_BOOT_PINBSEL_SET_MSK   0x000000e0

The mask used to set the ALT_SYSMGR_BOOT_PINBSEL register field value.

#define ALT_SYSMGR_BOOT_PINBSEL_CLR_MSK   0xffffff1f

The mask used to clear the ALT_SYSMGR_BOOT_PINBSEL register field value.

#define ALT_SYSMGR_BOOT_PINBSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_PINBSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_PINBSEL_GET (   value)    (((value) & 0x000000e0) >> 5)

Extracts the ALT_SYSMGR_BOOT_PINBSEL field value from a register.

#define ALT_SYSMGR_BOOT_PINBSEL_SET (   value)    (((value) << 5) & 0x000000e0)

Produces a ALT_SYSMGR_BOOT_PINBSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_PINCSEL_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field.

#define ALT_SYSMGR_BOOT_PINCSEL_MSB   9

The Most Significant Bit (MSB) position of the ALT_SYSMGR_BOOT_PINCSEL register field.

#define ALT_SYSMGR_BOOT_PINCSEL_WIDTH   2

The width in bits of the ALT_SYSMGR_BOOT_PINCSEL register field.

#define ALT_SYSMGR_BOOT_PINCSEL_SET_MSK   0x00000300

The mask used to set the ALT_SYSMGR_BOOT_PINCSEL register field value.

#define ALT_SYSMGR_BOOT_PINCSEL_CLR_MSK   0xfffffcff

The mask used to clear the ALT_SYSMGR_BOOT_PINCSEL register field value.

#define ALT_SYSMGR_BOOT_PINCSEL_RESET   0x0

The reset value of the ALT_SYSMGR_BOOT_PINCSEL register field is UNKNOWN.

#define ALT_SYSMGR_BOOT_PINCSEL_GET (   value)    (((value) & 0x00000300) >> 8)

Extracts the ALT_SYSMGR_BOOT_PINCSEL field value from a register.

#define ALT_SYSMGR_BOOT_PINCSEL_SET (   value)    (((value) << 8) & 0x00000300)

Produces a ALT_SYSMGR_BOOT_PINCSEL register field value suitable for setting the register.

#define ALT_SYSMGR_BOOT_OFST   0x14

The byte offset of the ALT_SYSMGR_BOOT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_BOOT.