Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control Register 0 - ctrlr0

Description

This register controls the serial data transfer. It is impossible to write to this register when the SPI Slave is enabled. The SPI Slave is enabled and disabled by writing to the SPIENR register.

Register Layout

Bits Access Reset Description
[3:0] RW 0x7 Data Frame Size
[5:4] RW 0x0 Frame Format
[6] RW 0x0 Serial Clock Phase
[7] RW 0x0 Serial Clock Polarity
[9:8] RW 0x0 Transfer Mode
[10] RW 0x0 Slave Output Enable
[11] RW 0x0 Shift Register Loop
[15:12] RW 0x0 Control Frame Size
[31:16] ??? 0x0 UNDEFINED

Field : Data Frame Size - dfs

Selects the data frame length. When the data frame size is programmed to be less than 16 bits, the receive data are automatically right-justified by the receive logic, with the upper bits of the receiver FIFO zero-padded. You must right- justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT 0x3 4-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT 0x4 5-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT 0x5 6-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT 0x6 7-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT 0x7 8-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT 0x8 9-bit serial data transfer
ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT 0x9 10-bit serial data transfer

Field Access Macros:

#define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT   0x3
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT   0x4
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT   0x5
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT   0x6
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT   0x7
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT   0x8
 
#define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT   0x9
 
#define ALT_SPIS_CTLR0_DFS_LSB   0
 
#define ALT_SPIS_CTLR0_DFS_MSB   3
 
#define ALT_SPIS_CTLR0_DFS_WIDTH   4
 
#define ALT_SPIS_CTLR0_DFS_SET_MSK   0x0000000f
 
#define ALT_SPIS_CTLR0_DFS_CLR_MSK   0xfffffff0
 
#define ALT_SPIS_CTLR0_DFS_RESET   0x7
 
#define ALT_SPIS_CTLR0_DFS_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_SPIS_CTLR0_DFS_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : Frame Format - frf

Selects which serial protocol transfers the data.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_FRF_E_MOTSPI 0x0 Motorola SPI
ALT_SPIS_CTLR0_FRF_E_TISSP 0x1 Texas instruments SSP
ALT_SPIS_CTLR0_FRF_E_NATMW 0x2 National Semi Microwire

Field Access Macros:

#define ALT_SPIS_CTLR0_FRF_E_MOTSPI   0x0
 
#define ALT_SPIS_CTLR0_FRF_E_TISSP   0x1
 
#define ALT_SPIS_CTLR0_FRF_E_NATMW   0x2
 
#define ALT_SPIS_CTLR0_FRF_LSB   4
 
#define ALT_SPIS_CTLR0_FRF_MSB   5
 
#define ALT_SPIS_CTLR0_FRF_WIDTH   2
 
#define ALT_SPIS_CTLR0_FRF_SET_MSK   0x00000030
 
#define ALT_SPIS_CTLR0_FRF_CLR_MSK   0xffffffcf
 
#define ALT_SPIS_CTLR0_FRF_RESET   0x0
 
#define ALT_SPIS_CTLR0_FRF_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_SPIS_CTLR0_FRF_SET(value)   (((value) << 4) & 0x00000030)
 

Field : Serial Clock Phase - scph

Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_SCPH_E_INACTLOW 0x0 Inactive state of serial clock is low
ALT_SPIS_CTLR0_SCPH_E_INACTHIGH 0x1 Inactive state of serial clock is high

Field Access Macros:

#define ALT_SPIS_CTLR0_SCPH_E_INACTLOW   0x0
 
#define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH   0x1
 
#define ALT_SPIS_CTLR0_SCPH_LSB   6
 
#define ALT_SPIS_CTLR0_SCPH_MSB   6
 
#define ALT_SPIS_CTLR0_SCPH_WIDTH   1
 
#define ALT_SPIS_CTLR0_SCPH_SET_MSK   0x00000040
 
#define ALT_SPIS_CTLR0_SCPH_CLR_MSK   0xffffffbf
 
#define ALT_SPIS_CTLR0_SCPH_RESET   0x0
 
#define ALT_SPIS_CTLR0_SCPH_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SPIS_CTLR0_SCPH_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Serial Clock Polarity - scpol

Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock, which is held inactive when the spi master is not actively transferring data on the serial bus.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_SCPOL_E_MIDBIT 0x0 Serial clock toggles in middle of first data bit
ALT_SPIS_CTLR0_SCPOL_E_STARTBIT 0x1 Serial clock toggles at start of first data bit

Field Access Macros:

#define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT   0x0
 
#define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT   0x1
 
#define ALT_SPIS_CTLR0_SCPOL_LSB   7
 
#define ALT_SPIS_CTLR0_SCPOL_MSB   7
 
#define ALT_SPIS_CTLR0_SCPOL_WIDTH   1
 
#define ALT_SPIS_CTLR0_SCPOL_SET_MSK   0x00000080
 
#define ALT_SPIS_CTLR0_SCPOL_CLR_MSK   0xffffff7f
 
#define ALT_SPIS_CTLR0_SCPOL_RESET   0x0
 
#define ALT_SPIS_CTLR0_SCPOL_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SPIS_CTLR0_SCPOL_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Transfer Mode - tmod

Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In receive-only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_TMOD_E_TXRX 0x0 Transmit & and Receive
ALT_SPIS_CTLR0_TMOD_E_TXONLY 0x1 Transmit Only
ALT_SPIS_CTLR0_TMOD_E_RXONLY 0x2 Receive Only

Field Access Macros:

#define ALT_SPIS_CTLR0_TMOD_E_TXRX   0x0
 
#define ALT_SPIS_CTLR0_TMOD_E_TXONLY   0x1
 
#define ALT_SPIS_CTLR0_TMOD_E_RXONLY   0x2
 
#define ALT_SPIS_CTLR0_TMOD_LSB   8
 
#define ALT_SPIS_CTLR0_TMOD_MSB   9
 
#define ALT_SPIS_CTLR0_TMOD_WIDTH   2
 
#define ALT_SPIS_CTLR0_TMOD_SET_MSK   0x00000300
 
#define ALT_SPIS_CTLR0_TMOD_CLR_MSK   0xfffffcff
 
#define ALT_SPIS_CTLR0_TMOD_RESET   0x0
 
#define ALT_SPIS_CTLR0_TMOD_GET(value)   (((value) & 0x00000300) >> 8)
 
#define ALT_SPIS_CTLR0_TMOD_SET(value)   (((value) << 8) & 0x00000300)
 

Field : Slave Output Enable - slv_oe

This bit enables or disables the setting of the spis0_ssi_oe_n output from the SPI Slave. When SLV_OE = 1, the spis0_ssi_oe_n output can never be active. When the spis0_ssi_oe_n output controls the tri-state buffer on the txd output from the slave, a high impedance state is always present on the slave spis0_txd output when SLV_OE = 1. This is useful when the master transmits in broadcast mode (master transmits data to all slave devices). Only one slave may respond with data on the master spis0_rxd line. This bit is enabled after reset and must be disabled by software (when broadcast mode is used), if you do not want this device to respond with data.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_SLV_OE_E_END 0x0 Slave txd is enabled
ALT_SPIS_CTLR0_SLV_OE_E_DISD 0x1 Slave txd is disabled

Field Access Macros:

#define ALT_SPIS_CTLR0_SLV_OE_E_END   0x0
 
#define ALT_SPIS_CTLR0_SLV_OE_E_DISD   0x1
 
#define ALT_SPIS_CTLR0_SLV_OE_LSB   10
 
#define ALT_SPIS_CTLR0_SLV_OE_MSB   10
 
#define ALT_SPIS_CTLR0_SLV_OE_WIDTH   1
 
#define ALT_SPIS_CTLR0_SLV_OE_SET_MSK   0x00000400
 
#define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK   0xfffffbff
 
#define ALT_SPIS_CTLR0_SLV_OE_RESET   0x0
 
#define ALT_SPIS_CTLR0_SLV_OE_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SPIS_CTLR0_SLV_OE_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Shift Register Loop - srl

Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input.

Field Enumeration Values:

Enum Value Description
ALT_SPIS_CTLR0_SRL_E_NORMMOD 0x0 Normal Mode Operation
ALT_SPIS_CTLR0_SRL_E_TESTMOD 0x1 Test Mode Operation

Field Access Macros:

#define ALT_SPIS_CTLR0_SRL_E_NORMMOD   0x0
 
#define ALT_SPIS_CTLR0_SRL_E_TESTMOD   0x1
 
#define ALT_SPIS_CTLR0_SRL_LSB   11
 
#define ALT_SPIS_CTLR0_SRL_MSB   11
 
#define ALT_SPIS_CTLR0_SRL_WIDTH   1
 
#define ALT_SPIS_CTLR0_SRL_SET_MSK   0x00000800
 
#define ALT_SPIS_CTLR0_SRL_CLR_MSK   0xfffff7ff
 
#define ALT_SPIS_CTLR0_SRL_RESET   0x0
 
#define ALT_SPIS_CTLR0_SRL_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SPIS_CTLR0_SRL_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Control Frame Size - cfs

Selects the length of the control word for the Microwire frame format. The length (in bits) is the value of this field plus 1.

Field Access Macros:

#define ALT_SPIS_CTLR0_CFS_LSB   12
 
#define ALT_SPIS_CTLR0_CFS_MSB   15
 
#define ALT_SPIS_CTLR0_CFS_WIDTH   4
 
#define ALT_SPIS_CTLR0_CFS_SET_MSK   0x0000f000
 
#define ALT_SPIS_CTLR0_CFS_CLR_MSK   0xffff0fff
 
#define ALT_SPIS_CTLR0_CFS_RESET   0x0
 
#define ALT_SPIS_CTLR0_CFS_GET(value)   (((value) & 0x0000f000) >> 12)
 
#define ALT_SPIS_CTLR0_CFS_SET(value)   (((value) << 12) & 0x0000f000)
 

Data Structures

struct  ALT_SPIS_CTLR0_s
 

Macros

#define ALT_SPIS_CTLR0_OFST   0x0
 
#define ALT_SPIS_CTLR0_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))
 

Typedefs

typedef struct ALT_SPIS_CTLR0_s ALT_SPIS_CTLR0_t
 

Data Structure Documentation

struct ALT_SPIS_CTLR0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SPIS_CTLR0.

Data Fields
uint32_t dfs: 4 Data Frame Size
uint32_t frf: 2 Frame Format
uint32_t scph: 1 Serial Clock Phase
uint32_t scpol: 1 Serial Clock Polarity
uint32_t tmod: 2 Transfer Mode
uint32_t slv_oe: 1 Slave Output Enable
uint32_t srl: 1 Shift Register Loop
uint32_t cfs: 4 Control Frame Size
uint32_t __pad0__: 16 UNDEFINED

Macro Definitions

#define ALT_SPIS_CTLR0_DFS_E_WIDTH4BIT   0x3

Enumerated value for register field ALT_SPIS_CTLR0_DFS

4-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH5BIT   0x4

Enumerated value for register field ALT_SPIS_CTLR0_DFS

5-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH6BIT   0x5

Enumerated value for register field ALT_SPIS_CTLR0_DFS

6-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH7BIT   0x6

Enumerated value for register field ALT_SPIS_CTLR0_DFS

7-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH8BIT   0x7

Enumerated value for register field ALT_SPIS_CTLR0_DFS

8-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH9BIT   0x8

Enumerated value for register field ALT_SPIS_CTLR0_DFS

9-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_E_WIDTH10BIT   0x9

Enumerated value for register field ALT_SPIS_CTLR0_DFS

10-bit serial data transfer

#define ALT_SPIS_CTLR0_DFS_LSB   0

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_DFS register field.

#define ALT_SPIS_CTLR0_DFS_MSB   3

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_DFS register field.

#define ALT_SPIS_CTLR0_DFS_WIDTH   4

The width in bits of the ALT_SPIS_CTLR0_DFS register field.

#define ALT_SPIS_CTLR0_DFS_SET_MSK   0x0000000f

The mask used to set the ALT_SPIS_CTLR0_DFS register field value.

#define ALT_SPIS_CTLR0_DFS_CLR_MSK   0xfffffff0

The mask used to clear the ALT_SPIS_CTLR0_DFS register field value.

#define ALT_SPIS_CTLR0_DFS_RESET   0x7

The reset value of the ALT_SPIS_CTLR0_DFS register field.

#define ALT_SPIS_CTLR0_DFS_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_SPIS_CTLR0_DFS field value from a register.

#define ALT_SPIS_CTLR0_DFS_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_SPIS_CTLR0_DFS register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_FRF_E_MOTSPI   0x0

Enumerated value for register field ALT_SPIS_CTLR0_FRF

Motorola SPI

#define ALT_SPIS_CTLR0_FRF_E_TISSP   0x1

Enumerated value for register field ALT_SPIS_CTLR0_FRF

Texas instruments SSP

#define ALT_SPIS_CTLR0_FRF_E_NATMW   0x2

Enumerated value for register field ALT_SPIS_CTLR0_FRF

National Semi Microwire

#define ALT_SPIS_CTLR0_FRF_LSB   4

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_FRF register field.

#define ALT_SPIS_CTLR0_FRF_MSB   5

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_FRF register field.

#define ALT_SPIS_CTLR0_FRF_WIDTH   2

The width in bits of the ALT_SPIS_CTLR0_FRF register field.

#define ALT_SPIS_CTLR0_FRF_SET_MSK   0x00000030

The mask used to set the ALT_SPIS_CTLR0_FRF register field value.

#define ALT_SPIS_CTLR0_FRF_CLR_MSK   0xffffffcf

The mask used to clear the ALT_SPIS_CTLR0_FRF register field value.

#define ALT_SPIS_CTLR0_FRF_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_FRF register field.

#define ALT_SPIS_CTLR0_FRF_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_SPIS_CTLR0_FRF field value from a register.

#define ALT_SPIS_CTLR0_FRF_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_SPIS_CTLR0_FRF register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_SCPH_E_INACTLOW   0x0

Enumerated value for register field ALT_SPIS_CTLR0_SCPH

Inactive state of serial clock is low

#define ALT_SPIS_CTLR0_SCPH_E_INACTHIGH   0x1

Enumerated value for register field ALT_SPIS_CTLR0_SCPH

Inactive state of serial clock is high

#define ALT_SPIS_CTLR0_SCPH_LSB   6

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPH register field.

#define ALT_SPIS_CTLR0_SCPH_MSB   6

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPH register field.

#define ALT_SPIS_CTLR0_SCPH_WIDTH   1

The width in bits of the ALT_SPIS_CTLR0_SCPH register field.

#define ALT_SPIS_CTLR0_SCPH_SET_MSK   0x00000040

The mask used to set the ALT_SPIS_CTLR0_SCPH register field value.

#define ALT_SPIS_CTLR0_SCPH_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SPIS_CTLR0_SCPH register field value.

#define ALT_SPIS_CTLR0_SCPH_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_SCPH register field.

#define ALT_SPIS_CTLR0_SCPH_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SPIS_CTLR0_SCPH field value from a register.

#define ALT_SPIS_CTLR0_SCPH_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SPIS_CTLR0_SCPH register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_SCPOL_E_MIDBIT   0x0

Enumerated value for register field ALT_SPIS_CTLR0_SCPOL

Serial clock toggles in middle of first data bit

#define ALT_SPIS_CTLR0_SCPOL_E_STARTBIT   0x1

Enumerated value for register field ALT_SPIS_CTLR0_SCPOL

Serial clock toggles at start of first data bit

#define ALT_SPIS_CTLR0_SCPOL_LSB   7

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SCPOL register field.

#define ALT_SPIS_CTLR0_SCPOL_MSB   7

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SCPOL register field.

#define ALT_SPIS_CTLR0_SCPOL_WIDTH   1

The width in bits of the ALT_SPIS_CTLR0_SCPOL register field.

#define ALT_SPIS_CTLR0_SCPOL_SET_MSK   0x00000080

The mask used to set the ALT_SPIS_CTLR0_SCPOL register field value.

#define ALT_SPIS_CTLR0_SCPOL_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SPIS_CTLR0_SCPOL register field value.

#define ALT_SPIS_CTLR0_SCPOL_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_SCPOL register field.

#define ALT_SPIS_CTLR0_SCPOL_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SPIS_CTLR0_SCPOL field value from a register.

#define ALT_SPIS_CTLR0_SCPOL_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SPIS_CTLR0_SCPOL register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_TMOD_E_TXRX   0x0

Enumerated value for register field ALT_SPIS_CTLR0_TMOD

Transmit & and Receive

#define ALT_SPIS_CTLR0_TMOD_E_TXONLY   0x1

Enumerated value for register field ALT_SPIS_CTLR0_TMOD

Transmit Only

#define ALT_SPIS_CTLR0_TMOD_E_RXONLY   0x2

Enumerated value for register field ALT_SPIS_CTLR0_TMOD

Receive Only

#define ALT_SPIS_CTLR0_TMOD_LSB   8

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_TMOD register field.

#define ALT_SPIS_CTLR0_TMOD_MSB   9

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_TMOD register field.

#define ALT_SPIS_CTLR0_TMOD_WIDTH   2

The width in bits of the ALT_SPIS_CTLR0_TMOD register field.

#define ALT_SPIS_CTLR0_TMOD_SET_MSK   0x00000300

The mask used to set the ALT_SPIS_CTLR0_TMOD register field value.

#define ALT_SPIS_CTLR0_TMOD_CLR_MSK   0xfffffcff

The mask used to clear the ALT_SPIS_CTLR0_TMOD register field value.

#define ALT_SPIS_CTLR0_TMOD_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_TMOD register field.

#define ALT_SPIS_CTLR0_TMOD_GET (   value)    (((value) & 0x00000300) >> 8)

Extracts the ALT_SPIS_CTLR0_TMOD field value from a register.

#define ALT_SPIS_CTLR0_TMOD_SET (   value)    (((value) << 8) & 0x00000300)

Produces a ALT_SPIS_CTLR0_TMOD register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_SLV_OE_E_END   0x0

Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE

Slave txd is enabled

#define ALT_SPIS_CTLR0_SLV_OE_E_DISD   0x1

Enumerated value for register field ALT_SPIS_CTLR0_SLV_OE

Slave txd is disabled

#define ALT_SPIS_CTLR0_SLV_OE_LSB   10

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SLV_OE register field.

#define ALT_SPIS_CTLR0_SLV_OE_MSB   10

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SLV_OE register field.

#define ALT_SPIS_CTLR0_SLV_OE_WIDTH   1

The width in bits of the ALT_SPIS_CTLR0_SLV_OE register field.

#define ALT_SPIS_CTLR0_SLV_OE_SET_MSK   0x00000400

The mask used to set the ALT_SPIS_CTLR0_SLV_OE register field value.

#define ALT_SPIS_CTLR0_SLV_OE_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SPIS_CTLR0_SLV_OE register field value.

#define ALT_SPIS_CTLR0_SLV_OE_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_SLV_OE register field.

#define ALT_SPIS_CTLR0_SLV_OE_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SPIS_CTLR0_SLV_OE field value from a register.

#define ALT_SPIS_CTLR0_SLV_OE_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SPIS_CTLR0_SLV_OE register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_SRL_E_NORMMOD   0x0

Enumerated value for register field ALT_SPIS_CTLR0_SRL

Normal Mode Operation

#define ALT_SPIS_CTLR0_SRL_E_TESTMOD   0x1

Enumerated value for register field ALT_SPIS_CTLR0_SRL

Test Mode Operation

#define ALT_SPIS_CTLR0_SRL_LSB   11

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_SRL register field.

#define ALT_SPIS_CTLR0_SRL_MSB   11

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_SRL register field.

#define ALT_SPIS_CTLR0_SRL_WIDTH   1

The width in bits of the ALT_SPIS_CTLR0_SRL register field.

#define ALT_SPIS_CTLR0_SRL_SET_MSK   0x00000800

The mask used to set the ALT_SPIS_CTLR0_SRL register field value.

#define ALT_SPIS_CTLR0_SRL_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SPIS_CTLR0_SRL register field value.

#define ALT_SPIS_CTLR0_SRL_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_SRL register field.

#define ALT_SPIS_CTLR0_SRL_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SPIS_CTLR0_SRL field value from a register.

#define ALT_SPIS_CTLR0_SRL_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SPIS_CTLR0_SRL register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_CFS_LSB   12

The Least Significant Bit (LSB) position of the ALT_SPIS_CTLR0_CFS register field.

#define ALT_SPIS_CTLR0_CFS_MSB   15

The Most Significant Bit (MSB) position of the ALT_SPIS_CTLR0_CFS register field.

#define ALT_SPIS_CTLR0_CFS_WIDTH   4

The width in bits of the ALT_SPIS_CTLR0_CFS register field.

#define ALT_SPIS_CTLR0_CFS_SET_MSK   0x0000f000

The mask used to set the ALT_SPIS_CTLR0_CFS register field value.

#define ALT_SPIS_CTLR0_CFS_CLR_MSK   0xffff0fff

The mask used to clear the ALT_SPIS_CTLR0_CFS register field value.

#define ALT_SPIS_CTLR0_CFS_RESET   0x0

The reset value of the ALT_SPIS_CTLR0_CFS register field.

#define ALT_SPIS_CTLR0_CFS_GET (   value)    (((value) & 0x0000f000) >> 12)

Extracts the ALT_SPIS_CTLR0_CFS field value from a register.

#define ALT_SPIS_CTLR0_CFS_SET (   value)    (((value) << 12) & 0x0000f000)

Produces a ALT_SPIS_CTLR0_CFS register field value suitable for setting the register.

#define ALT_SPIS_CTLR0_OFST   0x0

The byte offset of the ALT_SPIS_CTLR0 register from the beginning of the component.

#define ALT_SPIS_CTLR0_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIS_CTLR0_OFST))

The address of the ALT_SPIS_CTLR0 register.

Typedef Documentation

The typedef declaration for register ALT_SPIS_CTLR0.