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Altera HWLIB
16.0
The Altera HW Manager API Reference Manual
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These functions provide a simple, low-latency, low-performance signal interface between the SoC and the FPGA. There is a General Purpose Output (GPO) register that provides a path to drive up to 32 signals from the SoC to the FPGA. There is a General Purpose Input (GPI) register that provides a path to read up to 32 signals driven from the FPGA to the SoC.
Typedefs | |
typedef enum ALT_FPGA_GPI_e | ALT_FPGA_GPI_t |
typedef enum ALT_FPGA_GPO_e | ALT_FPGA_GPO_t |
ENUMS | |
enum | ALT_FPGA_GPI_e { ALT_FPGA_GPI_0 = (int32_t)(1UL << 0), ALT_FPGA_GPI_1 = (int32_t)(1UL << 1), ALT_FPGA_GPI_2 = (int32_t)(1UL << 2), ALT_FPGA_GPI_3 = (int32_t)(1UL << 3), ALT_FPGA_GPI_4 = (int32_t)(1UL << 4), ALT_FPGA_GPI_5 = (int32_t)(1UL << 5), ALT_FPGA_GPI_6 = (int32_t)(1UL << 6), ALT_FPGA_GPI_7 = (int32_t)(1UL << 7), ALT_FPGA_GPI_8 = (int32_t)(1UL << 8), ALT_FPGA_GPI_9 = (int32_t)(1UL << 9), ALT_FPGA_GPI_10 = (int32_t)(1UL << 10), ALT_FPGA_GPI_11 = (int32_t)(1UL << 11), ALT_FPGA_GPI_12 = (int32_t)(1UL << 12), ALT_FPGA_GPI_13 = (int32_t)(1UL << 13), ALT_FPGA_GPI_14 = (int32_t)(1UL << 14), ALT_FPGA_GPI_15 = (int32_t)(1UL << 15), ALT_FPGA_GPI_16 = (int32_t)(1UL << 16), ALT_FPGA_GPI_17 = (int32_t)(1UL << 17), ALT_FPGA_GPI_18 = (int32_t)(1UL << 18), ALT_FPGA_GPI_19 = (int32_t)(1UL << 19), ALT_FPGA_GPI_20 = (int32_t)(1UL << 20), ALT_FPGA_GPI_21 = (int32_t)(1UL << 21), ALT_FPGA_GPI_22 = (int32_t)(1UL << 22), ALT_FPGA_GPI_23 = (int32_t)(1UL << 23), ALT_FPGA_GPI_24 = (int32_t)(1UL << 24), ALT_FPGA_GPI_25 = (int32_t)(1UL << 25), ALT_FPGA_GPI_26 = (int32_t)(1UL << 26), ALT_FPGA_GPI_27 = (int32_t)(1UL << 27), ALT_FPGA_GPI_28 = (int32_t)(1UL << 28), ALT_FPGA_GPI_29 = (int32_t)(1UL << 29), ALT_FPGA_GPI_30 = (int32_t)(1UL << 30), ALT_FPGA_GPI_31 = (int32_t)(1UL << 31) } |
enum | ALT_FPGA_GPO_e { ALT_FPGA_GPO_0 = (int32_t)(1UL << 0), ALT_FPGA_GPO_1 = (int32_t)(1UL << 1), ALT_FPGA_GPO_2 = (int32_t)(1UL << 2), ALT_FPGA_GPO_3 = (int32_t)(1UL << 3), ALT_FPGA_GPO_4 = (int32_t)(1UL << 4), ALT_FPGA_GPO_5 = (int32_t)(1UL << 5), ALT_FPGA_GPO_6 = (int32_t)(1UL << 6), ALT_FPGA_GPO_7 = (int32_t)(1UL << 7), ALT_FPGA_GPO_8 = (int32_t)(1UL << 8), ALT_FPGA_GPO_9 = (int32_t)(1UL << 9), ALT_FPGA_GPO_10 = (int32_t)(1UL << 10), ALT_FPGA_GPO_11 = (int32_t)(1UL << 11), ALT_FPGA_GPO_12 = (int32_t)(1UL << 12), ALT_FPGA_GPO_13 = (int32_t)(1UL << 13), ALT_FPGA_GPO_14 = (int32_t)(1UL << 14), ALT_FPGA_GPO_15 = (int32_t)(1UL << 15), ALT_FPGA_GPO_16 = (int32_t)(1UL << 16), ALT_FPGA_GPO_17 = (int32_t)(1UL << 17), ALT_FPGA_GPO_18 = (int32_t)(1UL << 18), ALT_FPGA_GPO_19 = (int32_t)(1UL << 19), ALT_FPGA_GPO_20 = (int32_t)(1UL << 20), ALT_FPGA_GPO_21 = (int32_t)(1UL << 21), ALT_FPGA_GPO_22 = (int32_t)(1UL << 22), ALT_FPGA_GPO_23 = (int32_t)(1UL << 23), ALT_FPGA_GPO_24 = (int32_t)(1UL << 24), ALT_FPGA_GPO_25 = (int32_t)(1UL << 25), ALT_FPGA_GPO_26 = (int32_t)(1UL << 26), ALT_FPGA_GPO_27 = (int32_t)(1UL << 27), ALT_FPGA_GPO_28 = (int32_t)(1UL << 28), ALT_FPGA_GPO_29 = (int32_t)(1UL << 29), ALT_FPGA_GPO_30 = (int32_t)(1UL << 30), ALT_FPGA_GPO_31 = (int32_t)(1UL << 31) } |
Functions | |
uint32_t | alt_fpga_gpi_read (uint32_t mask) |
ALT_STATUS_CODE | alt_fpga_gpo_write (uint32_t mask, uint32_t value) |
typedef enum ALT_FPGA_GPI_e ALT_FPGA_GPI_t |
This type definition enumerates the signal mask selections for the General Purpose Input (GPI) signals driven from the FPGA to the SoC.
typedef enum ALT_FPGA_GPO_e ALT_FPGA_GPO_t |
This type definition enumerates the signal mask selections for the General Purpose Output (GPO) signals driven from the SoC to the FPGA.
enum ALT_FPGA_GPI_e |
This type definition enumerates the signal mask selections for the General Purpose Input (GPI) signals driven from the FPGA to the SoC.
enum ALT_FPGA_GPO_e |
This type definition enumerates the signal mask selections for the General Purpose Output (GPO) signals driven from the SoC to the FPGA.
uint32_t alt_fpga_gpi_read | ( | uint32_t | mask | ) |
Reads the General Purpose Input (GPI) register value.
Returns the GPI register value that is the masked selection of the 32 f2s_gp signal values driven by the FPGA. The mask may be defined by the logical OR of ALT_FPGA_GPI_t values.
NOTE: If the FPGA is not in User Mode then the value of this register undefined.
mask | The set of signals (where mask bits equal one) to read. Other signals values (where mask bits equal zero) are returned as 0. |
ALT_STATUS_CODE alt_fpga_gpo_write | ( | uint32_t | mask, |
uint32_t | value | ||
) |
Writes the General Purpose Output (GPO) register value.
Writes the GPO data outputs with the specified values. The GPO drives the 32 s2f_gp signal values to the FPGA. Output signals are only written if their corresponding mask bits are set.
NOTE: If the FPGA is not in User Mode then the effect of this operation is undefined.
mask | The set of signals (where mask bits equal one) to write. Other signals (where mask bits equal zero) are not changed. The mask may be defined by the logical OR of ALT_FPGA_GPO_t values. |
value | The 32-bit aggregate GPO register value. Values for the corressponding signal bits specified in the mask are written to the FPGA signals. |
ALT_E_SUCCESS | Successful status. |
ALT_E_ERROR | The write failed. |