Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Status Register - stat

Description

The STAT register contains bits that indicate the reset source. For reset sources, a field is 1 if its associated reset requester caused the reset.

Software clears bits by writing them with a value of 1. Writes to bits with a value of 0 are ignored.

After a cold reset is complete, all bits are reset to their reset value except for the bit(s) that indicate the source of the cold reset. If multiple cold reset requests overlap with each other, the source de-asserts the request last will be logged. The other reset request source(s) de-assert the request in the same cycle will also be logged, the rest of the fields are reset to default value of 0.

After a warm reset is complete, the bit(s) that indicate the source of the warm reset are set to 1. A warm reset doesn't clear any of the bits in the STAT register; these bits must be cleared by software writing the STAT register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 HPS Power-On Voltage Detector Cold Reset
[1] RW 0x0 Power-On FPGA Voltage Detector Cold Reset
[2] RW 0x0 nPOR Pin Cold Reset
[3] RW 0x0 FPGA Core Cold Reset
[4] RW 0x0 CONFIG_IO Cold Reset
[5] RW 0x0 Software Cold Reset
[7:6] ??? 0x0 UNDEFINED
[8] RW 0x0 nRST Pin Warm Reset
[9] RW 0x0 FPGA Core Warm Reset
[10] RW 0x0 Software Warm Reset
[11] RW 0x0 MPU Watchdog 0 Warm Reset
[12] RW 0x0 MPU Watchdog 1 Warm Reset
[13] RW 0x0 L4 Watchdog 0 Warm Reset
[14] RW 0x0 L4 Watchdog 1 Warm Reset
[15] ??? 0x0 UNDEFINED
[16] RW 0x0 FPGA Core Debug Reset
[17] RW 0x0 DAP Debug Reset
[31:18] ??? 0x0 UNDEFINED

Field : HPS Power-On Voltage Detector Cold Reset - porhpsvoltrst

Built-in HPS POR voltage detector triggered a cold reset. Security Manager brought Reset Manager out of POR Reset.

Field Access Macros:

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_LSB   0
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_MSB   0
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET_MSK   0x00000001
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_CLR_MSK   0xfffffffe
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Power-On FPGA Voltage Detector Cold Reset - porfpgavoltrst

Built-in FPGA POR voltage detector triggered a cold reset. Security Manager brought Reset Manager out of POR Reset.

Field Access Macros:

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_LSB   1
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_MSB   1
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET_MSK   0x00000002
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_CLR_MSK   0xfffffffd
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET(value)   (((value) << 1) & 0x00000002)
 

Field : nPOR Pin Cold Reset - nporpinrst

nPOR pin triggered a cold reset (por_pin_req = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_NPORPINRST_LSB   2
 
#define ALT_RSTMGR_STAT_NPORPINRST_MSB   2
 
#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK   0x00000004
 
#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK   0xfffffffb
 
#define ALT_RSTMGR_STAT_NPORPINRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_NPORPINRST_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_RSTMGR_STAT_NPORPINRST_SET(value)   (((value) << 2) & 0x00000004)
 

Field : FPGA Core Cold Reset - fpgacoldrst

FPGA core triggered a cold reset (f2s_cold_rst_req = 1)

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB   3
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB   3
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK   0x00000008
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK   0xfffffff7
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_RSTMGR_STAT_FPGACOLDRST_SET(value)   (((value) << 3) & 0x00000008)
 

Field : CONFIG_IO Cold Reset - configiocoldrst

FPGA entered CONFIG_IO mode and a triggered a cold reset

Field Access Macros:

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB   4
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB   4
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK   0x00000010
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK   0xffffffef
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Software Cold Reset - swcoldrst

Software wrote CTRL.SWCOLDRSTREQ to 1 and triggered a cold reset.

Field Access Macros:

#define ALT_RSTMGR_STAT_SWCOLDRST_LSB   5
 
#define ALT_RSTMGR_STAT_SWCOLDRST_MSB   5
 
#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK   0x00000020
 
#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK   0xffffffdf
 
#define ALT_RSTMGR_STAT_SWCOLDRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_SWCOLDRST_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_RSTMGR_STAT_SWCOLDRST_SET(value)   (((value) << 5) & 0x00000020)
 

Field : nRST Pin Warm Reset - nrstpinrst

nRST pin triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_NRSTPINRST_LSB   8
 
#define ALT_RSTMGR_STAT_NRSTPINRST_MSB   8
 
#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK   0x00000100
 
#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK   0xfffffeff
 
#define ALT_RSTMGR_STAT_NRSTPINRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_NRSTPINRST_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_RSTMGR_STAT_NRSTPINRST_SET(value)   (((value) << 8) & 0x00000100)
 

Field : FPGA Core Warm Reset - fpgawarmrst

FPGA core triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB   9
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB   9
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK   0x00000200
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK   0xfffffdff
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_RSTMGR_STAT_FPGAWARMRST_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Software Warm Reset - swwarmrst

Software wrote CTRL.SWARMRSTREQ to 1 and triggered a hardware sequenced warm reset.

Field Access Macros:

#define ALT_RSTMGR_STAT_SWWARMRST_LSB   10
 
#define ALT_RSTMGR_STAT_SWWARMRST_MSB   10
 
#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK   0x00000400
 
#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK   0xfffffbff
 
#define ALT_RSTMGR_STAT_SWWARMRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_SWWARMRST_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_RSTMGR_STAT_SWWARMRST_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MPU Watchdog 0 Warm Reset - mpuwd0rst

MPU Watchdog 0 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_MPUWD0RST_LSB   11
 
#define ALT_RSTMGR_STAT_MPUWD0RST_MSB   11
 
#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK   0x00000800
 
#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK   0xfffff7ff
 
#define ALT_RSTMGR_STAT_MPUWD0RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_MPUWD0RST_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_RSTMGR_STAT_MPUWD0RST_SET(value)   (((value) << 11) & 0x00000800)
 

Field : MPU Watchdog 1 Warm Reset - mpuwd1rst

MPU Watchdog 1 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_MPUWD1RST_LSB   12
 
#define ALT_RSTMGR_STAT_MPUWD1RST_MSB   12
 
#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK   0x00001000
 
#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK   0xffffefff
 
#define ALT_RSTMGR_STAT_MPUWD1RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_MPUWD1RST_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_RSTMGR_STAT_MPUWD1RST_SET(value)   (((value) << 12) & 0x00001000)
 

Field : L4 Watchdog 0 Warm Reset - l4wd0rst

L4 Watchdog 0 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_L4WD0RST_LSB   13
 
#define ALT_RSTMGR_STAT_L4WD0RST_MSB   13
 
#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK   0x00002000
 
#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK   0xffffdfff
 
#define ALT_RSTMGR_STAT_L4WD0RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_L4WD0RST_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_RSTMGR_STAT_L4WD0RST_SET(value)   (((value) << 13) & 0x00002000)
 

Field : L4 Watchdog 1 Warm Reset - l4wd1rst

L4 Watchdog 1 triggered a hardware sequenced warm reset

Field Access Macros:

#define ALT_RSTMGR_STAT_L4WD1RST_LSB   14
 
#define ALT_RSTMGR_STAT_L4WD1RST_MSB   14
 
#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH   1
 
#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK   0x00004000
 
#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK   0xffffbfff
 
#define ALT_RSTMGR_STAT_L4WD1RST_RESET   0x0
 
#define ALT_RSTMGR_STAT_L4WD1RST_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_RSTMGR_STAT_L4WD1RST_SET(value)   (((value) << 14) & 0x00004000)
 

Field : FPGA Core Debug Reset - fpgadbgrst

FPGA triggered debug reset

Field Access Macros:

#define ALT_RSTMGR_STAT_FPGADBGRST_LSB   16
 
#define ALT_RSTMGR_STAT_FPGADBGRST_MSB   16
 
#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK   0x00010000
 
#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK   0xfffeffff
 
#define ALT_RSTMGR_STAT_FPGADBGRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_FPGADBGRST_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_RSTMGR_STAT_FPGADBGRST_SET(value)   (((value) << 16) & 0x00010000)
 

Field : DAP Debug Reset - cdbgreqrst

DAP triggered debug reset

Field Access Macros:

#define ALT_RSTMGR_STAT_CDBGREQRST_LSB   17
 
#define ALT_RSTMGR_STAT_CDBGREQRST_MSB   17
 
#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH   1
 
#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK   0x00020000
 
#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK   0xfffdffff
 
#define ALT_RSTMGR_STAT_CDBGREQRST_RESET   0x0
 
#define ALT_RSTMGR_STAT_CDBGREQRST_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_RSTMGR_STAT_CDBGREQRST_SET(value)   (((value) << 17) & 0x00020000)
 

Data Structures

struct  ALT_RSTMGR_STAT_s
 

Macros

#define ALT_RSTMGR_STAT_RESET   0x00000000
 
#define ALT_RSTMGR_STAT_OFST   0x0
 

Typedefs

typedef struct ALT_RSTMGR_STAT_s ALT_RSTMGR_STAT_t
 

Data Structure Documentation

struct ALT_RSTMGR_STAT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_STAT.

Data Fields
uint32_t porhpsvoltrst: 1 HPS Power-On Voltage Detector Cold Reset
uint32_t porfpgavoltrst: 1 Power-On FPGA Voltage Detector Cold Reset
uint32_t nporpinrst: 1 nPOR Pin Cold Reset
uint32_t fpgacoldrst: 1 FPGA Core Cold Reset
uint32_t configiocoldrst: 1 CONFIG_IO Cold Reset
uint32_t swcoldrst: 1 Software Cold Reset
uint32_t __pad0__: 2 UNDEFINED
uint32_t nrstpinrst: 1 nRST Pin Warm Reset
uint32_t fpgawarmrst: 1 FPGA Core Warm Reset
uint32_t swwarmrst: 1 Software Warm Reset
uint32_t mpuwd0rst: 1 MPU Watchdog 0 Warm Reset
uint32_t mpuwd1rst: 1 MPU Watchdog 1 Warm Reset
uint32_t l4wd0rst: 1 L4 Watchdog 0 Warm Reset
uint32_t l4wd1rst: 1 L4 Watchdog 1 Warm Reset
uint32_t __pad1__: 1 UNDEFINED
uint32_t fpgadbgrst: 1 FPGA Core Debug Reset
uint32_t cdbgreqrst: 1 DAP Debug Reset
uint32_t __pad2__: 14 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_MSB   0

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET_MSK   0x00000001

The mask used to set the ALT_RSTMGR_STAT_PORHPSVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_CLR_MSK   0xfffffffe

The mask used to clear the ALT_RSTMGR_STAT_PORHPSVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_PORHPSVOLTRST register field.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_RSTMGR_STAT_PORHPSVOLTRST field value from a register.

#define ALT_RSTMGR_STAT_PORHPSVOLTRST_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_RSTMGR_STAT_PORHPSVOLTRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_LSB   1

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_MSB   1

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET_MSK   0x00000002

The mask used to set the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_CLR_MSK   0xfffffffd

The mask used to clear the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_PORFPGAVOLTRST register field.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_RSTMGR_STAT_PORFPGAVOLTRST field value from a register.

#define ALT_RSTMGR_STAT_PORFPGAVOLTRST_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_RSTMGR_STAT_PORFPGAVOLTRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_NPORPINRST_LSB   2

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_MSB   2

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_SET_MSK   0x00000004

The mask used to set the ALT_RSTMGR_STAT_NPORPINRST register field value.

#define ALT_RSTMGR_STAT_NPORPINRST_CLR_MSK   0xfffffffb

The mask used to clear the ALT_RSTMGR_STAT_NPORPINRST register field value.

#define ALT_RSTMGR_STAT_NPORPINRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_NPORPINRST register field.

#define ALT_RSTMGR_STAT_NPORPINRST_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_RSTMGR_STAT_NPORPINRST field value from a register.

#define ALT_RSTMGR_STAT_NPORPINRST_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_RSTMGR_STAT_NPORPINRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGACOLDRST_LSB   3

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_MSB   3

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_SET_MSK   0x00000008

The mask used to set the ALT_RSTMGR_STAT_FPGACOLDRST register field value.

#define ALT_RSTMGR_STAT_FPGACOLDRST_CLR_MSK   0xfffffff7

The mask used to clear the ALT_RSTMGR_STAT_FPGACOLDRST register field value.

#define ALT_RSTMGR_STAT_FPGACOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGACOLDRST register field.

#define ALT_RSTMGR_STAT_FPGACOLDRST_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_RSTMGR_STAT_FPGACOLDRST field value from a register.

#define ALT_RSTMGR_STAT_FPGACOLDRST_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_RSTMGR_STAT_FPGACOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_LSB   4

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_MSB   4

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET_MSK   0x00000010

The mask used to set the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_CLR_MSK   0xffffffef

The mask used to clear the ALT_RSTMGR_STAT_CFGIOCOLDRST register field value.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_CFGIOCOLDRST register field.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_RSTMGR_STAT_CFGIOCOLDRST field value from a register.

#define ALT_RSTMGR_STAT_CFGIOCOLDRST_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_RSTMGR_STAT_CFGIOCOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SWCOLDRST_LSB   5

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_MSB   5

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_SET_MSK   0x00000020

The mask used to set the ALT_RSTMGR_STAT_SWCOLDRST register field value.

#define ALT_RSTMGR_STAT_SWCOLDRST_CLR_MSK   0xffffffdf

The mask used to clear the ALT_RSTMGR_STAT_SWCOLDRST register field value.

#define ALT_RSTMGR_STAT_SWCOLDRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SWCOLDRST register field.

#define ALT_RSTMGR_STAT_SWCOLDRST_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_RSTMGR_STAT_SWCOLDRST field value from a register.

#define ALT_RSTMGR_STAT_SWCOLDRST_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_RSTMGR_STAT_SWCOLDRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_NRSTPINRST_LSB   8

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_MSB   8

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_SET_MSK   0x00000100

The mask used to set the ALT_RSTMGR_STAT_NRSTPINRST register field value.

#define ALT_RSTMGR_STAT_NRSTPINRST_CLR_MSK   0xfffffeff

The mask used to clear the ALT_RSTMGR_STAT_NRSTPINRST register field value.

#define ALT_RSTMGR_STAT_NRSTPINRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_NRSTPINRST register field.

#define ALT_RSTMGR_STAT_NRSTPINRST_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_RSTMGR_STAT_NRSTPINRST field value from a register.

#define ALT_RSTMGR_STAT_NRSTPINRST_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_RSTMGR_STAT_NRSTPINRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGAWARMRST_LSB   9

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_MSB   9

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_SET_MSK   0x00000200

The mask used to set the ALT_RSTMGR_STAT_FPGAWARMRST register field value.

#define ALT_RSTMGR_STAT_FPGAWARMRST_CLR_MSK   0xfffffdff

The mask used to clear the ALT_RSTMGR_STAT_FPGAWARMRST register field value.

#define ALT_RSTMGR_STAT_FPGAWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGAWARMRST register field.

#define ALT_RSTMGR_STAT_FPGAWARMRST_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_RSTMGR_STAT_FPGAWARMRST field value from a register.

#define ALT_RSTMGR_STAT_FPGAWARMRST_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_RSTMGR_STAT_FPGAWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_SWWARMRST_LSB   10

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_MSB   10

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_SET_MSK   0x00000400

The mask used to set the ALT_RSTMGR_STAT_SWWARMRST register field value.

#define ALT_RSTMGR_STAT_SWWARMRST_CLR_MSK   0xfffffbff

The mask used to clear the ALT_RSTMGR_STAT_SWWARMRST register field value.

#define ALT_RSTMGR_STAT_SWWARMRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_SWWARMRST register field.

#define ALT_RSTMGR_STAT_SWWARMRST_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_RSTMGR_STAT_SWWARMRST field value from a register.

#define ALT_RSTMGR_STAT_SWWARMRST_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_RSTMGR_STAT_SWWARMRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_MPUWD0RST_LSB   11

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_MSB   11

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_SET_MSK   0x00000800

The mask used to set the ALT_RSTMGR_STAT_MPUWD0RST register field value.

#define ALT_RSTMGR_STAT_MPUWD0RST_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_RSTMGR_STAT_MPUWD0RST register field value.

#define ALT_RSTMGR_STAT_MPUWD0RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_MPUWD0RST register field.

#define ALT_RSTMGR_STAT_MPUWD0RST_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_RSTMGR_STAT_MPUWD0RST field value from a register.

#define ALT_RSTMGR_STAT_MPUWD0RST_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_RSTMGR_STAT_MPUWD0RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_MPUWD1RST_LSB   12

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_MSB   12

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_SET_MSK   0x00001000

The mask used to set the ALT_RSTMGR_STAT_MPUWD1RST register field value.

#define ALT_RSTMGR_STAT_MPUWD1RST_CLR_MSK   0xffffefff

The mask used to clear the ALT_RSTMGR_STAT_MPUWD1RST register field value.

#define ALT_RSTMGR_STAT_MPUWD1RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_MPUWD1RST register field.

#define ALT_RSTMGR_STAT_MPUWD1RST_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_RSTMGR_STAT_MPUWD1RST field value from a register.

#define ALT_RSTMGR_STAT_MPUWD1RST_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_RSTMGR_STAT_MPUWD1RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_L4WD0RST_LSB   13

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_MSB   13

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_SET_MSK   0x00002000

The mask used to set the ALT_RSTMGR_STAT_L4WD0RST register field value.

#define ALT_RSTMGR_STAT_L4WD0RST_CLR_MSK   0xffffdfff

The mask used to clear the ALT_RSTMGR_STAT_L4WD0RST register field value.

#define ALT_RSTMGR_STAT_L4WD0RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_L4WD0RST register field.

#define ALT_RSTMGR_STAT_L4WD0RST_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_RSTMGR_STAT_L4WD0RST field value from a register.

#define ALT_RSTMGR_STAT_L4WD0RST_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_RSTMGR_STAT_L4WD0RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_L4WD1RST_LSB   14

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_MSB   14

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_SET_MSK   0x00004000

The mask used to set the ALT_RSTMGR_STAT_L4WD1RST register field value.

#define ALT_RSTMGR_STAT_L4WD1RST_CLR_MSK   0xffffbfff

The mask used to clear the ALT_RSTMGR_STAT_L4WD1RST register field value.

#define ALT_RSTMGR_STAT_L4WD1RST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_L4WD1RST register field.

#define ALT_RSTMGR_STAT_L4WD1RST_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_RSTMGR_STAT_L4WD1RST field value from a register.

#define ALT_RSTMGR_STAT_L4WD1RST_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_RSTMGR_STAT_L4WD1RST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_FPGADBGRST_LSB   16

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_MSB   16

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_SET_MSK   0x00010000

The mask used to set the ALT_RSTMGR_STAT_FPGADBGRST register field value.

#define ALT_RSTMGR_STAT_FPGADBGRST_CLR_MSK   0xfffeffff

The mask used to clear the ALT_RSTMGR_STAT_FPGADBGRST register field value.

#define ALT_RSTMGR_STAT_FPGADBGRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_FPGADBGRST register field.

#define ALT_RSTMGR_STAT_FPGADBGRST_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_RSTMGR_STAT_FPGADBGRST field value from a register.

#define ALT_RSTMGR_STAT_FPGADBGRST_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_RSTMGR_STAT_FPGADBGRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_CDBGREQRST_LSB   17

The Least Significant Bit (LSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_MSB   17

The Most Significant Bit (MSB) position of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_WIDTH   1

The width in bits of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_SET_MSK   0x00020000

The mask used to set the ALT_RSTMGR_STAT_CDBGREQRST register field value.

#define ALT_RSTMGR_STAT_CDBGREQRST_CLR_MSK   0xfffdffff

The mask used to clear the ALT_RSTMGR_STAT_CDBGREQRST register field value.

#define ALT_RSTMGR_STAT_CDBGREQRST_RESET   0x0

The reset value of the ALT_RSTMGR_STAT_CDBGREQRST register field.

#define ALT_RSTMGR_STAT_CDBGREQRST_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_RSTMGR_STAT_CDBGREQRST field value from a register.

#define ALT_RSTMGR_STAT_CDBGREQRST_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_RSTMGR_STAT_CDBGREQRST register field value suitable for setting the register.

#define ALT_RSTMGR_STAT_RESET   0x00000000

The reset value of the ALT_RSTMGR_STAT register.

#define ALT_RSTMGR_STAT_OFST   0x0

The byte offset of the ALT_RSTMGR_STAT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_STAT.