Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gmacgrp_mac_configuration

Description

Register 0 (MAC Configuration Register)

The MAC Configuration register establishes receive and transmit operating modes.

Register Layout

Bits Access Reset Description
[1:0] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_PRELEN
[2] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_RE
[3] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_TE
[4] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_DC
[6:5] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_BL
[7] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_ACS
[8] R 0x0 ALT_EMAC_GMAC_MAC_CFG_LUD
[9] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_DR
[10] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_IPC
[11] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_DM
[12] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_LM
[13] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_DO
[14] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_FES
[15] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_PS
[16] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_DCRS
[19:17] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_IFG
[20] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_JE
[21] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_BE
[22] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_JD
[23] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_WD
[24] R 0x0 ALT_EMAC_GMAC_MAC_CFG_TC
[25] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_CST
[26] R 0x0 ALT_EMAC_GMAC_MAC_CFG_SFTERR
[27] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_TWOKPE
[30:28] RW 0x0 ALT_EMAC_GMAC_MAC_CFG_SARC
[31] R 0x0 ALT_EMAC_GMAC_MAC_CFG_RSVD_31

Field : prelen

Preamble Length for Transmit Frames

These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating in the full-duplex mode.

  • 2'b00: 7 bytes of preamble
  • 2'b01: 5 byte of preamble
  • 2'b10: 3 bytes of preamble
  • 2'b11: 1 byte of preamble

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES | 0x0 | ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES | 0x1 | ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES | 0x2 | ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM1BYTE | 0x3 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM1BYTE   0x3
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB   0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB   1
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH   2
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK   0x00000003
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK   0xfffffffc
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value)   (((value) << 0) & 0x00000003)
 

Field : re

Receiver Enable

When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_RE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB   2
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB   2
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : te

Transmitter Enable

When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_TE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB   3
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB   3
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value)   (((value) << 3) & 0x00000008)
 

Field : dc

Deferral Check

When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode.

If the MAC is configured for 1000 Mbps operation or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but it is prevented because of an active carrier sense signal (CRS) on GMII or MII.

The defer time is not cumulative. For example, if the transmitter defers for 10,000 bit times because the CRS signal is active and then the CRS signal becomes inactive, the transmitter transmits and collision happens. Because of collision, the transmitter needs to back off and then defer again after back off completion. In such a scenario, the deferral timer is reset to 0 and it is restarted.

When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB   4
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB   4
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value)   (((value) << 4) & 0x00000010)
 

Field : bl

Back-Off Limit

The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode and is reserved (RO) in the full-duplex-only configuration.

  • 00: k = min (n, 10)
  • 01: k = min (n, 8)
  • 10: k = min (n, 4)
  • 11: k = min (n, 1)

where n = retransmission attempt. The random integer r takes the value in the

range 0 <= r < kth power of 2

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 | 0x0 | ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 | 0x1 | ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 | 0x2 | ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 | 0x3 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1   0x3
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB   5
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB   6
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH   2
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK   0x00000060
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK   0xffffff9f
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value)   (((value) & 0x00000060) >> 5)
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value)   (((value) << 5) & 0x00000060)
 

Field : acs

Automatic Pad or CRC Stripping

When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field.

When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_ACS_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB   7
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB   7
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : lud

Link Up or Down

This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface:

  • 0: Link Down
  • 1: Link Up

This bit is reserved (RO with default value) and is enabled when the RGMII, SGMII, or SMII interface is enabled during core configuration.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_LUD_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB   8
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB   8
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value)   (((value) << 8) & 0x00000100)
 

Field : dr

Disable Retry

When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status.

When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex mode and is reserved (RO with default value) in the full-duplex-only configuration.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_DR_E_END | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB   9
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB   9
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value)   (((value) << 9) & 0x00000200)
 

Field : ipc

Checksum Offload

When this bit is set, the MAC calculates the 16-bit one's complement of the one's complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected).

When this bit is reset, this function is disabled.

When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits are always cleared.

If the IP Checksum Offload feature is not enabled during core configuration, this bit is reserved (RO with default value).

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_IPC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB   10
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB   10
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value)   (((value) << 10) & 0x00000400)
 

Field : dm

Duplex Mode

When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configuration.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB   11
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB   11
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value)   (((value) << 11) & 0x00000800)
 

Field : lm

Loopback Mode

When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input (clk_rx_i) is required for the loopback to work properly, because the Transmit clock is not looped-back internally.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_LM_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB   12
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB   12
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value)   (((value) << 12) & 0x00001000)
 

Field : do

Disable Receive Own

When this bit is set, the MAC disables the reception of frames when the phy_txen_o is asserted in the half-duplex mode.

When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.

This bit is not applicable if the MAC is operating in the full-duplex mode. This bit is reserved (RO with default value) if the MAC is configured for the full- duplex-only operation.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_DO_E_END | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB   13
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB   13
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value)   (((value) << 13) & 0x00002000)
 

Field : fes

Speed

This bit selects the speed in the MII, RMII, SMII, RGMII, SGMII, or RevMII interface

  • 0: 10 Mbps
  • 1: 100 Mbps

This bit is reserved (RO) by default and is enabled only when the parameter SPEED_SELECT = Enabled. This bit generates link speed encoding when Bit 24 (TC) is set in the RGMII, SMII, or SGMII mode. This bit is always enabled for RGMII, SGMII, SMII, or RevMII interface.

In configurations with RGMII, SGMII, SMII, or RevMII interface, this bit is driven as an output signal (mac_speed_o[0]) to reflect the value of this bit in the mac_speed_o signal. In configurations with RMII, MII, or GMII interface, you can optionally drive this bit as an output signal (mac_speed_o[0]) to reflect its value in the mac_speed_o signal.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 | 0x0 | ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB   14
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB   14
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK   0x00004000
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value)   (((value) << 14) & 0x00004000)
 

Field : ps

Port Select

This bit selects the Ethernet line speed:

  • 0: For 1000 Mbps operations
  • 1: For 10 or 100 Mbps operations

In 10 or 100 Mbps operations, this bit, along with FES bit, selects the exact line speed. In the 10 or 100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations, this bit is read-only with the appropriate value. In default 10, 100, or 1000 Mbps configuration, this bit is R_W. The mac_portselect_o signal reflects the value of this bit.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL | 0x0 | ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB   15
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB   15
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK   0x00008000
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value)   (((value) << 15) & 0x00008000)
 

Field : dcrs

Disable Carrier Sense During Transmission

When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.

This bit is reserved (and RO) in the full-duplex-only configurations.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB   16
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB   16
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value)   (((value) << 16) & 0x00010000)
 

Field : ifg

Inter-Frame Gap

These bits control the minimum IFG between frames during transmission.

  • 000: 96 bit times
  • 001: 88 bit times
  • 010: 80 bit times
  • ...
  • 111: 40 bit times

In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 64 bit times (and above) in the GMAC-CORE configuration and 80 bit times (and above) in other configurations.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES | 0x0 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES | 0x1 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES | 0x2 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES | 0x3 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES | 0x4 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES | 0x5 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES | 0x6 | ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES | 0x7 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES   0x3
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES   0x4
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES   0x5
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES   0x6
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES   0x7
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB   17
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB   19
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH   3
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK   0x000e0000
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK   0xfff1ffff
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : je

Jumbo Frame Enable

When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_JE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB   20
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB   20
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value)   (((value) << 20) & 0x00100000)
 

Field : be

Frame Burst Enable

When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode. This bit is reserved (and RO) in the 10/100 Mbps only or full-duplex-only configurations.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_BE_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB   21
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB   21
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value)   (((value) << 21) & 0x00200000)
 

Field : jd

Jabber Disable

When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,384 bytes.

When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_JD_E_END | 0x0 | ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB   22
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB   22
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK   0x00400000
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value)   (((value) << 22) & 0x00400000)
 

Field : wd

Watchdog Disable

When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,384 bytes.

When this bit is reset, the MAC does not allow a receive frame which more than 2,048 bytes (10,240 if JE is set high) or the value programmed in Register 55 (Watchdog Timeout Register).

The MAC cuts off any bytes received after the watchdog limit number of bytes.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_WD_E_END | 0x0 | ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB   23
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB   23
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK   0x00800000
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value)   (((value) << 23) & 0x00800000)
 

Field : tc

Transmit Configuration in RGMII, SGMII, or SMII

When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or SGMII port. When this bit is reset, no such information is driven to the PHY. This bit is reserved (and RO) if the RGMII, SMII, or SGMII PHY port is not selected during core configuration.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_TC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB   24
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB   24
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value)   (((value) << 24) & 0x01000000)
 

Field : cst

CRC Stripping for Type Frames

When this bit is set, the last 4 bytes (FCS) of all frames of Ether type (Length/Type field greater than or equal to 1,536) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver. This function is valid when Type 2 Checksum Offload Engine is enabled.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD | 0x0 | ALT_EMAC_GMAC_MAC_CFG_CST_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB   25
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB   25
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value)   (((value) << 25) & 0x02000000)
 

Field : sfterr

SMII Force Transmit Error

When set, this bit indicates to the PHY to force a transmit error in the SMII frame being transmitted. This bit is reserved if the SMII PHY port is not selected during core configuration.

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_LSB   26
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_MSB   26
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET_MSK   0x04000000
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_CLR_MSK   0xfbffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET(value)   (((value) << 26) & 0x04000000)
 

Field : twokpe

IEEE 802.3as Support for 2K Packets

When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets.

When Bit 20 (JE) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames. When this bit is reset and Bit 20 (JE) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames. When Bit 20 is set, setting this bit has no effect on Giant Frame status.

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB   27
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB   27
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK   0x08000000
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK   0xf7ffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value)   (((value) << 27) & 0x08000000)
 

Field : sarc

Source Address Insertion or Replacement Control

This field controls the source address insertion or replacement for all transmitted frames. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement based on the values of Bits [29:28]:

  • 2'b0x: The input signals mti_sa_ctrl_i and ati_sa_ctrl_i control the SA field generation.
  • 2'b10:

    • If Bit 30 is set to 0, the MAC inserts the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames.
    • If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC inserts the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames.
  • 2'b11:

    • If Bit 30 is set to 0, the MAC replaces the content of the MAC Address 0 registers (registers 16 and 17) in the SA field of all transmitted frames.
    • If Bit 30 is set to 1 and the Enable MAC Address Register 1 option is selected during core configuration, the MAC replaces the content of the MAC Address 1 registers (registers 18 and 19) in the SA field of all transmitted frames.

Note:

- Changes to this field take effect only on the start of a frame. If you
  write this register field when a frame is being transmitted, only the
  subsequent frame can use the updated value, that is, the current frame
  does not use the updated value.

- These bits are reserved and RO when the Enable SA, VLAN, and CRC Insertion
  on TX feature is not selected during core configuration.

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_SARC_LSB   28
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_MSB   30
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_WIDTH   3
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_SET_MSK   0x70000000
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_CLR_MSK   0x8fffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_GET(value)   (((value) & 0x70000000) >> 28)
 
#define ALT_EMAC_GMAC_MAC_CFG_SARC_SET(value)   (((value) << 28) & 0x70000000)
 

Field : reserved_31

Reserved

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_LSB   31
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_MSB   31
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET_MSK   0x80000000
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_CLR_MSK   0x7fffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MAC_CFG_s
 

Macros

#define ALT_EMAC_GMAC_MAC_CFG_RESET   0x00000000
 
#define ALT_EMAC_GMAC_MAC_CFG_OFST   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MAC_CFG_s 
ALT_EMAC_GMAC_MAC_CFG_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MAC_CFG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MAC_CFG.

Data Fields
uint32_t prelen: 2 ALT_EMAC_GMAC_MAC_CFG_PRELEN
uint32_t re: 1 ALT_EMAC_GMAC_MAC_CFG_RE
uint32_t te: 1 ALT_EMAC_GMAC_MAC_CFG_TE
uint32_t dc: 1 ALT_EMAC_GMAC_MAC_CFG_DC
uint32_t bl: 2 ALT_EMAC_GMAC_MAC_CFG_BL
uint32_t acs: 1 ALT_EMAC_GMAC_MAC_CFG_ACS
const uint32_t lud: 1 ALT_EMAC_GMAC_MAC_CFG_LUD
uint32_t dr: 1 ALT_EMAC_GMAC_MAC_CFG_DR
uint32_t ipc: 1 ALT_EMAC_GMAC_MAC_CFG_IPC
uint32_t dm: 1 ALT_EMAC_GMAC_MAC_CFG_DM
uint32_t lm: 1 ALT_EMAC_GMAC_MAC_CFG_LM
uint32_t do_: 1 ALT_EMAC_GMAC_MAC_CFG_DO
uint32_t fes: 1 ALT_EMAC_GMAC_MAC_CFG_FES
uint32_t ps: 1 ALT_EMAC_GMAC_MAC_CFG_PS
uint32_t dcrs: 1 ALT_EMAC_GMAC_MAC_CFG_DCRS
uint32_t ifg: 3 ALT_EMAC_GMAC_MAC_CFG_IFG
uint32_t je: 1 ALT_EMAC_GMAC_MAC_CFG_JE
uint32_t be: 1 ALT_EMAC_GMAC_MAC_CFG_BE
uint32_t jd: 1 ALT_EMAC_GMAC_MAC_CFG_JD
uint32_t wd: 1 ALT_EMAC_GMAC_MAC_CFG_WD
const uint32_t tc: 1 ALT_EMAC_GMAC_MAC_CFG_TC
uint32_t cst: 1 ALT_EMAC_GMAC_MAC_CFG_CST
const uint32_t sfterr: 1 ALT_EMAC_GMAC_MAC_CFG_SFTERR
uint32_t twokpe: 1 ALT_EMAC_GMAC_MAC_CFG_TWOKPE
uint32_t sarc: 3 ALT_EMAC_GMAC_MAC_CFG_SARC
const uint32_t reserved_31: 1 ALT_EMAC_GMAC_MAC_CFG_RSVD_31

Macro Definitions

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM1BYTE   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK   0x00000003

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK   0xfffffffc

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE

#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_RE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE

#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TE_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC

#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DC_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK   0x00000060

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK   0xffffff9f

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_GET (   value)    (((value) & 0x00000060) >> 5)

Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_BL_SET (   value)    (((value) << 5) & 0x00000060)

Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS

#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD

#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR

#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DR_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC

#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM

#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DM_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM

#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_LM_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO

#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DO_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES

#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value.

#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value.

#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_FES_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS

#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_PS_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES   0x4

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES   0x5

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES   0x6

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES   0x7

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH   3

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK   0x000e0000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE

#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_JE_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE

#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_BE_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD

#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_JD_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD

#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_WD_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC

#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TC_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST

#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value.

#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value.

#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_CST_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_LSB   26

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_MSB   26

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET_MSK   0x04000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_CLR_MSK   0xfbffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_SFTERR register field.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_EMAC_GMAC_MAC_CFG_SFTERR field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_SFTERR_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_SFTERR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB   27

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB   27

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK   0x08000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_LSB   28

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_SARC register field.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_MSB   30

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_SARC register field.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_WIDTH   3

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_SARC register field.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_SET_MSK   0x70000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_SARC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_CLR_MSK   0x8fffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_SARC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_SARC register field.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_GET (   value)    (((value) & 0x70000000) >> 28)

Extracts the ALT_EMAC_GMAC_MAC_CFG_SARC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_SARC_SET (   value)    (((value) << 28) & 0x70000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_SARC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_LSB   31

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET_MSK   0x80000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_CLR_MSK   0x7fffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_EMAC_GMAC_MAC_CFG_RSVD_31 field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_RSVD_31_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_RSVD_31 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_RESET   0x00000000

The reset value of the ALT_EMAC_GMAC_MAC_CFG register.

#define ALT_EMAC_GMAC_MAC_CFG_OFST   0x0

The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component.

#define ALT_EMAC_GMAC_MAC_CFG_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))

The address of the ALT_EMAC_GMAC_MAC_CFG register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG.