Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 OSC1 Peripherals Security - l4osc1

Description

Controls security settings for L4 OSC1 peripherals.

Register Layout

Bits Access Reset Description
[0] W 0x0 L4 Watchdog Timer 0 Security
[1] W 0x0 L4 Watchdog Timer 0 Security
[2] W 0x0 Clock Manager Security
[3] W 0x0 Reset Manager Security
[4] W 0x0 System Manager Security
[5] W 0x0 OSC1 Timer 0 Security
[6] W 0x0 OSC1 Timer 1 Security
[31:7] ??? 0x0 UNDEFINED

Field : L4 Watchdog Timer 0 Security - l4wd0

Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_L4WD0_LSB   0
 
#define ALT_L3_SEC_L4OSC1_L4WD0_MSB   0
 
#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK   0x00000001
 
#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK   0xfffffffe
 
#define ALT_L3_SEC_L4OSC1_L4WD0_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_L4WD0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L3_SEC_L4OSC1_L4WD0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : L4 Watchdog Timer 0 Security - l4wd1

Controls whether secure or non-secure masters can access the L4 Watchdog Timer 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_L4WD1_LSB   1
 
#define ALT_L3_SEC_L4OSC1_L4WD1_MSB   1
 
#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK   0x00000002
 
#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK   0xfffffffd
 
#define ALT_L3_SEC_L4OSC1_L4WD1_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_L4WD1_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L3_SEC_L4OSC1_L4WD1_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Clock Manager Security - clkmgr

Controls whether secure or non-secure masters can access the Clock Manager slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB   2
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB   2
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK   0x00000004
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK   0xfffffffb
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_L3_SEC_L4OSC1_CLKMGR_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Reset Manager Security - rstmgr

Controls whether secure or non-secure masters can access the Reset Manager slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB   3
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB   3
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK   0x00000008
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK   0xfffffff7
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_L3_SEC_L4OSC1_RSTMGR_SET(value)   (((value) << 3) & 0x00000008)
 

Field : System Manager Security - sysmgr

Controls whether secure or non-secure masters can access the System Manager slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB   4
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB   4
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK   0x00000010
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK   0xffffffef
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_L3_SEC_L4OSC1_SYSMGR_SET(value)   (((value) << 4) & 0x00000010)
 

Field : OSC1 Timer 0 Security - osc1timer0

Controls whether secure or non-secure masters can access the OSC1 Timer 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB   5
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB   5
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK   0x00000020
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK   0xffffffdf
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET(value)   (((value) << 5) & 0x00000020)
 

Field : OSC1 Timer 1 Security - osc1timer1

Controls whether secure or non-secure masters can access the OSC1 Timer 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB   6
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB   6
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH   1
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK   0x00000040
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK   0xffffffbf
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET   0x0
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET(value)   (((value) << 6) & 0x00000040)
 

Data Structures

struct  ALT_L3_SEC_L4OSC1_s
 

Macros

#define ALT_L3_SEC_L4OSC1_OFST   0xc
 

Typedefs

typedef struct ALT_L3_SEC_L4OSC1_s ALT_L3_SEC_L4OSC1_t
 

Data Structure Documentation

struct ALT_L3_SEC_L4OSC1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L3_SEC_L4OSC1.

Data Fields
uint32_t l4wd0: 1 L4 Watchdog Timer 0 Security
uint32_t l4wd1: 1 L4 Watchdog Timer 0 Security
uint32_t clkmgr: 1 Clock Manager Security
uint32_t rstmgr: 1 Reset Manager Security
uint32_t sysmgr: 1 System Manager Security
uint32_t osc1timer0: 1 OSC1 Timer 0 Security
uint32_t osc1timer1: 1 OSC1 Timer 1 Security
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_L3_SEC_L4OSC1_L4WD0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_L4WD0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_L4WD0_LSB   0

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field.

#define ALT_L3_SEC_L4OSC1_L4WD0_MSB   0

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD0 register field.

#define ALT_L3_SEC_L4OSC1_L4WD0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_L4WD0 register field.

#define ALT_L3_SEC_L4OSC1_L4WD0_SET_MSK   0x00000001

The mask used to set the ALT_L3_SEC_L4OSC1_L4WD0 register field value.

#define ALT_L3_SEC_L4OSC1_L4WD0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD0 register field value.

#define ALT_L3_SEC_L4OSC1_L4WD0_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_L4WD0 register field.

#define ALT_L3_SEC_L4OSC1_L4WD0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L3_SEC_L4OSC1_L4WD0 field value from a register.

#define ALT_L3_SEC_L4OSC1_L4WD0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L3_SEC_L4OSC1_L4WD0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_L4WD1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_L4WD1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_L4WD1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_L4WD1_LSB   1

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field.

#define ALT_L3_SEC_L4OSC1_L4WD1_MSB   1

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_L4WD1 register field.

#define ALT_L3_SEC_L4OSC1_L4WD1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_L4WD1 register field.

#define ALT_L3_SEC_L4OSC1_L4WD1_SET_MSK   0x00000002

The mask used to set the ALT_L3_SEC_L4OSC1_L4WD1 register field value.

#define ALT_L3_SEC_L4OSC1_L4WD1_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L3_SEC_L4OSC1_L4WD1 register field value.

#define ALT_L3_SEC_L4OSC1_L4WD1_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_L4WD1 register field.

#define ALT_L3_SEC_L4OSC1_L4WD1_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L3_SEC_L4OSC1_L4WD1 field value from a register.

#define ALT_L3_SEC_L4OSC1_L4WD1_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L3_SEC_L4OSC1_L4WD1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_CLKMGR_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_CLKMGR_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_CLKMGR

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_CLKMGR_LSB   2

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field.

#define ALT_L3_SEC_L4OSC1_CLKMGR_MSB   2

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_CLKMGR register field.

#define ALT_L3_SEC_L4OSC1_CLKMGR_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_CLKMGR register field.

#define ALT_L3_SEC_L4OSC1_CLKMGR_SET_MSK   0x00000004

The mask used to set the ALT_L3_SEC_L4OSC1_CLKMGR register field value.

#define ALT_L3_SEC_L4OSC1_CLKMGR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_L3_SEC_L4OSC1_CLKMGR register field value.

#define ALT_L3_SEC_L4OSC1_CLKMGR_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_CLKMGR register field.

#define ALT_L3_SEC_L4OSC1_CLKMGR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_L3_SEC_L4OSC1_CLKMGR field value from a register.

#define ALT_L3_SEC_L4OSC1_CLKMGR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_L3_SEC_L4OSC1_CLKMGR register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_RSTMGR_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_RSTMGR_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_RSTMGR

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_RSTMGR_LSB   3

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field.

#define ALT_L3_SEC_L4OSC1_RSTMGR_MSB   3

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_RSTMGR register field.

#define ALT_L3_SEC_L4OSC1_RSTMGR_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_RSTMGR register field.

#define ALT_L3_SEC_L4OSC1_RSTMGR_SET_MSK   0x00000008

The mask used to set the ALT_L3_SEC_L4OSC1_RSTMGR register field value.

#define ALT_L3_SEC_L4OSC1_RSTMGR_CLR_MSK   0xfffffff7

The mask used to clear the ALT_L3_SEC_L4OSC1_RSTMGR register field value.

#define ALT_L3_SEC_L4OSC1_RSTMGR_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_RSTMGR register field.

#define ALT_L3_SEC_L4OSC1_RSTMGR_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_L3_SEC_L4OSC1_RSTMGR field value from a register.

#define ALT_L3_SEC_L4OSC1_RSTMGR_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_L3_SEC_L4OSC1_RSTMGR register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_SYSMGR_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_SYSMGR_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_SYSMGR

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_SYSMGR_LSB   4

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field.

#define ALT_L3_SEC_L4OSC1_SYSMGR_MSB   4

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_SYSMGR register field.

#define ALT_L3_SEC_L4OSC1_SYSMGR_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_SYSMGR register field.

#define ALT_L3_SEC_L4OSC1_SYSMGR_SET_MSK   0x00000010

The mask used to set the ALT_L3_SEC_L4OSC1_SYSMGR register field value.

#define ALT_L3_SEC_L4OSC1_SYSMGR_CLR_MSK   0xffffffef

The mask used to clear the ALT_L3_SEC_L4OSC1_SYSMGR register field value.

#define ALT_L3_SEC_L4OSC1_SYSMGR_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_SYSMGR register field.

#define ALT_L3_SEC_L4OSC1_SYSMGR_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_L3_SEC_L4OSC1_SYSMGR field value from a register.

#define ALT_L3_SEC_L4OSC1_SYSMGR_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_L3_SEC_L4OSC1_SYSMGR register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_LSB   5

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_MSB   5

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET_MSK   0x00000020

The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_CLR_MSK   0xffffffdf

The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR0 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR0 field value from a register.

#define ALT_L3_SEC_L4OSC1_OSC1TMR0_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_L3_SEC_L4OSC1_OSC1TMR0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4OSC1_OSC1TMR1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_LSB   6

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_MSB   6

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET_MSK   0x00000040

The mask used to set the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_CLR_MSK   0xffffffbf

The mask used to clear the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_RESET   0x0

The reset value of the ALT_L3_SEC_L4OSC1_OSC1TMR1 register field.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_L3_SEC_L4OSC1_OSC1TMR1 field value from a register.

#define ALT_L3_SEC_L4OSC1_OSC1TMR1_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_L3_SEC_L4OSC1_OSC1TMR1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4OSC1_OFST   0xc

The byte offset of the ALT_L3_SEC_L4OSC1 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_L3_SEC_L4OSC1.