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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Timing parameter between re high to re low (Trhz) for the next bank
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x32 | ALT_NAND_CFG_RE_2_RE_VALUE |
[31:6] | ??? | Unknown | UNDEFINED |
Field : value | |
Signifies the number of bus interface clk_x clocks that should be introduced between read enable going high to a bank to the read enable going low to the next bank. The number of clocks is the function of device parameter Trhz and controller clock frequency. Field Access Macros: | |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0 |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5 |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6 |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0 |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32 |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_NAND_CFG_RE_2_RE_VALUE_SET(value) (((value) << 0) & 0x0000003f) |
Data Structures | |
struct | ALT_NAND_CFG_RE_2_RE_s |
Macros | |
#define | ALT_NAND_CFG_RE_2_RE_RESET 0x00000032 |
#define | ALT_NAND_CFG_RE_2_RE_OFST 0x290 |
Typedefs | |
typedef struct ALT_NAND_CFG_RE_2_RE_s | ALT_NAND_CFG_RE_2_RE_t |
struct ALT_NAND_CFG_RE_2_RE_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_RE_2_RE.
Data Fields | ||
---|---|---|
uint32_t | value: 6 | ALT_NAND_CFG_RE_2_RE_VALUE |
uint32_t | __pad0__: 26 | UNDEFINED |
#define ALT_NAND_CFG_RE_2_RE_VALUE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field.
#define ALT_NAND_CFG_RE_2_RE_VALUE_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RE_2_RE_VALUE register field.
#define ALT_NAND_CFG_RE_2_RE_VALUE_WIDTH 6 |
The width in bits of the ALT_NAND_CFG_RE_2_RE_VALUE register field.
#define ALT_NAND_CFG_RE_2_RE_VALUE_SET_MSK 0x0000003f |
The mask used to set the ALT_NAND_CFG_RE_2_RE_VALUE register field value.
#define ALT_NAND_CFG_RE_2_RE_VALUE_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_NAND_CFG_RE_2_RE_VALUE register field value.
#define ALT_NAND_CFG_RE_2_RE_VALUE_RESET 0x32 |
The reset value of the ALT_NAND_CFG_RE_2_RE_VALUE register field.
#define ALT_NAND_CFG_RE_2_RE_VALUE_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_NAND_CFG_RE_2_RE_VALUE field value from a register.
#define ALT_NAND_CFG_RE_2_RE_VALUE_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_NAND_CFG_RE_2_RE_VALUE register field value suitable for setting the register.
#define ALT_NAND_CFG_RE_2_RE_RESET 0x00000032 |
The reset value of the ALT_NAND_CFG_RE_2_RE register.
#define ALT_NAND_CFG_RE_2_RE_OFST 0x290 |
The byte offset of the ALT_NAND_CFG_RE_2_RE register from the beginning of the component.
typedef struct ALT_NAND_CFG_RE_2_RE_s ALT_NAND_CFG_RE_2_RE_t |
The typedef declaration for register ALT_NAND_CFG_RE_2_RE.