Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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alt_fpga_manager.h
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32 
33 /*
34  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_fpga_manager.h#1 $
35  */
36 
37 #ifndef __ALT_FPGA_MGR_H__
38 #define __ALT_FPGA_MGR_H__
39 
40 #include "hwlib.h"
41 #include "alt_dma.h"
42 #include <stdio.h>
43 
44 #ifdef __cplusplus
45 extern "C"
46 {
47 #endif /* __cplusplus */
48 
67 #ifndef ALT_FPGA_ENABLE_DMA_SUPPORT
68 #define ALT_FPGA_ENABLE_DMA_SUPPORT (0)
69 #endif
70 
78 ALT_STATUS_CODE alt_fpga_init(void);
79 
86 ALT_STATUS_CODE alt_fpga_uninit(void);
87 
108 ALT_STATUS_CODE alt_fpga_control_enable(void);
109 
118 ALT_STATUS_CODE alt_fpga_control_disable(void);
119 
128 bool alt_fpga_control_is_enabled(void);
129 
134 typedef enum ALT_FPGA_STATE_e
135 {
147 
155 
163 
170 
177 
183 
195 
197 
204 
210 {
216 
222 
228 
234 
240 
246 
252 
258 
268 
278 
288 
293 
295 
312 uint32_t alt_fpga_mon_status_get(void);
313 
329 ALT_STATUS_CODE alt_fgpa_reset_assert(void);
330 
345 ALT_STATUS_CODE alt_fgpa_reset_deassert(void);
346 
367 {
373 
379 
385 
391 
397 
403 
409 
415 
421 
427 
433 
439 
444 
446 
457 
478 ALT_STATUS_CODE alt_fpga_cfg_mode_set(ALT_FPGA_CFG_MODE_t cfg_mode);
479 
523 typedef int32_t (*alt_fpga_istream_t)(void* buf, size_t buf_len, void* user_data);
524 
564 ALT_STATUS_CODE alt_fpga_configure(const void* cfg_buf,
565  size_t cfg_buf_len);
566 
567 #if ALT_FPGA_ENABLE_DMA_SUPPORT
568 
603 ALT_STATUS_CODE alt_fpga_configure_dma(const void* cfg_buf,
604  size_t cfg_buf_len,
605  ALT_DMA_CHANNEL_t dma_channel);
606 
607 #endif
608 
643 ALT_STATUS_CODE alt_fpga_istream_configure(alt_fpga_istream_t cfg_stream,
644  void * user_data);
645 
646 #if ALT_FPGA_ENABLE_DMA_SUPPORT
647 
685 ALT_STATUS_CODE alt_fpga_istream_configure_dma(alt_fpga_istream_t cfg_stream,
686  void * user_data,
687  ALT_DMA_CHANNEL_t dma_channel);
688 
689 #endif
690 
751 ALT_STATUS_CODE alt_fpga_man_irq_disable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
752 
775 ALT_STATUS_CODE alt_fpga_man_irq_enable(ALT_FPGA_MON_STATUS_t mon_stat_mask);
776 
797 typedef enum ALT_FPGA_GPI_e
798 {
800  ALT_FPGA_GPI_0 = (int32_t)(1UL << 0),
801 
803  ALT_FPGA_GPI_1 = (int32_t)(1UL << 1),
804 
806  ALT_FPGA_GPI_2 = (int32_t)(1UL << 2),
807 
809  ALT_FPGA_GPI_3 = (int32_t)(1UL << 3),
810 
812  ALT_FPGA_GPI_4 = (int32_t)(1UL << 4),
813 
815  ALT_FPGA_GPI_5 = (int32_t)(1UL << 5),
816 
818  ALT_FPGA_GPI_6 = (int32_t)(1UL << 6),
819 
821  ALT_FPGA_GPI_7 = (int32_t)(1UL << 7),
822 
824  ALT_FPGA_GPI_8 = (int32_t)(1UL << 8),
825 
827  ALT_FPGA_GPI_9 = (int32_t)(1UL << 9),
828 
830  ALT_FPGA_GPI_10 = (int32_t)(1UL << 10),
831 
833  ALT_FPGA_GPI_11 = (int32_t)(1UL << 11),
834 
836  ALT_FPGA_GPI_12 = (int32_t)(1UL << 12),
837 
839  ALT_FPGA_GPI_13 = (int32_t)(1UL << 13),
840 
842  ALT_FPGA_GPI_14 = (int32_t)(1UL << 14),
843 
845  ALT_FPGA_GPI_15 = (int32_t)(1UL << 15),
846 
848  ALT_FPGA_GPI_16 = (int32_t)(1UL << 16),
849 
851  ALT_FPGA_GPI_17 = (int32_t)(1UL << 17),
852 
854  ALT_FPGA_GPI_18 = (int32_t)(1UL << 18),
855 
857  ALT_FPGA_GPI_19 = (int32_t)(1UL << 19),
858 
860  ALT_FPGA_GPI_20 = (int32_t)(1UL << 20),
861 
863  ALT_FPGA_GPI_21 = (int32_t)(1UL << 21),
864 
866  ALT_FPGA_GPI_22 = (int32_t)(1UL << 22),
867 
869  ALT_FPGA_GPI_23 = (int32_t)(1UL << 23),
870 
872  ALT_FPGA_GPI_24 = (int32_t)(1UL << 24),
873 
875  ALT_FPGA_GPI_25 = (int32_t)(1UL << 25),
876 
878  ALT_FPGA_GPI_26 = (int32_t)(1UL << 26),
879 
881  ALT_FPGA_GPI_27 = (int32_t)(1UL << 27),
882 
884  ALT_FPGA_GPI_28 = (int32_t)(1UL << 28),
885 
887  ALT_FPGA_GPI_29 = (int32_t)(1UL << 29),
888 
890  ALT_FPGA_GPI_30 = (int32_t)(1UL << 30),
891 
893  ALT_FPGA_GPI_31 = (int32_t)(1UL << 31)
894 
896 
914 uint32_t alt_fpga_gpi_read(uint32_t mask);
915 
920 typedef enum ALT_FPGA_GPO_e
921 {
923  ALT_FPGA_GPO_0 = (int32_t)(1UL << 0),
924 
926  ALT_FPGA_GPO_1 = (int32_t)(1UL << 1),
927 
929  ALT_FPGA_GPO_2 = (int32_t)(1UL << 2),
930 
932  ALT_FPGA_GPO_3 = (int32_t)(1UL << 3),
933 
935  ALT_FPGA_GPO_4 = (int32_t)(1UL << 4),
936 
938  ALT_FPGA_GPO_5 = (int32_t)(1UL << 5),
939 
941  ALT_FPGA_GPO_6 = (int32_t)(1UL << 6),
942 
944  ALT_FPGA_GPO_7 = (int32_t)(1UL << 7),
945 
947  ALT_FPGA_GPO_8 = (int32_t)(1UL << 8),
948 
950  ALT_FPGA_GPO_9 = (int32_t)(1UL << 9),
951 
953  ALT_FPGA_GPO_10 = (int32_t)(1UL << 10),
954 
956  ALT_FPGA_GPO_11 = (int32_t)(1UL << 11),
957 
959  ALT_FPGA_GPO_12 = (int32_t)(1UL << 12),
960 
962  ALT_FPGA_GPO_13 = (int32_t)(1UL << 13),
963 
965  ALT_FPGA_GPO_14 = (int32_t)(1UL << 14),
966 
968  ALT_FPGA_GPO_15 = (int32_t)(1UL << 15),
969 
971  ALT_FPGA_GPO_16 = (int32_t)(1UL << 16),
972 
974  ALT_FPGA_GPO_17 = (int32_t)(1UL << 17),
975 
977  ALT_FPGA_GPO_18 = (int32_t)(1UL << 18),
978 
980  ALT_FPGA_GPO_19 = (int32_t)(1UL << 19),
981 
983  ALT_FPGA_GPO_20 = (int32_t)(1UL << 20),
984 
986  ALT_FPGA_GPO_21 = (int32_t)(1UL << 21),
987 
989  ALT_FPGA_GPO_22 = (int32_t)(1UL << 22),
990 
992  ALT_FPGA_GPO_23 = (int32_t)(1UL << 23),
993 
995  ALT_FPGA_GPO_24 = (int32_t)(1UL << 24),
996 
998  ALT_FPGA_GPO_25 = (int32_t)(1UL << 25),
999 
1001  ALT_FPGA_GPO_26 = (int32_t)(1UL << 26),
1002 
1004  ALT_FPGA_GPO_27 = (int32_t)(1UL << 27),
1005 
1007  ALT_FPGA_GPO_28 = (int32_t)(1UL << 28),
1008 
1010  ALT_FPGA_GPO_29 = (int32_t)(1UL << 29),
1011 
1013  ALT_FPGA_GPO_30 = (int32_t)(1UL << 30),
1014 
1016  ALT_FPGA_GPO_31 = (int32_t)(1UL << 31)
1017 
1018 } ALT_FPGA_GPO_t;
1019 
1044 ALT_STATUS_CODE alt_fpga_gpo_write(uint32_t mask, uint32_t value);
1045 
1054 #ifdef __cplusplus
1055 }
1056 #endif /* __cplusplus */
1057 
1058 #endif /* __ALT_FPGA_MGR_H__ */