Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : EMAC L3 Master AxCACHE Register - emac_global

Description

Controls the L3 master ARCACHE and AWCACHE AXI signals.

These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation

All fields are reset by a cold or warm reset.

Register Layout

Bits Access Reset Description
[0] RW 0x0 PTP Clock Select
[31:1] ??? 0x0 UNDEFINED

Field : PTP Clock Select - ptp_clk_sel

Selects the source of the PTP reference clock between emac_ptp_clk from the Clock Manager or f2s_ptp_ref_clk from the FPGA Fabric.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK | 0x0 | ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK | 0x1 |

Field Access Macros:

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK   0x0
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK   0x1
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_LSB   0
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_MSB   0
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_WIDTH   1
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET_MSK   0x00000001
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_RESET   0x0
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET(value)   (((value) << 0) & 0x00000001)
 

Data Structures

struct  ALT_SYSMGR_EMAC_GLOB_s
 

Macros

#define ALT_SYSMGR_EMAC_GLOB_RESET   0x00000000
 
#define ALT_SYSMGR_EMAC_GLOB_OFST   0x40
 

Typedefs

typedef struct
ALT_SYSMGR_EMAC_GLOB_s 
ALT_SYSMGR_EMAC_GLOB_t
 

Data Structure Documentation

struct ALT_SYSMGR_EMAC_GLOB_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_EMAC_GLOB.

Data Fields
uint32_t ptp_clk_sel: 1 PTP Clock Select
uint32_t __pad0__: 31 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_EMAC_PTP_CLK   0x0

Enumerated value for register field ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_E_F2S_PTP_REF_CLK   0x1

Enumerated value for register field ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_WIDTH   1

The width in bits of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL field value from a register.

#define ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_EMAC_GLOB_PTP_CLK_SEL register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC_GLOB_RESET   0x00000000

The reset value of the ALT_SYSMGR_EMAC_GLOB register.

#define ALT_SYSMGR_EMAC_GLOB_OFST   0x40

The byte offset of the ALT_SYSMGR_EMAC_GLOB register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_EMAC_GLOB.