Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : onfi_timing_mode

Description

Asynchronous Timing modes supported by the connected ONFI device

Register Layout

Bits Access Reset Description
[5:0] R 0x0 ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE
[31:6] ??? Unknown UNDEFINED

Field : value

The values in the field should be interpreted as follows[list]

[*]Bit 0 - Supports Timing mode 0.

[*]Bit 1 - Supports Timing mode 1.

[*]Bit 2 - Supports Timing mode 2.

[*]Bit 3 - Supports Timing mode 3.

[*]Bit 4 - Supports Timing mode 4.

[*]Bit 5 - Supports Timing mode 5.[/list]

Field Access Macros:

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB   0
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB   5
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH   6
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK   0x0000003f
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK   0xffffffc0
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET   0x0
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET(value)   (((value) & 0x0000003f) >> 0)
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET(value)   (((value) << 0) & 0x0000003f)
 

Data Structures

struct  ALT_NAND_PARAM_ONFI_TIMING_MOD_s
 

Macros

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_RESET   0x00000000
 
#define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST   0xa0
 

Typedefs

typedef struct
ALT_NAND_PARAM_ONFI_TIMING_MOD_s 
ALT_NAND_PARAM_ONFI_TIMING_MOD_t
 

Data Structure Documentation

struct ALT_NAND_PARAM_ONFI_TIMING_MOD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_PARAM_ONFI_TIMING_MOD.

Data Fields
const uint32_t value: 6 ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE
uint32_t __pad0__: 26 UNDEFINED

Macro Definitions

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_MSB   5

The Most Significant Bit (MSB) position of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_WIDTH   6

The width in bits of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET_MSK   0x0000003f

The mask used to set the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_CLR_MSK   0xffffffc0

The mask used to clear the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_RESET   0x0

The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_GET (   value)    (((value) & 0x0000003f) >> 0)

Extracts the ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE field value from a register.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE_SET (   value)    (((value) << 0) & 0x0000003f)

Produces a ALT_NAND_PARAM_ONFI_TIMING_MOD_VALUE register field value suitable for setting the register.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_RESET   0x00000000

The reset value of the ALT_NAND_PARAM_ONFI_TIMING_MOD register.

#define ALT_NAND_PARAM_ONFI_TIMING_MOD_OFST   0xa0

The byte offset of the ALT_NAND_PARAM_ONFI_TIMING_MOD register from the beginning of the component.

Typedef Documentation