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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Instance i_io48_pin_mux_shared_3v_io_grp of component ALT_PINMUX_SHARED_3V_IO_GRP.
#define ALT_PINMUX_SHARED_3V_IO_Q1_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_1_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_1 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_2_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_2 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_3_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_3 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_4_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_4 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_5_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_5 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_6_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_6 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_7_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_7 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_8_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_8 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_9_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_9 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_10_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_10 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_11_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_11 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q1_12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q1_12_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q1_12 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_1_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_1 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_2_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_2 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_3_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_3 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_4_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_4 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_5_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_5 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_6_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_6 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_7_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_7 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_8_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_8 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_9_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_9 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_10_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_10 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_11_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_11 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q2_12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q2_12_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q2_12 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_1_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_1 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_2_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_2 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_3_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_3 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_4_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_4 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_5_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_5 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_6_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_6 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_7_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_7 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_8_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_8 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_9_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_9 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_10_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_10 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_11_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_11 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q3_12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q3_12_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q3_12 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_1_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_1_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_1 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_2_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_2_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_2 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_3_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_3_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_3 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_4_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_4_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_4 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_5_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_5_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_5 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_6_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_6_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_6 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_7_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_7_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_7 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_8_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_8_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_8 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_9_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_9_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_9 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_10_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_10_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_10 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_11_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_11_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_11 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_Q4_12_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + ALT_PINMUX_SHARED_3V_IO_Q4_12_OFST)) |
The address of the ALT_PINMUX_SHARED_3V_IO_Q4_12 register for the ALT_PINMUX_SHARED_3V_IO_GRP instance.
#define ALT_PINMUX_SHARED_3V_IO_GRP_OFST 0xffd07000 |
The base address byte offset for the start of the ALT_PINMUX_SHARED_3V_IO_GRP component.
#define ALT_PINMUX_SHARED_3V_IO_GRP_ADDR ALT_CAST(void *, (ALT_CAST(char *, ALT_HPS_ADDR) + ALT_PINMUX_SHARED_3V_IO_GRP_OFST)) |
The start address of the ALT_PINMUX_SHARED_3V_IO_GRP component.
#define ALT_PINMUX_SHARED_3V_IO_GRP_LB_ADDR ALT_PINMUX_SHARED_3V_IO_GRP_ADDR |
The lower bound address range of the ALT_PINMUX_SHARED_3V_IO_GRP component.
#define ALT_PINMUX_SHARED_3V_IO_GRP_UB_ADDR ALT_CAST(void *, ((ALT_CAST(char *, ALT_PINMUX_SHARED_3V_IO_GRP_ADDR) + 0x200) - 1)) |
The upper bound address range of the ALT_PINMUX_SHARED_3V_IO_GRP component.