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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This bits is used to test interrupt from ECC RAM to GIC
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_ECC_OTG0_ECC_INTTEST_TSERRA |
[7:1] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | ALT_ECC_OTG0_ECC_INTTEST_TDERRA |
[31:9] | ??? | 0x0 | UNDEFINED |
Field : TSERRA | |
Test PORTA Single-bit error. Field Access Macros: | |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_LSB 0 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_MSB 0 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_WIDTH 1 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_SET_MSK 0x00000001 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_RESET 0x0 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_ECC_OTG0_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001) |
Field : TDERRA | |
Test PORTA Double-bit error. Field Access Macros: | |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_LSB 8 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_MSB 8 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_WIDTH 1 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_SET_MSK 0x00000100 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_RESET 0x0 |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_ECC_OTG0_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100) |
Data Structures | |
struct | ALT_ECC_OTG0_ECC_INTTEST_s |
Macros | |
#define | ALT_ECC_OTG0_ECC_INTTEST_RESET 0x00000000 |
#define | ALT_ECC_OTG0_ECC_INTTEST_OFST 0x24 |
Typedefs | |
typedef struct ALT_ECC_OTG0_ECC_INTTEST_s | ALT_ECC_OTG0_ECC_INTTEST_t |
struct ALT_ECC_OTG0_ECC_INTTEST_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_ECC_OTG0_ECC_INTTEST.
Data Fields | ||
---|---|---|
uint32_t | TSERRA: 1 | ALT_ECC_OTG0_ECC_INTTEST_TSERRA |
uint32_t | __pad0__: 7 | UNDEFINED |
uint32_t | TDERRA: 1 | ALT_ECC_OTG0_ECC_INTTEST_TDERRA |
uint32_t | __pad1__: 23 | UNDEFINED |
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_WIDTH 1 |
The width in bits of the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_SET_MSK 0x00000001 |
The mask used to set the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field value.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field value.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_RESET 0x0 |
The reset value of the ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_ECC_OTG0_ECC_INTTEST_TSERRA field value from a register.
#define ALT_ECC_OTG0_ECC_INTTEST_TSERRA_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_ECC_OTG0_ECC_INTTEST_TSERRA register field value suitable for setting the register.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_WIDTH 1 |
The width in bits of the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_SET_MSK 0x00000100 |
The mask used to set the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field value.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field value.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_RESET 0x0 |
The reset value of the ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_ECC_OTG0_ECC_INTTEST_TDERRA field value from a register.
#define ALT_ECC_OTG0_ECC_INTTEST_TDERRA_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_ECC_OTG0_ECC_INTTEST_TDERRA register field value suitable for setting the register.
#define ALT_ECC_OTG0_ECC_INTTEST_RESET 0x00000000 |
The reset value of the ALT_ECC_OTG0_ECC_INTTEST register.
#define ALT_ECC_OTG0_ECC_INTTEST_OFST 0x24 |
The byte offset of the ALT_ECC_OTG0_ECC_INTTEST register from the beginning of the component.
typedef struct ALT_ECC_OTG0_ECC_INTTEST_s ALT_ECC_OTG0_ECC_INTTEST_t |
The typedef declaration for register ALT_ECC_OTG0_ECC_INTTEST.