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Register : por_reset_count

Description

The number of cycles the controller waits after reset to issue the first RESET command to the device.

Register Layout

Bits Access Reset Description
[15:0] RW 0x13b ALT_NAND_CFG_POR_RST_COUNT_VALUE
[31:16] ??? 0x0 UNDEFINED

Field : value

The controller waits for this number of cycles before issuing the first RESET command to the device. The number in this register is multiplied internally by 16 in the controller to form the final reset wait count.

Field Access Macros:

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB   0
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB   15
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH   16
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK   0x0000ffff
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK   0xffff0000
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET   0x13b
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET(value)   (((value) << 0) & 0x0000ffff)
 

Data Structures

struct  ALT_NAND_CFG_POR_RST_COUNT_s
 

Macros

#define ALT_NAND_CFG_POR_RST_COUNT_OFST   0x2a0
 

Typedefs

typedef struct
ALT_NAND_CFG_POR_RST_COUNT_s 
ALT_NAND_CFG_POR_RST_COUNT_t
 

Data Structure Documentation

struct ALT_NAND_CFG_POR_RST_COUNT_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_CFG_POR_RST_COUNT.

Data Fields
uint32_t value: 16 ALT_NAND_CFG_POR_RST_COUNT_VALUE
uint32_t __pad0__: 16 UNDEFINED

Macro Definitions

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_MSB   15

The Most Significant Bit (MSB) position of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_WIDTH   16

The width in bits of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET_MSK   0x0000ffff

The mask used to set the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_CLR_MSK   0xffff0000

The mask used to clear the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_RESET   0x13b

The reset value of the ALT_NAND_CFG_POR_RST_COUNT_VALUE register field.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_NAND_CFG_POR_RST_COUNT_VALUE field value from a register.

#define ALT_NAND_CFG_POR_RST_COUNT_VALUE_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_NAND_CFG_POR_RST_COUNT_VALUE register field value suitable for setting the register.

#define ALT_NAND_CFG_POR_RST_COUNT_OFST   0x2a0

The byte offset of the ALT_NAND_CFG_POR_RST_COUNT register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_CFG_POR_RST_COUNT.