Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 128 (MMC Receive Checksum Offload Interrupt Mask Register) - MMC_IPC_Receive_Interrupt_Mask

Description

This register maintains the mask for the interrupt generated from the receive IPC statistic

counters.

Register Layout

Bits Access Reset Description
[0] RW 0x0 MMC Receive IPV4 Good Frame Counter Interrupt Mask
[1] RW 0x0 MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
[2] RW 0x0 MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
[3] RW 0x0 MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
[4] RW 0x0 MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
[5] RW 0x0 MMC Receive IPV6 Good Frame Counter Interrupt Mask
[6] RW 0x0 MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
[7] RW 0x0 MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
[8] RW 0x0 MMC Receive UDP Good Frame Counter Interrupt Mask
[9] RW 0x0 MMC Receive UDP Error Frame Counter Interrupt Mask
[10] RW 0x0 MMC Receive TCP Good Frame Counter Interrupt Mask
[11] RW 0x0 MMC Receive TCP Error Frame Counter Interrupt Mask
[12] RW 0x0 MMC Receive ICMP Good Frame Counter Interrupt Mask
[13] RW 0x0 MMC Receive ICMP Error Frame Counter Interrupt Mask
[15:14] ??? 0x0 UNDEFINED
[16] RW 0x0 MMC Receive IPV4 Good Octet Counter Interrupt Mask
[17] RW 0x0 MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
[18] RW 0x0 MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
[19] RW 0x0 MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
[20] RW 0x0 MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
[21] RW 0x0 MMC Receive IPV6 Good Octet Counter Interrupt Mask
[22] RW 0x0 MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
[23] RW 0x0 MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
[24] RW 0x0 MMC Receive UDP Good Octet Counter Interrupt Mask
[25] RW 0x0 MMC Receive UDP Error Octet Counter Interrupt Mask
[26] RW 0x0 MMC Receive TCP Good Octet Counter Interrupt Mask
[27] RW 0x0 MMC Receive TCP Error Octet Counter Interrupt Mask
[28] RW 0x0 MMC Receive ICMP Good Octet Counter Interrupt Mask
[29] RW 0x0 MMC Receive ICMP Error Octet Counter Interrupt Mask
[31:30] ??? 0x0 UNDEFINED

Field : MMC Receive IPV4 Good Frame Counter Interrupt Mask - rxipv4gfim

Setting this bit masks the interrupt when the rxipv4_gd_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB   0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB   0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET(value)   (((value) << 0) & 0x00000001)
 

Field : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask - rxipv4herfim

Setting this bit masks the interrupt when the rxipv4_hdrerr_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET(value)   (((value) << 1) & 0x00000002)
 

Field : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask - rxipv4nopayfim

Setting this bit masks the interrupt when the rxipv4_nopay_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB   2
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB   2
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET(value)   (((value) << 2) & 0x00000004)
 

Field : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask - rxipv4fragfim

Setting this bit masks the interrupt when the rxipv4_frag_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB   3
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB   3
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET(value)   (((value) << 3) & 0x00000008)
 

Field : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask - rxipv4udsblfim

Setting this bit masks the interrupt when the rxipv4_udsbl_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB   4
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB   4
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET(value)   (((value) << 4) & 0x00000010)
 

Field : MMC Receive IPV6 Good Frame Counter Interrupt Mask - rxipv6gfim

Setting this bit masks the interrupt when the rxipv6_gd_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB   5
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB   5
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET(value)   (((value) << 5) & 0x00000020)
 

Field : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask - rxipv6herfim

Setting this bit masks the interrupt when the rxipv6_hdrerr_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB   6
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB   6
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK   0x00000040
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET(value)   (((value) << 6) & 0x00000040)
 

Field : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask - rxipv6nopayfim

Setting this bit masks the interrupt when the rxipv6_nopay_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB   7
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB   7
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET(value)   (((value) << 7) & 0x00000080)
 

Field : MMC Receive UDP Good Frame Counter Interrupt Mask - rxudpgfim

Setting this bit masks the interrupt when the rxudp_gd_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB   8
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB   8
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET(value)   (((value) << 8) & 0x00000100)
 

Field : MMC Receive UDP Error Frame Counter Interrupt Mask - rxudperfim

Setting this bit masks the interrupt when the rxudp_err_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB   9
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB   9
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET(value)   (((value) << 9) & 0x00000200)
 

Field : MMC Receive TCP Good Frame Counter Interrupt Mask - rxtcpgfim

Setting this bit masks the interrupt when the rxtcp_gd_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB   10
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB   10
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET(value)   (((value) << 10) & 0x00000400)
 

Field : MMC Receive TCP Error Frame Counter Interrupt Mask - rxtcperfim

Setting this bit masks the interrupt when the rxtcp_err_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB   11
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB   11
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET(value)   (((value) << 11) & 0x00000800)
 

Field : MMC Receive ICMP Good Frame Counter Interrupt Mask - rxicmpgfim

Setting this bit masks the interrupt when the rxicmp_gd_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB   12
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB   12
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET(value)   (((value) << 12) & 0x00001000)
 

Field : MMC Receive ICMP Error Frame Counter Interrupt Mask - rxicmperfim

Setting this bit masks the interrupt when the rxicmp_err_frms counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB   13
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB   13
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET(value)   (((value) << 13) & 0x00002000)
 

Field : MMC Receive IPV4 Good Octet Counter Interrupt Mask - rxipv4goim

Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB   16
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB   16
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET(value)   (((value) << 16) & 0x00010000)
 

Field : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask - rxipv4heroim

Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB   17
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB   17
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK   0x00020000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK   0xfffdffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET(value)   (((value) << 17) & 0x00020000)
 

Field : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask - rxipv4nopayoim

Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB   18
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB   18
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET(value)   (((value) << 18) & 0x00040000)
 

Field : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask - rxipv4fragoim

Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB   19
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB   19
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET(value)   (((value) << 19) & 0x00080000)
 

Field : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask - rxipv4udsbloim

Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB   20
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB   20
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET(value)   (((value) << 20) & 0x00100000)
 

Field : MMC Receive IPV6 Good Octet Counter Interrupt Mask - rxipv6goim

Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB   21
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB   21
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET(value)   (((value) << 21) & 0x00200000)
 

Field : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask - rxipv6heroim

Setting this bit masks interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB   22
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB   22
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK   0x00400000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET(value)   (((value) << 22) & 0x00400000)
 

Field : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask - rxipv6nopayoim

Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB   23
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB   23
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK   0x00800000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET(value)   (((value) << 23) & 0x00800000)
 

Field : MMC Receive UDP Good Octet Counter Interrupt Mask - rxudpgoim

Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB   24
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB   24
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET(value)   (((value) << 24) & 0x01000000)
 

Field : MMC Receive UDP Error Octet Counter Interrupt Mask - rxudperoim

Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB   25
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB   25
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET(value)   (((value) << 25) & 0x02000000)
 

Field : MMC Receive TCP Good Octet Counter Interrupt Mask - rxtcpgoim

Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB   26
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB   26
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK   0x04000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK   0xfbffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET(value)   (((value) << 26) & 0x04000000)
 

Field : MMC Receive TCP Error Octet Counter Interrupt Mask - rxtcperoim

Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB   27
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB   27
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK   0x08000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK   0xf7ffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET(value)   (((value) << 27) & 0x08000000)
 

Field : MMC Receive ICMP Good Octet Counter Interrupt Mask - rxicmpgoim

Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB   28
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB   28
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK   0x10000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK   0xefffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET(value)   (((value) & 0x10000000) >> 28)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET(value)   (((value) << 28) & 0x10000000)
 

Field : MMC Receive ICMP Error Octet Counter Interrupt Mask - rxicmperoim

Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR 0x0 counter < half max
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR 0x1 counter >= half max or max

Field Access Macros:

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR   0x1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB   29
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB   29
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH   1
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK   0x20000000
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK   0xdfffffff
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET   0x0
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET(value)   (((value) & 0x20000000) >> 29)
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET(value)   (((value) << 29) & 0x20000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s
 

Macros

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST   0x200
 
#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s 
ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK.

Data Fields
uint32_t rxipv4gfim: 1 MMC Receive IPV4 Good Frame Counter Interrupt Mask
uint32_t rxipv4herfim: 1 MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
uint32_t rxipv4nopayfim: 1 MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
uint32_t rxipv4fragfim: 1 MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
uint32_t rxipv4udsblfim: 1 MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
uint32_t rxipv6gfim: 1 MMC Receive IPV6 Good Frame Counter Interrupt Mask
uint32_t rxipv6herfim: 1 MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
uint32_t rxipv6nopayfim: 1 MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
uint32_t rxudpgfim: 1 MMC Receive UDP Good Frame Counter Interrupt Mask
uint32_t rxudperfim: 1 MMC Receive UDP Error Frame Counter Interrupt Mask
uint32_t rxtcpgfim: 1 MMC Receive TCP Good Frame Counter Interrupt Mask
uint32_t rxtcperfim: 1 MMC Receive TCP Error Frame Counter Interrupt Mask
uint32_t rxicmpgfim: 1 MMC Receive ICMP Good Frame Counter Interrupt Mask
uint32_t rxicmperfim: 1 MMC Receive ICMP Error Frame Counter Interrupt Mask
uint32_t __pad0__: 2 UNDEFINED
uint32_t rxipv4goim: 1 MMC Receive IPV4 Good Octet Counter Interrupt Mask
uint32_t rxipv4heroim: 1 MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
uint32_t rxipv4nopayoim: 1 MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
uint32_t rxipv4fragoim: 1 MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
uint32_t rxipv4udsbloim: 1 MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
uint32_t rxipv6goim: 1 MMC Receive IPV6 Good Octet Counter Interrupt Mask
uint32_t rxipv6heroim: 1 MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
uint32_t rxipv6nopayoim: 1 MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
uint32_t rxudpgoim: 1 MMC Receive UDP Good Octet Counter Interrupt Mask
uint32_t rxudperoim: 1 MMC Receive UDP Error Octet Counter Interrupt Mask
uint32_t rxtcpgoim: 1 MMC Receive TCP Good Octet Counter Interrupt Mask
uint32_t rxtcperoim: 1 MMC Receive TCP Error Octet Counter Interrupt Mask
uint32_t rxicmpgoim: 1 MMC Receive ICMP Good Octet Counter Interrupt Mask
uint32_t rxicmperoim: 1 MMC Receive ICMP Error Octet Counter Interrupt Mask
uint32_t __pad1__: 2 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPERFIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4GOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET_MSK   0x00020000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_CLR_MSK   0xfffdffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4HEROIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4NOPAYOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4FRAGOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV4UDSBLOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6GOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6HEROIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_IPV6NOPAYOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPGOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_UDPEROIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_LSB   26

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_MSB   26

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET_MSK   0x04000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_CLR_MSK   0xfbffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPGOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_LSB   27

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_MSB   27

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET_MSK   0x08000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_TCPEROIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_LSB   28

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_MSB   28

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET_MSK   0x10000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_CLR_MSK   0xefffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_GET (   value)    (((value) & 0x10000000) >> 28)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM_SET (   value)    (((value) << 28) & 0x10000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPGOIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_NOMSKINTR   0x0

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM

counter < half max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_E_MSKINTR   0x1

Enumerated value for register field ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM

counter >= half max or max

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_LSB   29

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_MSB   29

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET_MSK   0x20000000

The mask used to set the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_CLR_MSK   0xdfffffff

The mask used to clear the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_GET (   value)    (((value) & 0x20000000) >> 29)

Extracts the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM field value from a register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM_SET (   value)    (((value) << 29) & 0x20000000)

Produces a ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ICMPEROIM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST   0x200

The byte offset of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register from the beginning of the component.

#define ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK_OFST))

The address of the ALT_EMAC_GMAC_MMC_IPC_RX_INT_MSK register.

Typedef Documentation