Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : QSPI Configuration Register - cfg

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 QSPI Enable
[1] RW 0x0 Clock Polarity
[2] RW 0x0 Select Clock Phase
[6:3] ??? 0x0 UNDEFINED
[7] RW 0x0 Enable Direct Access Controller
[8] RW 0x0 Legacy IP Mode Enable
[9] RW 0x0 Peripheral select decode
[13:10] RW 0x0 Peripheral Chip Select Lines
[14] RW 0x0 Write Protect Flash Pin
[15] RW 0x0 Enable DMA Peripheral Interface
[16] RW 0x0 Enable AHB Address Re-mapping
[17] RW 0x0 Enter XIP Mode on next READ
[18] RW 0x0 Enter XIP Mode Immediately
[22:19] RW 0xf Master Mode Baud Rate Divisor
[30:23] ??? 0x0 UNDEFINED
[31] R 0x0 Serial interface and QSPI pipeline is IDLE

Field : QSPI Enable - en

If this bit is disabled, the QSPI will finish the current transfer of the data word (FF_W) and stop sending. When Enabled, and qspi_n_mo_en = 0, all output enables are inactive and all pins are set to input mode.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_EN_E_DIS 0x0 Disable the QSPI
ALT_QSPI_CFG_EN_E_EN 0x1 Enable the QSPI

Field Access Macros:

#define ALT_QSPI_CFG_EN_E_DIS   0x0
 
#define ALT_QSPI_CFG_EN_E_EN   0x1
 
#define ALT_QSPI_CFG_EN_LSB   0
 
#define ALT_QSPI_CFG_EN_MSB   0
 
#define ALT_QSPI_CFG_EN_WIDTH   1
 
#define ALT_QSPI_CFG_EN_SET_MSK   0x00000001
 
#define ALT_QSPI_CFG_EN_CLR_MSK   0xfffffffe
 
#define ALT_QSPI_CFG_EN_RESET   0x0
 
#define ALT_QSPI_CFG_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_QSPI_CFG_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Clock Polarity - selclkpol

Controls spiclk modes of operation.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_SELCLKPOL_E_LOW 0x1 SPI clock is quiescent low
ALT_QSPI_CFG_SELCLKPOL_E_HIGH 0x0 SPI clock is quiescent high

Field Access Macros:

#define ALT_QSPI_CFG_SELCLKPOL_E_LOW   0x1
 
#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH   0x0
 
#define ALT_QSPI_CFG_SELCLKPOL_LSB   1
 
#define ALT_QSPI_CFG_SELCLKPOL_MSB   1
 
#define ALT_QSPI_CFG_SELCLKPOL_WIDTH   1
 
#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK   0x00000002
 
#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK   0xfffffffd
 
#define ALT_QSPI_CFG_SELCLKPOL_RESET   0x0
 
#define ALT_QSPI_CFG_SELCLKPOL_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_QSPI_CFG_SELCLKPOL_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Select Clock Phase - selclkphase

Selects whether the clock is in an active or inactive phase outside the SPI word.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_SELCLKPHASE_E_ACT 0x0 SPI clock is quiescent low
ALT_QSPI_CFG_SELCLKPHASE_E_INACT 0x1 Clock Inactive

Field Access Macros:

#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT   0x0
 
#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT   0x1
 
#define ALT_QSPI_CFG_SELCLKPHASE_LSB   2
 
#define ALT_QSPI_CFG_SELCLKPHASE_MSB   2
 
#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH   1
 
#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK   0x00000004
 
#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK   0xfffffffb
 
#define ALT_QSPI_CFG_SELCLKPHASE_RESET   0x0
 
#define ALT_QSPI_CFG_SELCLKPHASE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_QSPI_CFG_SELCLKPHASE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Enable Direct Access Controller - endiracc

If disabled, the Direct Access Controller becomes inactive once the current transfer of the data word (FF_W) is complete. When the Direct Access Controller and Indirect Access Controller are both disabled, all AHB requests are completed with an error response.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENDIRACC_E_DIS 0x0 Disable Direct Access Ctrl
ALT_QSPI_CFG_ENDIRACC_E_EN 0x1 Enable Direct Access Ctrl

Field Access Macros:

#define ALT_QSPI_CFG_ENDIRACC_E_DIS   0x0
 
#define ALT_QSPI_CFG_ENDIRACC_E_EN   0x1
 
#define ALT_QSPI_CFG_ENDIRACC_LSB   7
 
#define ALT_QSPI_CFG_ENDIRACC_MSB   7
 
#define ALT_QSPI_CFG_ENDIRACC_WIDTH   1
 
#define ALT_QSPI_CFG_ENDIRACC_SET_MSK   0x00000080
 
#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK   0xffffff7f
 
#define ALT_QSPI_CFG_ENDIRACC_RESET   0x0
 
#define ALT_QSPI_CFG_ENDIRACC_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_QSPI_CFG_ENDIRACC_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Legacy IP Mode Enable - enlegacyip

This bit can select the Direct Access Controller/Indirect Access Controller or legacy mode.If legacy mode is selected, any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid AHB read will pop the internal RX-FIFO, retrieving data that was forwarded by the external FLASH device on the SPI lines, byte transfers of 4, 2 or 1 are permitted and controlled via the HSIZE input.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD 0x1 Legacy Mode
ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD 0x0 Use Direct/Indirect Access Controller

Field Access Macros:

#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD   0x1
 
#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD   0x0
 
#define ALT_QSPI_CFG_ENLEGACYIP_LSB   8
 
#define ALT_QSPI_CFG_ENLEGACYIP_MSB   8
 
#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH   1
 
#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK   0x00000100
 
#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK   0xfffffeff
 
#define ALT_QSPI_CFG_ENLEGACYIP_RESET   0x0
 
#define ALT_QSPI_CFG_ENLEGACYIP_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_QSPI_CFG_ENLEGACYIP_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Peripheral select decode - perseldec

Select between '1 of 4 selects' or 'external 4-to-16 decode'. The qspi_n_ss_out[3:0] output signals are controlled.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16 0x1 Select external 4-to-16 decode
ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4 0x0 Selects 1 of 4 qspi_n_ss_out[3:0]

Field Access Macros:

#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16   0x1
 
#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4   0x0
 
#define ALT_QSPI_CFG_PERSELDEC_LSB   9
 
#define ALT_QSPI_CFG_PERSELDEC_MSB   9
 
#define ALT_QSPI_CFG_PERSELDEC_WIDTH   1
 
#define ALT_QSPI_CFG_PERSELDEC_SET_MSK   0x00000200
 
#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK   0xfffffdff
 
#define ALT_QSPI_CFG_PERSELDEC_RESET   0x0
 
#define ALT_QSPI_CFG_PERSELDEC_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_QSPI_CFG_PERSELDEC_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Peripheral Chip Select Lines - percslines

Peripheral chip select line output decode type. As per perseldec, if perseldec = 0, the decode is select 1 of 4 decoding on signals, qspi_n_ss_out[3:0], The asserted decode line goes to 0. If perseldec = 1, the signals qspi_n_ss_out[3:0] require an external 4 to 16 decoder.

Field Access Macros:

#define ALT_QSPI_CFG_PERCSLINES_LSB   10
 
#define ALT_QSPI_CFG_PERCSLINES_MSB   13
 
#define ALT_QSPI_CFG_PERCSLINES_WIDTH   4
 
#define ALT_QSPI_CFG_PERCSLINES_SET_MSK   0x00003c00
 
#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK   0xffffc3ff
 
#define ALT_QSPI_CFG_PERCSLINES_RESET   0x0
 
#define ALT_QSPI_CFG_PERCSLINES_GET(value)   (((value) & 0x00003c00) >> 10)
 
#define ALT_QSPI_CFG_PERCSLINES_SET(value)   (((value) << 10) & 0x00003c00)
 

Field : Write Protect Flash Pin - wp

This bit controls the write protect pin of the flash devices. The signal qspi_mo2_wpn needs to be resynchronized to the generated memory clock as necessary.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_WP_E_WRPROTON 0x1 Enable Write Protect
ALT_QSPI_CFG_WP_E_WRTPROTOFF 0x0 Disable Write Protect

Field Access Macros:

#define ALT_QSPI_CFG_WP_E_WRPROTON   0x1
 
#define ALT_QSPI_CFG_WP_E_WRTPROTOFF   0x0
 
#define ALT_QSPI_CFG_WP_LSB   14
 
#define ALT_QSPI_CFG_WP_MSB   14
 
#define ALT_QSPI_CFG_WP_WIDTH   1
 
#define ALT_QSPI_CFG_WP_SET_MSK   0x00004000
 
#define ALT_QSPI_CFG_WP_CLR_MSK   0xffffbfff
 
#define ALT_QSPI_CFG_WP_RESET   0x0
 
#define ALT_QSPI_CFG_WP_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_QSPI_CFG_WP_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Enable DMA Peripheral Interface - endma

Allows DMA handshaking mode. When enabled the QSPI will trigger DMA transfer requests via the DMA peripheral interface.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENDMA_E_EN 0x1 Enable DMA Mode
ALT_QSPI_CFG_ENDMA_E_DIS 0x0 Disable DMA Mode

Field Access Macros:

#define ALT_QSPI_CFG_ENDMA_E_EN   0x1
 
#define ALT_QSPI_CFG_ENDMA_E_DIS   0x0
 
#define ALT_QSPI_CFG_ENDMA_LSB   15
 
#define ALT_QSPI_CFG_ENDMA_MSB   15
 
#define ALT_QSPI_CFG_ENDMA_WIDTH   1
 
#define ALT_QSPI_CFG_ENDMA_SET_MSK   0x00008000
 
#define ALT_QSPI_CFG_ENDMA_CLR_MSK   0xffff7fff
 
#define ALT_QSPI_CFG_ENDMA_RESET   0x0
 
#define ALT_QSPI_CFG_ENDMA_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_QSPI_CFG_ENDMA_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Enable AHB Address Re-mapping - enahbremap

(Direct Access Mode Only) When enabled, the incoming AHB address will be adapted and sent to the FLASH device as (address + N), where N is the value stored in the remap address register.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENAHBREMAP_E_EN 0x1 Enable AHB Re-mapping
ALT_QSPI_CFG_ENAHBREMAP_E_DIS 0x0 Disable AHB Re-mapping

Field Access Macros:

#define ALT_QSPI_CFG_ENAHBREMAP_E_EN   0x1
 
#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS   0x0
 
#define ALT_QSPI_CFG_ENAHBREMAP_LSB   16
 
#define ALT_QSPI_CFG_ENAHBREMAP_MSB   16
 
#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH   1
 
#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK   0x00010000
 
#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK   0xfffeffff
 
#define ALT_QSPI_CFG_ENAHBREMAP_RESET   0x0
 
#define ALT_QSPI_CFG_ENAHBREMAP_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_QSPI_CFG_ENAHBREMAP_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Enter XIP Mode on next READ - enterxipnextrd

If XIP is enabled, then setting to disabled will cause the controller to exit XIP mode on the next READ instruction. If XIP is disabled, then setting to enabled will inform the controller that the device is ready to enter XIP on the next READ instruction. The controller will therefore send the appropriate command sequence, including mode bits to cause the device to enter XIP mode. Use this register after the controller has ensured the FLASH device has been configured to be ready to enter XIP mode. Note : To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only AFTER the next READ instruction is executed. Software should therefore ensure that at least one READ instruction is requested after resetting this bit before it can be sure XIP mode in the device is exited.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN 0x1 Enter XIP Mode on next READ instruction
ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS 0x0 Exit XIP Mode on next READ instruction

Field Access Macros:

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN   0x1
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS   0x0
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB   17
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB   17
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH   1
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK   0x00020000
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK   0xfffdffff
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET   0x0
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET(value)   (((value) << 17) & 0x00020000)
 

Field : Enter XIP Mode Immediately - enterxipimm

If XIP is enabled, then setting to disabled will cause the controller to exit XIP mode on the next READ instruction. If XIP is disabled, then setting enable will operate the device in XIP mode immediately. Use this register when the external device wakes up in XIP mode (as per the contents of its non- volatile configuration register). The controller will assume the next READ instruction will be passed to the device as an XIP instruction, and therefore will not require the READ opcode to be transferred. Note: To exit XIP mode, this bit should be set to 0. This will take effect in the attached device only after the next READ instruction is executed. Software therefore should ensure that at least one READ instruction is requested after resetting this bit in order to be sure that XIP mode is exited.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_ENTERXIPIMM_E_EN 0x1 Enter XIP Mode immediately
ALT_QSPI_CFG_ENTERXIPIMM_E_DIS 0x0 Exit XIP Mode on next READ instruction

Field Access Macros:

#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN   0x1
 
#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS   0x0
 
#define ALT_QSPI_CFG_ENTERXIPIMM_LSB   18
 
#define ALT_QSPI_CFG_ENTERXIPIMM_MSB   18
 
#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH   1
 
#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK   0x00040000
 
#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK   0xfffbffff
 
#define ALT_QSPI_CFG_ENTERXIPIMM_RESET   0x0
 
#define ALT_QSPI_CFG_ENTERXIPIMM_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_QSPI_CFG_ENTERXIPIMM_SET(value)   (((value) << 18) & 0x00040000)
 

Field : Master Mode Baud Rate Divisor - bauddiv

SPI baud rate = ref_clk / (2 * baud_rate_divisor)

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_BAUDDIV_E_BAUD2 0x0 Baud Rate Div/2
ALT_QSPI_CFG_BAUDDIV_E_BAUD4 0x1 Baud Rate Div/4
ALT_QSPI_CFG_BAUDDIV_E_BAUD6 0x2 Baud Rate Div/6
ALT_QSPI_CFG_BAUDDIV_E_BAUD8 0x3 Baud Rate Div/8
ALT_QSPI_CFG_BAUDDIV_E_BAUD10 0x4 Baud Rate Div/10
ALT_QSPI_CFG_BAUDDIV_E_BAUD12 0x5 Baud Rate Div/12
ALT_QSPI_CFG_BAUDDIV_E_BAUD14 0x6 Baud Rate Div/14
ALT_QSPI_CFG_BAUDDIV_E_BAUD16 0x7 Baud Rate Div/16
ALT_QSPI_CFG_BAUDDIV_E_BAUD18 0x8 Baud Rate Div/18
ALT_QSPI_CFG_BAUDDIV_E_BAUD20 0x9 Baud Rate Div/20
ALT_QSPI_CFG_BAUDDIV_E_BAUD22 0xa Baud Rate Div/22
ALT_QSPI_CFG_BAUDDIV_E_BAUD24 0xb Baud Rate Div/24
ALT_QSPI_CFG_BAUDDIV_E_BAUD26 0xc Baud Rate Div/26
ALT_QSPI_CFG_BAUDDIV_E_BAUD28 0xd Baud Rate Div/28
ALT_QSPI_CFG_BAUDDIV_E_BAUD30 0xe Baud Rate Div/30
ALT_QSPI_CFG_BAUDDIV_E_BAUD32 0xf Baud Rate Div/32

Field Access Macros:

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2   0x0
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4   0x1
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6   0x2
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8   0x3
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10   0x4
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12   0x5
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14   0x6
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16   0x7
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18   0x8
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20   0x9
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22   0xa
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24   0xb
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26   0xc
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28   0xd
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30   0xe
 
#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32   0xf
 
#define ALT_QSPI_CFG_BAUDDIV_LSB   19
 
#define ALT_QSPI_CFG_BAUDDIV_MSB   22
 
#define ALT_QSPI_CFG_BAUDDIV_WIDTH   4
 
#define ALT_QSPI_CFG_BAUDDIV_SET_MSK   0x00780000
 
#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK   0xff87ffff
 
#define ALT_QSPI_CFG_BAUDDIV_RESET   0xf
 
#define ALT_QSPI_CFG_BAUDDIV_GET(value)   (((value) & 0x00780000) >> 19)
 
#define ALT_QSPI_CFG_BAUDDIV_SET(value)   (((value) << 19) & 0x00780000)
 

Field : Serial interface and QSPI pipeline is IDLE - idle

This is a STATUS read-only bit. Note this is a retimed signal, so there will be some inherent delay on the generation of this status signal.

Field Enumeration Values:

Enum Value Description
ALT_QSPI_CFG_IDLE_E_SET 0x1 Idle Mode
ALT_QSPI_CFG_IDLE_E_NOTSET 0x0 Non-Idle Mode

Field Access Macros:

#define ALT_QSPI_CFG_IDLE_E_SET   0x1
 
#define ALT_QSPI_CFG_IDLE_E_NOTSET   0x0
 
#define ALT_QSPI_CFG_IDLE_LSB   31
 
#define ALT_QSPI_CFG_IDLE_MSB   31
 
#define ALT_QSPI_CFG_IDLE_WIDTH   1
 
#define ALT_QSPI_CFG_IDLE_SET_MSK   0x80000000
 
#define ALT_QSPI_CFG_IDLE_CLR_MSK   0x7fffffff
 
#define ALT_QSPI_CFG_IDLE_RESET   0x0
 
#define ALT_QSPI_CFG_IDLE_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_QSPI_CFG_IDLE_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_QSPI_CFG_s
 

Macros

#define ALT_QSPI_CFG_OFST   0x0
 

Typedefs

typedef struct ALT_QSPI_CFG_s ALT_QSPI_CFG_t
 

Data Structure Documentation

struct ALT_QSPI_CFG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_QSPI_CFG.

Data Fields
uint32_t en: 1 QSPI Enable
uint32_t selclkpol: 1 Clock Polarity
uint32_t selclkphase: 1 Select Clock Phase
uint32_t __pad0__: 4 UNDEFINED
uint32_t endiracc: 1 Enable Direct Access Controller
uint32_t enlegacyip: 1 Legacy IP Mode Enable
uint32_t perseldec: 1 Peripheral select decode
uint32_t percslines: 4 Peripheral Chip Select Lines
uint32_t wp: 1 Write Protect Flash Pin
uint32_t endma: 1 Enable DMA Peripheral Interface
uint32_t enahbremap: 1 Enable AHB Address Re-mapping
uint32_t enterxipnextrd: 1 Enter XIP Mode on next READ
uint32_t enterxipimm: 1 Enter XIP Mode Immediately
uint32_t bauddiv: 4 Master Mode Baud Rate Divisor
uint32_t __pad1__: 8 UNDEFINED
const uint32_t idle: 1 Serial interface and QSPI pipeline is IDLE

Macro Definitions

#define ALT_QSPI_CFG_EN_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_EN

Disable the QSPI

#define ALT_QSPI_CFG_EN_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_EN

Enable the QSPI

#define ALT_QSPI_CFG_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_EN register field.

#define ALT_QSPI_CFG_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_EN register field.

#define ALT_QSPI_CFG_EN_WIDTH   1

The width in bits of the ALT_QSPI_CFG_EN register field.

#define ALT_QSPI_CFG_EN_SET_MSK   0x00000001

The mask used to set the ALT_QSPI_CFG_EN register field value.

#define ALT_QSPI_CFG_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_QSPI_CFG_EN register field value.

#define ALT_QSPI_CFG_EN_RESET   0x0

The reset value of the ALT_QSPI_CFG_EN register field.

#define ALT_QSPI_CFG_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_QSPI_CFG_EN field value from a register.

#define ALT_QSPI_CFG_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_QSPI_CFG_EN register field value suitable for setting the register.

#define ALT_QSPI_CFG_SELCLKPOL_E_LOW   0x1

Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL

SPI clock is quiescent low

#define ALT_QSPI_CFG_SELCLKPOL_E_HIGH   0x0

Enumerated value for register field ALT_QSPI_CFG_SELCLKPOL

SPI clock is quiescent high

#define ALT_QSPI_CFG_SELCLKPOL_LSB   1

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPOL register field.

#define ALT_QSPI_CFG_SELCLKPOL_MSB   1

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPOL register field.

#define ALT_QSPI_CFG_SELCLKPOL_WIDTH   1

The width in bits of the ALT_QSPI_CFG_SELCLKPOL register field.

#define ALT_QSPI_CFG_SELCLKPOL_SET_MSK   0x00000002

The mask used to set the ALT_QSPI_CFG_SELCLKPOL register field value.

#define ALT_QSPI_CFG_SELCLKPOL_CLR_MSK   0xfffffffd

The mask used to clear the ALT_QSPI_CFG_SELCLKPOL register field value.

#define ALT_QSPI_CFG_SELCLKPOL_RESET   0x0

The reset value of the ALT_QSPI_CFG_SELCLKPOL register field.

#define ALT_QSPI_CFG_SELCLKPOL_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_QSPI_CFG_SELCLKPOL field value from a register.

#define ALT_QSPI_CFG_SELCLKPOL_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_QSPI_CFG_SELCLKPOL register field value suitable for setting the register.

#define ALT_QSPI_CFG_SELCLKPHASE_E_ACT   0x0

Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE

SPI clock is quiescent low

#define ALT_QSPI_CFG_SELCLKPHASE_E_INACT   0x1

Enumerated value for register field ALT_QSPI_CFG_SELCLKPHASE

Clock Inactive

#define ALT_QSPI_CFG_SELCLKPHASE_LSB   2

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field.

#define ALT_QSPI_CFG_SELCLKPHASE_MSB   2

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_SELCLKPHASE register field.

#define ALT_QSPI_CFG_SELCLKPHASE_WIDTH   1

The width in bits of the ALT_QSPI_CFG_SELCLKPHASE register field.

#define ALT_QSPI_CFG_SELCLKPHASE_SET_MSK   0x00000004

The mask used to set the ALT_QSPI_CFG_SELCLKPHASE register field value.

#define ALT_QSPI_CFG_SELCLKPHASE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_QSPI_CFG_SELCLKPHASE register field value.

#define ALT_QSPI_CFG_SELCLKPHASE_RESET   0x0

The reset value of the ALT_QSPI_CFG_SELCLKPHASE register field.

#define ALT_QSPI_CFG_SELCLKPHASE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_QSPI_CFG_SELCLKPHASE field value from a register.

#define ALT_QSPI_CFG_SELCLKPHASE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_QSPI_CFG_SELCLKPHASE register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENDIRACC_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_ENDIRACC

Disable Direct Access Ctrl

#define ALT_QSPI_CFG_ENDIRACC_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_ENDIRACC

Enable Direct Access Ctrl

#define ALT_QSPI_CFG_ENDIRACC_LSB   7

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDIRACC register field.

#define ALT_QSPI_CFG_ENDIRACC_MSB   7

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDIRACC register field.

#define ALT_QSPI_CFG_ENDIRACC_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENDIRACC register field.

#define ALT_QSPI_CFG_ENDIRACC_SET_MSK   0x00000080

The mask used to set the ALT_QSPI_CFG_ENDIRACC register field value.

#define ALT_QSPI_CFG_ENDIRACC_CLR_MSK   0xffffff7f

The mask used to clear the ALT_QSPI_CFG_ENDIRACC register field value.

#define ALT_QSPI_CFG_ENDIRACC_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENDIRACC register field.

#define ALT_QSPI_CFG_ENDIRACC_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_QSPI_CFG_ENDIRACC field value from a register.

#define ALT_QSPI_CFG_ENDIRACC_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_QSPI_CFG_ENDIRACC register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENLEGACYIP_E_LEGMOD   0x1

Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP

Legacy Mode

#define ALT_QSPI_CFG_ENLEGACYIP_E_DIMOD   0x0

Enumerated value for register field ALT_QSPI_CFG_ENLEGACYIP

Use Direct/Indirect Access Controller

#define ALT_QSPI_CFG_ENLEGACYIP_LSB   8

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field.

#define ALT_QSPI_CFG_ENLEGACYIP_MSB   8

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENLEGACYIP register field.

#define ALT_QSPI_CFG_ENLEGACYIP_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENLEGACYIP register field.

#define ALT_QSPI_CFG_ENLEGACYIP_SET_MSK   0x00000100

The mask used to set the ALT_QSPI_CFG_ENLEGACYIP register field value.

#define ALT_QSPI_CFG_ENLEGACYIP_CLR_MSK   0xfffffeff

The mask used to clear the ALT_QSPI_CFG_ENLEGACYIP register field value.

#define ALT_QSPI_CFG_ENLEGACYIP_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENLEGACYIP register field.

#define ALT_QSPI_CFG_ENLEGACYIP_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_QSPI_CFG_ENLEGACYIP field value from a register.

#define ALT_QSPI_CFG_ENLEGACYIP_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_QSPI_CFG_ENLEGACYIP register field value suitable for setting the register.

#define ALT_QSPI_CFG_PERSELDEC_E_SEL4TO16   0x1

Enumerated value for register field ALT_QSPI_CFG_PERSELDEC

Select external 4-to-16 decode

#define ALT_QSPI_CFG_PERSELDEC_E_SEL1OF4   0x0

Enumerated value for register field ALT_QSPI_CFG_PERSELDEC

Selects 1 of 4 qspi_n_ss_out[3:0]

#define ALT_QSPI_CFG_PERSELDEC_LSB   9

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERSELDEC register field.

#define ALT_QSPI_CFG_PERSELDEC_MSB   9

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERSELDEC register field.

#define ALT_QSPI_CFG_PERSELDEC_WIDTH   1

The width in bits of the ALT_QSPI_CFG_PERSELDEC register field.

#define ALT_QSPI_CFG_PERSELDEC_SET_MSK   0x00000200

The mask used to set the ALT_QSPI_CFG_PERSELDEC register field value.

#define ALT_QSPI_CFG_PERSELDEC_CLR_MSK   0xfffffdff

The mask used to clear the ALT_QSPI_CFG_PERSELDEC register field value.

#define ALT_QSPI_CFG_PERSELDEC_RESET   0x0

The reset value of the ALT_QSPI_CFG_PERSELDEC register field.

#define ALT_QSPI_CFG_PERSELDEC_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_QSPI_CFG_PERSELDEC field value from a register.

#define ALT_QSPI_CFG_PERSELDEC_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_QSPI_CFG_PERSELDEC register field value suitable for setting the register.

#define ALT_QSPI_CFG_PERCSLINES_LSB   10

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_PERCSLINES register field.

#define ALT_QSPI_CFG_PERCSLINES_MSB   13

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_PERCSLINES register field.

#define ALT_QSPI_CFG_PERCSLINES_WIDTH   4

The width in bits of the ALT_QSPI_CFG_PERCSLINES register field.

#define ALT_QSPI_CFG_PERCSLINES_SET_MSK   0x00003c00

The mask used to set the ALT_QSPI_CFG_PERCSLINES register field value.

#define ALT_QSPI_CFG_PERCSLINES_CLR_MSK   0xffffc3ff

The mask used to clear the ALT_QSPI_CFG_PERCSLINES register field value.

#define ALT_QSPI_CFG_PERCSLINES_RESET   0x0

The reset value of the ALT_QSPI_CFG_PERCSLINES register field.

#define ALT_QSPI_CFG_PERCSLINES_GET (   value)    (((value) & 0x00003c00) >> 10)

Extracts the ALT_QSPI_CFG_PERCSLINES field value from a register.

#define ALT_QSPI_CFG_PERCSLINES_SET (   value)    (((value) << 10) & 0x00003c00)

Produces a ALT_QSPI_CFG_PERCSLINES register field value suitable for setting the register.

#define ALT_QSPI_CFG_WP_E_WRPROTON   0x1

Enumerated value for register field ALT_QSPI_CFG_WP

Enable Write Protect

#define ALT_QSPI_CFG_WP_E_WRTPROTOFF   0x0

Enumerated value for register field ALT_QSPI_CFG_WP

Disable Write Protect

#define ALT_QSPI_CFG_WP_LSB   14

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_WP register field.

#define ALT_QSPI_CFG_WP_MSB   14

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_WP register field.

#define ALT_QSPI_CFG_WP_WIDTH   1

The width in bits of the ALT_QSPI_CFG_WP register field.

#define ALT_QSPI_CFG_WP_SET_MSK   0x00004000

The mask used to set the ALT_QSPI_CFG_WP register field value.

#define ALT_QSPI_CFG_WP_CLR_MSK   0xffffbfff

The mask used to clear the ALT_QSPI_CFG_WP register field value.

#define ALT_QSPI_CFG_WP_RESET   0x0

The reset value of the ALT_QSPI_CFG_WP register field.

#define ALT_QSPI_CFG_WP_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_QSPI_CFG_WP field value from a register.

#define ALT_QSPI_CFG_WP_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_QSPI_CFG_WP register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENDMA_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_ENDMA

Enable DMA Mode

#define ALT_QSPI_CFG_ENDMA_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_ENDMA

Disable DMA Mode

#define ALT_QSPI_CFG_ENDMA_LSB   15

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENDMA register field.

#define ALT_QSPI_CFG_ENDMA_MSB   15

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENDMA register field.

#define ALT_QSPI_CFG_ENDMA_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENDMA register field.

#define ALT_QSPI_CFG_ENDMA_SET_MSK   0x00008000

The mask used to set the ALT_QSPI_CFG_ENDMA register field value.

#define ALT_QSPI_CFG_ENDMA_CLR_MSK   0xffff7fff

The mask used to clear the ALT_QSPI_CFG_ENDMA register field value.

#define ALT_QSPI_CFG_ENDMA_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENDMA register field.

#define ALT_QSPI_CFG_ENDMA_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_QSPI_CFG_ENDMA field value from a register.

#define ALT_QSPI_CFG_ENDMA_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_QSPI_CFG_ENDMA register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENAHBREMAP_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP

Enable AHB Re-mapping

#define ALT_QSPI_CFG_ENAHBREMAP_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_ENAHBREMAP

Disable AHB Re-mapping

#define ALT_QSPI_CFG_ENAHBREMAP_LSB   16

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field.

#define ALT_QSPI_CFG_ENAHBREMAP_MSB   16

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENAHBREMAP register field.

#define ALT_QSPI_CFG_ENAHBREMAP_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENAHBREMAP register field.

#define ALT_QSPI_CFG_ENAHBREMAP_SET_MSK   0x00010000

The mask used to set the ALT_QSPI_CFG_ENAHBREMAP register field value.

#define ALT_QSPI_CFG_ENAHBREMAP_CLR_MSK   0xfffeffff

The mask used to clear the ALT_QSPI_CFG_ENAHBREMAP register field value.

#define ALT_QSPI_CFG_ENAHBREMAP_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENAHBREMAP register field.

#define ALT_QSPI_CFG_ENAHBREMAP_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_QSPI_CFG_ENAHBREMAP field value from a register.

#define ALT_QSPI_CFG_ENAHBREMAP_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_QSPI_CFG_ENAHBREMAP register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD

Enter XIP Mode on next READ instruction

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_ENTERXIPNEXTRD

Exit XIP Mode on next READ instruction

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_LSB   17

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_MSB   17

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET_MSK   0x00020000

The mask used to set the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_CLR_MSK   0xfffdffff

The mask used to clear the ALT_QSPI_CFG_ENTERXIPNEXTRD register field value.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENTERXIPNEXTRD register field.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_QSPI_CFG_ENTERXIPNEXTRD field value from a register.

#define ALT_QSPI_CFG_ENTERXIPNEXTRD_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_QSPI_CFG_ENTERXIPNEXTRD register field value suitable for setting the register.

#define ALT_QSPI_CFG_ENTERXIPIMM_E_EN   0x1

Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM

Enter XIP Mode immediately

#define ALT_QSPI_CFG_ENTERXIPIMM_E_DIS   0x0

Enumerated value for register field ALT_QSPI_CFG_ENTERXIPIMM

Exit XIP Mode on next READ instruction

#define ALT_QSPI_CFG_ENTERXIPIMM_LSB   18

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field.

#define ALT_QSPI_CFG_ENTERXIPIMM_MSB   18

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_ENTERXIPIMM register field.

#define ALT_QSPI_CFG_ENTERXIPIMM_WIDTH   1

The width in bits of the ALT_QSPI_CFG_ENTERXIPIMM register field.

#define ALT_QSPI_CFG_ENTERXIPIMM_SET_MSK   0x00040000

The mask used to set the ALT_QSPI_CFG_ENTERXIPIMM register field value.

#define ALT_QSPI_CFG_ENTERXIPIMM_CLR_MSK   0xfffbffff

The mask used to clear the ALT_QSPI_CFG_ENTERXIPIMM register field value.

#define ALT_QSPI_CFG_ENTERXIPIMM_RESET   0x0

The reset value of the ALT_QSPI_CFG_ENTERXIPIMM register field.

#define ALT_QSPI_CFG_ENTERXIPIMM_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_QSPI_CFG_ENTERXIPIMM field value from a register.

#define ALT_QSPI_CFG_ENTERXIPIMM_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_QSPI_CFG_ENTERXIPIMM register field value suitable for setting the register.

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD2   0x0

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/2

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD4   0x1

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/4

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD6   0x2

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/6

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD8   0x3

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/8

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD10   0x4

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/10

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD12   0x5

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/12

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD14   0x6

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/14

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD16   0x7

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/16

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD18   0x8

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/18

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD20   0x9

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/20

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD22   0xa

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/22

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD24   0xb

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/24

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD26   0xc

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/26

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD28   0xd

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/28

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD30   0xe

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/30

#define ALT_QSPI_CFG_BAUDDIV_E_BAUD32   0xf

Enumerated value for register field ALT_QSPI_CFG_BAUDDIV

Baud Rate Div/32

#define ALT_QSPI_CFG_BAUDDIV_LSB   19

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_BAUDDIV register field.

#define ALT_QSPI_CFG_BAUDDIV_MSB   22

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_BAUDDIV register field.

#define ALT_QSPI_CFG_BAUDDIV_WIDTH   4

The width in bits of the ALT_QSPI_CFG_BAUDDIV register field.

#define ALT_QSPI_CFG_BAUDDIV_SET_MSK   0x00780000

The mask used to set the ALT_QSPI_CFG_BAUDDIV register field value.

#define ALT_QSPI_CFG_BAUDDIV_CLR_MSK   0xff87ffff

The mask used to clear the ALT_QSPI_CFG_BAUDDIV register field value.

#define ALT_QSPI_CFG_BAUDDIV_RESET   0xf

The reset value of the ALT_QSPI_CFG_BAUDDIV register field.

#define ALT_QSPI_CFG_BAUDDIV_GET (   value)    (((value) & 0x00780000) >> 19)

Extracts the ALT_QSPI_CFG_BAUDDIV field value from a register.

#define ALT_QSPI_CFG_BAUDDIV_SET (   value)    (((value) << 19) & 0x00780000)

Produces a ALT_QSPI_CFG_BAUDDIV register field value suitable for setting the register.

#define ALT_QSPI_CFG_IDLE_E_SET   0x1

Enumerated value for register field ALT_QSPI_CFG_IDLE

Idle Mode

#define ALT_QSPI_CFG_IDLE_E_NOTSET   0x0

Enumerated value for register field ALT_QSPI_CFG_IDLE

Non-Idle Mode

#define ALT_QSPI_CFG_IDLE_LSB   31

The Least Significant Bit (LSB) position of the ALT_QSPI_CFG_IDLE register field.

#define ALT_QSPI_CFG_IDLE_MSB   31

The Most Significant Bit (MSB) position of the ALT_QSPI_CFG_IDLE register field.

#define ALT_QSPI_CFG_IDLE_WIDTH   1

The width in bits of the ALT_QSPI_CFG_IDLE register field.

#define ALT_QSPI_CFG_IDLE_SET_MSK   0x80000000

The mask used to set the ALT_QSPI_CFG_IDLE register field value.

#define ALT_QSPI_CFG_IDLE_CLR_MSK   0x7fffffff

The mask used to clear the ALT_QSPI_CFG_IDLE register field value.

#define ALT_QSPI_CFG_IDLE_RESET   0x0

The reset value of the ALT_QSPI_CFG_IDLE register field.

#define ALT_QSPI_CFG_IDLE_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_QSPI_CFG_IDLE field value from a register.

#define ALT_QSPI_CFG_IDLE_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_QSPI_CFG_IDLE register field value suitable for setting the register.

#define ALT_QSPI_CFG_OFST   0x0

The byte offset of the ALT_QSPI_CFG register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_QSPI_CFG.