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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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EMMC DDR Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT |
[31:1] | ??? | 0x0 | UNDEFINED |
Field : half_start_bit | |
Control for start bit detection mechanism inside DWC_mobile_storage based on duration of start bit; each bit refers to one slot. For eMMC 4.5, start bit can be: ■ Full cycle (HALF_START_BIT = 0) ■ Less than one full cycle (HALF_START_BIT = 1) Set HALF_START_BIT=1 for eMMC 4.5 and above; set to 0 for SD applications. Field Access Macros: | |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_LSB 0 |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_MSB 0 |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_WIDTH 1 |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET_MSK 0x00000001 |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_CLR_MSK 0xfffffffe |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_RESET 0x0 |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET(value) (((value) << 0) & 0x00000001) |
Data Structures | |
struct | ALT_SDMMC_EMMC_DDR_REG_s |
Macros | |
#define | ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000 |
#define | ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c |
Typedefs | |
typedef struct ALT_SDMMC_EMMC_DDR_REG_s | ALT_SDMMC_EMMC_DDR_REG_t |
struct ALT_SDMMC_EMMC_DDR_REG_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_EMMC_DDR_REG.
Data Fields | ||
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uint32_t | half_start_bit: 1 | ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT |
uint32_t | __pad0__: 31 | UNDEFINED |
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_WIDTH 1 |
The width in bits of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET_MSK 0x00000001 |
The mask used to set the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_RESET 0x0 |
The reset value of the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT field value from a register.
#define ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDMMC_EMMC_DDR_REG_HALF_START_BIT register field value suitable for setting the register.
#define ALT_SDMMC_EMMC_DDR_REG_RESET 0x00000000 |
The reset value of the ALT_SDMMC_EMMC_DDR_REG register.
#define ALT_SDMMC_EMMC_DDR_REG_OFST 0x10c |
The byte offset of the ALT_SDMMC_EMMC_DDR_REG register from the beginning of the component.
typedef struct ALT_SDMMC_EMMC_DDR_REG_s ALT_SDMMC_EMMC_DDR_REG_t |
The typedef declaration for register ALT_SDMMC_EMMC_DDR_REG.