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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 66 (MMC Transmit Interrupt Register)
The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half of their maximum values (0x8000_0000 for 32-bit counter and 0x8000 for 16-bit counter), and the maximum values (0xFFFF_FFFF for 32-bit counter and 0xFFFF for 16-bit counter). When Counter Stop Rollover is set, then interrupts are set but the counter remains at all- ones. The MMC Transmit Interrupt register is a 32-bit wide register. An interrupt bit is cleared when the respective MMC counter that caused the interrupt is read. The least significant byte lane (Bits[7:0]) of the respective counter must be read in order to clear the interrupt bit.
Register Layout
Field : txgboctis | |
MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB 0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB 0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET(value) (((value) << 0) & 0x00000001) |
Field : txgbfrmis | |
MMC Transmit Good Bad Frame Counter Interrupt Status This bit is set when the txframecount_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET(value) (((value) << 1) & 0x00000002) |
Field : txbcgfis | |
MMC Transmit Broadcast Good Frame Counter Interrupt Status This bit is set when the txbroadcastframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB 2 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB 2 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK 0x00000004 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK 0xfffffffb |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET(value) (((value) << 2) & 0x00000004) |
Field : txmcgfis | |
MMC Transmit Multicast Good Frame Counter Interrupt Status This bit is set when the txmulticastframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB 3 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB 3 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET(value) (((value) << 3) & 0x00000008) |
Field : tx64octgbfis | |
MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status. This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB 4 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB 4 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK 0x00000010 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK 0xffffffef |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET(value) (((value) << 4) & 0x00000010) |
Field : tx65t127octgbfis | |
MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB 5 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB 5 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK 0x00000020 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK 0xffffffdf |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET(value) (((value) << 5) & 0x00000020) |
Field : tx128t255octgbfis | |
MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB 6 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB 6 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK 0x00000040 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK 0xffffffbf |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET(value) (((value) << 6) & 0x00000040) |
Field : tx256t511octgbfis | |
MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB 7 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB 7 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK 0x00000080 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK 0xffffff7f |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET(value) (((value) << 7) & 0x00000080) |
Field : tx512t1023octgbfis | |
MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB 8 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB 8 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK 0x00000100 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK 0xfffffeff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET(value) (((value) << 8) & 0x00000100) |
Field : tx1024tmaxoctgbfis | |
MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB 9 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB 9 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00000200 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffffdff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET(value) (((value) << 9) & 0x00000200) |
Field : txucgbfis | |
MMC Transmit Unicast Good Bad Frame Counter Interrupt Status This bit is set when the txunicastframes_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB 10 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB 10 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK 0x00000400 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK 0xfffffbff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET(value) (((value) << 10) & 0x00000400) |
Field : txmcgbfis | |
MMC Transmit Multicast Good Bad Frame Counter Interrupt Status This bit is set when the txmulticastframes_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB 11 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB 11 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK 0x00000800 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK 0xfffff7ff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET(value) (((value) << 11) & 0x00000800) |
Field : txbcgbfis | |
MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status This bit is set when the txbroadcastframes_gb counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB 12 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB 12 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK 0x00001000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK 0xffffefff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET(value) (((value) << 12) & 0x00001000) |
Field : txuflowerfis | |
MMC Transmit Underflow Error Frame Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB 13 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB 13 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK 0x00002000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK 0xffffdfff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET(value) (((value) << 13) & 0x00002000) |
Field : txscolgfis | |
MMC Transmit Single Collision Good Frame Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB 14 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB 14 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK 0x00004000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK 0xffffbfff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET(value) (((value) << 14) & 0x00004000) |
Field : txmcolgfis | |
MMC Transmit Multiple Collision Good Frame Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB 15 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB 15 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK 0x00008000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK 0xffff7fff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET(value) (((value) << 15) & 0x00008000) |
Field : txdeffis | |
MMC Transmit Deferred Frame Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB 16 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB 16 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET(value) (((value) << 16) & 0x00010000) |
Field : txlatcolfis | |
MMC Transmit Late Collision Frame Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB 17 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB 17 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK 0x00020000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK 0xfffdffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET(value) (((value) & 0x00020000) >> 17) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET(value) (((value) << 17) & 0x00020000) |
Field : txexcolfis | |
MMC Transmit Excessive Collision Frame Counter Interrupt Status This bit is set when the txexcesscol counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB 18 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB 18 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK 0x00040000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK 0xfffbffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET(value) (((value) << 18) & 0x00040000) |
Field : txcarerfis | |
MMC Transmit Carrier Error Frame Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB 19 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB 19 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK 0x00080000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK 0xfff7ffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET(value) (((value) << 19) & 0x00080000) |
Field : txgoctis | |
MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB 20 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB 20 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK 0x00100000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK 0xffefffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET(value) (((value) & 0x00100000) >> 20) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET(value) (((value) << 20) & 0x00100000) |
Field : txgfrmis | |
MMC Transmit Good Frame Counter Interrupt Status This bit is set when the txframecount_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB 21 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB 21 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK 0x00200000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK 0xffdfffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET(value) (((value) & 0x00200000) >> 21) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET(value) (((value) << 21) & 0x00200000) |
Field : txexdeffis | |
MMC Transmit Excessive Deferral Frame Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB 22 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB 22 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK 0x00400000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK 0xffbfffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET(value) (((value) << 22) & 0x00400000) |
Field : txpausfis | |
MMC Transmit Pause Frame Counter Interrupt Status This bit is set when the txpauseframeserror counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB 23 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB 23 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK 0x00800000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK 0xff7fffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET(value) (((value) << 23) & 0x00800000) |
Field : txvlangfis | |
MMC Transmit VLAN Good Frame Counter Interrupt Status This bit is set when the txvlanframes_g counter reaches half of the maximum value or the maximum value. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD | 0x0 | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END 0x1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB 24 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB 24 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK 0x01000000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK 0xfeffffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET(value) (((value) << 24) & 0x01000000) |
Field : txosizegfis | |
MMC Transmit Oversize Good Frame Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB 25 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB 25 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH 1 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK 0x02000000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK 0xfdffffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET(value) (((value) << 25) & 0x02000000) |
Field : reserved_31_26 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_LSB 26 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_MSB 31 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_WIDTH 6 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET_MSK 0xfc000000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_CLR_MSK 0x03ffffff |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_RESET 0x0 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26) |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000) |
Data Structures | |
struct | ALT_EMAC_GMAC_MMC_TX_INT_s |
Macros | |
#define | ALT_EMAC_GMAC_MMC_TX_INT_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_OFST 0x108 |
#define | ALT_EMAC_GMAC_MMC_TX_INT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_MMC_TX_INT_s | ALT_EMAC_GMAC_MMC_TX_INT_t |
struct ALT_EMAC_GMAC_MMC_TX_INT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_MMC_TX_INT.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBOCTIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_GBFRMIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_64OCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_65T127OCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET_MSK 0x00000040 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_128T255OCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_256T511OCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_512T1023OCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET_MSK 0x00000200 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_1024TMAXOCTGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET_MSK 0x00000400 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_UCGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET_MSK 0x00000800 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET_MSK 0x00001000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_CLR_MSK 0xffffefff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_BCGBFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_UFLOWERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET_MSK 0x00004000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_SCOLGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET_MSK 0x00008000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_MCOLGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_DEFFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET_MSK 0x00020000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_CLR_MSK 0xfffdffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_GET | ( | value | ) | (((value) & 0x00020000) >> 17) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS_SET | ( | value | ) | (((value) << 17) & 0x00020000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_LATCOLFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXCOLFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_CARERFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET_MSK 0x00100000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_CLR_MSK 0xffefffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_GET | ( | value | ) | (((value) & 0x00100000) >> 20) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS_SET | ( | value | ) | (((value) << 20) & 0x00100000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_GOCTIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET_MSK 0x00200000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_CLR_MSK 0xffdfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_GET | ( | value | ) | (((value) & 0x00200000) >> 21) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS_SET | ( | value | ) | (((value) << 21) & 0x00200000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_GFRMIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET_MSK 0x00400000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_EXDEFFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET_MSK 0x00800000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_PAUSFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_VLANGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_OSIZEGFIS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_WIDTH 6 |
The width in bits of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET_MSK 0xfc000000 |
The mask used to set the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_CLR_MSK 0x03ffffff |
The mask used to clear the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_GET | ( | value | ) | (((value) & 0xfc000000) >> 26) |
Extracts the ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 field value from a register.
#define ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26_SET | ( | value | ) | (((value) << 26) & 0xfc000000) |
Produces a ALT_EMAC_GMAC_MMC_TX_INT_RSVD_31_26 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_MMC_TX_INT_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_MMC_TX_INT register.
#define ALT_EMAC_GMAC_MMC_TX_INT_OFST 0x108 |
The byte offset of the ALT_EMAC_GMAC_MMC_TX_INT register from the beginning of the component.
#define ALT_EMAC_GMAC_MMC_TX_INT_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MMC_TX_INT_OFST)) |
The address of the ALT_EMAC_GMAC_MMC_TX_INT register.
typedef struct ALT_EMAC_GMAC_MMC_TX_INT_s ALT_EMAC_GMAC_MMC_TX_INT_t |
The typedef declaration for register ALT_EMAC_GMAC_MMC_TX_INT.