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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This is the register the CPU writes to when filling the TX FIFO. Reading from this register returns bytes from RX FIFO.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x0 | Tx Rx Data |
[8] | W | 0x0 | Master Read Write Control |
[9] | W | 0x0 | Generate Stop |
[10] | W | 0x0 | Generate Restart |
[31:11] | ??? | 0x0 | UNDEFINED |
Field : Tx Rx Data - dat | |
This Field contains the data to be transmitted or received on the I2C bus. If you are writing to these bits and want to perform a read, bits 7:0 (dat) are ignored by the I2C. However, when you read from this register, these bits return the value of data received on the I2C interface. Field Access Macros: | |
#define | ALT_I2C_DATA_CMD_DAT_LSB 0 |
#define | ALT_I2C_DATA_CMD_DAT_MSB 7 |
#define | ALT_I2C_DATA_CMD_DAT_WIDTH 8 |
#define | ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff |
#define | ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 |
#define | ALT_I2C_DATA_CMD_DAT_RESET 0x0 |
#define | ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff) |
Field : Master Read Write Control - cmd | ||||||||||
This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the CPU data is to be transmitted. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a tx_abrt interrupt (bit 6 of the Raw Intr Status Register), unless bit 11 special in the Target Address Register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a tx_abrt interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on I2C, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing I2C. In this type of scenario, I2C ignores the Data Cmd write, generates a tx_abrt interrupt, and waits to service the RD_REQ interrupt. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_DATA_CMD_CMD_E_RD 0x1 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_E_WR 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_LSB 8 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_MSB 8 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_WIDTH 1 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_RESET 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : Generate Stop - stop | ||||||||||
This bit controls whether a STOP is issued after the byte is sent or received. 1 = STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. 0 = STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_LSB 9 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_MSB 9 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_WIDTH 1 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_RESET 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9) | |||||||||
#define | ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200) | |||||||||
Field : Generate Restart - restart | ||||||||||
This bit controls whether a RESTART is issued before the byte is sent or received. 1 = A RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command. 0 = A RESTART is issued only if the transfer direction is changing from the previous command. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_LSB 10 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_MSB 10 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_WIDTH 1 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_RESET 0x0 | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10) | |||||||||
#define | ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400) | |||||||||
Data Structures | |
struct | ALT_I2C_DATA_CMD_s |
Macros | |
#define | ALT_I2C_DATA_CMD_OFST 0x10 |
#define | ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) |
Typedefs | |
typedef struct ALT_I2C_DATA_CMD_s | ALT_I2C_DATA_CMD_t |
struct ALT_I2C_DATA_CMD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_DATA_CMD.
Data Fields | ||
---|---|---|
uint32_t | dat: 8 | Tx Rx Data |
uint32_t | cmd: 1 | Master Read Write Control |
uint32_t | stop: 1 | Generate Stop |
uint32_t | restart: 1 | Generate Restart |
uint32_t | __pad0__: 21 | UNDEFINED |
#define ALT_I2C_DATA_CMD_DAT_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_DAT register field.
#define ALT_I2C_DATA_CMD_DAT_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_DAT register field.
#define ALT_I2C_DATA_CMD_DAT_WIDTH 8 |
The width in bits of the ALT_I2C_DATA_CMD_DAT register field.
#define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff |
The mask used to set the ALT_I2C_DATA_CMD_DAT register field value.
#define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_I2C_DATA_CMD_DAT register field value.
#define ALT_I2C_DATA_CMD_DAT_RESET 0x0 |
The reset value of the ALT_I2C_DATA_CMD_DAT register field.
#define ALT_I2C_DATA_CMD_DAT_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_I2C_DATA_CMD_DAT field value from a register.
#define ALT_I2C_DATA_CMD_DAT_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_I2C_DATA_CMD_DAT register field value suitable for setting the register.
#define ALT_I2C_DATA_CMD_CMD_E_RD 0x1 |
Enumerated value for register field ALT_I2C_DATA_CMD_CMD
Master Read
#define ALT_I2C_DATA_CMD_CMD_E_WR 0x0 |
Enumerated value for register field ALT_I2C_DATA_CMD_CMD
Master Write
#define ALT_I2C_DATA_CMD_CMD_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_CMD register field.
#define ALT_I2C_DATA_CMD_CMD_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_CMD register field.
#define ALT_I2C_DATA_CMD_CMD_WIDTH 1 |
The width in bits of the ALT_I2C_DATA_CMD_CMD register field.
#define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100 |
The mask used to set the ALT_I2C_DATA_CMD_CMD register field value.
#define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_I2C_DATA_CMD_CMD register field value.
#define ALT_I2C_DATA_CMD_CMD_RESET 0x0 |
The reset value of the ALT_I2C_DATA_CMD_CMD register field.
#define ALT_I2C_DATA_CMD_CMD_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_I2C_DATA_CMD_CMD field value from a register.
#define ALT_I2C_DATA_CMD_CMD_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_I2C_DATA_CMD_CMD register field value suitable for setting the register.
#define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1 |
Enumerated value for register field ALT_I2C_DATA_CMD_STOP
Issue Stop
#define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0 |
Enumerated value for register field ALT_I2C_DATA_CMD_STOP
Do Not Issue Stop
#define ALT_I2C_DATA_CMD_STOP_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_STOP register field.
#define ALT_I2C_DATA_CMD_STOP_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_STOP register field.
#define ALT_I2C_DATA_CMD_STOP_WIDTH 1 |
The width in bits of the ALT_I2C_DATA_CMD_STOP register field.
#define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200 |
The mask used to set the ALT_I2C_DATA_CMD_STOP register field value.
#define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_I2C_DATA_CMD_STOP register field value.
#define ALT_I2C_DATA_CMD_STOP_RESET 0x0 |
The reset value of the ALT_I2C_DATA_CMD_STOP register field.
#define ALT_I2C_DATA_CMD_STOP_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_I2C_DATA_CMD_STOP field value from a register.
#define ALT_I2C_DATA_CMD_STOP_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_I2C_DATA_CMD_STOP register field value suitable for setting the register.
#define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1 |
Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
Issue Restart
#define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0 |
Enumerated value for register field ALT_I2C_DATA_CMD_RESTART
Issue Restart On Direction Change
#define ALT_I2C_DATA_CMD_RESTART_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_I2C_DATA_CMD_RESTART register field.
#define ALT_I2C_DATA_CMD_RESTART_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_I2C_DATA_CMD_RESTART register field.
#define ALT_I2C_DATA_CMD_RESTART_WIDTH 1 |
The width in bits of the ALT_I2C_DATA_CMD_RESTART register field.
#define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400 |
The mask used to set the ALT_I2C_DATA_CMD_RESTART register field value.
#define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_I2C_DATA_CMD_RESTART register field value.
#define ALT_I2C_DATA_CMD_RESTART_RESET 0x0 |
The reset value of the ALT_I2C_DATA_CMD_RESTART register field.
#define ALT_I2C_DATA_CMD_RESTART_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_I2C_DATA_CMD_RESTART field value from a register.
#define ALT_I2C_DATA_CMD_RESTART_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_I2C_DATA_CMD_RESTART register field value suitable for setting the register.
#define ALT_I2C_DATA_CMD_OFST 0x10 |
The byte offset of the ALT_I2C_DATA_CMD register from the beginning of the component.
#define ALT_I2C_DATA_CMD_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST)) |
The address of the ALT_I2C_DATA_CMD register.
typedef struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t |
The typedef declaration for register ALT_I2C_DATA_CMD.