![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Priority register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x0 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 |
[7:2] | ??? | Unknown | UNDEFINED |
[9:8] | RW | 0x1 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 |
[30:10] | ??? | Unknown | UNDEFINED |
[31] | R | 0x1 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK |
Field : P0 | |
In Programmable or Bandwidth Limiter mode, the priority level for write transactions. In Bandwidth Regulator mode, the priority level when the used throughput is above the threshold. In Bandwidth Regulator mode, P0 should have a value equal or lower than P1. Field Access Macros: | |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_LSB 0 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_MSB 1 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_WIDTH 2 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_SET_MSK 0x00000003 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_CLR_MSK 0xfffffffc |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_RESET 0x0 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_GET(value) (((value) & 0x00000003) >> 0) |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_SET(value) (((value) << 0) & 0x00000003) |
Field : P1 | |
In Programmable or Bandwidth Limiter mode, the priority level for read transactions. In Bandwidth regulator mode, the priority level when the used throughput is below the threshold. In Bandwidth Regulator mode, P1 should have a value equal or greater than P0. Field Access Macros: | |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_LSB 8 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_MSB 9 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_WIDTH 2 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_SET_MSK 0x00000300 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_CLR_MSK 0xfffffcff |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_RESET 0x1 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_GET(value) (((value) & 0x00000300) >> 8) |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_SET(value) (((value) << 8) & 0x00000300) |
Field : MARK | |
Backward compatibility marker when 0. Field Access Macros: | |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_LSB 31 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_MSB 31 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_WIDTH 1 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_SET_MSK 0x80000000 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_CLR_MSK 0x7fffffff |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_RESET 0x1 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_GET(value) (((value) & 0x80000000) >> 31) |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_SET(value) (((value) << 31) & 0x80000000) |
Data Structures | |
struct | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_s |
Macros | |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_RESET 0x80000100 |
#define | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_OFST 0x8 |
Typedefs | |
typedef struct ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_s | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_t |
struct ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI.
Data Fields | ||
---|---|---|
uint32_t | P0: 2 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 |
uint32_t | __pad0__: 6 | UNDEFINED |
uint32_t | P1: 2 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 |
uint32_t | __pad1__: 21 | UNDEFINED |
const uint32_t | MARK: 1 | ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK |
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_WIDTH 2 |
The width in bits of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_SET_MSK 0x00000003 |
The mask used to set the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_RESET 0x0 |
The reset value of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 field value from a register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P0 register field value suitable for setting the register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_WIDTH 2 |
The width in bits of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_SET_MSK 0x00000300 |
The mask used to set the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_RESET 0x1 |
The reset value of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 field value from a register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_P1 register field value suitable for setting the register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_LSB 31 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_WIDTH 1 |
The width in bits of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_SET_MSK 0x80000000 |
The mask used to set the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_CLR_MSK 0x7fffffff |
The mask used to clear the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field value.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_RESET 0x1 |
The reset value of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_GET | ( | value | ) | (((value) & 0x80000000) >> 31) |
Extracts the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK field value from a register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK_SET | ( | value | ) | (((value) << 31) & 0x80000000) |
Produces a ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_MARK register field value suitable for setting the register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_RESET 0x80000100 |
The reset value of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI register.
#define ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI_OFST 0x8 |
The byte offset of the ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI register from the beginning of the component.
The typedef declaration for register ALT_NOC_MPU_NAND_M_MAIN_QOS_PRI.