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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains information used to control Boot ROM code.
Reset only on a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Warm Reset Configure Pin Mux for Boot Pins |
[1] | RW | 0x0 | Warm Reset Configure IOs for Boot Pins |
[31:2] | ??? | 0x0 | UNDEFINED |
Field : Warm Reset Configure Pin Mux for Boot Pins - warmrstcfgpinmux | |
Specifies whether the Boot ROM code configures the pin mux for boot pins after a warm reset. Note that the Boot ROM code always configures the pin mux for boot pins after a cold reset. After the Boot ROM code configures the pin mux for boot pins, it always disables this field. It is up to user software to enable this field if it wants a different behavior. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD | 0x0 | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET(value) (((value) << 0) & 0x00000001) |
Field : Warm Reset Configure IOs for Boot Pins - warmrstcfgio | |
Specifies whether the Boot ROM code configures the IOs used by boot after a warm reset. Note that the Boot ROM code always configures the IOs used by boot after a cold reset. After the Boot ROM code configures the IOs used by boot, it always disables this field. It is up to user software to enable this field if it wants a different behavior. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD | 0x0 | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET(value) (((value) << 1) & 0x00000002) |
Data Structures | |
struct | ALT_SYSMGR_ROM_ROMCODE_CTL_s |
Macros | |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_RESET 0x00000000 |
#define | ALT_SYSMGR_ROM_ROMCODE_CTL_OFST 0x4 |
Typedefs | |
typedef struct ALT_SYSMGR_ROM_ROMCODE_CTL_s | ALT_SYSMGR_ROM_ROMCODE_CTL_t |
struct ALT_SYSMGR_ROM_ROMCODE_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_ROM_ROMCODE_CTL.
Data Fields | ||
---|---|---|
uint32_t | warmrstcfgpinmux: 1 | Warm Reset Configure Pin Mux for Boot Pins |
uint32_t | warmrstcfgio: 1 | Warm Reset Configure IOs for Boot Pins |
uint32_t | __pad0__: 30 | UNDEFINED |
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_DISD 0x0 |
Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_E_END 0x1 |
Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_RESET 0x0 |
The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX field value from a register.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGPINMUX register field value suitable for setting the register.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_DISD 0x0 |
Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_E_END 0x1 |
Enumerated value for register field ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_RESET 0x0 |
The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO field value from a register.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_ROM_ROMCODE_CTL_WARMRSTCFGIO register field value suitable for setting the register.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_RESET 0x00000000 |
The reset value of the ALT_SYSMGR_ROM_ROMCODE_CTL register.
#define ALT_SYSMGR_ROM_ROMCODE_CTL_OFST 0x4 |
The byte offset of the ALT_SYSMGR_ROM_ROMCODE_CTL register from the beginning of the component.
typedef struct ALT_SYSMGR_ROM_ROMCODE_CTL_s ALT_SYSMGR_ROM_ROMCODE_CTL_t |
The typedef declaration for register ALT_SYSMGR_ROM_ROMCODE_CTL.