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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Read/Write Enable low pulse width
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[4:0] | RW | 0x12 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE |
[31:5] | ??? | 0x0 | UNDEFINED |
Field : value | |
Number of nand_mp_clk cycles that read or write enable will kept low to meet the min Trp/Twp parameter of the device. The value in this register plus rdwr_en_hi_cnt register value should meet the min cycle time of the device connected. The default value is calculated assuming the max nand_mp_clk time period of 4ns to work with ONFI Mode 0 mode of 100ns device cycle time. This assumes a 1x/4x clocking scheme. Field Access Macros: | |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0 |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4 |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5 |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0 |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12 |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET(value) (((value) & 0x0000001f) >> 0) |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET(value) (((value) << 0) & 0x0000001f) |
Data Structures | |
struct | ALT_NAND_CFG_RDWR_EN_LO_CNT_s |
Macros | |
#define | ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0 |
Typedefs | |
typedef struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s | ALT_NAND_CFG_RDWR_EN_LO_CNT_t |
struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT.
Data Fields | ||
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uint32_t | value: 5 | ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_WIDTH 5 |
The width in bits of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET_MSK 0x0000001f |
The mask used to set the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_CLR_MSK 0xffffffe0 |
The mask used to clear the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_RESET 0x12 |
The reset value of the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_GET | ( | value | ) | (((value) & 0x0000001f) >> 0) |
Extracts the ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE field value from a register.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE_SET | ( | value | ) | (((value) << 0) & 0x0000001f) |
Produces a ALT_NAND_CFG_RDWR_EN_LO_CNT_VALUE register field value suitable for setting the register.
#define ALT_NAND_CFG_RDWR_EN_LO_CNT_OFST 0x1f0 |
The byte offset of the ALT_NAND_CFG_RDWR_EN_LO_CNT register from the beginning of the component.
typedef struct ALT_NAND_CFG_RDWR_EN_LO_CNT_s ALT_NAND_CFG_RDWR_EN_LO_CNT_t |
The typedef declaration for register ALT_NAND_CFG_RDWR_EN_LO_CNT.