Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Component : ALT_IO48_HMC_MMR

Description

Members

 Register : dbgcfg0
 
 Register : dbgcfg1
 
 Register : dbgcfg2
 
 Register : dbgcfg3
 
 Register : dbgcfg4
 
 Register : dbgcfg5
 
 Register : dbgcfg6
 
 Register : reserve0
 
 Register : reserve1
 
 Register : reserve2
 
 Register : ctrlcfg0
 
 Register : ctrlcfg1
 
 Register : ctrlcfg2
 
 Register : ctrlcfg3
 
 Register : ctrlcfg4
 
 Register : ctrlcfg5
 
 Register : ctrlcfg6
 
 Register : ctrlcfg7
 
 Register : ctrlcfg8
 
 Register : ctrlcfg9
 
 Register : dramtiming0
 
 Register : dramodt0
 
 Register : dramodt1
 
 Register : sbcfg0
 
 Register : sbcfg1
 
 Register : sbcfg2
 
 Register : sbcfg3
 
 Register : sbcfg4
 
 Register : sbcfg5
 
 Register : sbcfg6
 
 Register : sbcfg7
 
 Register : caltiming0
 
 Register : caltiming1
 
 Register : caltiming2
 
 Register : caltiming3
 
 Register : caltiming4
 
 Register : caltiming5
 
 Register : caltiming6
 
 Register : caltiming7
 
 Register : caltiming8
 
 Register : caltiming9
 
 Register : caltiming10
 
 Register : dramaddrw
 
 Register : sideband0
 
 Register : sideband1
 
 Register : sideband2
 
 Register : sideband3
 
 Register : sideband4
 
 Register : sideband5
 
 Register : sideband6
 
 Register : sideband7
 
 Register : sideband8
 
 Register : sideband9
 
 Register : sideband10
 
 Register : sideband11
 
 Register : sideband12
 
 Register : sideband13
 
 Register : sideband14
 
 Register : sideband15
 
 Register : dramsts
 
 Register : dbgdone
 
 Register : dbgsignals
 
 Register : dbgreset
 
 Register : dbgmatch
 
 Register : counter0mask
 
 Register : counter1mask
 
 Register : counter0match
 
 Register : counter1match
 
 Register : niosreserve0
 
 Register : niosreserve1
 
 Register : niosreserve2
 

Data Structures

struct  ALT_IO48_HMC_MMR_s
 
struct  ALT_IO48_HMC_MMR_raw_s
 

Typedefs

typedef struct ALT_IO48_HMC_MMR_s ALT_IO48_HMC_MMR_t
 
typedef struct
ALT_IO48_HMC_MMR_raw_s 
ALT_IO48_HMC_MMR_raw_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register group ALT_IO48_HMC_MMR.

Data Fields
volatile ALT_IO48_HMC_MMR_DBGCFG0_t dbgcfg0 ALT_IO48_HMC_MMR_DBGCFG0
volatile ALT_IO48_HMC_MMR_DBGCFG1_t dbgcfg1 ALT_IO48_HMC_MMR_DBGCFG1
volatile ALT_IO48_HMC_MMR_DBGCFG2_t dbgcfg2 ALT_IO48_HMC_MMR_DBGCFG2
volatile ALT_IO48_HMC_MMR_DBGCFG3_t dbgcfg3 ALT_IO48_HMC_MMR_DBGCFG3
volatile ALT_IO48_HMC_MMR_DBGCFG4_t dbgcfg4 ALT_IO48_HMC_MMR_DBGCFG4
volatile ALT_IO48_HMC_MMR_DBGCFG5_t dbgcfg5 ALT_IO48_HMC_MMR_DBGCFG5
volatile ALT_IO48_HMC_MMR_DBGCFG6_t dbgcfg6 ALT_IO48_HMC_MMR_DBGCFG6
volatile
ALT_IO48_HMC_MMR_RESERVE0_t
reserve0 ALT_IO48_HMC_MMR_RESERVE0
volatile
ALT_IO48_HMC_MMR_RESERVE1_t
reserve1 ALT_IO48_HMC_MMR_RESERVE1
volatile
ALT_IO48_HMC_MMR_RESERVE2_t
reserve2 ALT_IO48_HMC_MMR_RESERVE2
volatile ALT_IO48_HMC_MMR_CTLCFG0_t ctrlcfg0 ALT_IO48_HMC_MMR_CTLCFG0
volatile ALT_IO48_HMC_MMR_CTLCFG1_t ctrlcfg1 ALT_IO48_HMC_MMR_CTLCFG1
volatile ALT_IO48_HMC_MMR_CTLCFG2_t ctrlcfg2 ALT_IO48_HMC_MMR_CTLCFG2
volatile ALT_IO48_HMC_MMR_CTLCFG3_t ctrlcfg3 ALT_IO48_HMC_MMR_CTLCFG3
volatile ALT_IO48_HMC_MMR_CTLCFG4_t ctrlcfg4 ALT_IO48_HMC_MMR_CTLCFG4
volatile ALT_IO48_HMC_MMR_CTLCFG5_t ctrlcfg5 ALT_IO48_HMC_MMR_CTLCFG5
volatile ALT_IO48_HMC_MMR_CTLCFG6_t ctrlcfg6 ALT_IO48_HMC_MMR_CTLCFG6
volatile ALT_IO48_HMC_MMR_CTLCFG7_t ctrlcfg7 ALT_IO48_HMC_MMR_CTLCFG7
volatile ALT_IO48_HMC_MMR_CTLCFG8_t ctrlcfg8 ALT_IO48_HMC_MMR_CTLCFG8
volatile ALT_IO48_HMC_MMR_CTLCFG9_t ctrlcfg9 ALT_IO48_HMC_MMR_CTLCFG9
volatile
ALT_IO48_HMC_MMR_DRAMTIMING0_t
dramtiming0 ALT_IO48_HMC_MMR_DRAMTIMING0
volatile
ALT_IO48_HMC_MMR_DRAMODT0_t
dramodt0 ALT_IO48_HMC_MMR_DRAMODT0
volatile
ALT_IO48_HMC_MMR_DRAMODT1_t
dramodt1 ALT_IO48_HMC_MMR_DRAMODT1
volatile ALT_IO48_HMC_MMR_SBCFG0_t sbcfg0 ALT_IO48_HMC_MMR_SBCFG0
volatile ALT_IO48_HMC_MMR_SBCFG1_t sbcfg1 ALT_IO48_HMC_MMR_SBCFG1
volatile ALT_IO48_HMC_MMR_SBCFG2_t sbcfg2 ALT_IO48_HMC_MMR_SBCFG2
volatile ALT_IO48_HMC_MMR_SBCFG3_t sbcfg3 ALT_IO48_HMC_MMR_SBCFG3
volatile ALT_IO48_HMC_MMR_SBCFG4_t sbcfg4 ALT_IO48_HMC_MMR_SBCFG4
volatile ALT_IO48_HMC_MMR_SBCFG5_t sbcfg5 ALT_IO48_HMC_MMR_SBCFG5
volatile ALT_IO48_HMC_MMR_SBCFG6_t sbcfg6 ALT_IO48_HMC_MMR_SBCFG6
volatile ALT_IO48_HMC_MMR_SBCFG7_t sbcfg7 ALT_IO48_HMC_MMR_SBCFG7
volatile
ALT_IO48_HMC_MMR_CALTIMING0_t
caltiming0 ALT_IO48_HMC_MMR_CALTIMING0
volatile
ALT_IO48_HMC_MMR_CALTIMING1_t
caltiming1 ALT_IO48_HMC_MMR_CALTIMING1
volatile
ALT_IO48_HMC_MMR_CALTIMING2_t
caltiming2 ALT_IO48_HMC_MMR_CALTIMING2
volatile
ALT_IO48_HMC_MMR_CALTIMING3_t
caltiming3 ALT_IO48_HMC_MMR_CALTIMING3
volatile
ALT_IO48_HMC_MMR_CALTIMING4_t
caltiming4 ALT_IO48_HMC_MMR_CALTIMING4
volatile
ALT_IO48_HMC_MMR_CALTIMING5_t
caltiming5 ALT_IO48_HMC_MMR_CALTIMING5
volatile
ALT_IO48_HMC_MMR_CALTIMING6_t
caltiming6 ALT_IO48_HMC_MMR_CALTIMING6
volatile
ALT_IO48_HMC_MMR_CALTIMING7_t
caltiming7 ALT_IO48_HMC_MMR_CALTIMING7
volatile
ALT_IO48_HMC_MMR_CALTIMING8_t
caltiming8 ALT_IO48_HMC_MMR_CALTIMING8
volatile
ALT_IO48_HMC_MMR_CALTIMING9_t
caltiming9 ALT_IO48_HMC_MMR_CALTIMING9
volatile
ALT_IO48_HMC_MMR_CALTIMING10_t
caltiming10 ALT_IO48_HMC_MMR_CALTIMING10
volatile
ALT_IO48_HMC_MMR_DRAMADDRW_t
dramaddrw ALT_IO48_HMC_MMR_DRAMADDRW
volatile
ALT_IO48_HMC_MMR_SIDEBAND0_t
sideband0 ALT_IO48_HMC_MMR_SIDEBAND0
volatile
ALT_IO48_HMC_MMR_SIDEBAND1_t
sideband1 ALT_IO48_HMC_MMR_SIDEBAND1
volatile
ALT_IO48_HMC_MMR_SIDEBAND2_t
sideband2 ALT_IO48_HMC_MMR_SIDEBAND2
volatile
ALT_IO48_HMC_MMR_SIDEBAND3_t
sideband3 ALT_IO48_HMC_MMR_SIDEBAND3
volatile
ALT_IO48_HMC_MMR_SIDEBAND4_t
sideband4 ALT_IO48_HMC_MMR_SIDEBAND4
volatile
ALT_IO48_HMC_MMR_SIDEBAND5_t
sideband5 ALT_IO48_HMC_MMR_SIDEBAND5
volatile
ALT_IO48_HMC_MMR_SIDEBAND6_t
sideband6 ALT_IO48_HMC_MMR_SIDEBAND6
volatile
ALT_IO48_HMC_MMR_SIDEBAND7_t
sideband7 ALT_IO48_HMC_MMR_SIDEBAND7
volatile
ALT_IO48_HMC_MMR_SIDEBAND8_t
sideband8 ALT_IO48_HMC_MMR_SIDEBAND8
volatile
ALT_IO48_HMC_MMR_SIDEBAND9_t
sideband9 ALT_IO48_HMC_MMR_SIDEBAND9
volatile
ALT_IO48_HMC_MMR_SIDEBAND10_t
sideband10 ALT_IO48_HMC_MMR_SIDEBAND10
volatile
ALT_IO48_HMC_MMR_SIDEBAND11_t
sideband11 ALT_IO48_HMC_MMR_SIDEBAND11
volatile
ALT_IO48_HMC_MMR_SIDEBAND12_t
sideband12 ALT_IO48_HMC_MMR_SIDEBAND12
volatile
ALT_IO48_HMC_MMR_SIDEBAND13_t
sideband13 ALT_IO48_HMC_MMR_SIDEBAND13
volatile
ALT_IO48_HMC_MMR_SIDEBAND14_t
sideband14 ALT_IO48_HMC_MMR_SIDEBAND14
volatile
ALT_IO48_HMC_MMR_SIDEBAND15_t
sideband15 ALT_IO48_HMC_MMR_SIDEBAND15
volatile ALT_IO48_HMC_MMR_DRAMSTS_t dramsts ALT_IO48_HMC_MMR_DRAMSTS
volatile ALT_IO48_HMC_MMR_DBGDONE_t dbgdone ALT_IO48_HMC_MMR_DBGDONE
volatile
ALT_IO48_HMC_MMR_DBGSIGNALS_t
dbgsignals ALT_IO48_HMC_MMR_DBGSIGNALS
volatile ALT_IO48_HMC_MMR_DBGRST_t dbgreset ALT_IO48_HMC_MMR_DBGRST
volatile
ALT_IO48_HMC_MMR_DBGMATCH_t
dbgmatch ALT_IO48_HMC_MMR_DBGMATCH
volatile
ALT_IO48_HMC_MMR_CNTR0MSK_t
counter0mask ALT_IO48_HMC_MMR_CNTR0MSK
volatile
ALT_IO48_HMC_MMR_CNTR1MSK_t
counter1mask ALT_IO48_HMC_MMR_CNTR1MSK
volatile
ALT_IO48_HMC_MMR_CNTR0MATCH_t
counter0match ALT_IO48_HMC_MMR_CNTR0MATCH
volatile
ALT_IO48_HMC_MMR_CNTR1MATCH_t
counter1match ALT_IO48_HMC_MMR_CNTR1MATCH
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE0_t
niosreserve0 ALT_IO48_HMC_MMR_NIOSRESERVE0
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE1_t
niosreserve1 ALT_IO48_HMC_MMR_NIOSRESERVE1
volatile
ALT_IO48_HMC_MMR_NIOSRESERVE2_t
niosreserve2 ALT_IO48_HMC_MMR_NIOSRESERVE2
volatile uint32_t _pad_0x11c_0x1000 UNDEFINED
struct ALT_IO48_HMC_MMR_raw_s

The struct declaration for the raw register contents of register group ALT_IO48_HMC_MMR.

Data Fields
volatile uint32_t dbgcfg0 ALT_IO48_HMC_MMR_DBGCFG0
volatile uint32_t dbgcfg1 ALT_IO48_HMC_MMR_DBGCFG1
volatile uint32_t dbgcfg2 ALT_IO48_HMC_MMR_DBGCFG2
volatile uint32_t dbgcfg3 ALT_IO48_HMC_MMR_DBGCFG3
volatile uint32_t dbgcfg4 ALT_IO48_HMC_MMR_DBGCFG4
volatile uint32_t dbgcfg5 ALT_IO48_HMC_MMR_DBGCFG5
volatile uint32_t dbgcfg6 ALT_IO48_HMC_MMR_DBGCFG6
volatile uint32_t reserve0 ALT_IO48_HMC_MMR_RESERVE0
volatile uint32_t reserve1 ALT_IO48_HMC_MMR_RESERVE1
volatile uint32_t reserve2 ALT_IO48_HMC_MMR_RESERVE2
volatile uint32_t ctrlcfg0 ALT_IO48_HMC_MMR_CTLCFG0
volatile uint32_t ctrlcfg1 ALT_IO48_HMC_MMR_CTLCFG1
volatile uint32_t ctrlcfg2 ALT_IO48_HMC_MMR_CTLCFG2
volatile uint32_t ctrlcfg3 ALT_IO48_HMC_MMR_CTLCFG3
volatile uint32_t ctrlcfg4 ALT_IO48_HMC_MMR_CTLCFG4
volatile uint32_t ctrlcfg5 ALT_IO48_HMC_MMR_CTLCFG5
volatile uint32_t ctrlcfg6 ALT_IO48_HMC_MMR_CTLCFG6
volatile uint32_t ctrlcfg7 ALT_IO48_HMC_MMR_CTLCFG7
volatile uint32_t ctrlcfg8 ALT_IO48_HMC_MMR_CTLCFG8
volatile uint32_t ctrlcfg9 ALT_IO48_HMC_MMR_CTLCFG9
volatile uint32_t dramtiming0 ALT_IO48_HMC_MMR_DRAMTIMING0
volatile uint32_t dramodt0 ALT_IO48_HMC_MMR_DRAMODT0
volatile uint32_t dramodt1 ALT_IO48_HMC_MMR_DRAMODT1
volatile uint32_t sbcfg0 ALT_IO48_HMC_MMR_SBCFG0
volatile uint32_t sbcfg1 ALT_IO48_HMC_MMR_SBCFG1
volatile uint32_t sbcfg2 ALT_IO48_HMC_MMR_SBCFG2
volatile uint32_t sbcfg3 ALT_IO48_HMC_MMR_SBCFG3
volatile uint32_t sbcfg4 ALT_IO48_HMC_MMR_SBCFG4
volatile uint32_t sbcfg5 ALT_IO48_HMC_MMR_SBCFG5
volatile uint32_t sbcfg6 ALT_IO48_HMC_MMR_SBCFG6
volatile uint32_t sbcfg7 ALT_IO48_HMC_MMR_SBCFG7
volatile uint32_t caltiming0 ALT_IO48_HMC_MMR_CALTIMING0
volatile uint32_t caltiming1 ALT_IO48_HMC_MMR_CALTIMING1
volatile uint32_t caltiming2 ALT_IO48_HMC_MMR_CALTIMING2
volatile uint32_t caltiming3 ALT_IO48_HMC_MMR_CALTIMING3
volatile uint32_t caltiming4 ALT_IO48_HMC_MMR_CALTIMING4
volatile uint32_t caltiming5 ALT_IO48_HMC_MMR_CALTIMING5
volatile uint32_t caltiming6 ALT_IO48_HMC_MMR_CALTIMING6
volatile uint32_t caltiming7 ALT_IO48_HMC_MMR_CALTIMING7
volatile uint32_t caltiming8 ALT_IO48_HMC_MMR_CALTIMING8
volatile uint32_t caltiming9 ALT_IO48_HMC_MMR_CALTIMING9
volatile uint32_t caltiming10 ALT_IO48_HMC_MMR_CALTIMING10
volatile uint32_t dramaddrw ALT_IO48_HMC_MMR_DRAMADDRW
volatile uint32_t sideband0 ALT_IO48_HMC_MMR_SIDEBAND0
volatile uint32_t sideband1 ALT_IO48_HMC_MMR_SIDEBAND1
volatile uint32_t sideband2 ALT_IO48_HMC_MMR_SIDEBAND2
volatile uint32_t sideband3 ALT_IO48_HMC_MMR_SIDEBAND3
volatile uint32_t sideband4 ALT_IO48_HMC_MMR_SIDEBAND4
volatile uint32_t sideband5 ALT_IO48_HMC_MMR_SIDEBAND5
volatile uint32_t sideband6 ALT_IO48_HMC_MMR_SIDEBAND6
volatile uint32_t sideband7 ALT_IO48_HMC_MMR_SIDEBAND7
volatile uint32_t sideband8 ALT_IO48_HMC_MMR_SIDEBAND8
volatile uint32_t sideband9 ALT_IO48_HMC_MMR_SIDEBAND9
volatile uint32_t sideband10 ALT_IO48_HMC_MMR_SIDEBAND10
volatile uint32_t sideband11 ALT_IO48_HMC_MMR_SIDEBAND11
volatile uint32_t sideband12 ALT_IO48_HMC_MMR_SIDEBAND12
volatile uint32_t sideband13 ALT_IO48_HMC_MMR_SIDEBAND13
volatile uint32_t sideband14 ALT_IO48_HMC_MMR_SIDEBAND14
volatile uint32_t sideband15 ALT_IO48_HMC_MMR_SIDEBAND15
volatile uint32_t dramsts ALT_IO48_HMC_MMR_DRAMSTS
volatile uint32_t dbgdone ALT_IO48_HMC_MMR_DBGDONE
volatile uint32_t dbgsignals ALT_IO48_HMC_MMR_DBGSIGNALS
volatile uint32_t dbgreset ALT_IO48_HMC_MMR_DBGRST
volatile uint32_t dbgmatch ALT_IO48_HMC_MMR_DBGMATCH
volatile uint32_t counter0mask ALT_IO48_HMC_MMR_CNTR0MSK
volatile uint32_t counter1mask ALT_IO48_HMC_MMR_CNTR1MSK
volatile uint32_t counter0match ALT_IO48_HMC_MMR_CNTR0MATCH
volatile uint32_t counter1match ALT_IO48_HMC_MMR_CNTR1MATCH
volatile uint32_t niosreserve0 ALT_IO48_HMC_MMR_NIOSRESERVE0
volatile uint32_t niosreserve1 ALT_IO48_HMC_MMR_NIOSRESERVE1
volatile uint32_t niosreserve2 ALT_IO48_HMC_MMR_NIOSRESERVE2
volatile uint32_t _pad_0x11c_0x1000 UNDEFINED

Typedef Documentation

The typedef declaration for register group ALT_IO48_HMC_MMR.

The typedef declaration for the raw register contents of register group ALT_IO48_HMC_MMR.