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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Name: I2C Interrupt Status Register
Size: 14 bits
Address Offset: 0x2C
Read/Write Access: Read
Each bit in this register has a corresponding mask bit
in the IC_INTR_MASK register. These bits are cleared by reading the matching
interrupt clear register. The unmasked raw versions of these bits are
available in the IC_RAW_INTR_STAT register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_UNDER |
[1] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_OVER |
[2] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_FULL |
[3] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_OVER |
[4] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_EMPTY |
[5] | R | 0x0 | ALT_I2C_INTR_STAT_R_RD_REQ |
[6] | R | 0x0 | ALT_I2C_INTR_STAT_R_TX_ABRT |
[7] | R | 0x0 | ALT_I2C_INTR_STAT_R_RX_DONE |
[8] | R | 0x0 | ALT_I2C_INTR_STAT_R_ACTIVITY |
[9] | R | 0x0 | ALT_I2C_INTR_STAT_R_STOP_DET |
[10] | R | 0x0 | ALT_I2C_INTR_STAT_R_START_DET |
[11] | R | 0x0 | ALT_I2C_INTR_STAT_R_GEN_CALL |
[12] | R | 0x0 | ALT_I2C_INTR_STAT_R_RESTART_DET |
[13] | R | 0x0 | ALT_I2C_INTR_STAT_R_MST_ON_HOLD |
[31:14] | ??? | 0x0 | UNDEFINED |
Field : r_rx_under | |
Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001) |
Field : r_rx_over | |
Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. NOTE: If the parameter IC_RX_FULL_HLD_BUS_EN=1, then the RX_OVER interrupt is never set to 1, because the criteria to set this interrupt are never met. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002) |
Field : r_rx_full | |
Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004) |
Field : r_tx_over | |
Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008) |
Field : r_tx_empty | |
The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010) |
Field : r_rd_req | |
This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020) |
Field : r_tx_abrt | |
This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The DW_apb_i2c flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040) |
Field : r_rx_done | |
When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080) |
Field : r_activity | |
This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it:
Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100) |
Field : r_stop_det | |
The behavior of the STOP_DET interrupt status differs based on the STOP_DET_IFADDRESSED selection in the IC_CON register When STOP_DET_IFADDRESSED =0 : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In slave mode, a STOP_DET interrupt is generated irrespective of whether the slave is addressed or not. When STOP_DET_IFADDRESSED = 1 : In Master Mode (MASTER_MODE = 1'b1), indicates a STOP condition has occured on the I2C interface. In Slave Mode (MASTER_MODE = 1'b0),STOP_DET interrupt is generated only if the slave is addressed. NOTE: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IFADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200) |
Field : r_start_det | |
Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_START_DET_LSB 10 |
#define | ALT_I2C_INTR_STAT_R_START_DET_MSB 10 |
#define | ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 |
#define | ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff |
#define | ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400) |
Field : r_gen_call | |
Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800) |
Field : r_restart_det | |
Indicates a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in slave mode and addressed. This feature is avaliable only when IC_SLV_RESTART_DET_EN is enabled. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_LSB 12 |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_MSB 12 |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000 |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_I2C_INTR_STAT_R_RESTART_DET_SET(value) (((value) << 12) & 0x00001000) |
Field : r_master_on_hold | |
Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_LSB 13 |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_MSB 13 |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_WIDTH 1 |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET_MSK 0x00002000 |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_CLR_MSK 0xffffdfff |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_RESET 0x0 |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET(value) (((value) << 13) & 0x00002000) |
Data Structures | |
struct | ALT_I2C_INTR_STAT_s |
Macros | |
#define | ALT_I2C_INTR_STAT_RESET 0x00000000 |
#define | ALT_I2C_INTR_STAT_OFST 0x2c |
#define | ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) |
Typedefs | |
typedef struct ALT_I2C_INTR_STAT_s | ALT_I2C_INTR_STAT_t |
struct ALT_I2C_INTR_STAT_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_INTR_STAT.
Data Fields | ||
---|---|---|
const uint32_t | r_rx_under: 1 | ALT_I2C_INTR_STAT_R_RX_UNDER |
const uint32_t | r_rx_over: 1 | ALT_I2C_INTR_STAT_R_RX_OVER |
const uint32_t | r_rx_full: 1 | ALT_I2C_INTR_STAT_R_RX_FULL |
const uint32_t | r_tx_over: 1 | ALT_I2C_INTR_STAT_R_TX_OVER |
const uint32_t | r_tx_empty: 1 | ALT_I2C_INTR_STAT_R_TX_EMPTY |
const uint32_t | r_rd_req: 1 | ALT_I2C_INTR_STAT_R_RD_REQ |
const uint32_t | r_tx_abrt: 1 | ALT_I2C_INTR_STAT_R_TX_ABRT |
const uint32_t | r_rx_done: 1 | ALT_I2C_INTR_STAT_R_RX_DONE |
const uint32_t | r_activity: 1 | ALT_I2C_INTR_STAT_R_ACTIVITY |
const uint32_t | r_stop_det: 1 | ALT_I2C_INTR_STAT_R_STOP_DET |
const uint32_t | r_start_det: 1 | ALT_I2C_INTR_STAT_R_START_DET |
const uint32_t | r_gen_call: 1 | ALT_I2C_INTR_STAT_R_GEN_CALL |
const uint32_t | r_restart_det: 1 | ALT_I2C_INTR_STAT_R_RESTART_DET |
const uint32_t | r_master_on_hold: 1 | ALT_I2C_INTR_STAT_R_MST_ON_HOLD |
uint32_t | __pad0__: 18 | UNDEFINED |
#define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_UNDER register field.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RX_UNDER register field.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001 |
The mask used to set the ALT_I2C_INTR_STAT_R_RX_UNDER register field value.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_I2C_INTR_STAT_R_RX_UNDER register field value.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RX_UNDER register field.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_I2C_INTR_STAT_R_RX_UNDER field value from a register.
#define ALT_I2C_INTR_STAT_R_RX_UNDER_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_I2C_INTR_STAT_R_RX_UNDER register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field.
#define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_OVER register field.
#define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RX_OVER register field.
#define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002 |
The mask used to set the ALT_I2C_INTR_STAT_R_RX_OVER register field value.
#define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_I2C_INTR_STAT_R_RX_OVER register field value.
#define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RX_OVER register field.
#define ALT_I2C_INTR_STAT_R_RX_OVER_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_I2C_INTR_STAT_R_RX_OVER field value from a register.
#define ALT_I2C_INTR_STAT_R_RX_OVER_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_I2C_INTR_STAT_R_RX_OVER register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field.
#define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_FULL register field.
#define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RX_FULL register field.
#define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004 |
The mask used to set the ALT_I2C_INTR_STAT_R_RX_FULL register field value.
#define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_I2C_INTR_STAT_R_RX_FULL register field value.
#define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RX_FULL register field.
#define ALT_I2C_INTR_STAT_R_RX_FULL_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_I2C_INTR_STAT_R_RX_FULL field value from a register.
#define ALT_I2C_INTR_STAT_R_RX_FULL_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_I2C_INTR_STAT_R_RX_FULL register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field.
#define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_OVER register field.
#define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_TX_OVER register field.
#define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008 |
The mask used to set the ALT_I2C_INTR_STAT_R_TX_OVER register field value.
#define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_I2C_INTR_STAT_R_TX_OVER register field value.
#define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_TX_OVER register field.
#define ALT_I2C_INTR_STAT_R_TX_OVER_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_I2C_INTR_STAT_R_TX_OVER field value from a register.
#define ALT_I2C_INTR_STAT_R_TX_OVER_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_I2C_INTR_STAT_R_TX_OVER register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010 |
The mask used to set the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef |
The mask used to clear the ALT_I2C_INTR_STAT_R_TX_EMPTY register field value.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_TX_EMPTY register field.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_I2C_INTR_STAT_R_TX_EMPTY field value from a register.
#define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_I2C_INTR_STAT_R_TX_EMPTY register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field.
#define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RD_REQ register field.
#define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RD_REQ register field.
#define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020 |
The mask used to set the ALT_I2C_INTR_STAT_R_RD_REQ register field value.
#define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_I2C_INTR_STAT_R_RD_REQ register field value.
#define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RD_REQ register field.
#define ALT_I2C_INTR_STAT_R_RD_REQ_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_I2C_INTR_STAT_R_RD_REQ field value from a register.
#define ALT_I2C_INTR_STAT_R_RD_REQ_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_I2C_INTR_STAT_R_RD_REQ register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_TX_ABRT register field.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_TX_ABRT register field.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040 |
The mask used to set the ALT_I2C_INTR_STAT_R_TX_ABRT register field value.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_I2C_INTR_STAT_R_TX_ABRT register field value.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_TX_ABRT register field.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_I2C_INTR_STAT_R_TX_ABRT field value from a register.
#define ALT_I2C_INTR_STAT_R_TX_ABRT_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_I2C_INTR_STAT_R_TX_ABRT register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field.
#define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RX_DONE register field.
#define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RX_DONE register field.
#define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080 |
The mask used to set the ALT_I2C_INTR_STAT_R_RX_DONE register field value.
#define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_I2C_INTR_STAT_R_RX_DONE register field value.
#define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RX_DONE register field.
#define ALT_I2C_INTR_STAT_R_RX_DONE_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_I2C_INTR_STAT_R_RX_DONE field value from a register.
#define ALT_I2C_INTR_STAT_R_RX_DONE_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_I2C_INTR_STAT_R_RX_DONE register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_ACTIVITY register field.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_ACTIVITY register field.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100 |
The mask used to set the ALT_I2C_INTR_STAT_R_ACTIVITY register field value.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_I2C_INTR_STAT_R_ACTIVITY register field value.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_ACTIVITY register field.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_I2C_INTR_STAT_R_ACTIVITY field value from a register.
#define ALT_I2C_INTR_STAT_R_ACTIVITY_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_I2C_INTR_STAT_R_ACTIVITY register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field.
#define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_STOP_DET register field.
#define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_STOP_DET register field.
#define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200 |
The mask used to set the ALT_I2C_INTR_STAT_R_STOP_DET register field value.
#define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_I2C_INTR_STAT_R_STOP_DET register field value.
#define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_STOP_DET register field.
#define ALT_I2C_INTR_STAT_R_STOP_DET_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_I2C_INTR_STAT_R_STOP_DET field value from a register.
#define ALT_I2C_INTR_STAT_R_STOP_DET_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_I2C_INTR_STAT_R_STOP_DET register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_START_DET_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field.
#define ALT_I2C_INTR_STAT_R_START_DET_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_START_DET register field.
#define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_START_DET register field.
#define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400 |
The mask used to set the ALT_I2C_INTR_STAT_R_START_DET register field value.
#define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_I2C_INTR_STAT_R_START_DET register field value.
#define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_START_DET register field.
#define ALT_I2C_INTR_STAT_R_START_DET_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_I2C_INTR_STAT_R_START_DET field value from a register.
#define ALT_I2C_INTR_STAT_R_START_DET_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_I2C_INTR_STAT_R_START_DET register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_GEN_CALL register field.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_GEN_CALL register field.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800 |
The mask used to set the ALT_I2C_INTR_STAT_R_GEN_CALL register field value.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_I2C_INTR_STAT_R_GEN_CALL register field value.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_GEN_CALL register field.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_I2C_INTR_STAT_R_GEN_CALL field value from a register.
#define ALT_I2C_INTR_STAT_R_GEN_CALL_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_I2C_INTR_STAT_R_GEN_CALL register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_RESTART_DET register field.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_RESTART_DET register field.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_RESTART_DET register field.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_SET_MSK 0x00001000 |
The mask used to set the ALT_I2C_INTR_STAT_R_RESTART_DET register field value.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_CLR_MSK 0xffffefff |
The mask used to clear the ALT_I2C_INTR_STAT_R_RESTART_DET register field value.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_RESTART_DET register field.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_I2C_INTR_STAT_R_RESTART_DET field value from a register.
#define ALT_I2C_INTR_STAT_R_RESTART_DET_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_I2C_INTR_STAT_R_RESTART_DET register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_WIDTH 1 |
The width in bits of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET_MSK 0x00002000 |
The mask used to set the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_RESET 0x0 |
The reset value of the ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_I2C_INTR_STAT_R_MST_ON_HOLD field value from a register.
#define ALT_I2C_INTR_STAT_R_MST_ON_HOLD_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_I2C_INTR_STAT_R_MST_ON_HOLD register field value suitable for setting the register.
#define ALT_I2C_INTR_STAT_RESET 0x00000000 |
The reset value of the ALT_I2C_INTR_STAT register.
#define ALT_I2C_INTR_STAT_OFST 0x2c |
The byte offset of the ALT_I2C_INTR_STAT register from the beginning of the component.
#define ALT_I2C_INTR_STAT_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST)) |
The address of the ALT_I2C_INTR_STAT register.
typedef struct ALT_I2C_INTR_STAT_s ALT_I2C_INTR_STAT_t |
The typedef declaration for register ALT_I2C_INTR_STAT.