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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The CTRL register is used by software to control reset behavior.It includes fields for software to initiate the cold and warm reset, enable hardware handshake with other modules before warm reset, and perform software handshake. The software handshake sequence must match the hardware sequence. Software mustde-assert the handshake request after asserting warm reset and before de- assert the warm reset.
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | SDRAM Self-Refresh Request |
[1] | RW | 0x0 | FPGA Manager Handshake Request |
[2] | RW | 0x0 | FPGA Handshake Request |
[3] | RW | 0x0 | ETR (Embedded Trace Router) Stall Request |
[31:4] | ??? | Unknown | UNDEFINED |
Field : SDRAM Self-Refresh Request - sdrselfrefreq | |
Software writes this field 1 to request to the SDRAM Controller Subsystem that it puts the SDRAM devices into self-refresh mode. This is done to preserve SDRAM contents across a software warm reset. Software waits for the SDRSELFREFACK to be 1 and then writes this field to 0. Note that it is possible for the SDRAM Controller Subsystem to never assert SDRSELFREFACK so software should timeout if SDRSELFREFACK is never asserted. Field Access Macros: | |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0 |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0 |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1 |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001 |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0 |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET(value) (((value) << 0) & 0x00000001) |
Field : FPGA Manager Handshake Request - fpgamgrhsreq | |
Software writes this field 1 to request to the FPGA Manager to idle its output clock. Software waits for the FPGAMGRHSACK to be 1 and then writes this field to 0. Note that it is possible for the FPGA Manager to never assert FPGAMGRHSACK so software should timeout in this case. Field Access Macros: | |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_LSB 1 |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_MSB 1 |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_WIDTH 1 |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET_MSK 0x00000002 |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_CLR_MSK 0xfffffffd |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_RESET 0x0 |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET(value) (((value) << 1) & 0x00000002) |
Field : FPGA Handshake Request - fpgahsreq | |
Software writes this field 1 to initiate handshake request to FPGA . Software waits for the FPGAHSACK to be active and then writes this field to 0. Note that it is possible for the FPGA to never assert FPGAHSACK so software should timeout in this case. Field Access Macros: | |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2 |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2 |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1 |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004 |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0 |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET(value) (((value) << 2) & 0x00000004) |
Field : ETR (Embedded Trace Router) Stall Request - etrstallreq | |
Software writes this field 1 to request to the ETR that it stalls its AXI master to the L3 Interconnect. Software waits for the ETRSTALLACK to be 1 and then writes this field to 0. Note that it is possible for the ETR to never assert ETRSTALLACK so software should timeout if ETRSTALLACK is never asserted. Field Access Macros: | |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0 |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET(value) (((value) << 3) & 0x00000008) |
Data Structures | |
struct | ALT_RSTMGR_HDSKREQ_s |
Macros | |
#define | ALT_RSTMGR_HDSKREQ_RESET 0x00100000 |
#define | ALT_RSTMGR_HDSKREQ_OFST 0x14 |
Typedefs | |
typedef struct ALT_RSTMGR_HDSKREQ_s | ALT_RSTMGR_HDSKREQ_t |
struct ALT_RSTMGR_HDSKREQ_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_RSTMGR_HDSKREQ.
Data Fields | ||
---|---|---|
uint32_t | sdrselfrefreq: 1 | SDRAM Self-Refresh Request |
uint32_t | fpgamgrhsreq: 1 | FPGA Manager Handshake Request |
uint32_t | fpgahsreq: 1 | FPGA Handshake Request |
uint32_t | etrstallreq: 1 | ETR (Embedded Trace Router) Stall Request |
uint32_t | __pad0__: 28 | UNDEFINED |
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_WIDTH 1 |
The width in bits of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET_MSK 0x00000001 |
The mask used to set the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_RESET 0x0 |
The reset value of the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ field value from a register.
#define ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_RSTMGR_HDSKREQ_SDRSELFREFREQ register field value suitable for setting the register.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_WIDTH 1 |
The width in bits of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET_MSK 0x00000002 |
The mask used to set the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_RESET 0x0 |
The reset value of the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ field value from a register.
#define ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_RSTMGR_HDSKREQ_FPGAMGRHSREQ register field value suitable for setting the register.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_WIDTH 1 |
The width in bits of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET_MSK 0x00000004 |
The mask used to set the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_RESET 0x0 |
The reset value of the ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_RSTMGR_HDSKREQ_FPGAHSREQ field value from a register.
#define ALT_RSTMGR_HDSKREQ_FPGAHSREQ_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_RSTMGR_HDSKREQ_FPGAHSREQ register field value suitable for setting the register.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_WIDTH 1 |
The width in bits of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET_MSK 0x00000008 |
The mask used to set the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_RESET 0x0 |
The reset value of the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_RSTMGR_HDSKREQ_ETRSTALLREQ field value from a register.
#define ALT_RSTMGR_HDSKREQ_ETRSTALLREQ_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_RSTMGR_HDSKREQ_ETRSTALLREQ register field value suitable for setting the register.
#define ALT_RSTMGR_HDSKREQ_RESET 0x00100000 |
The reset value of the ALT_RSTMGR_HDSKREQ register.
#define ALT_RSTMGR_HDSKREQ_OFST 0x14 |
The byte offset of the ALT_RSTMGR_HDSKREQ register from the beginning of the component.
typedef struct ALT_RSTMGR_HDSKREQ_s ALT_RSTMGR_HDSKREQ_t |
The typedef declaration for register ALT_RSTMGR_HDSKREQ.