Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ctrlcfg1

Description

Register Layout

Bits Access Reset Description
[4:0] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN
[6:5] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER
[7] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC
[8] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC
[9] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC
[10] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC
[11] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC
[12] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA
[13] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA
[14] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA
[15] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA
[16] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA
[17] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA
[18] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD
[24:19] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT
[25] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN
[26] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM
[27] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM
[28] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM
[29] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM
[30] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM
[31] ??? 0x0 UNDEFINED

Field : cfg_dbc3_burst_length

Configures burst length for DBC3. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_LSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_MSB   4
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET_MSK   0x0000001f
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_CLR_MSK   0xffffffe0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_GET(value)   (((value) & 0x0000001f) >> 0)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET(value)   (((value) << 0) & 0x0000001f)
 

Field : cfg_addr_order

Selects the order for address interleaving. Programming this field with different values gives different mappings between the AXI or Avalon-MM address and the SDRAM address. Program this field with the following binary values to select the ordering. "00" - chip, row, bank(BG, BA), column; "01" - chip, bank(BG, BA), row, column; "10"-row, chip, bank(BG, BA), column;

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_LSB   5
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_MSB   6
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_WIDTH   2
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET_MSK   0x00000060
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_CLR_MSK   0xffffff9f
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_GET(value)   (((value) & 0x00000060) >> 5)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET(value)   (((value) << 5) & 0x00000060)
 

Field : cfg_ctrl_enable_ecc

Enable the generation and checking of ECC.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_LSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_MSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET_MSK   0x00000080
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_CLR_MSK   0xffffff7f
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET(value)   (((value) << 7) & 0x00000080)
 

Field : cfg_dbc0_enable_ecc

Enable the generation and checking of ECC.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_LSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_MSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET_MSK   0x00000100
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_CLR_MSK   0xfffffeff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET(value)   (((value) << 8) & 0x00000100)
 

Field : cfg_dbc1_enable_ecc

Enable the generation and checking of ECC.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_LSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_MSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET_MSK   0x00000200
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_CLR_MSK   0xfffffdff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET(value)   (((value) << 9) & 0x00000200)
 

Field : cfg_dbc2_enable_ecc

Enable the generation and checking of ECC.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_LSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_MSB   10
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET_MSK   0x00000400
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_CLR_MSK   0xfffffbff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET(value)   (((value) << 10) & 0x00000400)
 

Field : cfg_dbc3_enable_ecc

Enable the generation and checking of ECC.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_LSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_MSB   11
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET_MSK   0x00000800
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_CLR_MSK   0xfffff7ff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET(value)   (((value) << 11) & 0x00000800)
 

Field : cfg_reorder_data

This bit controls whether the controller can re-order operations to optimize SDRAM bandwidth. It should generally be set to a one.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_LSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_MSB   12
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET_MSK   0x00001000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_CLR_MSK   0xffffefff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET(value)   (((value) << 12) & 0x00001000)
 

Field : cfg_ctrl_reorder_rdata

This bit controls whether the controller need to re-order the read return data.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_LSB   13
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_MSB   13
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET_MSK   0x00002000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_CLR_MSK   0xffffdfff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET(value)   (((value) << 13) & 0x00002000)
 

Field : cfg_dbc0_reorder_rdata

This bit controls whether the controller need to re-order the read return data.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_LSB   14
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_MSB   14
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK   0x00004000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK   0xffffbfff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET(value)   (((value) << 14) & 0x00004000)
 

Field : cfg_dbc1_reorder_rdata

This bit controls whether the controller need to re-order the read return data.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_LSB   15
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_MSB   15
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK   0x00008000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK   0xffff7fff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET(value)   (((value) << 15) & 0x00008000)
 

Field : cfg_dbc2_reorder_rdata

This bit controls whether the controller need to re-order the read return data.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_LSB   16
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_MSB   16
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK   0x00010000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK   0xfffeffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET(value)   (((value) << 16) & 0x00010000)
 

Field : cfg_dbc3_reorder_rdata

This bit controls whether the controller need to re-order the read return data.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_LSB   17
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_MSB   17
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK   0x00020000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK   0xfffdffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET(value)   (((value) << 17) & 0x00020000)
 

Field : cfg_reorder_read

This bit controls whether the controller can re-order read command to. 1

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_LSB   18
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_MSB   18
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET_MSK   0x00040000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_CLR_MSK   0xfffbffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET(value)   (((value) << 18) & 0x00040000)
 

Field : cfg_starve_limit

Specifies the number of DRAM burst transactions an individual transaction will allow to reorder ahead of it before its priority is raised in the memory controller.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_LSB   19
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_MSB   24
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_WIDTH   6
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET_MSK   0x01f80000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_CLR_MSK   0xfe07ffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_GET(value)   (((value) & 0x01f80000) >> 19)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET(value)   (((value) << 19) & 0x01f80000)
 

Field : cfg_dqstrk_en

Enables DQS tracking in the PHY.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_LSB   25
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_MSB   25
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET_MSK   0x02000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_CLR_MSK   0xfdffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET(value)   (((value) << 25) & 0x02000000)
 

Field : cfg_ctrl_enable_dm

Set to a one to enable DRAM operation if DM pins are connected.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_LSB   26
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_MSB   26
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET_MSK   0x04000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_CLR_MSK   0xfbffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET(value)   (((value) << 26) & 0x04000000)
 

Field : cfg_dbc0_enable_dm

Set to a one to enable DRAM operation if DM pins are connected.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_LSB   27
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_MSB   27
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET_MSK   0x08000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_CLR_MSK   0xf7ffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET(value)   (((value) << 27) & 0x08000000)
 

Field : cfg_dbc1_enable_dm

Set to a one to enable DRAM operation if DM pins are connected.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_LSB   28
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_MSB   28
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET_MSK   0x10000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_CLR_MSK   0xefffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_GET(value)   (((value) & 0x10000000) >> 28)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET(value)   (((value) << 28) & 0x10000000)
 

Field : cfg_dbc2_enable_dm

Set to a one to enable DRAM operation if DM pins are connected.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_LSB   29
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_MSB   29
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET_MSK   0x20000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_CLR_MSK   0xdfffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_GET(value)   (((value) & 0x20000000) >> 29)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET(value)   (((value) << 29) & 0x20000000)
 

Field : cfg_dbc3_enable_dm

Set to a one to enable DRAM operation if DM pins are connected.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_LSB   30
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_MSB   30
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_WIDTH   1
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET_MSK   0x40000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_CLR_MSK   0xbfffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET(value)   (((value) << 30) & 0x40000000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CTLCFG1_s
 

Macros

#define ALT_IO48_HMC_MMR_CTLCFG1_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CTLCFG1_OFST   0x2c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CTLCFG1_s 
ALT_IO48_HMC_MMR_CTLCFG1_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CTLCFG1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG1.

Data Fields
uint32_t cfg_dbc3_burst_length: 5 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN
uint32_t cfg_addr_order: 2 ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER
uint32_t cfg_ctrl_enable_ecc: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC
uint32_t cfg_dbc0_enable_ecc: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC
uint32_t cfg_dbc1_enable_ecc: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC
uint32_t cfg_dbc2_enable_ecc: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC
uint32_t cfg_dbc3_enable_ecc: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC
uint32_t cfg_reorder_data: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA
uint32_t cfg_ctrl_reorder_rdata: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA
uint32_t cfg_dbc0_reorder_rdata: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA
uint32_t cfg_dbc1_reorder_rdata: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA
uint32_t cfg_dbc2_reorder_rdata: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA
uint32_t cfg_dbc3_reorder_rdata: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA
uint32_t cfg_reorder_read: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD
uint32_t cfg_starve_limit: 6 ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT
uint32_t cfg_dqstrk_en: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN
uint32_t cfg_ctrl_enable_dm: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM
uint32_t cfg_dbc0_enable_dm: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM
uint32_t cfg_dbc1_enable_dm: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM
uint32_t cfg_dbc2_enable_dm: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM
uint32_t cfg_dbc3_enable_dm: 1 ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM
uint32_t __pad0__: 1 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_MSB   4

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET_MSK   0x0000001f

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_CLR_MSK   0xffffffe0

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_GET (   value)    (((value) & 0x0000001f) >> 0)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN_SET (   value)    (((value) << 0) & 0x0000001f)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_BURST_LEN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_LSB   5

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_MSB   6

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET_MSK   0x00000060

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_CLR_MSK   0xffffff9f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_GET (   value)    (((value) & 0x00000060) >> 5)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER_SET (   value)    (((value) << 5) & 0x00000060)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_ADDR_ORDER register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_LSB   7

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_MSB   7

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET_MSK   0x00000080

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_CLR_MSK   0xffffff7f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_ECC register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_LSB   8

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET_MSK   0x00000100

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_CLR_MSK   0xfffffeff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_ECC register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_MSB   9

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET_MSK   0x00000200

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_CLR_MSK   0xfffffdff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_ECC register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_LSB   10

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_MSB   10

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET_MSK   0x00000400

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_CLR_MSK   0xfffffbff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_ECC register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_LSB   11

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_MSB   11

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET_MSK   0x00000800

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_ECC register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_LSB   12

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_MSB   12

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET_MSK   0x00001000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_CLR_MSK   0xffffefff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_DATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_LSB   13

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_MSB   13

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET_MSK   0x00002000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_CLR_MSK   0xffffdfff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_REORDER_RDATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_LSB   14

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_MSB   14

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET_MSK   0x00004000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_CLR_MSK   0xffffbfff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_REORDER_RDATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_LSB   15

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET_MSK   0x00008000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_CLR_MSK   0xffff7fff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_REORDER_RDATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_MSB   16

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET_MSK   0x00010000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_CLR_MSK   0xfffeffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_REORDER_RDATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_LSB   17

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_MSB   17

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET_MSK   0x00020000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_CLR_MSK   0xfffdffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_REORDER_RDATA register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_LSB   18

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_MSB   18

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET_MSK   0x00040000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_CLR_MSK   0xfffbffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_REORDER_RD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_LSB   19

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_MSB   24

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET_MSK   0x01f80000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_CLR_MSK   0xfe07ffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_GET (   value)    (((value) & 0x01f80000) >> 19)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT_SET (   value)    (((value) << 19) & 0x01f80000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_STARVE_LIMIT register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_LSB   25

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_MSB   25

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET_MSK   0x02000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_CLR_MSK   0xfdffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DQSTRK_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_LSB   26

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_MSB   26

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET_MSK   0x04000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_CLR_MSK   0xfbffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_CTL_EN_DM register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_LSB   27

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_MSB   27

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET_MSK   0x08000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC0_EN_DM register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_LSB   28

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_MSB   28

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET_MSK   0x10000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_CLR_MSK   0xefffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_GET (   value)    (((value) & 0x10000000) >> 28)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM_SET (   value)    (((value) << 28) & 0x10000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC1_EN_DM register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_LSB   29

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_MSB   29

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET_MSK   0x20000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_CLR_MSK   0xdfffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_GET (   value)    (((value) & 0x20000000) >> 29)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM_SET (   value)    (((value) << 29) & 0x20000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC2_EN_DM register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_LSB   30

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_MSB   30

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET_MSK   0x40000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_CLR_MSK   0xbfffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG1_CFG_DBC3_EN_DM register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG1_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CTLCFG1 register.

#define ALT_IO48_HMC_MMR_CTLCFG1_OFST   0x2c

The byte offset of the ALT_IO48_HMC_MMR_CTLCFG1 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG1.