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alt_noc_fw_l4_per_scr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
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#define __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_LSB 8
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_MSB 8
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET_MSK 0x00000100
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_LSB 16
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_MSB 16
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_PER_SCR_NAND_REG_s
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{
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uint32_t
mpu_m0
: 1;
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uint32_t : 7;
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uint32_t
dma
: 1;
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uint32_t : 7;
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uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_NAND_REG_s
ALT_NOC_FW_L4_PER_SCR_NAND_REG_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_RESET 0x00000000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_REG_OFST 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_LSB 8
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_MSB 8
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET_MSK 0x00000100
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_LSB 16
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_MSB 16
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
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{
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uint32_t
mpu_m0
: 1;
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uint32_t : 7;
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uint32_t
dma
: 1;
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uint32_t : 7;
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uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_NAND_DATA_s
ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_RESET 0x00000000
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#define ALT_NOC_FW_L4_PER_SCR_NAND_DATA_OFST 0x4
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_LSB 8
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_MSB 8
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET_MSK 0x00000100
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_DMA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_LSB 16
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_MSB 16
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s
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{
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uint32_t
mpu_m0
: 1;
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uint32_t : 7;
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uint32_t
dma
: 1;
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uint32_t : 7;
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uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_s
ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_RESET 0x00000000
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#define ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_OFST 0x8
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_LSB 8
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_MSB 8
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET_MSK 0x00000100
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_LSB 16
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_MSB 16
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_PER_SCR_USB0_REG_s
668
{
669
uint32_t
mpu_m0
: 1;
670
uint32_t : 7;
671
uint32_t
dma
: 1;
672
uint32_t : 7;
673
uint32_t
fpga2soc
: 1;
674
uint32_t : 7;
675
uint32_t
ahb_ap
: 1;
676
uint32_t : 7;
677
};
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typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_USB0_REG_s
ALT_NOC_FW_L4_PER_SCR_USB0_REG_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_RESET 0x00000000
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#define ALT_NOC_FW_L4_PER_SCR_USB0_REG_OFST 0xc
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_LSB 8
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_MSB 8
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_WIDTH 1
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET_MSK 0x00000100
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_CLR_MSK 0xfffffeff
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_RESET 0x0
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_LSB 16
773
774
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_MSB 16
775
776
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_WIDTH 1
777
778
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET_MSK 0x00010000
779
780
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_CLR_MSK 0xfffeffff
781
782
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_RESET 0x0
783
784
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
785
786
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
787
799
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_LSB 24
800
801
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_MSB 24
802
803
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_WIDTH 1
804
805
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET_MSK 0x01000000
806
807
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_CLR_MSK 0xfeffffff
808
809
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_RESET 0x0
810
811
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
812
813
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
814
815
#ifndef __ASSEMBLY__
816
826
struct
ALT_NOC_FW_L4_PER_SCR_USB1_REG_s
827
{
828
uint32_t
mpu_m0
: 1;
829
uint32_t : 7;
830
uint32_t
dma
: 1;
831
uint32_t : 7;
832
uint32_t
fpga2soc
: 1;
833
uint32_t : 7;
834
uint32_t
ahb_ap
: 1;
835
uint32_t : 7;
836
};
837
839
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_USB1_REG_s
ALT_NOC_FW_L4_PER_SCR_USB1_REG_t
;
840
#endif
/* __ASSEMBLY__ */
841
843
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_RESET 0x00000000
844
845
#define ALT_NOC_FW_L4_PER_SCR_USB1_REG_OFST 0x10
846
866
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_LSB 0
867
868
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_MSB 31
869
870
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_WIDTH 32
871
872
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET_MSK 0xffffffff
873
874
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_CLR_MSK 0x00000000
875
876
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_RESET 0x1
877
878
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
879
880
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
881
882
#ifndef __ASSEMBLY__
883
893
struct
ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s
894
{
895
uint32_t
Reserved
: 32;
896
};
897
899
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_s
ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t
;
900
#endif
/* __ASSEMBLY__ */
901
903
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_RESET 0x00000001
904
905
#define ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_OFST 0x14
906
926
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_LSB 0
927
928
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_MSB 31
929
930
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_WIDTH 32
931
932
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET_MSK 0xffffffff
933
934
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_CLR_MSK 0x00000000
935
936
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_RESET 0x0
937
938
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
939
940
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RSVD_SET(value) (((value) << 0) & 0xffffffff)
941
942
#ifndef __ASSEMBLY__
943
953
struct
ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s
954
{
955
uint32_t
Reserved
: 32;
956
};
957
959
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_s
ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t
;
960
#endif
/* __ASSEMBLY__ */
961
963
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_RESET 0x00000000
964
965
#define ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_OFST 0x18
966
997
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_LSB 0
998
999
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_MSB 0
1000
1001
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_WIDTH 1
1002
1003
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET_MSK 0x00000001
1004
1005
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_CLR_MSK 0xfffffffe
1006
1007
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_RESET 0x0
1008
1009
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1010
1011
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1012
1024
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_LSB 8
1025
1026
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_MSB 8
1027
1028
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_WIDTH 1
1029
1030
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET_MSK 0x00000100
1031
1032
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_CLR_MSK 0xfffffeff
1033
1034
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_RESET 0x0
1035
1036
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1037
1038
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_DMA_SET(value) (((value) << 8) & 0x00000100)
1039
1051
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_LSB 16
1052
1053
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_MSB 16
1054
1055
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_WIDTH 1
1056
1057
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET_MSK 0x00010000
1058
1059
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_CLR_MSK 0xfffeffff
1060
1061
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_RESET 0x0
1062
1063
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1064
1065
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_F2H_SET(value) (((value) << 16) & 0x00010000)
1066
1078
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_LSB 24
1079
1080
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_MSB 24
1081
1082
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_WIDTH 1
1083
1084
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET_MSK 0x01000000
1085
1086
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_CLR_MSK 0xfeffffff
1087
1088
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_RESET 0x0
1089
1090
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1091
1092
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1093
1094
#ifndef __ASSEMBLY__
1095
1105
struct
ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s
1106
{
1107
uint32_t
mpu_m0
: 1;
1108
uint32_t : 7;
1109
uint32_t
dma
: 1;
1110
uint32_t : 7;
1111
uint32_t
fpga2soc
: 1;
1112
uint32_t : 7;
1113
uint32_t
ahb_ap
: 1;
1114
uint32_t : 7;
1115
};
1116
1118
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SPI_MST0_s
ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t
;
1119
#endif
/* __ASSEMBLY__ */
1120
1122
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_RESET 0x00000000
1123
1124
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST0_OFST 0x1c
1125
1156
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_LSB 0
1157
1158
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_MSB 0
1159
1160
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_WIDTH 1
1161
1162
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET_MSK 0x00000001
1163
1164
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_CLR_MSK 0xfffffffe
1165
1166
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_RESET 0x0
1167
1168
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1169
1170
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1171
1183
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_LSB 8
1184
1185
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_MSB 8
1186
1187
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_WIDTH 1
1188
1189
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET_MSK 0x00000100
1190
1191
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_CLR_MSK 0xfffffeff
1192
1193
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_RESET 0x0
1194
1195
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1196
1197
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_DMA_SET(value) (((value) << 8) & 0x00000100)
1198
1210
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_LSB 16
1211
1212
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_MSB 16
1213
1214
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_WIDTH 1
1215
1216
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET_MSK 0x00010000
1217
1218
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_CLR_MSK 0xfffeffff
1219
1220
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_RESET 0x0
1221
1222
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1223
1224
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_F2H_SET(value) (((value) << 16) & 0x00010000)
1225
1237
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_LSB 24
1238
1239
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_MSB 24
1240
1241
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_WIDTH 1
1242
1243
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET_MSK 0x01000000
1244
1245
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_CLR_MSK 0xfeffffff
1246
1247
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_RESET 0x0
1248
1249
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1250
1251
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1252
1253
#ifndef __ASSEMBLY__
1254
1264
struct
ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s
1265
{
1266
uint32_t
mpu_m0
: 1;
1267
uint32_t : 7;
1268
uint32_t
dma
: 1;
1269
uint32_t : 7;
1270
uint32_t
fpga2soc
: 1;
1271
uint32_t : 7;
1272
uint32_t
ahb_ap
: 1;
1273
uint32_t : 7;
1274
};
1275
1277
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SPI_MST1_s
ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t
;
1278
#endif
/* __ASSEMBLY__ */
1279
1281
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_RESET 0x00000000
1282
1283
#define ALT_NOC_FW_L4_PER_SCR_SPI_MST1_OFST 0x20
1284
1315
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_LSB 0
1316
1317
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_MSB 0
1318
1319
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_WIDTH 1
1320
1321
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET_MSK 0x00000001
1322
1323
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_CLR_MSK 0xfffffffe
1324
1325
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_RESET 0x0
1326
1327
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1328
1329
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1330
1342
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_LSB 8
1343
1344
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_MSB 8
1345
1346
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_WIDTH 1
1347
1348
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET_MSK 0x00000100
1349
1350
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_CLR_MSK 0xfffffeff
1351
1352
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_RESET 0x0
1353
1354
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1355
1356
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_DMA_SET(value) (((value) << 8) & 0x00000100)
1357
1369
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_LSB 16
1370
1371
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_MSB 16
1372
1373
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_WIDTH 1
1374
1375
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET_MSK 0x00010000
1376
1377
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_CLR_MSK 0xfffeffff
1378
1379
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_RESET 0x0
1380
1381
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1382
1383
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_F2H_SET(value) (((value) << 16) & 0x00010000)
1384
1396
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_LSB 24
1397
1398
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_MSB 24
1399
1400
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_WIDTH 1
1401
1402
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET_MSK 0x01000000
1403
1404
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_CLR_MSK 0xfeffffff
1405
1406
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_RESET 0x0
1407
1408
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1409
1410
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1411
1412
#ifndef __ASSEMBLY__
1413
1423
struct
ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s
1424
{
1425
uint32_t
mpu_m0
: 1;
1426
uint32_t : 7;
1427
uint32_t
dma
: 1;
1428
uint32_t : 7;
1429
uint32_t
fpga2soc
: 1;
1430
uint32_t : 7;
1431
uint32_t
ahb_ap
: 1;
1432
uint32_t : 7;
1433
};
1434
1436
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_s
ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t
;
1437
#endif
/* __ASSEMBLY__ */
1438
1440
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_RESET 0x00000000
1441
1442
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_OFST 0x24
1443
1474
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_LSB 0
1475
1476
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_MSB 0
1477
1478
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_WIDTH 1
1479
1480
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET_MSK 0x00000001
1481
1482
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_CLR_MSK 0xfffffffe
1483
1484
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_RESET 0x0
1485
1486
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1487
1488
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1489
1501
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_LSB 8
1502
1503
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_MSB 8
1504
1505
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_WIDTH 1
1506
1507
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET_MSK 0x00000100
1508
1509
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_CLR_MSK 0xfffffeff
1510
1511
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_RESET 0x0
1512
1513
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1514
1515
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_DMA_SET(value) (((value) << 8) & 0x00000100)
1516
1528
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_LSB 16
1529
1530
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_MSB 16
1531
1532
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_WIDTH 1
1533
1534
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET_MSK 0x00010000
1535
1536
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_CLR_MSK 0xfffeffff
1537
1538
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_RESET 0x0
1539
1540
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1541
1542
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_F2H_SET(value) (((value) << 16) & 0x00010000)
1543
1555
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_LSB 24
1556
1557
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_MSB 24
1558
1559
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_WIDTH 1
1560
1561
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET_MSK 0x01000000
1562
1563
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_CLR_MSK 0xfeffffff
1564
1565
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_RESET 0x0
1566
1567
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1568
1569
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1570
1571
#ifndef __ASSEMBLY__
1572
1582
struct
ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s
1583
{
1584
uint32_t
mpu_m0
: 1;
1585
uint32_t : 7;
1586
uint32_t
dma
: 1;
1587
uint32_t : 7;
1588
uint32_t
fpga2soc
: 1;
1589
uint32_t : 7;
1590
uint32_t
ahb_ap
: 1;
1591
uint32_t : 7;
1592
};
1593
1595
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_s
ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t
;
1596
#endif
/* __ASSEMBLY__ */
1597
1599
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_RESET 0x00000000
1600
1601
#define ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_OFST 0x28
1602
1633
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_LSB 0
1634
1635
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_MSB 0
1636
1637
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_WIDTH 1
1638
1639
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET_MSK 0x00000001
1640
1641
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_CLR_MSK 0xfffffffe
1642
1643
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_RESET 0x0
1644
1645
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1646
1647
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1648
1660
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_LSB 8
1661
1662
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_MSB 8
1663
1664
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_WIDTH 1
1665
1666
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET_MSK 0x00000100
1667
1668
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_CLR_MSK 0xfffffeff
1669
1670
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_RESET 0x0
1671
1672
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_GET(value) (((value) & 0x00000100) >> 8)
1673
1674
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_DMA_SET(value) (((value) << 8) & 0x00000100)
1675
1687
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_LSB 16
1688
1689
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_MSB 16
1690
1691
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_WIDTH 1
1692
1693
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET_MSK 0x00010000
1694
1695
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_CLR_MSK 0xfffeffff
1696
1697
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_RESET 0x0
1698
1699
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_GET(value) (((value) & 0x00010000) >> 16)
1700
1701
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_F2H_SET(value) (((value) << 16) & 0x00010000)
1702
1714
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_LSB 24
1715
1716
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_MSB 24
1717
1718
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_WIDTH 1
1719
1720
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET_MSK 0x01000000
1721
1722
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_CLR_MSK 0xfeffffff
1723
1724
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_RESET 0x0
1725
1726
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1727
1728
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1729
1730
#ifndef __ASSEMBLY__
1731
1741
struct
ALT_NOC_FW_L4_PER_SCR_EMAC0_s
1742
{
1743
uint32_t
mpu_m0
: 1;
1744
uint32_t : 7;
1745
uint32_t
dma
: 1;
1746
uint32_t : 7;
1747
uint32_t
fpga2soc
: 1;
1748
uint32_t : 7;
1749
uint32_t
ahb_ap
: 1;
1750
uint32_t : 7;
1751
};
1752
1754
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_EMAC0_s
ALT_NOC_FW_L4_PER_SCR_EMAC0_t
;
1755
#endif
/* __ASSEMBLY__ */
1756
1758
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_RESET 0x00000000
1759
1760
#define ALT_NOC_FW_L4_PER_SCR_EMAC0_OFST 0x2c
1761
1792
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_LSB 0
1793
1794
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_MSB 0
1795
1796
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_WIDTH 1
1797
1798
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET_MSK 0x00000001
1799
1800
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_CLR_MSK 0xfffffffe
1801
1802
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_RESET 0x0
1803
1804
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1805
1806
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1807
1819
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_LSB 8
1820
1821
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_MSB 8
1822
1823
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_WIDTH 1
1824
1825
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET_MSK 0x00000100
1826
1827
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_CLR_MSK 0xfffffeff
1828
1829
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_RESET 0x0
1830
1831
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_GET(value) (((value) & 0x00000100) >> 8)
1832
1833
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_DMA_SET(value) (((value) << 8) & 0x00000100)
1834
1846
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_LSB 16
1847
1848
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_MSB 16
1849
1850
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_WIDTH 1
1851
1852
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET_MSK 0x00010000
1853
1854
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_CLR_MSK 0xfffeffff
1855
1856
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_RESET 0x0
1857
1858
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_GET(value) (((value) & 0x00010000) >> 16)
1859
1860
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_F2H_SET(value) (((value) << 16) & 0x00010000)
1861
1873
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_LSB 24
1874
1875
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_MSB 24
1876
1877
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_WIDTH 1
1878
1879
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET_MSK 0x01000000
1880
1881
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_CLR_MSK 0xfeffffff
1882
1883
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_RESET 0x0
1884
1885
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1886
1887
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1888
1889
#ifndef __ASSEMBLY__
1890
1900
struct
ALT_NOC_FW_L4_PER_SCR_EMAC1_s
1901
{
1902
uint32_t
mpu_m0
: 1;
1903
uint32_t : 7;
1904
uint32_t
dma
: 1;
1905
uint32_t : 7;
1906
uint32_t
fpga2soc
: 1;
1907
uint32_t : 7;
1908
uint32_t
ahb_ap
: 1;
1909
uint32_t : 7;
1910
};
1911
1913
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_EMAC1_s
ALT_NOC_FW_L4_PER_SCR_EMAC1_t
;
1914
#endif
/* __ASSEMBLY__ */
1915
1917
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_RESET 0x00000000
1918
1919
#define ALT_NOC_FW_L4_PER_SCR_EMAC1_OFST 0x30
1920
1951
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_LSB 0
1952
1953
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_MSB 0
1954
1955
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_WIDTH 1
1956
1957
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET_MSK 0x00000001
1958
1959
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_CLR_MSK 0xfffffffe
1960
1961
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_RESET 0x0
1962
1963
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1964
1965
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1966
1978
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_LSB 8
1979
1980
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_MSB 8
1981
1982
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_WIDTH 1
1983
1984
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET_MSK 0x00000100
1985
1986
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_CLR_MSK 0xfffffeff
1987
1988
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_RESET 0x0
1989
1990
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_GET(value) (((value) & 0x00000100) >> 8)
1991
1992
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_DMA_SET(value) (((value) << 8) & 0x00000100)
1993
2005
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_LSB 16
2006
2007
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_MSB 16
2008
2009
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_WIDTH 1
2010
2011
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET_MSK 0x00010000
2012
2013
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_CLR_MSK 0xfffeffff
2014
2015
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_RESET 0x0
2016
2017
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2018
2019
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_F2H_SET(value) (((value) << 16) & 0x00010000)
2020
2032
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_LSB 24
2033
2034
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_MSB 24
2035
2036
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_WIDTH 1
2037
2038
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET_MSK 0x01000000
2039
2040
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_CLR_MSK 0xfeffffff
2041
2042
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_RESET 0x0
2043
2044
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2045
2046
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2047
2048
#ifndef __ASSEMBLY__
2049
2059
struct
ALT_NOC_FW_L4_PER_SCR_EMAC2_s
2060
{
2061
uint32_t
mpu_m0
: 1;
2062
uint32_t : 7;
2063
uint32_t
dma
: 1;
2064
uint32_t : 7;
2065
uint32_t
fpga2soc
: 1;
2066
uint32_t : 7;
2067
uint32_t
ahb_ap
: 1;
2068
uint32_t : 7;
2069
};
2070
2072
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_EMAC2_s
ALT_NOC_FW_L4_PER_SCR_EMAC2_t
;
2073
#endif
/* __ASSEMBLY__ */
2074
2076
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_RESET 0x00000000
2077
2078
#define ALT_NOC_FW_L4_PER_SCR_EMAC2_OFST 0x34
2079
2099
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_LSB 0
2100
2101
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_MSB 31
2102
2103
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_WIDTH 32
2104
2105
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET_MSK 0xffffffff
2106
2107
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_CLR_MSK 0x00000000
2108
2109
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_RESET 0x0
2110
2111
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
2112
2113
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RSVD_SET(value) (((value) << 0) & 0xffffffff)
2114
2115
#ifndef __ASSEMBLY__
2116
2126
struct
ALT_NOC_FW_L4_PER_SCR_EMAC3_s
2127
{
2128
uint32_t
Reserved
: 32;
2129
};
2130
2132
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_EMAC3_s
ALT_NOC_FW_L4_PER_SCR_EMAC3_t
;
2133
#endif
/* __ASSEMBLY__ */
2134
2136
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_RESET 0x00000000
2137
2138
#define ALT_NOC_FW_L4_PER_SCR_EMAC3_OFST 0x38
2139
2170
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_LSB 0
2171
2172
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_MSB 0
2173
2174
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_WIDTH 1
2175
2176
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET_MSK 0x00000001
2177
2178
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_CLR_MSK 0xfffffffe
2179
2180
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_RESET 0x0
2181
2182
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2183
2184
#define ALT_NOC_FW_L4_PER_SCR_QSPI_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2185
2197
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_LSB 8
2198
2199
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_MSB 8
2200
2201
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_WIDTH 1
2202
2203
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET_MSK 0x00000100
2204
2205
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_CLR_MSK 0xfffffeff
2206
2207
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_RESET 0x0
2208
2209
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_GET(value) (((value) & 0x00000100) >> 8)
2210
2211
#define ALT_NOC_FW_L4_PER_SCR_QSPI_DMA_SET(value) (((value) << 8) & 0x00000100)
2212
2224
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_LSB 16
2225
2226
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_MSB 16
2227
2228
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_WIDTH 1
2229
2230
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET_MSK 0x00010000
2231
2232
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_CLR_MSK 0xfffeffff
2233
2234
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_RESET 0x0
2235
2236
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_GET(value) (((value) & 0x00010000) >> 16)
2237
2238
#define ALT_NOC_FW_L4_PER_SCR_QSPI_F2H_SET(value) (((value) << 16) & 0x00010000)
2239
2251
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_LSB 24
2252
2253
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_MSB 24
2254
2255
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_WIDTH 1
2256
2257
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET_MSK 0x01000000
2258
2259
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_CLR_MSK 0xfeffffff
2260
2261
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_RESET 0x0
2262
2263
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2264
2265
#define ALT_NOC_FW_L4_PER_SCR_QSPI_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2266
2267
#ifndef __ASSEMBLY__
2268
2278
struct
ALT_NOC_FW_L4_PER_SCR_QSPI_s
2279
{
2280
uint32_t
mpu_m0
: 1;
2281
uint32_t : 7;
2282
uint32_t
dma
: 1;
2283
uint32_t : 7;
2284
uint32_t
fpga2soc
: 1;
2285
uint32_t : 7;
2286
uint32_t
ahb_ap
: 1;
2287
uint32_t : 7;
2288
};
2289
2291
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_QSPI_s
ALT_NOC_FW_L4_PER_SCR_QSPI_t
;
2292
#endif
/* __ASSEMBLY__ */
2293
2295
#define ALT_NOC_FW_L4_PER_SCR_QSPI_RESET 0x00000000
2296
2297
#define ALT_NOC_FW_L4_PER_SCR_QSPI_OFST 0x3c
2298
2329
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_LSB 0
2330
2331
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_MSB 0
2332
2333
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_WIDTH 1
2334
2335
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET_MSK 0x00000001
2336
2337
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_CLR_MSK 0xfffffffe
2338
2339
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_RESET 0x0
2340
2341
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2342
2343
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2344
2356
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_LSB 8
2357
2358
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_MSB 8
2359
2360
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_WIDTH 1
2361
2362
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET_MSK 0x00000100
2363
2364
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_CLR_MSK 0xfffffeff
2365
2366
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_RESET 0x0
2367
2368
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_GET(value) (((value) & 0x00000100) >> 8)
2369
2370
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_DMA_SET(value) (((value) << 8) & 0x00000100)
2371
2383
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_LSB 16
2384
2385
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_MSB 16
2386
2387
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_WIDTH 1
2388
2389
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET_MSK 0x00010000
2390
2391
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_CLR_MSK 0xfffeffff
2392
2393
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_RESET 0x0
2394
2395
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2396
2397
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_F2H_SET(value) (((value) << 16) & 0x00010000)
2398
2410
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_LSB 24
2411
2412
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_MSB 24
2413
2414
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_WIDTH 1
2415
2416
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET_MSK 0x01000000
2417
2418
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_CLR_MSK 0xfeffffff
2419
2420
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_RESET 0x0
2421
2422
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2423
2424
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2425
2426
#ifndef __ASSEMBLY__
2427
2437
struct
ALT_NOC_FW_L4_PER_SCR_SDMMC_s
2438
{
2439
uint32_t
mpu_m0
: 1;
2440
uint32_t : 7;
2441
uint32_t
dma
: 1;
2442
uint32_t : 7;
2443
uint32_t
fpga2soc
: 1;
2444
uint32_t : 7;
2445
uint32_t
ahb_ap
: 1;
2446
uint32_t : 7;
2447
};
2448
2450
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SDMMC_s
ALT_NOC_FW_L4_PER_SCR_SDMMC_t
;
2451
#endif
/* __ASSEMBLY__ */
2452
2454
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_RESET 0x00000000
2455
2456
#define ALT_NOC_FW_L4_PER_SCR_SDMMC_OFST 0x40
2457
2488
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_LSB 0
2489
2490
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_MSB 0
2491
2492
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_WIDTH 1
2493
2494
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET_MSK 0x00000001
2495
2496
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_CLR_MSK 0xfffffffe
2497
2498
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_RESET 0x0
2499
2500
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2501
2502
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2503
2515
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_LSB 8
2516
2517
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_MSB 8
2518
2519
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_WIDTH 1
2520
2521
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET_MSK 0x00000100
2522
2523
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_CLR_MSK 0xfffffeff
2524
2525
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_RESET 0x0
2526
2527
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_GET(value) (((value) & 0x00000100) >> 8)
2528
2529
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_DMA_SET(value) (((value) << 8) & 0x00000100)
2530
2542
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_LSB 16
2543
2544
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_MSB 16
2545
2546
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_WIDTH 1
2547
2548
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET_MSK 0x00010000
2549
2550
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_CLR_MSK 0xfffeffff
2551
2552
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_RESET 0x0
2553
2554
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_GET(value) (((value) & 0x00010000) >> 16)
2555
2556
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_F2H_SET(value) (((value) << 16) & 0x00010000)
2557
2569
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_LSB 24
2570
2571
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_MSB 24
2572
2573
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_WIDTH 1
2574
2575
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET_MSK 0x01000000
2576
2577
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_CLR_MSK 0xfeffffff
2578
2579
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_RESET 0x0
2580
2581
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2582
2583
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2584
2585
#ifndef __ASSEMBLY__
2586
2596
struct
ALT_NOC_FW_L4_PER_SCR_GPIO0_s
2597
{
2598
uint32_t
mpu_m0
: 1;
2599
uint32_t : 7;
2600
uint32_t
dma
: 1;
2601
uint32_t : 7;
2602
uint32_t
fpga2soc
: 1;
2603
uint32_t : 7;
2604
uint32_t
ahb_ap
: 1;
2605
uint32_t : 7;
2606
};
2607
2609
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_GPIO0_s
ALT_NOC_FW_L4_PER_SCR_GPIO0_t
;
2610
#endif
/* __ASSEMBLY__ */
2611
2613
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_RESET 0x00000000
2614
2615
#define ALT_NOC_FW_L4_PER_SCR_GPIO0_OFST 0x44
2616
2647
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_LSB 0
2648
2649
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_MSB 0
2650
2651
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_WIDTH 1
2652
2653
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET_MSK 0x00000001
2654
2655
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_CLR_MSK 0xfffffffe
2656
2657
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_RESET 0x0
2658
2659
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2660
2661
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2662
2674
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_LSB 8
2675
2676
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_MSB 8
2677
2678
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_WIDTH 1
2679
2680
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET_MSK 0x00000100
2681
2682
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_CLR_MSK 0xfffffeff
2683
2684
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_RESET 0x0
2685
2686
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_GET(value) (((value) & 0x00000100) >> 8)
2687
2688
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_DMA_SET(value) (((value) << 8) & 0x00000100)
2689
2701
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_LSB 16
2702
2703
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_MSB 16
2704
2705
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_WIDTH 1
2706
2707
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET_MSK 0x00010000
2708
2709
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_CLR_MSK 0xfffeffff
2710
2711
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_RESET 0x0
2712
2713
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_GET(value) (((value) & 0x00010000) >> 16)
2714
2715
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_F2H_SET(value) (((value) << 16) & 0x00010000)
2716
2728
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_LSB 24
2729
2730
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_MSB 24
2731
2732
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_WIDTH 1
2733
2734
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET_MSK 0x01000000
2735
2736
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_CLR_MSK 0xfeffffff
2737
2738
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_RESET 0x0
2739
2740
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2741
2742
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2743
2744
#ifndef __ASSEMBLY__
2745
2755
struct
ALT_NOC_FW_L4_PER_SCR_GPIO1_s
2756
{
2757
uint32_t
mpu_m0
: 1;
2758
uint32_t : 7;
2759
uint32_t
dma
: 1;
2760
uint32_t : 7;
2761
uint32_t
fpga2soc
: 1;
2762
uint32_t : 7;
2763
uint32_t
ahb_ap
: 1;
2764
uint32_t : 7;
2765
};
2766
2768
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_GPIO1_s
ALT_NOC_FW_L4_PER_SCR_GPIO1_t
;
2769
#endif
/* __ASSEMBLY__ */
2770
2772
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_RESET 0x00000000
2773
2774
#define ALT_NOC_FW_L4_PER_SCR_GPIO1_OFST 0x48
2775
2806
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_LSB 0
2807
2808
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_MSB 0
2809
2810
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_WIDTH 1
2811
2812
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET_MSK 0x00000001
2813
2814
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_CLR_MSK 0xfffffffe
2815
2816
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_RESET 0x0
2817
2818
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2819
2820
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2821
2833
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_LSB 8
2834
2835
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_MSB 8
2836
2837
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_WIDTH 1
2838
2839
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET_MSK 0x00000100
2840
2841
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_CLR_MSK 0xfffffeff
2842
2843
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_RESET 0x0
2844
2845
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_GET(value) (((value) & 0x00000100) >> 8)
2846
2847
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_DMA_SET(value) (((value) << 8) & 0x00000100)
2848
2860
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_LSB 16
2861
2862
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_MSB 16
2863
2864
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_WIDTH 1
2865
2866
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET_MSK 0x00010000
2867
2868
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_CLR_MSK 0xfffeffff
2869
2870
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_RESET 0x0
2871
2872
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_GET(value) (((value) & 0x00010000) >> 16)
2873
2874
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_F2H_SET(value) (((value) << 16) & 0x00010000)
2875
2887
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_LSB 24
2888
2889
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_MSB 24
2890
2891
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_WIDTH 1
2892
2893
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET_MSK 0x01000000
2894
2895
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_CLR_MSK 0xfeffffff
2896
2897
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_RESET 0x0
2898
2899
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2900
2901
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2902
2903
#ifndef __ASSEMBLY__
2904
2914
struct
ALT_NOC_FW_L4_PER_SCR_GPIO2_s
2915
{
2916
uint32_t
mpu_m0
: 1;
2917
uint32_t : 7;
2918
uint32_t
dma
: 1;
2919
uint32_t : 7;
2920
uint32_t
fpga2soc
: 1;
2921
uint32_t : 7;
2922
uint32_t
ahb_ap
: 1;
2923
uint32_t : 7;
2924
};
2925
2927
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_GPIO2_s
ALT_NOC_FW_L4_PER_SCR_GPIO2_t
;
2928
#endif
/* __ASSEMBLY__ */
2929
2931
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_RESET 0x00000000
2932
2933
#define ALT_NOC_FW_L4_PER_SCR_GPIO2_OFST 0x4c
2934
2965
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_LSB 0
2966
2967
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_MSB 0
2968
2969
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_WIDTH 1
2970
2971
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET_MSK 0x00000001
2972
2973
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_CLR_MSK 0xfffffffe
2974
2975
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_RESET 0x0
2976
2977
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2978
2979
#define ALT_NOC_FW_L4_PER_SCR_I2C0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2980
2992
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_LSB 8
2993
2994
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_MSB 8
2995
2996
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_WIDTH 1
2997
2998
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET_MSK 0x00000100
2999
3000
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_CLR_MSK 0xfffffeff
3001
3002
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_RESET 0x0
3003
3004
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3005
3006
#define ALT_NOC_FW_L4_PER_SCR_I2C0_DMA_SET(value) (((value) << 8) & 0x00000100)
3007
3019
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_LSB 16
3020
3021
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_MSB 16
3022
3023
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_WIDTH 1
3024
3025
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET_MSK 0x00010000
3026
3027
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_CLR_MSK 0xfffeffff
3028
3029
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_RESET 0x0
3030
3031
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3032
3033
#define ALT_NOC_FW_L4_PER_SCR_I2C0_F2H_SET(value) (((value) << 16) & 0x00010000)
3034
3046
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_LSB 24
3047
3048
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_MSB 24
3049
3050
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_WIDTH 1
3051
3052
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET_MSK 0x01000000
3053
3054
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_CLR_MSK 0xfeffffff
3055
3056
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_RESET 0x0
3057
3058
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3059
3060
#define ALT_NOC_FW_L4_PER_SCR_I2C0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3061
3062
#ifndef __ASSEMBLY__
3063
3073
struct
ALT_NOC_FW_L4_PER_SCR_I2C0_s
3074
{
3075
uint32_t
mpu_m0
: 1;
3076
uint32_t : 7;
3077
uint32_t
dma
: 1;
3078
uint32_t : 7;
3079
uint32_t
fpga2soc
: 1;
3080
uint32_t : 7;
3081
uint32_t
ahb_ap
: 1;
3082
uint32_t : 7;
3083
};
3084
3086
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_I2C0_s
ALT_NOC_FW_L4_PER_SCR_I2C0_t
;
3087
#endif
/* __ASSEMBLY__ */
3088
3090
#define ALT_NOC_FW_L4_PER_SCR_I2C0_RESET 0x00000000
3091
3092
#define ALT_NOC_FW_L4_PER_SCR_I2C0_OFST 0x50
3093
3124
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_LSB 0
3125
3126
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_MSB 0
3127
3128
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_WIDTH 1
3129
3130
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET_MSK 0x00000001
3131
3132
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_CLR_MSK 0xfffffffe
3133
3134
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_RESET 0x0
3135
3136
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3137
3138
#define ALT_NOC_FW_L4_PER_SCR_I2C1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3139
3151
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_LSB 8
3152
3153
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_MSB 8
3154
3155
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_WIDTH 1
3156
3157
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET_MSK 0x00000100
3158
3159
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_CLR_MSK 0xfffffeff
3160
3161
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_RESET 0x0
3162
3163
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3164
3165
#define ALT_NOC_FW_L4_PER_SCR_I2C1_DMA_SET(value) (((value) << 8) & 0x00000100)
3166
3178
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_LSB 16
3179
3180
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_MSB 16
3181
3182
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_WIDTH 1
3183
3184
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET_MSK 0x00010000
3185
3186
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_CLR_MSK 0xfffeffff
3187
3188
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_RESET 0x0
3189
3190
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3191
3192
#define ALT_NOC_FW_L4_PER_SCR_I2C1_F2H_SET(value) (((value) << 16) & 0x00010000)
3193
3205
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_LSB 24
3206
3207
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_MSB 24
3208
3209
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_WIDTH 1
3210
3211
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET_MSK 0x01000000
3212
3213
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_CLR_MSK 0xfeffffff
3214
3215
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_RESET 0x0
3216
3217
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3218
3219
#define ALT_NOC_FW_L4_PER_SCR_I2C1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3220
3221
#ifndef __ASSEMBLY__
3222
3232
struct
ALT_NOC_FW_L4_PER_SCR_I2C1_s
3233
{
3234
uint32_t
mpu_m0
: 1;
3235
uint32_t : 7;
3236
uint32_t
dma
: 1;
3237
uint32_t : 7;
3238
uint32_t
fpga2soc
: 1;
3239
uint32_t : 7;
3240
uint32_t
ahb_ap
: 1;
3241
uint32_t : 7;
3242
};
3243
3245
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_I2C1_s
ALT_NOC_FW_L4_PER_SCR_I2C1_t
;
3246
#endif
/* __ASSEMBLY__ */
3247
3249
#define ALT_NOC_FW_L4_PER_SCR_I2C1_RESET 0x00000000
3250
3251
#define ALT_NOC_FW_L4_PER_SCR_I2C1_OFST 0x54
3252
3283
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_LSB 0
3284
3285
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_MSB 0
3286
3287
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_WIDTH 1
3288
3289
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET_MSK 0x00000001
3290
3291
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_CLR_MSK 0xfffffffe
3292
3293
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_RESET 0x0
3294
3295
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3296
3297
#define ALT_NOC_FW_L4_PER_SCR_I2C2_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3298
3310
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_LSB 8
3311
3312
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_MSB 8
3313
3314
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_WIDTH 1
3315
3316
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET_MSK 0x00000100
3317
3318
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_CLR_MSK 0xfffffeff
3319
3320
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_RESET 0x0
3321
3322
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_GET(value) (((value) & 0x00000100) >> 8)
3323
3324
#define ALT_NOC_FW_L4_PER_SCR_I2C2_DMA_SET(value) (((value) << 8) & 0x00000100)
3325
3337
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_LSB 16
3338
3339
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_MSB 16
3340
3341
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_WIDTH 1
3342
3343
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET_MSK 0x00010000
3344
3345
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_CLR_MSK 0xfffeffff
3346
3347
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_RESET 0x0
3348
3349
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_GET(value) (((value) & 0x00010000) >> 16)
3350
3351
#define ALT_NOC_FW_L4_PER_SCR_I2C2_F2H_SET(value) (((value) << 16) & 0x00010000)
3352
3364
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_LSB 24
3365
3366
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_MSB 24
3367
3368
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_WIDTH 1
3369
3370
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET_MSK 0x01000000
3371
3372
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_CLR_MSK 0xfeffffff
3373
3374
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_RESET 0x0
3375
3376
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3377
3378
#define ALT_NOC_FW_L4_PER_SCR_I2C2_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3379
3380
#ifndef __ASSEMBLY__
3381
3391
struct
ALT_NOC_FW_L4_PER_SCR_I2C2_s
3392
{
3393
uint32_t
mpu_m0
: 1;
3394
uint32_t : 7;
3395
uint32_t
dma
: 1;
3396
uint32_t : 7;
3397
uint32_t
fpga2soc
: 1;
3398
uint32_t : 7;
3399
uint32_t
ahb_ap
: 1;
3400
uint32_t : 7;
3401
};
3402
3404
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_I2C2_s
ALT_NOC_FW_L4_PER_SCR_I2C2_t
;
3405
#endif
/* __ASSEMBLY__ */
3406
3408
#define ALT_NOC_FW_L4_PER_SCR_I2C2_RESET 0x00000000
3409
3410
#define ALT_NOC_FW_L4_PER_SCR_I2C2_OFST 0x58
3411
3442
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_LSB 0
3443
3444
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_MSB 0
3445
3446
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_WIDTH 1
3447
3448
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET_MSK 0x00000001
3449
3450
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_CLR_MSK 0xfffffffe
3451
3452
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_RESET 0x0
3453
3454
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3455
3456
#define ALT_NOC_FW_L4_PER_SCR_I2C3_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3457
3469
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_LSB 8
3470
3471
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_MSB 8
3472
3473
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_WIDTH 1
3474
3475
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET_MSK 0x00000100
3476
3477
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_CLR_MSK 0xfffffeff
3478
3479
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_RESET 0x0
3480
3481
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_GET(value) (((value) & 0x00000100) >> 8)
3482
3483
#define ALT_NOC_FW_L4_PER_SCR_I2C3_DMA_SET(value) (((value) << 8) & 0x00000100)
3484
3496
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_LSB 16
3497
3498
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_MSB 16
3499
3500
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_WIDTH 1
3501
3502
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET_MSK 0x00010000
3503
3504
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_CLR_MSK 0xfffeffff
3505
3506
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_RESET 0x0
3507
3508
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_GET(value) (((value) & 0x00010000) >> 16)
3509
3510
#define ALT_NOC_FW_L4_PER_SCR_I2C3_F2H_SET(value) (((value) << 16) & 0x00010000)
3511
3523
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_LSB 24
3524
3525
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_MSB 24
3526
3527
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_WIDTH 1
3528
3529
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET_MSK 0x01000000
3530
3531
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_CLR_MSK 0xfeffffff
3532
3533
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_RESET 0x0
3534
3535
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3536
3537
#define ALT_NOC_FW_L4_PER_SCR_I2C3_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3538
3539
#ifndef __ASSEMBLY__
3540
3550
struct
ALT_NOC_FW_L4_PER_SCR_I2C3_s
3551
{
3552
uint32_t
mpu_m0
: 1;
3553
uint32_t : 7;
3554
uint32_t
dma
: 1;
3555
uint32_t : 7;
3556
uint32_t
fpga2soc
: 1;
3557
uint32_t : 7;
3558
uint32_t
ahb_ap
: 1;
3559
uint32_t : 7;
3560
};
3561
3563
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_I2C3_s
ALT_NOC_FW_L4_PER_SCR_I2C3_t
;
3564
#endif
/* __ASSEMBLY__ */
3565
3567
#define ALT_NOC_FW_L4_PER_SCR_I2C3_RESET 0x00000000
3568
3569
#define ALT_NOC_FW_L4_PER_SCR_I2C3_OFST 0x5c
3570
3601
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_LSB 0
3602
3603
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_MSB 0
3604
3605
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_WIDTH 1
3606
3607
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET_MSK 0x00000001
3608
3609
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_CLR_MSK 0xfffffffe
3610
3611
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_RESET 0x0
3612
3613
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3614
3615
#define ALT_NOC_FW_L4_PER_SCR_I2C4_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3616
3628
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_LSB 8
3629
3630
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_MSB 8
3631
3632
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_WIDTH 1
3633
3634
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET_MSK 0x00000100
3635
3636
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_CLR_MSK 0xfffffeff
3637
3638
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_RESET 0x0
3639
3640
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_GET(value) (((value) & 0x00000100) >> 8)
3641
3642
#define ALT_NOC_FW_L4_PER_SCR_I2C4_DMA_SET(value) (((value) << 8) & 0x00000100)
3643
3655
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_LSB 16
3656
3657
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_MSB 16
3658
3659
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_WIDTH 1
3660
3661
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET_MSK 0x00010000
3662
3663
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_CLR_MSK 0xfffeffff
3664
3665
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_RESET 0x0
3666
3667
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_GET(value) (((value) & 0x00010000) >> 16)
3668
3669
#define ALT_NOC_FW_L4_PER_SCR_I2C4_F2H_SET(value) (((value) << 16) & 0x00010000)
3670
3682
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_LSB 24
3683
3684
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_MSB 24
3685
3686
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_WIDTH 1
3687
3688
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET_MSK 0x01000000
3689
3690
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_CLR_MSK 0xfeffffff
3691
3692
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_RESET 0x0
3693
3694
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3695
3696
#define ALT_NOC_FW_L4_PER_SCR_I2C4_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3697
3698
#ifndef __ASSEMBLY__
3699
3709
struct
ALT_NOC_FW_L4_PER_SCR_I2C4_s
3710
{
3711
uint32_t
mpu_m0
: 1;
3712
uint32_t : 7;
3713
uint32_t
dma
: 1;
3714
uint32_t : 7;
3715
uint32_t
fpga2soc
: 1;
3716
uint32_t : 7;
3717
uint32_t
ahb_ap
: 1;
3718
uint32_t : 7;
3719
};
3720
3722
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_I2C4_s
ALT_NOC_FW_L4_PER_SCR_I2C4_t
;
3723
#endif
/* __ASSEMBLY__ */
3724
3726
#define ALT_NOC_FW_L4_PER_SCR_I2C4_RESET 0x00000000
3727
3728
#define ALT_NOC_FW_L4_PER_SCR_I2C4_OFST 0x60
3729
3760
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_LSB 0
3761
3762
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_MSB 0
3763
3764
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_WIDTH 1
3765
3766
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET_MSK 0x00000001
3767
3768
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_CLR_MSK 0xfffffffe
3769
3770
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_RESET 0x0
3771
3772
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3773
3774
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3775
3787
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_LSB 8
3788
3789
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_MSB 8
3790
3791
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_WIDTH 1
3792
3793
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET_MSK 0x00000100
3794
3795
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_CLR_MSK 0xfffffeff
3796
3797
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_RESET 0x0
3798
3799
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3800
3801
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_DMA_SET(value) (((value) << 8) & 0x00000100)
3802
3814
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_LSB 16
3815
3816
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_MSB 16
3817
3818
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_WIDTH 1
3819
3820
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET_MSK 0x00010000
3821
3822
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_CLR_MSK 0xfffeffff
3823
3824
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_RESET 0x0
3825
3826
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3827
3828
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_F2H_SET(value) (((value) << 16) & 0x00010000)
3829
3841
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_LSB 24
3842
3843
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_MSB 24
3844
3845
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_WIDTH 1
3846
3847
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET_MSK 0x01000000
3848
3849
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_CLR_MSK 0xfeffffff
3850
3851
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_RESET 0x0
3852
3853
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3854
3855
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3856
3857
#ifndef __ASSEMBLY__
3858
3868
struct
ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s
3869
{
3870
uint32_t
mpu_m0
: 1;
3871
uint32_t : 7;
3872
uint32_t
dma
: 1;
3873
uint32_t : 7;
3874
uint32_t
fpga2soc
: 1;
3875
uint32_t : 7;
3876
uint32_t
ahb_ap
: 1;
3877
uint32_t : 7;
3878
};
3879
3881
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SP_TMR0_s
ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t
;
3882
#endif
/* __ASSEMBLY__ */
3883
3885
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_RESET 0x00000000
3886
3887
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR0_OFST 0x64
3888
3919
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_LSB 0
3920
3921
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_MSB 0
3922
3923
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_WIDTH 1
3924
3925
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET_MSK 0x00000001
3926
3927
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_CLR_MSK 0xfffffffe
3928
3929
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_RESET 0x0
3930
3931
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3932
3933
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3934
3946
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_LSB 8
3947
3948
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_MSB 8
3949
3950
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_WIDTH 1
3951
3952
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET_MSK 0x00000100
3953
3954
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_CLR_MSK 0xfffffeff
3955
3956
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_RESET 0x0
3957
3958
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3959
3960
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_DMA_SET(value) (((value) << 8) & 0x00000100)
3961
3973
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_LSB 16
3974
3975
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_MSB 16
3976
3977
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_WIDTH 1
3978
3979
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET_MSK 0x00010000
3980
3981
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_CLR_MSK 0xfffeffff
3982
3983
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_RESET 0x0
3984
3985
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3986
3987
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_F2H_SET(value) (((value) << 16) & 0x00010000)
3988
4000
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_LSB 24
4001
4002
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_MSB 24
4003
4004
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_WIDTH 1
4005
4006
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET_MSK 0x01000000
4007
4008
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_CLR_MSK 0xfeffffff
4009
4010
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_RESET 0x0
4011
4012
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4013
4014
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4015
4016
#ifndef __ASSEMBLY__
4017
4027
struct
ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s
4028
{
4029
uint32_t
mpu_m0
: 1;
4030
uint32_t : 7;
4031
uint32_t
dma
: 1;
4032
uint32_t : 7;
4033
uint32_t
fpga2soc
: 1;
4034
uint32_t : 7;
4035
uint32_t
ahb_ap
: 1;
4036
uint32_t : 7;
4037
};
4038
4040
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_SP_TMR1_s
ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t
;
4041
#endif
/* __ASSEMBLY__ */
4042
4044
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_RESET 0x00000000
4045
4046
#define ALT_NOC_FW_L4_PER_SCR_SP_TMR1_OFST 0x68
4047
4078
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_LSB 0
4079
4080
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_MSB 0
4081
4082
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_WIDTH 1
4083
4084
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET_MSK 0x00000001
4085
4086
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_CLR_MSK 0xfffffffe
4087
4088
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_RESET 0x0
4089
4090
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4091
4092
#define ALT_NOC_FW_L4_PER_SCR_UART0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4093
4105
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_LSB 8
4106
4107
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_MSB 8
4108
4109
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_WIDTH 1
4110
4111
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET_MSK 0x00000100
4112
4113
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_CLR_MSK 0xfffffeff
4114
4115
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_RESET 0x0
4116
4117
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_GET(value) (((value) & 0x00000100) >> 8)
4118
4119
#define ALT_NOC_FW_L4_PER_SCR_UART0_DMA_SET(value) (((value) << 8) & 0x00000100)
4120
4132
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_LSB 16
4133
4134
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_MSB 16
4135
4136
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_WIDTH 1
4137
4138
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET_MSK 0x00010000
4139
4140
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_CLR_MSK 0xfffeffff
4141
4142
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_RESET 0x0
4143
4144
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_GET(value) (((value) & 0x00010000) >> 16)
4145
4146
#define ALT_NOC_FW_L4_PER_SCR_UART0_F2H_SET(value) (((value) << 16) & 0x00010000)
4147
4159
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_LSB 24
4160
4161
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_MSB 24
4162
4163
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_WIDTH 1
4164
4165
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET_MSK 0x01000000
4166
4167
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_CLR_MSK 0xfeffffff
4168
4169
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_RESET 0x0
4170
4171
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4172
4173
#define ALT_NOC_FW_L4_PER_SCR_UART0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4174
4175
#ifndef __ASSEMBLY__
4176
4186
struct
ALT_NOC_FW_L4_PER_SCR_UART0_s
4187
{
4188
uint32_t
mpu_m0
: 1;
4189
uint32_t : 7;
4190
uint32_t
dma
: 1;
4191
uint32_t : 7;
4192
uint32_t
fpga2soc
: 1;
4193
uint32_t : 7;
4194
uint32_t
ahb_ap
: 1;
4195
uint32_t : 7;
4196
};
4197
4199
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_UART0_s
ALT_NOC_FW_L4_PER_SCR_UART0_t
;
4200
#endif
/* __ASSEMBLY__ */
4201
4203
#define ALT_NOC_FW_L4_PER_SCR_UART0_RESET 0x00000000
4204
4205
#define ALT_NOC_FW_L4_PER_SCR_UART0_OFST 0x6c
4206
4237
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_LSB 0
4238
4239
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_MSB 0
4240
4241
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_WIDTH 1
4242
4243
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET_MSK 0x00000001
4244
4245
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_CLR_MSK 0xfffffffe
4246
4247
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_RESET 0x0
4248
4249
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4250
4251
#define ALT_NOC_FW_L4_PER_SCR_UART1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4252
4264
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_LSB 8
4265
4266
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_MSB 8
4267
4268
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_WIDTH 1
4269
4270
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET_MSK 0x00000100
4271
4272
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_CLR_MSK 0xfffffeff
4273
4274
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_RESET 0x0
4275
4276
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_GET(value) (((value) & 0x00000100) >> 8)
4277
4278
#define ALT_NOC_FW_L4_PER_SCR_UART1_DMA_SET(value) (((value) << 8) & 0x00000100)
4279
4291
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_LSB 16
4292
4293
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_MSB 16
4294
4295
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_WIDTH 1
4296
4297
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET_MSK 0x00010000
4298
4299
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_CLR_MSK 0xfffeffff
4300
4301
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_RESET 0x0
4302
4303
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_GET(value) (((value) & 0x00010000) >> 16)
4304
4305
#define ALT_NOC_FW_L4_PER_SCR_UART1_F2H_SET(value) (((value) << 16) & 0x00010000)
4306
4318
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_LSB 24
4319
4320
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_MSB 24
4321
4322
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_WIDTH 1
4323
4324
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET_MSK 0x01000000
4325
4326
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_CLR_MSK 0xfeffffff
4327
4328
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_RESET 0x0
4329
4330
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4331
4332
#define ALT_NOC_FW_L4_PER_SCR_UART1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4333
4334
#ifndef __ASSEMBLY__
4335
4345
struct
ALT_NOC_FW_L4_PER_SCR_UART1_s
4346
{
4347
uint32_t
mpu_m0
: 1;
4348
uint32_t : 7;
4349
uint32_t
dma
: 1;
4350
uint32_t : 7;
4351
uint32_t
fpga2soc
: 1;
4352
uint32_t : 7;
4353
uint32_t
ahb_ap
: 1;
4354
uint32_t : 7;
4355
};
4356
4358
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_UART1_s
ALT_NOC_FW_L4_PER_SCR_UART1_t
;
4359
#endif
/* __ASSEMBLY__ */
4360
4362
#define ALT_NOC_FW_L4_PER_SCR_UART1_RESET 0x00000000
4363
4364
#define ALT_NOC_FW_L4_PER_SCR_UART1_OFST 0x70
4365
4366
#ifndef __ASSEMBLY__
4367
4377
struct
ALT_NOC_FW_L4_PER_SCR_s
4378
{
4379
volatile
ALT_NOC_FW_L4_PER_SCR_NAND_REG_t
nand_register
;
4380
volatile
ALT_NOC_FW_L4_PER_SCR_NAND_DATA_t
nand_data
;
4381
volatile
ALT_NOC_FW_L4_PER_SCR_QSPI_DATA_t
qspi_data
;
4382
volatile
ALT_NOC_FW_L4_PER_SCR_USB0_REG_t
usb0_register
;
4383
volatile
ALT_NOC_FW_L4_PER_SCR_USB1_REG_t
usb1_register
;
4384
volatile
ALT_NOC_FW_L4_PER_SCR_DMA_NONSECURE_t
dma_nonsecure
;
4385
volatile
ALT_NOC_FW_L4_PER_SCR_DMA_SECURE_t
dma_secure
;
4386
volatile
ALT_NOC_FW_L4_PER_SCR_SPI_MST0_t
spi_master0
;
4387
volatile
ALT_NOC_FW_L4_PER_SCR_SPI_MST1_t
spi_master1
;
4388
volatile
ALT_NOC_FW_L4_PER_SCR_SPI_SLV0_t
spi_slave0
;
4389
volatile
ALT_NOC_FW_L4_PER_SCR_SPI_SLV1_t
spi_slave1
;
4390
volatile
ALT_NOC_FW_L4_PER_SCR_EMAC0_t
emac0
;
4391
volatile
ALT_NOC_FW_L4_PER_SCR_EMAC1_t
emac1
;
4392
volatile
ALT_NOC_FW_L4_PER_SCR_EMAC2_t
emac2
;
4393
volatile
ALT_NOC_FW_L4_PER_SCR_EMAC3_t
emac3
;
4394
volatile
ALT_NOC_FW_L4_PER_SCR_QSPI_t
qspi
;
4395
volatile
ALT_NOC_FW_L4_PER_SCR_SDMMC_t
sdmmc
;
4396
volatile
ALT_NOC_FW_L4_PER_SCR_GPIO0_t
gpio0
;
4397
volatile
ALT_NOC_FW_L4_PER_SCR_GPIO1_t
gpio1
;
4398
volatile
ALT_NOC_FW_L4_PER_SCR_GPIO2_t
gpio2
;
4399
volatile
ALT_NOC_FW_L4_PER_SCR_I2C0_t
i2c0
;
4400
volatile
ALT_NOC_FW_L4_PER_SCR_I2C1_t
i2c1
;
4401
volatile
ALT_NOC_FW_L4_PER_SCR_I2C2_t
i2c2
;
4402
volatile
ALT_NOC_FW_L4_PER_SCR_I2C3_t
i2c3
;
4403
volatile
ALT_NOC_FW_L4_PER_SCR_I2C4_t
i2c4
;
4404
volatile
ALT_NOC_FW_L4_PER_SCR_SP_TMR0_t
sp_timer0
;
4405
volatile
ALT_NOC_FW_L4_PER_SCR_SP_TMR1_t
sp_timer1
;
4406
volatile
ALT_NOC_FW_L4_PER_SCR_UART0_t
uart0
;
4407
volatile
ALT_NOC_FW_L4_PER_SCR_UART1_t
uart1
;
4408
volatile
uint32_t
_pad_0x74_0x100
[35];
4409
};
4410
4412
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_s
ALT_NOC_FW_L4_PER_SCR_t
;
4414
struct
ALT_NOC_FW_L4_PER_SCR_raw_s
4415
{
4416
volatile
uint32_t
nand_register
;
4417
volatile
uint32_t
nand_data
;
4418
volatile
uint32_t
qspi_data
;
4419
volatile
uint32_t
usb0_register
;
4420
volatile
uint32_t
usb1_register
;
4421
volatile
uint32_t
dma_nonsecure
;
4422
volatile
uint32_t
dma_secure
;
4423
volatile
uint32_t
spi_master0
;
4424
volatile
uint32_t
spi_master1
;
4425
volatile
uint32_t
spi_slave0
;
4426
volatile
uint32_t
spi_slave1
;
4427
volatile
uint32_t
emac0
;
4428
volatile
uint32_t
emac1
;
4429
volatile
uint32_t
emac2
;
4430
volatile
uint32_t
emac3
;
4431
volatile
uint32_t
qspi
;
4432
volatile
uint32_t
sdmmc
;
4433
volatile
uint32_t
gpio0
;
4434
volatile
uint32_t
gpio1
;
4435
volatile
uint32_t
gpio2
;
4436
volatile
uint32_t
i2c0
;
4437
volatile
uint32_t
i2c1
;
4438
volatile
uint32_t
i2c2
;
4439
volatile
uint32_t
i2c3
;
4440
volatile
uint32_t
i2c4
;
4441
volatile
uint32_t
sp_timer0
;
4442
volatile
uint32_t
sp_timer1
;
4443
volatile
uint32_t
uart0
;
4444
volatile
uint32_t
uart1
;
4445
volatile
uint32_t
_pad_0x74_0x100
[35];
4446
};
4447
4449
typedef
volatile
struct
ALT_NOC_FW_L4_PER_SCR_raw_s
ALT_NOC_FW_L4_PER_SCR_raw_t
;
4450
#endif
/* __ASSEMBLY__ */
4451
4453
#ifdef __cplusplus
4454
}
4455
#endif
/* __cplusplus */
4456
#endif
/* __ALT_SOCAL_NOC_FW_L4_PER_SCR_H__ */
4457
include
soc_a10
socal
alt_noc_fw_l4_per_scr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2