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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register implements JEDEC standardized timing parameters. It should be programmed in clock cycles, for the value specified by the memory vendor.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[12:0] | RW | Unknown | Refresh Interval |
[16:13] | RW | Unknown | Activate to Read or Write Delay |
[20:17] | RW | Unknown | Row Precharge Time |
[24:21] | RW | Unknown | Write Recovery Time |
[28:25] | RW | Unknown | Write to Read Time |
[31:29] | ??? | 0x0 | UNDEFINED |
Field : Refresh Interval - trefi | |
The refresh interval timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_GET(value) (((value) & 0x00001fff) >> 0) |
#define | ALT_SDR_CTL_DRAMTIMING2_TREFI_SET(value) (((value) << 0) & 0x00001fff) |
Field : Activate to Read or Write Delay - trcd | |
The activate to read/write timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_GET(value) (((value) & 0x0001e000) >> 13) |
#define | ALT_SDR_CTL_DRAMTIMING2_TRCD_SET(value) (((value) << 13) & 0x0001e000) |
Field : Row Precharge Time - trp | |
The precharge to activate timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_GET(value) (((value) & 0x001e0000) >> 17) |
#define | ALT_SDR_CTL_DRAMTIMING2_TRP_SET(value) (((value) << 17) & 0x001e0000) |
Field : Write Recovery Time - twr | |
The write recovery timing. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_GET(value) (((value) & 0x01e00000) >> 21) |
#define | ALT_SDR_CTL_DRAMTIMING2_TWR_SET(value) (((value) << 21) & 0x01e00000) |
Field : Write to Read Time - twtr | |
The write to read timing parameter. Field Access Macros: | |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_GET(value) (((value) & 0x1e000000) >> 25) |
#define | ALT_SDR_CTL_DRAMTIMING2_TWTR_SET(value) (((value) << 25) & 0x1e000000) |
Data Structures | |
struct | ALT_SDR_CTL_DRAMTIMING2_s |
Macros | |
#define | ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 |
Typedefs | |
typedef struct ALT_SDR_CTL_DRAMTIMING2_s | ALT_SDR_CTL_DRAMTIMING2_t |
struct ALT_SDR_CTL_DRAMTIMING2_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_DRAMTIMING2.
Data Fields | ||
---|---|---|
uint32_t | trefi: 13 | Refresh Interval |
uint32_t | trcd: 4 | Activate to Read or Write Delay |
uint32_t | trp: 4 | Row Precharge Time |
uint32_t | twr: 4 | Write Recovery Time |
uint32_t | twtr: 4 | Write to Read Time |
uint32_t | __pad0__: 3 | UNDEFINED |
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_WIDTH 13 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET_MSK 0x00001fff |
The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_CLR_MSK 0xffffe000 |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TREFI register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING2_TREFI register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_GET | ( | value | ) | (((value) & 0x00001fff) >> 0) |
Extracts the ALT_SDR_CTL_DRAMTIMING2_TREFI field value from a register.
#define ALT_SDR_CTL_DRAMTIMING2_TREFI_SET | ( | value | ) | (((value) << 0) & 0x00001fff) |
Produces a ALT_SDR_CTL_DRAMTIMING2_TREFI register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET_MSK 0x0001e000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_CLR_MSK 0xfffe1fff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRCD register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRCD register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_GET | ( | value | ) | (((value) & 0x0001e000) >> 13) |
Extracts the ALT_SDR_CTL_DRAMTIMING2_TRCD field value from a register.
#define ALT_SDR_CTL_DRAMTIMING2_TRCD_SET | ( | value | ) | (((value) << 13) & 0x0001e000) |
Produces a ALT_SDR_CTL_DRAMTIMING2_TRCD register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_MSB 20 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TRP register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TRP register field.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET_MSK 0x001e0000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TRP register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_CLR_MSK 0xffe1ffff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TRP register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING2_TRP register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_GET | ( | value | ) | (((value) & 0x001e0000) >> 17) |
Extracts the ALT_SDR_CTL_DRAMTIMING2_TRP field value from a register.
#define ALT_SDR_CTL_DRAMTIMING2_TRP_SET | ( | value | ) | (((value) << 17) & 0x001e0000) |
Produces a ALT_SDR_CTL_DRAMTIMING2_TRP register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_LSB 21 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET_MSK 0x01e00000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWR register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_CLR_MSK 0xfe1fffff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWR register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWR register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_GET | ( | value | ) | (((value) & 0x01e00000) >> 21) |
Extracts the ALT_SDR_CTL_DRAMTIMING2_TWR field value from a register.
#define ALT_SDR_CTL_DRAMTIMING2_TWR_SET | ( | value | ) | (((value) << 21) & 0x01e00000) |
Produces a ALT_SDR_CTL_DRAMTIMING2_TWR register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_WIDTH 4 |
The width in bits of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET_MSK 0x1e000000 |
The mask used to set the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_CLR_MSK 0xe1ffffff |
The mask used to clear the ALT_SDR_CTL_DRAMTIMING2_TWTR register field value.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_RESET 0x0 |
The reset value of the ALT_SDR_CTL_DRAMTIMING2_TWTR register field is UNKNOWN.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_GET | ( | value | ) | (((value) & 0x1e000000) >> 25) |
Extracts the ALT_SDR_CTL_DRAMTIMING2_TWTR field value from a register.
#define ALT_SDR_CTL_DRAMTIMING2_TWTR_SET | ( | value | ) | (((value) << 25) & 0x1e000000) |
Produces a ALT_SDR_CTL_DRAMTIMING2_TWTR register field value suitable for setting the register.
#define ALT_SDR_CTL_DRAMTIMING2_OFST 0x8 |
The byte offset of the ALT_SDR_CTL_DRAMTIMING2 register from the beginning of the component.
typedef struct ALT_SDR_CTL_DRAMTIMING2_s ALT_SDR_CTL_DRAMTIMING2_t |
The typedef declaration for register ALT_SDR_CTL_DRAMTIMING2.