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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Contains fields that control clock dividers for clocks derived from the Peripheral PLL
Fields are only reset by a cold reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[2:0] | RW | 0x0 | USB Clock Divider |
[5:3] | RW | 0x0 | SPI Master Clock Divider |
[8:6] | RW | 0x0 | CAN0 Clock Divider |
[11:9] | RW | 0x0 | CAN1 Clock Divider |
[31:12] | ??? | 0x0 | UNDEFINED |
Field : SPI Master Clock Divider - spimclk | ||||||||||||||||||||||||||||
The spi_m_clk is divided down from the periph_base_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET(value) (((value) & 0x00000038) >> 3) | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET(value) (((value) << 3) & 0x00000038) | |||||||||||||||||||||||||||
Field : CAN0 Clock Divider - can0clk | ||||||||||||||||||||||||||||
The can0_clk is divided down from the periph_base_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET(value) (((value) & 0x000001c0) >> 6) | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET(value) (((value) << 6) & 0x000001c0) | |||||||||||||||||||||||||||
Field : CAN1 Clock Divider - can1clk | ||||||||||||||||||||||||||||
The can1_clk is divided down from the periph_base_clk by the value specified in this field. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET(value) (((value) & 0x00000e00) >> 9) | |||||||||||||||||||||||||||
#define | ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET(value) (((value) << 9) & 0x00000e00) | |||||||||||||||||||||||||||
Data Structures | |
struct | ALT_CLKMGR_PERPLL_DIV_s |
Macros | |
#define | ALT_CLKMGR_PERPLL_DIV_OFST 0x24 |
Typedefs | |
typedef struct ALT_CLKMGR_PERPLL_DIV_s | ALT_CLKMGR_PERPLL_DIV_t |
struct ALT_CLKMGR_PERPLL_DIV_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_PERPLL_DIV.
Data Fields | ||
---|---|---|
uint32_t | usbclk: 3 | USB Clock Divider |
uint32_t | spimclk: 3 | SPI Master Clock Divider |
uint32_t | can0clk: 3 | CAN0 Clock Divider |
uint32_t | can1clk: 3 | CAN1 Clock Divider |
uint32_t | __pad0__: 20 | UNDEFINED |
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Divide By 1
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Divide By 2
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Divide By 4
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Divide By 8
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Divide By 16
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_USBCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET_MSK 0x00000007 |
The mask used to set the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_CLR_MSK 0xfffffff8 |
The mask used to clear the ALT_CLKMGR_PERPLL_DIV_USBCLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_DIV_USBCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_GET | ( | value | ) | (((value) & 0x00000007) >> 0) |
Extracts the ALT_CLKMGR_PERPLL_DIV_USBCLK field value from a register.
#define ALT_CLKMGR_PERPLL_DIV_USBCLK_SET | ( | value | ) | (((value) << 0) & 0x00000007) |
Produces a ALT_CLKMGR_PERPLL_DIV_USBCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Divide By 1
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Divide By 2
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Divide By 4
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Divide By 8
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Divide By 16
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_SPIMCLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET_MSK 0x00000038 |
The mask used to set the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_CLR_MSK 0xffffffc7 |
The mask used to clear the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_GET | ( | value | ) | (((value) & 0x00000038) >> 3) |
Extracts the ALT_CLKMGR_PERPLL_DIV_SPIMCLK field value from a register.
#define ALT_CLKMGR_PERPLL_DIV_SPIMCLK_SET | ( | value | ) | (((value) << 3) & 0x00000038) |
Produces a ALT_CLKMGR_PERPLL_DIV_SPIMCLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Divide By 1
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Divide By 2
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Divide By 4
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Divide By 8
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Divide By 16
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN0CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET_MSK 0x000001c0 |
The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_CLR_MSK 0xfffffe3f |
The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_GET | ( | value | ) | (((value) & 0x000001c0) >> 6) |
Extracts the ALT_CLKMGR_PERPLL_DIV_CAN0CLK field value from a register.
#define ALT_CLKMGR_PERPLL_DIV_CAN0CLK_SET | ( | value | ) | (((value) << 6) & 0x000001c0) |
Produces a ALT_CLKMGR_PERPLL_DIV_CAN0CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV1 0x0 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Divide By 1
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV2 0x1 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Divide By 2
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV4 0x2 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Divide By 4
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV8 0x3 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Divide By 8
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_DIV16 0x4 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Divide By 16
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_1 0x5 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_2 0x6 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_E_RSVD_3 0x7 |
Enumerated value for register field ALT_CLKMGR_PERPLL_DIV_CAN1CLK
Reserved
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_WIDTH 3 |
The width in bits of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET_MSK 0x00000e00 |
The mask used to set the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_CLR_MSK 0xfffff1ff |
The mask used to clear the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_RESET 0x0 |
The reset value of the ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_GET | ( | value | ) | (((value) & 0x00000e00) >> 9) |
Extracts the ALT_CLKMGR_PERPLL_DIV_CAN1CLK field value from a register.
#define ALT_CLKMGR_PERPLL_DIV_CAN1CLK_SET | ( | value | ) | (((value) << 9) & 0x00000e00) |
Produces a ALT_CLKMGR_PERPLL_DIV_CAN1CLK register field value suitable for setting the register.
#define ALT_CLKMGR_PERPLL_DIV_OFST 0x24 |
The byte offset of the ALT_CLKMGR_PERPLL_DIV register from the beginning of the component.
typedef struct ALT_CLKMGR_PERPLL_DIV_s ALT_CLKMGR_PERPLL_DIV_t |
The typedef declaration for register ALT_CLKMGR_PERPLL_DIV.