Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : ddr_T_main_Probe_CfgCtl

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN
[1] R 0x0 ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT
[31:2] ??? Unknown UNDEFINED

Field : GLOBALEN

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_LSB   0
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_MSB   0
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_WIDTH   1
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET_MSK   0x00000001
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_CLR_MSK   0xfffffffe
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_RESET   0x0
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : ACTIVE

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_LSB   1
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_MSB   1
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_WIDTH   1
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET_MSK   0x00000002
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_CLR_MSK   0xfffffffd
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_RESET   0x0
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET(value)   (((value) << 1) & 0x00000002)
 

Data Structures

struct  ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s
 

Macros

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_RESET   0x00000000
 
#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_OFST   0xc
 

Typedefs

typedef struct
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s 
ALT_NOC_MPU_DDR_T_PRB_CFGCTL_t
 

Data Structure Documentation

struct ALT_NOC_MPU_DDR_T_PRB_CFGCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_CFGCTL.

Data Fields
uint32_t GLOBALEN: 1 ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN
const uint32_t ACTIVE: 1 ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT
uint32_t __pad0__: 30 UNDEFINED

Macro Definitions

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_WIDTH   1

The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET_MSK   0x00000001

The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_RESET   0x0

The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN field value from a register.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_NOC_MPU_DDR_T_PRB_CFGCTL_GLOBEN register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_LSB   1

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_MSB   1

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_WIDTH   1

The width in bits of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET_MSK   0x00000002

The mask used to set the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_CLR_MSK   0xfffffffd

The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_RESET   0x0

The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT field value from a register.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_NOC_MPU_DDR_T_PRB_CFGCTL_ACT register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_RESET   0x00000000

The reset value of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL register.

#define ALT_NOC_MPU_DDR_T_PRB_CFGCTL_OFST   0xc

The byte offset of the ALT_NOC_MPU_DDR_T_PRB_CFGCTL register from the beginning of the component.

Typedef Documentation