Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : mintsts

Description

Masked Interrupt Status Register

Register Layout

Bits Access Reset Description
[0] R 0x0 Card Detect
[1] R 0x0 Response Error
[2] R 0x0 Command Done
[3] R 0x0 Data Transfer Over
[4] R 0x0 Data TX FIFO Data Request
[5] R 0x0 Receive FIFO Data Request
[6] R 0x0 Response CRC Error
[7] R 0x0 Data CRC Error
[8] R 0x0 Response Timeout
[9] R 0x0 Data Read Timeout
[10] R 0x0 Data Starvation Host Timeout
[11] R 0x0 FIFO Underrun Overrun Error
[12] R 0x0 Hardware Locked Write Error
[13] R 0x0 Start-bit Error
[14] R 0x0 Auto Command Done
[15] R 0x0 End-bit Error
[31:16] R 0x0 ALT_SDMMC_MINTSTS_SDIO_INT

Field : Card Detect - cd

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_CD_E_MSK 0x0 Card Detected Mask
ALT_SDMMC_MINTSTS_CD_E_NOMSK 0x1 Card Detected No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_CD_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_CD_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_CD_LSB   0
 
#define ALT_SDMMC_MINTSTS_CD_MSB   0
 
#define ALT_SDMMC_MINTSTS_CD_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_CD_SET_MSK   0x00000001
 
#define ALT_SDMMC_MINTSTS_CD_CLR_MSK   0xfffffffe
 
#define ALT_SDMMC_MINTSTS_CD_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_CD_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SDMMC_MINTSTS_CD_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Response Error - resp

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_RESP_E_MSK 0x0 Response error Mask
ALT_SDMMC_MINTSTS_RESP_E_NOMSK 0x1 Response error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_RESP_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_RESP_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_RESP_LSB   1
 
#define ALT_SDMMC_MINTSTS_RESP_MSB   1
 
#define ALT_SDMMC_MINTSTS_RESP_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_RESP_SET_MSK   0x00000002
 
#define ALT_SDMMC_MINTSTS_RESP_CLR_MSK   0xfffffffd
 
#define ALT_SDMMC_MINTSTS_RESP_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_RESP_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SDMMC_MINTSTS_RESP_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Command Done - cmd_done

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK 0x0 Command Done Mask
ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK 0x1 Command Done No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_LSB   2
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_MSB   2
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK   0x00000004
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK   0xfffffffb
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SDMMC_MINTSTS_CMD_DONE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Data Transfer Over - dt

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_DT_E_MSK 0x0 Data transfer over Mask
ALT_SDMMC_MINTSTS_DT_E_NOMSK 0x1 Data transfer over No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_DT_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_DT_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_DT_LSB   3
 
#define ALT_SDMMC_MINTSTS_DT_MSB   3
 
#define ALT_SDMMC_MINTSTS_DT_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_DT_SET_MSK   0x00000008
 
#define ALT_SDMMC_MINTSTS_DT_CLR_MSK   0xfffffff7
 
#define ALT_SDMMC_MINTSTS_DT_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_DT_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SDMMC_MINTSTS_DT_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Data TX FIFO Data Request - dttxfifodr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK 0x0 Transmit FIFO data request Mask
ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK 0x1 Transmit FIFO data request No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB   4
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB   4
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK   0x00000010
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK   0xffffffef
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Receive FIFO Data Request - rxfifodr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK 0x0 Receive FIFO data request Mask
ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK 0x1 Receive FIFO data request No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_LSB   5
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_MSB   5
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK   0x00000020
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK   0xffffffdf
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SDMMC_MINTSTS_RXFIFODR_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Response CRC Error - respcrcerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK 0x0 Response CRC error Mask
ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK 0x1 Response CRC error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB   6
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB   6
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK   0x00000040
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK   0xffffffbf
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Data CRC Error - datacrcerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK 0x0 Data CRC error Mask
ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK 0x1 Data CRC error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_LSB   7
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_MSB   7
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK   0x00000080
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK   0xffffff7f
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SDMMC_MINTSTS_DATACRCERR_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Response Timeout - respto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_RESPTO_E_MSK 0x0 Response timeout Mask
ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK 0x1 Response timeout No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_RESPTO_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_RESPTO_LSB   8
 
#define ALT_SDMMC_MINTSTS_RESPTO_MSB   8
 
#define ALT_SDMMC_MINTSTS_RESPTO_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK   0x00000100
 
#define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK   0xfffffeff
 
#define ALT_SDMMC_MINTSTS_RESPTO_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_RESPTO_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SDMMC_MINTSTS_RESPTO_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Data Read Timeout - datardto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_DATARDTO_E_MSK 0x0 Data read timeout Mask
ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK 0x1 Data read timeout No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_DATARDTO_LSB   9
 
#define ALT_SDMMC_MINTSTS_DATARDTO_MSB   9
 
#define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK   0x00000200
 
#define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK   0xfffffdff
 
#define ALT_SDMMC_MINTSTS_DATARDTO_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_DATARDTO_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SDMMC_MINTSTS_DATARDTO_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Data Starvation Host Timeout - dshto

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_DSHTO_E_MSK 0x0 Data starvation by host timeout Mask
ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK 0x1 Data starvation by host timeout No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_DSHTO_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_DSHTO_LSB   10
 
#define ALT_SDMMC_MINTSTS_DSHTO_MSB   10
 
#define ALT_SDMMC_MINTSTS_DSHTO_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK   0x00000400
 
#define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK   0xfffffbff
 
#define ALT_SDMMC_MINTSTS_DSHTO_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_DSHTO_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SDMMC_MINTSTS_DSHTO_SET(value)   (((value) << 10) & 0x00000400)
 

Field : FIFO Underrun Overrun Error - fifoovunerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK 0x0 FIFO underrun/overrun error Mask
ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK 0x1 FIFO underrun/overrun error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB   11
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB   11
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK   0x00000800
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK   0xfffff7ff
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Hardware Locked Write Error - hlwerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_HLWERR_E_MSK 0x0 Hardware locked write error Mask
ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK 0x1 Hardware locked write error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_HLWERR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_HLWERR_LSB   12
 
#define ALT_SDMMC_MINTSTS_HLWERR_MSB   12
 
#define ALT_SDMMC_MINTSTS_HLWERR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK   0x00001000
 
#define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK   0xffffefff
 
#define ALT_SDMMC_MINTSTS_HLWERR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_HLWERR_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_SDMMC_MINTSTS_HLWERR_SET(value)   (((value) << 12) & 0x00001000)
 

Field : Start-bit Error - strerr

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_STRERR_E_MSK 0x0 Start-bit error Mask
ALT_SDMMC_MINTSTS_STRERR_E_NOMSK 0x1 Start-bit error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_STRERR_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_STRERR_LSB   13
 
#define ALT_SDMMC_MINTSTS_STRERR_MSB   13
 
#define ALT_SDMMC_MINTSTS_STRERR_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_STRERR_SET_MSK   0x00002000
 
#define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK   0xffffdfff
 
#define ALT_SDMMC_MINTSTS_STRERR_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_STRERR_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_SDMMC_MINTSTS_STRERR_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Auto Command Done - acd

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_ACD_E_MSK 0x0 Auto command done Mask
ALT_SDMMC_MINTSTS_ACD_E_NOMSK 0x1 Auto command done No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_ACD_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_ACD_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_ACD_LSB   14
 
#define ALT_SDMMC_MINTSTS_ACD_MSB   14
 
#define ALT_SDMMC_MINTSTS_ACD_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_ACD_SET_MSK   0x00004000
 
#define ALT_SDMMC_MINTSTS_ACD_CLR_MSK   0xffffbfff
 
#define ALT_SDMMC_MINTSTS_ACD_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_ACD_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_SDMMC_MINTSTS_ACD_SET(value)   (((value) << 14) & 0x00004000)
 

Field : End-bit Error - ebe

Interrupt enabled only if corresponding bit in interrupt mask register is set.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_EBE_E_MSK 0x0 End-bit error Mask
ALT_SDMMC_MINTSTS_EBE_E_NOMSK 0x1 End-bit error No Mask

Field Access Macros:

#define ALT_SDMMC_MINTSTS_EBE_E_MSK   0x0
 
#define ALT_SDMMC_MINTSTS_EBE_E_NOMSK   0x1
 
#define ALT_SDMMC_MINTSTS_EBE_LSB   15
 
#define ALT_SDMMC_MINTSTS_EBE_MSB   15
 
#define ALT_SDMMC_MINTSTS_EBE_WIDTH   1
 
#define ALT_SDMMC_MINTSTS_EBE_SET_MSK   0x00008000
 
#define ALT_SDMMC_MINTSTS_EBE_CLR_MSK   0xffff7fff
 
#define ALT_SDMMC_MINTSTS_EBE_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_EBE_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_SDMMC_MINTSTS_EBE_SET(value)   (((value) << 15) & 0x00008000)
 

Field : sdio_interrupt

Interrupt from SDIO card; one bit for each card. Bit[31] corresponds to Card[15], and bit[16] is for Card[0]. SDIO interrupt for card enabled only if corresponding sdio_int_mask bit is set in Interrupt mask register (mask bit 1 enables interrupt; 0 masks interrupt).

0-No SDIO interrupt from card

1-SDIO interrupt from card

In MMC-Ver3.3-only mode, bits always 0.

Field Enumeration Values:

Enum Value Description
ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT 0x0 No SDIO interrupt from card
ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT 0x1 SDIO interrupt from card

Field Access Macros:

#define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT   0x0
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT   0x1
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_LSB   16
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_MSB   31
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH   16
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK   0xffff0000
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK   0x0000ffff
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_RESET   0x0
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_SDMMC_MINTSTS_SDIO_INT_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_SDMMC_MINTSTS_s
 

Macros

#define ALT_SDMMC_MINTSTS_RESET   0x00000000
 
#define ALT_SDMMC_MINTSTS_OFST   0x40
 

Typedefs

typedef struct ALT_SDMMC_MINTSTS_s ALT_SDMMC_MINTSTS_t
 

Data Structure Documentation

struct ALT_SDMMC_MINTSTS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_MINTSTS.

Data Fields
const uint32_t cd: 1 Card Detect
const uint32_t resp: 1 Response Error
const uint32_t cmd_done: 1 Command Done
const uint32_t dt: 1 Data Transfer Over
const uint32_t dttxfifodr: 1 Data TX FIFO Data Request
const uint32_t rxfifodr: 1 Receive FIFO Data Request
const uint32_t respcrcerr: 1 Response CRC Error
const uint32_t datacrcerr: 1 Data CRC Error
const uint32_t respto: 1 Response Timeout
const uint32_t datardto: 1 Data Read Timeout
const uint32_t dshto: 1 Data Starvation Host Timeout
const uint32_t fifoovunerr: 1 FIFO Underrun Overrun Error
const uint32_t hlwerr: 1 Hardware Locked Write Error
const uint32_t strerr: 1 Start-bit Error
const uint32_t acd: 1 Auto Command Done
const uint32_t ebe: 1 End-bit Error
const uint32_t sdio_interrupt: 16 ALT_SDMMC_MINTSTS_SDIO_INT

Macro Definitions

#define ALT_SDMMC_MINTSTS_CD_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_CD

Card Detected Mask

#define ALT_SDMMC_MINTSTS_CD_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_CD

Card Detected No Mask

#define ALT_SDMMC_MINTSTS_CD_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CD register field.

#define ALT_SDMMC_MINTSTS_CD_MSB   0

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CD register field.

#define ALT_SDMMC_MINTSTS_CD_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_CD register field.

#define ALT_SDMMC_MINTSTS_CD_SET_MSK   0x00000001

The mask used to set the ALT_SDMMC_MINTSTS_CD register field value.

#define ALT_SDMMC_MINTSTS_CD_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SDMMC_MINTSTS_CD register field value.

#define ALT_SDMMC_MINTSTS_CD_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_CD register field.

#define ALT_SDMMC_MINTSTS_CD_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SDMMC_MINTSTS_CD field value from a register.

#define ALT_SDMMC_MINTSTS_CD_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SDMMC_MINTSTS_CD register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_RESP_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_RESP

Response error Mask

#define ALT_SDMMC_MINTSTS_RESP_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_RESP

Response error No Mask

#define ALT_SDMMC_MINTSTS_RESP_LSB   1

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESP register field.

#define ALT_SDMMC_MINTSTS_RESP_MSB   1

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESP register field.

#define ALT_SDMMC_MINTSTS_RESP_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_RESP register field.

#define ALT_SDMMC_MINTSTS_RESP_SET_MSK   0x00000002

The mask used to set the ALT_SDMMC_MINTSTS_RESP register field value.

#define ALT_SDMMC_MINTSTS_RESP_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SDMMC_MINTSTS_RESP register field value.

#define ALT_SDMMC_MINTSTS_RESP_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_RESP register field.

#define ALT_SDMMC_MINTSTS_RESP_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SDMMC_MINTSTS_RESP field value from a register.

#define ALT_SDMMC_MINTSTS_RESP_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SDMMC_MINTSTS_RESP register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_CMD_DONE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE

Command Done Mask

#define ALT_SDMMC_MINTSTS_CMD_DONE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_CMD_DONE

Command Done No Mask

#define ALT_SDMMC_MINTSTS_CMD_DONE_LSB   2

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field.

#define ALT_SDMMC_MINTSTS_CMD_DONE_MSB   2

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_CMD_DONE register field.

#define ALT_SDMMC_MINTSTS_CMD_DONE_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_CMD_DONE register field.

#define ALT_SDMMC_MINTSTS_CMD_DONE_SET_MSK   0x00000004

The mask used to set the ALT_SDMMC_MINTSTS_CMD_DONE register field value.

#define ALT_SDMMC_MINTSTS_CMD_DONE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SDMMC_MINTSTS_CMD_DONE register field value.

#define ALT_SDMMC_MINTSTS_CMD_DONE_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_CMD_DONE register field.

#define ALT_SDMMC_MINTSTS_CMD_DONE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SDMMC_MINTSTS_CMD_DONE field value from a register.

#define ALT_SDMMC_MINTSTS_CMD_DONE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SDMMC_MINTSTS_CMD_DONE register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_DT_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_DT

Data transfer over Mask

#define ALT_SDMMC_MINTSTS_DT_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_DT

Data transfer over No Mask

#define ALT_SDMMC_MINTSTS_DT_LSB   3

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DT register field.

#define ALT_SDMMC_MINTSTS_DT_MSB   3

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DT register field.

#define ALT_SDMMC_MINTSTS_DT_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_DT register field.

#define ALT_SDMMC_MINTSTS_DT_SET_MSK   0x00000008

The mask used to set the ALT_SDMMC_MINTSTS_DT register field value.

#define ALT_SDMMC_MINTSTS_DT_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SDMMC_MINTSTS_DT register field value.

#define ALT_SDMMC_MINTSTS_DT_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_DT register field.

#define ALT_SDMMC_MINTSTS_DT_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SDMMC_MINTSTS_DT field value from a register.

#define ALT_SDMMC_MINTSTS_DT_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SDMMC_MINTSTS_DT register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR

Transmit FIFO data request Mask

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_DTTXFIFODR

Transmit FIFO data request No Mask

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_LSB   4

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_MSB   4

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET_MSK   0x00000010

The mask used to set the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_CLR_MSK   0xffffffef

The mask used to clear the ALT_SDMMC_MINTSTS_DTTXFIFODR register field value.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_DTTXFIFODR register field.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SDMMC_MINTSTS_DTTXFIFODR field value from a register.

#define ALT_SDMMC_MINTSTS_DTTXFIFODR_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SDMMC_MINTSTS_DTTXFIFODR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_RXFIFODR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR

Receive FIFO data request Mask

#define ALT_SDMMC_MINTSTS_RXFIFODR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_RXFIFODR

Receive FIFO data request No Mask

#define ALT_SDMMC_MINTSTS_RXFIFODR_LSB   5

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field.

#define ALT_SDMMC_MINTSTS_RXFIFODR_MSB   5

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RXFIFODR register field.

#define ALT_SDMMC_MINTSTS_RXFIFODR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_RXFIFODR register field.

#define ALT_SDMMC_MINTSTS_RXFIFODR_SET_MSK   0x00000020

The mask used to set the ALT_SDMMC_MINTSTS_RXFIFODR register field value.

#define ALT_SDMMC_MINTSTS_RXFIFODR_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SDMMC_MINTSTS_RXFIFODR register field value.

#define ALT_SDMMC_MINTSTS_RXFIFODR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_RXFIFODR register field.

#define ALT_SDMMC_MINTSTS_RXFIFODR_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SDMMC_MINTSTS_RXFIFODR field value from a register.

#define ALT_SDMMC_MINTSTS_RXFIFODR_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SDMMC_MINTSTS_RXFIFODR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR

Response CRC error Mask

#define ALT_SDMMC_MINTSTS_RESPCRCERR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_RESPCRCERR

Response CRC error No Mask

#define ALT_SDMMC_MINTSTS_RESPCRCERR_LSB   6

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_MSB   6

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPCRCERR register field.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_RESPCRCERR register field.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET_MSK   0x00000040

The mask used to set the ALT_SDMMC_MINTSTS_RESPCRCERR register field value.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SDMMC_MINTSTS_RESPCRCERR register field value.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_RESPCRCERR register field.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SDMMC_MINTSTS_RESPCRCERR field value from a register.

#define ALT_SDMMC_MINTSTS_RESPCRCERR_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SDMMC_MINTSTS_RESPCRCERR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_DATACRCERR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR

Data CRC error Mask

#define ALT_SDMMC_MINTSTS_DATACRCERR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_DATACRCERR

Data CRC error No Mask

#define ALT_SDMMC_MINTSTS_DATACRCERR_LSB   7

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field.

#define ALT_SDMMC_MINTSTS_DATACRCERR_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATACRCERR register field.

#define ALT_SDMMC_MINTSTS_DATACRCERR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_DATACRCERR register field.

#define ALT_SDMMC_MINTSTS_DATACRCERR_SET_MSK   0x00000080

The mask used to set the ALT_SDMMC_MINTSTS_DATACRCERR register field value.

#define ALT_SDMMC_MINTSTS_DATACRCERR_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SDMMC_MINTSTS_DATACRCERR register field value.

#define ALT_SDMMC_MINTSTS_DATACRCERR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_DATACRCERR register field.

#define ALT_SDMMC_MINTSTS_DATACRCERR_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SDMMC_MINTSTS_DATACRCERR field value from a register.

#define ALT_SDMMC_MINTSTS_DATACRCERR_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SDMMC_MINTSTS_DATACRCERR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_RESPTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO

Response timeout Mask

#define ALT_SDMMC_MINTSTS_RESPTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_RESPTO

Response timeout No Mask

#define ALT_SDMMC_MINTSTS_RESPTO_LSB   8

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field.

#define ALT_SDMMC_MINTSTS_RESPTO_MSB   8

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_RESPTO register field.

#define ALT_SDMMC_MINTSTS_RESPTO_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_RESPTO register field.

#define ALT_SDMMC_MINTSTS_RESPTO_SET_MSK   0x00000100

The mask used to set the ALT_SDMMC_MINTSTS_RESPTO register field value.

#define ALT_SDMMC_MINTSTS_RESPTO_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SDMMC_MINTSTS_RESPTO register field value.

#define ALT_SDMMC_MINTSTS_RESPTO_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_RESPTO register field.

#define ALT_SDMMC_MINTSTS_RESPTO_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SDMMC_MINTSTS_RESPTO field value from a register.

#define ALT_SDMMC_MINTSTS_RESPTO_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SDMMC_MINTSTS_RESPTO register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_DATARDTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO

Data read timeout Mask

#define ALT_SDMMC_MINTSTS_DATARDTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_DATARDTO

Data read timeout No Mask

#define ALT_SDMMC_MINTSTS_DATARDTO_LSB   9

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field.

#define ALT_SDMMC_MINTSTS_DATARDTO_MSB   9

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DATARDTO register field.

#define ALT_SDMMC_MINTSTS_DATARDTO_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_DATARDTO register field.

#define ALT_SDMMC_MINTSTS_DATARDTO_SET_MSK   0x00000200

The mask used to set the ALT_SDMMC_MINTSTS_DATARDTO register field value.

#define ALT_SDMMC_MINTSTS_DATARDTO_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SDMMC_MINTSTS_DATARDTO register field value.

#define ALT_SDMMC_MINTSTS_DATARDTO_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_DATARDTO register field.

#define ALT_SDMMC_MINTSTS_DATARDTO_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SDMMC_MINTSTS_DATARDTO field value from a register.

#define ALT_SDMMC_MINTSTS_DATARDTO_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SDMMC_MINTSTS_DATARDTO register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_DSHTO_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO

Data starvation by host timeout Mask

#define ALT_SDMMC_MINTSTS_DSHTO_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_DSHTO

Data starvation by host timeout No Mask

#define ALT_SDMMC_MINTSTS_DSHTO_LSB   10

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field.

#define ALT_SDMMC_MINTSTS_DSHTO_MSB   10

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_DSHTO register field.

#define ALT_SDMMC_MINTSTS_DSHTO_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_DSHTO register field.

#define ALT_SDMMC_MINTSTS_DSHTO_SET_MSK   0x00000400

The mask used to set the ALT_SDMMC_MINTSTS_DSHTO register field value.

#define ALT_SDMMC_MINTSTS_DSHTO_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SDMMC_MINTSTS_DSHTO register field value.

#define ALT_SDMMC_MINTSTS_DSHTO_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_DSHTO register field.

#define ALT_SDMMC_MINTSTS_DSHTO_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SDMMC_MINTSTS_DSHTO field value from a register.

#define ALT_SDMMC_MINTSTS_DSHTO_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SDMMC_MINTSTS_DSHTO register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR

FIFO underrun/overrun error Mask

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_FIFOOVUNERR

FIFO underrun/overrun error No Mask

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_LSB   11

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_MSB   11

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET_MSK   0x00000800

The mask used to set the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_FIFOOVUNERR register field.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SDMMC_MINTSTS_FIFOOVUNERR field value from a register.

#define ALT_SDMMC_MINTSTS_FIFOOVUNERR_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SDMMC_MINTSTS_FIFOOVUNERR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_HLWERR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR

Hardware locked write error Mask

#define ALT_SDMMC_MINTSTS_HLWERR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_HLWERR

Hardware locked write error No Mask

#define ALT_SDMMC_MINTSTS_HLWERR_LSB   12

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field.

#define ALT_SDMMC_MINTSTS_HLWERR_MSB   12

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_HLWERR register field.

#define ALT_SDMMC_MINTSTS_HLWERR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_HLWERR register field.

#define ALT_SDMMC_MINTSTS_HLWERR_SET_MSK   0x00001000

The mask used to set the ALT_SDMMC_MINTSTS_HLWERR register field value.

#define ALT_SDMMC_MINTSTS_HLWERR_CLR_MSK   0xffffefff

The mask used to clear the ALT_SDMMC_MINTSTS_HLWERR register field value.

#define ALT_SDMMC_MINTSTS_HLWERR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_HLWERR register field.

#define ALT_SDMMC_MINTSTS_HLWERR_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_SDMMC_MINTSTS_HLWERR field value from a register.

#define ALT_SDMMC_MINTSTS_HLWERR_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_SDMMC_MINTSTS_HLWERR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_STRERR_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR

Start-bit error Mask

#define ALT_SDMMC_MINTSTS_STRERR_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_STRERR

Start-bit error No Mask

#define ALT_SDMMC_MINTSTS_STRERR_LSB   13

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_STRERR register field.

#define ALT_SDMMC_MINTSTS_STRERR_MSB   13

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_STRERR register field.

#define ALT_SDMMC_MINTSTS_STRERR_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_STRERR register field.

#define ALT_SDMMC_MINTSTS_STRERR_SET_MSK   0x00002000

The mask used to set the ALT_SDMMC_MINTSTS_STRERR register field value.

#define ALT_SDMMC_MINTSTS_STRERR_CLR_MSK   0xffffdfff

The mask used to clear the ALT_SDMMC_MINTSTS_STRERR register field value.

#define ALT_SDMMC_MINTSTS_STRERR_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_STRERR register field.

#define ALT_SDMMC_MINTSTS_STRERR_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_SDMMC_MINTSTS_STRERR field value from a register.

#define ALT_SDMMC_MINTSTS_STRERR_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_SDMMC_MINTSTS_STRERR register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_ACD_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_ACD

Auto command done Mask

#define ALT_SDMMC_MINTSTS_ACD_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_ACD

Auto command done No Mask

#define ALT_SDMMC_MINTSTS_ACD_LSB   14

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_ACD register field.

#define ALT_SDMMC_MINTSTS_ACD_MSB   14

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_ACD register field.

#define ALT_SDMMC_MINTSTS_ACD_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_ACD register field.

#define ALT_SDMMC_MINTSTS_ACD_SET_MSK   0x00004000

The mask used to set the ALT_SDMMC_MINTSTS_ACD register field value.

#define ALT_SDMMC_MINTSTS_ACD_CLR_MSK   0xffffbfff

The mask used to clear the ALT_SDMMC_MINTSTS_ACD register field value.

#define ALT_SDMMC_MINTSTS_ACD_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_ACD register field.

#define ALT_SDMMC_MINTSTS_ACD_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_SDMMC_MINTSTS_ACD field value from a register.

#define ALT_SDMMC_MINTSTS_ACD_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_SDMMC_MINTSTS_ACD register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_EBE_E_MSK   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_EBE

End-bit error Mask

#define ALT_SDMMC_MINTSTS_EBE_E_NOMSK   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_EBE

End-bit error No Mask

#define ALT_SDMMC_MINTSTS_EBE_LSB   15

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_EBE register field.

#define ALT_SDMMC_MINTSTS_EBE_MSB   15

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_EBE register field.

#define ALT_SDMMC_MINTSTS_EBE_WIDTH   1

The width in bits of the ALT_SDMMC_MINTSTS_EBE register field.

#define ALT_SDMMC_MINTSTS_EBE_SET_MSK   0x00008000

The mask used to set the ALT_SDMMC_MINTSTS_EBE register field value.

#define ALT_SDMMC_MINTSTS_EBE_CLR_MSK   0xffff7fff

The mask used to clear the ALT_SDMMC_MINTSTS_EBE register field value.

#define ALT_SDMMC_MINTSTS_EBE_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_EBE register field.

#define ALT_SDMMC_MINTSTS_EBE_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_SDMMC_MINTSTS_EBE field value from a register.

#define ALT_SDMMC_MINTSTS_EBE_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_SDMMC_MINTSTS_EBE register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_SDIO_INT_E_INACT   0x0

Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT

No SDIO interrupt from card

#define ALT_SDMMC_MINTSTS_SDIO_INT_E_ACT   0x1

Enumerated value for register field ALT_SDMMC_MINTSTS_SDIO_INT

SDIO interrupt from card

#define ALT_SDMMC_MINTSTS_SDIO_INT_LSB   16

The Least Significant Bit (LSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field.

#define ALT_SDMMC_MINTSTS_SDIO_INT_MSB   31

The Most Significant Bit (MSB) position of the ALT_SDMMC_MINTSTS_SDIO_INT register field.

#define ALT_SDMMC_MINTSTS_SDIO_INT_WIDTH   16

The width in bits of the ALT_SDMMC_MINTSTS_SDIO_INT register field.

#define ALT_SDMMC_MINTSTS_SDIO_INT_SET_MSK   0xffff0000

The mask used to set the ALT_SDMMC_MINTSTS_SDIO_INT register field value.

#define ALT_SDMMC_MINTSTS_SDIO_INT_CLR_MSK   0x0000ffff

The mask used to clear the ALT_SDMMC_MINTSTS_SDIO_INT register field value.

#define ALT_SDMMC_MINTSTS_SDIO_INT_RESET   0x0

The reset value of the ALT_SDMMC_MINTSTS_SDIO_INT register field.

#define ALT_SDMMC_MINTSTS_SDIO_INT_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_SDMMC_MINTSTS_SDIO_INT field value from a register.

#define ALT_SDMMC_MINTSTS_SDIO_INT_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_SDMMC_MINTSTS_SDIO_INT register field value suitable for setting the register.

#define ALT_SDMMC_MINTSTS_RESET   0x00000000

The reset value of the ALT_SDMMC_MINTSTS register.

#define ALT_SDMMC_MINTSTS_OFST   0x40

The byte offset of the ALT_SDMMC_MINTSTS register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_MINTSTS.