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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
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[0] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN |
[1] | RW | 0x0 | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN |
[31:2] | ??? | 0x0 | UNDEFINED |
Field : cfg_short_dqstrk_ctrl_en | |
Set to 1 to enable controller controlled DQS short tracking, Set to 0 to enable sequencer controlled DQS short tracking Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_LSB 0 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_MSB 0 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET_MSK 0x00000001 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_CLR_MSK 0xfffffffe |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : cfg_period_dqstrk_ctrl_en | |
Set to 1 to enable controller to issue periodic DQS tracking Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_LSB 1 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_MSB 1 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET_MSK 0x00000002 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_CLR_MSK 0xfffffffd |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET(value) (((value) << 1) & 0x00000002) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_SBCFG5_s |
Macros | |
#define | ALT_IO48_HMC_MMR_SBCFG5_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_SBCFG5_OFST 0x70 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_SBCFG5_s | ALT_IO48_HMC_MMR_SBCFG5_t |
struct ALT_IO48_HMC_MMR_SBCFG5_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_SBCFG5.
Data Fields | ||
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uint32_t | cfg_short_dqstrk_ctrl_en: 1 | ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN |
uint32_t | cfg_period_dqstrk_ctrl_en: 1 | ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN |
uint32_t | __pad0__: 30 | UNDEFINED |
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_IO48_HMC_MMR_SBCFG5_CFG_SHORT_DQSTRK_CTL_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET_MSK 0x00000002 |
The mask used to set the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN field value from a register.
#define ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_IO48_HMC_MMR_SBCFG5_CFG_PERIOD_DQSTRK_CTL_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_SBCFG5_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_SBCFG5 register.
#define ALT_IO48_HMC_MMR_SBCFG5_OFST 0x70 |
The byte offset of the ALT_IO48_HMC_MMR_SBCFG5 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_SBCFG5_s ALT_IO48_HMC_MMR_SBCFG5_t |
The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG5.