Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : caltiming5

Description

Register Layout

Bits Access Reset Description
[9:0] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID
[19:10] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL
[31:20] ??? 0x0 UNDEFINED

Field : cfg_t_param_srf_to_valid

Self-refresh to valid bank command window.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB   0
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB   9
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH   10
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK   0x000003ff
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK   0xfffffc00
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET(value)   (((value) & 0x000003ff) >> 0)
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET(value)   (((value) << 0) & 0x000003ff)
 

Field : cfg_t_param_srf_to_zq_cal

Self refresh to ZQ calibration window

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB   10
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB   19
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH   10
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK   0x000ffc00
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK   0xfff003ff
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET(value)   (((value) & 0x000ffc00) >> 10)
 
#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET(value)   (((value) << 10) & 0x000ffc00)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CALTIMING5_s
 

Macros

#define ALT_IO48_HMC_MMR_CALTIMING5_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CALTIMING5_OFST   0x90
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CALTIMING5_s 
ALT_IO48_HMC_MMR_CALTIMING5_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CALTIMING5_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING5.

Data Fields
uint32_t cfg_t_param_srf_to_valid: 10 ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID
uint32_t cfg_t_param_srf_to_zq_cal: 10 ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL
uint32_t __pad0__: 12 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_MSB   9

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_WIDTH   10

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET_MSK   0x000003ff

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_CLR_MSK   0xfffffc00

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_GET (   value)    (((value) & 0x000003ff) >> 0)

Extracts the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID_SET (   value)    (((value) << 0) & 0x000003ff)

Produces a ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_LSB   10

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_MSB   19

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_WIDTH   10

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET_MSK   0x000ffc00

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_CLR_MSK   0xfff003ff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_GET (   value)    (((value) & 0x000ffc00) >> 10)

Extracts the ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL_SET (   value)    (((value) << 10) & 0x000ffc00)

Produces a ALT_IO48_HMC_MMR_CALTIMING5_CFG_T_PARAM_SRF_TO_ZQ_CAL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING5_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CALTIMING5 register.

#define ALT_IO48_HMC_MMR_CALTIMING5_OFST   0x90

The byte offset of the ALT_IO48_HMC_MMR_CALTIMING5 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING5.