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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Modem Status Register
It should be noted that whenever bits 0, 1, 2 or 3 is set to logic one, to indicate
a change on the modem control inputs, a modem status interrupt will be generated
if enabled via the IER regardless of when the change occurred. Since the delta bits
(bits 0, 1, 3) can get set after a reset if their respective modem signals are
active (see individual bits for details), a read of the MSR after reset can be
performed to prevent unwanted interrupts.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | ALT_UART_MSR_DCTS |
[1] | R | 0x0 | ALT_UART_MSR_DDSR |
[2] | R | 0x0 | ALT_UART_MSR_TERI |
[3] | R | 0x0 | ALT_UART_MSR_DDCD |
[4] | R | 0x0 | ALT_UART_MSR_CTS |
[5] | R | 0x0 | ALT_UART_MSR_DSR |
[6] | R | 0x0 | ALT_UART_MSR_RI |
[7] | R | 0x0 | ALT_UART_MSR_DCD |
[31:8] | R | 0x0 | ALT_UART_MSR_RSVD_MSC_31TO8 |
Field : dcts | ||||||||||
Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. That is: 0 = no change on cts_n since last read of MSR 1 = change on cts_n since last read of MSR Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one), DCTS reflects changes on MCR[1] (RTS). Note, if the DCTS bit is not set and the cts_n signal is asserted (low) and a reset occurs (software or otherwise), then the DCTS bit will get set when the reset is removed if the cts_n signal remains asserted. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_DCTS_E_NOCHG 0x0 | |||||||||
#define | ALT_UART_MSR_DCTS_E_CHG 0x1 | |||||||||
#define | ALT_UART_MSR_DCTS_LSB 0 | |||||||||
#define | ALT_UART_MSR_DCTS_MSB 0 | |||||||||
#define | ALT_UART_MSR_DCTS_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_DCTS_SET_MSK 0x00000001 | |||||||||
#define | ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_UART_MSR_DCTS_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_DCTS_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_UART_MSR_DCTS_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : ddsr | ||||||||||
Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. That is: 0 = no change on dsr_n since last read of MSR 1 = change on dsr_n since last read of MSR Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] set to one), DDSR reflects changes on MCR[0] (DTR). Note, if the DDSR bit is not set and the dsr_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDSR bit will get set when the reset is removed if the dsr_n signal remains asserted. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_DDSR_E_NOCHG 0x0 | |||||||||
#define | ALT_UART_MSR_DDSR_E_CHG 0x1 | |||||||||
#define | ALT_UART_MSR_DDSR_LSB 1 | |||||||||
#define | ALT_UART_MSR_DDSR_MSB 1 | |||||||||
#define | ALT_UART_MSR_DDSR_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_DDSR_SET_MSK 0x00000002 | |||||||||
#define | ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_UART_MSR_DDSR_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_DDSR_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_UART_MSR_DDSR_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : teri | ||||||||||
Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active low, to an inactive high state) has occurred since the last time the MSR was read. That is: 0 = no change on ri_n since last read of MSR 1 = change on ri_n since last read of MSR Reading the MSR clears the TERI bit. In Loopback Mode (MCR[4] set to one), TERI reflects when MCR[2] (Out1) has changed state from a high to a low. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_TERI_E_NOCHG 0x0 | |||||||||
#define | ALT_UART_MSR_TERI_E_CHG 0x1 | |||||||||
#define | ALT_UART_MSR_TERI_LSB 2 | |||||||||
#define | ALT_UART_MSR_TERI_MSB 2 | |||||||||
#define | ALT_UART_MSR_TERI_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_TERI_SET_MSK 0x00000004 | |||||||||
#define | ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_UART_MSR_TERI_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_TERI_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_UART_MSR_TERI_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : ddcd | ||||||||||
Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. That is: 0 = no change on dcd_n since last read of MSR 1 = change on dcd_n since last read of MSR Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one), DDCD reflects changes on MCR[3] (Out2). Note, if the DDCD bit is not set and the dcd_n signal is asserted (low) and a reset occurs (software or otherwise), then the DDCD bit will get set when the reset is removed if the dcd_n signal remains asserted. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_DDCD_E_NOCHG 0x0 | |||||||||
#define | ALT_UART_MSR_DDCD_E_CHG 0x1 | |||||||||
#define | ALT_UART_MSR_DDCD_LSB 3 | |||||||||
#define | ALT_UART_MSR_DDCD_MSB 3 | |||||||||
#define | ALT_UART_MSR_DDCD_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_DDCD_SET_MSK 0x00000008 | |||||||||
#define | ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_UART_MSR_DDCD_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_DDCD_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_UART_MSR_DDCD_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : cts | ||||||||||
Clear to Send. This is used to indicate the current state of the modem control line cts_n. That is, this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange data with the DW_apb_uart. 0 = cts_n input is de-asserted (logic 1) 1 = cts_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), CTS is the same as MCR[1] (RTS). Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_CTS_E_LOGIC1 0x0 | |||||||||
#define | ALT_UART_MSR_CTS_E_LOGIC0 0x1 | |||||||||
#define | ALT_UART_MSR_CTS_LSB 4 | |||||||||
#define | ALT_UART_MSR_CTS_MSB 4 | |||||||||
#define | ALT_UART_MSR_CTS_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_CTS_SET_MSK 0x00000010 | |||||||||
#define | ALT_UART_MSR_CTS_CLR_MSK 0xffffffef | |||||||||
#define | ALT_UART_MSR_CTS_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_CTS_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_UART_MSR_CTS_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : dsr | ||||||||||
Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to establish communications with the DW_apb_uart. 0 = dsr_n input is de-asserted (logic 1) 1 = dsr_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DSR is the same as MCR[0] (DTR). Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_DSR_E_LOGIC1 0x0 | |||||||||
#define | ALT_UART_MSR_DSR_E_LOGIC0 0x1 | |||||||||
#define | ALT_UART_MSR_DSR_LSB 5 | |||||||||
#define | ALT_UART_MSR_DSR_MSB 5 | |||||||||
#define | ALT_UART_MSR_DSR_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_DSR_SET_MSK 0x00000020 | |||||||||
#define | ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_UART_MSR_DSR_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_DSR_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_UART_MSR_DSR_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : ri | ||||||||||
Ring Indicator. This is used to indicate the current state of the modem control line ri_n. That is this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received by the modem or data set. 0 = ri_n input is de-asserted (logic 1) 1 = ri_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), RI is the same as MCR[2] (Out1). Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_RI_E_LOGIC1 0x0 | |||||||||
#define | ALT_UART_MSR_RI_E_LOGIC0 0x1 | |||||||||
#define | ALT_UART_MSR_RI_LSB 6 | |||||||||
#define | ALT_UART_MSR_RI_MSB 6 | |||||||||
#define | ALT_UART_MSR_RI_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_RI_SET_MSK 0x00000040 | |||||||||
#define | ALT_UART_MSR_RI_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_UART_MSR_RI_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_RI_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_UART_MSR_RI_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : dcd | ||||||||||
Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected by the modem or data set. 0 = dcd_n input is de-asserted (logic 1) 1 = dcd_n input is asserted (logic 0) In Loopback Mode (MCR[4] set to one), DCD is the same as MCR[3] (Out2). Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_MSR_DCD_E_LOGIC1 0x0 | |||||||||
#define | ALT_UART_MSR_DCD_E_LOGIC0 0x1 | |||||||||
#define | ALT_UART_MSR_DCD_LSB 7 | |||||||||
#define | ALT_UART_MSR_DCD_MSB 7 | |||||||||
#define | ALT_UART_MSR_DCD_WIDTH 1 | |||||||||
#define | ALT_UART_MSR_DCD_SET_MSK 0x00000080 | |||||||||
#define | ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_UART_MSR_DCD_RESET 0x0 | |||||||||
#define | ALT_UART_MSR_DCD_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_UART_MSR_DCD_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : rsvd_msc_31to8 | |
Reserved bits [31:8] - Read Only Field Access Macros: | |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_LSB 8 |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_MSB 31 |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_WIDTH 24 |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_SET_MSK 0xffffff00 |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_CLR_MSK 0x000000ff |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_RESET 0x0 |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_GET(value) (((value) & 0xffffff00) >> 8) |
#define | ALT_UART_MSR_RSVD_MSC_31TO8_SET(value) (((value) << 8) & 0xffffff00) |
Data Structures | |
struct | ALT_UART_MSR_s |
Macros | |
#define | ALT_UART_MSR_RESET 0x00000000 |
#define | ALT_UART_MSR_OFST 0x18 |
#define | ALT_UART_MSR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) |
Typedefs | |
typedef struct ALT_UART_MSR_s | ALT_UART_MSR_t |
struct ALT_UART_MSR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_UART_MSR.
Data Fields | ||
---|---|---|
const uint32_t | dcts: 1 | ALT_UART_MSR_DCTS |
const uint32_t | ddsr: 1 | ALT_UART_MSR_DDSR |
const uint32_t | teri: 1 | ALT_UART_MSR_TERI |
const uint32_t | ddcd: 1 | ALT_UART_MSR_DDCD |
const uint32_t | cts: 1 | ALT_UART_MSR_CTS |
const uint32_t | dsr: 1 | ALT_UART_MSR_DSR |
const uint32_t | ri: 1 | ALT_UART_MSR_RI |
const uint32_t | dcd: 1 | ALT_UART_MSR_DCD |
const uint32_t | rsvd_msc_31to8: 24 | ALT_UART_MSR_RSVD_MSC_31TO8 |
#define ALT_UART_MSR_DCTS_E_NOCHG 0x0 |
Enumerated value for register field ALT_UART_MSR_DCTS
no change on uart_cts_n since last read of MSR
#define ALT_UART_MSR_DCTS_E_CHG 0x1 |
Enumerated value for register field ALT_UART_MSR_DCTS
change on uart_cts_n since last read of MSR
#define ALT_UART_MSR_DCTS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCTS register field.
#define ALT_UART_MSR_DCTS_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCTS register field.
#define ALT_UART_MSR_DCTS_WIDTH 1 |
The width in bits of the ALT_UART_MSR_DCTS register field.
#define ALT_UART_MSR_DCTS_SET_MSK 0x00000001 |
The mask used to set the ALT_UART_MSR_DCTS register field value.
#define ALT_UART_MSR_DCTS_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_UART_MSR_DCTS register field value.
#define ALT_UART_MSR_DCTS_RESET 0x0 |
The reset value of the ALT_UART_MSR_DCTS register field.
#define ALT_UART_MSR_DCTS_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_UART_MSR_DCTS field value from a register.
#define ALT_UART_MSR_DCTS_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_UART_MSR_DCTS register field value suitable for setting the register.
#define ALT_UART_MSR_DDSR_E_NOCHG 0x0 |
Enumerated value for register field ALT_UART_MSR_DDSR
no change on uart_dsr_n since last read of MSR
#define ALT_UART_MSR_DDSR_E_CHG 0x1 |
Enumerated value for register field ALT_UART_MSR_DDSR
change on uart_dsr_n since last read of MSR
#define ALT_UART_MSR_DDSR_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDSR register field.
#define ALT_UART_MSR_DDSR_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDSR register field.
#define ALT_UART_MSR_DDSR_WIDTH 1 |
The width in bits of the ALT_UART_MSR_DDSR register field.
#define ALT_UART_MSR_DDSR_SET_MSK 0x00000002 |
The mask used to set the ALT_UART_MSR_DDSR register field value.
#define ALT_UART_MSR_DDSR_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_UART_MSR_DDSR register field value.
#define ALT_UART_MSR_DDSR_RESET 0x0 |
The reset value of the ALT_UART_MSR_DDSR register field.
#define ALT_UART_MSR_DDSR_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_UART_MSR_DDSR field value from a register.
#define ALT_UART_MSR_DDSR_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_UART_MSR_DDSR register field value suitable for setting the register.
#define ALT_UART_MSR_TERI_E_NOCHG 0x0 |
Enumerated value for register field ALT_UART_MSR_TERI
no change on uart_ri_n since last read of MSR
#define ALT_UART_MSR_TERI_E_CHG 0x1 |
Enumerated value for register field ALT_UART_MSR_TERI
change on uart_ri_n since last read of MSR
#define ALT_UART_MSR_TERI_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_TERI register field.
#define ALT_UART_MSR_TERI_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_TERI register field.
#define ALT_UART_MSR_TERI_WIDTH 1 |
The width in bits of the ALT_UART_MSR_TERI register field.
#define ALT_UART_MSR_TERI_SET_MSK 0x00000004 |
The mask used to set the ALT_UART_MSR_TERI register field value.
#define ALT_UART_MSR_TERI_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_UART_MSR_TERI register field value.
#define ALT_UART_MSR_TERI_RESET 0x0 |
The reset value of the ALT_UART_MSR_TERI register field.
#define ALT_UART_MSR_TERI_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_UART_MSR_TERI field value from a register.
#define ALT_UART_MSR_TERI_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_UART_MSR_TERI register field value suitable for setting the register.
#define ALT_UART_MSR_DDCD_E_NOCHG 0x0 |
Enumerated value for register field ALT_UART_MSR_DDCD
no change on uart_dcd_n since last read of MSR
#define ALT_UART_MSR_DDCD_E_CHG 0x1 |
Enumerated value for register field ALT_UART_MSR_DDCD
change on uart_dcd_n since last read of MSR
#define ALT_UART_MSR_DDCD_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_DDCD register field.
#define ALT_UART_MSR_DDCD_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_DDCD register field.
#define ALT_UART_MSR_DDCD_WIDTH 1 |
The width in bits of the ALT_UART_MSR_DDCD register field.
#define ALT_UART_MSR_DDCD_SET_MSK 0x00000008 |
The mask used to set the ALT_UART_MSR_DDCD register field value.
#define ALT_UART_MSR_DDCD_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_UART_MSR_DDCD register field value.
#define ALT_UART_MSR_DDCD_RESET 0x0 |
The reset value of the ALT_UART_MSR_DDCD register field.
#define ALT_UART_MSR_DDCD_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_UART_MSR_DDCD field value from a register.
#define ALT_UART_MSR_DDCD_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_UART_MSR_DDCD register field value suitable for setting the register.
#define ALT_UART_MSR_CTS_E_LOGIC1 0x0 |
Enumerated value for register field ALT_UART_MSR_CTS
uart_cts_n input is de-asserted (logic 1)
#define ALT_UART_MSR_CTS_E_LOGIC0 0x1 |
Enumerated value for register field ALT_UART_MSR_CTS
uart_cts_n input is asserted (logic 0)
#define ALT_UART_MSR_CTS_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_CTS register field.
#define ALT_UART_MSR_CTS_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_CTS register field.
#define ALT_UART_MSR_CTS_WIDTH 1 |
The width in bits of the ALT_UART_MSR_CTS register field.
#define ALT_UART_MSR_CTS_SET_MSK 0x00000010 |
The mask used to set the ALT_UART_MSR_CTS register field value.
#define ALT_UART_MSR_CTS_CLR_MSK 0xffffffef |
The mask used to clear the ALT_UART_MSR_CTS register field value.
#define ALT_UART_MSR_CTS_RESET 0x0 |
The reset value of the ALT_UART_MSR_CTS register field.
#define ALT_UART_MSR_CTS_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_UART_MSR_CTS field value from a register.
#define ALT_UART_MSR_CTS_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_UART_MSR_CTS register field value suitable for setting the register.
#define ALT_UART_MSR_DSR_E_LOGIC1 0x0 |
Enumerated value for register field ALT_UART_MSR_DSR
uart_dsr_n input is de-asserted (logic 1)
#define ALT_UART_MSR_DSR_E_LOGIC0 0x1 |
Enumerated value for register field ALT_UART_MSR_DSR
uart_dsr_n input is asserted (logic 0)
#define ALT_UART_MSR_DSR_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_DSR register field.
#define ALT_UART_MSR_DSR_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_DSR register field.
#define ALT_UART_MSR_DSR_WIDTH 1 |
The width in bits of the ALT_UART_MSR_DSR register field.
#define ALT_UART_MSR_DSR_SET_MSK 0x00000020 |
The mask used to set the ALT_UART_MSR_DSR register field value.
#define ALT_UART_MSR_DSR_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_UART_MSR_DSR register field value.
#define ALT_UART_MSR_DSR_RESET 0x0 |
The reset value of the ALT_UART_MSR_DSR register field.
#define ALT_UART_MSR_DSR_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_UART_MSR_DSR field value from a register.
#define ALT_UART_MSR_DSR_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_UART_MSR_DSR register field value suitable for setting the register.
#define ALT_UART_MSR_RI_E_LOGIC1 0x0 |
Enumerated value for register field ALT_UART_MSR_RI
uart_ri_n input is de-asserted (logic 1)
#define ALT_UART_MSR_RI_E_LOGIC0 0x1 |
Enumerated value for register field ALT_UART_MSR_RI
uart_ri_n input is asserted (logic 0)
#define ALT_UART_MSR_RI_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_RI register field.
#define ALT_UART_MSR_RI_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_RI register field.
#define ALT_UART_MSR_RI_WIDTH 1 |
The width in bits of the ALT_UART_MSR_RI register field.
#define ALT_UART_MSR_RI_SET_MSK 0x00000040 |
The mask used to set the ALT_UART_MSR_RI register field value.
#define ALT_UART_MSR_RI_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_UART_MSR_RI register field value.
#define ALT_UART_MSR_RI_RESET 0x0 |
The reset value of the ALT_UART_MSR_RI register field.
#define ALT_UART_MSR_RI_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_UART_MSR_RI field value from a register.
#define ALT_UART_MSR_RI_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_UART_MSR_RI register field value suitable for setting the register.
#define ALT_UART_MSR_DCD_E_LOGIC1 0x0 |
Enumerated value for register field ALT_UART_MSR_DCD
uart_dcd_n input is de-asserted (logic 1)
#define ALT_UART_MSR_DCD_E_LOGIC0 0x1 |
Enumerated value for register field ALT_UART_MSR_DCD
uart_dcd_n input is asserted (logic 0)
#define ALT_UART_MSR_DCD_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_DCD register field.
#define ALT_UART_MSR_DCD_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_DCD register field.
#define ALT_UART_MSR_DCD_WIDTH 1 |
The width in bits of the ALT_UART_MSR_DCD register field.
#define ALT_UART_MSR_DCD_SET_MSK 0x00000080 |
The mask used to set the ALT_UART_MSR_DCD register field value.
#define ALT_UART_MSR_DCD_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_UART_MSR_DCD register field value.
#define ALT_UART_MSR_DCD_RESET 0x0 |
The reset value of the ALT_UART_MSR_DCD register field.
#define ALT_UART_MSR_DCD_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_UART_MSR_DCD field value from a register.
#define ALT_UART_MSR_DCD_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_UART_MSR_DCD register field value suitable for setting the register.
#define ALT_UART_MSR_RSVD_MSC_31TO8_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_UART_MSR_RSVD_MSC_31TO8 register field.
#define ALT_UART_MSR_RSVD_MSC_31TO8_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_UART_MSR_RSVD_MSC_31TO8 register field.
#define ALT_UART_MSR_RSVD_MSC_31TO8_WIDTH 24 |
The width in bits of the ALT_UART_MSR_RSVD_MSC_31TO8 register field.
#define ALT_UART_MSR_RSVD_MSC_31TO8_SET_MSK 0xffffff00 |
The mask used to set the ALT_UART_MSR_RSVD_MSC_31TO8 register field value.
#define ALT_UART_MSR_RSVD_MSC_31TO8_CLR_MSK 0x000000ff |
The mask used to clear the ALT_UART_MSR_RSVD_MSC_31TO8 register field value.
#define ALT_UART_MSR_RSVD_MSC_31TO8_RESET 0x0 |
The reset value of the ALT_UART_MSR_RSVD_MSC_31TO8 register field.
#define ALT_UART_MSR_RSVD_MSC_31TO8_GET | ( | value | ) | (((value) & 0xffffff00) >> 8) |
Extracts the ALT_UART_MSR_RSVD_MSC_31TO8 field value from a register.
#define ALT_UART_MSR_RSVD_MSC_31TO8_SET | ( | value | ) | (((value) << 8) & 0xffffff00) |
Produces a ALT_UART_MSR_RSVD_MSC_31TO8 register field value suitable for setting the register.
#define ALT_UART_MSR_RESET 0x00000000 |
The reset value of the ALT_UART_MSR register.
#define ALT_UART_MSR_OFST 0x18 |
The byte offset of the ALT_UART_MSR register from the beginning of the component.
#define ALT_UART_MSR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_MSR_OFST)) |
The address of the ALT_UART_MSR register.
typedef struct ALT_UART_MSR_s ALT_UART_MSR_t |
The typedef declaration for register ALT_UART_MSR.