Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : caltiming4

Description

Register Layout

Bits Access Reset Description
[5:0] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID
[11:6] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID
[17:12] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID
[25:18] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID
[31:26] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID

Field : cfg_t_param_wr_ap_to_valid

Write with autoprecharge to valid command timing.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB   0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB   5
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH   6
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK   0x0000003f
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK   0xffffffc0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET(value)   (((value) & 0x0000003f) >> 0)
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET(value)   (((value) << 0) & 0x0000003f)
 

Field : cfg_t_param_pch_to_valid

Precharge to valid command timing.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB   6
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB   11
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH   6
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK   0x00000fc0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK   0xfffff03f
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET(value)   (((value) & 0x00000fc0) >> 6)
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET(value)   (((value) << 6) & 0x00000fc0)
 

Field : cfg_t_param_pch_all_to_valid

Precharge all to banks being ready for bank activation command.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB   12
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB   17
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH   6
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK   0x0003f000
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK   0xfffc0fff
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET(value)   (((value) & 0x0003f000) >> 12)
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET(value)   (((value) << 12) & 0x0003f000)
 

Field : cfg_t_param_arf_to_valid

Auto Refresh to valid DRAM command window.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB   18
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB   25
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH   8
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK   0x03fc0000
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK   0xfc03ffff
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET(value)   (((value) & 0x03fc0000) >> 18)
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET(value)   (((value) << 18) & 0x03fc0000)
 

Field : cfg_t_param_pdn_to_valid

Power down to valid bank command window.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB   26
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB   31
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH   6
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK   0xfc000000
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK   0x03ffffff
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET(value)   (((value) & 0xfc000000) >> 26)
 
#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET(value)   (((value) << 26) & 0xfc000000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CALTIMING4_s
 

Macros

#define ALT_IO48_HMC_MMR_CALTIMING4_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CALTIMING4_OFST   0x8c
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CALTIMING4_s 
ALT_IO48_HMC_MMR_CALTIMING4_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CALTIMING4_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING4.

Data Fields
uint32_t cfg_t_param_wr_ap_to_valid: 6 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID
uint32_t cfg_t_param_pch_to_valid: 6 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID
uint32_t cfg_t_param_pch_all_to_valid: 6 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID
uint32_t cfg_t_param_arf_to_valid: 8 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID
uint32_t cfg_t_param_pdn_to_valid: 6 ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID

Macro Definitions

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_MSB   5

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET_MSK   0x0000003f

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_CLR_MSK   0xffffffc0

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_GET (   value)    (((value) & 0x0000003f) >> 0)

Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID_SET (   value)    (((value) << 0) & 0x0000003f)

Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_WR_AP_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_LSB   6

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_MSB   11

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET_MSK   0x00000fc0

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_CLR_MSK   0xfffff03f

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_GET (   value)    (((value) & 0x00000fc0) >> 6)

Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID_SET (   value)    (((value) << 6) & 0x00000fc0)

Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_LSB   12

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_MSB   17

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET_MSK   0x0003f000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_CLR_MSK   0xfffc0fff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_GET (   value)    (((value) & 0x0003f000) >> 12)

Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID_SET (   value)    (((value) << 12) & 0x0003f000)

Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PCH_ALL_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_LSB   18

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_MSB   25

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_WIDTH   8

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET_MSK   0x03fc0000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_CLR_MSK   0xfc03ffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_GET (   value)    (((value) & 0x03fc0000) >> 18)

Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID_SET (   value)    (((value) << 18) & 0x03fc0000)

Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_ARF_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_LSB   26

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET_MSK   0xfc000000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_CLR_MSK   0x03ffffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_GET (   value)    (((value) & 0xfc000000) >> 26)

Extracts the ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID_SET (   value)    (((value) << 26) & 0xfc000000)

Produces a ALT_IO48_HMC_MMR_CALTIMING4_CFG_T_PARAM_PDN_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING4_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CALTIMING4 register.

#define ALT_IO48_HMC_MMR_CALTIMING4_OFST   0x8c

The byte offset of the ALT_IO48_HMC_MMR_CALTIMING4 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING4.