Altera HWLIB  16.0
The Altera HW Manager API Reference Manual
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MMU Management API

Description

This module defines an API for configuring and managing the Cortex-A9 MMU.

The APIs in this module are divided into two categories:

The functions in the low-level MMU API provide capabilities to:

The low-level API does not directly support any particular virtual address implementation model. Many features of the MMU hardware are oriented toward efficient implementation of protected virtual addressing in a multi-tasking operating system environment.

While the functions in the low-level MMU API could be used to facilitate a port to an operating system exploiting these MMU features, the API itself does not directly implement any particular virtual address implementation model or policy.

The other API does directly support a simplified virtual address space implementation model. This API provides a client facility to programmatically define a simplified virtual address space from a set of high level memory region configurations. The API also provides a convenient method to enable the virtual address space once it is defined.

For a complete understanding of the possible configurations and operation of the MMU, consult the following references:

Members

 MMU Management
 
 MMU Virtual Address Space Creation
 
 MMU Virtual Address to Physical Address
 

Typedefs

typedef enum ALT_MMU_TTB_S_e ALT_MMU_TTB_S_t
 
typedef enum ALT_MMU_TTB_NS_e ALT_MMU_TTB_NS_t
 
typedef enum ALT_MMU_TTB_XN_e ALT_MMU_TTB_XN_t
 
typedef enum ALT_MMU_DAP_e ALT_MMU_DAP_t
 
typedef enum ALT_MMU_AP_e ALT_MMU_AP_t
 
typedef enum ALT_MMU_ATTR_e ALT_MMU_ATTR_t
 

ENUMS

enum  ALT_MMU_TTB_S_e { ALT_MMU_TTB_S_NON_SHAREABLE = 0, ALT_MMU_TTB_S_SHAREABLE = 1 }
 
enum  ALT_MMU_TTB_NS_e { ALT_MMU_TTB_NS_SECURE = 0, ALT_MMU_TTB_NS_NON_SECURE = 1 }
 
enum  ALT_MMU_TTB_XN_e { ALT_MMU_TTB_XN_DISABLE = 0, ALT_MMU_TTB_XN_ENABLE = 1 }
 
enum  ALT_MMU_DAP_e { ALT_MMU_DAP_NO_ACCESS = 0x0, ALT_MMU_DAP_CLIENT = 0x1, ALT_MMU_DAP_RESERVED = 0x2, ALT_MMU_DAP_MANAGER = 0x3 }
 
enum  ALT_MMU_AP_e {
  ALT_MMU_AP_NO_ACCESS = 0, ALT_MMU_AP_PRIV_ACCESS = 1, ALT_MMU_AP_USER_READ_ONLY = 2, ALT_MMU_AP_FULL_ACCESS = 3,
  ALT_MMU_AP_PRIV_READ_ONLY = 5, ALT_MMU_AP_READ_ONLY = 7
}
 
enum  ALT_MMU_ATTR_e {
  ALT_MMU_ATTR_FAULT = 0xff, ALT_MMU_ATTR_STRONG = 0x00, ALT_MMU_ATTR_DEVICE = 0x01, ALT_MMU_ATTR_WT = 0x02,
  ALT_MMU_ATTR_WB = 0x03, ALT_MMU_ATTR_NC = 0x10, ALT_MMU_ATTR_WBA = 0x13, ALT_MMU_ATTR_DEVICE_NS = 0x20,
  ALT_MMU_ATTR_NC_NC = 0x40, ALT_MMU_ATTR_NC_WBA = 0x50, ALT_MMU_ATTR_NC_WT = 0x60, ALT_MMU_ATTR_NC_WB = 0x70,
  ALT_MMU_ATTR_WBA_NC = 0x41, ALT_MMU_ATTR_WBA_WBA = 0x51, ALT_MMU_ATTR_WBA_WT = 0x61, ALT_MMU_ATTR_WBA_WB = 0x71,
  ALT_MMU_ATTR_WT_NC = 0x42, ALT_MMU_ATTR_WT_WBA = 0x52, ALT_MMU_ATTR_WT_WT = 0x62, ALT_MMU_ATTR_WT_WB = 0x72,
  ALT_MMU_ATTR_WB_NC = 0x43, ALT_MMU_ATTR_WB_WBA = 0x53, ALT_MMU_ATTR_WB_WT = 0x63, ALT_MMU_ATTR_WB_WB = 0x73
}
 

Typedef Documentation

This type enumerates the options for Shareability (S) properties in translation table descriptors. This control determines whether the addressed region is Shareable memory or not.

The Shareability property (S bit):

  • Is ignored if the entry refers to Device or Strongly-ordered memory.
  • For Normal memory, determines whether the memory region is Shareable or Non-shareable:
    • S == 0 Normal memory region is Non-shareable.
    • S == 1 Normal memory region is Shareable.

This type enumerates the options for Non-Secure (NS) controls in translation table descriptors. This control specifies whether memory accesses made from the secure state translate physical address in the secure or non-secure address map. The value of the NS bit in the first level page table descriptor applies to all entries in the corresponding second-level translation table.

This type enumerates the options for Execute Never (XN) controls in translation table descriptors that determine whether the processor can execute instructions from the addressed region.

This type enumerates the Domain Access Permission (DAP) options that can be set in the Domain Access Control Register (DACR).

typedef enum ALT_MMU_AP_e ALT_MMU_AP_t

Typedef name for enum ALT_MMU_AP_e

Typedef name for enum ALT_MMU_ATTR_e

Enumeration Type Documentation

This type enumerates the options for Shareability (S) properties in translation table descriptors. This control determines whether the addressed region is Shareable memory or not.

The Shareability property (S bit):

  • Is ignored if the entry refers to Device or Strongly-ordered memory.
  • For Normal memory, determines whether the memory region is Shareable or Non-shareable:
    • S == 0 Normal memory region is Non-shareable.
    • S == 1 Normal memory region is Shareable.
Enumerator:
ALT_MMU_TTB_S_NON_SHAREABLE 

Non-Shareable address map

ALT_MMU_TTB_S_SHAREABLE 

Shareable address map

This type enumerates the options for Non-Secure (NS) controls in translation table descriptors. This control specifies whether memory accesses made from the secure state translate physical address in the secure or non-secure address map. The value of the NS bit in the first level page table descriptor applies to all entries in the corresponding second-level translation table.

Enumerator:
ALT_MMU_TTB_NS_SECURE 

Secure address map

ALT_MMU_TTB_NS_NON_SECURE 

Non-Secure address map

This type enumerates the options for Execute Never (XN) controls in translation table descriptors that determine whether the processor can execute instructions from the addressed region.

Enumerator:
ALT_MMU_TTB_XN_DISABLE 

Instructions can be executed from this memory region.

ALT_MMU_TTB_XN_ENABLE 

Instructions cannot be executed from this memory region. A permission fault is generated if an attempt to execute an instruction from this memory region. However, if using the short-descriptor translation table format, the fault is generated only if the access is to memory in the client domain.

This type enumerates the Domain Access Permission (DAP) options that can be set in the Domain Access Control Register (DACR).

Enumerator:
ALT_MMU_DAP_NO_ACCESS 

No access. Any access to the domain generates a Domain fault.

ALT_MMU_DAP_CLIENT 

Client. Accesses are checked against the permission bits in the translation tables.

ALT_MMU_DAP_RESERVED 

Reserved, effect is UNPREDICTABLE.

ALT_MMU_DAP_MANAGER 

Manager. Accesses are not checked against the permission bits in the translation tables.

This type enumerates the Access Permissions that can be specified for a memory region.

Memory access control is defined using access permission bits in translation table descriptors that control access to the corresponding memory region.

The HWLIB uses the short-descriptor translation table format for defining the access permissions where three bits, AP[2:0], define the access permissions. The SCTLR.AFE must be set to 0.

The following table provides a summary of the enumerations, AP bit encodings, and access permission descriptions for this type.

Enumeration AP Value Privileged (PL1) Access User (PL0) Access Description
ALT_MMU_AP_NO_ACCESS 000 No Access No Access No Access
ALT_MMU_AP_PRIV_ACCESS 001 Read/Write No Access Privileged access only
ALT_MMU_AP_USER_READ_ONLY 010 Read/Write Read Only Write in user mode generates a fault
ALT_MMU_AP_FULL_ACCESS 011 Read/Write Read/Write Full Access
N/A 100 Unknown Unknown Reserved
ALT_MMU_AP_PRIV_READ_ONLY 101 Read Only No Access Privileged read only
N/A 110 Read Only Read Only Read Only - deprecated
ALT_MMU_AP_READ_ONLY 111 Read Only Read Only Read Only
Enumerator:
ALT_MMU_AP_NO_ACCESS 

No Access

ALT_MMU_AP_PRIV_ACCESS 

Privileged access only

ALT_MMU_AP_USER_READ_ONLY 

Write in user mode generates a fault

ALT_MMU_AP_FULL_ACCESS 

Full Access

ALT_MMU_AP_PRIV_READ_ONLY 

Privileged read only

ALT_MMU_AP_READ_ONLY 

Read Only

This type enumerates the Memory Region attributes that can be specifed in MMU translation table entries. Memory attributes determine the memory ordering and cache policies for inner/outer domains used for a particular range of memory.

Within the translation table entries, the memory region attributes are encoded using a combination of the descriptor entry data fields (TEX, C, B). Memory attribute settings also affect the meaning of other memory region properties such as shareability (S).

The tables below describe the available enumerations for specifying different memory region attributes and their affect on shareability.

The memory attributes enumerated here are meant to be used is a system where TEX remap is disabled (i.e. SCTLR.TRE is set to 0).

Enumeration TEX C B Description Shareability
ALT_MMU_ATTR_STRONG 000 0 0 Strongly Ordered Shareable
ALT_MMU_ATTR_DEVICE 000 0 1 Device Shareable
ALT_MMU_ATTR_WT 000 1 0 Inner/Outer Write-Through, No Write Allocate Determined by descriptor [S] bit
ALT_MMU_ATTR_WB 000 1 1 Inner/Outer Write-Back, No Write Allocate Determined by descriptor [S] bit
ALT_MMU_ATTR_NC 001 0 0 Inner/Outer Non-Cacheable Determined by descriptor [S] bit
N/A 001 0 1 Reserved Reserved
N/A 001 1 0 Implementation Defined -
ALT_MMU_ATTR_WBA 001 1 1 Inner/Outer Write-Back, Write Allocate Determined by descriptor [S] bit
ALT_MMU_ATTR_DEVICE_NS 010 0 0 Device Non-Shareable
N/A 010 0 1 Reserved Reserved
N/A 010 1 0 Reserved Reserved
N/A 010 1 1 Reserved Reserved
ALT_MMU_ATTR_AA_BB 1BB A A Cached where AA = Inner Policy, BB = Outer Policy Determined by descriptor [S] bit

Cache Policy Encoding for AA, BB

Mnemonic Encoding Bit Encoding Cache Policy
NC 00 Non-Cacheable
WBA 01 Write-Back, Write Allocate
WT 10 Write-Through, No Write Allocate
WB 11 Write-Back, No Write Allocate
Enumerator:
ALT_MMU_ATTR_FAULT 

Generates fault descriptor entries for memory region

ALT_MMU_ATTR_STRONG 

Strongly Ordered Shareable

ALT_MMU_ATTR_DEVICE 

Device Shareable

ALT_MMU_ATTR_WT 

Inner/Outer Write-Through, No Write Allocate, Shareability determined by [S]

ALT_MMU_ATTR_WB 

Inner/Outer Write-Back, No Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_NC 

Inner/Outer Non-Cacheable, Shareability determined by [S] bit

ALT_MMU_ATTR_WBA 

Inner/Outer Write-Back, Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_DEVICE_NS 

Device Non-Shareable

ALT_MMU_ATTR_NC_NC 

Inner Non-Cacheable, Outer Non-Cacheable, Shareability determined by [S] bit

ALT_MMU_ATTR_NC_WBA 

Inner Non-Cacheable, Outer Write-Back Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_NC_WT 

Inner Non-Cacheable, Outer Write-Through, Shareability determined by [S] bit

ALT_MMU_ATTR_NC_WB 

Inner Non-Cacheable, Outer Write-Back, Shareability determined by [S] bit

ALT_MMU_ATTR_WBA_NC 

Inner Write-Back Write Allocate, Outer Non-Cacheable, Shareability determined by [S] bit

ALT_MMU_ATTR_WBA_WBA 

Inner Write-Back Write Allocate, Outer Write-Back Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_WBA_WT 

Inner Write-Back Write Allocate, Outer Write-Through, Shareability determined by [S] bit

ALT_MMU_ATTR_WBA_WB 

Inner Write-Back Write Allocate, Outer Write-Back, Shareability determined by [S] bit

ALT_MMU_ATTR_WT_NC 

Inner Write-Through, Outer Non-Cacheable, Shareability determined by [S] bit

ALT_MMU_ATTR_WT_WBA 

Inner Write-Through, Outer Write-Back Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_WT_WT 

Inner Write-Through, Outer Write-Through, Shareability determined by [S] bit

ALT_MMU_ATTR_WT_WB 

Inner Write-Through, Outer Write-Back, Shareability determined by [S] bit

ALT_MMU_ATTR_WB_NC 

Inner Write-Back, Outer Non-Cacheable, Shareability determined by [S] bit

ALT_MMU_ATTR_WB_WBA 

Inner Write-Back, Outer Write-Back Write Allocate, Shareability determined by [S] bit

ALT_MMU_ATTR_WB_WT 

Inner Write-Back, Outer Write-Through, Shareability determined by [S] bit

ALT_MMU_ATTR_WB_WB 

Inner Write-Back, Outer Write-Back, Shareability determined by [S] bit