Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : NAND RAM ECC Enable Register - nand

Description

This register is used to enable ECC on the NAND RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error.

Only reset by a cold reset (ignores warm reset).

Register Layout

Bits Access Reset Description
[0] RW 0x0 NAND RAM ECC Enable
[1] RW 0x0 NAND ECCBUFFER RAM ECC inject single, correctable Error
[2] RW 0x0 NAND ECCBUFFER RAM ECC inject double bit, non-correctable error
[3] RW 0x0 NAND WRFIFO RAM ECC inject single, correctable Error
[4] RW 0x0 NAND WRFIFO RAM ECC inject double bit, non-correctable error
[5] RW 0x0 NAND RDFIFO RAM ECC inject single, correctable Error
[6] RW 0x0 NAND RDFIFO RAM ECC inject double bit, non-correctable error
[7] RW 0x0 NAND ECCBUFFER RAM ECC single, correctable error interrupt status
[8] RW 0x0 NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status
[9] RW 0x0 NAND WRFIFO RAM ECC single, correctable error interrupt status
[10] RW 0x0 NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status
[11] RW 0x0 NAND RDFIFO RAM ECC single, correctable error interrupt status
[12] RW 0x0 NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status
[31:13] ??? 0x0 UNDEFINED

Field : NAND RAM ECC Enable - en

Enable ECC for NAND RAM

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_EN_LSB   0
 
#define ALT_SYSMGR_ECC_NAND_EN_MSB   0
 
#define ALT_SYSMGR_ECC_NAND_EN_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK   0x00000001
 
#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_ECC_NAND_EN_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_ECC_NAND_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : NAND ECCBUFFER RAM ECC inject single, correctable Error - eccbufinjs

Changing this bit from zero to one injects a single, correctable error into the NAND ECCBUFFER RAM. This only injects one error into the NAND ECCBUFFER RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK   0x00000002
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK   0xfffffffd
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET(value)   (((value) << 1) & 0x00000002)
 

Field : NAND ECCBUFFER RAM ECC inject double bit, non-correctable error - eccbufinjd

Changing this bit from zero to one injects a double, non-correctable error into the NAND ECCBUFFER RAM. This only injects one double bit error into the NAND ECCBUFFER RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB   2
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB   2
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK   0x00000004
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK   0xfffffffb
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET(value)   (((value) << 2) & 0x00000004)
 

Field : NAND WRFIFO RAM ECC inject single, correctable Error - wrfifoinjs

Changing this bit from zero to one injects a single, correctable error into the NAND WRFIFO RAM. This only injects one error into the NAND WRFIFO RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB   3
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB   3
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK   0x00000008
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK   0xfffffff7
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET(value)   (((value) << 3) & 0x00000008)
 

Field : NAND WRFIFO RAM ECC inject double bit, non-correctable error - wrfifoinjd

Changing this bit from zero to one injects a double, non-correctable error into the NAND WRFIFO RAM. This only injects one double bit error into the NAND WRFIFO RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB   4
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB   4
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK   0x00000010
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK   0xffffffef
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET(value)   (((value) << 4) & 0x00000010)
 

Field : NAND RDFIFO RAM ECC inject single, correctable Error - rdfifoinjs

Changing this bit from zero to one injects a single, correctable error into the NAND RDFIFO RAM. This only injects one error into the NAND RDFIFO RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB   5
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB   5
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK   0x00000020
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK   0xffffffdf
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET(value)   (((value) << 5) & 0x00000020)
 

Field : NAND RDFIFO RAM ECC inject double bit, non-correctable error - rdfifoinjd

Changing this bit from zero to one injects a double, non-correctable error into the NAND RDFIFO RAM. This only injects one double bit error into the NAND RDFIFO RAM.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB   6
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB   6
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK   0x00000040
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK   0xffffffbf
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET(value)   (((value) << 6) & 0x00000040)
 

Field : NAND ECCBUFFER RAM ECC single, correctable error interrupt status - eccbufserr

This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB   7
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB   7
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK   0x00000080
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK   0xffffff7f
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET(value)   (((value) << 7) & 0x00000080)
 

Field : NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status - eccbufderr

This bit is an interrupt status bit for NAND ECCBUFFER RAM ECC double bit, non- correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND ECCBUFFER RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB   8
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB   8
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK   0x00000100
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK   0xfffffeff
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET(value)   (((value) << 8) & 0x00000100)
 

Field : NAND WRFIFO RAM ECC single, correctable error interrupt status - wrfifoserr

This bit is an interrupt status bit for NAND WRFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB   9
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB   9
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK   0x00000200
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK   0xfffffdff
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET(value)   (((value) << 9) & 0x00000200)
 

Field : NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status - wrfifoderr

This bit is an interrupt status bit for NAND WRFIFO RAM ECC double bit, non- correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND WRFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB   10
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB   10
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK   0x00000400
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK   0xfffffbff
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET(value)   (((value) << 10) & 0x00000400)
 

Field : NAND RDFIFO RAM ECC single, correctable error interrupt status - rdfifoserr

This bit is an interrupt status bit for NAND RDFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB   11
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB   11
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK   0x00000800
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK   0xfffff7ff
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET(value)   (((value) << 11) & 0x00000800)
 

Field : NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status - rdfifoderr

This bit is an interrupt status bit for NAND RDFIFO RAM ECC double bit, non- correctable error. It is set by hardware when double bit, non-correctable error occurs in NAND RDFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status.

Field Access Macros:

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB   12
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB   12
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH   1
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK   0x00001000
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK   0xffffefff
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET   0x0
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET(value)   (((value) << 12) & 0x00001000)
 

Data Structures

struct  ALT_SYSMGR_ECC_NAND_s
 

Macros

#define ALT_SYSMGR_ECC_NAND_OFST   0x24
 

Typedefs

typedef struct
ALT_SYSMGR_ECC_NAND_s 
ALT_SYSMGR_ECC_NAND_t
 

Data Structure Documentation

struct ALT_SYSMGR_ECC_NAND_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_ECC_NAND.

Data Fields
uint32_t en: 1 NAND RAM ECC Enable
uint32_t eccbufinjs: 1 NAND ECCBUFFER RAM ECC inject single, correctable Error
uint32_t eccbufinjd: 1 NAND ECCBUFFER RAM ECC inject double bit, non-correctable error
uint32_t wrfifoinjs: 1 NAND WRFIFO RAM ECC inject single, correctable Error
uint32_t wrfifoinjd: 1 NAND WRFIFO RAM ECC inject double bit, non-correctable error
uint32_t rdfifoinjs: 1 NAND RDFIFO RAM ECC inject single, correctable Error
uint32_t rdfifoinjd: 1 NAND RDFIFO RAM ECC inject double bit, non-correctable error
uint32_t eccbufserr: 1 NAND ECCBUFFER RAM ECC single, correctable error interrupt status
uint32_t eccbufderr: 1 NAND ECCBUFFER RAM ECC double bit, non-correctable error interrupt status
uint32_t wrfifoserr: 1 NAND WRFIFO RAM ECC single, correctable error interrupt status
uint32_t wrfifoderr: 1 NAND WRFIFO RAM ECC double bit, non-correctable error interrupt status
uint32_t rdfifoserr: 1 NAND RDFIFO RAM ECC single, correctable error interrupt status
uint32_t rdfifoderr: 1 NAND RDFIFO RAM ECC double bit, non-correctable error interrupt status
uint32_t __pad0__: 19 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_ECC_NAND_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_EN register field.

#define ALT_SYSMGR_ECC_NAND_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_EN register field.

#define ALT_SYSMGR_ECC_NAND_EN_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_EN register field.

#define ALT_SYSMGR_ECC_NAND_EN_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_ECC_NAND_EN register field value.

#define ALT_SYSMGR_ECC_NAND_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_ECC_NAND_EN register field value.

#define ALT_SYSMGR_ECC_NAND_EN_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_EN register field.

#define ALT_SYSMGR_ECC_NAND_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_ECC_NAND_EN field value from a register.

#define ALT_SYSMGR_ECC_NAND_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_ECC_NAND_EN register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_LSB   1

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET_MSK   0x00000002

The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJS field value from a register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJS_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJS register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_LSB   2

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_MSB   2

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET_MSK   0x00000004

The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFINJD field value from a register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFINJD_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SYSMGR_ECC_NAND_ECCBUFINJD register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_LSB   3

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_MSB   3

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET_MSK   0x00000008

The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJS field value from a register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJS_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJS register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_LSB   4

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_MSB   4

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET_MSK   0x00000010

The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_CLR_MSK   0xffffffef

The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOINJD field value from a register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOINJD_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SYSMGR_ECC_NAND_WRFIFOINJD register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_LSB   5

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_MSB   5

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET_MSK   0x00000020

The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJS field value from a register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJS_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJS register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_LSB   6

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_MSB   6

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET_MSK   0x00000040

The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOINJD field value from a register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOINJD_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SYSMGR_ECC_NAND_RDFIFOINJD register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_LSB   7

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET_MSK   0x00000080

The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFSERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFSERR_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SYSMGR_ECC_NAND_ECCBUFSERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_MSB   8

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET_MSK   0x00000100

The mask used to set the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SYSMGR_ECC_NAND_ECCBUFDERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_ECCBUFDERR_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SYSMGR_ECC_NAND_ECCBUFDERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_LSB   9

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_MSB   9

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET_MSK   0x00000200

The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SYSMGR_ECC_NAND_WRFIFOSERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_WRFIFOSERR_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SYSMGR_ECC_NAND_WRFIFOSERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_LSB   10

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_MSB   10

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET_MSK   0x00000400

The mask used to set the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_WRFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SYSMGR_ECC_NAND_WRFIFODERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_WRFIFODERR_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SYSMGR_ECC_NAND_WRFIFODERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_LSB   11

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_MSB   11

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET_MSK   0x00000800

The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SYSMGR_ECC_NAND_RDFIFOSERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_RDFIFOSERR_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SYSMGR_ECC_NAND_RDFIFOSERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_LSB   12

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_MSB   12

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET_MSK   0x00001000

The mask used to set the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_CLR_MSK   0xffffefff

The mask used to clear the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_NAND_RDFIFODERR register field.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_SYSMGR_ECC_NAND_RDFIFODERR field value from a register.

#define ALT_SYSMGR_ECC_NAND_RDFIFODERR_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_SYSMGR_ECC_NAND_RDFIFODERR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_NAND_OFST   0x24

The byte offset of the ALT_SYSMGR_ECC_NAND register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_ECC_NAND.