Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : caltiming7

Description

Register Layout

Bits Access Reset Description
[8:0] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID
[15:9] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID
[19:16] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID
[29:20] RW 0x0 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID
[31:30] ??? 0x0 UNDEFINED

Field : cfg_t_param_zqcl_to_valid

Long ZQ calibration to valid

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB   0
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB   8
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH   9
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK   0x000001ff
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK   0xfffffe00
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET(value)   (((value) & 0x000001ff) >> 0)
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET(value)   (((value) << 0) & 0x000001ff)
 

Field : cfg_t_param_zqcs_to_valid

Short ZQ calibration to valid

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB   9
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB   15
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH   7
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK   0x0000fe00
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK   0xffff01ff
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET(value)   (((value) & 0x0000fe00) >> 9)
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET(value)   (((value) << 9) & 0x0000fe00)
 

Field : cfg_t_param_mrs_to_valid

Mode Register Setting to valid

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB   16
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB   19
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK   0x000f0000
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK   0xfff0ffff
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET(value)   (((value) & 0x000f0000) >> 16)
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET(value)   (((value) << 16) & 0x000f0000)
 

Field : cfg_t_param_mps_to_valid

Timing parameter for Maximum Power Saving to any valid command. tXMP

Field Access Macros:

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB   20
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB   29
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH   10
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK   0x3ff00000
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK   0xc00fffff
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET(value)   (((value) & 0x3ff00000) >> 20)
 
#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET(value)   (((value) << 20) & 0x3ff00000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CALTIMING7_s
 

Macros

#define ALT_IO48_HMC_MMR_CALTIMING7_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CALTIMING7_OFST   0x98
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CALTIMING7_s 
ALT_IO48_HMC_MMR_CALTIMING7_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CALTIMING7_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING7.

Data Fields
uint32_t cfg_t_param_zqcl_to_valid: 9 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID
uint32_t cfg_t_param_zqcs_to_valid: 7 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID
uint32_t cfg_t_param_mrs_to_valid: 4 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID
uint32_t cfg_t_param_mps_to_valid: 10 ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID
uint32_t __pad0__: 2 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_WIDTH   9

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET_MSK   0x000001ff

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_CLR_MSK   0xfffffe00

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_GET (   value)    (((value) & 0x000001ff) >> 0)

Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID_SET (   value)    (((value) << 0) & 0x000001ff)

Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCL_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_WIDTH   7

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET_MSK   0x0000fe00

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_CLR_MSK   0xffff01ff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_GET (   value)    (((value) & 0x0000fe00) >> 9)

Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID_SET (   value)    (((value) << 9) & 0x0000fe00)

Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_ZQCS_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_MSB   19

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET_MSK   0x000f0000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_CLR_MSK   0xfff0ffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_GET (   value)    (((value) & 0x000f0000) >> 16)

Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID_SET (   value)    (((value) << 16) & 0x000f0000)

Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MRS_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_LSB   20

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_MSB   29

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_WIDTH   10

The width in bits of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET_MSK   0x3ff00000

The mask used to set the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_CLR_MSK   0xc00fffff

The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_GET (   value)    (((value) & 0x3ff00000) >> 20)

Extracts the ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID field value from a register.

#define ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID_SET (   value)    (((value) << 20) & 0x3ff00000)

Produces a ALT_IO48_HMC_MMR_CALTIMING7_CFG_T_PARAM_MPS_TO_VALID register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CALTIMING7_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CALTIMING7 register.

#define ALT_IO48_HMC_MMR_CALTIMING7_OFST   0x98

The byte offset of the ALT_IO48_HMC_MMR_CALTIMING7 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING7.