Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Device Configuration Register - dcfg

Description

This register configures the core in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming.

Register Layout

Bits Access Reset Description
[1:0] RW 0x0 Device Speed
[2] RW 0x0 Non-Zero-Length Status OUT Handshak
[3] RW 0x0 Enable 32 KHz Suspend mode
[10:4] RW 0x0 Device Address
[12:11] RW 0x0 Periodic Frame Interval
[13] RW 0x0 Enable Device OUT NA
[22:14] ??? 0x0 UNDEFINED
[23] RW 0x0 Enable Scatter gather DMA in device mode
[25:24] RW 0x0 Periodic Scheduling Interva
[31:26] RW 0x2 Resume Validation Period

Field : Device Speed - devspd

Indicates the speed at which the application requires the core to enumerate, or the maximum speed the application can support. However, the actual bus speed is determined only after the chirp sequence is completed, and is based on the speed of the USB host to which the core is connected.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20 0x0 High speed USB 2.0 PHY clock is 30 MHz or 60 MHz
ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20 0x1 Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz
ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116 0x2 Low speed USB 1.1 transceiver clock is 6 MHz
ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148 0x3 Full speed USB 1.1 transceiver clock is 48 MHz

Field Access Macros:

#define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20   0x0
 
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20   0x1
 
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116   0x2
 
#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148   0x3
 
#define ALT_USB_DEV_DCFG_DEVSPD_LSB   0
 
#define ALT_USB_DEV_DCFG_DEVSPD_MSB   1
 
#define ALT_USB_DEV_DCFG_DEVSPD_WIDTH   2
 
#define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK   0x00000003
 
#define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK   0xfffffffc
 
#define ALT_USB_DEV_DCFG_DEVSPD_RESET   0x0
 
#define ALT_USB_DEV_DCFG_DEVSPD_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_USB_DEV_DCFG_DEVSPD_SET(value)   (((value) << 0) & 0x00000003)
 

Field : Non-Zero-Length Status OUT Handshak - nzstsouthshk

The application can use this field to select the handshake the core sends on receiving a nonzero-length data packet during the OUT transaction of a control transfer's Status stage. 1: Send a STALL handshake on a nonzero-length statusOUT transaction and do not send the received OUT packet tothe application. 0: Send the received OUT packet to the application (zerolengthor nonzero-length) and send a handshake based onthe NAK and STALL bits for the endpoint in the DeviceEndpoint Control register.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT 0x0 Send the received OUT packet to the application
: zerolength
ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL 0x1 Send a STALL handshake on a nonzero-length
: status OUT transaction and do not send the
: received OUT packet to the application

Field Access Macros:

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT   0x0
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL   0x1
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB   2
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB   2
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH   1
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK   0x00000004
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK   0xfffffffb
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET   0x0
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Enable 32 KHz Suspend mode - ena32khzsusp

When the USB 1.1 Full-Speed Serial Transceiver Interface is chosen and this bit is set, the core expects the 48-MHz PHY clock to be switched to 32 KHz during a suspend. This bit can only be set if USB 1.1 Full-Speed Serial Transceiver Interface has been selected. If USB 1.1 Full-Speed Serial Transceiver Interface has not been selected, this bit must be zero.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD 0x0 USB 1.1 Full-Speed Serial Transceiver not
: selected
ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END 0x1 USB 1.1 Full-Speed Serial Transceiver Interface
: selected

Field Access Macros:

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD   0x0
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END   0x1
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB   3
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB   3
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH   1
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK   0x00000008
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK   0xfffffff7
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET   0x0
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Device Address - devaddr

The application must program this field after every SetAddress control command.

Field Access Macros:

#define ALT_USB_DEV_DCFG_DEVADDR_LSB   4
 
#define ALT_USB_DEV_DCFG_DEVADDR_MSB   10
 
#define ALT_USB_DEV_DCFG_DEVADDR_WIDTH   7
 
#define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK   0x000007f0
 
#define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK   0xfffff80f
 
#define ALT_USB_DEV_DCFG_DEVADDR_RESET   0x0
 
#define ALT_USB_DEV_DCFG_DEVADDR_GET(value)   (((value) & 0x000007f0) >> 4)
 
#define ALT_USB_DEV_DCFG_DEVADDR_SET(value)   (((value) << 4) & 0x000007f0)
 

Field : Periodic Frame Interval - perfrint

Indicates the time within a (micro)frame at which the application must be notified using the End Of Periodic Frame Interrupt. This can be used to determine If all the isochronous traffic for that (micro)frame is complete. 0x0: 80% of the (micro)frame interval 0x1: 85% 0x2: 90% 0x3: 95%

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80 0x0 80% of the (micro)frame interval
ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85 0x1 85% of the (micro)frame interval
ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90 0x2 90% of the (micro)frame interval
ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95 0x3 95% of the (micro)frame interval

Field Access Macros:

#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80   0x0
 
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85   0x1
 
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90   0x2
 
#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95   0x3
 
#define ALT_USB_DEV_DCFG_PERFRINT_LSB   11
 
#define ALT_USB_DEV_DCFG_PERFRINT_MSB   12
 
#define ALT_USB_DEV_DCFG_PERFRINT_WIDTH   2
 
#define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK   0x00001800
 
#define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK   0xffffe7ff
 
#define ALT_USB_DEV_DCFG_PERFRINT_RESET   0x0
 
#define ALT_USB_DEV_DCFG_PERFRINT_GET(value)   (((value) & 0x00001800) >> 11)
 
#define ALT_USB_DEV_DCFG_PERFRINT_SET(value)   (((value) << 11) & 0x00001800)
 

Field : Enable Device OUT NA - endevoutnak

This bit enables setting NAK for Bulk OUT endpoints after the transfer is completed for Device mode Descriptor DMA It is one time programmable after reset like any other DCFG register bits.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD 0x0 The core does not set NAK after Bulk OUT
: transfer complete
ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END 0x1 The core sets NAK after Bulk OUT transfer
: complete

Field Access Macros:

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD   0x0
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END   0x1
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB   13
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB   13
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH   1
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK   0x00002000
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK   0xffffdfff
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET   0x0
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Enable Scatter gather DMA in device mode - descdma

When the Scatter/Gather DMA option selected during configuration of the RTL, the application can Set this bit during initialization to enable the Scatter/Gather DMA operation. This bit must be modified only once after a reset.The following combinations are available for programming:

GAHBCFG.DMAEn=0,DCFG.DescDMA=0 => Slave mode

GAHBCFG.DMAEn=0,DCFG.DescDMA=1 => Invalid

GAHBCFG.DMAEn=1,DCFG.DescDMA=0 => Buffered DMA

mode GAHBCFG.DMAEn=1,DCFG.DescDMA=1 => Scatter/Gather DMA mode

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_DESCDMA_E_DISD 0x0 Disable Scatter gather DMA
ALT_USB_DEV_DCFG_DESCDMA_E_END 0x1 Enable Scatter gather DMA

Field Access Macros:

#define ALT_USB_DEV_DCFG_DESCDMA_E_DISD   0x0
 
#define ALT_USB_DEV_DCFG_DESCDMA_E_END   0x1
 
#define ALT_USB_DEV_DCFG_DESCDMA_LSB   23
 
#define ALT_USB_DEV_DCFG_DESCDMA_MSB   23
 
#define ALT_USB_DEV_DCFG_DESCDMA_WIDTH   1
 
#define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK   0x00800000
 
#define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK   0xff7fffff
 
#define ALT_USB_DEV_DCFG_DESCDMA_RESET   0x0
 
#define ALT_USB_DEV_DCFG_DESCDMA_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_USB_DEV_DCFG_DESCDMA_SET(value)   (((value) << 23) & 0x00800000)
 

Field : Periodic Scheduling Interva - perschintvl

PerSchIntvl must be programmed only for Scatter/Gather DMAmode. Description: This field specifies the amount of time the Internal DMA engine must allocate for fetching periodic IN endpoint data. Based on the number of periodic endpoints, this value must be specified as 25,50 or 75% of (micro)frame. When any periodic endpoints are active, the internal DMA engine allocates the specified amount of time in fetching periodic IN endpoint data . When no periodic endpoints are active, Then the internal DMA engine services non- periodic endpoints, ignoring this field. After the specified time within a (micro)frame, the DMA switches to fetching for non-periodic endpoints. 2'b00: 25% of (micro)frame. 2'b01: 50% of (micro)frame. 2'b10: 75% of (micro)frame. 2'b11: Reserved.Reset: 2'b00Access: read-write

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25 0x0 25% of (micro)frame
ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50 0x1 50% of (micro)frame
ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75 0x2 75% of (micro)frame
ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD 0x3 Reserved

Field Access Macros:

#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25   0x0
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50   0x1
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75   0x2
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD   0x3
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB   24
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB   25
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH   2
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK   0x03000000
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK   0xfcffffff
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET   0x0
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_GET(value)   (((value) & 0x03000000) >> 24)
 
#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET(value)   (((value) << 24) & 0x03000000)
 

Field : Resume Validation Period - resvalid

This field is effective only when DCFG.Ena32KHzSusp is set. It will control the resume period when the core resumes from suspend. The core counts for ResValid number of clock cycles to detect a valid resume when this is set

Field Access Macros:

#define ALT_USB_DEV_DCFG_RESVALID_LSB   26
 
#define ALT_USB_DEV_DCFG_RESVALID_MSB   31
 
#define ALT_USB_DEV_DCFG_RESVALID_WIDTH   6
 
#define ALT_USB_DEV_DCFG_RESVALID_SET_MSK   0xfc000000
 
#define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK   0x03ffffff
 
#define ALT_USB_DEV_DCFG_RESVALID_RESET   0x2
 
#define ALT_USB_DEV_DCFG_RESVALID_GET(value)   (((value) & 0xfc000000) >> 26)
 
#define ALT_USB_DEV_DCFG_RESVALID_SET(value)   (((value) << 26) & 0xfc000000)
 

Data Structures

struct  ALT_USB_DEV_DCFG_s
 

Macros

#define ALT_USB_DEV_DCFG_OFST   0x0
 
#define ALT_USB_DEV_DCFG_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST))
 

Typedefs

typedef struct ALT_USB_DEV_DCFG_s ALT_USB_DEV_DCFG_t
 

Data Structure Documentation

struct ALT_USB_DEV_DCFG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_USB_DEV_DCFG.

Data Fields
uint32_t devspd: 2 Device Speed
uint32_t nzstsouthshk: 1 Non-Zero-Length Status OUT Handshak
uint32_t ena32khzsusp: 1 Enable 32 KHz Suspend mode
uint32_t devaddr: 7 Device Address
uint32_t perfrint: 2 Periodic Frame Interval
uint32_t endevoutnak: 1 Enable Device OUT NA
uint32_t __pad0__: 9 UNDEFINED
uint32_t descdma: 1 Enable Scatter gather DMA in device mode
uint32_t perschintvl: 2 Periodic Scheduling Interva
uint32_t resvalid: 6 Resume Validation Period

Macro Definitions

#define ALT_USB_DEV_DCFG_DEVSPD_E_USBHS20   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD

High speed USB 2.0 PHY clock is 30 MHz or 60 MHz

#define ALT_USB_DEV_DCFG_DEVSPD_E_USBFS20   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD

Full speed USB 2.0 PHY clock is 30 MHz or 60 MHz

#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS116   0x2

Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD

Low speed USB 1.1 transceiver clock is 6 MHz

#define ALT_USB_DEV_DCFG_DEVSPD_E_USBLS1148   0x3

Enumerated value for register field ALT_USB_DEV_DCFG_DEVSPD

Full speed USB 1.1 transceiver clock is 48 MHz

#define ALT_USB_DEV_DCFG_DEVSPD_LSB   0

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field.

#define ALT_USB_DEV_DCFG_DEVSPD_MSB   1

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVSPD register field.

#define ALT_USB_DEV_DCFG_DEVSPD_WIDTH   2

The width in bits of the ALT_USB_DEV_DCFG_DEVSPD register field.

#define ALT_USB_DEV_DCFG_DEVSPD_SET_MSK   0x00000003

The mask used to set the ALT_USB_DEV_DCFG_DEVSPD register field value.

#define ALT_USB_DEV_DCFG_DEVSPD_CLR_MSK   0xfffffffc

The mask used to clear the ALT_USB_DEV_DCFG_DEVSPD register field value.

#define ALT_USB_DEV_DCFG_DEVSPD_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_DEVSPD register field.

#define ALT_USB_DEV_DCFG_DEVSPD_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_USB_DEV_DCFG_DEVSPD field value from a register.

#define ALT_USB_DEV_DCFG_DEVSPD_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_USB_DEV_DCFG_DEVSPD register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDOUT   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK

Send the received OUT packet to the application zerolength

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_E_SENDSTALL   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_NZSTSOUTHSHK

Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_LSB   2

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_MSB   2

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_WIDTH   1

The width in bits of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET_MSK   0x00000004

The mask used to set the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_CLR_MSK   0xfffffffb

The mask used to clear the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_USB_DEV_DCFG_NZSTSOUTHSHK field value from a register.

#define ALT_USB_DEV_DCFG_NZSTSOUTHSHK_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_USB_DEV_DCFG_NZSTSOUTHSHK register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP

USB 1.1 Full-Speed Serial Transceiver not selected

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_ENA32KHZSUSP

USB 1.1 Full-Speed Serial Transceiver Interface selected

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_LSB   3

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_MSB   3

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_WIDTH   1

The width in bits of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET_MSK   0x00000008

The mask used to set the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_CLR_MSK   0xfffffff7

The mask used to clear the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_ENA32KHZSUSP register field.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_USB_DEV_DCFG_ENA32KHZSUSP field value from a register.

#define ALT_USB_DEV_DCFG_ENA32KHZSUSP_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_USB_DEV_DCFG_ENA32KHZSUSP register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_DEVADDR_LSB   4

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field.

#define ALT_USB_DEV_DCFG_DEVADDR_MSB   10

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DEVADDR register field.

#define ALT_USB_DEV_DCFG_DEVADDR_WIDTH   7

The width in bits of the ALT_USB_DEV_DCFG_DEVADDR register field.

#define ALT_USB_DEV_DCFG_DEVADDR_SET_MSK   0x000007f0

The mask used to set the ALT_USB_DEV_DCFG_DEVADDR register field value.

#define ALT_USB_DEV_DCFG_DEVADDR_CLR_MSK   0xfffff80f

The mask used to clear the ALT_USB_DEV_DCFG_DEVADDR register field value.

#define ALT_USB_DEV_DCFG_DEVADDR_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_DEVADDR register field.

#define ALT_USB_DEV_DCFG_DEVADDR_GET (   value)    (((value) & 0x000007f0) >> 4)

Extracts the ALT_USB_DEV_DCFG_DEVADDR field value from a register.

#define ALT_USB_DEV_DCFG_DEVADDR_SET (   value)    (((value) << 4) & 0x000007f0)

Produces a ALT_USB_DEV_DCFG_DEVADDR register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF80   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT

80% of the (micro)frame interval

#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF85   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT

85% of the (micro)frame interval

#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF90   0x2

Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT

90% of the (micro)frame interval

#define ALT_USB_DEV_DCFG_PERFRINT_E_EOPF95   0x3

Enumerated value for register field ALT_USB_DEV_DCFG_PERFRINT

95% of the (micro)frame interval

#define ALT_USB_DEV_DCFG_PERFRINT_LSB   11

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field.

#define ALT_USB_DEV_DCFG_PERFRINT_MSB   12

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERFRINT register field.

#define ALT_USB_DEV_DCFG_PERFRINT_WIDTH   2

The width in bits of the ALT_USB_DEV_DCFG_PERFRINT register field.

#define ALT_USB_DEV_DCFG_PERFRINT_SET_MSK   0x00001800

The mask used to set the ALT_USB_DEV_DCFG_PERFRINT register field value.

#define ALT_USB_DEV_DCFG_PERFRINT_CLR_MSK   0xffffe7ff

The mask used to clear the ALT_USB_DEV_DCFG_PERFRINT register field value.

#define ALT_USB_DEV_DCFG_PERFRINT_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_PERFRINT register field.

#define ALT_USB_DEV_DCFG_PERFRINT_GET (   value)    (((value) & 0x00001800) >> 11)

Extracts the ALT_USB_DEV_DCFG_PERFRINT field value from a register.

#define ALT_USB_DEV_DCFG_PERFRINT_SET (   value)    (((value) << 11) & 0x00001800)

Produces a ALT_USB_DEV_DCFG_PERFRINT register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK

The core does not set NAK after Bulk OUT transfer complete

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_ENDEVOUTNAK

The core sets NAK after Bulk OUT transfer complete

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_LSB   13

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_MSB   13

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_WIDTH   1

The width in bits of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET_MSK   0x00002000

The mask used to set the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_CLR_MSK   0xffffdfff

The mask used to clear the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_ENDEVOUTNAK register field.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_USB_DEV_DCFG_ENDEVOUTNAK field value from a register.

#define ALT_USB_DEV_DCFG_ENDEVOUTNAK_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_USB_DEV_DCFG_ENDEVOUTNAK register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_DESCDMA_E_DISD   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA

Disable Scatter gather DMA

#define ALT_USB_DEV_DCFG_DESCDMA_E_END   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_DESCDMA

Enable Scatter gather DMA

#define ALT_USB_DEV_DCFG_DESCDMA_LSB   23

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field.

#define ALT_USB_DEV_DCFG_DESCDMA_MSB   23

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_DESCDMA register field.

#define ALT_USB_DEV_DCFG_DESCDMA_WIDTH   1

The width in bits of the ALT_USB_DEV_DCFG_DESCDMA register field.

#define ALT_USB_DEV_DCFG_DESCDMA_SET_MSK   0x00800000

The mask used to set the ALT_USB_DEV_DCFG_DESCDMA register field value.

#define ALT_USB_DEV_DCFG_DESCDMA_CLR_MSK   0xff7fffff

The mask used to clear the ALT_USB_DEV_DCFG_DESCDMA register field value.

#define ALT_USB_DEV_DCFG_DESCDMA_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_DESCDMA register field.

#define ALT_USB_DEV_DCFG_DESCDMA_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_USB_DEV_DCFG_DESCDMA field value from a register.

#define ALT_USB_DEV_DCFG_DESCDMA_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_USB_DEV_DCFG_DESCDMA register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF25   0x0

Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL

25% of (micro)frame

#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF50   0x1

Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL

50% of (micro)frame

#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_MF75   0x2

Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL

75% of (micro)frame

#define ALT_USB_DEV_DCFG_PERSCHINTVL_E_RSVD   0x3

Enumerated value for register field ALT_USB_DEV_DCFG_PERSCHINTVL

Reserved

#define ALT_USB_DEV_DCFG_PERSCHINTVL_LSB   24

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_MSB   25

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_PERSCHINTVL register field.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_WIDTH   2

The width in bits of the ALT_USB_DEV_DCFG_PERSCHINTVL register field.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET_MSK   0x03000000

The mask used to set the ALT_USB_DEV_DCFG_PERSCHINTVL register field value.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_CLR_MSK   0xfcffffff

The mask used to clear the ALT_USB_DEV_DCFG_PERSCHINTVL register field value.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_RESET   0x0

The reset value of the ALT_USB_DEV_DCFG_PERSCHINTVL register field.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_GET (   value)    (((value) & 0x03000000) >> 24)

Extracts the ALT_USB_DEV_DCFG_PERSCHINTVL field value from a register.

#define ALT_USB_DEV_DCFG_PERSCHINTVL_SET (   value)    (((value) << 24) & 0x03000000)

Produces a ALT_USB_DEV_DCFG_PERSCHINTVL register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_RESVALID_LSB   26

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DCFG_RESVALID register field.

#define ALT_USB_DEV_DCFG_RESVALID_MSB   31

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DCFG_RESVALID register field.

#define ALT_USB_DEV_DCFG_RESVALID_WIDTH   6

The width in bits of the ALT_USB_DEV_DCFG_RESVALID register field.

#define ALT_USB_DEV_DCFG_RESVALID_SET_MSK   0xfc000000

The mask used to set the ALT_USB_DEV_DCFG_RESVALID register field value.

#define ALT_USB_DEV_DCFG_RESVALID_CLR_MSK   0x03ffffff

The mask used to clear the ALT_USB_DEV_DCFG_RESVALID register field value.

#define ALT_USB_DEV_DCFG_RESVALID_RESET   0x2

The reset value of the ALT_USB_DEV_DCFG_RESVALID register field.

#define ALT_USB_DEV_DCFG_RESVALID_GET (   value)    (((value) & 0xfc000000) >> 26)

Extracts the ALT_USB_DEV_DCFG_RESVALID field value from a register.

#define ALT_USB_DEV_DCFG_RESVALID_SET (   value)    (((value) << 26) & 0xfc000000)

Produces a ALT_USB_DEV_DCFG_RESVALID register field value suitable for setting the register.

#define ALT_USB_DEV_DCFG_OFST   0x0

The byte offset of the ALT_USB_DEV_DCFG register from the beginning of the component.

#define ALT_USB_DEV_DCFG_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DCFG_OFST))

The address of the ALT_USB_DEV_DCFG register.

Typedef Documentation

The typedef declaration for register ALT_USB_DEV_DCFG.