Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Test IO Control Register - testioctrl

Description

Contains fields setting the IO output select for Test Clock and Debug outputs. The dedicated IO outputs includes two outputs for the Main PLL clock outputs (PLL_CLK0 and PLL_CLK1), two outputs for the Peripheral PLL clock outputs (PLL_CLK2 and PLL_CLK3), and one output for miscelaneous debug for the Main and Peripheral PLL (PLL_CLK4).

The Test Clock and Debug outputs will only propigate to the dedicated IO based on the IO pinmux configuration. If Test Clocks are selected in the pinmux, then the selects in this register determine which PLL clocks and PLL debug signals will propigate to the IOs.

Register Layout

Bits Access Reset Description
[3:0] RW 0x8 Main Clock Select
[7:4] ??? 0x0 UNDEFINED
[11:8] RW 0x8 Peripheral Clock Select
[15:12] ??? 0x0 UNDEFINED
[20:16] RW 0x10 Debug Clock Select
[31:21] ??? 0x0 UNDEFINED

Field : Main Clock Select - mainclksel

Selects the source of PLL_CLK0 and PLL_CLK1 dedicated IO outputs if selected. All of the CLKOUT# counter outputs are from the Main PLL.

The following table determines the PLL counter output select:

sel PLL_CLK0 PLL_CLK1

0000 CLKOUT0 CLKOUT8

0001 CLKOUT1 CLKOUT9

0010 CLKOUT2 CLKOUT10

0011 CLKOUT3 CLKOUT11

0100 CLKOUT4 CLKOUT13

0101 CLKOUT5 CLKOUT14

0110 CLKOUT6 CLKOUT15

0111 CLKOUT7 CLKOUT16

1xxx VSS VSS

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_LSB   0
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_MSB   3
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_WIDTH   4
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET_MSK   0x0000000f
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_CLR_MSK   0xfffffff0
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_RESET   0x8
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : Peripheral Clock Select - periclksel

Selects the source of PLL_CLK2 and PLL_CLK3 dedicated IO outputs if selected. All of the CLKOUT# counter outputs are from the Peripheral PLL.

The following table determines the PLL counter output select:

sel PLL_CLK2 PLL_CLK3

0000 CLKOUT0 CLKOUT8

0001 CLKOUT1 CLKOUT9

0010 CLKOUT2 CLKOUT10

0011 CLKOUT3 CLKOUT11

0100 CLKOUT4 CLKOUT13

0101 CLKOUT5 CLKOUT14

0110 CLKOUT6 CLKOUT15

0111 CLKOUT7 CLKOUT16

1xxx VSS VSS

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_LSB   8
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_MSB   11
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_WIDTH   4
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET_MSK   0x00000f00
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_CLR_MSK   0xfffff0ff
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_RESET   0x8
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_GET(value)   (((value) & 0x00000f00) >> 8)
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET(value)   (((value) << 8) & 0x00000f00)
 

Field : Debug Clock Select - debugclksel

Selects the source of PLL_CLK4 for miscellaneous PLL signals.

Bit[3] (p below) determines if from the debug output is from the Main or Peripheral PLL. If 0, the the output is from the Main PLL and if 1, the output is from the Peripheral PLL.

The following table determines the PLL debug output select:

sel PLL_CLK4

0p000 OUTRESETACK0

0p001 OUTRESETACK3

0p010 OUTRESETACK7

0p011 PLLRESET

0p100 OUTRESETACK15

0p101 FBSLIP

0p110 RFSLIP

0p111 LOCK

1xxxx VSS

Field Access Macros:

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_LSB   16
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_MSB   20
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_WIDTH   5
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET_MSK   0x001f0000
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_CLR_MSK   0xffe0ffff
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_RESET   0x10
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_GET(value)   (((value) & 0x001f0000) >> 16)
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET(value)   (((value) << 16) & 0x001f0000)
 

Data Structures

struct  ALT_CLKMGR_CLKMGR_TESTIOCTL_s
 

Macros

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_RESET   0x00100808
 
#define ALT_CLKMGR_CLKMGR_TESTIOCTL_OFST   0x20
 

Typedefs

typedef struct
ALT_CLKMGR_CLKMGR_TESTIOCTL_s 
ALT_CLKMGR_CLKMGR_TESTIOCTL_t
 

Data Structure Documentation

struct ALT_CLKMGR_CLKMGR_TESTIOCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_CLKMGR_TESTIOCTL.

Data Fields
uint32_t mainclksel: 4 Main Clock Select
uint32_t __pad0__: 4 UNDEFINED
uint32_t periclksel: 4 Peripheral Clock Select
uint32_t __pad1__: 4 UNDEFINED
uint32_t debugclksel: 5 Debug Clock Select
uint32_t __pad2__: 11 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_MSB   3

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_WIDTH   4

The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET_MSK   0x0000000f

The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_CLR_MSK   0xfffffff0

The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_RESET   0x8

The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL field value from a register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_MAINCLKSEL register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_LSB   8

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_MSB   11

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_WIDTH   4

The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET_MSK   0x00000f00

The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_CLR_MSK   0xfffff0ff

The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_RESET   0x8

The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_GET (   value)    (((value) & 0x00000f00) >> 8)

Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL field value from a register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL_SET (   value)    (((value) << 8) & 0x00000f00)

Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_PERICLKSEL register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_LSB   16

The Least Significant Bit (LSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_MSB   20

The Most Significant Bit (MSB) position of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_WIDTH   5

The width in bits of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET_MSK   0x001f0000

The mask used to set the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_CLR_MSK   0xffe0ffff

The mask used to clear the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_RESET   0x10

The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_GET (   value)    (((value) & 0x001f0000) >> 16)

Extracts the ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL field value from a register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL_SET (   value)    (((value) << 16) & 0x001f0000)

Produces a ALT_CLKMGR_CLKMGR_TESTIOCTL_DBGCLKSEL register field value suitable for setting the register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_RESET   0x00100808

The reset value of the ALT_CLKMGR_CLKMGR_TESTIOCTL register.

#define ALT_CLKMGR_CLKMGR_TESTIOCTL_OFST   0x20

The byte offset of the ALT_CLKMGR_CLKMGR_TESTIOCTL register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_CLKMGR_TESTIOCTL.