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alt_i2c.h
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32 
35 #ifndef __ALTERA_ALT_I2C_H__
36 #define __ALTERA_ALT_I2C_H__
37 
38 #ifdef __cplusplus
39 extern "C"
40 {
41 #endif /* __cplusplus */
42 
93 #define ALT_I2C_CON_MST_MOD_E_DIS 0x0
94 
99 #define ALT_I2C_CON_MST_MOD_E_EN 0x1
100 
102 #define ALT_I2C_CON_MST_MOD_LSB 0
103 
104 #define ALT_I2C_CON_MST_MOD_MSB 0
105 
106 #define ALT_I2C_CON_MST_MOD_WIDTH 1
107 
108 #define ALT_I2C_CON_MST_MOD_SET_MSK 0x00000001
109 
110 #define ALT_I2C_CON_MST_MOD_CLR_MSK 0xfffffffe
111 
112 #define ALT_I2C_CON_MST_MOD_RESET 0x1
113 
114 #define ALT_I2C_CON_MST_MOD_GET(value) (((value) & 0x00000001) >> 0)
115 
116 #define ALT_I2C_CON_MST_MOD_SET(value) (((value) << 0) & 0x00000001)
117 
141 #define ALT_I2C_CON_SPEED_E_STANDARD 0x1
142 
147 #define ALT_I2C_CON_SPEED_E_FAST 0x2
148 
150 #define ALT_I2C_CON_SPEED_LSB 1
151 
152 #define ALT_I2C_CON_SPEED_MSB 2
153 
154 #define ALT_I2C_CON_SPEED_WIDTH 2
155 
156 #define ALT_I2C_CON_SPEED_SET_MSK 0x00000006
157 
158 #define ALT_I2C_CON_SPEED_CLR_MSK 0xfffffff9
159 
160 #define ALT_I2C_CON_SPEED_RESET 0x2
161 
162 #define ALT_I2C_CON_SPEED_GET(value) (((value) & 0x00000006) >> 1)
163 
164 #define ALT_I2C_CON_SPEED_SET(value) (((value) << 1) & 0x00000006)
165 
189 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR7BIT 0x0
190 
195 #define ALT_I2C_CON_IC_10BITADDR_SLV_E_SLVADDR10BIT 0x1
196 
198 #define ALT_I2C_CON_IC_10BITADDR_SLV_LSB 3
199 
200 #define ALT_I2C_CON_IC_10BITADDR_SLV_MSB 3
201 
202 #define ALT_I2C_CON_IC_10BITADDR_SLV_WIDTH 1
203 
204 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET_MSK 0x00000008
205 
206 #define ALT_I2C_CON_IC_10BITADDR_SLV_CLR_MSK 0xfffffff7
207 
208 #define ALT_I2C_CON_IC_10BITADDR_SLV_RESET 0x1
209 
210 #define ALT_I2C_CON_IC_10BITADDR_SLV_GET(value) (((value) & 0x00000008) >> 3)
211 
212 #define ALT_I2C_CON_IC_10BITADDR_SLV_SET(value) (((value) << 3) & 0x00000008)
213 
235 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR7BIT 0x0
236 
241 #define ALT_I2C_CON_IC_10BITADDR_MST_E_MSTADDR10BIT 0x1
242 
244 #define ALT_I2C_CON_IC_10BITADDR_MST_LSB 4
245 
246 #define ALT_I2C_CON_IC_10BITADDR_MST_MSB 4
247 
248 #define ALT_I2C_CON_IC_10BITADDR_MST_WIDTH 1
249 
250 #define ALT_I2C_CON_IC_10BITADDR_MST_SET_MSK 0x00000010
251 
252 #define ALT_I2C_CON_IC_10BITADDR_MST_CLR_MSK 0xffffffef
253 
254 #define ALT_I2C_CON_IC_10BITADDR_MST_RESET 0x1
255 
256 #define ALT_I2C_CON_IC_10BITADDR_MST_GET(value) (((value) & 0x00000010) >> 4)
257 
258 #define ALT_I2C_CON_IC_10BITADDR_MST_SET(value) (((value) << 4) & 0x00000010)
259 
300 #define ALT_I2C_CON_IC_RESTART_EN_E_DIS 0x0
301 
306 #define ALT_I2C_CON_IC_RESTART_EN_E_EN 0x1
307 
309 #define ALT_I2C_CON_IC_RESTART_EN_LSB 5
310 
311 #define ALT_I2C_CON_IC_RESTART_EN_MSB 5
312 
313 #define ALT_I2C_CON_IC_RESTART_EN_WIDTH 1
314 
315 #define ALT_I2C_CON_IC_RESTART_EN_SET_MSK 0x00000020
316 
317 #define ALT_I2C_CON_IC_RESTART_EN_CLR_MSK 0xffffffdf
318 
319 #define ALT_I2C_CON_IC_RESTART_EN_RESET 0x1
320 
321 #define ALT_I2C_CON_IC_RESTART_EN_GET(value) (((value) & 0x00000020) >> 5)
322 
323 #define ALT_I2C_CON_IC_RESTART_EN_SET(value) (((value) << 5) & 0x00000020)
324 
349 #define ALT_I2C_CON_IC_SLV_DIS_E_DIS 0x1
350 
355 #define ALT_I2C_CON_IC_SLV_DIS_E_EN 0x0
356 
358 #define ALT_I2C_CON_IC_SLV_DIS_LSB 6
359 
360 #define ALT_I2C_CON_IC_SLV_DIS_MSB 6
361 
362 #define ALT_I2C_CON_IC_SLV_DIS_WIDTH 1
363 
364 #define ALT_I2C_CON_IC_SLV_DIS_SET_MSK 0x00000040
365 
366 #define ALT_I2C_CON_IC_SLV_DIS_CLR_MSK 0xffffffbf
367 
368 #define ALT_I2C_CON_IC_SLV_DIS_RESET 0x1
369 
370 #define ALT_I2C_CON_IC_SLV_DIS_GET(value) (((value) & 0x00000040) >> 6)
371 
372 #define ALT_I2C_CON_IC_SLV_DIS_SET(value) (((value) << 6) & 0x00000040)
373 
374 #ifndef __ASSEMBLY__
375 
386 {
387  uint32_t master_mode : 1;
388  uint32_t speed : 2;
389  uint32_t ic_10bitaddr_slave : 1;
390  uint32_t ic_10bitaddr_master : 1;
391  uint32_t ic_restart_en : 1;
392  uint32_t ic_slave_disable : 1;
393  uint32_t : 25;
394 };
395 
397 typedef volatile struct ALT_I2C_CON_s ALT_I2C_CON_t;
398 #endif /* __ASSEMBLY__ */
399 
401 #define ALT_I2C_CON_OFST 0x0
402 
403 #define ALT_I2C_CON_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CON_OFST))
404 
443 #define ALT_I2C_TAR_IC_TAR_LSB 0
444 
445 #define ALT_I2C_TAR_IC_TAR_MSB 9
446 
447 #define ALT_I2C_TAR_IC_TAR_WIDTH 10
448 
449 #define ALT_I2C_TAR_IC_TAR_SET_MSK 0x000003ff
450 
451 #define ALT_I2C_TAR_IC_TAR_CLR_MSK 0xfffffc00
452 
453 #define ALT_I2C_TAR_IC_TAR_RESET 0x55
454 
455 #define ALT_I2C_TAR_IC_TAR_GET(value) (((value) & 0x000003ff) >> 0)
456 
457 #define ALT_I2C_TAR_IC_TAR_SET(value) (((value) << 0) & 0x000003ff)
458 
484 #define ALT_I2C_TAR_GC_OR_START_E_GENCALL 0x0
485 
490 #define ALT_I2C_TAR_GC_OR_START_E_STARTBYTE 0x1
491 
493 #define ALT_I2C_TAR_GC_OR_START_LSB 10
494 
495 #define ALT_I2C_TAR_GC_OR_START_MSB 10
496 
497 #define ALT_I2C_TAR_GC_OR_START_WIDTH 1
498 
499 #define ALT_I2C_TAR_GC_OR_START_SET_MSK 0x00000400
500 
501 #define ALT_I2C_TAR_GC_OR_START_CLR_MSK 0xfffffbff
502 
503 #define ALT_I2C_TAR_GC_OR_START_RESET 0x0
504 
505 #define ALT_I2C_TAR_GC_OR_START_GET(value) (((value) & 0x00000400) >> 10)
506 
507 #define ALT_I2C_TAR_GC_OR_START_SET(value) (((value) << 10) & 0x00000400)
508 
532 #define ALT_I2C_TAR_SPECIAL_E_GENCALL 0x0
533 
538 #define ALT_I2C_TAR_SPECIAL_E_STARTBYTE 0x1
539 
541 #define ALT_I2C_TAR_SPECIAL_LSB 11
542 
543 #define ALT_I2C_TAR_SPECIAL_MSB 11
544 
545 #define ALT_I2C_TAR_SPECIAL_WIDTH 1
546 
547 #define ALT_I2C_TAR_SPECIAL_SET_MSK 0x00000800
548 
549 #define ALT_I2C_TAR_SPECIAL_CLR_MSK 0xfffff7ff
550 
551 #define ALT_I2C_TAR_SPECIAL_RESET 0x0
552 
553 #define ALT_I2C_TAR_SPECIAL_GET(value) (((value) & 0x00000800) >> 11)
554 
555 #define ALT_I2C_TAR_SPECIAL_SET(value) (((value) << 11) & 0x00000800)
556 
578 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START7 0x0
579 
584 #define ALT_I2C_TAR_IC_10BITADDR_MST_E_START10 0x1
585 
587 #define ALT_I2C_TAR_IC_10BITADDR_MST_LSB 12
588 
589 #define ALT_I2C_TAR_IC_10BITADDR_MST_MSB 12
590 
591 #define ALT_I2C_TAR_IC_10BITADDR_MST_WIDTH 1
592 
593 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET_MSK 0x00001000
594 
595 #define ALT_I2C_TAR_IC_10BITADDR_MST_CLR_MSK 0xffffefff
596 
597 #define ALT_I2C_TAR_IC_10BITADDR_MST_RESET 0x1
598 
599 #define ALT_I2C_TAR_IC_10BITADDR_MST_GET(value) (((value) & 0x00001000) >> 12)
600 
601 #define ALT_I2C_TAR_IC_10BITADDR_MST_SET(value) (((value) << 12) & 0x00001000)
602 
603 #ifndef __ASSEMBLY__
604 
615 {
616  uint32_t ic_tar : 10;
617  uint32_t gc_or_start : 1;
618  uint32_t special : 1;
619  uint32_t ic_10bitaddr_master : 1;
620  uint32_t : 19;
621 };
622 
624 typedef volatile struct ALT_I2C_TAR_s ALT_I2C_TAR_t;
625 #endif /* __ASSEMBLY__ */
626 
628 #define ALT_I2C_TAR_OFST 0x4
629 
630 #define ALT_I2C_TAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TAR_OFST))
631 
665 #define ALT_I2C_SAR_IC_SAR_LSB 0
666 
667 #define ALT_I2C_SAR_IC_SAR_MSB 9
668 
669 #define ALT_I2C_SAR_IC_SAR_WIDTH 10
670 
671 #define ALT_I2C_SAR_IC_SAR_SET_MSK 0x000003ff
672 
673 #define ALT_I2C_SAR_IC_SAR_CLR_MSK 0xfffffc00
674 
675 #define ALT_I2C_SAR_IC_SAR_RESET 0x55
676 
677 #define ALT_I2C_SAR_IC_SAR_GET(value) (((value) & 0x000003ff) >> 0)
678 
679 #define ALT_I2C_SAR_IC_SAR_SET(value) (((value) << 0) & 0x000003ff)
680 
681 #ifndef __ASSEMBLY__
682 
693 {
694  uint32_t ic_sar : 10;
695  uint32_t : 22;
696 };
697 
699 typedef volatile struct ALT_I2C_SAR_s ALT_I2C_SAR_t;
700 #endif /* __ASSEMBLY__ */
701 
703 #define ALT_I2C_SAR_OFST 0x8
704 
705 #define ALT_I2C_SAR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SAR_OFST))
706 
736 #define ALT_I2C_DATA_CMD_DAT_LSB 0
737 
738 #define ALT_I2C_DATA_CMD_DAT_MSB 7
739 
740 #define ALT_I2C_DATA_CMD_DAT_WIDTH 8
741 
742 #define ALT_I2C_DATA_CMD_DAT_SET_MSK 0x000000ff
743 
744 #define ALT_I2C_DATA_CMD_DAT_CLR_MSK 0xffffff00
745 
746 #define ALT_I2C_DATA_CMD_DAT_RESET 0x0
747 
748 #define ALT_I2C_DATA_CMD_DAT_GET(value) (((value) & 0x000000ff) >> 0)
749 
750 #define ALT_I2C_DATA_CMD_DAT_SET(value) (((value) << 0) & 0x000000ff)
751 
787 #define ALT_I2C_DATA_CMD_CMD_E_RD 0x1
788 
793 #define ALT_I2C_DATA_CMD_CMD_E_WR 0x0
794 
796 #define ALT_I2C_DATA_CMD_CMD_LSB 8
797 
798 #define ALT_I2C_DATA_CMD_CMD_MSB 8
799 
800 #define ALT_I2C_DATA_CMD_CMD_WIDTH 1
801 
802 #define ALT_I2C_DATA_CMD_CMD_SET_MSK 0x00000100
803 
804 #define ALT_I2C_DATA_CMD_CMD_CLR_MSK 0xfffffeff
805 
806 #define ALT_I2C_DATA_CMD_CMD_RESET 0x0
807 
808 #define ALT_I2C_DATA_CMD_CMD_GET(value) (((value) & 0x00000100) >> 8)
809 
810 #define ALT_I2C_DATA_CMD_CMD_SET(value) (((value) << 8) & 0x00000100)
811 
842 #define ALT_I2C_DATA_CMD_STOP_E_STOP 0x1
843 
848 #define ALT_I2C_DATA_CMD_STOP_E_NO_STOP 0x0
849 
851 #define ALT_I2C_DATA_CMD_STOP_LSB 9
852 
853 #define ALT_I2C_DATA_CMD_STOP_MSB 9
854 
855 #define ALT_I2C_DATA_CMD_STOP_WIDTH 1
856 
857 #define ALT_I2C_DATA_CMD_STOP_SET_MSK 0x00000200
858 
859 #define ALT_I2C_DATA_CMD_STOP_CLR_MSK 0xfffffdff
860 
861 #define ALT_I2C_DATA_CMD_STOP_RESET 0x0
862 
863 #define ALT_I2C_DATA_CMD_STOP_GET(value) (((value) & 0x00000200) >> 9)
864 
865 #define ALT_I2C_DATA_CMD_STOP_SET(value) (((value) << 9) & 0x00000200)
866 
895 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART 0x1
896 
901 #define ALT_I2C_DATA_CMD_RESTART_E_RESTART_ON_DIR_CHANGE 0x0
902 
904 #define ALT_I2C_DATA_CMD_RESTART_LSB 10
905 
906 #define ALT_I2C_DATA_CMD_RESTART_MSB 10
907 
908 #define ALT_I2C_DATA_CMD_RESTART_WIDTH 1
909 
910 #define ALT_I2C_DATA_CMD_RESTART_SET_MSK 0x00000400
911 
912 #define ALT_I2C_DATA_CMD_RESTART_CLR_MSK 0xfffffbff
913 
914 #define ALT_I2C_DATA_CMD_RESTART_RESET 0x0
915 
916 #define ALT_I2C_DATA_CMD_RESTART_GET(value) (((value) & 0x00000400) >> 10)
917 
918 #define ALT_I2C_DATA_CMD_RESTART_SET(value) (((value) << 10) & 0x00000400)
919 
920 #ifndef __ASSEMBLY__
921 
932 {
933  uint32_t dat : 8;
934  uint32_t cmd : 1;
935  uint32_t stop : 1;
936  uint32_t restart : 1;
937  uint32_t : 21;
938 };
939 
941 typedef volatile struct ALT_I2C_DATA_CMD_s ALT_I2C_DATA_CMD_t;
942 #endif /* __ASSEMBLY__ */
943 
945 #define ALT_I2C_DATA_CMD_OFST 0x10
946 
947 #define ALT_I2C_DATA_CMD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DATA_CMD_OFST))
948 
981 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB 0
982 
983 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB 15
984 
985 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_WIDTH 16
986 
987 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET_MSK 0x0000ffff
988 
989 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_CLR_MSK 0xffff0000
990 
991 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET 0x190
992 
993 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
994 
995 #define ALT_I2C_SS_SCL_HCNT_IC_SS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
996 
997 #ifndef __ASSEMBLY__
998 
1009 {
1010  uint32_t ic_ss_scl_hcnt : 16;
1011  uint32_t : 16;
1012 };
1013 
1016 #endif /* __ASSEMBLY__ */
1017 
1019 #define ALT_I2C_SS_SCL_HCNT_OFST 0x14
1020 
1021 #define ALT_I2C_SS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_HCNT_OFST))
1022 
1051 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB 0
1052 
1053 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB 15
1054 
1055 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_WIDTH 16
1056 
1057 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET_MSK 0x0000ffff
1058 
1059 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_CLR_MSK 0xffff0000
1060 
1061 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET 0x1d6
1062 
1063 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1064 
1065 #define ALT_I2C_SS_SCL_LCNT_IC_SS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1066 
1067 #ifndef __ASSEMBLY__
1068 
1079 {
1080  uint32_t ic_ss_scl_lcnt : 16;
1081  uint32_t : 16;
1082 };
1083 
1086 #endif /* __ASSEMBLY__ */
1087 
1089 #define ALT_I2C_SS_SCL_LCNT_OFST 0x18
1090 
1091 #define ALT_I2C_SS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SS_SCL_LCNT_OFST))
1092 
1123 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB 0
1124 
1125 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB 15
1126 
1127 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_WIDTH 16
1128 
1129 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET_MSK 0x0000ffff
1130 
1131 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_CLR_MSK 0xffff0000
1132 
1133 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET 0x3c
1134 
1135 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1136 
1137 #define ALT_I2C_FS_SCL_HCNT_IC_FS_SCL_HCNT_SET(value) (((value) << 0) & 0x0000ffff)
1138 
1139 #ifndef __ASSEMBLY__
1140 
1151 {
1152  uint32_t ic_fs_scl_hcnt : 16;
1153  uint32_t : 16;
1154 };
1155 
1158 #endif /* __ASSEMBLY__ */
1159 
1161 #define ALT_I2C_FS_SCL_HCNT_OFST 0x1c
1162 
1163 #define ALT_I2C_FS_SCL_HCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_HCNT_OFST))
1164 
1193 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB 0
1194 
1195 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB 15
1196 
1197 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_WIDTH 16
1198 
1199 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET_MSK 0x0000ffff
1200 
1201 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_CLR_MSK 0xffff0000
1202 
1203 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET 0x82
1204 
1205 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_GET(value) (((value) & 0x0000ffff) >> 0)
1206 
1207 #define ALT_I2C_FS_SCL_LCNT_IC_FS_SCL_LCNT_SET(value) (((value) << 0) & 0x0000ffff)
1208 
1209 #ifndef __ASSEMBLY__
1210 
1221 {
1222  uint32_t ic_fs_scl_lcnt : 16;
1223  uint32_t : 16;
1224 };
1225 
1228 #endif /* __ASSEMBLY__ */
1229 
1231 #define ALT_I2C_FS_SCL_LCNT_OFST 0x20
1232 
1233 #define ALT_I2C_FS_SCL_LCNT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SCL_LCNT_OFST))
1234 
1274 #define ALT_I2C_INTR_STAT_R_RX_UNDER_LSB 0
1275 
1276 #define ALT_I2C_INTR_STAT_R_RX_UNDER_MSB 0
1277 
1278 #define ALT_I2C_INTR_STAT_R_RX_UNDER_WIDTH 1
1279 
1280 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET_MSK 0x00000001
1281 
1282 #define ALT_I2C_INTR_STAT_R_RX_UNDER_CLR_MSK 0xfffffffe
1283 
1284 #define ALT_I2C_INTR_STAT_R_RX_UNDER_RESET 0x0
1285 
1286 #define ALT_I2C_INTR_STAT_R_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1287 
1288 #define ALT_I2C_INTR_STAT_R_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1289 
1303 #define ALT_I2C_INTR_STAT_R_RX_OVER_LSB 1
1304 
1305 #define ALT_I2C_INTR_STAT_R_RX_OVER_MSB 1
1306 
1307 #define ALT_I2C_INTR_STAT_R_RX_OVER_WIDTH 1
1308 
1309 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET_MSK 0x00000002
1310 
1311 #define ALT_I2C_INTR_STAT_R_RX_OVER_CLR_MSK 0xfffffffd
1312 
1313 #define ALT_I2C_INTR_STAT_R_RX_OVER_RESET 0x0
1314 
1315 #define ALT_I2C_INTR_STAT_R_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1316 
1317 #define ALT_I2C_INTR_STAT_R_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1318 
1333 #define ALT_I2C_INTR_STAT_R_RX_FULL_LSB 2
1334 
1335 #define ALT_I2C_INTR_STAT_R_RX_FULL_MSB 2
1336 
1337 #define ALT_I2C_INTR_STAT_R_RX_FULL_WIDTH 1
1338 
1339 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET_MSK 0x00000004
1340 
1341 #define ALT_I2C_INTR_STAT_R_RX_FULL_CLR_MSK 0xfffffffb
1342 
1343 #define ALT_I2C_INTR_STAT_R_RX_FULL_RESET 0x0
1344 
1345 #define ALT_I2C_INTR_STAT_R_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1346 
1347 #define ALT_I2C_INTR_STAT_R_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1348 
1361 #define ALT_I2C_INTR_STAT_R_TX_OVER_LSB 3
1362 
1363 #define ALT_I2C_INTR_STAT_R_TX_OVER_MSB 3
1364 
1365 #define ALT_I2C_INTR_STAT_R_TX_OVER_WIDTH 1
1366 
1367 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET_MSK 0x00000008
1368 
1369 #define ALT_I2C_INTR_STAT_R_TX_OVER_CLR_MSK 0xfffffff7
1370 
1371 #define ALT_I2C_INTR_STAT_R_TX_OVER_RESET 0x0
1372 
1373 #define ALT_I2C_INTR_STAT_R_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1374 
1375 #define ALT_I2C_INTR_STAT_R_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1376 
1391 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_LSB 4
1392 
1393 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_MSB 4
1394 
1395 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_WIDTH 1
1396 
1397 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET_MSK 0x00000010
1398 
1399 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_CLR_MSK 0xffffffef
1400 
1401 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_RESET 0x0
1402 
1403 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1404 
1405 #define ALT_I2C_INTR_STAT_R_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1406 
1422 #define ALT_I2C_INTR_STAT_R_RD_REQ_LSB 5
1423 
1424 #define ALT_I2C_INTR_STAT_R_RD_REQ_MSB 5
1425 
1426 #define ALT_I2C_INTR_STAT_R_RD_REQ_WIDTH 1
1427 
1428 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET_MSK 0x00000020
1429 
1430 #define ALT_I2C_INTR_STAT_R_RD_REQ_CLR_MSK 0xffffffdf
1431 
1432 #define ALT_I2C_INTR_STAT_R_RD_REQ_RESET 0x0
1433 
1434 #define ALT_I2C_INTR_STAT_R_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1435 
1436 #define ALT_I2C_INTR_STAT_R_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1437 
1456 #define ALT_I2C_INTR_STAT_R_TX_ABRT_LSB 6
1457 
1458 #define ALT_I2C_INTR_STAT_R_TX_ABRT_MSB 6
1459 
1460 #define ALT_I2C_INTR_STAT_R_TX_ABRT_WIDTH 1
1461 
1462 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET_MSK 0x00000040
1463 
1464 #define ALT_I2C_INTR_STAT_R_TX_ABRT_CLR_MSK 0xffffffbf
1465 
1466 #define ALT_I2C_INTR_STAT_R_TX_ABRT_RESET 0x0
1467 
1468 #define ALT_I2C_INTR_STAT_R_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1469 
1470 #define ALT_I2C_INTR_STAT_R_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1471 
1483 #define ALT_I2C_INTR_STAT_R_RX_DONE_LSB 7
1484 
1485 #define ALT_I2C_INTR_STAT_R_RX_DONE_MSB 7
1486 
1487 #define ALT_I2C_INTR_STAT_R_RX_DONE_WIDTH 1
1488 
1489 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET_MSK 0x00000080
1490 
1491 #define ALT_I2C_INTR_STAT_R_RX_DONE_CLR_MSK 0xffffff7f
1492 
1493 #define ALT_I2C_INTR_STAT_R_RX_DONE_RESET 0x0
1494 
1495 #define ALT_I2C_INTR_STAT_R_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1496 
1497 #define ALT_I2C_INTR_STAT_R_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1498 
1521 #define ALT_I2C_INTR_STAT_R_ACTIVITY_LSB 8
1522 
1523 #define ALT_I2C_INTR_STAT_R_ACTIVITY_MSB 8
1524 
1525 #define ALT_I2C_INTR_STAT_R_ACTIVITY_WIDTH 1
1526 
1527 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET_MSK 0x00000100
1528 
1529 #define ALT_I2C_INTR_STAT_R_ACTIVITY_CLR_MSK 0xfffffeff
1530 
1531 #define ALT_I2C_INTR_STAT_R_ACTIVITY_RESET 0x0
1532 
1533 #define ALT_I2C_INTR_STAT_R_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1534 
1535 #define ALT_I2C_INTR_STAT_R_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1536 
1547 #define ALT_I2C_INTR_STAT_R_STOP_DET_LSB 9
1548 
1549 #define ALT_I2C_INTR_STAT_R_STOP_DET_MSB 9
1550 
1551 #define ALT_I2C_INTR_STAT_R_STOP_DET_WIDTH 1
1552 
1553 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET_MSK 0x00000200
1554 
1555 #define ALT_I2C_INTR_STAT_R_STOP_DET_CLR_MSK 0xfffffdff
1556 
1557 #define ALT_I2C_INTR_STAT_R_STOP_DET_RESET 0x0
1558 
1559 #define ALT_I2C_INTR_STAT_R_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1560 
1561 #define ALT_I2C_INTR_STAT_R_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1562 
1573 #define ALT_I2C_INTR_STAT_R_START_DET_LSB 10
1574 
1575 #define ALT_I2C_INTR_STAT_R_START_DET_MSB 10
1576 
1577 #define ALT_I2C_INTR_STAT_R_START_DET_WIDTH 1
1578 
1579 #define ALT_I2C_INTR_STAT_R_START_DET_SET_MSK 0x00000400
1580 
1581 #define ALT_I2C_INTR_STAT_R_START_DET_CLR_MSK 0xfffffbff
1582 
1583 #define ALT_I2C_INTR_STAT_R_START_DET_RESET 0x0
1584 
1585 #define ALT_I2C_INTR_STAT_R_START_DET_GET(value) (((value) & 0x00000400) >> 10)
1586 
1587 #define ALT_I2C_INTR_STAT_R_START_DET_SET(value) (((value) << 10) & 0x00000400)
1588 
1601 #define ALT_I2C_INTR_STAT_R_GEN_CALL_LSB 11
1602 
1603 #define ALT_I2C_INTR_STAT_R_GEN_CALL_MSB 11
1604 
1605 #define ALT_I2C_INTR_STAT_R_GEN_CALL_WIDTH 1
1606 
1607 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET_MSK 0x00000800
1608 
1609 #define ALT_I2C_INTR_STAT_R_GEN_CALL_CLR_MSK 0xfffff7ff
1610 
1611 #define ALT_I2C_INTR_STAT_R_GEN_CALL_RESET 0x0
1612 
1613 #define ALT_I2C_INTR_STAT_R_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
1614 
1615 #define ALT_I2C_INTR_STAT_R_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
1616 
1617 #ifndef __ASSEMBLY__
1618 
1629 {
1630  const uint32_t r_rx_under : 1;
1631  const uint32_t r_rx_over : 1;
1632  const uint32_t r_rx_full : 1;
1633  const uint32_t r_tx_over : 1;
1634  const uint32_t r_tx_empty : 1;
1635  const uint32_t r_rd_req : 1;
1636  const uint32_t r_tx_abrt : 1;
1637  const uint32_t r_rx_done : 1;
1638  const uint32_t r_activity : 1;
1639  const uint32_t r_stop_det : 1;
1640  const uint32_t r_start_det : 1;
1641  const uint32_t r_gen_call : 1;
1642  uint32_t : 20;
1643 };
1644 
1647 #endif /* __ASSEMBLY__ */
1648 
1650 #define ALT_I2C_INTR_STAT_OFST 0x2c
1651 
1652 #define ALT_I2C_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_STAT_OFST))
1653 
1690 #define ALT_I2C_INTR_MSK_M_RX_UNDER_LSB 0
1691 
1692 #define ALT_I2C_INTR_MSK_M_RX_UNDER_MSB 0
1693 
1694 #define ALT_I2C_INTR_MSK_M_RX_UNDER_WIDTH 1
1695 
1696 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET_MSK 0x00000001
1697 
1698 #define ALT_I2C_INTR_MSK_M_RX_UNDER_CLR_MSK 0xfffffffe
1699 
1700 #define ALT_I2C_INTR_MSK_M_RX_UNDER_RESET 0x1
1701 
1702 #define ALT_I2C_INTR_MSK_M_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
1703 
1704 #define ALT_I2C_INTR_MSK_M_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
1705 
1719 #define ALT_I2C_INTR_MSK_M_RX_OVER_LSB 1
1720 
1721 #define ALT_I2C_INTR_MSK_M_RX_OVER_MSB 1
1722 
1723 #define ALT_I2C_INTR_MSK_M_RX_OVER_WIDTH 1
1724 
1725 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET_MSK 0x00000002
1726 
1727 #define ALT_I2C_INTR_MSK_M_RX_OVER_CLR_MSK 0xfffffffd
1728 
1729 #define ALT_I2C_INTR_MSK_M_RX_OVER_RESET 0x1
1730 
1731 #define ALT_I2C_INTR_MSK_M_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
1732 
1733 #define ALT_I2C_INTR_MSK_M_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
1734 
1749 #define ALT_I2C_INTR_MSK_M_RX_FULL_LSB 2
1750 
1751 #define ALT_I2C_INTR_MSK_M_RX_FULL_MSB 2
1752 
1753 #define ALT_I2C_INTR_MSK_M_RX_FULL_WIDTH 1
1754 
1755 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET_MSK 0x00000004
1756 
1757 #define ALT_I2C_INTR_MSK_M_RX_FULL_CLR_MSK 0xfffffffb
1758 
1759 #define ALT_I2C_INTR_MSK_M_RX_FULL_RESET 0x1
1760 
1761 #define ALT_I2C_INTR_MSK_M_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
1762 
1763 #define ALT_I2C_INTR_MSK_M_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
1764 
1777 #define ALT_I2C_INTR_MSK_M_TX_OVER_LSB 3
1778 
1779 #define ALT_I2C_INTR_MSK_M_TX_OVER_MSB 3
1780 
1781 #define ALT_I2C_INTR_MSK_M_TX_OVER_WIDTH 1
1782 
1783 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET_MSK 0x00000008
1784 
1785 #define ALT_I2C_INTR_MSK_M_TX_OVER_CLR_MSK 0xfffffff7
1786 
1787 #define ALT_I2C_INTR_MSK_M_TX_OVER_RESET 0x1
1788 
1789 #define ALT_I2C_INTR_MSK_M_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
1790 
1791 #define ALT_I2C_INTR_MSK_M_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
1792 
1808 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_LSB 4
1809 
1810 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_MSB 4
1811 
1812 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_WIDTH 1
1813 
1814 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET_MSK 0x00000010
1815 
1816 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_CLR_MSK 0xffffffef
1817 
1818 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_RESET 0x1
1819 
1820 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
1821 
1822 #define ALT_I2C_INTR_MSK_M_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
1823 
1839 #define ALT_I2C_INTR_MSK_M_RD_REQ_LSB 5
1840 
1841 #define ALT_I2C_INTR_MSK_M_RD_REQ_MSB 5
1842 
1843 #define ALT_I2C_INTR_MSK_M_RD_REQ_WIDTH 1
1844 
1845 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET_MSK 0x00000020
1846 
1847 #define ALT_I2C_INTR_MSK_M_RD_REQ_CLR_MSK 0xffffffdf
1848 
1849 #define ALT_I2C_INTR_MSK_M_RD_REQ_RESET 0x1
1850 
1851 #define ALT_I2C_INTR_MSK_M_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
1852 
1853 #define ALT_I2C_INTR_MSK_M_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
1854 
1873 #define ALT_I2C_INTR_MSK_M_TX_ABRT_LSB 6
1874 
1875 #define ALT_I2C_INTR_MSK_M_TX_ABRT_MSB 6
1876 
1877 #define ALT_I2C_INTR_MSK_M_TX_ABRT_WIDTH 1
1878 
1879 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET_MSK 0x00000040
1880 
1881 #define ALT_I2C_INTR_MSK_M_TX_ABRT_CLR_MSK 0xffffffbf
1882 
1883 #define ALT_I2C_INTR_MSK_M_TX_ABRT_RESET 0x1
1884 
1885 #define ALT_I2C_INTR_MSK_M_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
1886 
1887 #define ALT_I2C_INTR_MSK_M_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
1888 
1900 #define ALT_I2C_INTR_MSK_M_RX_DONE_LSB 7
1901 
1902 #define ALT_I2C_INTR_MSK_M_RX_DONE_MSB 7
1903 
1904 #define ALT_I2C_INTR_MSK_M_RX_DONE_WIDTH 1
1905 
1906 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET_MSK 0x00000080
1907 
1908 #define ALT_I2C_INTR_MSK_M_RX_DONE_CLR_MSK 0xffffff7f
1909 
1910 #define ALT_I2C_INTR_MSK_M_RX_DONE_RESET 0x1
1911 
1912 #define ALT_I2C_INTR_MSK_M_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
1913 
1914 #define ALT_I2C_INTR_MSK_M_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
1915 
1938 #define ALT_I2C_INTR_MSK_M_ACTIVITY_LSB 8
1939 
1940 #define ALT_I2C_INTR_MSK_M_ACTIVITY_MSB 8
1941 
1942 #define ALT_I2C_INTR_MSK_M_ACTIVITY_WIDTH 1
1943 
1944 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET_MSK 0x00000100
1945 
1946 #define ALT_I2C_INTR_MSK_M_ACTIVITY_CLR_MSK 0xfffffeff
1947 
1948 #define ALT_I2C_INTR_MSK_M_ACTIVITY_RESET 0x0
1949 
1950 #define ALT_I2C_INTR_MSK_M_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
1951 
1952 #define ALT_I2C_INTR_MSK_M_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
1953 
1964 #define ALT_I2C_INTR_MSK_M_STOP_DET_LSB 9
1965 
1966 #define ALT_I2C_INTR_MSK_M_STOP_DET_MSB 9
1967 
1968 #define ALT_I2C_INTR_MSK_M_STOP_DET_WIDTH 1
1969 
1970 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET_MSK 0x00000200
1971 
1972 #define ALT_I2C_INTR_MSK_M_STOP_DET_CLR_MSK 0xfffffdff
1973 
1974 #define ALT_I2C_INTR_MSK_M_STOP_DET_RESET 0x0
1975 
1976 #define ALT_I2C_INTR_MSK_M_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
1977 
1978 #define ALT_I2C_INTR_MSK_M_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
1979 
1990 #define ALT_I2C_INTR_MSK_M_START_DET_LSB 10
1991 
1992 #define ALT_I2C_INTR_MSK_M_START_DET_MSB 10
1993 
1994 #define ALT_I2C_INTR_MSK_M_START_DET_WIDTH 1
1995 
1996 #define ALT_I2C_INTR_MSK_M_START_DET_SET_MSK 0x00000400
1997 
1998 #define ALT_I2C_INTR_MSK_M_START_DET_CLR_MSK 0xfffffbff
1999 
2000 #define ALT_I2C_INTR_MSK_M_START_DET_RESET 0x0
2001 
2002 #define ALT_I2C_INTR_MSK_M_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2003 
2004 #define ALT_I2C_INTR_MSK_M_START_DET_SET(value) (((value) << 10) & 0x00000400)
2005 
2018 #define ALT_I2C_INTR_MSK_M_GEN_CALL_LSB 11
2019 
2020 #define ALT_I2C_INTR_MSK_M_GEN_CALL_MSB 11
2021 
2022 #define ALT_I2C_INTR_MSK_M_GEN_CALL_WIDTH 1
2023 
2024 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET_MSK 0x00000800
2025 
2026 #define ALT_I2C_INTR_MSK_M_GEN_CALL_CLR_MSK 0xfffff7ff
2027 
2028 #define ALT_I2C_INTR_MSK_M_GEN_CALL_RESET 0x1
2029 
2030 #define ALT_I2C_INTR_MSK_M_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2031 
2032 #define ALT_I2C_INTR_MSK_M_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2033 
2034 #ifndef __ASSEMBLY__
2035 
2046 {
2047  uint32_t m_rx_under : 1;
2048  uint32_t m_rx_over : 1;
2049  uint32_t m_rx_full : 1;
2050  uint32_t m_tx_over : 1;
2051  uint32_t m_tx_empty : 1;
2052  uint32_t m_rd_req : 1;
2053  uint32_t m_tx_abrt : 1;
2054  uint32_t m_rx_done : 1;
2055  uint32_t m_activity : 1;
2056  uint32_t m_stop_det : 1;
2057  uint32_t m_start_det : 1;
2058  uint32_t m_gen_call : 1;
2059  uint32_t : 20;
2060 };
2061 
2063 typedef volatile struct ALT_I2C_INTR_MSK_s ALT_I2C_INTR_MSK_t;
2064 #endif /* __ASSEMBLY__ */
2065 
2067 #define ALT_I2C_INTR_MSK_OFST 0x30
2068 
2069 #define ALT_I2C_INTR_MSK_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_INTR_MSK_OFST))
2070 
2108 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_LSB 0
2109 
2110 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_MSB 0
2111 
2112 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_WIDTH 1
2113 
2114 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET_MSK 0x00000001
2115 
2116 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_CLR_MSK 0xfffffffe
2117 
2118 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_RESET 0x0
2119 
2120 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2121 
2122 #define ALT_I2C_RAW_INTR_STAT_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2123 
2137 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_LSB 1
2138 
2139 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_MSB 1
2140 
2141 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_WIDTH 1
2142 
2143 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET_MSK 0x00000002
2144 
2145 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_CLR_MSK 0xfffffffd
2146 
2147 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_RESET 0x0
2148 
2149 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_GET(value) (((value) & 0x00000002) >> 1)
2150 
2151 #define ALT_I2C_RAW_INTR_STAT_RX_OVER_SET(value) (((value) << 1) & 0x00000002)
2152 
2167 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_LSB 2
2168 
2169 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_MSB 2
2170 
2171 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_WIDTH 1
2172 
2173 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET_MSK 0x00000004
2174 
2175 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_CLR_MSK 0xfffffffb
2176 
2177 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_RESET 0x0
2178 
2179 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_GET(value) (((value) & 0x00000004) >> 2)
2180 
2181 #define ALT_I2C_RAW_INTR_STAT_RX_FULL_SET(value) (((value) << 2) & 0x00000004)
2182 
2195 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_LSB 3
2196 
2197 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_MSB 3
2198 
2199 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_WIDTH 1
2200 
2201 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET_MSK 0x00000008
2202 
2203 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_CLR_MSK 0xfffffff7
2204 
2205 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_RESET 0x0
2206 
2207 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_GET(value) (((value) & 0x00000008) >> 3)
2208 
2209 #define ALT_I2C_RAW_INTR_STAT_TX_OVER_SET(value) (((value) << 3) & 0x00000008)
2210 
2226 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_LSB 4
2227 
2228 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_MSB 4
2229 
2230 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_WIDTH 1
2231 
2232 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET_MSK 0x00000010
2233 
2234 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_CLR_MSK 0xffffffef
2235 
2236 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_RESET 0x0
2237 
2238 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_GET(value) (((value) & 0x00000010) >> 4)
2239 
2240 #define ALT_I2C_RAW_INTR_STAT_TX_EMPTY_SET(value) (((value) << 4) & 0x00000010)
2241 
2257 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_LSB 5
2258 
2259 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_MSB 5
2260 
2261 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_WIDTH 1
2262 
2263 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET_MSK 0x00000020
2264 
2265 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_CLR_MSK 0xffffffdf
2266 
2267 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_RESET 0x0
2268 
2269 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_GET(value) (((value) & 0x00000020) >> 5)
2270 
2271 #define ALT_I2C_RAW_INTR_STAT_RD_REQ_SET(value) (((value) << 5) & 0x00000020)
2272 
2291 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_LSB 6
2292 
2293 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_MSB 6
2294 
2295 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_WIDTH 1
2296 
2297 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET_MSK 0x00000040
2298 
2299 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_CLR_MSK 0xffffffbf
2300 
2301 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_RESET 0x0
2302 
2303 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_GET(value) (((value) & 0x00000040) >> 6)
2304 
2305 #define ALT_I2C_RAW_INTR_STAT_TX_ABRT_SET(value) (((value) << 6) & 0x00000040)
2306 
2318 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_LSB 7
2319 
2320 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_MSB 7
2321 
2322 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_WIDTH 1
2323 
2324 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET_MSK 0x00000080
2325 
2326 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_CLR_MSK 0xffffff7f
2327 
2328 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_RESET 0x0
2329 
2330 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_GET(value) (((value) & 0x00000080) >> 7)
2331 
2332 #define ALT_I2C_RAW_INTR_STAT_RX_DONE_SET(value) (((value) << 7) & 0x00000080)
2333 
2356 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_LSB 8
2357 
2358 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_MSB 8
2359 
2360 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_WIDTH 1
2361 
2362 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET_MSK 0x00000100
2363 
2364 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_CLR_MSK 0xfffffeff
2365 
2366 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_RESET 0x0
2367 
2368 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_GET(value) (((value) & 0x00000100) >> 8)
2369 
2370 #define ALT_I2C_RAW_INTR_STAT_ACTIVITY_SET(value) (((value) << 8) & 0x00000100)
2371 
2382 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_LSB 9
2383 
2384 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_MSB 9
2385 
2386 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_WIDTH 1
2387 
2388 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET_MSK 0x00000200
2389 
2390 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_CLR_MSK 0xfffffdff
2391 
2392 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_RESET 0x0
2393 
2394 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_GET(value) (((value) & 0x00000200) >> 9)
2395 
2396 #define ALT_I2C_RAW_INTR_STAT_STOP_DET_SET(value) (((value) << 9) & 0x00000200)
2397 
2408 #define ALT_I2C_RAW_INTR_STAT_START_DET_LSB 10
2409 
2410 #define ALT_I2C_RAW_INTR_STAT_START_DET_MSB 10
2411 
2412 #define ALT_I2C_RAW_INTR_STAT_START_DET_WIDTH 1
2413 
2414 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET_MSK 0x00000400
2415 
2416 #define ALT_I2C_RAW_INTR_STAT_START_DET_CLR_MSK 0xfffffbff
2417 
2418 #define ALT_I2C_RAW_INTR_STAT_START_DET_RESET 0x0
2419 
2420 #define ALT_I2C_RAW_INTR_STAT_START_DET_GET(value) (((value) & 0x00000400) >> 10)
2421 
2422 #define ALT_I2C_RAW_INTR_STAT_START_DET_SET(value) (((value) << 10) & 0x00000400)
2423 
2436 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_LSB 11
2437 
2438 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_MSB 11
2439 
2440 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_WIDTH 1
2441 
2442 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET_MSK 0x00000800
2443 
2444 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_CLR_MSK 0xfffff7ff
2445 
2446 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_RESET 0x0
2447 
2448 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_GET(value) (((value) & 0x00000800) >> 11)
2449 
2450 #define ALT_I2C_RAW_INTR_STAT_GEN_CALL_SET(value) (((value) << 11) & 0x00000800)
2451 
2452 #ifndef __ASSEMBLY__
2453 
2464 {
2465  const uint32_t rx_under : 1;
2466  const uint32_t rx_over : 1;
2467  const uint32_t rx_full : 1;
2468  const uint32_t tx_over : 1;
2469  const uint32_t tx_empty : 1;
2470  const uint32_t rd_req : 1;
2471  const uint32_t tx_abrt : 1;
2472  const uint32_t rx_done : 1;
2473  const uint32_t activity : 1;
2474  const uint32_t stop_det : 1;
2475  const uint32_t start_det : 1;
2476  const uint32_t gen_call : 1;
2477  uint32_t : 20;
2478 };
2479 
2482 #endif /* __ASSEMBLY__ */
2483 
2485 #define ALT_I2C_RAW_INTR_STAT_OFST 0x34
2486 
2487 #define ALT_I2C_RAW_INTR_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RAW_INTR_STAT_OFST))
2488 
2516 #define ALT_I2C_RX_TL_RX_TL_LSB 0
2517 
2518 #define ALT_I2C_RX_TL_RX_TL_MSB 7
2519 
2520 #define ALT_I2C_RX_TL_RX_TL_WIDTH 8
2521 
2522 #define ALT_I2C_RX_TL_RX_TL_SET_MSK 0x000000ff
2523 
2524 #define ALT_I2C_RX_TL_RX_TL_CLR_MSK 0xffffff00
2525 
2526 #define ALT_I2C_RX_TL_RX_TL_RESET 0x0
2527 
2528 #define ALT_I2C_RX_TL_RX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2529 
2530 #define ALT_I2C_RX_TL_RX_TL_SET(value) (((value) << 0) & 0x000000ff)
2531 
2532 #ifndef __ASSEMBLY__
2533 
2544 {
2545  uint32_t rx_tl : 8;
2546  uint32_t : 24;
2547 };
2548 
2550 typedef volatile struct ALT_I2C_RX_TL_s ALT_I2C_RX_TL_t;
2551 #endif /* __ASSEMBLY__ */
2552 
2554 #define ALT_I2C_RX_TL_OFST 0x38
2555 
2556 #define ALT_I2C_RX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RX_TL_OFST))
2557 
2585 #define ALT_I2C_TX_TL_TX_TL_LSB 0
2586 
2587 #define ALT_I2C_TX_TL_TX_TL_MSB 7
2588 
2589 #define ALT_I2C_TX_TL_TX_TL_WIDTH 8
2590 
2591 #define ALT_I2C_TX_TL_TX_TL_SET_MSK 0x000000ff
2592 
2593 #define ALT_I2C_TX_TL_TX_TL_CLR_MSK 0xffffff00
2594 
2595 #define ALT_I2C_TX_TL_TX_TL_RESET 0x0
2596 
2597 #define ALT_I2C_TX_TL_TX_TL_GET(value) (((value) & 0x000000ff) >> 0)
2598 
2599 #define ALT_I2C_TX_TL_TX_TL_SET(value) (((value) << 0) & 0x000000ff)
2600 
2601 #ifndef __ASSEMBLY__
2602 
2613 {
2614  uint32_t tx_tl : 8;
2615  uint32_t : 24;
2616 };
2617 
2619 typedef volatile struct ALT_I2C_TX_TL_s ALT_I2C_TX_TL_t;
2620 #endif /* __ASSEMBLY__ */
2621 
2623 #define ALT_I2C_TX_TL_OFST 0x3c
2624 
2625 #define ALT_I2C_TX_TL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_TL_OFST))
2626 
2652 #define ALT_I2C_CLR_INTR_CLR_INTR_LSB 0
2653 
2654 #define ALT_I2C_CLR_INTR_CLR_INTR_MSB 0
2655 
2656 #define ALT_I2C_CLR_INTR_CLR_INTR_WIDTH 1
2657 
2658 #define ALT_I2C_CLR_INTR_CLR_INTR_SET_MSK 0x00000001
2659 
2660 #define ALT_I2C_CLR_INTR_CLR_INTR_CLR_MSK 0xfffffffe
2661 
2662 #define ALT_I2C_CLR_INTR_CLR_INTR_RESET 0x0
2663 
2664 #define ALT_I2C_CLR_INTR_CLR_INTR_GET(value) (((value) & 0x00000001) >> 0)
2665 
2666 #define ALT_I2C_CLR_INTR_CLR_INTR_SET(value) (((value) << 0) & 0x00000001)
2667 
2668 #ifndef __ASSEMBLY__
2669 
2680 {
2681  const uint32_t clr_intr : 1;
2682  uint32_t : 31;
2683 };
2684 
2686 typedef volatile struct ALT_I2C_CLR_INTR_s ALT_I2C_CLR_INTR_t;
2687 #endif /* __ASSEMBLY__ */
2688 
2690 #define ALT_I2C_CLR_INTR_OFST 0x40
2691 
2692 #define ALT_I2C_CLR_INTR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_INTR_OFST))
2693 
2717 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_LSB 0
2718 
2719 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_MSB 0
2720 
2721 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_WIDTH 1
2722 
2723 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET_MSK 0x00000001
2724 
2725 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_CLR_MSK 0xfffffffe
2726 
2727 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_RESET 0x0
2728 
2729 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_GET(value) (((value) & 0x00000001) >> 0)
2730 
2731 #define ALT_I2C_CLR_RX_UNDER_CLR_RX_UNDER_SET(value) (((value) << 0) & 0x00000001)
2732 
2733 #ifndef __ASSEMBLY__
2734 
2745 {
2746  const uint32_t clr_rx_under : 1;
2747  uint32_t : 31;
2748 };
2749 
2752 #endif /* __ASSEMBLY__ */
2753 
2755 #define ALT_I2C_CLR_RX_UNDER_OFST 0x44
2756 
2757 #define ALT_I2C_CLR_RX_UNDER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_UNDER_OFST))
2758 
2782 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_LSB 0
2783 
2784 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_MSB 0
2785 
2786 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_WIDTH 1
2787 
2788 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET_MSK 0x00000001
2789 
2790 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_CLR_MSK 0xfffffffe
2791 
2792 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_RESET 0x0
2793 
2794 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2795 
2796 #define ALT_I2C_CLR_RX_OVER_CLR_RX_OVER_SET(value) (((value) << 0) & 0x00000001)
2797 
2798 #ifndef __ASSEMBLY__
2799 
2810 {
2811  const uint32_t clr_rx_over : 1;
2812  uint32_t : 31;
2813 };
2814 
2817 #endif /* __ASSEMBLY__ */
2818 
2820 #define ALT_I2C_CLR_RX_OVER_OFST 0x48
2821 
2822 #define ALT_I2C_CLR_RX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_OVER_OFST))
2823 
2847 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_LSB 0
2848 
2849 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_MSB 0
2850 
2851 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_WIDTH 1
2852 
2853 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET_MSK 0x00000001
2854 
2855 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_CLR_MSK 0xfffffffe
2856 
2857 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_RESET 0x0
2858 
2859 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_GET(value) (((value) & 0x00000001) >> 0)
2860 
2861 #define ALT_I2C_CLR_TX_OVER_CLR_TX_OVER_SET(value) (((value) << 0) & 0x00000001)
2862 
2863 #ifndef __ASSEMBLY__
2864 
2875 {
2876  const uint32_t clr_tx_over : 1;
2877  uint32_t : 31;
2878 };
2879 
2882 #endif /* __ASSEMBLY__ */
2883 
2885 #define ALT_I2C_CLR_TX_OVER_OFST 0x4c
2886 
2887 #define ALT_I2C_CLR_TX_OVER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_OVER_OFST))
2888 
2912 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_LSB 0
2913 
2914 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_MSB 0
2915 
2916 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_WIDTH 1
2917 
2918 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET_MSK 0x00000001
2919 
2920 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_CLR_MSK 0xfffffffe
2921 
2922 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_RESET 0x0
2923 
2924 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_GET(value) (((value) & 0x00000001) >> 0)
2925 
2926 #define ALT_I2C_CLR_RD_REQ_CLR_RD_REQ_SET(value) (((value) << 0) & 0x00000001)
2927 
2928 #ifndef __ASSEMBLY__
2929 
2940 {
2941  const uint32_t clr_rd_req : 1;
2942  uint32_t : 31;
2943 };
2944 
2947 #endif /* __ASSEMBLY__ */
2948 
2950 #define ALT_I2C_CLR_RD_REQ_OFST 0x50
2951 
2952 #define ALT_I2C_CLR_RD_REQ_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RD_REQ_OFST))
2953 
2980 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_LSB 0
2981 
2982 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_MSB 0
2983 
2984 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_WIDTH 1
2985 
2986 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET_MSK 0x00000001
2987 
2988 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_CLR_MSK 0xfffffffe
2989 
2990 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_RESET 0x0
2991 
2992 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_GET(value) (((value) & 0x00000001) >> 0)
2993 
2994 #define ALT_I2C_CLR_TX_ABRT_CLR_TX_ABT_SET(value) (((value) << 0) & 0x00000001)
2995 
2996 #ifndef __ASSEMBLY__
2997 
3008 {
3009  const uint32_t clr_tx_abort : 1;
3010  uint32_t : 31;
3011 };
3012 
3015 #endif /* __ASSEMBLY__ */
3016 
3018 #define ALT_I2C_CLR_TX_ABRT_OFST 0x54
3019 
3020 #define ALT_I2C_CLR_TX_ABRT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_TX_ABRT_OFST))
3021 
3045 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_LSB 0
3046 
3047 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_MSB 0
3048 
3049 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_WIDTH 1
3050 
3051 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET_MSK 0x00000001
3052 
3053 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_CLR_MSK 0xfffffffe
3054 
3055 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_RESET 0x0
3056 
3057 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_GET(value) (((value) & 0x00000001) >> 0)
3058 
3059 #define ALT_I2C_CLR_RX_DONE_CLR_RX_DONE_SET(value) (((value) << 0) & 0x00000001)
3060 
3061 #ifndef __ASSEMBLY__
3062 
3073 {
3074  const uint32_t clr_rx_done : 1;
3075  uint32_t : 31;
3076 };
3077 
3080 #endif /* __ASSEMBLY__ */
3081 
3083 #define ALT_I2C_CLR_RX_DONE_OFST 0x58
3084 
3085 #define ALT_I2C_CLR_RX_DONE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_RX_DONE_OFST))
3086 
3114 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_LSB 0
3115 
3116 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_MSB 0
3117 
3118 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_WIDTH 1
3119 
3120 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET_MSK 0x00000001
3121 
3122 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_CLR_MSK 0xfffffffe
3123 
3124 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_RESET 0x0
3125 
3126 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3127 
3128 #define ALT_I2C_CLR_ACTIVITY_CLR_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3129 
3130 #ifndef __ASSEMBLY__
3131 
3142 {
3143  const uint32_t clr_activity : 1;
3144  uint32_t : 31;
3145 };
3146 
3149 #endif /* __ASSEMBLY__ */
3150 
3152 #define ALT_I2C_CLR_ACTIVITY_OFST 0x5c
3153 
3154 #define ALT_I2C_CLR_ACTIVITY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_ACTIVITY_OFST))
3155 
3179 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_LSB 0
3180 
3181 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_MSB 0
3182 
3183 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_WIDTH 1
3184 
3185 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET_MSK 0x00000001
3186 
3187 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_CLR_MSK 0xfffffffe
3188 
3189 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_RESET 0x0
3190 
3191 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_GET(value) (((value) & 0x00000001) >> 0)
3192 
3193 #define ALT_I2C_CLR_STOP_DET_CLR_STOP_DET_SET(value) (((value) << 0) & 0x00000001)
3194 
3195 #ifndef __ASSEMBLY__
3196 
3207 {
3208  const uint32_t clr_stop_det : 1;
3209  uint32_t : 31;
3210 };
3211 
3214 #endif /* __ASSEMBLY__ */
3215 
3217 #define ALT_I2C_CLR_STOP_DET_OFST 0x60
3218 
3219 #define ALT_I2C_CLR_STOP_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_STOP_DET_OFST))
3220 
3244 #define ALT_I2C_CLR_START_DET_CLR_START_DET_LSB 0
3245 
3246 #define ALT_I2C_CLR_START_DET_CLR_START_DET_MSB 0
3247 
3248 #define ALT_I2C_CLR_START_DET_CLR_START_DET_WIDTH 1
3249 
3250 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET_MSK 0x00000001
3251 
3252 #define ALT_I2C_CLR_START_DET_CLR_START_DET_CLR_MSK 0xfffffffe
3253 
3254 #define ALT_I2C_CLR_START_DET_CLR_START_DET_RESET 0x0
3255 
3256 #define ALT_I2C_CLR_START_DET_CLR_START_DET_GET(value) (((value) & 0x00000001) >> 0)
3257 
3258 #define ALT_I2C_CLR_START_DET_CLR_START_DET_SET(value) (((value) << 0) & 0x00000001)
3259 
3260 #ifndef __ASSEMBLY__
3261 
3272 {
3273  const uint32_t clr_start_det : 1;
3274  uint32_t : 31;
3275 };
3276 
3279 #endif /* __ASSEMBLY__ */
3280 
3282 #define ALT_I2C_CLR_START_DET_OFST 0x64
3283 
3284 #define ALT_I2C_CLR_START_DET_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_START_DET_OFST))
3285 
3309 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_LSB 0
3310 
3311 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_MSB 0
3312 
3313 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_WIDTH 1
3314 
3315 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET_MSK 0x00000001
3316 
3317 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_CLR_MSK 0xfffffffe
3318 
3319 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_RESET 0x0
3320 
3321 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
3322 
3323 #define ALT_I2C_CLR_GEN_CALL_CLR_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
3324 
3325 #ifndef __ASSEMBLY__
3326 
3337 {
3338  const uint32_t clr_gen_call : 1;
3339  uint32_t : 31;
3340 };
3341 
3344 #endif /* __ASSEMBLY__ */
3345 
3347 #define ALT_I2C_CLR_GEN_CALL_OFST 0x68
3348 
3349 #define ALT_I2C_CLR_GEN_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_CLR_GEN_CALL_OFST))
3350 
3419 #define ALT_I2C_EN_EN_E_DIS 0x0
3420 
3425 #define ALT_I2C_EN_EN_E_EN 0x1
3426 
3428 #define ALT_I2C_EN_EN_LSB 0
3429 
3430 #define ALT_I2C_EN_EN_MSB 0
3431 
3432 #define ALT_I2C_EN_EN_WIDTH 1
3433 
3434 #define ALT_I2C_EN_EN_SET_MSK 0x00000001
3435 
3436 #define ALT_I2C_EN_EN_CLR_MSK 0xfffffffe
3437 
3438 #define ALT_I2C_EN_EN_RESET 0x0
3439 
3440 #define ALT_I2C_EN_EN_GET(value) (((value) & 0x00000001) >> 0)
3441 
3442 #define ALT_I2C_EN_EN_SET(value) (((value) << 0) & 0x00000001)
3443 
3453 #define ALT_I2C_EN_TXABT_LSB 1
3454 
3455 #define ALT_I2C_EN_TXABT_MSB 1
3456 
3457 #define ALT_I2C_EN_TXABT_WIDTH 1
3458 
3459 #define ALT_I2C_EN_TXABT_SET_MSK 0x00000002
3460 
3461 #define ALT_I2C_EN_TXABT_CLR_MSK 0xfffffffd
3462 
3463 #define ALT_I2C_EN_TXABT_RESET 0x0
3464 
3465 #define ALT_I2C_EN_TXABT_GET(value) (((value) & 0x00000002) >> 1)
3466 
3467 #define ALT_I2C_EN_TXABT_SET(value) (((value) << 1) & 0x00000002)
3468 
3469 #ifndef __ASSEMBLY__
3470 
3481 {
3482  uint32_t enable : 1;
3483  uint32_t txabort : 1;
3484  uint32_t : 30;
3485 };
3486 
3488 typedef volatile struct ALT_I2C_EN_s ALT_I2C_EN_t;
3489 #endif /* __ASSEMBLY__ */
3490 
3492 #define ALT_I2C_EN_OFST 0x6c
3493 
3494 #define ALT_I2C_EN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_OFST))
3495 
3535 #define ALT_I2C_STAT_ACTIVITY_LSB 0
3536 
3537 #define ALT_I2C_STAT_ACTIVITY_MSB 0
3538 
3539 #define ALT_I2C_STAT_ACTIVITY_WIDTH 1
3540 
3541 #define ALT_I2C_STAT_ACTIVITY_SET_MSK 0x00000001
3542 
3543 #define ALT_I2C_STAT_ACTIVITY_CLR_MSK 0xfffffffe
3544 
3545 #define ALT_I2C_STAT_ACTIVITY_RESET 0x0
3546 
3547 #define ALT_I2C_STAT_ACTIVITY_GET(value) (((value) & 0x00000001) >> 0)
3548 
3549 #define ALT_I2C_STAT_ACTIVITY_SET(value) (((value) << 0) & 0x00000001)
3550 
3571 #define ALT_I2C_STAT_TFNF_E_FULL 0x0
3572 
3577 #define ALT_I2C_STAT_TFNF_E_NOTFULL 0x1
3578 
3580 #define ALT_I2C_STAT_TFNF_LSB 1
3581 
3582 #define ALT_I2C_STAT_TFNF_MSB 1
3583 
3584 #define ALT_I2C_STAT_TFNF_WIDTH 1
3585 
3586 #define ALT_I2C_STAT_TFNF_SET_MSK 0x00000002
3587 
3588 #define ALT_I2C_STAT_TFNF_CLR_MSK 0xfffffffd
3589 
3590 #define ALT_I2C_STAT_TFNF_RESET 0x1
3591 
3592 #define ALT_I2C_STAT_TFNF_GET(value) (((value) & 0x00000002) >> 1)
3593 
3594 #define ALT_I2C_STAT_TFNF_SET(value) (((value) << 1) & 0x00000002)
3595 
3616 #define ALT_I2C_STAT_TFE_E_NOTEMPTY 0x0
3617 
3622 #define ALT_I2C_STAT_TFE_E_EMPTY 0x1
3623 
3625 #define ALT_I2C_STAT_TFE_LSB 2
3626 
3627 #define ALT_I2C_STAT_TFE_MSB 2
3628 
3629 #define ALT_I2C_STAT_TFE_WIDTH 1
3630 
3631 #define ALT_I2C_STAT_TFE_SET_MSK 0x00000004
3632 
3633 #define ALT_I2C_STAT_TFE_CLR_MSK 0xfffffffb
3634 
3635 #define ALT_I2C_STAT_TFE_RESET 0x1
3636 
3637 #define ALT_I2C_STAT_TFE_GET(value) (((value) & 0x00000004) >> 2)
3638 
3639 #define ALT_I2C_STAT_TFE_SET(value) (((value) << 2) & 0x00000004)
3640 
3661 #define ALT_I2C_STAT_RFNE_E_EMPTY 0x0
3662 
3667 #define ALT_I2C_STAT_RFNE_E_NOTEMPTY 0x1
3668 
3670 #define ALT_I2C_STAT_RFNE_LSB 3
3671 
3672 #define ALT_I2C_STAT_RFNE_MSB 3
3673 
3674 #define ALT_I2C_STAT_RFNE_WIDTH 1
3675 
3676 #define ALT_I2C_STAT_RFNE_SET_MSK 0x00000008
3677 
3678 #define ALT_I2C_STAT_RFNE_CLR_MSK 0xfffffff7
3679 
3680 #define ALT_I2C_STAT_RFNE_RESET 0x0
3681 
3682 #define ALT_I2C_STAT_RFNE_GET(value) (((value) & 0x00000008) >> 3)
3683 
3684 #define ALT_I2C_STAT_RFNE_SET(value) (((value) << 3) & 0x00000008)
3685 
3706 #define ALT_I2C_STAT_RFF_E_NOTFULL 0x0
3707 
3712 #define ALT_I2C_STAT_RFF_E_FULL 0x1
3713 
3715 #define ALT_I2C_STAT_RFF_LSB 4
3716 
3717 #define ALT_I2C_STAT_RFF_MSB 4
3718 
3719 #define ALT_I2C_STAT_RFF_WIDTH 1
3720 
3721 #define ALT_I2C_STAT_RFF_SET_MSK 0x00000010
3722 
3723 #define ALT_I2C_STAT_RFF_CLR_MSK 0xffffffef
3724 
3725 #define ALT_I2C_STAT_RFF_RESET 0x0
3726 
3727 #define ALT_I2C_STAT_RFF_GET(value) (((value) & 0x00000010) >> 4)
3728 
3729 #define ALT_I2C_STAT_RFF_SET(value) (((value) << 4) & 0x00000010)
3730 
3755 #define ALT_I2C_STAT_MST_ACTIVITY_E_IDLE 0x0
3756 
3761 #define ALT_I2C_STAT_MST_ACTIVITY_E_NOTIDLE 0x1
3762 
3764 #define ALT_I2C_STAT_MST_ACTIVITY_LSB 5
3765 
3766 #define ALT_I2C_STAT_MST_ACTIVITY_MSB 5
3767 
3768 #define ALT_I2C_STAT_MST_ACTIVITY_WIDTH 1
3769 
3770 #define ALT_I2C_STAT_MST_ACTIVITY_SET_MSK 0x00000020
3771 
3772 #define ALT_I2C_STAT_MST_ACTIVITY_CLR_MSK 0xffffffdf
3773 
3774 #define ALT_I2C_STAT_MST_ACTIVITY_RESET 0x0
3775 
3776 #define ALT_I2C_STAT_MST_ACTIVITY_GET(value) (((value) & 0x00000020) >> 5)
3777 
3778 #define ALT_I2C_STAT_MST_ACTIVITY_SET(value) (((value) << 5) & 0x00000020)
3779 
3803 #define ALT_I2C_STAT_SLV_ACTIVITY_E_IDLE 0x0
3804 
3809 #define ALT_I2C_STAT_SLV_ACTIVITY_E_NOTIDLE 0x1
3810 
3812 #define ALT_I2C_STAT_SLV_ACTIVITY_LSB 6
3813 
3814 #define ALT_I2C_STAT_SLV_ACTIVITY_MSB 6
3815 
3816 #define ALT_I2C_STAT_SLV_ACTIVITY_WIDTH 1
3817 
3818 #define ALT_I2C_STAT_SLV_ACTIVITY_SET_MSK 0x00000040
3819 
3820 #define ALT_I2C_STAT_SLV_ACTIVITY_CLR_MSK 0xffffffbf
3821 
3822 #define ALT_I2C_STAT_SLV_ACTIVITY_RESET 0x0
3823 
3824 #define ALT_I2C_STAT_SLV_ACTIVITY_GET(value) (((value) & 0x00000040) >> 6)
3825 
3826 #define ALT_I2C_STAT_SLV_ACTIVITY_SET(value) (((value) << 6) & 0x00000040)
3827 
3828 #ifndef __ASSEMBLY__
3829 
3840 {
3841  const uint32_t activity : 1;
3842  const uint32_t tfnf : 1;
3843  const uint32_t tfe : 1;
3844  const uint32_t rfne : 1;
3845  const uint32_t rff : 1;
3846  const uint32_t mst_activity : 1;
3847  const uint32_t slv_activity : 1;
3848  uint32_t : 25;
3849 };
3850 
3852 typedef volatile struct ALT_I2C_STAT_s ALT_I2C_STAT_t;
3853 #endif /* __ASSEMBLY__ */
3854 
3856 #define ALT_I2C_STAT_OFST 0x70
3857 
3858 #define ALT_I2C_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_STAT_OFST))
3859 
3891 #define ALT_I2C_TXFLR_TXFLR_LSB 0
3892 
3893 #define ALT_I2C_TXFLR_TXFLR_MSB 6
3894 
3895 #define ALT_I2C_TXFLR_TXFLR_WIDTH 7
3896 
3897 #define ALT_I2C_TXFLR_TXFLR_SET_MSK 0x0000007f
3898 
3899 #define ALT_I2C_TXFLR_TXFLR_CLR_MSK 0xffffff80
3900 
3901 #define ALT_I2C_TXFLR_TXFLR_RESET 0x0
3902 
3903 #define ALT_I2C_TXFLR_TXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3904 
3905 #define ALT_I2C_TXFLR_TXFLR_SET(value) (((value) << 0) & 0x0000007f)
3906 
3907 #ifndef __ASSEMBLY__
3908 
3919 {
3920  const uint32_t txflr : 7;
3921  uint32_t : 25;
3922 };
3923 
3925 typedef volatile struct ALT_I2C_TXFLR_s ALT_I2C_TXFLR_t;
3926 #endif /* __ASSEMBLY__ */
3927 
3929 #define ALT_I2C_TXFLR_OFST 0x74
3930 
3931 #define ALT_I2C_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TXFLR_OFST))
3932 
3963 #define ALT_I2C_RXFLR_RXFLR_LSB 0
3964 
3965 #define ALT_I2C_RXFLR_RXFLR_MSB 6
3966 
3967 #define ALT_I2C_RXFLR_RXFLR_WIDTH 7
3968 
3969 #define ALT_I2C_RXFLR_RXFLR_SET_MSK 0x0000007f
3970 
3971 #define ALT_I2C_RXFLR_RXFLR_CLR_MSK 0xffffff80
3972 
3973 #define ALT_I2C_RXFLR_RXFLR_RESET 0x0
3974 
3975 #define ALT_I2C_RXFLR_RXFLR_GET(value) (((value) & 0x0000007f) >> 0)
3976 
3977 #define ALT_I2C_RXFLR_RXFLR_SET(value) (((value) << 0) & 0x0000007f)
3978 
3979 #ifndef __ASSEMBLY__
3980 
3991 {
3992  const uint32_t rxflr : 7;
3993  uint32_t : 25;
3994 };
3995 
3997 typedef volatile struct ALT_I2C_RXFLR_s ALT_I2C_RXFLR_t;
3998 #endif /* __ASSEMBLY__ */
3999 
4001 #define ALT_I2C_RXFLR_OFST 0x78
4002 
4003 #define ALT_I2C_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_RXFLR_OFST))
4004 
4030 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_LSB 0
4031 
4032 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_MSB 15
4033 
4034 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_WIDTH 16
4035 
4036 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET_MSK 0x0000ffff
4037 
4038 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_CLR_MSK 0xffff0000
4039 
4040 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_RESET 0x1
4041 
4042 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_GET(value) (((value) & 0x0000ffff) >> 0)
4043 
4044 #define ALT_I2C_SDA_HOLD_IC_SDA_HOLD_SET(value) (((value) << 0) & 0x0000ffff)
4045 
4046 #ifndef __ASSEMBLY__
4047 
4058 {
4059  uint32_t ic_sda_hold : 16;
4060  uint32_t : 16;
4061 };
4062 
4064 typedef volatile struct ALT_I2C_SDA_HOLD_s ALT_I2C_SDA_HOLD_t;
4065 #endif /* __ASSEMBLY__ */
4066 
4068 #define ALT_I2C_SDA_HOLD_OFST 0x7c
4069 
4070 #define ALT_I2C_SDA_HOLD_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_HOLD_OFST))
4071 
4118 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB 0
4119 
4120 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB 0
4121 
4122 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH 1
4123 
4124 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK 0x00000001
4125 
4126 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK 0xfffffffe
4127 
4128 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET 0x0
4129 
4130 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value) (((value) & 0x00000001) >> 0)
4131 
4132 #define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value) (((value) << 0) & 0x00000001)
4133 
4144 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB 1
4145 
4146 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB 1
4147 
4148 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH 1
4149 
4150 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK 0x00000002
4151 
4152 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK 0xfffffffd
4153 
4154 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET 0x0
4155 
4156 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value) (((value) & 0x00000002) >> 1)
4157 
4158 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value) (((value) << 1) & 0x00000002)
4159 
4171 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB 2
4172 
4173 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB 2
4174 
4175 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH 1
4176 
4177 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK 0x00000004
4178 
4179 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK 0xfffffffb
4180 
4181 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET 0x0
4182 
4183 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value) (((value) & 0x00000004) >> 2)
4184 
4185 #define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value) (((value) << 2) & 0x00000004)
4186 
4198 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB 3
4199 
4200 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB 3
4201 
4202 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH 1
4203 
4204 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK 0x00000008
4205 
4206 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK 0xfffffff7
4207 
4208 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET 0x0
4209 
4210 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value) (((value) & 0x00000008) >> 3)
4211 
4212 #define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value) (((value) << 3) & 0x00000008)
4213 
4224 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB 4
4225 
4226 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB 4
4227 
4228 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH 1
4229 
4230 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK 0x00000010
4231 
4232 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK 0xffffffef
4233 
4234 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET 0x0
4235 
4236 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value) (((value) & 0x00000010) >> 4)
4237 
4238 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value) (((value) << 4) & 0x00000010)
4239 
4251 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB 5
4252 
4253 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB 5
4254 
4255 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH 1
4256 
4257 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK 0x00000020
4258 
4259 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK 0xffffffdf
4260 
4261 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET 0x0
4262 
4263 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value) (((value) & 0x00000020) >> 5)
4264 
4265 #define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value) (((value) << 5) & 0x00000020)
4266 
4277 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB 6
4278 
4279 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB 6
4280 
4281 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH 1
4282 
4283 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK 0x00000040
4284 
4285 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK 0xffffffbf
4286 
4287 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET 0x0
4288 
4289 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value) (((value) & 0x00000040) >> 6)
4290 
4291 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value) (((value) << 6) & 0x00000040)
4292 
4303 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB 7
4304 
4305 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB 7
4306 
4307 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH 1
4308 
4309 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK 0x00000080
4310 
4311 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK 0xffffff7f
4312 
4313 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET 0x0
4314 
4315 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value) (((value) & 0x00000080) >> 7)
4316 
4317 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value) (((value) << 7) & 0x00000080)
4318 
4330 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB 8
4331 
4332 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB 8
4333 
4334 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH 1
4335 
4336 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK 0x00000100
4337 
4338 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK 0xfffffeff
4339 
4340 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET 0x0
4341 
4342 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value) (((value) & 0x00000100) >> 8)
4343 
4344 #define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value) (((value) << 8) & 0x00000100)
4345 
4363 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB 9
4364 
4365 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB 9
4366 
4367 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH 1
4368 
4369 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK 0x00000200
4370 
4371 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK 0xfffffdff
4372 
4373 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET 0x0
4374 
4375 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value) (((value) & 0x00000200) >> 9)
4376 
4377 #define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value) (((value) << 9) & 0x00000200)
4378 
4389 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB 10
4390 
4391 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB 10
4392 
4393 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH 1
4394 
4395 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK 0x00000400
4396 
4397 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK 0xfffffbff
4398 
4399 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET 0x0
4400 
4401 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value) (((value) & 0x00000400) >> 10)
4402 
4403 #define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value) (((value) << 10) & 0x00000400)
4404 
4415 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB 11
4416 
4417 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB 11
4418 
4419 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH 1
4420 
4421 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK 0x00000800
4422 
4423 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK 0xfffff7ff
4424 
4425 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET 0x0
4426 
4427 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value) (((value) & 0x00000800) >> 11)
4428 
4429 #define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value) (((value) << 11) & 0x00000800)
4430 
4442 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB 12
4443 
4444 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB 12
4445 
4446 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH 1
4447 
4448 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK 0x00001000
4449 
4450 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK 0xffffefff
4451 
4452 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET 0x0
4453 
4454 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value) (((value) & 0x00001000) >> 12)
4455 
4456 #define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value) (((value) << 12) & 0x00001000)
4457 
4469 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB 13
4470 
4471 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB 13
4472 
4473 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH 1
4474 
4475 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK 0x00002000
4476 
4477 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK 0xffffdfff
4478 
4479 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET 0x0
4480 
4481 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value) (((value) & 0x00002000) >> 13)
4482 
4483 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value) (((value) << 13) & 0x00002000)
4484 
4499 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB 14
4500 
4501 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB 14
4502 
4503 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH 1
4504 
4505 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK 0x00004000
4506 
4507 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK 0xffffbfff
4508 
4509 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET 0x0
4510 
4511 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value) (((value) & 0x00004000) >> 14)
4512 
4513 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value) (((value) << 14) & 0x00004000)
4514 
4526 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB 15
4527 
4528 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB 15
4529 
4530 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH 1
4531 
4532 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK 0x00008000
4533 
4534 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK 0xffff7fff
4535 
4536 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET 0x0
4537 
4538 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value) (((value) & 0x00008000) >> 15)
4539 
4540 #define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value) (((value) << 15) & 0x00008000)
4541 
4542 #ifndef __ASSEMBLY__
4543 
4554 {
4555  uint32_t abrt_7b_addr_noack : 1;
4556  uint32_t abrt_10addr1_noack : 1;
4557  uint32_t abrt_10addr2_noack : 1;
4558  uint32_t abrt_txdata_noack : 1;
4559  uint32_t abrt_gcall_noack : 1;
4560  uint32_t abrt_gcall_read : 1;
4561  uint32_t abrt_hs_ackdet : 1;
4562  uint32_t abrt_sbyte_ackdet : 1;
4563  uint32_t abrt_hs_norstrt : 1;
4564  uint32_t abrt_sbyte_norstrt : 1;
4565  uint32_t abrt_10b_rd_norstrt : 1;
4566  uint32_t abrt_master_dis : 1;
4567  uint32_t arb_lost : 1;
4568  uint32_t abrt_slvflush_txfifo : 1;
4569  uint32_t abrt_slv_arblost : 1;
4570  uint32_t abrt_slvrd_intx : 1;
4571  uint32_t : 16;
4572 };
4573 
4576 #endif /* __ASSEMBLY__ */
4577 
4579 #define ALT_I2C_TX_ABRT_SRC_OFST 0x80
4580 
4581 #define ALT_I2C_TX_ABRT_SRC_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
4582 
4617 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_AFTERDBYTE 0x1
4618 
4623 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_E_NORM 0x0
4624 
4626 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_LSB 0
4627 
4628 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_MSB 0
4629 
4630 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_WIDTH 1
4631 
4632 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET_MSK 0x00000001
4633 
4634 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_CLR_MSK 0xfffffffe
4635 
4636 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_RESET 0x0
4637 
4638 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_GET(value) (((value) & 0x00000001) >> 0)
4639 
4640 #define ALT_I2C_SLV_DATA_NACK_ONLY_NACK_SET(value) (((value) << 0) & 0x00000001)
4641 
4642 #ifndef __ASSEMBLY__
4643 
4654 {
4655  uint32_t nack : 1;
4656  uint32_t : 31;
4657 };
4658 
4661 #endif /* __ASSEMBLY__ */
4662 
4664 #define ALT_I2C_SLV_DATA_NACK_ONLY_OFST 0x84
4665 
4666 #define ALT_I2C_SLV_DATA_NACK_ONLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SLV_DATA_NACK_ONLY_OFST))
4667 
4704 #define ALT_I2C_DMA_CR_RDMAE_E_DIS 0x0
4705 
4710 #define ALT_I2C_DMA_CR_RDMAE_E_EN 0x1
4711 
4713 #define ALT_I2C_DMA_CR_RDMAE_LSB 0
4714 
4715 #define ALT_I2C_DMA_CR_RDMAE_MSB 0
4716 
4717 #define ALT_I2C_DMA_CR_RDMAE_WIDTH 1
4718 
4719 #define ALT_I2C_DMA_CR_RDMAE_SET_MSK 0x00000001
4720 
4721 #define ALT_I2C_DMA_CR_RDMAE_CLR_MSK 0xfffffffe
4722 
4723 #define ALT_I2C_DMA_CR_RDMAE_RESET 0x0
4724 
4725 #define ALT_I2C_DMA_CR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
4726 
4727 #define ALT_I2C_DMA_CR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
4728 
4749 #define ALT_I2C_DMA_CR_TDMAE_E_DIS 0x0
4750 
4755 #define ALT_I2C_DMA_CR_TDMAE_E_EN 0x1
4756 
4758 #define ALT_I2C_DMA_CR_TDMAE_LSB 1
4759 
4760 #define ALT_I2C_DMA_CR_TDMAE_MSB 1
4761 
4762 #define ALT_I2C_DMA_CR_TDMAE_WIDTH 1
4763 
4764 #define ALT_I2C_DMA_CR_TDMAE_SET_MSK 0x00000002
4765 
4766 #define ALT_I2C_DMA_CR_TDMAE_CLR_MSK 0xfffffffd
4767 
4768 #define ALT_I2C_DMA_CR_TDMAE_RESET 0x0
4769 
4770 #define ALT_I2C_DMA_CR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
4771 
4772 #define ALT_I2C_DMA_CR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
4773 
4774 #ifndef __ASSEMBLY__
4775 
4786 {
4787  uint32_t rdmae : 1;
4788  uint32_t tdmae : 1;
4789  uint32_t : 30;
4790 };
4791 
4793 typedef volatile struct ALT_I2C_DMA_CR_s ALT_I2C_DMA_CR_t;
4794 #endif /* __ASSEMBLY__ */
4795 
4797 #define ALT_I2C_DMA_CR_OFST 0x88
4798 
4799 #define ALT_I2C_DMA_CR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_CR_OFST))
4800 
4826 #define ALT_I2C_DMA_TDLR_DMATDL_LSB 0
4827 
4828 #define ALT_I2C_DMA_TDLR_DMATDL_MSB 5
4829 
4830 #define ALT_I2C_DMA_TDLR_DMATDL_WIDTH 6
4831 
4832 #define ALT_I2C_DMA_TDLR_DMATDL_SET_MSK 0x0000003f
4833 
4834 #define ALT_I2C_DMA_TDLR_DMATDL_CLR_MSK 0xffffffc0
4835 
4836 #define ALT_I2C_DMA_TDLR_DMATDL_RESET 0x0
4837 
4838 #define ALT_I2C_DMA_TDLR_DMATDL_GET(value) (((value) & 0x0000003f) >> 0)
4839 
4840 #define ALT_I2C_DMA_TDLR_DMATDL_SET(value) (((value) << 0) & 0x0000003f)
4841 
4842 #ifndef __ASSEMBLY__
4843 
4854 {
4855  uint32_t dmatdl : 6;
4856  uint32_t : 26;
4857 };
4858 
4860 typedef volatile struct ALT_I2C_DMA_TDLR_s ALT_I2C_DMA_TDLR_t;
4861 #endif /* __ASSEMBLY__ */
4862 
4864 #define ALT_I2C_DMA_TDLR_OFST 0x8c
4865 
4866 #define ALT_I2C_DMA_TDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_TDLR_OFST))
4867 
4895 #define ALT_I2C_DMA_RDLR_DMARDL_LSB 0
4896 
4897 #define ALT_I2C_DMA_RDLR_DMARDL_MSB 5
4898 
4899 #define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6
4900 
4901 #define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f
4902 
4903 #define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0
4904 
4905 #define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0
4906 
4907 #define ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0)
4908 
4909 #define ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f)
4910 
4911 #ifndef __ASSEMBLY__
4912 
4923 {
4924  uint32_t dmardl : 6;
4925  uint32_t : 26;
4926 };
4927 
4929 typedef volatile struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t;
4930 #endif /* __ASSEMBLY__ */
4931 
4933 #define ALT_I2C_DMA_RDLR_OFST 0x90
4934 
4935 #define ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST))
4936 
4970 #define ALT_I2C_SDA_SETUP_SDA_SETUP_LSB 0
4971 
4972 #define ALT_I2C_SDA_SETUP_SDA_SETUP_MSB 7
4973 
4974 #define ALT_I2C_SDA_SETUP_SDA_SETUP_WIDTH 8
4975 
4976 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET_MSK 0x000000ff
4977 
4978 #define ALT_I2C_SDA_SETUP_SDA_SETUP_CLR_MSK 0xffffff00
4979 
4980 #define ALT_I2C_SDA_SETUP_SDA_SETUP_RESET 0x64
4981 
4982 #define ALT_I2C_SDA_SETUP_SDA_SETUP_GET(value) (((value) & 0x000000ff) >> 0)
4983 
4984 #define ALT_I2C_SDA_SETUP_SDA_SETUP_SET(value) (((value) << 0) & 0x000000ff)
4985 
4986 #ifndef __ASSEMBLY__
4987 
4998 {
4999  uint32_t sda_setup : 8;
5000  uint32_t : 24;
5001 };
5002 
5005 #endif /* __ASSEMBLY__ */
5006 
5008 #define ALT_I2C_SDA_SETUP_OFST 0x94
5009 
5010 #define ALT_I2C_SDA_SETUP_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_SDA_SETUP_OFST))
5011 
5047 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_NACK 0x0
5048 
5053 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_E_ACK 0x1
5054 
5056 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB 0
5057 
5058 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB 0
5059 
5060 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_WIDTH 1
5061 
5062 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET_MSK 0x00000001
5063 
5064 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_CLR_MSK 0xfffffffe
5065 
5066 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET 0x1
5067 
5068 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_GET(value) (((value) & 0x00000001) >> 0)
5069 
5070 #define ALT_I2C_ACK_GENERAL_CALL_ACK_GEN_CALL_SET(value) (((value) << 0) & 0x00000001)
5071 
5072 #ifndef __ASSEMBLY__
5073 
5084 {
5085  uint32_t ack_gen_call : 1;
5086  uint32_t : 31;
5087 };
5088 
5091 #endif /* __ASSEMBLY__ */
5092 
5094 #define ALT_I2C_ACK_GENERAL_CALL_OFST 0x98
5095 
5096 #define ALT_I2C_ACK_GENERAL_CALL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_ACK_GENERAL_CALL_OFST))
5097 
5132 #define ALT_I2C_EN_STAT_IC_EN_LSB 0
5133 
5134 #define ALT_I2C_EN_STAT_IC_EN_MSB 0
5135 
5136 #define ALT_I2C_EN_STAT_IC_EN_WIDTH 1
5137 
5138 #define ALT_I2C_EN_STAT_IC_EN_SET_MSK 0x00000001
5139 
5140 #define ALT_I2C_EN_STAT_IC_EN_CLR_MSK 0xfffffffe
5141 
5142 #define ALT_I2C_EN_STAT_IC_EN_RESET 0x0
5143 
5144 #define ALT_I2C_EN_STAT_IC_EN_GET(value) (((value) & 0x00000001) >> 0)
5145 
5146 #define ALT_I2C_EN_STAT_IC_EN_SET(value) (((value) << 0) & 0x00000001)
5147 
5170 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_LSB 1
5171 
5172 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_MSB 1
5173 
5174 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_WIDTH 1
5175 
5176 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET_MSK 0x00000002
5177 
5178 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_CLR_MSK 0xfffffffd
5179 
5180 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_RESET 0x0
5181 
5182 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_GET(value) (((value) & 0x00000002) >> 1)
5183 
5184 #define ALT_I2C_EN_STAT_SLV_DISD_WHILE_BUSY_SET(value) (((value) << 1) & 0x00000002)
5185 
5205 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_LSB 2
5206 
5207 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_MSB 2
5208 
5209 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_WIDTH 1
5210 
5211 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET_MSK 0x00000004
5212 
5213 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_CLR_MSK 0xfffffffb
5214 
5215 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_RESET 0x0
5216 
5217 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_GET(value) (((value) & 0x00000004) >> 2)
5218 
5219 #define ALT_I2C_EN_STAT_SLV_RX_DATA_LOST_SET(value) (((value) << 2) & 0x00000004)
5220 
5221 #ifndef __ASSEMBLY__
5222 
5233 {
5234  const uint32_t ic_en : 1;
5235  const uint32_t slv_disabled_while_busy : 1;
5236  const uint32_t slv_rx_data_lost : 1;
5237  uint32_t : 29;
5238 };
5239 
5241 typedef volatile struct ALT_I2C_EN_STAT_s ALT_I2C_EN_STAT_t;
5242 #endif /* __ASSEMBLY__ */
5243 
5245 #define ALT_I2C_EN_STAT_OFST 0x9c
5246 
5247 #define ALT_I2C_EN_STAT_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_EN_STAT_OFST))
5248 
5280 #define ALT_I2C_FS_SPKLEN_SPKLEN_LSB 0
5281 
5282 #define ALT_I2C_FS_SPKLEN_SPKLEN_MSB 7
5283 
5284 #define ALT_I2C_FS_SPKLEN_SPKLEN_WIDTH 8
5285 
5286 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET_MSK 0x000000ff
5287 
5288 #define ALT_I2C_FS_SPKLEN_SPKLEN_CLR_MSK 0xffffff00
5289 
5290 #define ALT_I2C_FS_SPKLEN_SPKLEN_RESET 0x2
5291 
5292 #define ALT_I2C_FS_SPKLEN_SPKLEN_GET(value) (((value) & 0x000000ff) >> 0)
5293 
5294 #define ALT_I2C_FS_SPKLEN_SPKLEN_SET(value) (((value) << 0) & 0x000000ff)
5295 
5296 #ifndef __ASSEMBLY__
5297 
5308 {
5309  uint32_t spklen : 8;
5310  uint32_t : 24;
5311 };
5312 
5315 #endif /* __ASSEMBLY__ */
5316 
5318 #define ALT_I2C_FS_SPKLEN_OFST 0xa0
5319 
5320 #define ALT_I2C_FS_SPKLEN_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_FS_SPKLEN_OFST))
5321 
5362 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2
5363 
5365 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB 0
5366 
5367 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB 1
5368 
5369 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH 2
5370 
5371 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK 0x00000003
5372 
5373 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK 0xfffffffc
5374 
5375 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET 0x2
5376 
5377 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value) (((value) & 0x00000003) >> 0)
5378 
5379 #define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value) (((value) << 0) & 0x00000003)
5380 
5400 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2
5401 
5403 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB 2
5404 
5405 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB 3
5406 
5407 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH 2
5408 
5409 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK 0x0000000c
5410 
5411 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK 0xfffffff3
5412 
5413 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET 0x2
5414 
5415 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value) (((value) & 0x0000000c) >> 2)
5416 
5417 #define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value) (((value) << 2) & 0x0000000c)
5418 
5438 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0
5439 
5441 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB 4
5442 
5443 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB 4
5444 
5445 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH 1
5446 
5447 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK 0x00000010
5448 
5449 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK 0xffffffef
5450 
5451 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET 0x0
5452 
5453 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value) (((value) & 0x00000010) >> 4)
5454 
5455 #define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value) (((value) << 4) & 0x00000010)
5456 
5476 #define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1
5477 
5479 #define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB 5
5480 
5481 #define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB 5
5482 
5483 #define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH 1
5484 
5485 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK 0x00000020
5486 
5487 #define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK 0xffffffdf
5488 
5489 #define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET 0x1
5490 
5491 #define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value) (((value) & 0x00000020) >> 5)
5492 
5493 #define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value) (((value) << 5) & 0x00000020)
5494 
5514 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1
5515 
5517 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB 6
5518 
5519 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB 6
5520 
5521 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH 1
5522 
5523 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK 0x00000040
5524 
5525 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK 0xffffffbf
5526 
5527 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET 0x1
5528 
5529 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value) (((value) & 0x00000040) >> 6)
5530 
5531 #define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value) (((value) << 6) & 0x00000040)
5532 
5556 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1
5557 
5559 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB 7
5560 
5561 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB 7
5562 
5563 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH 1
5564 
5565 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK 0x00000080
5566 
5567 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK 0xffffff7f
5568 
5569 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET 0x1
5570 
5571 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value) (((value) & 0x00000080) >> 7)
5572 
5573 #define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value) (((value) << 7) & 0x00000080)
5574 
5594 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40
5595 
5597 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB 8
5598 
5599 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB 15
5600 
5601 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH 8
5602 
5603 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK 0x0000ff00
5604 
5605 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK 0xffff00ff
5606 
5607 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET 0x3f
5608 
5609 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value) (((value) & 0x0000ff00) >> 8)
5610 
5611 #define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value) (((value) << 8) & 0x0000ff00)
5612 
5632 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40
5633 
5635 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB 16
5636 
5637 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB 23
5638 
5639 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH 8
5640 
5641 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK 0x00ff0000
5642 
5643 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK 0xff00ffff
5644 
5645 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET 0x3f
5646 
5647 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value) (((value) & 0x00ff0000) >> 16)
5648 
5649 #define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value) (((value) << 16) & 0x00ff0000)
5650 
5651 #ifndef __ASSEMBLY__
5652 
5663 {
5664  const uint32_t apb_data_width : 2;
5665  const uint32_t max_speed_mode : 2;
5666  const uint32_t hc_count_values : 1;
5667  const uint32_t intr_io : 1;
5668  const uint32_t has_dma : 1;
5669  const uint32_t add_encoded_params : 1;
5670  const uint32_t rx_buffer_depth : 8;
5671  const uint32_t tx_buffer_depth : 8;
5672  uint32_t : 8;
5673 };
5674 
5677 #endif /* __ASSEMBLY__ */
5678 
5680 #define ALT_I2C_COMP_PARAM_1_OFST 0xf4
5681 
5682 #define ALT_I2C_COMP_PARAM_1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
5683 
5715 #define ALT_I2C_COMP_VER_IC_COMP_VER_E_VER_1_20A 0x3132302a
5716 
5718 #define ALT_I2C_COMP_VER_IC_COMP_VER_LSB 0
5719 
5720 #define ALT_I2C_COMP_VER_IC_COMP_VER_MSB 31
5721 
5722 #define ALT_I2C_COMP_VER_IC_COMP_VER_WIDTH 32
5723 
5724 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET_MSK 0xffffffff
5725 
5726 #define ALT_I2C_COMP_VER_IC_COMP_VER_CLR_MSK 0x00000000
5727 
5728 #define ALT_I2C_COMP_VER_IC_COMP_VER_RESET 0x3132302a
5729 
5730 #define ALT_I2C_COMP_VER_IC_COMP_VER_GET(value) (((value) & 0xffffffff) >> 0)
5731 
5732 #define ALT_I2C_COMP_VER_IC_COMP_VER_SET(value) (((value) << 0) & 0xffffffff)
5733 
5734 #ifndef __ASSEMBLY__
5735 
5746 {
5747  const uint32_t ic_comp_version : 32;
5748 };
5749 
5751 typedef volatile struct ALT_I2C_COMP_VER_s ALT_I2C_COMP_VER_t;
5752 #endif /* __ASSEMBLY__ */
5753 
5755 #define ALT_I2C_COMP_VER_OFST 0xf8
5756 
5757 #define ALT_I2C_COMP_VER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_VER_OFST))
5758 
5782 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_LSB 0
5783 
5784 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_MSB 31
5785 
5786 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_WIDTH 32
5787 
5788 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET_MSK 0xffffffff
5789 
5790 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_CLR_MSK 0x00000000
5791 
5792 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_RESET 0x44570140
5793 
5794 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_GET(value) (((value) & 0xffffffff) >> 0)
5795 
5796 #define ALT_I2C_COMP_TYPE_IC_COMP_TYPE_SET(value) (((value) << 0) & 0xffffffff)
5797 
5798 #ifndef __ASSEMBLY__
5799 
5810 {
5811  const uint32_t ic_comp_type : 32;
5812 };
5813 
5816 #endif /* __ASSEMBLY__ */
5817 
5819 #define ALT_I2C_COMP_TYPE_OFST 0xfc
5820 
5821 #define ALT_I2C_COMP_TYPE_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_TYPE_OFST))
5822 
5823 #ifndef __ASSEMBLY__
5824 
5835 {
5839  volatile uint32_t _pad_0xc_0xf;
5845  volatile uint32_t _pad_0x24_0x2b[2];
5876  volatile uint32_t _pad_0xa4_0xf3[20];
5880 };
5881 
5883 typedef volatile struct ALT_I2C_s ALT_I2C_t;
5886 {
5887  volatile uint32_t ic_con;
5888  volatile uint32_t ic_tar;
5889  volatile uint32_t ic_sar;
5890  volatile uint32_t _pad_0xc_0xf;
5891  volatile uint32_t ic_data_cmd;
5892  volatile uint32_t ic_ss_scl_hcnt;
5893  volatile uint32_t ic_ss_scl_lcnt;
5894  volatile uint32_t ic_fs_scl_hcnt;
5895  volatile uint32_t ic_fs_scl_lcnt;
5896  volatile uint32_t _pad_0x24_0x2b[2];
5897  volatile uint32_t ic_intr_stat;
5898  volatile uint32_t ic_intr_mask;
5899  volatile uint32_t ic_raw_intr_stat;
5900  volatile uint32_t ic_rx_tl;
5901  volatile uint32_t ic_tx_tl;
5902  volatile uint32_t ic_clr_intr;
5903  volatile uint32_t ic_clr_rx_under;
5904  volatile uint32_t ic_clr_rx_over;
5905  volatile uint32_t ic_clr_tx_over;
5906  volatile uint32_t ic_clr_rd_req;
5907  volatile uint32_t ic_clr_tx_abrt;
5908  volatile uint32_t ic_clr_rx_done;
5909  volatile uint32_t ic_clr_activity;
5910  volatile uint32_t ic_clr_stop_det;
5911  volatile uint32_t ic_clr_start_det;
5912  volatile uint32_t ic_clr_gen_call;
5913  volatile uint32_t ic_enable;
5914  volatile uint32_t ic_status;
5915  volatile uint32_t ic_txflr;
5916  volatile uint32_t ic_rxflr;
5917  volatile uint32_t ic_sda_hold;
5918  volatile uint32_t ic_tx_abrt_source;
5919  volatile uint32_t ic_slv_data_nack_only;
5920  volatile uint32_t ic_dma_cr;
5921  volatile uint32_t ic_dma_tdlr;
5922  volatile uint32_t ic_dma_rdlr;
5923  volatile uint32_t ic_sda_setup;
5924  volatile uint32_t ic_ack_general_call;
5925  volatile uint32_t ic_enable_status;
5926  volatile uint32_t ic_fs_spklen;
5927  volatile uint32_t _pad_0xa4_0xf3[20];
5928  volatile uint32_t ic_comp_param_1;
5929  volatile uint32_t ic_comp_version;
5930  volatile uint32_t ic_comp_type;
5931 };
5932 
5934 typedef volatile struct ALT_I2C_raw_s ALT_I2C_raw_t;
5935 #endif /* __ASSEMBLY__ */
5936 
5938 #ifdef __cplusplus
5939 }
5940 #endif /* __cplusplus */
5941 #endif /* __ALTERA_ALT_I2C_H__ */
5942