Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : gpio_config_reg2

Description

Name: GPIO Configuration Register 2

Size: 32 bits

Address Offset: 0x70

Read/Write Access: Read

Register Layout

Bits Access Reset Description
[4:0] R 0x17 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
[9:5] R 0x7 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
[14:10] R 0x7 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
[19:15] R 0x7 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
[31:20] ??? 0x0 UNDEFINED

Field : encoded_id_pwidth_a

The value of this register is derived from the

GPIO_PWIDTH_A configuration parameter.

0x0 = 8 bits

0x1 = 16 bits

0x2 = 32 bits

0x3 = Reserved

Field Enumeration Values:

Enum Value Description
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS 0x7 Width (less 1) of 8 bits
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE24BITS 0x1c Width (less 1) of 24 bits

Field Access Macros:

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE24BITS   0x1c
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB   0
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB   4
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH   5
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK   0x0000001f
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK   0xffffffe0
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET   0x17
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET(value)   (((value) & 0x0000001f) >> 0)
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET(value)   (((value) << 0) & 0x0000001f)
 

Field : encoded_id_pwidth_b

The value of this register is derived from the

GPIO_PWIDTH_B configuration parameter.

0x0 = 8 bits

0x1 = 16 bits

0x2 = 32 bits

0x3 = Reserved

Field Enumeration Values:

Enum Value Description
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS 0x7 Width (less 1) of 8 bits
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE24BITS 0x1c Width (less 1) of 24 bits

Field Access Macros:

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE24BITS   0x1c
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB   5
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB   9
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH   5
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK   0x000003e0
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK   0xfffffc1f
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET(value)   (((value) & 0x000003e0) >> 5)
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET(value)   (((value) << 5) & 0x000003e0)
 

Field : encoded_id_pwidth_c

The value of this register is derived from the

GPIO_PWIDTH_C configuration parameter.

0x0 = 8 bits

0x1 = 16 bits

0x2 = 32 bits

0x3 = Reserved

Field Enumeration Values:

Enum Value Description
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS 0x7 Width (less 1) of 8 bits
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE24BITS 0x1c Width (less 1) of 24 bits

Field Access Macros:

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE24BITS   0x1c
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB   10
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB   14
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH   5
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK   0x00007c00
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK   0xffff83ff
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET(value)   (((value) & 0x00007c00) >> 10)
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET(value)   (((value) << 10) & 0x00007c00)
 

Field : encoded_id_pwidth_d

The value of this register is derived from the

GPIO_PWIDTH_D configuration parameter.

0x0 = 8 bits

0x1 = 16 bits

0x2 = 32 bits

0x3 = Reserved

Field Enumeration Values:

Enum Value Description
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS 0x7 Width (less 1) of 8 bits
ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE24BITS 0x1c Width (less 1) of 24 bits

Field Access Macros:

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE24BITS   0x1c
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB   15
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB   19
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH   5
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK   0x000f8000
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK   0xfff07fff
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET   0x7
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET(value)   (((value) & 0x000f8000) >> 15)
 
#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET(value)   (((value) << 15) & 0x000f8000)
 

Data Structures

struct  ALT_GPIO_CFG_REG2_s
 

Macros

#define ALT_GPIO_CFG_REG2_RESET   0x00039cf7
 
#define ALT_GPIO_CFG_REG2_OFST   0x70
 
#define ALT_GPIO_CFG_REG2_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))
 

Typedefs

typedef struct ALT_GPIO_CFG_REG2_s ALT_GPIO_CFG_REG2_t
 

Data Structure Documentation

struct ALT_GPIO_CFG_REG2_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_GPIO_CFG_REG2.

Data Fields
const uint32_t encoded_id_pwidth_a: 5 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A
const uint32_t encoded_id_pwidth_b: 5 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B
const uint32_t encoded_id_pwidth_c: 5 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C
const uint32_t encoded_id_pwidth_d: 5 ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D
uint32_t __pad0__: 12 UNDEFINED

Macro Definitions

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE8BITS   0x7

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A

Width (less 1) of 8 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_E_WIDTHLESSONE24BITS   0x1c

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A

Width (less 1) of 24 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_LSB   0

The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_MSB   4

The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_WIDTH   5

The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET_MSK   0x0000001f

The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_CLR_MSK   0xffffffe0

The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_RESET   0x17

The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_GET (   value)    (((value) & 0x0000001f) >> 0)

Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A field value from a register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A_SET (   value)    (((value) << 0) & 0x0000001f)

Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_A register field value suitable for setting the register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE8BITS   0x7

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B

Width (less 1) of 8 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_E_WIDTHLESSONE24BITS   0x1c

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B

Width (less 1) of 24 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_LSB   5

The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_MSB   9

The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_WIDTH   5

The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET_MSK   0x000003e0

The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_CLR_MSK   0xfffffc1f

The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_RESET   0x7

The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_GET (   value)    (((value) & 0x000003e0) >> 5)

Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B field value from a register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B_SET (   value)    (((value) << 5) & 0x000003e0)

Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_B register field value suitable for setting the register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE8BITS   0x7

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C

Width (less 1) of 8 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_E_WIDTHLESSONE24BITS   0x1c

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C

Width (less 1) of 24 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_LSB   10

The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_MSB   14

The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_WIDTH   5

The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET_MSK   0x00007c00

The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_CLR_MSK   0xffff83ff

The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_RESET   0x7

The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_GET (   value)    (((value) & 0x00007c00) >> 10)

Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C field value from a register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C_SET (   value)    (((value) << 10) & 0x00007c00)

Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_C register field value suitable for setting the register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE8BITS   0x7

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D

Width (less 1) of 8 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_E_WIDTHLESSONE24BITS   0x1c

Enumerated value for register field ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D

Width (less 1) of 24 bits

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_LSB   15

The Least Significant Bit (LSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_MSB   19

The Most Significant Bit (MSB) position of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_WIDTH   5

The width in bits of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET_MSK   0x000f8000

The mask used to set the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_CLR_MSK   0xfff07fff

The mask used to clear the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_RESET   0x7

The reset value of the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_GET (   value)    (((value) & 0x000f8000) >> 15)

Extracts the ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D field value from a register.

#define ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D_SET (   value)    (((value) << 15) & 0x000f8000)

Produces a ALT_GPIO_CFG_REG2_ENC_ID_PWIDTH_D register field value suitable for setting the register.

#define ALT_GPIO_CFG_REG2_RESET   0x00039cf7

The reset value of the ALT_GPIO_CFG_REG2 register.

#define ALT_GPIO_CFG_REG2_OFST   0x70

The byte offset of the ALT_GPIO_CFG_REG2 register from the beginning of the component.

#define ALT_GPIO_CFG_REG2_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_GPIO_CFG_REG2_OFST))

The address of the ALT_GPIO_CFG_REG2 register.

Typedef Documentation

The typedef declaration for register ALT_GPIO_CFG_REG2.