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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Internal DMAC Interrupt Enable Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_SDMMC_IDINTEN_TI |
[1] | RW | 0x0 | ALT_SDMMC_IDINTEN_RI |
[2] | RW | 0x0 | ALT_SDMMC_IDINTEN_FBE |
[3] | ??? | 0x0 | UNDEFINED |
[4] | RW | 0x0 | ALT_SDMMC_IDINTEN_DU |
[5] | RW | 0x0 | ALT_SDMMC_IDINTEN_CES |
[7:6] | ??? | 0x0 | UNDEFINED |
[8] | RW | 0x0 | ALT_SDMMC_IDINTEN_NI |
[9] | RW | 0x0 | ALT_SDMMC_IDINTEN_AI |
[31:10] | ??? | 0x0 | UNDEFINED |
Field : ti | ||||||||||
Transmit Interrupt Enable. When set with Normal Interrupt Summary Enable, Transmit Interrupt is enabled. When reset, Transmit Interrupt is disabled. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_TI_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_LSB 0 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_MSB 0 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SDMMC_IDINTEN_TI_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : ri | ||||||||||
Receive Interrupt Enable. When set with Normal Interrupt Summary Enable, Receive Interrupt is enabled. When reset, Receive Interrupt is disabled. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_RI_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_LSB 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_MSB 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SDMMC_IDINTEN_RI_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : fbe | ||||||||||
Fatal Bus Error Enable. When set with Abnormal Interrupt Summary Enable, the Fatal Bus Error Interrupt is enabled. When reset, Fatal Bus Error Enable Interrupt is disabled. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_LSB 2 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_MSB 2 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SDMMC_IDINTEN_FBE_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : du | ||||||||||
Descriptor Unavailable Interrupt. When set along with Abnormal Interrupt Summary Enable, the DU interrupt is enabled. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_DU_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_LSB 4 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_MSB 4 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SDMMC_IDINTEN_DU_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : ces | ||||||||||
Card Error summary Interrupt Enable. When set, it enables the Card Interrupt summary. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_CES_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_LSB 5 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_MSB 5 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_SDMMC_IDINTEN_CES_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : ni | ||||||||||
Normal Interrupt Summary Enable. When set, a normal interrupt is enabled. When reset, a normal interrupt is disabled. This bit enables the following bits: ■ IDINTEN[0] - Transmit Interrupt ■ IDINTEN[1] - Receive Interrupt Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_NI_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_LSB 8 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_MSB 8 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_GET(value) (((value) & 0x00000100) >> 8) | |||||||||
#define | ALT_SDMMC_IDINTEN_NI_SET(value) (((value) << 8) & 0x00000100) | |||||||||
Field : ai | ||||||||||
Abnormal Interrupt Summary Enable. When set, an abnormal interrupt is enabled. This bit enables the following bits: ■ IDINTEN[2] - Fatal Bus Error Interrupt ■ IDINTEN[4] - DU Interrupt Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_IDINTEN_AI_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_E_END 0x1 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_LSB 9 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_MSB 9 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_WIDTH 1 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_RESET 0x0 | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_GET(value) (((value) & 0x00000200) >> 9) | |||||||||
#define | ALT_SDMMC_IDINTEN_AI_SET(value) (((value) << 9) & 0x00000200) | |||||||||
Data Structures | |
struct | ALT_SDMMC_IDINTEN_s |
Macros | |
#define | ALT_SDMMC_IDINTEN_RESET 0x00000000 |
#define | ALT_SDMMC_IDINTEN_OFST 0x90 |
Typedefs | |
typedef struct ALT_SDMMC_IDINTEN_s | ALT_SDMMC_IDINTEN_t |
struct ALT_SDMMC_IDINTEN_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_IDINTEN.
Data Fields | ||
---|---|---|
uint32_t | ti: 1 | ALT_SDMMC_IDINTEN_TI |
uint32_t | ri: 1 | ALT_SDMMC_IDINTEN_RI |
uint32_t | fbe: 1 | ALT_SDMMC_IDINTEN_FBE |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | du: 1 | ALT_SDMMC_IDINTEN_DU |
uint32_t | ces: 1 | ALT_SDMMC_IDINTEN_CES |
uint32_t | __pad1__: 2 | UNDEFINED |
uint32_t | ni: 1 | ALT_SDMMC_IDINTEN_NI |
uint32_t | ai: 1 | ALT_SDMMC_IDINTEN_AI |
uint32_t | __pad2__: 22 | UNDEFINED |
#define ALT_SDMMC_IDINTEN_TI_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_TI
Transmit Interrupt is disabled
#define ALT_SDMMC_IDINTEN_TI_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_TI
Transmit Interrupt is enabled
#define ALT_SDMMC_IDINTEN_TI_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_TI register field.
#define ALT_SDMMC_IDINTEN_TI_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_TI register field.
#define ALT_SDMMC_IDINTEN_TI_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_TI register field.
#define ALT_SDMMC_IDINTEN_TI_SET_MSK 0x00000001 |
The mask used to set the ALT_SDMMC_IDINTEN_TI register field value.
#define ALT_SDMMC_IDINTEN_TI_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDMMC_IDINTEN_TI register field value.
#define ALT_SDMMC_IDINTEN_TI_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_TI register field.
#define ALT_SDMMC_IDINTEN_TI_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDMMC_IDINTEN_TI field value from a register.
#define ALT_SDMMC_IDINTEN_TI_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDMMC_IDINTEN_TI register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_RI_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_RI
Receive Interrupt is disabled
#define ALT_SDMMC_IDINTEN_RI_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_RI
Receive Interrupt is enabled
#define ALT_SDMMC_IDINTEN_RI_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_RI register field.
#define ALT_SDMMC_IDINTEN_RI_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_RI register field.
#define ALT_SDMMC_IDINTEN_RI_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_RI register field.
#define ALT_SDMMC_IDINTEN_RI_SET_MSK 0x00000002 |
The mask used to set the ALT_SDMMC_IDINTEN_RI register field value.
#define ALT_SDMMC_IDINTEN_RI_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SDMMC_IDINTEN_RI register field value.
#define ALT_SDMMC_IDINTEN_RI_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_RI register field.
#define ALT_SDMMC_IDINTEN_RI_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SDMMC_IDINTEN_RI field value from a register.
#define ALT_SDMMC_IDINTEN_RI_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SDMMC_IDINTEN_RI register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_FBE_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
Fatal Bus Error Interrupt is disabled
#define ALT_SDMMC_IDINTEN_FBE_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_FBE
Fatal Bus Error Interrupt is enabled
#define ALT_SDMMC_IDINTEN_FBE_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_FBE register field.
#define ALT_SDMMC_IDINTEN_FBE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_FBE register field.
#define ALT_SDMMC_IDINTEN_FBE_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_FBE register field.
#define ALT_SDMMC_IDINTEN_FBE_SET_MSK 0x00000004 |
The mask used to set the ALT_SDMMC_IDINTEN_FBE register field value.
#define ALT_SDMMC_IDINTEN_FBE_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SDMMC_IDINTEN_FBE register field value.
#define ALT_SDMMC_IDINTEN_FBE_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_FBE register field.
#define ALT_SDMMC_IDINTEN_FBE_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SDMMC_IDINTEN_FBE field value from a register.
#define ALT_SDMMC_IDINTEN_FBE_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SDMMC_IDINTEN_FBE register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_DU_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_DU
Descriptor Unavailable Interrupt is disabled
#define ALT_SDMMC_IDINTEN_DU_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_DU
Descriptor Unavailable Interrupt is enabled
#define ALT_SDMMC_IDINTEN_DU_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_DU register field.
#define ALT_SDMMC_IDINTEN_DU_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_DU register field.
#define ALT_SDMMC_IDINTEN_DU_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_DU register field.
#define ALT_SDMMC_IDINTEN_DU_SET_MSK 0x00000010 |
The mask used to set the ALT_SDMMC_IDINTEN_DU register field value.
#define ALT_SDMMC_IDINTEN_DU_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SDMMC_IDINTEN_DU register field value.
#define ALT_SDMMC_IDINTEN_DU_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_DU register field.
#define ALT_SDMMC_IDINTEN_DU_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SDMMC_IDINTEN_DU field value from a register.
#define ALT_SDMMC_IDINTEN_DU_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SDMMC_IDINTEN_DU register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_CES_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_CES
Card Error Summary Interrupt is disabled
#define ALT_SDMMC_IDINTEN_CES_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_CES
Card Error Summary Interrupt is enabled
#define ALT_SDMMC_IDINTEN_CES_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_CES register field.
#define ALT_SDMMC_IDINTEN_CES_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_CES register field.
#define ALT_SDMMC_IDINTEN_CES_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_CES register field.
#define ALT_SDMMC_IDINTEN_CES_SET_MSK 0x00000020 |
The mask used to set the ALT_SDMMC_IDINTEN_CES register field value.
#define ALT_SDMMC_IDINTEN_CES_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_SDMMC_IDINTEN_CES register field value.
#define ALT_SDMMC_IDINTEN_CES_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_CES register field.
#define ALT_SDMMC_IDINTEN_CES_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_SDMMC_IDINTEN_CES field value from a register.
#define ALT_SDMMC_IDINTEN_CES_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_SDMMC_IDINTEN_CES register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_NI_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_NI
Normal Interrupt Summary is disabled
#define ALT_SDMMC_IDINTEN_NI_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_NI
Normal Interrupt Summary is enabled
#define ALT_SDMMC_IDINTEN_NI_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_NI register field.
#define ALT_SDMMC_IDINTEN_NI_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_NI register field.
#define ALT_SDMMC_IDINTEN_NI_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_NI register field.
#define ALT_SDMMC_IDINTEN_NI_SET_MSK 0x00000100 |
The mask used to set the ALT_SDMMC_IDINTEN_NI register field value.
#define ALT_SDMMC_IDINTEN_NI_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SDMMC_IDINTEN_NI register field value.
#define ALT_SDMMC_IDINTEN_NI_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_NI register field.
#define ALT_SDMMC_IDINTEN_NI_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SDMMC_IDINTEN_NI field value from a register.
#define ALT_SDMMC_IDINTEN_NI_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SDMMC_IDINTEN_NI register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_AI_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_IDINTEN_AI
Abnormal Interrupt Summary is disabled
#define ALT_SDMMC_IDINTEN_AI_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_IDINTEN_AI
Abnormal Interrupt Summary is enabled
#define ALT_SDMMC_IDINTEN_AI_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_IDINTEN_AI register field.
#define ALT_SDMMC_IDINTEN_AI_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_IDINTEN_AI register field.
#define ALT_SDMMC_IDINTEN_AI_WIDTH 1 |
The width in bits of the ALT_SDMMC_IDINTEN_AI register field.
#define ALT_SDMMC_IDINTEN_AI_SET_MSK 0x00000200 |
The mask used to set the ALT_SDMMC_IDINTEN_AI register field value.
#define ALT_SDMMC_IDINTEN_AI_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_SDMMC_IDINTEN_AI register field value.
#define ALT_SDMMC_IDINTEN_AI_RESET 0x0 |
The reset value of the ALT_SDMMC_IDINTEN_AI register field.
#define ALT_SDMMC_IDINTEN_AI_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_SDMMC_IDINTEN_AI field value from a register.
#define ALT_SDMMC_IDINTEN_AI_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_SDMMC_IDINTEN_AI register field value suitable for setting the register.
#define ALT_SDMMC_IDINTEN_RESET 0x00000000 |
The reset value of the ALT_SDMMC_IDINTEN register.
#define ALT_SDMMC_IDINTEN_OFST 0x90 |
The byte offset of the ALT_SDMMC_IDINTEN register from the beginning of the component.
typedef struct ALT_SDMMC_IDINTEN_s ALT_SDMMC_IDINTEN_t |
The typedef declaration for register ALT_SDMMC_IDINTEN.