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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Used to drive freeze signals to HPS HIO bank (DDR SDRAM).
All fields are only reset by a cold reset (ignore warm reset).
The following equation determines when the weak pullup resistor is enabled:
enabled = ~wkpullup | (CFF & cfg & tristate)
where CFF is the value of weak pullup as set by IO configuration
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | IO Configuration |
[1] | RW | 0x0 | IO Bus Hold |
[2] | RW | 0x0 | IO Tri-State |
[3] | RW | 0x0 | IO Weak Pullup |
[4] | RW | 0x0 | IO Slew-rate |
[5] | RW | 0x1 | DLL Reset |
[6] | RW | 0x1 | OCT Reset |
[7] | RW | 0x1 | IO and DQS Reset |
[8] | RW | 0x0 | OCT Calibration and Configuration Enable |
[31:9] | ??? | 0x0 | UNDEFINED |
Field : IO Configuration - cfg | ||||||||||||||||
Controls IO configuration Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET(value) (((value) & 0x00000001) >> 0) | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET(value) (((value) << 0) & 0x00000001) | |||||||||||||||
Field : IO Bus Hold - bushold | ||||||||||
Controls bus hold circuit Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : IO Tri-State - tristate | ||||||||||
Controls IO tri-state Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : IO Weak Pullup - wkpullup | |||||||||||||
Controls weak pullup resistor Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET(value) (((value) & 0x00000008) >> 3) | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET(value) (((value) << 3) & 0x00000008) | ||||||||||||
Field : IO Slew-rate - slew | ||||||||||
Controls IO slew-rate Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : DLL Reset - dllrst | |||||||||||||
Controls DLL (Delay-Locked Loop) reset. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET(value) (((value) & 0x00000020) >> 5) | ||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET(value) (((value) << 5) & 0x00000020) | ||||||||||||
Field : OCT Reset - octrst | ||||||||||
Controls OCT reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET(value) (((value) & 0x00000040) >> 6) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET(value) (((value) << 6) & 0x00000040) | |||||||||
Field : IO and DQS Reset - regrst | ||||||||||
Controls IO and DQS reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET(value) (((value) & 0x00000080) >> 7) | |||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET(value) (((value) << 7) & 0x00000080) | |||||||||
Field : OCT Calibration and Configuration Enable - oct_cfgen_calstart | ||||||||||||||||
Controls OCT calibration and OCT IO configuration enable. Field Enumeration Values:
Field Access Macros: | ||||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET(value) (((value) & 0x00000100) >> 8) | |||||||||||||||
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET(value) (((value) << 8) & 0x00000100) | |||||||||||||||
Data Structures | |
struct | ALT_SYSMGR_FRZCTL_HIOCTL_s |
Macros | |
#define | ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 |
Typedefs | |
typedef struct ALT_SYSMGR_FRZCTL_HIOCTL_s | ALT_SYSMGR_FRZCTL_HIOCTL_t |
struct ALT_SYSMGR_FRZCTL_HIOCTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_FRZCTL_HIOCTL.
Data Fields | ||
---|---|---|
uint32_t | cfg: 1 | IO Configuration |
uint32_t | bushold: 1 | IO Bus Hold |
uint32_t | tristate: 1 | IO Tri-State |
uint32_t | wkpullup: 1 | IO Weak Pullup |
uint32_t | slew: 1 | IO Slew-rate |
uint32_t | dllrst: 1 | DLL Reset |
uint32_t | octrst: 1 | OCT Reset |
uint32_t | regrst: 1 | IO and DQS Reset |
uint32_t | oct_cfgen_calstart: 1 | OCT Calibration and Configuration Enable |
uint32_t | __pad0__: 23 | UNDEFINED |
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
Disable IO configuration (forced to a safe value).
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_CFG
Enables IO configuration as previously configured by software using the Scan Manager.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_CFG field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_CFG_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_CFG register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
Disable bus hold circuit.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD
Bus hold circuit controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_BUSHOLD register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_EN 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
IO tri-state enabled.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE
IO tri-state controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET_MSK 0x00000004 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_TRISTATE register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_EN 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
Weak pullup resistor enabled.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP
Weak pullup resistor enable controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET_MSK 0x00000008 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_WKPULLUP register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_SLOW 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
Slew-rate forced to slow.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_E_CFG 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_SLEW
Slew-rate controlled by IO configuration.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_SLEW field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_SLEW_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_SLEW register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
No reset or clock gating.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST
Resets registers in the DLL and gates off DLL clock.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET_MSK 0x00000020 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_RESET 0x1 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_DLLRST register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
No reset.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST
Resets registers in the OCT.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET_MSK 0x00000040 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_RESET 0x1 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCTRST register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
No reset.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_REGRST
Resets all IO registers and DQS registers.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET_MSK 0x00000080 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_RESET 0x1 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_REGRST field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_REGRST_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_REGRST register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
Disables IO configuration (forced to a safe value) in OCT calibration block.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART
Starts OCT calibration state machine and enables IO configuration in OCT calibration block.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET_MSK 0x00000100 |
The mask used to set the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_RESET 0x0 |
The reset value of the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART field value from a register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SYSMGR_FRZCTL_HIOCTL_OCT_CFGEN_CALSTART register field value suitable for setting the register.
#define ALT_SYSMGR_FRZCTL_HIOCTL_OFST 0x10 |
The byte offset of the ALT_SYSMGR_FRZCTL_HIOCTL register from the beginning of the component.
typedef struct ALT_SYSMGR_FRZCTL_HIOCTL_s ALT_SYSMGR_FRZCTL_HIOCTL_t |
The typedef declaration for register ALT_SYSMGR_FRZCTL_HIOCTL.