Altera HWLIB  16.0
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alt_nand_private.h
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32 
33 /*
34  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/alt_nand_private.h#1 $
35  */
36 
41 #ifndef __ALT_NAND_PRIVATE_H__
42 #define __ALT_NAND_PRIVATE_H__
43 
44 
45 /*
46  * *****************************************
47  * Struct for NAND Manager IO block
48  * which consists of cfg, param, status, ecc and dma register blocks
49  * located at address: ALT_NAND_CFG_ADDR
50  * *****************************************
51  */
52 typedef struct {
53  ALT_NAND_CFG_raw_t* cfg; // nand configuration block
54  ALT_NAND_PARAM_raw_t* param; // nand parameter block
55  ALT_NAND_STAT_raw_t* stat; // nand status block
56  ALT_NAND_ECC_raw_t* ecc; // nand ecc block
57  ALT_NAND_DMA_raw_t* dma; // nand dma block
58  volatile uint32_t * const ctrl_addr; // indirect access address control
59  volatile uint32_t * const data_addr; // fifo access address control
60 } ALT_NAND_MGR_t;
61 
62 //
63 // flash memory characterization
64 //
65 typedef struct
66 {
67  uint32_t manufacturer_id;
68  uint32_t device_id;
69  uint32_t device_param_0;
70  uint32_t device_param_1;
71  uint32_t device_param_2;
72  uint32_t page_size;
73  uint32_t spare_size;
74  uint32_t revision;
75  uint32_t onfi_device_features;
76  uint32_t onfi_optional_commands;
77  uint32_t onfi_timing_mode;
78  uint32_t onfi_pgm_cache_timing_mode;
79  uint32_t onfi_compliant;
80  uint32_t onfi_device_no_of_luns;
81  uint32_t onfi_device_no_of_blocks_per_lun;
82  uint32_t features;
83 
84  uint32_t number_of_planes;
85  uint32_t pages_per_block;
86  uint32_t device_width;
87  uint32_t device_main_area_size;
88  uint32_t device_spare_area_size;
89  uint32_t block_size;
90  uint32_t spare_area_skip_bytes;
91  uint32_t first_block_of_next_plane;
92  uint32_t page_size_32;
93  uint32_t page_shift;
94  uint32_t block_shift;
95  uint32_t dma_burst_length;
96  uint32_t ecc_correct;
97 } FLASH_CHARACTERIZATION_t;
98 
99 
100 typedef uint32_t (*nand_interrupt_handler_t)(uint32_t interrup_status_register, uint32_t interrup_status_mask );
101 
102 
103 /*
104  * Some default values.
105  */
106 #define ALT_HHP_NAND_SECTOR_SIZE (512)
107 #define ALT_HHP_NAND_PAGE_SIZE (2048)
108 #define ALT_HHP_NAND_PAGE_SHIFT (11)
109 #define ALT_HHP_NAND_SPARE_SIZE (128) /* Spare bytes per page. */
110 #define ALT_HHP_NAND_PAGES_PER_BLOCK (64) /* 128 pages per block (512KB) */
111 #define ALT_HHP_NAND_BLOCK_SIZE (ALT_HHP_NAND_PAGE_SIZE *ALT_HHP_NAND_PAGES_PER_BLOCK)
112 #define ALT_HHP_NAND_ECC_CORRECT (8) /* 8 bit ECC. */
113 #define ALT_HHP_NAND_SPARE_SKIP (2) /* Skip the first 2 bytes of the spare space. */
114 #define ALT_HHP_NAND_BLOCK_SHIFT (6) /* from page boundary */
115 #define ALT_HHP_NAND_MANUFACTURER_ID (0x1)
116 #define ALT_HHP_NAND_DEVICE_ID (0xd3)
117 #define ALT_HHP_NAND_REVISION (5)
118 
119 #define ALT_HHP_NAND_NUMBER_OF_PLANES (2)
120 #define ALT_HHP_NAND_DEVICE_WIDTH (0)
121 #define ALT_HHP_NAND_FIRST_BLOCK_OF_NEXT_PLANE (2048)
122 
123 #define ALT_HHP_NAND_NUM_OF_LUNS (2)
124 #define ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS (4096)
125 #define ALT_HHP_NAND_NUM_OF_BLOCK_TOTAL (ALT_HHP_NAND_NUM_OF_LUNS * ALT_HHP_NAND_NUM_OF_BLOCK_PER_LUNS)
126 
127 //
128 // Constants from 8.1. Address Mapping
129 //
130 // Table 8.2
131 #define ALT_HHP_NAND_MODE_00 (0x00000000)
132 #define ALT_HHP_NAND_MODE_01 (0x04000000)
133 #define ALT_HHP_NAND_MODE_10 (0x08000000)
134 #define ALT_HHP_NAND_MODE_11 (0x0C000000)
135 
136 #define ALT_HHP_NAND_ADDR_MAP_CMD_MAP_LSB_INDEX (26)
137 #define ALT_HHP_NAND_ADDR_MAP_BANK_SEL_LSB_INDEX (24)
138 #define ALT_HHP_NAND_ADDR_MAP_MEM_ADDR_LSB_INDEX (0)
139 
140 #define ALT_HHP_NAND_10_OP_DEFAULT_AREA (0x0042)
141 #define ALT_HHP_NAND_10_OP_ERASE_BLOCK (0x0001)
142 #define ALT_HHP_NAND_10_OP_LOAD_PAGE (0x0060)
143 #define ALT_HHP_NAND_10_OP_DEST_ADDR (0x0061)
144 #define ALT_HHP_NAND_10_OP_WRITE_PAGE (0x0062)
145 
146 #define ALT_HHP_NAND_10_OP_READ_PIPE (0x2000)
147 #define ALT_HHP_NAND_10_OP_WRITE_PIPE (0x2100)
148 
149 #define ALT_HHP_UINT32_MASK ((uint32_t) -1)
150 
151 
152 #define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_ENABLE (1)
153 #define ALT_NAND_BOOTSTRAP_INHIBIT_INIT_DISABLE (0)
154 #define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_ENABLE (1)
155 #define ALT_NAND_BOOTSTRAP_INHIBIT_B0P0_LOAD_DISABLE (0)
156 #define ALT_NAND_BOOTSTRAP_512B_DEVICE_ENABLE (1)
157 #define ALT_NAND_BOOTSTRAP_512B_DEVICE_DISABLE (0)
158 #define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_EABLE (1)
159 #define ALT_NAND_BOOTSTRAP_TWO_ROW_ADDR_CYCLES_DISABLE (0)
160 
161 #define ALT_NAND_FLASH_MEM_BANK_0 (0)
162 #define ALT_NAND_FLASH_MEM_BANK_1 (1)
163 #define ALT_NAND_FLASH_MEM_BANK_2 (2)
164 #define ALT_NAND_FLASH_MEM_BANK_3 (3)
165 
166 uint32_t alt_nand_poll_for_interrupt_status_register(uint32_t , uint32_t );
167 uint32_t ffs32(uint32_t);
168 uint32_t alt_nand_compose_map10_cmd_addr(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr);
169 int32_t alt_nand_full_page_read_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer);
170 void alt_nand_write_indirect(const uint32_t address, const uint32_t value);
171 uint32_t alt_nand_read_indirect(const uint32_t address);
172 int32_t alt_nand_full_page_write_with_map10(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer);
173 void alt_nand_full_page_read_with_map10_post_read_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t *buffer);
174 void alt_nand_full_page_write_with_map10_post_write_with_map01(const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t *buffer);
175 
176 void alt_nand_set_sysmgr_bootstrap_value( uint32_t bootstrp_inhibit_init,
177  uint32_t bootstrp_inhibit_b0p0_load,
178  uint32_t bootstrp_512b_device,
179  uint32_t bootstrp_two_row_addr_cycles);
180 void alt_nand_reset_bank(uint32_t bank);
181 uint32_t alt_nand_bank_get(void);
182 
183 void alt_nand_dma_write_cmd_structure( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, const uint32_t page_count, uint64_t mem_addr, int32_t is_read_op, const uint32_t burst_len );
184 
185 void alt_nand_dma_set_enabled( int32_t is_enabled );
186 int32_t alt_nand_dma_page_read( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr );
187 int32_t alt_nand_dma_page_write( const uint32_t bank, const uint32_t block_addr, const uint32_t page_addr, uint32_t mem_addr );
188 ALT_STATUS_CODE alt_nand_flash_init_manual(void *);
189 void alt_nand_erase_block_callback(ALT_STATUS_CODE, void *);
190 void alt_nand_dma_page_callback(ALT_STATUS_CODE, void *);
191 void nand_print_device(void);
192 uint32_t nand_read_register(uint32_t offset);
193 void alt_nand_rb_pin_mode_set(uint32_t);
194 void alt_nand_rb_pin_mode_clear(uint32_t);
195 
196 #endif /* __ALT_NAND_PRIVATE_H__ */