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alt_noc_fw_l4_sys_scr.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
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#define __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__
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#ifndef __ASSEMBLY__
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#ifdef __cplusplus
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#include <cstdint>
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extern
"C"
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{
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#else
/* __cplusplus */
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#include <stdint.h>
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#endif
/* __cplusplus */
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_MSB 31
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_WIDTH 32
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET_MSK 0xffffffff
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_CLR_MSK 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s
99
{
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uint32_t
Reserved
: 32;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_s
ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_OFST 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_MSB 31
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_WIDTH 32
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET_MSK 0xffffffff
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_CLR_MSK 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s
159
{
160
uint32_t
Reserved
: 32;
161
};
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typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_s
ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_OFST 0x4
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_LSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_MSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
282
{
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uint32_t
mpu_m0
: 1;
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uint32_t : 15;
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uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_s
ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_OFST 0x8
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_LSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_MSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
410
{
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uint32_t
mpu_m0
: 1;
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uint32_t : 15;
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uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
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};
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typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t
;
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#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_OFST 0xc
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_LSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_MSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
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struct
ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
538
{
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uint32_t
mpu_m0
: 1;
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uint32_t : 15;
541
uint32_t
fpga2soc
: 1;
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uint32_t : 7;
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uint32_t
ahb_ap
: 1;
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uint32_t : 7;
545
};
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typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t
;
549
#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_OFST 0x10
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_LSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_MSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_LSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_MSB 24
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET_MSK 0x01000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
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#ifndef __ASSEMBLY__
655
665
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
666
{
667
uint32_t
mpu_m0
: 1;
668
uint32_t : 15;
669
uint32_t
fpga2soc
: 1;
670
uint32_t : 7;
671
uint32_t
ahb_ap
: 1;
672
uint32_t : 7;
673
};
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676
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t
;
677
#endif
/* __ASSEMBLY__ */
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_RESET 0x00000000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_OFST 0x14
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_LSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_MSB 0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET_MSK 0x00000001
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_RESET 0x0
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_LSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_MSB 16
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_WIDTH 1
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET_MSK 0x00010000
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_CLR_MSK 0xfffeffff
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#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_RESET 0x0
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751
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
752
753
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
754
766
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_LSB 24
767
768
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_MSB 24
769
770
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_WIDTH 1
771
772
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET_MSK 0x01000000
773
774
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
775
776
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_RESET 0x0
777
778
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
779
780
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
781
782
#ifndef __ASSEMBLY__
783
793
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
794
{
795
uint32_t
mpu_m0
: 1;
796
uint32_t : 15;
797
uint32_t
fpga2soc
: 1;
798
uint32_t : 7;
799
uint32_t
ahb_ap
: 1;
800
uint32_t : 7;
801
};
802
804
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t
;
805
#endif
/* __ASSEMBLY__ */
806
808
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_RESET 0x00000000
809
810
#define ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_OFST 0x18
811
840
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_LSB 0
841
842
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_MSB 0
843
844
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_WIDTH 1
845
846
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET_MSK 0x00000001
847
848
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_CLR_MSK 0xfffffffe
849
850
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_RESET 0x0
851
852
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
853
854
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
855
867
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_LSB 16
868
869
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_MSB 16
870
871
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_WIDTH 1
872
873
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET_MSK 0x00010000
874
875
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_CLR_MSK 0xfffeffff
876
877
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_RESET 0x0
878
879
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
880
881
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
882
894
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_LSB 24
895
896
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_MSB 24
897
898
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_WIDTH 1
899
900
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET_MSK 0x01000000
901
902
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_CLR_MSK 0xfeffffff
903
904
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_RESET 0x0
905
906
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
907
908
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
909
910
#ifndef __ASSEMBLY__
911
921
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
922
{
923
uint32_t
mpu_m0
: 1;
924
uint32_t : 15;
925
uint32_t
fpga2soc
: 1;
926
uint32_t : 7;
927
uint32_t
ahb_ap
: 1;
928
uint32_t : 7;
929
};
930
932
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t
;
933
#endif
/* __ASSEMBLY__ */
934
936
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_RESET 0x00000000
937
938
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_OFST 0x1c
939
968
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_LSB 0
969
970
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_MSB 0
971
972
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_WIDTH 1
973
974
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET_MSK 0x00000001
975
976
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_CLR_MSK 0xfffffffe
977
978
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_RESET 0x0
979
980
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
981
982
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
983
995
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_LSB 16
996
997
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_MSB 16
998
999
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_WIDTH 1
1000
1001
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET_MSK 0x00010000
1002
1003
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_CLR_MSK 0xfffeffff
1004
1005
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_RESET 0x0
1006
1007
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1008
1009
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1010
1022
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_LSB 24
1023
1024
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_MSB 24
1025
1026
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_WIDTH 1
1027
1028
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET_MSK 0x01000000
1029
1030
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_CLR_MSK 0xfeffffff
1031
1032
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_RESET 0x0
1033
1034
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1035
1036
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1037
1038
#ifndef __ASSEMBLY__
1039
1049
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
1050
{
1051
uint32_t
mpu_m0
: 1;
1052
uint32_t : 15;
1053
uint32_t
fpga2soc
: 1;
1054
uint32_t : 7;
1055
uint32_t
ahb_ap
: 1;
1056
uint32_t : 7;
1057
};
1058
1060
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t
;
1061
#endif
/* __ASSEMBLY__ */
1062
1064
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_RESET 0x00000000
1065
1066
#define ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_OFST 0x20
1067
1087
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_LSB 0
1088
1089
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_MSB 31
1090
1091
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_WIDTH 32
1092
1093
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET_MSK 0xffffffff
1094
1095
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_CLR_MSK 0x00000000
1096
1097
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_RESET 0x0
1098
1099
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1100
1101
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1102
1103
#ifndef __ASSEMBLY__
1104
1114
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s
1115
{
1116
uint32_t
Reserved
: 32;
1117
};
1118
1120
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t
;
1121
#endif
/* __ASSEMBLY__ */
1122
1124
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_RESET 0x00000000
1125
1126
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_OFST 0x24
1127
1147
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_LSB 0
1148
1149
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_MSB 31
1150
1151
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_WIDTH 32
1152
1153
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET_MSK 0xffffffff
1154
1155
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_CLR_MSK 0x00000000
1156
1157
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_RESET 0x0
1158
1159
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_GET(value) (((value) & 0xffffffff) >> 0)
1160
1161
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RSVD_SET(value) (((value) << 0) & 0xffffffff)
1162
1163
#ifndef __ASSEMBLY__
1164
1174
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s
1175
{
1176
uint32_t
Reserved
: 32;
1177
};
1178
1180
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_s
ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t
;
1181
#endif
/* __ASSEMBLY__ */
1182
1184
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_RESET 0x00000000
1185
1186
#define ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_OFST 0x28
1187
1216
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_LSB 0
1217
1218
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_MSB 0
1219
1220
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_WIDTH 1
1221
1222
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET_MSK 0x00000001
1223
1224
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_CLR_MSK 0xfffffffe
1225
1226
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_RESET 0x0
1227
1228
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1229
1230
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1231
1243
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_LSB 16
1244
1245
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_MSB 16
1246
1247
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_WIDTH 1
1248
1249
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET_MSK 0x00010000
1250
1251
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_CLR_MSK 0xfffeffff
1252
1253
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_RESET 0x0
1254
1255
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1256
1257
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1258
1270
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_LSB 24
1271
1272
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_MSB 24
1273
1274
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_WIDTH 1
1275
1276
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET_MSK 0x01000000
1277
1278
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_CLR_MSK 0xfeffffff
1279
1280
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_RESET 0x0
1281
1282
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1283
1284
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1285
1286
#ifndef __ASSEMBLY__
1287
1297
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
1298
{
1299
uint32_t
mpu_m0
: 1;
1300
uint32_t : 15;
1301
uint32_t
fpga2soc
: 1;
1302
uint32_t : 7;
1303
uint32_t
ahb_ap
: 1;
1304
uint32_t : 7;
1305
};
1306
1308
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_s
ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t
;
1309
#endif
/* __ASSEMBLY__ */
1310
1312
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_RESET 0x00000000
1313
1314
#define ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_OFST 0x2c
1315
1344
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_LSB 0
1345
1346
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_MSB 0
1347
1348
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_WIDTH 1
1349
1350
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET_MSK 0x00000001
1351
1352
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_CLR_MSK 0xfffffffe
1353
1354
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_RESET 0x0
1355
1356
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1357
1358
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1359
1371
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_LSB 16
1372
1373
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_MSB 16
1374
1375
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_WIDTH 1
1376
1377
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET_MSK 0x00010000
1378
1379
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_CLR_MSK 0xfffeffff
1380
1381
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_RESET 0x0
1382
1383
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1384
1385
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1386
1398
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_LSB 24
1399
1400
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_MSB 24
1401
1402
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_WIDTH 1
1403
1404
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET_MSK 0x01000000
1405
1406
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_CLR_MSK 0xfeffffff
1407
1408
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_RESET 0x0
1409
1410
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1411
1412
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1413
1414
#ifndef __ASSEMBLY__
1415
1425
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s
1426
{
1427
uint32_t
mpu_m0
: 1;
1428
uint32_t : 15;
1429
uint32_t
fpga2soc
: 1;
1430
uint32_t : 7;
1431
uint32_t
ahb_ap
: 1;
1432
uint32_t : 7;
1433
};
1434
1436
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_s
ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t
;
1437
#endif
/* __ASSEMBLY__ */
1438
1440
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_RESET 0x00000000
1441
1442
#define ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_OFST 0x30
1443
1472
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_LSB 0
1473
1474
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_MSB 0
1475
1476
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_WIDTH 1
1477
1478
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET_MSK 0x00000001
1479
1480
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_CLR_MSK 0xfffffffe
1481
1482
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_RESET 0x0
1483
1484
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1485
1486
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1487
1499
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_LSB 16
1500
1501
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_MSB 16
1502
1503
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_WIDTH 1
1504
1505
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET_MSK 0x00010000
1506
1507
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_CLR_MSK 0xfffeffff
1508
1509
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_RESET 0x0
1510
1511
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1512
1513
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1514
1526
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_LSB 24
1527
1528
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_MSB 24
1529
1530
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_WIDTH 1
1531
1532
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET_MSK 0x01000000
1533
1534
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_CLR_MSK 0xfeffffff
1535
1536
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_RESET 0x0
1537
1538
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1539
1540
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1541
1542
#ifndef __ASSEMBLY__
1543
1553
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s
1554
{
1555
uint32_t
mpu_m0
: 1;
1556
uint32_t : 15;
1557
uint32_t
fpga2soc
: 1;
1558
uint32_t : 7;
1559
uint32_t
ahb_ap
: 1;
1560
uint32_t : 7;
1561
};
1562
1564
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_s
ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t
;
1565
#endif
/* __ASSEMBLY__ */
1566
1568
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_RESET 0x00000000
1569
1570
#define ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_OFST 0x34
1571
1600
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_LSB 0
1601
1602
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_MSB 0
1603
1604
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_WIDTH 1
1605
1606
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET_MSK 0x00000001
1607
1608
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_CLR_MSK 0xfffffffe
1609
1610
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_RESET 0x0
1611
1612
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1613
1614
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1615
1627
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_LSB 16
1628
1629
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_MSB 16
1630
1631
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_WIDTH 1
1632
1633
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET_MSK 0x00010000
1634
1635
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_CLR_MSK 0xfffeffff
1636
1637
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_RESET 0x0
1638
1639
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1640
1641
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1642
1654
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_LSB 24
1655
1656
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_MSB 24
1657
1658
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_WIDTH 1
1659
1660
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET_MSK 0x01000000
1661
1662
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_CLR_MSK 0xfeffffff
1663
1664
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_RESET 0x0
1665
1666
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1667
1668
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1669
1670
#ifndef __ASSEMBLY__
1671
1681
struct
ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s
1682
{
1683
uint32_t
mpu_m0
: 1;
1684
uint32_t : 15;
1685
uint32_t
fpga2soc
: 1;
1686
uint32_t : 7;
1687
uint32_t
ahb_ap
: 1;
1688
uint32_t : 7;
1689
};
1690
1692
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_s
ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t
;
1693
#endif
/* __ASSEMBLY__ */
1694
1696
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_RESET 0x00000000
1697
1698
#define ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_OFST 0x38
1699
1728
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_LSB 0
1729
1730
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_MSB 0
1731
1732
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_WIDTH 1
1733
1734
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET_MSK 0x00000001
1735
1736
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_CLR_MSK 0xfffffffe
1737
1738
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_RESET 0x0
1739
1740
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1741
1742
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1743
1755
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_LSB 16
1756
1757
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_MSB 16
1758
1759
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_WIDTH 1
1760
1761
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET_MSK 0x00010000
1762
1763
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_CLR_MSK 0xfffeffff
1764
1765
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_RESET 0x0
1766
1767
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1768
1769
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1770
1782
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_LSB 24
1783
1784
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_MSB 24
1785
1786
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_WIDTH 1
1787
1788
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET_MSK 0x01000000
1789
1790
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_CLR_MSK 0xfeffffff
1791
1792
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_RESET 0x0
1793
1794
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1795
1796
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1797
1798
#ifndef __ASSEMBLY__
1799
1809
struct
ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s
1810
{
1811
uint32_t
mpu_m0
: 1;
1812
uint32_t : 15;
1813
uint32_t
fpga2soc
: 1;
1814
uint32_t : 7;
1815
uint32_t
ahb_ap
: 1;
1816
uint32_t : 7;
1817
};
1818
1820
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_s
ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t
;
1821
#endif
/* __ASSEMBLY__ */
1822
1824
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_RESET 0x00000000
1825
1826
#define ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_OFST 0x3c
1827
1856
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_LSB 0
1857
1858
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_MSB 0
1859
1860
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_WIDTH 1
1861
1862
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET_MSK 0x00000001
1863
1864
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_CLR_MSK 0xfffffffe
1865
1866
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_RESET 0x0
1867
1868
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1869
1870
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1871
1883
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_LSB 16
1884
1885
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_MSB 16
1886
1887
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_WIDTH 1
1888
1889
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET_MSK 0x00010000
1890
1891
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_CLR_MSK 0xfffeffff
1892
1893
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_RESET 0x0
1894
1895
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
1896
1897
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
1898
1910
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_LSB 24
1911
1912
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_MSB 24
1913
1914
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_WIDTH 1
1915
1916
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET_MSK 0x01000000
1917
1918
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_CLR_MSK 0xfeffffff
1919
1920
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_RESET 0x0
1921
1922
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
1923
1924
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
1925
1926
#ifndef __ASSEMBLY__
1927
1937
struct
ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
1938
{
1939
uint32_t
mpu_m0
: 1;
1940
uint32_t : 15;
1941
uint32_t
fpga2soc
: 1;
1942
uint32_t : 7;
1943
uint32_t
ahb_ap
: 1;
1944
uint32_t : 7;
1945
};
1946
1948
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_s
ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t
;
1949
#endif
/* __ASSEMBLY__ */
1950
1952
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_RESET 0x00000000
1953
1954
#define ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_OFST 0x40
1955
1984
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_LSB 0
1985
1986
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_MSB 0
1987
1988
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_WIDTH 1
1989
1990
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET_MSK 0x00000001
1991
1992
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_CLR_MSK 0xfffffffe
1993
1994
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_RESET 0x0
1995
1996
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
1997
1998
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
1999
2011
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_LSB 16
2012
2013
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_MSB 16
2014
2015
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_WIDTH 1
2016
2017
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET_MSK 0x00010000
2018
2019
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_CLR_MSK 0xfffeffff
2020
2021
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_RESET 0x0
2022
2023
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2024
2025
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2026
2038
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_LSB 24
2039
2040
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_MSB 24
2041
2042
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_WIDTH 1
2043
2044
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET_MSK 0x01000000
2045
2046
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_CLR_MSK 0xfeffffff
2047
2048
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_RESET 0x0
2049
2050
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2051
2052
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2053
2054
#ifndef __ASSEMBLY__
2055
2065
struct
ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
2066
{
2067
uint32_t
mpu_m0
: 1;
2068
uint32_t : 15;
2069
uint32_t
fpga2soc
: 1;
2070
uint32_t : 7;
2071
uint32_t
ahb_ap
: 1;
2072
uint32_t : 7;
2073
};
2074
2076
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_s
ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t
;
2077
#endif
/* __ASSEMBLY__ */
2078
2080
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_RESET 0x00000000
2081
2082
#define ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_OFST 0x44
2083
2112
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_LSB 0
2113
2114
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_MSB 0
2115
2116
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_WIDTH 1
2117
2118
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET_MSK 0x00000001
2119
2120
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_CLR_MSK 0xfffffffe
2121
2122
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_RESET 0x0
2123
2124
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2125
2126
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2127
2139
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_LSB 16
2140
2141
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_MSB 16
2142
2143
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_WIDTH 1
2144
2145
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET_MSK 0x00010000
2146
2147
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_CLR_MSK 0xfffeffff
2148
2149
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_RESET 0x0
2150
2151
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_GET(value) (((value) & 0x00010000) >> 16)
2152
2153
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_F2H_SET(value) (((value) << 16) & 0x00010000)
2154
2166
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_LSB 24
2167
2168
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_MSB 24
2169
2170
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_WIDTH 1
2171
2172
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET_MSK 0x01000000
2173
2174
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_CLR_MSK 0xfeffffff
2175
2176
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_RESET 0x0
2177
2178
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2179
2180
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2181
2182
#ifndef __ASSEMBLY__
2183
2193
struct
ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
2194
{
2195
uint32_t
mpu_m0
: 1;
2196
uint32_t : 15;
2197
uint32_t
fpga2soc
: 1;
2198
uint32_t : 7;
2199
uint32_t
ahb_ap
: 1;
2200
uint32_t : 7;
2201
};
2202
2204
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_s
ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t
;
2205
#endif
/* __ASSEMBLY__ */
2206
2208
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_RESET 0x00000000
2209
2210
#define ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_OFST 0x48
2211
2242
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_LSB 0
2243
2244
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_MSB 0
2245
2246
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_WIDTH 1
2247
2248
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET_MSK 0x00000001
2249
2250
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2251
2252
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_RESET 0x0
2253
2254
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2255
2256
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2257
2269
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_LSB 8
2270
2271
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_MSB 8
2272
2273
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_WIDTH 1
2274
2275
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET_MSK 0x00000100
2276
2277
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_CLR_MSK 0xfffffeff
2278
2279
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_RESET 0x0
2280
2281
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2282
2283
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2284
2296
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_LSB 16
2297
2298
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_MSB 16
2299
2300
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_WIDTH 1
2301
2302
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET_MSK 0x00010000
2303
2304
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_CLR_MSK 0xfffeffff
2305
2306
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_RESET 0x0
2307
2308
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2309
2310
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2311
2323
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_LSB 24
2324
2325
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_MSB 24
2326
2327
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_WIDTH 1
2328
2329
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET_MSK 0x01000000
2330
2331
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2332
2333
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_RESET 0x0
2334
2335
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2336
2337
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2338
2339
#ifndef __ASSEMBLY__
2340
2350
struct
ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s
2351
{
2352
uint32_t
mpu_m0
: 1;
2353
uint32_t : 7;
2354
uint32_t
dma
: 1;
2355
uint32_t : 7;
2356
uint32_t
fpga2soc
: 1;
2357
uint32_t : 7;
2358
uint32_t
ahb_ap
: 1;
2359
uint32_t : 7;
2360
};
2361
2363
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_s
ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t
;
2364
#endif
/* __ASSEMBLY__ */
2365
2367
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_RESET 0x00000000
2368
2369
#define ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_OFST 0x4c
2370
2399
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_LSB 0
2400
2401
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_MSB 0
2402
2403
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_WIDTH 1
2404
2405
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET_MSK 0x00000001
2406
2407
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_CLR_MSK 0xfffffffe
2408
2409
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_RESET 0x0
2410
2411
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2412
2413
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2414
2426
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_LSB 8
2427
2428
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_MSB 8
2429
2430
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_WIDTH 1
2431
2432
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET_MSK 0x00000100
2433
2434
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_CLR_MSK 0xfffffeff
2435
2436
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_RESET 0x0
2437
2438
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2439
2440
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2441
2453
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_LSB 24
2454
2455
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_MSB 24
2456
2457
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_WIDTH 1
2458
2459
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET_MSK 0x01000000
2460
2461
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_CLR_MSK 0xfeffffff
2462
2463
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_RESET 0x0
2464
2465
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2466
2467
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2468
2469
#ifndef __ASSEMBLY__
2470
2480
struct
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s
2481
{
2482
uint32_t
mpu_m0
: 1;
2483
uint32_t : 7;
2484
uint32_t
dma
: 1;
2485
uint32_t : 15;
2486
uint32_t
ahb_ap
: 1;
2487
uint32_t : 7;
2488
};
2489
2491
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_s
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t
;
2492
#endif
/* __ASSEMBLY__ */
2493
2495
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_RESET 0x00000000
2496
2497
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_OFST 0x50
2498
2529
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_LSB 0
2530
2531
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_MSB 0
2532
2533
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_WIDTH 1
2534
2535
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET_MSK 0x00000001
2536
2537
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_CLR_MSK 0xfffffffe
2538
2539
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_RESET 0x0
2540
2541
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2542
2543
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2544
2556
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_LSB 8
2557
2558
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_MSB 8
2559
2560
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_WIDTH 1
2561
2562
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET_MSK 0x00000100
2563
2564
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_CLR_MSK 0xfffffeff
2565
2566
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_RESET 0x0
2567
2568
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
2569
2570
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
2571
2583
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_LSB 16
2584
2585
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_MSB 16
2586
2587
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_WIDTH 1
2588
2589
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET_MSK 0x00010000
2590
2591
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_CLR_MSK 0xfffeffff
2592
2593
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_RESET 0x0
2594
2595
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
2596
2597
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
2598
2610
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_LSB 24
2611
2612
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_MSB 24
2613
2614
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_WIDTH 1
2615
2616
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET_MSK 0x01000000
2617
2618
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_CLR_MSK 0xfeffffff
2619
2620
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_RESET 0x0
2621
2622
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2623
2624
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2625
2626
#ifndef __ASSEMBLY__
2627
2637
struct
ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s
2638
{
2639
uint32_t
mpu_m0
: 1;
2640
uint32_t : 7;
2641
uint32_t
dma
: 1;
2642
uint32_t : 7;
2643
uint32_t
fpga2soc
: 1;
2644
uint32_t : 7;
2645
uint32_t
ahb_ap
: 1;
2646
uint32_t : 7;
2647
};
2648
2650
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_s
ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t
;
2651
#endif
/* __ASSEMBLY__ */
2652
2654
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_RESET 0x00000000
2655
2656
#define ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_OFST 0x54
2657
2688
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_LSB 0
2689
2690
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_MSB 0
2691
2692
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_WIDTH 1
2693
2694
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET_MSK 0x00000001
2695
2696
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2697
2698
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_RESET 0x0
2699
2700
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2701
2702
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2703
2715
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_LSB 8
2716
2717
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_MSB 8
2718
2719
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_WIDTH 1
2720
2721
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET_MSK 0x00000100
2722
2723
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_CLR_MSK 0xfffffeff
2724
2725
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_RESET 0x0
2726
2727
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2728
2729
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2730
2742
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_LSB 16
2743
2744
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_MSB 16
2745
2746
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_WIDTH 1
2747
2748
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET_MSK 0x00010000
2749
2750
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_CLR_MSK 0xfffeffff
2751
2752
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_RESET 0x0
2753
2754
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2755
2756
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2757
2769
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_LSB 24
2770
2771
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_MSB 24
2772
2773
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_WIDTH 1
2774
2775
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET_MSK 0x01000000
2776
2777
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2778
2779
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_RESET 0x0
2780
2781
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2782
2783
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2784
2785
#ifndef __ASSEMBLY__
2786
2796
struct
ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s
2797
{
2798
uint32_t
mpu_m0
: 1;
2799
uint32_t : 7;
2800
uint32_t
dma
: 1;
2801
uint32_t : 7;
2802
uint32_t
fpga2soc
: 1;
2803
uint32_t : 7;
2804
uint32_t
ahb_ap
: 1;
2805
uint32_t : 7;
2806
};
2807
2809
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_s
ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t
;
2810
#endif
/* __ASSEMBLY__ */
2811
2813
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_RESET 0x00000000
2814
2815
#define ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_OFST 0x58
2816
2847
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_LSB 0
2848
2849
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_MSB 0
2850
2851
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_WIDTH 1
2852
2853
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET_MSK 0x00000001
2854
2855
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_CLR_MSK 0xfffffffe
2856
2857
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_RESET 0x0
2858
2859
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
2860
2861
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
2862
2874
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_LSB 8
2875
2876
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_MSB 8
2877
2878
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_WIDTH 1
2879
2880
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET_MSK 0x00000100
2881
2882
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_CLR_MSK 0xfffffeff
2883
2884
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_RESET 0x0
2885
2886
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_GET(value) (((value) & 0x00000100) >> 8)
2887
2888
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_DMA_SET(value) (((value) << 8) & 0x00000100)
2889
2901
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_LSB 16
2902
2903
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_MSB 16
2904
2905
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_WIDTH 1
2906
2907
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET_MSK 0x00010000
2908
2909
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_CLR_MSK 0xfffeffff
2910
2911
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_RESET 0x0
2912
2913
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_GET(value) (((value) & 0x00010000) >> 16)
2914
2915
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_F2H_SET(value) (((value) << 16) & 0x00010000)
2916
2928
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_LSB 24
2929
2930
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_MSB 24
2931
2932
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_WIDTH 1
2933
2934
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET_MSK 0x01000000
2935
2936
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_CLR_MSK 0xfeffffff
2937
2938
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_RESET 0x0
2939
2940
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
2941
2942
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
2943
2944
#ifndef __ASSEMBLY__
2945
2955
struct
ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s
2956
{
2957
uint32_t
mpu_m0
: 1;
2958
uint32_t : 7;
2959
uint32_t
dma
: 1;
2960
uint32_t : 7;
2961
uint32_t
fpga2soc
: 1;
2962
uint32_t : 7;
2963
uint32_t
ahb_ap
: 1;
2964
uint32_t : 7;
2965
};
2966
2968
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_s
ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t
;
2969
#endif
/* __ASSEMBLY__ */
2970
2972
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_RESET 0x00000000
2973
2974
#define ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_OFST 0x5c
2975
3006
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_LSB 0
3007
3008
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_MSB 0
3009
3010
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_WIDTH 1
3011
3012
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET_MSK 0x00000001
3013
3014
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_CLR_MSK 0xfffffffe
3015
3016
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_RESET 0x0
3017
3018
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3019
3020
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3021
3033
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_LSB 8
3034
3035
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_MSB 8
3036
3037
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_WIDTH 1
3038
3039
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET_MSK 0x00000100
3040
3041
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_CLR_MSK 0xfffffeff
3042
3043
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_RESET 0x0
3044
3045
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3046
3047
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3048
3060
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_LSB 16
3061
3062
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_MSB 16
3063
3064
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_WIDTH 1
3065
3066
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET_MSK 0x00010000
3067
3068
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_CLR_MSK 0xfffeffff
3069
3070
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_RESET 0x0
3071
3072
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3073
3074
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3075
3087
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_LSB 24
3088
3089
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_MSB 24
3090
3091
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_WIDTH 1
3092
3093
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET_MSK 0x01000000
3094
3095
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_CLR_MSK 0xfeffffff
3096
3097
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_RESET 0x0
3098
3099
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3100
3101
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3102
3103
#ifndef __ASSEMBLY__
3104
3114
struct
ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s
3115
{
3116
uint32_t
mpu_m0
: 1;
3117
uint32_t : 7;
3118
uint32_t
dma
: 1;
3119
uint32_t : 7;
3120
uint32_t
fpga2soc
: 1;
3121
uint32_t : 7;
3122
uint32_t
ahb_ap
: 1;
3123
uint32_t : 7;
3124
};
3125
3127
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_s
ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t
;
3128
#endif
/* __ASSEMBLY__ */
3129
3131
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_RESET 0x00000000
3132
3133
#define ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_OFST 0x60
3134
3165
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_LSB 0
3166
3167
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_MSB 0
3168
3169
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_WIDTH 1
3170
3171
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET_MSK 0x00000001
3172
3173
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_CLR_MSK 0xfffffffe
3174
3175
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_RESET 0x0
3176
3177
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3178
3179
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3180
3192
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_LSB 8
3193
3194
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_MSB 8
3195
3196
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_WIDTH 1
3197
3198
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET_MSK 0x00000100
3199
3200
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_CLR_MSK 0xfffffeff
3201
3202
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_RESET 0x0
3203
3204
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_GET(value) (((value) & 0x00000100) >> 8)
3205
3206
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_DMA_SET(value) (((value) << 8) & 0x00000100)
3207
3219
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_LSB 16
3220
3221
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_MSB 16
3222
3223
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_WIDTH 1
3224
3225
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET_MSK 0x00010000
3226
3227
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_CLR_MSK 0xfffeffff
3228
3229
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_RESET 0x0
3230
3231
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_GET(value) (((value) & 0x00010000) >> 16)
3232
3233
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_F2H_SET(value) (((value) << 16) & 0x00010000)
3234
3246
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_LSB 24
3247
3248
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_MSB 24
3249
3250
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_WIDTH 1
3251
3252
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET_MSK 0x01000000
3253
3254
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_CLR_MSK 0xfeffffff
3255
3256
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_RESET 0x0
3257
3258
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3259
3260
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3261
3262
#ifndef __ASSEMBLY__
3263
3273
struct
ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s
3274
{
3275
uint32_t
mpu_m0
: 1;
3276
uint32_t : 7;
3277
uint32_t
dma
: 1;
3278
uint32_t : 7;
3279
uint32_t
fpga2soc
: 1;
3280
uint32_t : 7;
3281
uint32_t
ahb_ap
: 1;
3282
uint32_t : 7;
3283
};
3284
3286
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_s
ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t
;
3287
#endif
/* __ASSEMBLY__ */
3288
3290
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_RESET 0x00000000
3291
3292
#define ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_OFST 0x64
3293
3324
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_LSB 0
3325
3326
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_MSB 0
3327
3328
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_WIDTH 1
3329
3330
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET_MSK 0x00000001
3331
3332
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_CLR_MSK 0xfffffffe
3333
3334
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_RESET 0x0
3335
3336
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3337
3338
#define ALT_NOC_FW_L4_SYS_SCR_WD0_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3339
3351
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_LSB 8
3352
3353
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_MSB 8
3354
3355
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_WIDTH 1
3356
3357
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET_MSK 0x00000100
3358
3359
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_CLR_MSK 0xfffffeff
3360
3361
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_RESET 0x0
3362
3363
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_GET(value) (((value) & 0x00000100) >> 8)
3364
3365
#define ALT_NOC_FW_L4_SYS_SCR_WD0_DMA_SET(value) (((value) << 8) & 0x00000100)
3366
3378
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_LSB 16
3379
3380
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_MSB 16
3381
3382
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_WIDTH 1
3383
3384
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET_MSK 0x00010000
3385
3386
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_CLR_MSK 0xfffeffff
3387
3388
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_RESET 0x0
3389
3390
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_GET(value) (((value) & 0x00010000) >> 16)
3391
3392
#define ALT_NOC_FW_L4_SYS_SCR_WD0_F2H_SET(value) (((value) << 16) & 0x00010000)
3393
3405
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_LSB 24
3406
3407
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_MSB 24
3408
3409
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_WIDTH 1
3410
3411
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET_MSK 0x01000000
3412
3413
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_CLR_MSK 0xfeffffff
3414
3415
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_RESET 0x0
3416
3417
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3418
3419
#define ALT_NOC_FW_L4_SYS_SCR_WD0_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3420
3421
#ifndef __ASSEMBLY__
3422
3432
struct
ALT_NOC_FW_L4_SYS_SCR_WD0_s
3433
{
3434
uint32_t
mpu_m0
: 1;
3435
uint32_t : 7;
3436
uint32_t
dma
: 1;
3437
uint32_t : 7;
3438
uint32_t
fpga2soc
: 1;
3439
uint32_t : 7;
3440
uint32_t
ahb_ap
: 1;
3441
uint32_t : 7;
3442
};
3443
3445
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_WD0_s
ALT_NOC_FW_L4_SYS_SCR_WD0_t
;
3446
#endif
/* __ASSEMBLY__ */
3447
3449
#define ALT_NOC_FW_L4_SYS_SCR_WD0_RESET 0x00000000
3450
3451
#define ALT_NOC_FW_L4_SYS_SCR_WD0_OFST 0x68
3452
3483
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_LSB 0
3484
3485
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_MSB 0
3486
3487
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_WIDTH 1
3488
3489
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET_MSK 0x00000001
3490
3491
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_CLR_MSK 0xfffffffe
3492
3493
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_RESET 0x0
3494
3495
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3496
3497
#define ALT_NOC_FW_L4_SYS_SCR_WD1_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3498
3510
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_LSB 8
3511
3512
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_MSB 8
3513
3514
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_WIDTH 1
3515
3516
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET_MSK 0x00000100
3517
3518
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_CLR_MSK 0xfffffeff
3519
3520
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_RESET 0x0
3521
3522
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_GET(value) (((value) & 0x00000100) >> 8)
3523
3524
#define ALT_NOC_FW_L4_SYS_SCR_WD1_DMA_SET(value) (((value) << 8) & 0x00000100)
3525
3537
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_LSB 16
3538
3539
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_MSB 16
3540
3541
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_WIDTH 1
3542
3543
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET_MSK 0x00010000
3544
3545
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_CLR_MSK 0xfffeffff
3546
3547
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_RESET 0x0
3548
3549
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_GET(value) (((value) & 0x00010000) >> 16)
3550
3551
#define ALT_NOC_FW_L4_SYS_SCR_WD1_F2H_SET(value) (((value) << 16) & 0x00010000)
3552
3564
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_LSB 24
3565
3566
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_MSB 24
3567
3568
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_WIDTH 1
3569
3570
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET_MSK 0x01000000
3571
3572
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_CLR_MSK 0xfeffffff
3573
3574
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_RESET 0x0
3575
3576
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3577
3578
#define ALT_NOC_FW_L4_SYS_SCR_WD1_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3579
3580
#ifndef __ASSEMBLY__
3581
3591
struct
ALT_NOC_FW_L4_SYS_SCR_WD1_s
3592
{
3593
uint32_t
mpu_m0
: 1;
3594
uint32_t : 7;
3595
uint32_t
dma
: 1;
3596
uint32_t : 7;
3597
uint32_t
fpga2soc
: 1;
3598
uint32_t : 7;
3599
uint32_t
ahb_ap
: 1;
3600
uint32_t : 7;
3601
};
3602
3604
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_WD1_s
ALT_NOC_FW_L4_SYS_SCR_WD1_t
;
3605
#endif
/* __ASSEMBLY__ */
3606
3608
#define ALT_NOC_FW_L4_SYS_SCR_WD1_RESET 0x00000000
3609
3610
#define ALT_NOC_FW_L4_SYS_SCR_WD1_OFST 0x6c
3611
3643
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_LSB 0
3644
3645
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_MSB 0
3646
3647
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_WIDTH 1
3648
3649
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET_MSK 0x00000001
3650
3651
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_CLR_MSK 0xfffffffe
3652
3653
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_RESET 0x0
3654
3655
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3656
3657
#define ALT_NOC_FW_L4_SYS_SCR_DAP_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3658
3670
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_LSB 8
3671
3672
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_MSB 8
3673
3674
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_WIDTH 1
3675
3676
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET_MSK 0x00000100
3677
3678
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_CLR_MSK 0xfffffeff
3679
3680
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_RESET 0x0
3681
3682
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_GET(value) (((value) & 0x00000100) >> 8)
3683
3684
#define ALT_NOC_FW_L4_SYS_SCR_DAP_DMA_SET(value) (((value) << 8) & 0x00000100)
3685
3697
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_LSB 16
3698
3699
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_MSB 16
3700
3701
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_WIDTH 1
3702
3703
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET_MSK 0x00010000
3704
3705
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_CLR_MSK 0xfffeffff
3706
3707
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_RESET 0x0
3708
3709
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_GET(value) (((value) & 0x00010000) >> 16)
3710
3711
#define ALT_NOC_FW_L4_SYS_SCR_DAP_F2H_SET(value) (((value) << 16) & 0x00010000)
3712
3724
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_LSB 24
3725
3726
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_MSB 24
3727
3728
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_WIDTH 1
3729
3730
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET_MSK 0x01000000
3731
3732
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_CLR_MSK 0xfeffffff
3733
3734
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_RESET 0x0
3735
3736
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3737
3738
#define ALT_NOC_FW_L4_SYS_SCR_DAP_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3739
3751
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_LSB 25
3752
3753
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_MSB 25
3754
3755
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_WIDTH 1
3756
3757
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET_MSK 0x02000000
3758
3759
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_CLR_MSK 0xfdffffff
3760
3761
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_RESET 0x0
3762
3763
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_GET(value) (((value) & 0x02000000) >> 25)
3764
3765
#define ALT_NOC_FW_L4_SYS_SCR_DAP_ETR_SET(value) (((value) << 25) & 0x02000000)
3766
3767
#ifndef __ASSEMBLY__
3768
3778
struct
ALT_NOC_FW_L4_SYS_SCR_DAP_s
3779
{
3780
uint32_t
mpu_m0
: 1;
3781
uint32_t : 7;
3782
uint32_t
dma
: 1;
3783
uint32_t : 7;
3784
uint32_t
fpga2soc
: 1;
3785
uint32_t : 7;
3786
uint32_t
ahb_ap
: 1;
3787
uint32_t
etr
: 1;
3788
uint32_t : 6;
3789
};
3790
3792
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_DAP_s
ALT_NOC_FW_L4_SYS_SCR_DAP_t
;
3793
#endif
/* __ASSEMBLY__ */
3794
3796
#define ALT_NOC_FW_L4_SYS_SCR_DAP_RESET 0x00000000
3797
3798
#define ALT_NOC_FW_L4_SYS_SCR_DAP_OFST 0x70
3799
3828
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_LSB 0
3829
3830
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_MSB 0
3831
3832
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_WIDTH 1
3833
3834
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET_MSK 0x00000001
3835
3836
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3837
3838
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_RESET 0x0
3839
3840
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3841
3842
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3843
3855
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_LSB 8
3856
3857
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_MSB 8
3858
3859
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_WIDTH 1
3860
3861
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET_MSK 0x00000100
3862
3863
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_CLR_MSK 0xfffffeff
3864
3865
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_RESET 0x0
3866
3867
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3868
3869
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
3870
3882
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_LSB 24
3883
3884
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_MSB 24
3885
3886
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_WIDTH 1
3887
3888
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET_MSK 0x01000000
3889
3890
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
3891
3892
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_RESET 0x0
3893
3894
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
3895
3896
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
3897
3898
#ifndef __ASSEMBLY__
3899
3909
struct
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s
3910
{
3911
uint32_t
mpu_m0
: 1;
3912
uint32_t : 7;
3913
uint32_t
dma
: 1;
3914
uint32_t : 15;
3915
uint32_t
ahb_ap
: 1;
3916
uint32_t : 7;
3917
};
3918
3920
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_s
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t
;
3921
#endif
/* __ASSEMBLY__ */
3922
3924
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_RESET 0x00000000
3925
3926
#define ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_OFST 0x74
3927
3956
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_LSB 0
3957
3958
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_MSB 0
3959
3960
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_WIDTH 1
3961
3962
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET_MSK 0x00000001
3963
3964
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_CLR_MSK 0xfffffffe
3965
3966
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_RESET 0x0
3967
3968
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
3969
3970
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
3971
3983
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_LSB 8
3984
3985
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_MSB 8
3986
3987
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_WIDTH 1
3988
3989
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET_MSK 0x00000100
3990
3991
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_CLR_MSK 0xfffffeff
3992
3993
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_RESET 0x0
3994
3995
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_GET(value) (((value) & 0x00000100) >> 8)
3996
3997
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_DMA_SET(value) (((value) << 8) & 0x00000100)
3998
4010
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_LSB 24
4011
4012
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_MSB 24
4013
4014
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_WIDTH 1
4015
4016
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET_MSK 0x01000000
4017
4018
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_CLR_MSK 0xfeffffff
4019
4020
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_RESET 0x0
4021
4022
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4023
4024
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4025
4026
#ifndef __ASSEMBLY__
4027
4037
struct
ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s
4038
{
4039
uint32_t
mpu_m0
: 1;
4040
uint32_t : 7;
4041
uint32_t
dma
: 1;
4042
uint32_t : 15;
4043
uint32_t
ahb_ap
: 1;
4044
uint32_t : 7;
4045
};
4046
4048
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_s
ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t
;
4049
#endif
/* __ASSEMBLY__ */
4050
4052
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_RESET 0x00000000
4053
4054
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST 0x78
4055
4056
#define ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_OFST))
4057
4088
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_LSB 0
4089
4090
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_MSB 0
4091
4092
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_WIDTH 1
4093
4094
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET_MSK 0x00000001
4095
4096
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_CLR_MSK 0xfffffffe
4097
4098
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_RESET 0x0
4099
4100
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4101
4102
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4103
4115
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_LSB 8
4116
4117
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_MSB 8
4118
4119
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_WIDTH 1
4120
4121
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET_MSK 0x00000100
4122
4123
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_CLR_MSK 0xfffffeff
4124
4125
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_RESET 0x0
4126
4127
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4128
4129
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4130
4142
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_LSB 16
4143
4144
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_MSB 16
4145
4146
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_WIDTH 1
4147
4148
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET_MSK 0x00010000
4149
4150
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_CLR_MSK 0xfffeffff
4151
4152
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_RESET 0x0
4153
4154
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4155
4156
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4157
4169
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_LSB 24
4170
4171
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_MSB 24
4172
4173
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_WIDTH 1
4174
4175
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET_MSK 0x01000000
4176
4177
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_CLR_MSK 0xfeffffff
4178
4179
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_RESET 0x0
4180
4181
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4182
4183
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4184
4185
#ifndef __ASSEMBLY__
4186
4196
struct
ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s
4197
{
4198
uint32_t
mpu_m0
: 1;
4199
uint32_t : 7;
4200
uint32_t
dma
: 1;
4201
uint32_t : 7;
4202
uint32_t
fpga2soc
: 1;
4203
uint32_t : 7;
4204
uint32_t
ahb_ap
: 1;
4205
uint32_t : 7;
4206
};
4207
4209
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_HMC_REG_s
ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t
;
4210
#endif
/* __ASSEMBLY__ */
4211
4213
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_RESET 0x00000000
4214
4215
#define ALT_NOC_FW_L4_SYS_SCR_HMC_REG_OFST 0x7c
4216
4247
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_LSB 0
4248
4249
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_MSB 0
4250
4251
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_WIDTH 1
4252
4253
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET_MSK 0x00000001
4254
4255
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_CLR_MSK 0xfffffffe
4256
4257
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_RESET 0x0
4258
4259
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4260
4261
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4262
4274
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_LSB 8
4275
4276
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_MSB 8
4277
4278
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_WIDTH 1
4279
4280
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET_MSK 0x00000100
4281
4282
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_CLR_MSK 0xfffffeff
4283
4284
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_RESET 0x0
4285
4286
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_GET(value) (((value) & 0x00000100) >> 8)
4287
4288
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_DMA_SET(value) (((value) << 8) & 0x00000100)
4289
4301
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_LSB 16
4302
4303
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_MSB 16
4304
4305
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_WIDTH 1
4306
4307
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET_MSK 0x00010000
4308
4309
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_CLR_MSK 0xfffeffff
4310
4311
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_RESET 0x0
4312
4313
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4314
4315
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4316
4328
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_LSB 24
4329
4330
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_MSB 24
4331
4332
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_WIDTH 1
4333
4334
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET_MSK 0x01000000
4335
4336
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_CLR_MSK 0xfeffffff
4337
4338
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_RESET 0x0
4339
4340
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4341
4342
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4343
4344
#ifndef __ASSEMBLY__
4345
4355
struct
ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s
4356
{
4357
uint32_t
mpu_m0
: 1;
4358
uint32_t : 7;
4359
uint32_t
dma
: 1;
4360
uint32_t : 7;
4361
uint32_t
fpga2soc
: 1;
4362
uint32_t : 7;
4363
uint32_t
ahb_ap
: 1;
4364
uint32_t : 7;
4365
};
4366
4368
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_s
ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t
;
4369
#endif
/* __ASSEMBLY__ */
4370
4372
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_RESET 0x00000000
4373
4374
#define ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_OFST 0x80
4375
4404
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_LSB 0
4405
4406
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_MSB 0
4407
4408
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_WIDTH 1
4409
4410
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET_MSK 0x00000001
4411
4412
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_CLR_MSK 0xfffffffe
4413
4414
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_RESET 0x0
4415
4416
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4417
4418
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4419
4431
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_LSB 16
4432
4433
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_MSB 16
4434
4435
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_WIDTH 1
4436
4437
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET_MSK 0x00010000
4438
4439
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_CLR_MSK 0xfffeffff
4440
4441
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_RESET 0x0
4442
4443
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4444
4445
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4446
4458
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_LSB 24
4459
4460
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_MSB 24
4461
4462
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_WIDTH 1
4463
4464
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET_MSK 0x01000000
4465
4466
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_CLR_MSK 0xfeffffff
4467
4468
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_RESET 0x0
4469
4470
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4471
4472
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4473
4474
#ifndef __ASSEMBLY__
4475
4485
struct
ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s
4486
{
4487
uint32_t
mpu_m0
: 1;
4488
uint32_t : 15;
4489
uint32_t
fpga2soc
: 1;
4490
uint32_t : 7;
4491
uint32_t
ahb_ap
: 1;
4492
uint32_t : 7;
4493
};
4494
4496
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_s
ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t
;
4497
#endif
/* __ASSEMBLY__ */
4498
4500
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_RESET 0x00000000
4501
4502
#define ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_OFST 0x84
4503
4532
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_LSB 0
4533
4534
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_MSB 0
4535
4536
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_WIDTH 1
4537
4538
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET_MSK 0x00000001
4539
4540
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_CLR_MSK 0xfffffffe
4541
4542
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_RESET 0x0
4543
4544
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4545
4546
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4547
4559
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_LSB 16
4560
4561
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_MSB 16
4562
4563
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_WIDTH 1
4564
4565
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET_MSK 0x00010000
4566
4567
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_CLR_MSK 0xfffeffff
4568
4569
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_RESET 0x0
4570
4571
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_GET(value) (((value) & 0x00010000) >> 16)
4572
4573
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_F2H_SET(value) (((value) << 16) & 0x00010000)
4574
4586
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_LSB 24
4587
4588
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_MSB 24
4589
4590
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_WIDTH 1
4591
4592
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET_MSK 0x01000000
4593
4594
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_CLR_MSK 0xfeffffff
4595
4596
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_RESET 0x0
4597
4598
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4599
4600
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4601
4602
#ifndef __ASSEMBLY__
4603
4613
struct
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s
4614
{
4615
uint32_t
mpu_m0
: 1;
4616
uint32_t : 15;
4617
uint32_t
fpga2soc
: 1;
4618
uint32_t : 7;
4619
uint32_t
ahb_ap
: 1;
4620
uint32_t : 7;
4621
};
4622
4624
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_s
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t
;
4625
#endif
/* __ASSEMBLY__ */
4626
4628
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_RESET 0x00000000
4629
4630
#define ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_OFST 0x88
4631
4660
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_LSB 0
4661
4662
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_MSB 0
4663
4664
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_WIDTH 1
4665
4666
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET_MSK 0x00000001
4667
4668
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_CLR_MSK 0xfffffffe
4669
4670
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_RESET 0x0
4671
4672
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4673
4674
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4675
4687
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_LSB 16
4688
4689
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_MSB 16
4690
4691
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_WIDTH 1
4692
4693
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET_MSK 0x00010000
4694
4695
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_CLR_MSK 0xfffeffff
4696
4697
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_RESET 0x0
4698
4699
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4700
4701
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4702
4714
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_LSB 24
4715
4716
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_MSB 24
4717
4718
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_WIDTH 1
4719
4720
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET_MSK 0x01000000
4721
4722
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_CLR_MSK 0xfeffffff
4723
4724
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_RESET 0x0
4725
4726
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4727
4728
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4729
4730
#ifndef __ASSEMBLY__
4731
4741
struct
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s
4742
{
4743
uint32_t
mpu_m0
: 1;
4744
uint32_t : 15;
4745
uint32_t
fpga2soc
: 1;
4746
uint32_t : 7;
4747
uint32_t
ahb_ap
: 1;
4748
uint32_t : 7;
4749
};
4750
4752
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_s
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t
;
4753
#endif
/* __ASSEMBLY__ */
4754
4756
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_RESET 0x00000000
4757
4758
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_OFST 0x8c
4759
4788
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_LSB 0
4789
4790
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_MSB 0
4791
4792
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_WIDTH 1
4793
4794
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET_MSK 0x00000001
4795
4796
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4797
4798
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_RESET 0x0
4799
4800
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4801
4802
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4803
4815
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_LSB 16
4816
4817
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_MSB 16
4818
4819
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_WIDTH 1
4820
4821
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET_MSK 0x00010000
4822
4823
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_CLR_MSK 0xfffeffff
4824
4825
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_RESET 0x0
4826
4827
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4828
4829
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4830
4842
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_LSB 24
4843
4844
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_MSB 24
4845
4846
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_WIDTH 1
4847
4848
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET_MSK 0x01000000
4849
4850
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4851
4852
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_RESET 0x0
4853
4854
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4855
4856
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4857
4858
#ifndef __ASSEMBLY__
4859
4869
struct
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s
4870
{
4871
uint32_t
mpu_m0
: 1;
4872
uint32_t : 15;
4873
uint32_t
fpga2soc
: 1;
4874
uint32_t : 7;
4875
uint32_t
ahb_ap
: 1;
4876
uint32_t : 7;
4877
};
4878
4880
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_s
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t
;
4881
#endif
/* __ASSEMBLY__ */
4882
4884
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_RESET 0x00000000
4885
4886
#define ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_OFST 0x90
4887
4916
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_LSB 0
4917
4918
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_MSB 0
4919
4920
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_WIDTH 1
4921
4922
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET_MSK 0x00000001
4923
4924
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_CLR_MSK 0xfffffffe
4925
4926
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_RESET 0x0
4927
4928
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_GET(value) (((value) & 0x00000001) >> 0)
4929
4930
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_MPU_M0_SET(value) (((value) << 0) & 0x00000001)
4931
4943
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_LSB 16
4944
4945
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_MSB 16
4946
4947
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_WIDTH 1
4948
4949
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET_MSK 0x00010000
4950
4951
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_CLR_MSK 0xfffeffff
4952
4953
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_RESET 0x0
4954
4955
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_GET(value) (((value) & 0x00010000) >> 16)
4956
4957
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_F2H_SET(value) (((value) << 16) & 0x00010000)
4958
4970
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_LSB 24
4971
4972
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_MSB 24
4973
4974
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_WIDTH 1
4975
4976
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET_MSK 0x01000000
4977
4978
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_CLR_MSK 0xfeffffff
4979
4980
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_RESET 0x0
4981
4982
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_GET(value) (((value) & 0x01000000) >> 24)
4983
4984
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_AHB_AP_SET(value) (((value) << 24) & 0x01000000)
4985
4986
#ifndef __ASSEMBLY__
4987
4997
struct
ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s
4998
{
4999
uint32_t
mpu_m0
: 1;
5000
uint32_t : 15;
5001
uint32_t
fpga2soc
: 1;
5002
uint32_t : 7;
5003
uint32_t
ahb_ap
: 1;
5004
uint32_t : 7;
5005
};
5006
5008
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_s
ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t
;
5009
#endif
/* __ASSEMBLY__ */
5010
5012
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_RESET 0x00000000
5013
5014
#define ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_OFST 0x94
5015
5016
#ifndef __ASSEMBLY__
5017
5027
struct
ALT_NOC_FW_L4_SYS_SCR_s
5028
{
5029
volatile
ALT_NOC_FW_L4_SYS_SCR_CAN0_ECC_t
can0_ecc
;
5030
volatile
ALT_NOC_FW_L4_SYS_SCR_CAN1_ECC_t
can1_ecc
;
5031
volatile
ALT_NOC_FW_L4_SYS_SCR_DMA_ECC_t
dma_ecc
;
5032
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC_t
emac0rx_ecc
;
5033
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC_t
emac0tx_ecc
;
5034
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC_t
emac1rx_ecc
;
5035
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC_t
emac1tx_ecc
;
5036
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC_t
emac2rx_ecc
;
5037
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC_t
emac2tx_ecc
;
5038
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC3RX_ECC_t
emac3rx_ecc
;
5039
volatile
ALT_NOC_FW_L4_SYS_SCR_EMAC3TX_ECC_t
emac3tx_ecc
;
5040
volatile
ALT_NOC_FW_L4_SYS_SCR_NAND_ECC_t
nand_ecc
;
5041
volatile
ALT_NOC_FW_L4_SYS_SCR_NAND_RD_ECC_t
nand_read_ecc
;
5042
volatile
ALT_NOC_FW_L4_SYS_SCR_NAND_WR_ECC_t
nand_write_ecc
;
5043
volatile
ALT_NOC_FW_L4_SYS_SCR_ONCHIPRAM_ECC_t
onchipram_ecc
;
5044
volatile
ALT_NOC_FW_L4_SYS_SCR_QSPI_ECC_t
qspi_ecc
;
5045
volatile
ALT_NOC_FW_L4_SYS_SCR_SDMMC_ECC_t
sdmmc_ecc
;
5046
volatile
ALT_NOC_FW_L4_SYS_SCR_USB0_ECC_t
usb0_ecc
;
5047
volatile
ALT_NOC_FW_L4_SYS_SCR_USB1_ECC_t
usb1_ecc
;
5048
volatile
ALT_NOC_FW_L4_SYS_SCR_CLK_MANAGER_t
clock_manager
;
5049
volatile
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_REG_t
fpga_manager_register
;
5050
volatile
ALT_NOC_FW_L4_SYS_SCR_PIN_MUX_REG_t
pin_mux_register
;
5051
volatile
ALT_NOC_FW_L4_SYS_SCR_RST_MANAGER_t
reset_manager
;
5052
volatile
ALT_NOC_FW_L4_SYS_SCR_SYS_MANAGER_t
system_manager
;
5053
volatile
ALT_NOC_FW_L4_SYS_SCR_OSC0_TMR_t
osc0_timer
;
5054
volatile
ALT_NOC_FW_L4_SYS_SCR_OSC1_TMR_t
osc1_timer
;
5055
volatile
ALT_NOC_FW_L4_SYS_SCR_WD0_t
watchdog0
;
5056
volatile
ALT_NOC_FW_L4_SYS_SCR_WD1_t
watchdog1
;
5057
volatile
ALT_NOC_FW_L4_SYS_SCR_DAP_t
dap
;
5058
volatile
ALT_NOC_FW_L4_SYS_SCR_FPGA_MANAGER_STREAMING_t
fpga_manager_streaming
;
5059
volatile
ALT_NOC_FW_L4_SYS_SCR_SEC_MGR_STREAMING_t
security_manager_streaming
;
5060
volatile
ALT_NOC_FW_L4_SYS_SCR_HMC_REG_t
hmc_register
;
5061
volatile
ALT_NOC_FW_L4_SYS_SCR_HMC_ADAPTOR_REG_t
hmc_adaptor_register
;
5062
volatile
ALT_NOC_FW_L4_SYS_SCR_L3_INTERCONNECT_REG_t
l3_interconnect_register
;
5063
volatile
ALT_NOC_FW_L4_SYS_SCR_DDR_SCHED_REG_t
ddr_scheduler_register
;
5064
volatile
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_FW_CSR_t
l4_interconnect_firewall_csr
;
5065
volatile
ALT_NOC_FW_L4_SYS_SCR_L4_INTERCONNECT_PRBS_CSR_t
l4_interconnect_probes_csr
;
5066
volatile
ALT_NOC_FW_L4_SYS_SCR_L4_QOS_CSR_t
l4_qos_csr
;
5067
volatile
uint32_t
_pad_0x98_0x100
[26];
5068
};
5069
5071
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_s
ALT_NOC_FW_L4_SYS_SCR_t
;
5073
struct
ALT_NOC_FW_L4_SYS_SCR_raw_s
5074
{
5075
volatile
uint32_t
can0_ecc
;
5076
volatile
uint32_t
can1_ecc
;
5077
volatile
uint32_t
dma_ecc
;
5078
volatile
uint32_t
emac0rx_ecc
;
5079
volatile
uint32_t
emac0tx_ecc
;
5080
volatile
uint32_t
emac1rx_ecc
;
5081
volatile
uint32_t
emac1tx_ecc
;
5082
volatile
uint32_t
emac2rx_ecc
;
5083
volatile
uint32_t
emac2tx_ecc
;
5084
volatile
uint32_t
emac3rx_ecc
;
5085
volatile
uint32_t
emac3tx_ecc
;
5086
volatile
uint32_t
nand_ecc
;
5087
volatile
uint32_t
nand_read_ecc
;
5088
volatile
uint32_t
nand_write_ecc
;
5089
volatile
uint32_t
onchipram_ecc
;
5090
volatile
uint32_t
qspi_ecc
;
5091
volatile
uint32_t
sdmmc_ecc
;
5092
volatile
uint32_t
usb0_ecc
;
5093
volatile
uint32_t
usb1_ecc
;
5094
volatile
uint32_t
clock_manager
;
5095
volatile
uint32_t
fpga_manager_register
;
5096
volatile
uint32_t
pin_mux_register
;
5097
volatile
uint32_t
reset_manager
;
5098
volatile
uint32_t
system_manager
;
5099
volatile
uint32_t
osc0_timer
;
5100
volatile
uint32_t
osc1_timer
;
5101
volatile
uint32_t
watchdog0
;
5102
volatile
uint32_t
watchdog1
;
5103
volatile
uint32_t
dap
;
5104
volatile
uint32_t
fpga_manager_streaming
;
5105
volatile
uint32_t
security_manager_streaming
;
5106
volatile
uint32_t
hmc_register
;
5107
volatile
uint32_t
hmc_adaptor_register
;
5108
volatile
uint32_t
l3_interconnect_register
;
5109
volatile
uint32_t
ddr_scheduler_register
;
5110
volatile
uint32_t
l4_interconnect_firewall_csr
;
5111
volatile
uint32_t
l4_interconnect_probes_csr
;
5112
volatile
uint32_t
l4_qos_csr
;
5113
volatile
uint32_t
_pad_0x98_0x100
[26];
5114
};
5115
5117
typedef
volatile
struct
ALT_NOC_FW_L4_SYS_SCR_raw_s
ALT_NOC_FW_L4_SYS_SCR_raw_t
;
5118
#endif
/* __ASSEMBLY__ */
5119
5121
#ifdef __cplusplus
5122
}
5123
#endif
/* __cplusplus */
5124
#endif
/* __ALT_SOCAL_NOC_FW_L4_SYS_SCR_H__ */
5125
include
soc_a10
socal
alt_noc_fw_l4_sys_scr.h
Generated on Tue Sep 8 2015 13:33:01 for Altera SoCAL by
1.8.2