Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ctrlcfg0

Description

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE
[6:4] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE
[8:7] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS
[13:9] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN
[18:14] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN
[23:19] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN
[28:24] RW 0x0 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN
[31:29] ??? 0x0 UNDEFINED

Field : cfg_mem_type

Selects memory type. Program this field with one of the following binary values, "0000" for DDR3 SDRAM, "0001" for DDR4 SDRAM, "0010" for LPDDR3 SDRAM and "0011" for RLDRAM3.

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_LSB   0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_MSB   3
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_WIDTH   4
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET_MSK   0x0000000f
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_CLR_MSK   0xfffffff0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : cfg_dimm_type

Selects dimm type. Program this field with one of the following binary values, "3

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_LSB   4
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_MSB   6
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_WIDTH   3
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET_MSK   0x00000070
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_CLR_MSK   0xffffff8f
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_GET(value)   (((value) & 0x00000070) >> 4)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET(value)   (((value) << 4) & 0x00000070)
 

Field : cfg_ac_pos

Specify C/A (command/address) pin position. 2

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_LSB   7
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_MSB   8
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_WIDTH   2
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET_MSK   0x00000180
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_CLR_MSK   0xfffffe7f
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_GET(value)   (((value) & 0x00000180) >> 7)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET(value)   (((value) << 7) & 0x00000180)
 

Field : cfg_ctrl_burst_length

Configures burst length for control path. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_LSB   9
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_MSB   13
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET_MSK   0x00003e00
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_CLR_MSK   0xffffc1ff
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_GET(value)   (((value) & 0x00003e00) >> 9)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET(value)   (((value) << 9) & 0x00003e00)
 

Field : cfg_dbc0_burst_length

Configures burst length for DBC0. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_LSB   14
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_MSB   18
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET_MSK   0x0007c000
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_CLR_MSK   0xfff83fff
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_GET(value)   (((value) & 0x0007c000) >> 14)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET(value)   (((value) << 14) & 0x0007c000)
 

Field : cfg_dbc1_burst_length

Configures burst length for DBC1. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_LSB   19
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_MSB   23
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET_MSK   0x00f80000
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_CLR_MSK   0xff07ffff
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_GET(value)   (((value) & 0x00f80000) >> 19)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET(value)   (((value) << 19) & 0x00f80000)
 

Field : cfg_dbc2_burst_length

Configures burst length for DBC2. Legal values are valid for JEDEC allowed DRAM values for the DRAM selected in cfg_type. For DDR3, DDR4 and LPDDR3, this should be programmed with 8 (binary "01000"), for RLDRAM III it can be programmed with 2 or 4 or 8

Field Access Macros:

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_LSB   24
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_MSB   28
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_WIDTH   5
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET_MSK   0x1f000000
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_CLR_MSK   0xe0ffffff
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_GET(value)   (((value) & 0x1f000000) >> 24)
 
#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET(value)   (((value) << 24) & 0x1f000000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_CTLCFG0_s
 

Macros

#define ALT_IO48_HMC_MMR_CTLCFG0_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_CTLCFG0_OFST   0x28
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_CTLCFG0_s 
ALT_IO48_HMC_MMR_CTLCFG0_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_CTLCFG0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG0.

Data Fields
uint32_t cfg_mem_type: 4 ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE
uint32_t cfg_dimm_type: 3 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE
uint32_t cfg_ac_pos: 2 ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS
uint32_t cfg_ctrl_burst_length: 5 ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN
uint32_t cfg_dbc0_burst_length: 5 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN
uint32_t cfg_dbc1_burst_length: 5 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN
uint32_t cfg_dbc2_burst_length: 5 ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN
uint32_t __pad0__: 3 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_MSB   3

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET_MSK   0x0000000f

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_CLR_MSK   0xfffffff0

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_MEM_TYPE register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_LSB   4

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_MSB   6

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_WIDTH   3

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET_MSK   0x00000070

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_CLR_MSK   0xffffff8f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_GET (   value)    (((value) & 0x00000070) >> 4)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE_SET (   value)    (((value) << 4) & 0x00000070)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DIMM_TYPE register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_LSB   7

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_WIDTH   2

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET_MSK   0x00000180

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_CLR_MSK   0xfffffe7f

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_GET (   value)    (((value) & 0x00000180) >> 7)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS_SET (   value)    (((value) << 7) & 0x00000180)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_AC_POS register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_LSB   9

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_MSB   13

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET_MSK   0x00003e00

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_CLR_MSK   0xffffc1ff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_GET (   value)    (((value) & 0x00003e00) >> 9)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN_SET (   value)    (((value) << 9) & 0x00003e00)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_CTL_BURST_LEN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_LSB   14

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_MSB   18

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET_MSK   0x0007c000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_CLR_MSK   0xfff83fff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_GET (   value)    (((value) & 0x0007c000) >> 14)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN_SET (   value)    (((value) << 14) & 0x0007c000)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC0_BURST_LEN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_LSB   19

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_MSB   23

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET_MSK   0x00f80000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_CLR_MSK   0xff07ffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_GET (   value)    (((value) & 0x00f80000) >> 19)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN_SET (   value)    (((value) << 19) & 0x00f80000)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC1_BURST_LEN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_LSB   24

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_MSB   28

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_WIDTH   5

The width in bits of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET_MSK   0x1f000000

The mask used to set the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_CLR_MSK   0xe0ffffff

The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_GET (   value)    (((value) & 0x1f000000) >> 24)

Extracts the ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN field value from a register.

#define ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN_SET (   value)    (((value) << 24) & 0x1f000000)

Produces a ALT_IO48_HMC_MMR_CTLCFG0_CFG_DBC2_BURST_LEN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_CTLCFG0_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_CTLCFG0 register.

#define ALT_IO48_HMC_MMR_CTLCFG0_OFST   0x28

The byte offset of the ALT_IO48_HMC_MMR_CTLCFG0 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG0.