Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : wdt_torr

Description

Timeout Range Register

Register Layout

Bits Access Reset Description
[3:0] RW 0xf ALT_L4WD_TORR_TOP
[7:4] RW 0xf ALT_L4WD_TORR_TOP_INIT
[31:8] R 0x0 ALT_L4WD_TORR_RSVD

Field : top

Timeout period. Writes have no effect when the configuration parameter

WDT_HC_TOP = 1, thus making this register read-only. This field is used

to select the timeout period from which the watchdog counter restarts.

A change of the timeout period takes effect only after the next counter

restart (kick). The range of values is limited by the WDT_CNT_WIDTH. If

TOP is programmed to select a range that is greater than the counter width,

the timeout period is truncated to fit to the counter width. This affects

only the non-user specified values as users are limited to these boundaries

during configuration. The range of values available for a 32-bit watchdog

counter are:

Where i = TOP and

t = timeout period

For i = 0 to 15

if WDT_USE_FIX_TOP==1

t = 2(16 + i)

else

t = WDT_USER_TOP_(i)

Field Enumeration Values:

Enum Value Description
ALT_L4WD_TORR_TOP_E_TMO64K 0x0 Timeout = 65536 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO128K 0x1 Timeout = 131072 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO256K 0x2 Timeout = 262144 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO512K 0x3 Timeout = 524288 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO1M 0x4 Timeout = 1048576 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO2M 0x5 Timeout = 2097152 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO4M 0x6 Timeout = 4194304 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO8M 0x7 Timeout = 8388608 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO16M 0x8 Timeout = 16777216 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO32M 0x9 Timeout = 33554432 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO64M 0xa Timeout = 67108864 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO128M 0xb Timeout = 134217728 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO256M 0xc Timeout = 268435456 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO512M 0xd Timeout = 536870912 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO1G 0xe Timeout = 1073741824 osc1_clk
ALT_L4WD_TORR_TOP_E_TMO2G 0xf Timeout = 2147483648 osc1_clk

Field Access Macros:

#define ALT_L4WD_TORR_TOP_E_TMO64K   0x0
 
#define ALT_L4WD_TORR_TOP_E_TMO128K   0x1
 
#define ALT_L4WD_TORR_TOP_E_TMO256K   0x2
 
#define ALT_L4WD_TORR_TOP_E_TMO512K   0x3
 
#define ALT_L4WD_TORR_TOP_E_TMO1M   0x4
 
#define ALT_L4WD_TORR_TOP_E_TMO2M   0x5
 
#define ALT_L4WD_TORR_TOP_E_TMO4M   0x6
 
#define ALT_L4WD_TORR_TOP_E_TMO8M   0x7
 
#define ALT_L4WD_TORR_TOP_E_TMO16M   0x8
 
#define ALT_L4WD_TORR_TOP_E_TMO32M   0x9
 
#define ALT_L4WD_TORR_TOP_E_TMO64M   0xa
 
#define ALT_L4WD_TORR_TOP_E_TMO128M   0xb
 
#define ALT_L4WD_TORR_TOP_E_TMO256M   0xc
 
#define ALT_L4WD_TORR_TOP_E_TMO512M   0xd
 
#define ALT_L4WD_TORR_TOP_E_TMO1G   0xe
 
#define ALT_L4WD_TORR_TOP_E_TMO2G   0xf
 
#define ALT_L4WD_TORR_TOP_LSB   0
 
#define ALT_L4WD_TORR_TOP_MSB   3
 
#define ALT_L4WD_TORR_TOP_WIDTH   4
 
#define ALT_L4WD_TORR_TOP_SET_MSK   0x0000000f
 
#define ALT_L4WD_TORR_TOP_CLR_MSK   0xfffffff0
 
#define ALT_L4WD_TORR_TOP_RESET   0xf
 
#define ALT_L4WD_TORR_TOP_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_L4WD_TORR_TOP_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : top_init

Timeout period for initialization.

Writes to these register bits have no effect when the configuration

parameter WDT_HC_TOP = 1 or WDT_ALWAYS_EN = 1. Used to

select the timeout period that the watchdog counter restarts from for

the first counter restart (kick). This register should be written after

reset and before the WDT is enabled.

A change of the TOP_INIT is seen only once the WDT has been

enabled, and any change after the first kick is not seen as subsequent

kicks use the period specified by the TOP bits.

The range of values is limited by the WDT_CNT_WIDTH. If

TOP_INIT is programmed to select a range that is greater than the

counter width, the timeout period is truncated to fit to the counter

width. This affects only the non-user specified values as users are

limited to these boundaries during configuration.

The range of values available for a 32-bit watchdog counter are:

Where i = TOP_INIT and

t = timeout period

For i = 0 to 15

if WDT_USE_FIX_TOP==1

t = 2(16 + i)

else

t = WDT_USER_TOP_INIT_(i)

NOTE: These bits exist only when the configuration parameter

WDT_DUAL_TOP = 1, otherwise, they are fixed at zero.

Field Enumeration Values:

Enum Value Description
ALT_L4WD_TORR_TOP_INIT_E_TMO64K 0x0 Timeout = 65536 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO128K 0x1 Timeout = 131072 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO256K 0x2 Timeout = 262144 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO512K 0x3 Timeout = 524288 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO1M 0x4 Timeout = 1048576 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO2M 0x5 Timeout = 2097152 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO4M 0x6 Timeout = 4194304 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO8M 0x7 Timeout = 8388608 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO16M 0x8 Timeout = 16777216 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO32M 0x9 Timeout = 33554432 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO64M 0xa Timeout = 67108864 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO128M 0xb Timeout = 134217728 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO256M 0xc Timeout = 268435456 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO512M 0xd Timeout = 536870912 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO1G 0xe Timeout = 1073741824 osc1_clk
ALT_L4WD_TORR_TOP_INIT_E_TMO2G 0xf Timeout = 2147483648 osc1_clk

Field Access Macros:

#define ALT_L4WD_TORR_TOP_INIT_E_TMO64K   0x0
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO128K   0x1
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO256K   0x2
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO512K   0x3
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO1M   0x4
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO2M   0x5
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO4M   0x6
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO8M   0x7
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO16M   0x8
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO32M   0x9
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO64M   0xa
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO128M   0xb
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO256M   0xc
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO512M   0xd
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO1G   0xe
 
#define ALT_L4WD_TORR_TOP_INIT_E_TMO2G   0xf
 
#define ALT_L4WD_TORR_TOP_INIT_LSB   4
 
#define ALT_L4WD_TORR_TOP_INIT_MSB   7
 
#define ALT_L4WD_TORR_TOP_INIT_WIDTH   4
 
#define ALT_L4WD_TORR_TOP_INIT_SET_MSK   0x000000f0
 
#define ALT_L4WD_TORR_TOP_INIT_CLR_MSK   0xffffff0f
 
#define ALT_L4WD_TORR_TOP_INIT_RESET   0xf
 
#define ALT_L4WD_TORR_TOP_INIT_GET(value)   (((value) & 0x000000f0) >> 4)
 
#define ALT_L4WD_TORR_TOP_INIT_SET(value)   (((value) << 4) & 0x000000f0)
 

Field : reserved

Reserved and read as 0.

Field Access Macros:

#define ALT_L4WD_TORR_RSVD_LSB   8
 
#define ALT_L4WD_TORR_RSVD_MSB   31
 
#define ALT_L4WD_TORR_RSVD_WIDTH   24
 
#define ALT_L4WD_TORR_RSVD_SET_MSK   0xffffff00
 
#define ALT_L4WD_TORR_RSVD_CLR_MSK   0x000000ff
 
#define ALT_L4WD_TORR_RSVD_RESET   0x0
 
#define ALT_L4WD_TORR_RSVD_GET(value)   (((value) & 0xffffff00) >> 8)
 
#define ALT_L4WD_TORR_RSVD_SET(value)   (((value) << 8) & 0xffffff00)
 

Data Structures

struct  ALT_L4WD_TORR_s
 

Macros

#define ALT_L4WD_TORR_RESET   0x000000ff
 
#define ALT_L4WD_TORR_OFST   0x4
 
#define ALT_L4WD_TORR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_TORR_OFST))
 

Typedefs

typedef struct ALT_L4WD_TORR_s ALT_L4WD_TORR_t
 

Data Structure Documentation

struct ALT_L4WD_TORR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L4WD_TORR.

Data Fields
uint32_t top: 4 ALT_L4WD_TORR_TOP
uint32_t top_init: 4 ALT_L4WD_TORR_TOP_INIT
const uint32_t reserved: 24 ALT_L4WD_TORR_RSVD

Macro Definitions

#define ALT_L4WD_TORR_TOP_E_TMO64K   0x0

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 65536 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO128K   0x1

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 131072 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO256K   0x2

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 262144 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO512K   0x3

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 524288 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO1M   0x4

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 1048576 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO2M   0x5

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 2097152 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO4M   0x6

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 4194304 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO8M   0x7

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 8388608 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO16M   0x8

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 16777216 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO32M   0x9

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 33554432 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO64M   0xa

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 67108864 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO128M   0xb

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 134217728 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO256M   0xc

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 268435456 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO512M   0xd

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 536870912 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO1G   0xe

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 1073741824 osc1_clk

#define ALT_L4WD_TORR_TOP_E_TMO2G   0xf

Enumerated value for register field ALT_L4WD_TORR_TOP

Timeout = 2147483648 osc1_clk

#define ALT_L4WD_TORR_TOP_LSB   0

The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP register field.

#define ALT_L4WD_TORR_TOP_MSB   3

The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP register field.

#define ALT_L4WD_TORR_TOP_WIDTH   4

The width in bits of the ALT_L4WD_TORR_TOP register field.

#define ALT_L4WD_TORR_TOP_SET_MSK   0x0000000f

The mask used to set the ALT_L4WD_TORR_TOP register field value.

#define ALT_L4WD_TORR_TOP_CLR_MSK   0xfffffff0

The mask used to clear the ALT_L4WD_TORR_TOP register field value.

#define ALT_L4WD_TORR_TOP_RESET   0xf

The reset value of the ALT_L4WD_TORR_TOP register field.

#define ALT_L4WD_TORR_TOP_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_L4WD_TORR_TOP field value from a register.

#define ALT_L4WD_TORR_TOP_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_L4WD_TORR_TOP register field value suitable for setting the register.

#define ALT_L4WD_TORR_TOP_INIT_E_TMO64K   0x0

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 65536 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO128K   0x1

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 131072 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO256K   0x2

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 262144 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO512K   0x3

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 524288 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO1M   0x4

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 1048576 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO2M   0x5

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 2097152 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO4M   0x6

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 4194304 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO8M   0x7

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 8388608 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO16M   0x8

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 16777216 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO32M   0x9

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 33554432 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO64M   0xa

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 67108864 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO128M   0xb

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 134217728 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO256M   0xc

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 268435456 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO512M   0xd

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 536870912 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO1G   0xe

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 1073741824 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_E_TMO2G   0xf

Enumerated value for register field ALT_L4WD_TORR_TOP_INIT

Timeout = 2147483648 osc1_clk

#define ALT_L4WD_TORR_TOP_INIT_LSB   4

The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_TOP_INIT register field.

#define ALT_L4WD_TORR_TOP_INIT_MSB   7

The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_TOP_INIT register field.

#define ALT_L4WD_TORR_TOP_INIT_WIDTH   4

The width in bits of the ALT_L4WD_TORR_TOP_INIT register field.

#define ALT_L4WD_TORR_TOP_INIT_SET_MSK   0x000000f0

The mask used to set the ALT_L4WD_TORR_TOP_INIT register field value.

#define ALT_L4WD_TORR_TOP_INIT_CLR_MSK   0xffffff0f

The mask used to clear the ALT_L4WD_TORR_TOP_INIT register field value.

#define ALT_L4WD_TORR_TOP_INIT_RESET   0xf

The reset value of the ALT_L4WD_TORR_TOP_INIT register field.

#define ALT_L4WD_TORR_TOP_INIT_GET (   value)    (((value) & 0x000000f0) >> 4)

Extracts the ALT_L4WD_TORR_TOP_INIT field value from a register.

#define ALT_L4WD_TORR_TOP_INIT_SET (   value)    (((value) << 4) & 0x000000f0)

Produces a ALT_L4WD_TORR_TOP_INIT register field value suitable for setting the register.

#define ALT_L4WD_TORR_RSVD_LSB   8

The Least Significant Bit (LSB) position of the ALT_L4WD_TORR_RSVD register field.

#define ALT_L4WD_TORR_RSVD_MSB   31

The Most Significant Bit (MSB) position of the ALT_L4WD_TORR_RSVD register field.

#define ALT_L4WD_TORR_RSVD_WIDTH   24

The width in bits of the ALT_L4WD_TORR_RSVD register field.

#define ALT_L4WD_TORR_RSVD_SET_MSK   0xffffff00

The mask used to set the ALT_L4WD_TORR_RSVD register field value.

#define ALT_L4WD_TORR_RSVD_CLR_MSK   0x000000ff

The mask used to clear the ALT_L4WD_TORR_RSVD register field value.

#define ALT_L4WD_TORR_RSVD_RESET   0x0

The reset value of the ALT_L4WD_TORR_RSVD register field.

#define ALT_L4WD_TORR_RSVD_GET (   value)    (((value) & 0xffffff00) >> 8)

Extracts the ALT_L4WD_TORR_RSVD field value from a register.

#define ALT_L4WD_TORR_RSVD_SET (   value)    (((value) << 8) & 0xffffff00)

Produces a ALT_L4WD_TORR_RSVD register field value suitable for setting the register.

#define ALT_L4WD_TORR_RESET   0x000000ff

The reset value of the ALT_L4WD_TORR register.

#define ALT_L4WD_TORR_OFST   0x4

The byte offset of the ALT_L4WD_TORR register from the beginning of the component.

#define ALT_L4WD_TORR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_TORR_OFST))

The address of the ALT_L4WD_TORR register.

Typedef Documentation

The typedef declaration for register ALT_L4WD_TORR.