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alt_ecc_emac2_tx_ecc.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__
36
#define __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__
37
38
#ifndef __ASSEMBLY__
39
#ifdef __cplusplus
40
#include <cstdint>
41
extern
"C"
42
{
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#else
/* __cplusplus */
44
#include <stdint.h>
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#endif
/* __cplusplus */
46
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_MSB 15
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_WIDTH 16
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_SET_MSK 0x0000ffff
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_CLR_MSK 0xffff0000
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_SIREV_SET(value) (((value) << 0) & 0x0000ffff)
89
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#ifndef __ASSEMBLY__
91
101
struct
ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_s
102
{
103
const
uint32_t
SIREV
: 16;
104
uint32_t : 16;
105
};
106
108
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_s
ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_t
;
109
#endif
/* __ASSEMBLY__ */
110
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_OFST 0x0
115
142
#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_ECC_EMAC2_TX_ECC_CTL_ECC_EN_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_LSB 8
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_MSB 8
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_SET_MSK 0x00000100
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_CLR_MSK 0xfffffeff
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_ECC_EMAC2_TX_ECC_CTL_CNT_RSTA_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_LSB 16
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_MSB 16
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_SET_MSK 0x00010000
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_CLR_MSK 0xfffeffff
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_ECC_EMAC2_TX_ECC_CTL_INITA_SET(value) (((value) << 16) & 0x00010000)
207
208
#ifndef __ASSEMBLY__
209
219
struct
ALT_ECC_EMAC2_TX_ECC_CTL_s
220
{
221
uint32_t
ECC_EN
: 1;
222
uint32_t : 7;
223
uint32_t
CNT_RSTA
: 1;
224
uint32_t : 7;
225
uint32_t
INITA
: 1;
226
uint32_t : 15;
227
};
228
230
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_CTL_s
ALT_ECC_EMAC2_TX_ECC_CTL_t
;
231
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_CTL_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_CTL_OFST 0x8
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_GET(value) (((value) & 0x00000001) >> 0)
274
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_INITCOMPLETEA_SET(value) (((value) << 0) & 0x00000001)
276
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#ifndef __ASSEMBLY__
278
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struct
ALT_ECC_EMAC2_TX_ECC_INITSTAT_s
289
{
290
uint32_t
INITCOMPLETEA
: 1;
291
uint32_t : 31;
292
};
293
295
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_INITSTAT_s
ALT_ECC_EMAC2_TX_ECC_INITSTAT_t
;
296
#endif
/* __ASSEMBLY__ */
297
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_INITSTAT_OFST 0xc
302
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_LSB 0
326
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_MSB 0
328
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_GET(value) (((value) & 0x00000001) >> 0)
338
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_SERRINTEN_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
342
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struct
ALT_ECC_EMAC2_TX_ECC_ERRINTEN_s
353
{
354
uint32_t
SERRINTEN
: 1;
355
uint32_t : 31;
356
};
357
359
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ERRINTEN_s
ALT_ECC_EMAC2_TX_ECC_ERRINTEN_t
;
360
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTEN_OFST 0x10
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_SERRINTS_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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416
struct
ALT_ECC_EMAC2_TX_ECC_ERRINTENS_s
417
{
418
uint32_t
SERRINTS
: 1;
419
uint32_t : 31;
420
};
421
423
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ERRINTENS_s
ALT_ECC_EMAC2_TX_ECC_ERRINTENS_t
;
424
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENS_OFST 0x14
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_SERRINTR_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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struct
ALT_ECC_EMAC2_TX_ECC_ERRINTENR_s
488
{
489
uint32_t
SERRINTR
: 1;
490
uint32_t : 31;
491
};
492
494
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ERRINTENR_s
ALT_ECC_EMAC2_TX_ECC_ERRINTENR_t
;
495
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_RESET 0x00000000
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#define ALT_ECC_EMAC2_TX_ECC_ERRINTENR_OFST 0x18
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_LSB 0
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_SET_MSK 0x00000001
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_CLR_MSK 0xfffffffe
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTMOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_LSB 8
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_MSB 8
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_SET_MSK 0x00000100
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_CLR_MSK 0xfffffeff
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_GET(value) (((value) & 0x00000100) >> 8)
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONOVF_SET(value) (((value) << 8) & 0x00000100)
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_LSB 16
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_MSB 16
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_WIDTH 1
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_SET_MSK 0x00010000
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_CLR_MSK 0xfffeffff
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_RESET 0x0
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_GET(value) (((value) & 0x00010000) >> 16)
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_INTONCMP_SET(value) (((value) << 16) & 0x00010000)
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#ifndef __ASSEMBLY__
595
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struct
ALT_ECC_EMAC2_TX_ECC_INTMOD_s
606
{
607
uint32_t
INTMODE
: 1;
608
uint32_t : 7;
609
uint32_t
INTONOVF
: 1;
610
uint32_t : 7;
611
uint32_t
INTONCMP
: 1;
612
uint32_t : 15;
613
};
614
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typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_INTMOD_s
ALT_ECC_EMAC2_TX_ECC_INTMOD_t
;
617
#endif
/* __ASSEMBLY__ */
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_RESET 0x00000000
621
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#define ALT_ECC_EMAC2_TX_ECC_INTMOD_OFST 0x1c
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#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_LSB 0
649
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#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_MSB 0
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#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_WIDTH 1
653
654
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_SET_MSK 0x00000001
655
656
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_CLR_MSK 0xfffffffe
657
658
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_RESET 0x0
659
660
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_GET(value) (((value) & 0x00000001) >> 0)
661
662
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TSERRA_SET(value) (((value) << 0) & 0x00000001)
663
673
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_LSB 8
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675
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_MSB 8
676
677
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_WIDTH 1
678
679
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_SET_MSK 0x00000100
680
681
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_CLR_MSK 0xfffffeff
682
683
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_RESET 0x0
684
685
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_GET(value) (((value) & 0x00000100) >> 8)
686
687
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_TDERRA_SET(value) (((value) << 8) & 0x00000100)
688
689
#ifndef __ASSEMBLY__
690
700
struct
ALT_ECC_EMAC2_TX_ECC_INTTEST_s
701
{
702
uint32_t
TSERRA
: 1;
703
uint32_t : 7;
704
uint32_t
TDERRA
: 1;
705
uint32_t : 23;
706
};
707
709
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_INTTEST_s
ALT_ECC_EMAC2_TX_ECC_INTTEST_t
;
710
#endif
/* __ASSEMBLY__ */
711
713
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_RESET 0x00000000
714
715
#define ALT_ECC_EMAC2_TX_ECC_INTTEST_OFST 0x24
716
739
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_LSB 0
740
741
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_MSB 0
742
743
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_WIDTH 1
744
745
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_SET_MSK 0x00000001
746
747
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_CLR_MSK 0xfffffffe
748
749
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_RESET 0x0
750
751
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_GET(value) (((value) & 0x00000001) >> 0)
752
753
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_CMPFLGA_SET(value) (((value) << 0) & 0x00000001)
754
755
#ifndef __ASSEMBLY__
756
766
struct
ALT_ECC_EMAC2_TX_ECC_MODSTAT_s
767
{
768
uint32_t
CMPFLGA
: 1;
769
uint32_t : 31;
770
};
771
773
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_MODSTAT_s
ALT_ECC_EMAC2_TX_ECC_MODSTAT_t
;
774
#endif
/* __ASSEMBLY__ */
775
777
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_RESET 0x00000000
778
779
#define ALT_ECC_EMAC2_TX_ECC_MODSTAT_OFST 0x28
780
804
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_LSB 0
805
806
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_MSB 9
807
808
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_WIDTH 10
809
810
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_SET_MSK 0x000003ff
811
812
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_CLR_MSK 0xfffffc00
813
814
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_RESET 0x0
815
816
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
817
818
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
819
820
#ifndef __ASSEMBLY__
821
831
struct
ALT_ECC_EMAC2_TX_ECC_DERRADDRA_s
832
{
833
uint32_t
Address
: 10;
834
uint32_t : 22;
835
};
836
838
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_DERRADDRA_s
ALT_ECC_EMAC2_TX_ECC_DERRADDRA_t
;
839
#endif
/* __ASSEMBLY__ */
840
842
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_RESET 0x00000000
843
844
#define ALT_ECC_EMAC2_TX_ECC_DERRADDRA_OFST 0x2c
845
869
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_LSB 0
870
871
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_MSB 9
872
873
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_WIDTH 10
874
875
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_SET_MSK 0x000003ff
876
877
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_CLR_MSK 0xfffffc00
878
879
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_RESET 0x0
880
881
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
882
883
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_ADDR_SET(value) (((value) << 0) & 0x000003ff)
884
885
#ifndef __ASSEMBLY__
886
896
struct
ALT_ECC_EMAC2_TX_ECC_SERRADDRA_s
897
{
898
uint32_t
Address
: 10;
899
uint32_t : 22;
900
};
901
903
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_SERRADDRA_s
ALT_ECC_EMAC2_TX_ECC_SERRADDRA_t
;
904
#endif
/* __ASSEMBLY__ */
905
907
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_RESET 0x00000000
908
909
#define ALT_ECC_EMAC2_TX_ECC_SERRADDRA_OFST 0x30
910
937
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_LSB 0
938
939
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_MSB 0
940
941
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_WIDTH 1
942
943
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_SET_MSK 0x00000001
944
945
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_CLR_MSK 0xfffffffe
946
947
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_RESET 0x0
948
949
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_GET(value) (((value) & 0x00000001) >> 0)
950
951
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_SERRPENA_SET(value) (((value) << 0) & 0x00000001)
952
962
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_LSB 8
963
964
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_MSB 8
965
966
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_WIDTH 1
967
968
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_SET_MSK 0x00000100
969
970
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_CLR_MSK 0xfffffeff
971
972
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_RESET 0x0
973
974
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_GET(value) (((value) & 0x00000100) >> 8)
975
976
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_DERRPENA_SET(value) (((value) << 8) & 0x00000100)
977
978
#ifndef __ASSEMBLY__
979
989
struct
ALT_ECC_EMAC2_TX_ECC_INTSTAT_s
990
{
991
uint32_t
SERRPENA
: 1;
992
uint32_t : 7;
993
uint32_t
DERRPENA
: 1;
994
uint32_t : 23;
995
};
996
998
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_INTSTAT_s
ALT_ECC_EMAC2_TX_ECC_INTSTAT_t
;
999
#endif
/* __ASSEMBLY__ */
1000
1002
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_RESET 0x00000000
1003
1004
#define ALT_ECC_EMAC2_TX_ECC_INTSTAT_OFST 0x20
1005
1027
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_LSB 0
1028
1029
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_MSB 31
1030
1031
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_WIDTH 32
1032
1033
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_SET_MSK 0xffffffff
1034
1035
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_CLR_MSK 0x00000000
1036
1037
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_RESET 0x0
1038
1039
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_GET(value) (((value) & 0xffffffff) >> 0)
1040
1041
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_SERRCNT_SET(value) (((value) << 0) & 0xffffffff)
1042
1043
#ifndef __ASSEMBLY__
1044
1054
struct
ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_s
1055
{
1056
uint32_t
SERRCNT
: 32;
1057
};
1058
1060
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_s
ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_t
;
1061
#endif
/* __ASSEMBLY__ */
1062
1064
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_RESET 0x00000000
1065
1066
#define ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_OFST 0x3c
1067
1091
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_LSB 0
1092
1093
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_MSB 9
1094
1095
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_WIDTH 10
1096
1097
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET_MSK 0x000003ff
1098
1099
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_CLR_MSK 0xfffffc00
1100
1101
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_RESET 0x0
1102
1103
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_GET(value) (((value) & 0x000003ff) >> 0)
1104
1105
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_ECC_ADDRBUS_SET(value) (((value) << 0) & 0x000003ff)
1106
1107
#ifndef __ASSEMBLY__
1108
1118
struct
ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_s
1119
{
1120
uint32_t
ECC_AddrBUS
: 10;
1121
uint32_t : 22;
1122
};
1123
1125
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_t
;
1126
#endif
/* __ASSEMBLY__ */
1127
1129
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_RESET 0x00000000
1130
1131
#define ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_OFST 0x40
1132
1154
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_LSB 0
1155
1156
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_MSB 31
1157
1158
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_WIDTH 32
1159
1160
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1161
1162
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1163
1164
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_RESET 0x0
1165
1166
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1167
1168
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1169
1170
#ifndef __ASSEMBLY__
1171
1181
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_s
1182
{
1183
uint32_t
ECC_RDataBUS
: 32;
1184
};
1185
1187
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_t
;
1188
#endif
/* __ASSEMBLY__ */
1189
1191
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_RESET 0x00000000
1192
1193
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_OFST 0x44
1194
1217
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_LSB 0
1218
1219
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_MSB 2
1220
1221
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_WIDTH 3
1222
1223
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET_MSK 0x00000007
1224
1225
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_CLR_MSK 0xfffffff8
1226
1227
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_RESET 0x0
1228
1229
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1230
1231
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0x00000007)
1232
1233
#ifndef __ASSEMBLY__
1234
1244
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_s
1245
{
1246
uint32_t
ECC_RDataBUS
: 3;
1247
uint32_t : 29;
1248
};
1249
1251
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_t
;
1252
#endif
/* __ASSEMBLY__ */
1253
1255
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_RESET 0x00000000
1256
1257
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_OFST 0x48
1258
1280
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_LSB 0
1281
1282
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_MSB 31
1283
1284
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_WIDTH 32
1285
1286
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1287
1288
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1289
1290
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_RESET 0x0
1291
1292
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1293
1294
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1295
1296
#ifndef __ASSEMBLY__
1297
1307
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_s
1308
{
1309
uint32_t
ECC_RDataBUS
: 32;
1310
};
1311
1313
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_t
;
1314
#endif
/* __ASSEMBLY__ */
1315
1317
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_RESET 0x00000000
1318
1319
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_OFST 0x4c
1320
1342
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_LSB 0
1343
1344
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_MSB 31
1345
1346
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_WIDTH 32
1347
1348
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET_MSK 0xffffffff
1349
1350
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_CLR_MSK 0x00000000
1351
1352
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_RESET 0x0
1353
1354
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1355
1356
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_ECC_RDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1357
1358
#ifndef __ASSEMBLY__
1359
1369
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_s
1370
{
1371
uint32_t
ECC_RDataBUS
: 32;
1372
};
1373
1375
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_t
;
1376
#endif
/* __ASSEMBLY__ */
1377
1379
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_RESET 0x00000000
1380
1381
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_OFST 0x50
1382
1404
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_LSB 0
1405
1406
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_MSB 31
1407
1408
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_WIDTH 32
1409
1410
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1411
1412
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1413
1414
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_RESET 0x0
1415
1416
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1417
1418
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1419
1420
#ifndef __ASSEMBLY__
1421
1431
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_s
1432
{
1433
uint32_t
ECC_WDataBUS
: 32;
1434
};
1435
1437
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_t
;
1438
#endif
/* __ASSEMBLY__ */
1439
1441
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_RESET 0x00000000
1442
1443
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_OFST 0x54
1444
1467
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_LSB 0
1468
1469
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_MSB 2
1470
1471
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_WIDTH 3
1472
1473
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET_MSK 0x00000007
1474
1475
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_CLR_MSK 0xfffffff8
1476
1477
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_RESET 0x0
1478
1479
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_GET(value) (((value) & 0x00000007) >> 0)
1480
1481
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0x00000007)
1482
1483
#ifndef __ASSEMBLY__
1484
1494
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_s
1495
{
1496
uint32_t
ECC_WDataBUS
: 3;
1497
uint32_t : 29;
1498
};
1499
1501
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_t
;
1502
#endif
/* __ASSEMBLY__ */
1503
1505
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_RESET 0x00000000
1506
1507
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_OFST 0x58
1508
1530
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_LSB 0
1531
1532
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_MSB 31
1533
1534
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_WIDTH 32
1535
1536
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1537
1538
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1539
1540
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_RESET 0x0
1541
1542
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1543
1544
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1545
1546
#ifndef __ASSEMBLY__
1547
1557
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_s
1558
{
1559
uint32_t
ECC_WDataBUS
: 32;
1560
};
1561
1563
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_t
;
1564
#endif
/* __ASSEMBLY__ */
1565
1567
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_RESET 0x00000000
1568
1569
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_OFST 0x5c
1570
1592
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_LSB 0
1593
1594
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_MSB 31
1595
1596
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_WIDTH 32
1597
1598
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET_MSK 0xffffffff
1599
1600
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_CLR_MSK 0x00000000
1601
1602
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_RESET 0x0
1603
1604
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_GET(value) (((value) & 0xffffffff) >> 0)
1605
1606
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_ECC_WDATABUS_SET(value) (((value) << 0) & 0xffffffff)
1607
1608
#ifndef __ASSEMBLY__
1609
1619
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_s
1620
{
1621
uint32_t
ECC_WDataBUS
: 32;
1622
};
1623
1625
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_t
;
1626
#endif
/* __ASSEMBLY__ */
1627
1629
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_RESET 0x00000000
1630
1631
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_OFST 0x60
1632
1662
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_LSB 0
1663
1664
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_MSB 6
1665
1666
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_WIDTH 7
1667
1668
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET_MSK 0x0000007f
1669
1670
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_CLR_MSK 0xffffff80
1671
1672
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_RESET 0x0
1673
1674
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1675
1676
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1677
1687
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_LSB 8
1688
1689
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_MSB 14
1690
1691
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_WIDTH 7
1692
1693
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET_MSK 0x00007f00
1694
1695
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_CLR_MSK 0xffff80ff
1696
1697
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_RESET 0x0
1698
1699
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
1700
1701
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
1702
1712
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_LSB 16
1713
1714
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_MSB 22
1715
1716
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_WIDTH 7
1717
1718
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET_MSK 0x007f0000
1719
1720
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_CLR_MSK 0xff80ffff
1721
1722
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_RESET 0x0
1723
1724
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
1725
1726
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
1727
1737
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_LSB 24
1738
1739
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_MSB 30
1740
1741
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_WIDTH 7
1742
1743
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET_MSK 0x7f000000
1744
1745
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_CLR_MSK 0x80ffffff
1746
1747
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_RESET 0x0
1748
1749
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
1750
1751
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_ECC_RDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
1752
1753
#ifndef __ASSEMBLY__
1754
1764
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_s
1765
{
1766
uint32_t
ECC_RDataecc0BUS
: 7;
1767
uint32_t : 1;
1768
uint32_t
ECC_RDataecc1BUS
: 7;
1769
uint32_t : 1;
1770
uint32_t
ECC_RDataecc2BUS
: 7;
1771
uint32_t : 1;
1772
uint32_t
ECC_RDataecc3BUS
: 7;
1773
uint32_t : 1;
1774
};
1775
1777
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_t
;
1778
#endif
/* __ASSEMBLY__ */
1779
1781
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_RESET 0x00000000
1782
1783
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_OFST 0x64
1784
1814
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_LSB 0
1815
1816
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_MSB 6
1817
1818
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_WIDTH 7
1819
1820
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET_MSK 0x0000007f
1821
1822
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_CLR_MSK 0xffffff80
1823
1824
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_RESET 0x0
1825
1826
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
1827
1828
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
1829
1839
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_LSB 8
1840
1841
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_MSB 14
1842
1843
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_WIDTH 7
1844
1845
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET_MSK 0x00007f00
1846
1847
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_CLR_MSK 0xffff80ff
1848
1849
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_RESET 0x0
1850
1851
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
1852
1853
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
1854
1864
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_LSB 16
1865
1866
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_MSB 22
1867
1868
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_WIDTH 7
1869
1870
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET_MSK 0x007f0000
1871
1872
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_CLR_MSK 0xff80ffff
1873
1874
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_RESET 0x0
1875
1876
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
1877
1878
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
1879
1889
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_LSB 24
1890
1891
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_MSB 30
1892
1893
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_WIDTH 7
1894
1895
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET_MSK 0x7f000000
1896
1897
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_CLR_MSK 0x80ffffff
1898
1899
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_RESET 0x0
1900
1901
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
1902
1903
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_ECC_RDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
1904
1905
#ifndef __ASSEMBLY__
1906
1916
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_s
1917
{
1918
uint32_t
ECC_RDataecc4BUS
: 7;
1919
uint32_t : 1;
1920
uint32_t
ECC_RDataecc5BUS
: 7;
1921
uint32_t : 1;
1922
uint32_t
ECC_RDataecc6BUS
: 7;
1923
uint32_t : 1;
1924
uint32_t
ECC_RDataecc7BUS
: 7;
1925
uint32_t : 1;
1926
};
1927
1929
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_t
;
1930
#endif
/* __ASSEMBLY__ */
1931
1933
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_RESET 0x00000000
1934
1935
#define ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_OFST 0x68
1936
1966
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_LSB 0
1967
1968
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_MSB 6
1969
1970
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_WIDTH 7
1971
1972
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET_MSK 0x0000007f
1973
1974
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_CLR_MSK 0xffffff80
1975
1976
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_RESET 0x0
1977
1978
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_GET(value) (((value) & 0x0000007f) >> 0)
1979
1980
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC0BUS_SET(value) (((value) << 0) & 0x0000007f)
1981
1991
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_LSB 8
1992
1993
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_MSB 14
1994
1995
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_WIDTH 7
1996
1997
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET_MSK 0x00007f00
1998
1999
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_CLR_MSK 0xffff80ff
2000
2001
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_RESET 0x0
2002
2003
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_GET(value) (((value) & 0x00007f00) >> 8)
2004
2005
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC1BUS_SET(value) (((value) << 8) & 0x00007f00)
2006
2016
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_LSB 16
2017
2018
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_MSB 22
2019
2020
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_WIDTH 7
2021
2022
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET_MSK 0x007f0000
2023
2024
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_CLR_MSK 0xff80ffff
2025
2026
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_RESET 0x0
2027
2028
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_GET(value) (((value) & 0x007f0000) >> 16)
2029
2030
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC2BUS_SET(value) (((value) << 16) & 0x007f0000)
2031
2041
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_LSB 24
2042
2043
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_MSB 30
2044
2045
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_WIDTH 7
2046
2047
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET_MSK 0x7f000000
2048
2049
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_CLR_MSK 0x80ffffff
2050
2051
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_RESET 0x0
2052
2053
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_GET(value) (((value) & 0x7f000000) >> 24)
2054
2055
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_ECC_WDATAECC3BUS_SET(value) (((value) << 24) & 0x7f000000)
2056
2057
#ifndef __ASSEMBLY__
2058
2068
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_s
2069
{
2070
uint32_t
ECC_WDataecc0BUS
: 7;
2071
uint32_t : 1;
2072
uint32_t
ECC_WDataecc1BUS
: 7;
2073
uint32_t : 1;
2074
uint32_t
ECC_WDataecc2BUS
: 7;
2075
uint32_t : 1;
2076
uint32_t
ECC_WDataecc3BUS
: 7;
2077
uint32_t : 1;
2078
};
2079
2081
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_t
;
2082
#endif
/* __ASSEMBLY__ */
2083
2085
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_RESET 0x00000000
2086
2087
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_OFST 0x6c
2088
2118
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_LSB 0
2119
2120
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_MSB 6
2121
2122
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_WIDTH 7
2123
2124
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET_MSK 0x0000007f
2125
2126
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_CLR_MSK 0xffffff80
2127
2128
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_RESET 0x0
2129
2130
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_GET(value) (((value) & 0x0000007f) >> 0)
2131
2132
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC4BUS_SET(value) (((value) << 0) & 0x0000007f)
2133
2143
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_LSB 8
2144
2145
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_MSB 14
2146
2147
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_WIDTH 7
2148
2149
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET_MSK 0x00007f00
2150
2151
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_CLR_MSK 0xffff80ff
2152
2153
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_RESET 0x0
2154
2155
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_GET(value) (((value) & 0x00007f00) >> 8)
2156
2157
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC5BUS_SET(value) (((value) << 8) & 0x00007f00)
2158
2168
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_LSB 16
2169
2170
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_MSB 22
2171
2172
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_WIDTH 7
2173
2174
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET_MSK 0x007f0000
2175
2176
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_CLR_MSK 0xff80ffff
2177
2178
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_RESET 0x0
2179
2180
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_GET(value) (((value) & 0x007f0000) >> 16)
2181
2182
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC6BUS_SET(value) (((value) << 16) & 0x007f0000)
2183
2193
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_LSB 24
2194
2195
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_MSB 30
2196
2197
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_WIDTH 7
2198
2199
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET_MSK 0x7f000000
2200
2201
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_CLR_MSK 0x80ffffff
2202
2203
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_RESET 0x0
2204
2205
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_GET(value) (((value) & 0x7f000000) >> 24)
2206
2207
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_ECC_WDATAECC7BUS_SET(value) (((value) << 24) & 0x7f000000)
2208
2209
#ifndef __ASSEMBLY__
2210
2220
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_s
2221
{
2222
uint32_t
ECC_WDataecc4BUS
: 7;
2223
uint32_t : 1;
2224
uint32_t
ECC_WDataecc5BUS
: 7;
2225
uint32_t : 1;
2226
uint32_t
ECC_WDataecc6BUS
: 7;
2227
uint32_t : 1;
2228
uint32_t
ECC_WDataecc7BUS
: 7;
2229
uint32_t : 1;
2230
};
2231
2233
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_t
;
2234
#endif
/* __ASSEMBLY__ */
2235
2237
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_RESET 0x00000000
2238
2239
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_OFST 0x70
2240
2263
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_LSB 0
2264
2265
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_MSB 0
2266
2267
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_WIDTH 1
2268
2269
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_SET_MSK 0x00000001
2270
2271
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_CLR_MSK 0xfffffffe
2272
2273
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_RESET 0x0
2274
2275
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_GET(value) (((value) & 0x00000001) >> 0)
2276
2277
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_DBEN_SET(value) (((value) << 0) & 0x00000001)
2278
2279
#ifndef __ASSEMBLY__
2280
2290
struct
ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_s
2291
{
2292
uint32_t
DBEN
: 1;
2293
uint32_t : 31;
2294
};
2295
2297
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_s
ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_t
;
2298
#endif
/* __ASSEMBLY__ */
2299
2301
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_RESET 0x00000000
2302
2303
#define ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_OFST 0x74
2304
2335
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_LSB 0
2336
2337
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_MSB 0
2338
2339
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_WIDTH 1
2340
2341
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET_MSK 0x00000001
2342
2343
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_CLR_MSK 0xfffffffe
2344
2345
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_RESET 0x0
2346
2347
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_GET(value) (((value) & 0x00000001) >> 0)
2348
2349
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_DATAOVR_SET(value) (((value) << 0) & 0x00000001)
2350
2360
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_LSB 1
2361
2362
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_MSB 1
2363
2364
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_WIDTH 1
2365
2366
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET_MSK 0x00000002
2367
2368
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_CLR_MSK 0xfffffffd
2369
2370
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_RESET 0x0
2371
2372
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_GET(value) (((value) & 0x00000002) >> 1)
2373
2374
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_ECCOVR_SET(value) (((value) << 1) & 0x00000002)
2375
2385
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_LSB 8
2386
2387
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_MSB 8
2388
2389
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_WIDTH 1
2390
2391
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET_MSK 0x00000100
2392
2393
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_CLR_MSK 0xfffffeff
2394
2395
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_RESET 0x0
2396
2397
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_GET(value) (((value) & 0x00000100) >> 8)
2398
2399
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RDWR_SET(value) (((value) << 8) & 0x00000100)
2400
2401
#ifndef __ASSEMBLY__
2402
2412
struct
ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s
2413
{
2414
uint32_t
DATAOVR
: 1;
2415
uint32_t
ECCOVR
: 1;
2416
uint32_t : 6;
2417
uint32_t
RDWR
: 1;
2418
uint32_t : 23;
2419
};
2420
2422
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_s
ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_t
;
2423
#endif
/* __ASSEMBLY__ */
2424
2426
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_RESET 0x00000000
2427
2428
#define ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_OFST 0x78
2429
2453
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_LSB 16
2454
2455
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_MSB 16
2456
2457
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_WIDTH 1
2458
2459
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_SET_MSK 0x00010000
2460
2461
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_CLR_MSK 0xfffeffff
2462
2463
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_RESET 0x0
2464
2465
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_GET(value) (((value) & 0x00010000) >> 16)
2466
2467
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_ENBUSA_SET(value) (((value) << 16) & 0x00010000)
2468
2469
#ifndef __ASSEMBLY__
2470
2480
struct
ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_s
2481
{
2482
uint32_t : 16;
2483
uint32_t
ENBUSA
: 1;
2484
uint32_t : 15;
2485
};
2486
2488
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_s
ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_t
;
2489
#endif
/* __ASSEMBLY__ */
2490
2492
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_RESET 0x00000000
2493
2494
#define ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_OFST 0x7c
2495
2518
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_LSB 0
2519
2520
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_MSB 0
2521
2522
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_WIDTH 1
2523
2524
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_SET_MSK 0x00000001
2525
2526
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_CLR_MSK 0xfffffffe
2527
2528
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_RESET 0x0
2529
2530
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_GET(value) (((value) & 0x00000001) >> 0)
2531
2532
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_WDEN_RAM_SET(value) (((value) << 0) & 0x00000001)
2533
2534
#ifndef __ASSEMBLY__
2535
2545
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_s
2546
{
2547
uint32_t
WDEN_RAM
: 1;
2548
uint32_t : 31;
2549
};
2550
2552
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_s
ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_t
;
2553
#endif
/* __ASSEMBLY__ */
2554
2556
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_RESET 0x00000000
2557
2558
#define ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_OFST 0x80
2559
2587
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_LSB 0
2588
2589
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_MSB 9
2590
2591
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_WIDTH 10
2592
2593
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET_MSK 0x000003ff
2594
2595
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_CLR_MSK 0xfffffc00
2596
2597
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_RESET 0x0
2598
2599
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_GET(value) (((value) & 0x000003ff) >> 0)
2600
2601
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_ADDR_SET(value) (((value) << 0) & 0x000003ff)
2602
2613
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_LSB 31
2614
2615
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_MSB 31
2616
2617
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_WIDTH 1
2618
2619
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET_MSK 0x80000000
2620
2621
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_CLR_MSK 0x7fffffff
2622
2623
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_RESET 0x0
2624
2625
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_GET(value) (((value) & 0x80000000) >> 31)
2626
2627
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_VALID_SET(value) (((value) << 31) & 0x80000000)
2628
2629
#ifndef __ASSEMBLY__
2630
2640
struct
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s
2641
{
2642
const
uint32_t
Address
: 10;
2643
uint32_t : 21;
2644
uint32_t
VALID
: 1;
2645
};
2646
2648
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_s
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_t
;
2649
#endif
/* __ASSEMBLY__ */
2650
2652
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_RESET 0x00000000
2653
2654
#define ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_OFST 0x90
2655
2656
#ifndef __ASSEMBLY__
2657
2667
struct
ALT_ECC_EMAC2_TX_ECC_s
2668
{
2669
volatile
ALT_ECC_EMAC2_TX_ECC_IP_REV_ID_t
IP_REV_ID
;
2670
volatile
uint32_t
_pad_0x4_0x7
;
2671
volatile
ALT_ECC_EMAC2_TX_ECC_CTL_t
CTRL
;
2672
volatile
ALT_ECC_EMAC2_TX_ECC_INITSTAT_t
INITSTAT
;
2673
volatile
ALT_ECC_EMAC2_TX_ECC_ERRINTEN_t
ERRINTEN
;
2674
volatile
ALT_ECC_EMAC2_TX_ECC_ERRINTENS_t
ERRINTENS
;
2675
volatile
ALT_ECC_EMAC2_TX_ECC_ERRINTENR_t
ERRINTENR
;
2676
volatile
ALT_ECC_EMAC2_TX_ECC_INTMOD_t
INTMODE
;
2677
volatile
ALT_ECC_EMAC2_TX_ECC_INTSTAT_t
INTSTAT
;
2678
volatile
ALT_ECC_EMAC2_TX_ECC_INTTEST_t
INTTEST
;
2679
volatile
ALT_ECC_EMAC2_TX_ECC_MODSTAT_t
MODSTAT
;
2680
volatile
ALT_ECC_EMAC2_TX_ECC_DERRADDRA_t
DERRADDRA
;
2681
volatile
ALT_ECC_EMAC2_TX_ECC_SERRADDRA_t
SERRADDRA
;
2682
volatile
uint32_t
_pad_0x34_0x3b
[2];
2683
volatile
ALT_ECC_EMAC2_TX_ECC_SERRCNTREG_t
SERRCNTREG
;
2684
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_ADDRBUS_t
ECC_Addrbus
;
2685
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA0BUS_t
ECC_RData0bus
;
2686
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA1BUS_t
ECC_RData1bus
;
2687
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA2BUS_t
ECC_RData2bus
;
2688
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATA3BUS_t
ECC_RData3bus
;
2689
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA0BUS_t
ECC_WData0bus
;
2690
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA1BUS_t
ECC_WData1bus
;
2691
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA2BUS_t
ECC_WData2bus
;
2692
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATA3BUS_t
ECC_WData3bus
;
2693
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC0BUS_t
ECC_RDataecc0bus
;
2694
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_RDATAECC1BUS_t
ECC_RDataecc1bus
;
2695
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC0BUS_t
ECC_WDataecc0bus
;
2696
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDATAECC1BUS_t
ECC_WDataecc1bus
;
2697
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_DBYTECTL_t
ECC_dbytectrl
;
2698
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_ACCCTL_t
ECC_accctrl
;
2699
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_STARTACC_t
ECC_startacc
;
2700
volatile
ALT_ECC_EMAC2_TX_ECC_ECC_WDCTL_t
ECC_wdctrl
;
2701
volatile
uint32_t
_pad_0x84_0x8f
[3];
2702
volatile
ALT_ECC_EMAC2_TX_ECC_SERRLKUPA0_t
SERRLKUPA0
;
2703
volatile
uint32_t
_pad_0x94_0x400
[219];
2704
};
2705
2707
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_s
ALT_ECC_EMAC2_TX_ECC_t
;
2709
struct
ALT_ECC_EMAC2_TX_ECC_raw_s
2710
{
2711
volatile
uint32_t
IP_REV_ID
;
2712
volatile
uint32_t
_pad_0x4_0x7
;
2713
volatile
uint32_t
CTRL
;
2714
volatile
uint32_t
INITSTAT
;
2715
volatile
uint32_t
ERRINTEN
;
2716
volatile
uint32_t
ERRINTENS
;
2717
volatile
uint32_t
ERRINTENR
;
2718
volatile
uint32_t
INTMODE
;
2719
volatile
uint32_t
INTSTAT
;
2720
volatile
uint32_t
INTTEST
;
2721
volatile
uint32_t
MODSTAT
;
2722
volatile
uint32_t
DERRADDRA
;
2723
volatile
uint32_t
SERRADDRA
;
2724
volatile
uint32_t
_pad_0x34_0x3b
[2];
2725
volatile
uint32_t
SERRCNTREG
;
2726
volatile
uint32_t
ECC_Addrbus
;
2727
volatile
uint32_t
ECC_RData0bus
;
2728
volatile
uint32_t
ECC_RData1bus
;
2729
volatile
uint32_t
ECC_RData2bus
;
2730
volatile
uint32_t
ECC_RData3bus
;
2731
volatile
uint32_t
ECC_WData0bus
;
2732
volatile
uint32_t
ECC_WData1bus
;
2733
volatile
uint32_t
ECC_WData2bus
;
2734
volatile
uint32_t
ECC_WData3bus
;
2735
volatile
uint32_t
ECC_RDataecc0bus
;
2736
volatile
uint32_t
ECC_RDataecc1bus
;
2737
volatile
uint32_t
ECC_WDataecc0bus
;
2738
volatile
uint32_t
ECC_WDataecc1bus
;
2739
volatile
uint32_t
ECC_dbytectrl
;
2740
volatile
uint32_t
ECC_accctrl
;
2741
volatile
uint32_t
ECC_startacc
;
2742
volatile
uint32_t
ECC_wdctrl
;
2743
volatile
uint32_t
_pad_0x84_0x8f
[3];
2744
volatile
uint32_t
SERRLKUPA0
;
2745
volatile
uint32_t
_pad_0x94_0x400
[219];
2746
};
2747
2749
typedef
volatile
struct
ALT_ECC_EMAC2_TX_ECC_raw_s
ALT_ECC_EMAC2_TX_ECC_raw_t
;
2750
#endif
/* __ASSEMBLY__ */
2751
2753
#ifdef __cplusplus
2754
}
2755
#endif
/* __cplusplus */
2756
#endif
/* __ALT_SOCAL_ECC_EMAC2_TX_ECC_H__ */
2757
include
soc_a10
socal
alt_ecc_emac2_tx_ecc.h
Generated on Tue Sep 8 2015 13:32:55 for Altera SoCAL by
1.8.2