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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
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[4:0] | RW | 0x0 | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR |
[31:5] | ??? | Unknown | UNDEFINED |
Field : TRACEALARMCLR | |
Setting a bit to 1 in register TraceAlarmClr clears the corresponding bit in register TraceAlarmStatus.The number of bits in register TraceAlarmClr is equal to (nFilter + 1). When nFilter is set to 0, TraceAlarmClr is reserved.NOTE The written value is not stored in TraceAlarmClr. A read always returns 0. Field Access Macros: | |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_LSB 0 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_MSB 4 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_GET(value) (((value) & 0x0000001f) >> 0) |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET(value) (((value) << 0) & 0x0000001f) |
Data Structures | |
struct | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s |
Macros | |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_RESET 0x00000000 |
#define | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_OFST 0x20 |
Typedefs | |
typedef struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_t |
struct ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR.
Data Fields | ||
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uint32_t | TRACEALARMCLR: 5 | ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR |
uint32_t | __pad0__: 27 | UNDEFINED |
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_WIDTH 5 |
The width in bits of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET_MSK 0x0000001f |
The mask used to set the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_CLR_MSK 0xffffffe0 |
The mask used to clear the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_RESET 0x0 |
The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_GET | ( | value | ) | (((value) & 0x0000001f) >> 0) |
Extracts the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR field value from a register.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR_SET | ( | value | ) | (((value) << 0) & 0x0000001f) |
Produces a ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_TRACEALARMCLR register field value suitable for setting the register.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_RESET 0x00000000 |
The reset value of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR register.
#define ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR_OFST 0x20 |
The byte offset of the ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR register from the beginning of the component.
The typedef declaration for register ALT_NOC_MPU_DDR_T_PRB_TRACEALARMCLR.