Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ic_tx_abrt_source

Description

Name: I2C Transmit Abort Source Register

Size: 32 bits

Address Offset: 0x80

Read/Write Access: Read

This register has 32 bits that indicate the source

of the TX_ABRT bit. Except for Bit 9, this register is

cleared whenever the IC_CLR_TX_ABRT register or the

IC_CLR_INTR register is read. To clear Bit 9, the source

of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must

be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared

(IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).

Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this

bit can be cleared in the same manner as other bits in this

register. If the source of the ABRT_SBYTE_NORSTRT is not fixed

before attempting to clear this bit, Bit 9 clears for one cycle

and is then re-asserted.

Register Layout

Bits Access Reset Description
[0] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK
[1] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK
[2] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK
[3] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK
[4] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK
[5] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD
[6] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET
[7] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET
[8] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT
[9] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT
[10] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT
[11] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS
[12] R 0x0 ALT_I2C_TX_ABRT_SRC_ARB_LOST
[13] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO
[14] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST
[15] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX
[16] R 0x0 ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT
[22:17] R 0x0 ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17
[31:23] R 0x0 ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT

Field : abrt_7b_addr_noack

1: Master is in 7-bit addressing mode

and the address sent was not

acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB   0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB   0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK   0x00000001
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK   0xfffffffe
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET(value)   (((value) << 0) & 0x00000001)
 

Field : abrt_10addr1_noack

1: Master is in 10-bit address mode and

the first 10-bit address byte was not

acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK   0x00000002
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK   0xfffffffd
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET(value)   (((value) << 1) & 0x00000002)
 

Field : abrt_10addr2_noack

1: Master is in 10-bit address mode and

the second address byte of the 10-bit

address was not acknowledged by any slave.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB   2
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB   2
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK   0x00000004
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK   0xfffffffb
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET(value)   (((value) << 2) & 0x00000004)
 

Field : abrt_txdata_noack

1: This is a master-mode only bit.

Master has received an

acknowledgement for the address, but

when it sent data byte(s) following the

address, it did not receive an

acknowledge from the remote slave(s).

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB   3
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB   3
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK   0x00000008
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK   0xfffffff7
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET(value)   (((value) << 3) & 0x00000008)
 

Field : abrt_gcall_noack

1: DW_apb_i2c in master mode sent a

General Call and no slave on the bus

acknowledged the General Call.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB   4
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB   4
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK   0x00000010
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK   0xffffffef
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET(value)   (((value) << 4) & 0x00000010)
 

Field : abrt_gcall_read

1: DW_apb_i2c in master mode sent a

General Call but the user programmed

the byte following the General Call to

be a read from the bus

(IC_DATA_CMD[9] is set to 1).

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB   5
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB   5
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK   0x00000020
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK   0xffffffdf
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET(value)   (((value) << 5) & 0x00000020)
 

Field : abrt_hs_ackdet

1: Master is in High Speed mode and

the High Speed Master code was

acknowledged (wrong behavior).

Reset value: 0x0

Role of DW_apb_i2c: Master

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB   6
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB   6
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK   0x00000040
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK   0xffffffbf
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET(value)   (((value) << 6) & 0x00000040)
 

Field : abrt_sbyte_ackdet

1: Master has sent a START Byte and

the START Byte was acknowledged (wrong behavior).

Reset value: 0x0

Role of DW_apb_i2c: Master

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB   7
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB   7
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK   0x00000080
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK   0xffffff7f
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET(value)   (((value) << 7) & 0x00000080)
 

Field : abrt_hs_norstrt

1: The restart is disabled

(IC_RESTART_EN bit (IC_CON[5]) =0)

and the user is trying to use the

master to transfer data in High Speed

mode.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB   8
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB   8
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK   0x00000100
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK   0xfffffeff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET(value)   (((value) << 8) & 0x00000100)
 

Field : abrt_sbyte_norstrt

To clear Bit 9, the source of the

ABRT_SBYTE_NORSTRT must be fixed first;

restart must be enabled (IC_CON[5]=1),

the SPECIAL bit must be cleared (IC_TAR[11]),

or the GC_OR_START bit must be cleared

(IC_TAR[10]). Once the source of the

ABRT_SBYTE_NORSTRT is fixed,

then this bit can be cleared in the same

manner as other bits in this register. If

the source of the ABRT_SBYTE_NORSTRT is not fixed

before attempting to clear this bit, bit 9

clears for one cycle and then gets reasserted.

1: The restart is disabled (IC_RESTART_EN bit

(IC_CON[5]) =0) and the user is trying to

send a START Byte.

Reset value: 0x0

Role of DW_apb_i2c: Master

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB   9
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB   9
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK   0x00000200
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK   0xfffffdff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET(value)   (((value) << 9) & 0x00000200)
 

Field : abrt_10b_rd_norstrt

1: The restart is disabled

(IC_RESTART_EN bit (IC_CON[5]) =0)

and the master sends a read

command in 10-bit addressing mode.

Reset value: 0x0

Role of DW_apb_i2c: Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB   10
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB   10
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK   0x00000400
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK   0xfffffbff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET(value)   (((value) << 10) & 0x00000400)
 

Field : abrt_master_dis

1: User tries to initiate a Master

operation with the Master mode disabled.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Master-Receiver

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB   11
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB   11
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK   0x00000800
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK   0xfffff7ff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET(value)   (((value) << 11) & 0x00000800)
 

Field : arb_lost

1: Master has lost arbitration, or if

IC_TX_ABRT_SOURCE[14] is also

set, then the slave transmitter has lost

arbitration.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

or Slave-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB   12
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB   12
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK   0x00001000
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK   0xffffefff
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET(value)   (((value) << 12) & 0x00001000)
 

Field : abrt_slvflush_txfifo

1: Slave has received a read command

and some data exists in the TX FIFO so

the slave issues a TX_ABRT interrupt to

flush old data in TX FIFO.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB   13
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB   13
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK   0x00002000
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK   0xffffdfff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET(value)   (((value) << 13) & 0x00002000)
 

Field : abrt_slv_arblost

1: Slave lost the bus while transmitting

data to a remote master.

IC_TX_ABRT_SOURCE[12] is set at

the same time.

Note: Even though the slave never

'owns' the bus, something could go

wrong on the bus. This is a fail safe

check. For instance, during a data

transmission at the low-to-high

transition of SCL, if what is on the data

bus is not what is supposed to be

transmitted, then DW_apb_i2c no

longer own the bus.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB   14
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB   14
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK   0x00004000
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK   0xffffbfff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET(value)   (((value) << 14) & 0x00004000)
 

Field : abrt_slvrd_intx

1: When the processor side responds to

a slave mode request for data to be

transmitted to a remote master and user

writes a 1 in CMD (bit 8) of

IC_DATA_CMD register.

Reset value: 0x0

Role of DW_apb_i2c: Slave-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB   15
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB   15
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK   0x00008000
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK   0xffff7fff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET(value)   (((value) << 15) & 0x00008000)
 

Field : abrt_user_abrt

This is a master-mode-only bit. Master has

detected the transfer abort (IC_ENABLE[1])

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_LSB   16
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_MSB   16
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_WIDTH   1
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET_MSK   0x00010000
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_CLR_MSK   0xfffeffff
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET(value)   (((value) << 16) & 0x00010000)
 

Field : rsvd_ic_tx_abrt_source_22to17

Reserved

Reset value: 0x0

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_LSB   17
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_MSB   22
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_WIDTH   6
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET_MSK   0x007e0000
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_CLR_MSK   0xff81ffff
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_GET(value)   (((value) & 0x007e0000) >> 17)
 
#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET(value)   (((value) << 17) & 0x007e0000)
 

Field : tx_flush_cnt

This field indicates the

number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt.

It is cleared whenever I2C is disabled.

Reset value: 0x0

Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter

Field Access Macros:

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_LSB   23
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_MSB   31
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_WIDTH   9
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET_MSK   0xff800000
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_CLR_MSK   0x007fffff
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_RESET   0x0
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_GET(value)   (((value) & 0xff800000) >> 23)
 
#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET(value)   (((value) << 23) & 0xff800000)
 

Data Structures

struct  ALT_I2C_TX_ABRT_SRC_s
 

Macros

#define ALT_I2C_TX_ABRT_SRC_RESET   0x00000000
 
#define ALT_I2C_TX_ABRT_SRC_OFST   0x80
 
#define ALT_I2C_TX_ABRT_SRC_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))
 

Typedefs

typedef struct
ALT_I2C_TX_ABRT_SRC_s 
ALT_I2C_TX_ABRT_SRC_t
 

Data Structure Documentation

struct ALT_I2C_TX_ABRT_SRC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_I2C_TX_ABRT_SRC.

Data Fields
const uint32_t abrt_7b_addr_noack: 1 ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK
const uint32_t abrt_10addr1_noack: 1 ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK
const uint32_t abrt_10addr2_noack: 1 ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK
const uint32_t abrt_txdata_noack: 1 ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK
const uint32_t abrt_gcall_noack: 1 ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK
const uint32_t abrt_gcall_read: 1 ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD
const uint32_t abrt_hs_ackdet: 1 ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET
const uint32_t abrt_sbyte_ackdet: 1 ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET
const uint32_t abrt_hs_norstrt: 1 ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT
const uint32_t abrt_sbyte_norstrt: 1 ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT
const uint32_t abrt_10b_rd_norstrt: 1 ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT
const uint32_t abrt_master_dis: 1 ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS
const uint32_t arb_lost: 1 ALT_I2C_TX_ABRT_SRC_ARB_LOST
const uint32_t abrt_slvflush_txfifo: 1 ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO
const uint32_t abrt_slv_arblost: 1 ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST
const uint32_t abrt_slvrd_intx: 1 ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX
const uint32_t abrt_user_abrt: 1 ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT
const uint32_t rsvd_ic_tx_abrt_source_22to17: 6 ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17
const uint32_t tx_flush_cnt: 9 ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT

Macro Definitions

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_LSB   0

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_MSB   0

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET_MSK   0x00000001

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_CLR_MSK   0xfffffffe

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_7B_ADDR_NOACK register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_LSB   1

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_MSB   1

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET_MSK   0x00000002

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_CLR_MSK   0xfffffffd

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR1_NOACK register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_LSB   2

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_MSB   2

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET_MSK   0x00000004

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_CLR_MSK   0xfffffffb

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10ADDR2_NOACK register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_LSB   3

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_MSB   3

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET_MSK   0x00000008

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_CLR_MSK   0xfffffff7

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_TXDATA_NOACK register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_LSB   4

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_MSB   4

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET_MSK   0x00000010

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_CLR_MSK   0xffffffef

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_NOACK register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_LSB   5

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_MSB   5

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET_MSK   0x00000020

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_CLR_MSK   0xffffffdf

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_GCALL_RD register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_LSB   6

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_MSB   6

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET_MSK   0x00000040

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_CLR_MSK   0xffffffbf

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_ACKDET register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_LSB   7

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_MSB   7

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET_MSK   0x00000080

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_CLR_MSK   0xffffff7f

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_ACKDET register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_LSB   8

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_MSB   8

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET_MSK   0x00000100

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_CLR_MSK   0xfffffeff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_HS_NORSTRT register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_LSB   9

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_MSB   9

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET_MSK   0x00000200

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_CLR_MSK   0xfffffdff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SBYTE_NORSTRT register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_LSB   10

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_MSB   10

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET_MSK   0x00000400

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_CLR_MSK   0xfffffbff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_10B_RD_NORSTRT register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_LSB   11

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_MSB   11

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET_MSK   0x00000800

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_MST_DIS register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_LSB   12

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_MSB   12

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET_MSK   0x00001000

The mask used to set the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_CLR_MSK   0xffffefff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ARB_LOST register field.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_I2C_TX_ABRT_SRC_ARB_LOST field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ARB_LOST_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_I2C_TX_ABRT_SRC_ARB_LOST register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_LSB   13

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_MSB   13

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET_MSK   0x00002000

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_CLR_MSK   0xffffdfff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVFLUSH_TXFIFO register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_LSB   14

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_MSB   14

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET_MSK   0x00004000

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_CLR_MSK   0xffffbfff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLV_ARBLOST register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_LSB   15

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_MSB   15

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET_MSK   0x00008000

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_CLR_MSK   0xffff7fff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_SLVRD_INTX register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_LSB   16

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_MSB   16

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_WIDTH   1

The width in bits of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET_MSK   0x00010000

The mask used to set the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_CLR_MSK   0xfffeffff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT field value from a register.

#define ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_I2C_TX_ABRT_SRC_ABRT_USER_ABRT register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_LSB   17

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_MSB   22

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_WIDTH   6

The width in bits of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET_MSK   0x007e0000

The mask used to set the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_CLR_MSK   0xff81ffff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_GET (   value)    (((value) & 0x007e0000) >> 17)

Extracts the ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 field value from a register.

#define ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17_SET (   value)    (((value) << 17) & 0x007e0000)

Produces a ALT_I2C_TX_ABRT_SRC_RSVD_IC_TX_ABRT_SRC_22TO17 register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_LSB   23

The Least Significant Bit (LSB) position of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_MSB   31

The Most Significant Bit (MSB) position of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_WIDTH   9

The width in bits of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET_MSK   0xff800000

The mask used to set the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_CLR_MSK   0x007fffff

The mask used to clear the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_RESET   0x0

The reset value of the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_GET (   value)    (((value) & 0xff800000) >> 23)

Extracts the ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT field value from a register.

#define ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT_SET (   value)    (((value) << 23) & 0xff800000)

Produces a ALT_I2C_TX_ABRT_SRC_TX_FLUSH_CNT register field value suitable for setting the register.

#define ALT_I2C_TX_ABRT_SRC_RESET   0x00000000

The reset value of the ALT_I2C_TX_ABRT_SRC register.

#define ALT_I2C_TX_ABRT_SRC_OFST   0x80

The byte offset of the ALT_I2C_TX_ABRT_SRC register from the beginning of the component.

#define ALT_I2C_TX_ABRT_SRC_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_TX_ABRT_SRC_OFST))

The address of the ALT_I2C_TX_ABRT_SRC register.

Typedef Documentation

The typedef declaration for register ALT_I2C_TX_ABRT_SRC.