Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ddr_T_main_Scheduler_Activate

Description

timing values concerning Activate commands, in Generic clock unit.

Register Layout

Bits Access Reset Description
[3:0] RW 0x2 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD
[9:4] RW 0xd ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW
[10] RW 0x1 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK
[31:11] ??? Unknown UNDEFINED

Field : RRD

Number of cycle between two consecutive Activate commands on different Banks of the same device.

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB   0
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_MSB   3
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_WIDTH   4
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET_MSK   0x0000000f
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_CLR_MSK   0xfffffff0
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_RESET   0x2
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : FAW

Number of cycle of the FAW period.

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB   4
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_MSB   9
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_WIDTH   6
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET_MSK   0x000003f0
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_CLR_MSK   0xfffffc0f
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_RESET   0xd
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_GET(value)   (((value) & 0x000003f0) >> 4)
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET(value)   (((value) << 4) & 0x000003f0)
 

Field : FAWBANK

Number of Bank of a given device involved in the FAW period.

Field Access Macros:

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB   10
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_MSB   10
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_WIDTH   1
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET_MSK   0x00000400
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_CLR_MSK   0xfffffbff
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_RESET   0x1
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET(value)   (((value) << 10) & 0x00000400)
 

Data Structures

struct  ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s
 

Macros

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RESET   0x000004d2
 
#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_OFST   0x38
 

Typedefs

typedef struct
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s 
ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_t
 

Data Structure Documentation

struct ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE.

Data Fields
uint32_t RRD: 4 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD
uint32_t FAW: 6 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW
uint32_t FAWBANK: 1 ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK
uint32_t __pad0__: 21 UNDEFINED

Macro Definitions

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_MSB   3

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_WIDTH   4

The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET_MSK   0x0000000f

The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_CLR_MSK   0xfffffff0

The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_RESET   0x2

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD field value from a register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RRD register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_LSB   4

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_MSB   9

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_WIDTH   6

The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET_MSK   0x000003f0

The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_CLR_MSK   0xfffffc0f

The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_RESET   0xd

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_GET (   value)    (((value) & 0x000003f0) >> 4)

Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW field value from a register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW_SET (   value)    (((value) << 4) & 0x000003f0)

Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAW register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_LSB   10

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_MSB   10

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_WIDTH   1

The width in bits of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET_MSK   0x00000400

The mask used to set the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_CLR_MSK   0xfffffbff

The mask used to clear the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_RESET   0x1

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK field value from a register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_FAWBANK register field value suitable for setting the register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_RESET   0x000004d2

The reset value of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE register.

#define ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE_OFST   0x38

The byte offset of the ALT_NOC_MPU_DDR_T_SCHED_ACTIVATE register from the beginning of the component.

Typedef Documentation