Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 7 (Interrupt Enable Register) - Interrupt_Enable

Description

The Interrupt Enable register enables the interrupts reported by Register 5 (Status Register). Setting a bit to 1'b1 enables a corresponding interrupt. After a hardware or software reset, all interrupts are disabled.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Transmit Interrupt Enable
[1] RW 0x0 Transmit Stopped Enable
[2] RW 0x0 Transmit Buffer Unvailable Enable
[3] RW 0x0 Transmit Jabber Timeout Enable
[4] RW 0x0 Overflow Interrupt Enable
[5] RW 0x0 Underflow Interrupt Enable
[6] RW 0x0 Receive Interrupt Enable
[7] RW 0x0 Receive Buffer Unavailable Enable
[8] RW 0x0 Receive Stopped Enable
[9] RW 0x0 Receive Watchdog Timeout Enable
[10] RW 0x0 Early Transmit Interrupt Enable
[12:11] ??? 0x0 UNDEFINED
[13] RW 0x0 Fatal Bus Error Enable
[14] RW 0x0 Early Receive Interrupt Enable
[15] RW 0x0 Abnormal Interrupt Summary Enable
[16] RW 0x0 Normal Interrupt Summary Enable
[31:17] ??? 0x0 UNDEFINED

Field : Transmit Interrupt Enable - tie

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Interrupt is enabled. When this bit is reset, the Transmit Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_TIE_E_DISD 0x0 Transmit Interrupt Disabled
ALT_EMAC_DMA_INT_EN_TIE_E_END 0x1 Transmit Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_TIE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_TIE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_TIE_LSB   0
 
#define ALT_EMAC_DMA_INT_EN_TIE_MSB   0
 
#define ALT_EMAC_DMA_INT_EN_TIE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_INT_EN_TIE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_TIE_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_INT_EN_TIE_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Transmit Stopped Enable - tse

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmission Stopped Interrupt is enabled. When this bit is reset, the Transmission Stopped Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_TSE_E_DISD 0x0 Transmit Stopped Interrupt Disabled
ALT_EMAC_DMA_INT_EN_TSE_E_END 0x1 Transmit Stopped Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_TSE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_TSE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_TSE_LSB   1
 
#define ALT_EMAC_DMA_INT_EN_TSE_MSB   1
 
#define ALT_EMAC_DMA_INT_EN_TSE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK   0x00000002
 
#define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_DMA_INT_EN_TSE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_TSE_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_DMA_INT_EN_TSE_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Transmit Buffer Unvailable Enable - tue

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Transmit Buffer Unavailable Interrupt is enabled. When this bit is reset, the Transmit Buffer Unavailable Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_TUE_E_DISD 0x0 Transmit Buffer Unavailable Interrupt Disabled
ALT_EMAC_DMA_INT_EN_TUE_E_END 0x1 Transmit Buffer Unavailable Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_TUE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_TUE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_TUE_LSB   2
 
#define ALT_EMAC_DMA_INT_EN_TUE_MSB   2
 
#define ALT_EMAC_DMA_INT_EN_TUE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK   0x00000004
 
#define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_DMA_INT_EN_TUE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_TUE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_DMA_INT_EN_TUE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Transmit Jabber Timeout Enable - tje

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Jabber Timeout Interrupt is enabled. When this bit is reset, the Transmit Jabber Timeout Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_TJE_E_DISD 0x0 Transmit Jabber Timeout Interrupt Disabled
ALT_EMAC_DMA_INT_EN_TJE_E_END 0x1 Transmit Jabber Timeout Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_TJE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_TJE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_TJE_LSB   3
 
#define ALT_EMAC_DMA_INT_EN_TJE_MSB   3
 
#define ALT_EMAC_DMA_INT_EN_TJE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK   0x00000008
 
#define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_DMA_INT_EN_TJE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_TJE_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_DMA_INT_EN_TJE_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Overflow Interrupt Enable - ove

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Overflow Interrupt is enabled. When this bit is reset, the Overflow Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_OVE_E_DISD 0x0 Transmit Overflow Interrupt Disabled
ALT_EMAC_DMA_INT_EN_OVE_E_END 0x1 Transmit Overflow Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_OVE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_OVE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_OVE_LSB   4
 
#define ALT_EMAC_DMA_INT_EN_OVE_MSB   4
 
#define ALT_EMAC_DMA_INT_EN_OVE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK   0x00000010
 
#define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK   0xffffffef
 
#define ALT_EMAC_DMA_INT_EN_OVE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_OVE_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_DMA_INT_EN_OVE_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Underflow Interrupt Enable - une

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Transmit Underflow Interrupt is enabled. When this bit is reset, the Underflow Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_UNE_E_DISD 0x0 Underflow Interrupt Disabled
ALT_EMAC_DMA_INT_EN_UNE_E_END 0x1 Underflow Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_UNE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_UNE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_UNE_LSB   5
 
#define ALT_EMAC_DMA_INT_EN_UNE_MSB   5
 
#define ALT_EMAC_DMA_INT_EN_UNE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK   0x00000020
 
#define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_DMA_INT_EN_UNE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_UNE_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_DMA_INT_EN_UNE_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Receive Interrupt Enable - rie

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Receive Interrupt is enabled. When this bit is reset, the Receive Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_RIE_E_DISD 0x0 Receive Interrupt Disabled
ALT_EMAC_DMA_INT_EN_RIE_E_END 0x1 Receive Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_RIE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_RIE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_RIE_LSB   6
 
#define ALT_EMAC_DMA_INT_EN_RIE_MSB   6
 
#define ALT_EMAC_DMA_INT_EN_RIE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK   0x00000040
 
#define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_DMA_INT_EN_RIE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_RIE_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_DMA_INT_EN_RIE_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Receive Buffer Unavailable Enable - rue

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Buffer Unavailable Interrupt is enabled. When this bit is reset, the Receive Buffer Unavailable Interrupt is disabled.

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_RUE_LSB   7
 
#define ALT_EMAC_DMA_INT_EN_RUE_MSB   7
 
#define ALT_EMAC_DMA_INT_EN_RUE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK   0x00000080
 
#define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_DMA_INT_EN_RUE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_RUE_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_DMA_INT_EN_RUE_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Receive Stopped Enable - rse

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Stopped Interrupt is enabled. When this bit is reset, the Receive Stopped Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_RSE_E_DISD 0x0 Receive Stopped Interrupt Disabled
ALT_EMAC_DMA_INT_EN_RSE_E_END 0x1 Receive Stopped Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_RSE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_RSE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_RSE_LSB   8
 
#define ALT_EMAC_DMA_INT_EN_RSE_MSB   8
 
#define ALT_EMAC_DMA_INT_EN_RSE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK   0x00000100
 
#define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_DMA_INT_EN_RSE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_RSE_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_DMA_INT_EN_RSE_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Receive Watchdog Timeout Enable - rwe

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Receive Watchdog Timeout Interrupt is enabled. When this bit is reset, the Receive Watchdog Timeout Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_RWE_E_DISD 0x0 Receive Watchdog Timeout Interrupt Disabled
ALT_EMAC_DMA_INT_EN_RWE_E_END 0x1 Receive Watchdog Timeout Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_RWE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_RWE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_RWE_LSB   9
 
#define ALT_EMAC_DMA_INT_EN_RWE_MSB   9
 
#define ALT_EMAC_DMA_INT_EN_RWE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK   0x00000200
 
#define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_DMA_INT_EN_RWE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_RWE_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_DMA_INT_EN_RWE_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Early Transmit Interrupt Enable - ete

When this bit is set with an Abnormal Interrupt Summary Enable (Bit 15), the Early Transmit Interrupt is enabled. When this bit is reset, the Early Transmit Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_ETE_E_DISD 0x0 Early Transmit Interrupt Disabled
ALT_EMAC_DMA_INT_EN_ETE_E_END 0x1 Early Transmit Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_ETE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_ETE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_ETE_LSB   10
 
#define ALT_EMAC_DMA_INT_EN_ETE_MSB   10
 
#define ALT_EMAC_DMA_INT_EN_ETE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK   0x00000400
 
#define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_DMA_INT_EN_ETE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_ETE_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_DMA_INT_EN_ETE_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Fatal Bus Error Enable - fbe

When this bit is set with Abnormal Interrupt Summary Enable (Bit 15), the Fatal Bus Error Interrupt is enabled. When this bit is reset, the Fatal Bus Error Enable Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_FBE_E_DISD 0x0 Fatal Bus Error Interrupt Disabled
ALT_EMAC_DMA_INT_EN_FBE_E_END 0x1 Fatal Bus Error Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_FBE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_FBE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_FBE_LSB   13
 
#define ALT_EMAC_DMA_INT_EN_FBE_MSB   13
 
#define ALT_EMAC_DMA_INT_EN_FBE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK   0x00002000
 
#define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_DMA_INT_EN_FBE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_FBE_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_DMA_INT_EN_FBE_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Early Receive Interrupt Enable - ere

When this bit is set with Normal Interrupt Summary Enable (Bit 16), the Early Receive Interrupt is enabled. When this bit is reset, the Early Receive Interrupt is disabled.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_ERE_E_DISD 0x0 Early Receive Interrupt Disabled
ALT_EMAC_DMA_INT_EN_ERE_E_END 0x1 Early Receive Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_ERE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_ERE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_ERE_LSB   14
 
#define ALT_EMAC_DMA_INT_EN_ERE_MSB   14
 
#define ALT_EMAC_DMA_INT_EN_ERE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK   0x00004000
 
#define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_DMA_INT_EN_ERE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_ERE_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_DMA_INT_EN_ERE_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Abnormal Interrupt Summary Enable - aie

When this bit is set, abnormal interrupt summary is enabled. When this bit is reset, the abnormal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register):

  • Register 5[1]: Transmit Process Stopped
  • Register 5[3]: Transmit Jabber Timeout
  • Register 5[4]: Receive Overflow
  • Register 5[5]: Transmit Underflow
  • Register 5[7]: Receive Buffer Unavailable
  • Register 5[8]: Receive Process Stopped
  • Register 5[9]: Receive Watchdog Timeout
  • Register 5[10]: Early Transmit Interrupt
  • Register 5[13]: Fatal Bus Error

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_AIE_E_DISD 0x0 Abnormal Interrupt Summary Interrupt Disabled
ALT_EMAC_DMA_INT_EN_AIE_E_END 0x1 Abnormal Interrupt Summary Interrupt Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_AIE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_AIE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_AIE_LSB   15
 
#define ALT_EMAC_DMA_INT_EN_AIE_MSB   15
 
#define ALT_EMAC_DMA_INT_EN_AIE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK   0x00008000
 
#define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_DMA_INT_EN_AIE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_AIE_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_DMA_INT_EN_AIE_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Normal Interrupt Summary Enable - nie

When this bit is set, normal interrupt summary is enabled. When this bit is reset, normal interrupt summary is disabled. This bit enables the following interrupts in Register 5 (Status Register):

  • Register 5[0]: Transmit Interrupt
  • Register 5[2]: Transmit Buffer Unavailable
  • Register 5[6]: Receive Interrupt
  • Register 5[14]: Early Receive Interrupt

Field Enumeration Values:

Enum Value Description
ALT_EMAC_DMA_INT_EN_NIE_E_DISD 0x0 Normal Interrupt Summary Disabled
ALT_EMAC_DMA_INT_EN_NIE_E_END 0x1 Normal Interrupt Summary Enabled

Field Access Macros:

#define ALT_EMAC_DMA_INT_EN_NIE_E_DISD   0x0
 
#define ALT_EMAC_DMA_INT_EN_NIE_E_END   0x1
 
#define ALT_EMAC_DMA_INT_EN_NIE_LSB   16
 
#define ALT_EMAC_DMA_INT_EN_NIE_MSB   16
 
#define ALT_EMAC_DMA_INT_EN_NIE_WIDTH   1
 
#define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK   0x00010000
 
#define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_DMA_INT_EN_NIE_RESET   0x0
 
#define ALT_EMAC_DMA_INT_EN_NIE_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_DMA_INT_EN_NIE_SET(value)   (((value) << 16) & 0x00010000)
 

Data Structures

struct  ALT_EMAC_DMA_INT_EN_s
 

Macros

#define ALT_EMAC_DMA_INT_EN_OFST   0x1c
 
#define ALT_EMAC_DMA_INT_EN_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_INT_EN_s 
ALT_EMAC_DMA_INT_EN_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_INT_EN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_INT_EN.

Data Fields
uint32_t tie: 1 Transmit Interrupt Enable
uint32_t tse: 1 Transmit Stopped Enable
uint32_t tue: 1 Transmit Buffer Unvailable Enable
uint32_t tje: 1 Transmit Jabber Timeout Enable
uint32_t ove: 1 Overflow Interrupt Enable
uint32_t une: 1 Underflow Interrupt Enable
uint32_t rie: 1 Receive Interrupt Enable
uint32_t rue: 1 Receive Buffer Unavailable Enable
uint32_t rse: 1 Receive Stopped Enable
uint32_t rwe: 1 Receive Watchdog Timeout Enable
uint32_t ete: 1 Early Transmit Interrupt Enable
uint32_t __pad0__: 2 UNDEFINED
uint32_t fbe: 1 Fatal Bus Error Enable
uint32_t ere: 1 Early Receive Interrupt Enable
uint32_t aie: 1 Abnormal Interrupt Summary Enable
uint32_t nie: 1 Normal Interrupt Summary Enable
uint32_t __pad1__: 15 UNDEFINED

Macro Definitions

#define ALT_EMAC_DMA_INT_EN_TIE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE

Transmit Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_TIE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TIE

Transmit Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_TIE_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field.

#define ALT_EMAC_DMA_INT_EN_TIE_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TIE register field.

#define ALT_EMAC_DMA_INT_EN_TIE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_TIE register field.

#define ALT_EMAC_DMA_INT_EN_TIE_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_INT_EN_TIE register field value.

#define ALT_EMAC_DMA_INT_EN_TIE_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_INT_EN_TIE register field value.

#define ALT_EMAC_DMA_INT_EN_TIE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_TIE register field.

#define ALT_EMAC_DMA_INT_EN_TIE_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_INT_EN_TIE field value from a register.

#define ALT_EMAC_DMA_INT_EN_TIE_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_INT_EN_TIE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_TSE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE

Transmit Stopped Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_TSE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TSE

Transmit Stopped Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_TSE_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field.

#define ALT_EMAC_DMA_INT_EN_TSE_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TSE register field.

#define ALT_EMAC_DMA_INT_EN_TSE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_TSE register field.

#define ALT_EMAC_DMA_INT_EN_TSE_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_DMA_INT_EN_TSE register field value.

#define ALT_EMAC_DMA_INT_EN_TSE_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_DMA_INT_EN_TSE register field value.

#define ALT_EMAC_DMA_INT_EN_TSE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_TSE register field.

#define ALT_EMAC_DMA_INT_EN_TSE_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_DMA_INT_EN_TSE field value from a register.

#define ALT_EMAC_DMA_INT_EN_TSE_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_DMA_INT_EN_TSE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_TUE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE

Transmit Buffer Unavailable Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_TUE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TUE

Transmit Buffer Unavailable Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_TUE_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field.

#define ALT_EMAC_DMA_INT_EN_TUE_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TUE register field.

#define ALT_EMAC_DMA_INT_EN_TUE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_TUE register field.

#define ALT_EMAC_DMA_INT_EN_TUE_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_DMA_INT_EN_TUE register field value.

#define ALT_EMAC_DMA_INT_EN_TUE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_DMA_INT_EN_TUE register field value.

#define ALT_EMAC_DMA_INT_EN_TUE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_TUE register field.

#define ALT_EMAC_DMA_INT_EN_TUE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_DMA_INT_EN_TUE field value from a register.

#define ALT_EMAC_DMA_INT_EN_TUE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_DMA_INT_EN_TUE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_TJE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE

Transmit Jabber Timeout Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_TJE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_TJE

Transmit Jabber Timeout Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_TJE_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field.

#define ALT_EMAC_DMA_INT_EN_TJE_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_TJE register field.

#define ALT_EMAC_DMA_INT_EN_TJE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_TJE register field.

#define ALT_EMAC_DMA_INT_EN_TJE_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_DMA_INT_EN_TJE register field value.

#define ALT_EMAC_DMA_INT_EN_TJE_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_DMA_INT_EN_TJE register field value.

#define ALT_EMAC_DMA_INT_EN_TJE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_TJE register field.

#define ALT_EMAC_DMA_INT_EN_TJE_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_DMA_INT_EN_TJE field value from a register.

#define ALT_EMAC_DMA_INT_EN_TJE_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_DMA_INT_EN_TJE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_OVE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE

Transmit Overflow Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_OVE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_OVE

Transmit Overflow Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_OVE_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field.

#define ALT_EMAC_DMA_INT_EN_OVE_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_OVE register field.

#define ALT_EMAC_DMA_INT_EN_OVE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_OVE register field.

#define ALT_EMAC_DMA_INT_EN_OVE_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_DMA_INT_EN_OVE register field value.

#define ALT_EMAC_DMA_INT_EN_OVE_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_DMA_INT_EN_OVE register field value.

#define ALT_EMAC_DMA_INT_EN_OVE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_OVE register field.

#define ALT_EMAC_DMA_INT_EN_OVE_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_DMA_INT_EN_OVE field value from a register.

#define ALT_EMAC_DMA_INT_EN_OVE_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_DMA_INT_EN_OVE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_UNE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE

Underflow Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_UNE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_UNE

Underflow Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_UNE_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field.

#define ALT_EMAC_DMA_INT_EN_UNE_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_UNE register field.

#define ALT_EMAC_DMA_INT_EN_UNE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_UNE register field.

#define ALT_EMAC_DMA_INT_EN_UNE_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_DMA_INT_EN_UNE register field value.

#define ALT_EMAC_DMA_INT_EN_UNE_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_DMA_INT_EN_UNE register field value.

#define ALT_EMAC_DMA_INT_EN_UNE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_UNE register field.

#define ALT_EMAC_DMA_INT_EN_UNE_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_DMA_INT_EN_UNE field value from a register.

#define ALT_EMAC_DMA_INT_EN_UNE_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_DMA_INT_EN_UNE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_RIE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE

Receive Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_RIE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RIE

Receive Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_RIE_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field.

#define ALT_EMAC_DMA_INT_EN_RIE_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RIE register field.

#define ALT_EMAC_DMA_INT_EN_RIE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_RIE register field.

#define ALT_EMAC_DMA_INT_EN_RIE_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_DMA_INT_EN_RIE register field value.

#define ALT_EMAC_DMA_INT_EN_RIE_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_DMA_INT_EN_RIE register field value.

#define ALT_EMAC_DMA_INT_EN_RIE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_RIE register field.

#define ALT_EMAC_DMA_INT_EN_RIE_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_DMA_INT_EN_RIE field value from a register.

#define ALT_EMAC_DMA_INT_EN_RIE_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_DMA_INT_EN_RIE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_RUE_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field.

#define ALT_EMAC_DMA_INT_EN_RUE_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RUE register field.

#define ALT_EMAC_DMA_INT_EN_RUE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_RUE register field.

#define ALT_EMAC_DMA_INT_EN_RUE_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_DMA_INT_EN_RUE register field value.

#define ALT_EMAC_DMA_INT_EN_RUE_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_DMA_INT_EN_RUE register field value.

#define ALT_EMAC_DMA_INT_EN_RUE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_RUE register field.

#define ALT_EMAC_DMA_INT_EN_RUE_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_DMA_INT_EN_RUE field value from a register.

#define ALT_EMAC_DMA_INT_EN_RUE_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_DMA_INT_EN_RUE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_RSE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE

Receive Stopped Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_RSE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RSE

Receive Stopped Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_RSE_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field.

#define ALT_EMAC_DMA_INT_EN_RSE_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RSE register field.

#define ALT_EMAC_DMA_INT_EN_RSE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_RSE register field.

#define ALT_EMAC_DMA_INT_EN_RSE_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_DMA_INT_EN_RSE register field value.

#define ALT_EMAC_DMA_INT_EN_RSE_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_DMA_INT_EN_RSE register field value.

#define ALT_EMAC_DMA_INT_EN_RSE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_RSE register field.

#define ALT_EMAC_DMA_INT_EN_RSE_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_DMA_INT_EN_RSE field value from a register.

#define ALT_EMAC_DMA_INT_EN_RSE_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_DMA_INT_EN_RSE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_RWE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE

Receive Watchdog Timeout Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_RWE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_RWE

Receive Watchdog Timeout Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_RWE_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field.

#define ALT_EMAC_DMA_INT_EN_RWE_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_RWE register field.

#define ALT_EMAC_DMA_INT_EN_RWE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_RWE register field.

#define ALT_EMAC_DMA_INT_EN_RWE_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_DMA_INT_EN_RWE register field value.

#define ALT_EMAC_DMA_INT_EN_RWE_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_DMA_INT_EN_RWE register field value.

#define ALT_EMAC_DMA_INT_EN_RWE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_RWE register field.

#define ALT_EMAC_DMA_INT_EN_RWE_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_DMA_INT_EN_RWE field value from a register.

#define ALT_EMAC_DMA_INT_EN_RWE_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_DMA_INT_EN_RWE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_ETE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE

Early Transmit Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_ETE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_ETE

Early Transmit Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_ETE_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field.

#define ALT_EMAC_DMA_INT_EN_ETE_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ETE register field.

#define ALT_EMAC_DMA_INT_EN_ETE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_ETE register field.

#define ALT_EMAC_DMA_INT_EN_ETE_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_DMA_INT_EN_ETE register field value.

#define ALT_EMAC_DMA_INT_EN_ETE_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_DMA_INT_EN_ETE register field value.

#define ALT_EMAC_DMA_INT_EN_ETE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_ETE register field.

#define ALT_EMAC_DMA_INT_EN_ETE_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_DMA_INT_EN_ETE field value from a register.

#define ALT_EMAC_DMA_INT_EN_ETE_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_DMA_INT_EN_ETE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_FBE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE

Fatal Bus Error Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_FBE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_FBE

Fatal Bus Error Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_FBE_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field.

#define ALT_EMAC_DMA_INT_EN_FBE_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_FBE register field.

#define ALT_EMAC_DMA_INT_EN_FBE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_FBE register field.

#define ALT_EMAC_DMA_INT_EN_FBE_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_DMA_INT_EN_FBE register field value.

#define ALT_EMAC_DMA_INT_EN_FBE_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_DMA_INT_EN_FBE register field value.

#define ALT_EMAC_DMA_INT_EN_FBE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_FBE register field.

#define ALT_EMAC_DMA_INT_EN_FBE_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_DMA_INT_EN_FBE field value from a register.

#define ALT_EMAC_DMA_INT_EN_FBE_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_DMA_INT_EN_FBE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_ERE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE

Early Receive Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_ERE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_ERE

Early Receive Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_ERE_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field.

#define ALT_EMAC_DMA_INT_EN_ERE_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_ERE register field.

#define ALT_EMAC_DMA_INT_EN_ERE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_ERE register field.

#define ALT_EMAC_DMA_INT_EN_ERE_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_DMA_INT_EN_ERE register field value.

#define ALT_EMAC_DMA_INT_EN_ERE_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_DMA_INT_EN_ERE register field value.

#define ALT_EMAC_DMA_INT_EN_ERE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_ERE register field.

#define ALT_EMAC_DMA_INT_EN_ERE_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_DMA_INT_EN_ERE field value from a register.

#define ALT_EMAC_DMA_INT_EN_ERE_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_DMA_INT_EN_ERE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_AIE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE

Abnormal Interrupt Summary Interrupt Disabled

#define ALT_EMAC_DMA_INT_EN_AIE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_AIE

Abnormal Interrupt Summary Interrupt Enabled

#define ALT_EMAC_DMA_INT_EN_AIE_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field.

#define ALT_EMAC_DMA_INT_EN_AIE_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_AIE register field.

#define ALT_EMAC_DMA_INT_EN_AIE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_AIE register field.

#define ALT_EMAC_DMA_INT_EN_AIE_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_DMA_INT_EN_AIE register field value.

#define ALT_EMAC_DMA_INT_EN_AIE_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_DMA_INT_EN_AIE register field value.

#define ALT_EMAC_DMA_INT_EN_AIE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_AIE register field.

#define ALT_EMAC_DMA_INT_EN_AIE_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_DMA_INT_EN_AIE field value from a register.

#define ALT_EMAC_DMA_INT_EN_AIE_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_DMA_INT_EN_AIE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_NIE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE

Normal Interrupt Summary Disabled

#define ALT_EMAC_DMA_INT_EN_NIE_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_INT_EN_NIE

Normal Interrupt Summary Enabled

#define ALT_EMAC_DMA_INT_EN_NIE_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field.

#define ALT_EMAC_DMA_INT_EN_NIE_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_INT_EN_NIE register field.

#define ALT_EMAC_DMA_INT_EN_NIE_WIDTH   1

The width in bits of the ALT_EMAC_DMA_INT_EN_NIE register field.

#define ALT_EMAC_DMA_INT_EN_NIE_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_DMA_INT_EN_NIE register field value.

#define ALT_EMAC_DMA_INT_EN_NIE_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_DMA_INT_EN_NIE register field value.

#define ALT_EMAC_DMA_INT_EN_NIE_RESET   0x0

The reset value of the ALT_EMAC_DMA_INT_EN_NIE register field.

#define ALT_EMAC_DMA_INT_EN_NIE_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_DMA_INT_EN_NIE field value from a register.

#define ALT_EMAC_DMA_INT_EN_NIE_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_DMA_INT_EN_NIE register field value suitable for setting the register.

#define ALT_EMAC_DMA_INT_EN_OFST   0x1c

The byte offset of the ALT_EMAC_DMA_INT_EN register from the beginning of the component.

#define ALT_EMAC_DMA_INT_EN_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_INT_EN_OFST))

The address of the ALT_EMAC_DMA_INT_EN register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_INT_EN.