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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | BG PWRDN |
[1] | RW | 0x1 | Power down |
[2] | RW | 0x0 | Enable |
[3] | RW | 0x0 | All Output Counter Reset |
[4] | RW | 0x0 | External Regulator Input Select |
[5] | RW | 0x0 | Fast Locking Enable |
[6] | RW | 0x1 | Saturation Enable |
[7] | ??? | 0x0 | UNDEFINED |
[9:8] | RW | 0x0 | Clock Source |
[15:10] | ??? | 0x0 | UNDEFINED |
[27:16] | RW | 0x1 | Loop Bandwidth Adjust |
[28] | RW | 0x0 | Loop Bandwidth Adjust Enabled |
[31:29] | ??? | 0x0 | UNDEFINED |
Field : BG PWRDN - bgpwrdn | |
If '1', powers down bandgap. If '0', bandgap is not power down. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_LSB 0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_MSB 0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET(value) (((value) << 0) & 0x00000001) |
Field : Power down - pwrdn | |
If '1', power down analog circuitry. If '0', analog circuitry not powered down. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_LSB 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_MSB 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002 |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET(value) (((value) << 1) & 0x00000002) |
Field : Enable - en | |
If '1', VCO is enabled. If '0', VCO is in reset. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_LSB 2 |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_MSB 2 |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004 |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_CLR_MSK 0xfffffffb |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_RESET 0x0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_CLKMGR_MAINPLL_VCO0_EN_SET(value) (((value) << 2) & 0x00000004) |
Field : All Output Counter Reset - outresetall | |
Before releasing Bypass, All Output Counter Reset must be set and cleared by software for correct clock operation. If '1', Reset phase multiplexer and all output counter state. So that after the assertion all the clocks output are start from rising edge align. If '0', phase multiplexer and output counter state not reset and no change to the phase of the clock outputs. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_LSB 3 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_MSB 3 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_RESET 0x0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET(value) (((value) << 3) & 0x00000008) |
Field : External Regulator Input Select - regextsel | |
If set to '1', the external regulator is selected for the PLL. If set to '0', the internal regulator is slected. It is strongly recommended to select the external regulator while the PLL is not enabled (in reset), and then disable the external regulater once the PLL becomes enabled. Software should simulateously update the 'Enable' bit and the 'External Regulator Input Select' in the same write access to the VCO register. When the 'Enable' bit is clear, the 'External Regulator Input Select' should be set, and vice versa. The reset value of this bit is applied on a cold reset; warm reset has no affect on this bit. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_LSB 4 |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_MSB 4 |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_RESET 0x0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET(value) (((value) << 4) & 0x00000010) |
Field : Fast Locking Enable - fasten | |
Enables fast locking circuit. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_LSB 5 |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_MSB 5 |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET_MSK 0x00000020 |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_RESET 0x0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET(value) (((value) << 5) & 0x00000020) |
Field : Saturation Enable - saten | |
Enables saturation behavior. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_LSB 6 |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_MSB 6 |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET_MSK 0x00000040 |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_CLR_MSK 0xffffffbf |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET(value) (((value) << 6) & 0x00000040) |
Field : Clock Source - psrc | |||||||||||||
Controls the VCO input clock source. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_EOSC1 0x0 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_F2S 0x2 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_MSB 9 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_WIDTH 2 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET_MSK 0x00000300 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_CLR_MSK 0xfffffcff | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_RESET 0x0 | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_GET(value) (((value) & 0x00000300) >> 8) | ||||||||||||
#define | ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET(value) (((value) << 8) & 0x00000300) | ||||||||||||
Field : Loop Bandwidth Adjust - bwadj | |
Provides Loop Bandwidth Adjust value. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_LSB 16 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_MSB 27 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_WIDTH 12 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET_MSK 0x0fff0000 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_RESET 0x1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_GET(value) (((value) & 0x0fff0000) >> 16) |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET(value) (((value) << 16) & 0x0fff0000) |
Field : Loop Bandwidth Adjust Enabled - bwadjen | |
If set to 1, the Loop Bandwidth Adjust value comes from the Loop Bandwidth Adjust field. If set to 0, the Loop Bandwidth Adjust value equals the M field divided by 2 value of the VCO Control Register. The M divided by 2 is the upper 12 bits (12:1) of the M field in the VCO register. Field Access Macros: | |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_LSB 28 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_MSB 28 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_WIDTH 1 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET_MSK 0x10000000 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_RESET 0x0 |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_GET(value) (((value) & 0x10000000) >> 28) |
#define | ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET(value) (((value) << 28) & 0x10000000) |
Data Structures | |
struct | ALT_CLKMGR_MAINPLL_VCO0_s |
Macros | |
#define | ALT_CLKMGR_MAINPLL_VCO0_RESET 0x00010043 |
#define | ALT_CLKMGR_MAINPLL_VCO0_OFST 0x0 |
Typedefs | |
typedef struct ALT_CLKMGR_MAINPLL_VCO0_s | ALT_CLKMGR_MAINPLL_VCO0_t |
struct ALT_CLKMGR_MAINPLL_VCO0_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_CLKMGR_MAINPLL_VCO0.
Data Fields | ||
---|---|---|
uint32_t | bgpwrdn: 1 | BG PWRDN |
uint32_t | pwrdn: 1 | Power down |
uint32_t | en: 1 | Enable |
uint32_t | outresetall: 1 | All Output Counter Reset |
uint32_t | regextsel: 1 | External Regulator Input Select |
uint32_t | fasten: 1 | Fast Locking Enable |
uint32_t | saten: 1 | Saturation Enable |
uint32_t | __pad0__: 1 | UNDEFINED |
uint32_t | psrc: 2 | Clock Source |
uint32_t | __pad1__: 6 | UNDEFINED |
uint32_t | bwadj: 12 | Loop Bandwidth Adjust |
uint32_t | bwadjen: 1 | Loop Bandwidth Adjust Enabled |
uint32_t | __pad2__: 3 | UNDEFINED |
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK 0x00000001 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_BGPWRDN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK 0x00000002 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_PWRDN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_PWRDN_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_PWRDN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_EN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_EN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_EN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_SET_MSK 0x00000004 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_EN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_EN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_EN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_EN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_EN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_EN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK 0x00000008 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_OUTRSTALL register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK 0x00000010 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_CLR_MSK 0xffffffef |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_REGEXTSEL register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET_MSK 0x00000020 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_FASTEN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_FASTEN_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_FASTEN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET_MSK 0x00000040 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_SATEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_SATEN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_SATEN_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_SATEN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_EOSC1 0x0 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
eosc1_clk
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
cb_intosc_clk
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_E_F2S 0x2 |
Enumerated value for register field ALT_CLKMGR_MAINPLL_VCO0_PSRC
f2s_free_clk
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_WIDTH 2 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET_MSK 0x00000300 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_PSRC register field.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_PSRC field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_PSRC_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_PSRC register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_WIDTH 12 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET_MSK 0x0fff0000 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_CLR_MSK 0xf000ffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_RESET 0x1 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_GET | ( | value | ) | (((value) & 0x0fff0000) >> 16) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_BWADJ field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJ_SET | ( | value | ) | (((value) << 16) & 0x0fff0000) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_BWADJ register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_WIDTH 1 |
The width in bits of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET_MSK 0x10000000 |
The mask used to set the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_CLR_MSK 0xefffffff |
The mask used to clear the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_RESET 0x0 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_CLKMGR_MAINPLL_VCO0_BWADJEN field value from a register.
#define ALT_CLKMGR_MAINPLL_VCO0_BWADJEN_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_CLKMGR_MAINPLL_VCO0_BWADJEN register field value suitable for setting the register.
#define ALT_CLKMGR_MAINPLL_VCO0_RESET 0x00010043 |
The reset value of the ALT_CLKMGR_MAINPLL_VCO0 register.
#define ALT_CLKMGR_MAINPLL_VCO0_OFST 0x0 |
The byte offset of the ALT_CLKMGR_MAINPLL_VCO0 register from the beginning of the component.
typedef struct ALT_CLKMGR_MAINPLL_VCO0_s ALT_CLKMGR_MAINPLL_VCO0_t |
The typedef declaration for register ALT_CLKMGR_MAINPLL_VCO0.