Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Shared IO 48 Q2 5 Mux Selection Register - pinmux_shared_io_q2_5

Description

This register is used to control the peripherals connected to shared IO48 pin Q2 5

Only reset by a cold reset (ignores warm reset).

NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.

Register Layout

Bits Access Reset Description
[3:0] RW 0xf Shared IO48 Q2 5 Mux Selection Field
[31:4] R 0x0 ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD

Field : Shared IO48 Q2 5 Mux Selection Field - sel

Select peripheral signals connected shared IO48 Q2 5

0000 (0) Pin is connected to Peripheral signal not applicable

0001 (1) Pin is connected to Peripheral signal not applicable

0010 (2) Pin is connected to Peripheral signal not applicable

0011 (3) Pin is connected to Peripheral signal not applicable

0100 (4) Pin is connected to Peripheral signal emac0.txd0

0101 (5) Pin is connected to Peripheral signal not applicable

0110 (6) Pin is connected to Peripheral signal not applicable

0111 (7) Pin is connected to Peripheral signal not applicable

1000 (8) Pin is connected to Peripheral signal usb1.data1

1001 (9) Pin is connected to Peripheral signal not applicable

1010 (10) Pin is connected to Peripheral signal not applicable

1011 (11) Pin is connected to Peripheral signal not applicable

1100 (12) Pin is connected to Peripheral signal not applicable

1101 (13) Pin is connected to Peripheral signal not applicable

1110 (14) Pin is connected to Peripheral signal nand.adq8

1111 (15) Pin is connected to Peripheral signal gpio0.io16

Field Access Macros:

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_LSB   0
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_MSB   3
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_WIDTH   4
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET_MSK   0x0000000f
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_CLR_MSK   0xfffffff0
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_RESET   0xf
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : Reserved

Reserved

Field Access Macros:

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_LSB   4
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_MSB   31
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_WIDTH   28
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET_MSK   0xfffffff0
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_CLR_MSK   0x0000000f
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_RESET   0x0
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_GET(value)   (((value) & 0xfffffff0) >> 4)
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET(value)   (((value) << 4) & 0xfffffff0)
 

Data Structures

struct  ALT_PINMUX_SHARED_3V_IO_Q2_5_s
 

Macros

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RESET   0x0000000f
 
#define ALT_PINMUX_SHARED_3V_IO_Q2_5_OFST   0x40
 

Typedefs

typedef struct
ALT_PINMUX_SHARED_3V_IO_Q2_5_s 
ALT_PINMUX_SHARED_3V_IO_Q2_5_t
 

Data Structure Documentation

struct ALT_PINMUX_SHARED_3V_IO_Q2_5_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_PINMUX_SHARED_3V_IO_Q2_5.

Data Fields
uint32_t sel: 4 Shared IO48 Q2 5 Mux Selection Field
const uint32_t Reserved: 28 ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD

Macro Definitions

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_MSB   3

The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_WIDTH   4

The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET_MSK   0x0000000f

The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_CLR_MSK   0xfffffff0

The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_RESET   0xf

The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL field value from a register.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_PINMUX_SHARED_3V_IO_Q2_5_SEL register field value suitable for setting the register.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_LSB   4

The Least Significant Bit (LSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_MSB   31

The Most Significant Bit (MSB) position of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_WIDTH   28

The width in bits of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET_MSK   0xfffffff0

The mask used to set the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_CLR_MSK   0x0000000f

The mask used to clear the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_RESET   0x0

The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_GET (   value)    (((value) & 0xfffffff0) >> 4)

Extracts the ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD field value from a register.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD_SET (   value)    (((value) << 4) & 0xfffffff0)

Produces a ALT_PINMUX_SHARED_3V_IO_Q2_5_RSVD register field value suitable for setting the register.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_RESET   0x0000000f

The reset value of the ALT_PINMUX_SHARED_3V_IO_Q2_5 register.

#define ALT_PINMUX_SHARED_3V_IO_Q2_5_OFST   0x40

The byte offset of the ALT_PINMUX_SHARED_3V_IO_Q2_5 register from the beginning of the component.

Typedef Documentation