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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Software Reset Register.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | W | 0x0 | ALT_UART_SRR_UR |
[1] | W | 0x0 | ALT_UART_SRR_RFR |
[2] | W | 0x0 | ALT_UART_SRR_XFR |
[31:3] | R | 0x0 | ALT_UART_SRR_RSVD_SRR_31TO3 |
Field : ur | ||||||||||
UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains will be reset. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_SRR_UR_E_NORST 0x0 | |||||||||
#define | ALT_UART_SRR_UR_E_RST 0x1 | |||||||||
#define | ALT_UART_SRR_UR_LSB 0 | |||||||||
#define | ALT_UART_SRR_UR_MSB 0 | |||||||||
#define | ALT_UART_SRR_UR_WIDTH 1 | |||||||||
#define | ALT_UART_SRR_UR_SET_MSK 0x00000001 | |||||||||
#define | ALT_UART_SRR_UR_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_UART_SRR_UR_RESET 0x0 | |||||||||
#define | ALT_UART_SRR_UR_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_UART_SRR_UR_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : rfr | ||||||||||
RCVR FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the reeive FIFO. This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals when additional DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is 'self-clearing' and it is not necessary to clear this bit. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_SRR_RFR_E_NORST 0x0 | |||||||||
#define | ALT_UART_SRR_RFR_E_RST 0x1 | |||||||||
#define | ALT_UART_SRR_RFR_LSB 1 | |||||||||
#define | ALT_UART_SRR_RFR_MSB 1 | |||||||||
#define | ALT_UART_SRR_RFR_WIDTH 1 | |||||||||
#define | ALT_UART_SRR_RFR_SET_MSK 0x00000002 | |||||||||
#define | ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_UART_SRR_RFR_RESET 0x0 | |||||||||
#define | ALT_UART_SRR_RFR_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_UART_SRR_RFR_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : xfr | ||||||||||
XMIT FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty static) just to reset the transmit FIFO. This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals when additional DMA handshaking signals are selected Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_UART_SRR_XFR_E_NORST 0x0 | |||||||||
#define | ALT_UART_SRR_XFR_E_RST 0x1 | |||||||||
#define | ALT_UART_SRR_XFR_LSB 2 | |||||||||
#define | ALT_UART_SRR_XFR_MSB 2 | |||||||||
#define | ALT_UART_SRR_XFR_WIDTH 1 | |||||||||
#define | ALT_UART_SRR_XFR_SET_MSK 0x00000004 | |||||||||
#define | ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_UART_SRR_XFR_RESET 0x0 | |||||||||
#define | ALT_UART_SRR_XFR_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_UART_SRR_XFR_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : rsvd_srr_31to3 | |
Reserved bits [31:3] - Read Only Field Access Macros: | |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_LSB 3 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_MSB 31 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_WIDTH 29 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_SET_MSK 0xfffffff8 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_CLR_MSK 0x00000007 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_RESET 0x0 |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_GET(value) (((value) & 0xfffffff8) >> 3) |
#define | ALT_UART_SRR_RSVD_SRR_31TO3_SET(value) (((value) << 3) & 0xfffffff8) |
Data Structures | |
struct | ALT_UART_SRR_s |
Macros | |
#define | ALT_UART_SRR_RESET 0x00000000 |
#define | ALT_UART_SRR_OFST 0x88 |
#define | ALT_UART_SRR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) |
Typedefs | |
typedef struct ALT_UART_SRR_s | ALT_UART_SRR_t |
struct ALT_UART_SRR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_UART_SRR.
Data Fields | ||
---|---|---|
uint32_t | ur: 1 | ALT_UART_SRR_UR |
uint32_t | rfr: 1 | ALT_UART_SRR_RFR |
uint32_t | xfr: 1 | ALT_UART_SRR_XFR |
const uint32_t | rsvd_srr_31to3: 29 | ALT_UART_SRR_RSVD_SRR_31TO3 |
#define ALT_UART_SRR_UR_E_NORST 0x0 |
Enumerated value for register field ALT_UART_SRR_UR
No reset Uart
#define ALT_UART_SRR_UR_E_RST 0x1 |
Enumerated value for register field ALT_UART_SRR_UR
Reset Uart
#define ALT_UART_SRR_UR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_UART_SRR_UR register field.
#define ALT_UART_SRR_UR_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_UART_SRR_UR register field.
#define ALT_UART_SRR_UR_WIDTH 1 |
The width in bits of the ALT_UART_SRR_UR register field.
#define ALT_UART_SRR_UR_SET_MSK 0x00000001 |
The mask used to set the ALT_UART_SRR_UR register field value.
#define ALT_UART_SRR_UR_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_UART_SRR_UR register field value.
#define ALT_UART_SRR_UR_RESET 0x0 |
The reset value of the ALT_UART_SRR_UR register field.
#define ALT_UART_SRR_UR_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_UART_SRR_UR field value from a register.
#define ALT_UART_SRR_UR_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_UART_SRR_UR register field value suitable for setting the register.
#define ALT_UART_SRR_RFR_E_NORST 0x0 |
Enumerated value for register field ALT_UART_SRR_RFR
No reset Rx FIFO
#define ALT_UART_SRR_RFR_E_RST 0x1 |
Enumerated value for register field ALT_UART_SRR_RFR
Reset Rx FIFO
#define ALT_UART_SRR_RFR_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_UART_SRR_RFR register field.
#define ALT_UART_SRR_RFR_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_UART_SRR_RFR register field.
#define ALT_UART_SRR_RFR_WIDTH 1 |
The width in bits of the ALT_UART_SRR_RFR register field.
#define ALT_UART_SRR_RFR_SET_MSK 0x00000002 |
The mask used to set the ALT_UART_SRR_RFR register field value.
#define ALT_UART_SRR_RFR_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_UART_SRR_RFR register field value.
#define ALT_UART_SRR_RFR_RESET 0x0 |
The reset value of the ALT_UART_SRR_RFR register field.
#define ALT_UART_SRR_RFR_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_UART_SRR_RFR field value from a register.
#define ALT_UART_SRR_RFR_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_UART_SRR_RFR register field value suitable for setting the register.
#define ALT_UART_SRR_XFR_E_NORST 0x0 |
Enumerated value for register field ALT_UART_SRR_XFR
No reset Tx FIFO
#define ALT_UART_SRR_XFR_E_RST 0x1 |
Enumerated value for register field ALT_UART_SRR_XFR
Reset Tx FIFO
#define ALT_UART_SRR_XFR_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_UART_SRR_XFR register field.
#define ALT_UART_SRR_XFR_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_UART_SRR_XFR register field.
#define ALT_UART_SRR_XFR_WIDTH 1 |
The width in bits of the ALT_UART_SRR_XFR register field.
#define ALT_UART_SRR_XFR_SET_MSK 0x00000004 |
The mask used to set the ALT_UART_SRR_XFR register field value.
#define ALT_UART_SRR_XFR_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_UART_SRR_XFR register field value.
#define ALT_UART_SRR_XFR_RESET 0x0 |
The reset value of the ALT_UART_SRR_XFR register field.
#define ALT_UART_SRR_XFR_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_UART_SRR_XFR field value from a register.
#define ALT_UART_SRR_XFR_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_UART_SRR_XFR register field value suitable for setting the register.
#define ALT_UART_SRR_RSVD_SRR_31TO3_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field.
#define ALT_UART_SRR_RSVD_SRR_31TO3_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_UART_SRR_RSVD_SRR_31TO3 register field.
#define ALT_UART_SRR_RSVD_SRR_31TO3_WIDTH 29 |
The width in bits of the ALT_UART_SRR_RSVD_SRR_31TO3 register field.
#define ALT_UART_SRR_RSVD_SRR_31TO3_SET_MSK 0xfffffff8 |
The mask used to set the ALT_UART_SRR_RSVD_SRR_31TO3 register field value.
#define ALT_UART_SRR_RSVD_SRR_31TO3_CLR_MSK 0x00000007 |
The mask used to clear the ALT_UART_SRR_RSVD_SRR_31TO3 register field value.
#define ALT_UART_SRR_RSVD_SRR_31TO3_RESET 0x0 |
The reset value of the ALT_UART_SRR_RSVD_SRR_31TO3 register field.
#define ALT_UART_SRR_RSVD_SRR_31TO3_GET | ( | value | ) | (((value) & 0xfffffff8) >> 3) |
Extracts the ALT_UART_SRR_RSVD_SRR_31TO3 field value from a register.
#define ALT_UART_SRR_RSVD_SRR_31TO3_SET | ( | value | ) | (((value) << 3) & 0xfffffff8) |
Produces a ALT_UART_SRR_RSVD_SRR_31TO3 register field value suitable for setting the register.
#define ALT_UART_SRR_RESET 0x00000000 |
The reset value of the ALT_UART_SRR register.
#define ALT_UART_SRR_OFST 0x88 |
The byte offset of the ALT_UART_SRR register from the beginning of the component.
#define ALT_UART_SRR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_SRR_OFST)) |
The address of the ALT_UART_SRR register.
typedef struct ALT_UART_SRR_s ALT_UART_SRR_t |
The typedef declaration for register ALT_UART_SRR.