Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : RX Sample Delay Register - rx_sample_dly

Description

This register controls the number of spi_m_clk cycles that are delayed (from the default sample time) before the actual sample of the rxd input occurs. It is impossible to write to this register when the SPI Master is enabled. The SPI Master is enabled and disabled by writing to the SPIENR register.

Register Layout

Bits Access Reset Description
[6:0] RW 0x0 Receive Data Sample Delay
[31:7] ??? 0x0 UNDEFINED

Field : Receive Data Sample Delay - rsd

This register is used to delay the sample of the rxd input port. Each value represents a single spi_m_clk delay on the sample of rxd.

Note; If this register is programmed with a value that exceeds 64, a 0 delay will be applied to the receive sample. The maximum delay is 64 spi_m_clk cycles.

Field Access Macros:

#define ALT_SPIM_RX_SMPL_DLY_RSD_LSB   0
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_MSB   6
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH   7
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK   0x0000007f
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK   0xffffff80
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_RESET   0x0
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value)   (((value) & 0x0000007f) >> 0)
 
#define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value)   (((value) << 0) & 0x0000007f)
 

Data Structures

struct  ALT_SPIM_RX_SMPL_DLY_s
 

Macros

#define ALT_SPIM_RX_SMPL_DLY_OFST   0xf0
 
#define ALT_SPIM_RX_SMPL_DLY_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))
 

Typedefs

typedef struct
ALT_SPIM_RX_SMPL_DLY_s 
ALT_SPIM_RX_SMPL_DLY_t
 

Data Structure Documentation

struct ALT_SPIM_RX_SMPL_DLY_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SPIM_RX_SMPL_DLY.

Data Fields
uint32_t rsd: 7 Receive Data Sample Delay
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_SPIM_RX_SMPL_DLY_RSD_LSB   0

The Least Significant Bit (LSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field.

#define ALT_SPIM_RX_SMPL_DLY_RSD_MSB   6

The Most Significant Bit (MSB) position of the ALT_SPIM_RX_SMPL_DLY_RSD register field.

#define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH   7

The width in bits of the ALT_SPIM_RX_SMPL_DLY_RSD register field.

#define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK   0x0000007f

The mask used to set the ALT_SPIM_RX_SMPL_DLY_RSD register field value.

#define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK   0xffffff80

The mask used to clear the ALT_SPIM_RX_SMPL_DLY_RSD register field value.

#define ALT_SPIM_RX_SMPL_DLY_RSD_RESET   0x0

The reset value of the ALT_SPIM_RX_SMPL_DLY_RSD register field.

#define ALT_SPIM_RX_SMPL_DLY_RSD_GET (   value)    (((value) & 0x0000007f) >> 0)

Extracts the ALT_SPIM_RX_SMPL_DLY_RSD field value from a register.

#define ALT_SPIM_RX_SMPL_DLY_RSD_SET (   value)    (((value) << 0) & 0x0000007f)

Produces a ALT_SPIM_RX_SMPL_DLY_RSD register field value suitable for setting the register.

#define ALT_SPIM_RX_SMPL_DLY_OFST   0xf0

The byte offset of the ALT_SPIM_RX_SMPL_DLY register from the beginning of the component.

#define ALT_SPIM_RX_SMPL_DLY_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))

The address of the ALT_SPIM_RX_SMPL_DLY register.

Typedef Documentation

The typedef declaration for register ALT_SPIM_RX_SMPL_DLY.