ALT_CLK_IN_PIN_OSC1 |
OSC_CLK_1_HPS External oscillator input:
- Input Pin
- Clock source to Main PLL
- Clock source to SDRAM PLL and Peripheral PLL if selected via register write
- Clock source for clock in safe mode
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ALT_CLK_IN_PIN_OSC2 |
OSC_CLK_2_HPS External Oscillator input:
- Input Pin
- Optional clock source to SDRAM PLL and Peripheral PLL if selected
- Typically used for Ethernet reference clock
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ALT_CLK_IN_PIN_JTAG |
JTAG_TCK_HPS
- Input Pin
- External HPS JTAG clock input.
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ALT_CLK_IN_PIN_ULPI0 |
ULPI0_CLK ULPI Clock provided by external USB0 PHY
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ALT_CLK_IN_PIN_ULPI1 |
ULPI1_CLK ULPI Clock provided by external USB1 PHY
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ALT_CLK_IN_PIN_EMAC0_RX |
EMAC0:RX_CLK Rx Reference Clock for EMAC0
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ALT_CLK_IN_PIN_EMAC1_RX |
EMAC1:RX_CLK Rx Reference Clock for EMAC1
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ALT_CLK_MAIN_PLL |
main_pll_ref_clkin Main PLL input reference clock, used to designate the Main PLL in PLL clock selections.
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ALT_CLK_PERIPHERAL_PLL |
periph_pll_ref_clkin Peripheral PLL input reference clock, used to designate the Peripheral PLL in PLL clock selections.
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ALT_CLK_SDRAM_PLL |
sdram_pll_ref_clkin SDRAM PLL input reference clock, used to designate the SDRAM PLL in PLL clock selections.
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ALT_CLK_OSC1 |
osc1_clk OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived directly from the osc_clk_1_HPS pin.
- alias for ALT_CLK_IN_PIN_OSC1
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ALT_CLK_MAIN_PLL_C0 |
Main PLL C0 Output
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ALT_CLK_MAIN_PLL_C1 |
Main PLL C1 Output
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ALT_CLK_MAIN_PLL_C2 |
Main PLL C2 Output
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ALT_CLK_MAIN_PLL_C3 |
Main PLL C3 Output
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ALT_CLK_MAIN_PLL_C4 |
Main PLL C4 Output
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ALT_CLK_MAIN_PLL_C5 |
Main PLL C5 Output
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ALT_CLK_MPU |
mpu_clk Main PLL C0 Output. Clock for MPU subsystem, including CPU0 and CPU1.
- Alias for ALT_CLK_MAIN_PLL_C0
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ALT_CLK_MPU_L2_RAM |
mpu_l2_ram_clk Clock for MPU level 2 (L2) RAM
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ALT_CLK_MPU_PERIPH |
mpu_periph_clk Clock for MPU snoop control unit (SCU) peripherals, such as the general interrupt controller (GIC)
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ALT_CLK_L3_MAIN |
main_clk Main PLL C1 Output
- Alias for ALT_CLK_MAIN_PLL_C1
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ALT_CLK_L3_MP |
l3_mp_clk Clock for L3 Master Peripheral Switch
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ALT_CLK_L3_SP |
l3_sp_clk Clock for L3 Slave Peripheral Switch
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ALT_CLK_L4_MAIN |
l4_main_clk Clock for L4 main bus
- Clock for DMA
- Clock for SPI masters
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ALT_CLK_L4_MP |
l4_mp_clk Clock for L4 master peripherals (MP) bus
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ALT_CLK_L4_SP |
l4_sp_clk Clock for L4 slave peripherals (SP) bus
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ALT_CLK_DBG_BASE |
dbg_base_clk Main PLL C2 Output
- Alias for ALT_CLK_MAIN_PLL_C2
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ALT_CLK_DBG_AT |
dbg_at_clk Clock for CoreSight debug Advanced Microcontroller Bus Architecture (AMBA) Trace Bus (ATB)
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ALT_CLK_DBG_TRACE |
dbg_trace_clk Clock for CoreSight debug Trace Port Interface Unit (TPIU)
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ALT_CLK_DBG_TIMER |
dbg_timer_clk Clock for the trace timestamp generator
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ALT_CLK_DBG |
dbg_clk Clock for Debug Access Port (DAP) and debug Advanced Peripheral Bus (APB)
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ALT_CLK_MAIN_QSPI |
main_qspi_clk Main PLL C3 Output. Quad SPI flash internal logic clock.
- Alias for ALT_CLK_MAIN_PLL_C3
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ALT_CLK_MAIN_NAND_SDMMC |
main_nand_sdmmc_clk Main PLL C4 Output. Input clock to flash controller clocks block.
- Alias for ALT_CLK_MAIN_PLL_C4
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ALT_CLK_CFG |
cfg_clk FPGA manager configuration clock.
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ALT_CLK_H2F_USER0 |
h2f_user0_clock Clock to FPGA fabric
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ALT_CLK_PERIPHERAL_PLL_C0 |
Peripheral PLL C0 Output
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ALT_CLK_PERIPHERAL_PLL_C1 |
Peripheral PLL C1 Output
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ALT_CLK_PERIPHERAL_PLL_C2 |
Peripheral PLL C2 Output
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ALT_CLK_PERIPHERAL_PLL_C3 |
Peripheral PLL C3 Output
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ALT_CLK_PERIPHERAL_PLL_C4 |
Peripheral PLL C4 Output
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ALT_CLK_PERIPHERAL_PLL_C5 |
Peripheral PLL C5 Output
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ALT_CLK_USB_MP |
usb_mp_clk Clock for USB
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ALT_CLK_SPI_M |
spi_m_clk Clock for L4 SPI master bus
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ALT_CLK_QSPI |
qspi_clk Clock for Quad SPI
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ALT_CLK_NAND_X |
nand_x_clk NAND flash controller master and slave clock
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ALT_CLK_NAND |
nand_clk Main clock for NAND flash controller
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ALT_CLK_SDMMC |
sdmmc_clk Clock for SD/MMC logic input clock
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ALT_CLK_EMAC0 |
emac0_clk EMAC 0 clock - Peripheral PLL C0 Output
- Alias for ALT_CLK_PERIPHERAL_PLL_C0
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ALT_CLK_EMAC1 |
emac1_clk EMAC 1 clock - Peripheral PLL C1 Output
- Alias for ALT_CLK_PERIPHERAL_PLL_C1
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ALT_CLK_CAN0 |
can0_clk Controller area network (CAN) controller 0 clock
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ALT_CLK_CAN1 |
can1_clk Controller area network (CAN) controller 1 clock
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ALT_CLK_GPIO_DB |
gpio_db_clk Debounce clock for GPIO0, GPIO1, and GPIO2
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ALT_CLK_H2F_USER1 |
h2f_user1_clock Clock to FPGA fabric - Peripheral PLL C5 Output
- Alias for ALT_CLK_PERIPHERAL_PLL_C5
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ALT_CLK_SDRAM_PLL_C0 |
SDRAM PLL C0 Output
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ALT_CLK_SDRAM_PLL_C1 |
SDRAM PLL C1 Output
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ALT_CLK_SDRAM_PLL_C2 |
SDRAM PLL C2 Output
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ALT_CLK_SDRAM_PLL_C3 |
SDRAM PLL C3 Output
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ALT_CLK_SDRAM_PLL_C4 |
SDRAM PLL C4 Output
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ALT_CLK_SDRAM_PLL_C5 |
SDRAM PLL C5 Output
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ALT_CLK_DDR_DQS |
ddr_dqs_clk Clock for MPFE, single-port controller, CSR access, and PHY - SDRAM PLL C0 Output
- Alias for ALT_CLK_SDRAM_PLL_C0
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ALT_CLK_DDR_2X_DQS |
ddr_2x_dqs_clk Clock for PHY - SDRAM PLL C1 Output
- Alias for ALT_CLK_SDRAM_PLL_C1
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ALT_CLK_DDR_DQ |
ddr_dq_clk Clock for PHY - SDRAM PLL C2 Output
- Alias for ALT_CLK_SDRAM_PLL_C2
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ALT_CLK_H2F_USER2 |
h2f_user2_clock Clock to FPGA fabric - SDRAM PLL C5 Output
- Alias for ALT_CLK_SDRAM_PLL_C5
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ALT_CLK_OUT_PIN_EMAC0_TX |
EMAC0:TX_CLK Tx Reference Clock for EMAC0
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ALT_CLK_OUT_PIN_EMAC1_TX |
EMAC1:TX_CLK Tx Reference Clock for EMAC1
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ALT_CLK_OUT_PIN_SDMMC |
SDMMC:CLK SD/MMC Card Clock
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ALT_CLK_OUT_PIN_I2C0_SCL |
I2C0:SCL I2C Clock for I2C0
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ALT_CLK_OUT_PIN_I2C1_SCL |
I2C1:SCL I2C Clock for I2C1
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ALT_CLK_OUT_PIN_I2C2_SCL |
I2C2:SCL I2C Clock for I2C2/2 wire
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ALT_CLK_OUT_PIN_I2C3_SCL |
I2C3:SCL I2C Clock for I2C1/2 wire
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ALT_CLK_OUT_PIN_SPIM0 |
SPIM0:CLK SPI Clock
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ALT_CLK_OUT_PIN_SPIM1 |
SPIM1:CLK SPI Clock
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ALT_CLK_OUT_PIN_QSPI |
QSPI:CLK QSPI Flash Clock
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