Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Device Status Register - dsts

Description

This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from Device All Interrupts (DAINT) register.

Register Layout

Bits Access Reset Description
[0] R 0x0 Suspend Status
[2:1] R 0x1 Enumerated Speed
[3] R 0x0 Erratic Error
[7:4] ??? 0x0 UNDEFINED
[21:8] R 0x0 Frame or Microframe Number of the Received SOF
[31:22] ??? 0x0 UNDEFINED

Field : Suspend Status - suspsts

In Device mode, this bit is Set as long as a Suspend condition is detected on the USB. The core enters the Suspended state when there is no activity on the phy_line_state_i signal for an extended period of time. The core comes out of the suspend:

  • When there is any activity on the phy_line_state_i signal
  • When the application writes to the Remote Wakeup Signaling bit in the Device Control register (DCTL.RmtWkUpSig).

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DSTS_SUSPSTS_E_INACT 0x0 No suspend state
ALT_USB_DEV_DSTS_SUSPSTS_E_ACT 0x1 Suspend state

Field Access Macros:

#define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT   0x0
 
#define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT   0x1
 
#define ALT_USB_DEV_DSTS_SUSPSTS_LSB   0
 
#define ALT_USB_DEV_DSTS_SUSPSTS_MSB   0
 
#define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH   1
 
#define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK   0x00000001
 
#define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK   0xfffffffe
 
#define ALT_USB_DEV_DSTS_SUSPSTS_RESET   0x0
 
#define ALT_USB_DEV_DSTS_SUSPSTS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_USB_DEV_DSTS_SUSPSTS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Enumerated Speed - enumspd

Indicates the speed at which the otg core has come up after speed detection through a chirp sequence.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060 0x0 High speed (PHY clock is running at 30 or 60
: MHz)
ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060 0x1 Full speed (PHY clock is running at 30 or 60
: MHz)
ALT_USB_DEV_DSTS_ENUMSPD_E_LS6 0x2 Low speed (PHY clock is running at 6 MHz)
ALT_USB_DEV_DSTS_ENUMSPD_E_FS48 0x3 Full speed (PHY clock is running at 48 MHz)

Field Access Macros:

#define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060   0x0
 
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060   0x1
 
#define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6   0x2
 
#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48   0x3
 
#define ALT_USB_DEV_DSTS_ENUMSPD_LSB   1
 
#define ALT_USB_DEV_DSTS_ENUMSPD_MSB   2
 
#define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH   2
 
#define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK   0x00000006
 
#define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK   0xfffffff9
 
#define ALT_USB_DEV_DSTS_ENUMSPD_RESET   0x1
 
#define ALT_USB_DEV_DSTS_ENUMSPD_GET(value)   (((value) & 0x00000006) >> 1)
 
#define ALT_USB_DEV_DSTS_ENUMSPD_SET(value)   (((value) << 1) & 0x00000006)
 

Field : Erratic Error - errticerr

The core sets this bit to report any erratic errors (phy_rxvalid_i/phy_rxvldh_i or phy_rxactive_i is asserted for at least 2 ms, due to PHY error) seen on the UTMI+ . Due to erratic errors, the otg core goes into Suspended state and an interrupt is generated to the application with Early Suspend bit of the Core Interrupt register (GINTSTS.ErlySusp). If the early suspend is asserted due to an erratic error, the application can only perform a soft disconnect recover.

Field Enumeration Values:

Enum Value Description
ALT_USB_DEV_DSTS_ERRTICERR_E_INACT 0x0 No Erratic Error
ALT_USB_DEV_DSTS_ERRTICERR_E_ACT 0x1 Erratic Error

Field Access Macros:

#define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT   0x0
 
#define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT   0x1
 
#define ALT_USB_DEV_DSTS_ERRTICERR_LSB   3
 
#define ALT_USB_DEV_DSTS_ERRTICERR_MSB   3
 
#define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH   1
 
#define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK   0x00000008
 
#define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK   0xfffffff7
 
#define ALT_USB_DEV_DSTS_ERRTICERR_RESET   0x0
 
#define ALT_USB_DEV_DSTS_ERRTICERR_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_USB_DEV_DSTS_ERRTICERR_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Frame or Microframe Number of the Received SOF - soffn

When the core is operating at high speed, this field contains a microframe number. When the core is operating at full or low speed, this field contains a Frame number.

Field Access Macros:

#define ALT_USB_DEV_DSTS_SOFFN_LSB   8
 
#define ALT_USB_DEV_DSTS_SOFFN_MSB   21
 
#define ALT_USB_DEV_DSTS_SOFFN_WIDTH   14
 
#define ALT_USB_DEV_DSTS_SOFFN_SET_MSK   0x003fff00
 
#define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK   0xffc000ff
 
#define ALT_USB_DEV_DSTS_SOFFN_RESET   0x0
 
#define ALT_USB_DEV_DSTS_SOFFN_GET(value)   (((value) & 0x003fff00) >> 8)
 
#define ALT_USB_DEV_DSTS_SOFFN_SET(value)   (((value) << 8) & 0x003fff00)
 

Data Structures

struct  ALT_USB_DEV_DSTS_s
 

Macros

#define ALT_USB_DEV_DSTS_OFST   0x8
 
#define ALT_USB_DEV_DSTS_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST))
 

Typedefs

typedef struct ALT_USB_DEV_DSTS_s ALT_USB_DEV_DSTS_t
 

Data Structure Documentation

struct ALT_USB_DEV_DSTS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_USB_DEV_DSTS.

Data Fields
const uint32_t suspsts: 1 Suspend Status
const uint32_t enumspd: 2 Enumerated Speed
const uint32_t errticerr: 1 Erratic Error
uint32_t __pad0__: 4 UNDEFINED
const uint32_t soffn: 14 Frame or Microframe Number of the Received SOF
uint32_t __pad1__: 10 UNDEFINED

Macro Definitions

#define ALT_USB_DEV_DSTS_SUSPSTS_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS

No suspend state

#define ALT_USB_DEV_DSTS_SUSPSTS_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DSTS_SUSPSTS

Suspend state

#define ALT_USB_DEV_DSTS_SUSPSTS_LSB   0

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field.

#define ALT_USB_DEV_DSTS_SUSPSTS_MSB   0

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SUSPSTS register field.

#define ALT_USB_DEV_DSTS_SUSPSTS_WIDTH   1

The width in bits of the ALT_USB_DEV_DSTS_SUSPSTS register field.

#define ALT_USB_DEV_DSTS_SUSPSTS_SET_MSK   0x00000001

The mask used to set the ALT_USB_DEV_DSTS_SUSPSTS register field value.

#define ALT_USB_DEV_DSTS_SUSPSTS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_USB_DEV_DSTS_SUSPSTS register field value.

#define ALT_USB_DEV_DSTS_SUSPSTS_RESET   0x0

The reset value of the ALT_USB_DEV_DSTS_SUSPSTS register field.

#define ALT_USB_DEV_DSTS_SUSPSTS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_USB_DEV_DSTS_SUSPSTS field value from a register.

#define ALT_USB_DEV_DSTS_SUSPSTS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_USB_DEV_DSTS_SUSPSTS register field value suitable for setting the register.

#define ALT_USB_DEV_DSTS_ENUMSPD_E_HS3060   0x0

Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD

High speed (PHY clock is running at 30 or 60 MHz)

#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS3060   0x1

Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD

Full speed (PHY clock is running at 30 or 60 MHz)

#define ALT_USB_DEV_DSTS_ENUMSPD_E_LS6   0x2

Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD

Low speed (PHY clock is running at 6 MHz)

#define ALT_USB_DEV_DSTS_ENUMSPD_E_FS48   0x3

Enumerated value for register field ALT_USB_DEV_DSTS_ENUMSPD

Full speed (PHY clock is running at 48 MHz)

#define ALT_USB_DEV_DSTS_ENUMSPD_LSB   1

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field.

#define ALT_USB_DEV_DSTS_ENUMSPD_MSB   2

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ENUMSPD register field.

#define ALT_USB_DEV_DSTS_ENUMSPD_WIDTH   2

The width in bits of the ALT_USB_DEV_DSTS_ENUMSPD register field.

#define ALT_USB_DEV_DSTS_ENUMSPD_SET_MSK   0x00000006

The mask used to set the ALT_USB_DEV_DSTS_ENUMSPD register field value.

#define ALT_USB_DEV_DSTS_ENUMSPD_CLR_MSK   0xfffffff9

The mask used to clear the ALT_USB_DEV_DSTS_ENUMSPD register field value.

#define ALT_USB_DEV_DSTS_ENUMSPD_RESET   0x1

The reset value of the ALT_USB_DEV_DSTS_ENUMSPD register field.

#define ALT_USB_DEV_DSTS_ENUMSPD_GET (   value)    (((value) & 0x00000006) >> 1)

Extracts the ALT_USB_DEV_DSTS_ENUMSPD field value from a register.

#define ALT_USB_DEV_DSTS_ENUMSPD_SET (   value)    (((value) << 1) & 0x00000006)

Produces a ALT_USB_DEV_DSTS_ENUMSPD register field value suitable for setting the register.

#define ALT_USB_DEV_DSTS_ERRTICERR_E_INACT   0x0

Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR

No Erratic Error

#define ALT_USB_DEV_DSTS_ERRTICERR_E_ACT   0x1

Enumerated value for register field ALT_USB_DEV_DSTS_ERRTICERR

Erratic Error

#define ALT_USB_DEV_DSTS_ERRTICERR_LSB   3

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field.

#define ALT_USB_DEV_DSTS_ERRTICERR_MSB   3

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_ERRTICERR register field.

#define ALT_USB_DEV_DSTS_ERRTICERR_WIDTH   1

The width in bits of the ALT_USB_DEV_DSTS_ERRTICERR register field.

#define ALT_USB_DEV_DSTS_ERRTICERR_SET_MSK   0x00000008

The mask used to set the ALT_USB_DEV_DSTS_ERRTICERR register field value.

#define ALT_USB_DEV_DSTS_ERRTICERR_CLR_MSK   0xfffffff7

The mask used to clear the ALT_USB_DEV_DSTS_ERRTICERR register field value.

#define ALT_USB_DEV_DSTS_ERRTICERR_RESET   0x0

The reset value of the ALT_USB_DEV_DSTS_ERRTICERR register field.

#define ALT_USB_DEV_DSTS_ERRTICERR_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_USB_DEV_DSTS_ERRTICERR field value from a register.

#define ALT_USB_DEV_DSTS_ERRTICERR_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_USB_DEV_DSTS_ERRTICERR register field value suitable for setting the register.

#define ALT_USB_DEV_DSTS_SOFFN_LSB   8

The Least Significant Bit (LSB) position of the ALT_USB_DEV_DSTS_SOFFN register field.

#define ALT_USB_DEV_DSTS_SOFFN_MSB   21

The Most Significant Bit (MSB) position of the ALT_USB_DEV_DSTS_SOFFN register field.

#define ALT_USB_DEV_DSTS_SOFFN_WIDTH   14

The width in bits of the ALT_USB_DEV_DSTS_SOFFN register field.

#define ALT_USB_DEV_DSTS_SOFFN_SET_MSK   0x003fff00

The mask used to set the ALT_USB_DEV_DSTS_SOFFN register field value.

#define ALT_USB_DEV_DSTS_SOFFN_CLR_MSK   0xffc000ff

The mask used to clear the ALT_USB_DEV_DSTS_SOFFN register field value.

#define ALT_USB_DEV_DSTS_SOFFN_RESET   0x0

The reset value of the ALT_USB_DEV_DSTS_SOFFN register field.

#define ALT_USB_DEV_DSTS_SOFFN_GET (   value)    (((value) & 0x003fff00) >> 8)

Extracts the ALT_USB_DEV_DSTS_SOFFN field value from a register.

#define ALT_USB_DEV_DSTS_SOFFN_SET (   value)    (((value) << 8) & 0x003fff00)

Produces a ALT_USB_DEV_DSTS_SOFFN register field value suitable for setting the register.

#define ALT_USB_DEV_DSTS_OFST   0x8

The byte offset of the ALT_USB_DEV_DSTS register from the beginning of the component.

#define ALT_USB_DEV_DSTS_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_DEV_DSTS_OFST))

The address of the ALT_USB_DEV_DSTS register.

Typedef Documentation

The typedef declaration for register ALT_USB_DEV_DSTS.