Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Control/Status Word Register - dma_config

Description

Consist of control bit and status information.

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL
[8] RW 0x0 ALT_FPGAMGR_DMA_CFG_DMAREQ_EN
[15:9] ??? 0x0 UNDEFINED
[16] RW 0x0 ALT_FPGAMGR_DMA_CFG_CLRFIFO
[31:17] ??? Unknown UNDEFINED

Field : dmareq_level

DMA request threshold level

Field Access Macros:

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_LSB   0
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_MSB   7
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_WIDTH   8
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET_MSK   0x000000ff
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_CLR_MSK   0xffffff00
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_RESET   0x0
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : dmareq_enable

Writing 1 will enable DMA request handshake from FPGA manager.

Writing 0 will disable DMA request handshake from FPGA manager.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS | 0x0 | ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN | 0x1 |

Field Access Macros:

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS   0x0
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN   0x1
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_LSB   8
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_MSB   8
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_WIDTH   1
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET_MSK   0x00000100
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_CLR_MSK   0xfffffeff
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_RESET   0x0
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET(value)   (((value) << 8) & 0x00000100)
 

Field : clearFifo

A write 1 to this bit field will empty the TxFifo. A read will always return 0.

Field Access Macros:

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_LSB   16
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_MSB   16
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_WIDTH   1
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET_MSK   0x00010000
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_CLR_MSK   0xfffeffff
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_RESET   0x0
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET(value)   (((value) << 16) & 0x00010000)
 

Data Structures

struct  ALT_FPGAMGR_DMA_CFG_s
 

Macros

#define ALT_FPGAMGR_DMA_CFG_RESET   0x00000000
 
#define ALT_FPGAMGR_DMA_CFG_OFST   0x90
 

Typedefs

typedef struct
ALT_FPGAMGR_DMA_CFG_s 
ALT_FPGAMGR_DMA_CFG_t
 

Data Structure Documentation

struct ALT_FPGAMGR_DMA_CFG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_FPGAMGR_DMA_CFG.

Data Fields
uint32_t dmareq_level: 8 ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL
uint32_t dmareq_enable: 1 ALT_FPGAMGR_DMA_CFG_DMAREQ_EN
uint32_t __pad0__: 7 UNDEFINED
uint32_t clearFifo: 1 ALT_FPGAMGR_DMA_CFG_CLRFIFO
uint32_t __pad1__: 15 UNDEFINED

Macro Definitions

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_MSB   7

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_WIDTH   8

The width in bits of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET_MSK   0x000000ff

The mask used to set the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_CLR_MSK   0xffffff00

The mask used to clear the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_RESET   0x0

The reset value of the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL field value from a register.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_FPGAMGR_DMA_CFG_DMAREQ_LEVEL register field value suitable for setting the register.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_DIS   0x0

Enumerated value for register field ALT_FPGAMGR_DMA_CFG_DMAREQ_EN

DMA request handshake disable.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_E_EN   0x1

Enumerated value for register field ALT_FPGAMGR_DMA_CFG_DMAREQ_EN

DMA request handshake enable

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_LSB   8

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_MSB   8

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_WIDTH   1

The width in bits of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET_MSK   0x00000100

The mask used to set the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_CLR_MSK   0xfffffeff

The mask used to clear the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_RESET   0x0

The reset value of the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_FPGAMGR_DMA_CFG_DMAREQ_EN field value from a register.

#define ALT_FPGAMGR_DMA_CFG_DMAREQ_EN_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_FPGAMGR_DMA_CFG_DMAREQ_EN register field value suitable for setting the register.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_LSB   16

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_MSB   16

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_WIDTH   1

The width in bits of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET_MSK   0x00010000

The mask used to set the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_CLR_MSK   0xfffeffff

The mask used to clear the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_RESET   0x0

The reset value of the ALT_FPGAMGR_DMA_CFG_CLRFIFO register field.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_FPGAMGR_DMA_CFG_CLRFIFO field value from a register.

#define ALT_FPGAMGR_DMA_CFG_CLRFIFO_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_FPGAMGR_DMA_CFG_CLRFIFO register field value suitable for setting the register.

#define ALT_FPGAMGR_DMA_CFG_RESET   0x00000000

The reset value of the ALT_FPGAMGR_DMA_CFG register.

#define ALT_FPGAMGR_DMA_CFG_OFST   0x90

The byte offset of the ALT_FPGAMGR_DMA_CFG register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_FPGAMGR_DMA_CFG.