Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : EMAC L3 Master AxCACHE Register - l3master

Description

Controls the L3 master ARCACHE and AWCACHE AXI signals.

These register bits should be updated only during system initialization prior to removing the peripheral from reset. They may not be changed dynamically during peripheral operation

All fields are reset by a cold or warm reset.

Register Layout

Bits Access Reset Description
[3:0] RW 0x0 EMAC ARCACHE
[7:4] RW 0x0 EMAC ARCACHE
[11:8] RW 0x0 EMAC AWCACHE
[15:12] RW 0x0 EMAC AWCACHE
[31:16] ??? 0x0 UNDEFINED

Field : EMAC ARCACHE - arcache_0

Specifies the values of the 2 EMAC ARCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF 0x0 Noncacheable and nonbufferable.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF 0x1 Bufferable only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC 0x2 Cacheable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 Cacheable and bufferable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1 0x4 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2 0x5 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 Cacheable write-through, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 Cacheable write-back, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3 0x8 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4 0x9 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa Cacheable write-through, allocate on writes
: only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb Cacheable write-back, allocate on writes only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5 0xc Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6 0xd Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe Cacheable write-through, allocate on both reads
: and writes.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC 0xf Cacheable write-back, allocate on both reads and
: writes.

Field Access Macros:

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB   0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB   3
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH   4
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK   0x0000000f
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK   0xfffffff0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET(value)   (((value) & 0x0000000f) >> 0)
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET(value)   (((value) << 0) & 0x0000000f)
 

Field : EMAC ARCACHE - arcache_1

Specifies the values of the 2 EMAC ARCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF 0x0 Noncacheable and nonbufferable.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF 0x1 Bufferable only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC 0x2 Cacheable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 Cacheable and bufferable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1 0x4 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2 0x5 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 Cacheable write-through, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 Cacheable write-back, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3 0x8 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4 0x9 Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa Cacheable write-through, allocate on writes
: only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb Cacheable write-back, allocate on writes only.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5 0xc Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6 0xd Reserved.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe Cacheable write-through, allocate on both reads
: and writes.
ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC 0xf Cacheable write-back, allocate on both reads and
: writes.

Field Access Macros:

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB   4
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB   7
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH   4
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK   0x000000f0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK   0xffffff0f
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET(value)   (((value) & 0x000000f0) >> 4)
 
#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET(value)   (((value) << 4) & 0x000000f0)
 

Field : EMAC AWCACHE - awcache_0

Specifies the values of the 2 EMAC AWCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF 0x0 Noncacheable and nonbufferable.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF 0x1 Bufferable only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC 0x2 Cacheable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC 0x3 Cacheable and bufferable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1 0x4 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2 0x5 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC 0x6 Cacheable write-through, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC 0x7 Cacheable write-back, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3 0x8 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4 0x9 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC 0xa Cacheable write-through, allocate on writes
: only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC 0xb Cacheable write-back, allocate on writes only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5 0xc Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6 0xd Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC 0xe Cacheable write-through, allocate on both reads
: and writes.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC 0xf Cacheable write-back, allocate on both reads and
: writes.

Field Access Macros:

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB   8
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB   11
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH   4
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK   0x00000f00
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK   0xfffff0ff
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET(value)   (((value) & 0x00000f00) >> 8)
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET(value)   (((value) << 8) & 0x00000f00)
 

Field : EMAC AWCACHE - awcache_1

Specifies the values of the 2 EMAC AWCACHE signals.

The field array index corresponds to the EMAC index.

Field Enumeration Values:

Enum Value Description
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF 0x0 Noncacheable and nonbufferable.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF 0x1 Bufferable only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC 0x2 Cacheable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC 0x3 Cacheable and bufferable, but do not allocate.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1 0x4 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2 0x5 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC 0x6 Cacheable write-through, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC 0x7 Cacheable write-back, allocate on reads only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3 0x8 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4 0x9 Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC 0xa Cacheable write-through, allocate on writes
: only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC 0xb Cacheable write-back, allocate on writes only.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5 0xc Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6 0xd Reserved.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC 0xe Cacheable write-through, allocate on both reads
: and writes.
ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC 0xf Cacheable write-back, allocate on both reads and
: writes.

Field Access Macros:

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF   0x1
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC   0x2
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC   0x3
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1   0x4
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2   0x5
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC   0x6
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC   0x7
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3   0x8
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4   0x9
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC   0xa
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC   0xb
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5   0xc
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6   0xd
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC   0xe
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC   0xf
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB   12
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB   15
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH   4
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK   0x0000f000
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK   0xffff0fff
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET   0x0
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET(value)   (((value) & 0x0000f000) >> 12)
 
#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET(value)   (((value) << 12) & 0x0000f000)
 

Data Structures

struct  ALT_SYSMGR_EMAC_L3MST_s
 

Macros

#define ALT_SYSMGR_EMAC_L3MST_OFST   0x4
 

Typedefs

typedef struct
ALT_SYSMGR_EMAC_L3MST_s 
ALT_SYSMGR_EMAC_L3MST_t
 

Data Structure Documentation

struct ALT_SYSMGR_EMAC_L3MST_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_EMAC_L3MST.

Data Fields
uint32_t arcache_0: 4 EMAC ARCACHE
uint32_t arcache_1: 4 EMAC ARCACHE
uint32_t awcache_0: 4 EMAC AWCACHE
uint32_t awcache_1: 4 EMAC AWCACHE
uint32_t __pad0__: 16 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Noncacheable and nonbufferable.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Bufferable only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable and bufferable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-through, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-back, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-through, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-back, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-through, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_0

Cacheable write-back, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_MSB   3

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET_MSK   0x0000000f

The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_CLR_MSK   0xfffffff0

The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_GET (   value)    (((value) & 0x0000000f) >> 0)

Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 field value from a register.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_0_SET (   value)    (((value) << 0) & 0x0000000f)

Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_0 register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Noncacheable and nonbufferable.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Bufferable only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable and bufferable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-through, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-back, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-through, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-back, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-through, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_ARCACHE_1

Cacheable write-back, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_LSB   4

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET_MSK   0x000000f0

The mask used to set the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_CLR_MSK   0xffffff0f

The mask used to clear the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_GET (   value)    (((value) & 0x000000f0) >> 4)

Extracts the ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 field value from a register.

#define ALT_SYSMGR_EMAC_L3MST_ARCACHE_1_SET (   value)    (((value) << 4) & 0x000000f0)

Produces a ALT_SYSMGR_EMAC_L3MST_ARCACHE_1 register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Noncacheable and nonbufferable.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Bufferable only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable and bufferable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-through, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-back, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-through, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-back, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-through, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_0

Cacheable write-back, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_MSB   11

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET_MSK   0x00000f00

The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_CLR_MSK   0xfffff0ff

The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_GET (   value)    (((value) & 0x00000f00) >> 8)

Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 field value from a register.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_0_SET (   value)    (((value) << 8) & 0x00000f00)

Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_0 register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_NONCACHE_NONBUFF   0x0

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Noncacheable and nonbufferable.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_BUFF   0x1

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Bufferable only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_NONALLOC   0x2

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_BUFF_NONALLOC   0x3

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable and bufferable, but do not allocate.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD1   0x4

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD2   0x5

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_RDALLOC   0x6

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-through, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_RDALLOC   0x7

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-back, allocate on reads only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD3   0x8

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD4   0x9

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_WRALLOC   0xa

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-through, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_WRALLOC   0xb

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-back, allocate on writes only.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD5   0xc

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_RSVD6   0xd

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Reserved.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRTHRU_ALLOC   0xe

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-through, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_E_CACHE_WRBACK_ALLOC   0xf

Enumerated value for register field ALT_SYSMGR_EMAC_L3MST_AWCACHE_1

Cacheable write-back, allocate on both reads and writes.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_LSB   12

The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_MSB   15

The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_WIDTH   4

The width in bits of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET_MSK   0x0000f000

The mask used to set the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_CLR_MSK   0xffff0fff

The mask used to clear the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_RESET   0x0

The reset value of the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_GET (   value)    (((value) & 0x0000f000) >> 12)

Extracts the ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 field value from a register.

#define ALT_SYSMGR_EMAC_L3MST_AWCACHE_1_SET (   value)    (((value) << 12) & 0x0000f000)

Produces a ALT_SYSMGR_EMAC_L3MST_AWCACHE_1 register field value suitable for setting the register.

#define ALT_SYSMGR_EMAC_L3MST_OFST   0x4

The byte offset of the ALT_SYSMGR_EMAC_L3MST register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_EMAC_L3MST.