Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Reset Cycles Count Register - counts

Description

The COUNTS register is used by software to control reset behavior.It includes fields for software to control the behavior of the warm reset and nRST pin.

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[19:0] RW 0x800 nRST Pin Count
[23:20] ??? 0x0 UNDEFINED
[31:24] RW 0x80 Warm reset release delay count

Field : nRST Pin Count - nrstcnt

The Reset Manager pulls down the nRST pin on a warm reset for the number of cycles specified in this register. A value of 0x0 prevents the Reset Manager from pulling down the nRST pin.

Field Access Macros:

#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB   0
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB   19
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH   20
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK   0x000fffff
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK   0xfff00000
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET   0x800
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_GET(value)   (((value) & 0x000fffff) >> 0)
 
#define ALT_RSTMGR_COUNTS_NRSTCNT_SET(value)   (((value) << 0) & 0x000fffff)
 

Field : Warm reset release delay count - warmrstcycles

On a warm reset, the Reset Manager releases the reset to the Clock Manager, and then waits for the number of cycles specified in this register before releasing the rest of the hardware controlled resets.

Field Access Macros:

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB   24
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB   31
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH   8
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK   0xff000000
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK   0x00ffffff
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET   0x80
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET(value)   (((value) & 0xff000000) >> 24)
 
#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET(value)   (((value) << 24) & 0xff000000)
 

Data Structures

struct  ALT_RSTMGR_COUNTS_s
 

Macros

#define ALT_RSTMGR_COUNTS_RESET   0x80000800
 
#define ALT_RSTMGR_COUNTS_OFST   0x1c
 

Typedefs

typedef struct ALT_RSTMGR_COUNTS_s ALT_RSTMGR_COUNTS_t
 

Data Structure Documentation

struct ALT_RSTMGR_COUNTS_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_COUNTS.

Data Fields
uint32_t nrstcnt: 20 nRST Pin Count
uint32_t __pad0__: 4 UNDEFINED
uint32_t warmrstcycles: 8 Warm reset release delay count

Macro Definitions

#define ALT_RSTMGR_COUNTS_NRSTCNT_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field.

#define ALT_RSTMGR_COUNTS_NRSTCNT_MSB   19

The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_NRSTCNT register field.

#define ALT_RSTMGR_COUNTS_NRSTCNT_WIDTH   20

The width in bits of the ALT_RSTMGR_COUNTS_NRSTCNT register field.

#define ALT_RSTMGR_COUNTS_NRSTCNT_SET_MSK   0x000fffff

The mask used to set the ALT_RSTMGR_COUNTS_NRSTCNT register field value.

#define ALT_RSTMGR_COUNTS_NRSTCNT_CLR_MSK   0xfff00000

The mask used to clear the ALT_RSTMGR_COUNTS_NRSTCNT register field value.

#define ALT_RSTMGR_COUNTS_NRSTCNT_RESET   0x800

The reset value of the ALT_RSTMGR_COUNTS_NRSTCNT register field.

#define ALT_RSTMGR_COUNTS_NRSTCNT_GET (   value)    (((value) & 0x000fffff) >> 0)

Extracts the ALT_RSTMGR_COUNTS_NRSTCNT field value from a register.

#define ALT_RSTMGR_COUNTS_NRSTCNT_SET (   value)    (((value) << 0) & 0x000fffff)

Produces a ALT_RSTMGR_COUNTS_NRSTCNT register field value suitable for setting the register.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_LSB   24

The Least Significant Bit (LSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_MSB   31

The Most Significant Bit (MSB) position of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_WIDTH   8

The width in bits of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET_MSK   0xff000000

The mask used to set the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_CLR_MSK   0x00ffffff

The mask used to clear the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_RESET   0x80

The reset value of the ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_GET (   value)    (((value) & 0xff000000) >> 24)

Extracts the ALT_RSTMGR_COUNTS_WARMRSTCYCLES field value from a register.

#define ALT_RSTMGR_COUNTS_WARMRSTCYCLES_SET (   value)    (((value) << 24) & 0xff000000)

Produces a ALT_RSTMGR_COUNTS_WARMRSTCYCLES register field value suitable for setting the register.

#define ALT_RSTMGR_COUNTS_RESET   0x80000800

The reset value of the ALT_RSTMGR_COUNTS register.

#define ALT_RSTMGR_COUNTS_OFST   0x1c

The byte offset of the ALT_RSTMGR_COUNTS register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_COUNTS.