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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
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[31:0] | RW | 0x0 | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U |
Field : cfg_bist_cmd1_u | |
TBD Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_LSB 0 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_MSB 31 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_GET(value) (((value) & 0xffffffff) >> 0) |
#define | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET(value) (((value) << 0) & 0xffffffff) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_DBGCFG4_s |
Macros | |
#define | ALT_IO48_HMC_MMR_DBGCFG4_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_DBGCFG4_OFST 0x10 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_DBGCFG4_s | ALT_IO48_HMC_MMR_DBGCFG4_t |
struct ALT_IO48_HMC_MMR_DBGCFG4_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG4.
Data Fields | ||
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uint32_t | cfg_bist_cmd1_u: 32 | ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U |
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_WIDTH 32 |
The width in bits of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET_MSK 0xffffffff |
The mask used to set the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_CLR_MSK 0x00000000 |
The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_GET | ( | value | ) | (((value) & 0xffffffff) >> 0) |
Extracts the ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U field value from a register.
#define ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U_SET | ( | value | ) | (((value) << 0) & 0xffffffff) |
Produces a ALT_IO48_HMC_MMR_DBGCFG4_CFG_BIST_CMD1_U register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_DBGCFG4_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_DBGCFG4 register.
#define ALT_IO48_HMC_MMR_DBGCFG4_OFST 0x10 |
The byte offset of the ALT_IO48_HMC_MMR_DBGCFG4 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_DBGCFG4_s ALT_IO48_HMC_MMR_DBGCFG4_t |
The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG4.