Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Clock Divider Register - clkdiv

Description

Divides Clock sdmmc_clk.

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 Clk Divider 0
[31:8] ??? 0x0 UNDEFINED

Field : Clk Divider 0 - clk_divider0

Clock divider-0 value. Clock division is 2*n. For example, value of 0 means divide by 2*0 = 0 (no division, bypass), value of 1 means divide by 2*1 = 2, value of ff means divide by 2*255 = 510, and so on.

Field Access Macros:

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB   0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB   7
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH   8
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK   0x000000ff
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK   0xffffff00
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET   0x0
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET(value)   (((value) << 0) & 0x000000ff)
 

Data Structures

struct  ALT_SDMMC_CLKDIV_s
 

Macros

#define ALT_SDMMC_CLKDIV_OFST   0x8
 

Typedefs

typedef struct ALT_SDMMC_CLKDIV_s ALT_SDMMC_CLKDIV_t
 

Data Structure Documentation

struct ALT_SDMMC_CLKDIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SDMMC_CLKDIV.

Data Fields
uint32_t clk_divider0: 8 Clk Divider 0
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_LSB   0

The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_MSB   7

The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_WIDTH   8

The width in bits of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET_MSK   0x000000ff

The mask used to set the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_CLR_MSK   0xffffff00

The mask used to clear the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_RESET   0x0

The reset value of the ALT_SDMMC_CLKDIV_CLK_DIVR0 register field.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_SDMMC_CLKDIV_CLK_DIVR0 field value from a register.

#define ALT_SDMMC_CLKDIV_CLK_DIVR0_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_SDMMC_CLKDIV_CLK_DIVR0 register field value suitable for setting the register.

#define ALT_SDMMC_CLKDIV_OFST   0x8

The byte offset of the ALT_SDMMC_CLKDIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SDMMC_CLKDIV.