Altera HWLIB  16.0
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alt_spi.h
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32 
33 /*
34  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/alt_spi.h#1 $
35  */
36 
41 #ifndef __ALT_SPI_H__
42 #define __ALT_SPI_H__
43 
44 #include "hwlib.h"
45 #include "alt_clock_manager.h"
46 #include "socal/alt_spis.h"
47 #include "socal/alt_spim.h"
48 #include "socal/alt_sysmgr.h"
49 #include "socal/hps.h"
50 #include "socal/socal.h"
51 
52 #ifdef __cplusplus
53 extern "C"
54 {
55 #endif /* __cplusplus */
56 
57 /******************************************************************************/
73 typedef enum ALT_SPI_CTLR_e
74 {
75  ALT_SPI_SPIM0 = (int32_t)ALT_SPIM0_OFST,
76  ALT_SPI_SPIM1 = (int32_t)ALT_SPIM1_OFST,
77  ALT_SPI_SPIS0 = (int32_t)ALT_SPIS0_OFST,
78  ALT_SPI_SPIS1 = (int32_t)ALT_SPIS1_OFST
80 
90 typedef enum ALT_SPI_FRF_e
91 {
103 } ALT_SPI_FRF_t;
104 
111 typedef enum ALT_SPI_SCPOL_e
112 {
116 
126 typedef enum ALT_SPI_SCPH_e
127 {
131 
136 typedef enum ALT_SPI_DFS_e
137 {
151 } ALT_SPI_DFS_t;
152 
157 typedef enum ALT_SPI_TMOD_e
158 {
164 
168 typedef enum ALT_SPI_OP_MODE_e
169 {
173 
174 /*
175  * A pointer or handle to the SPI controller device instance. The ALT_SPI_DEV_t is
176  * initialized by a call to alt_spi_init() and subsequently used by the other SPI
177  * controller API functions as a reference to a specific device.
178  *
179  * \internal
180  * ALT_SPI_DEV_t may be a struct or reference to an opaque data
181  * structure. Whatever "internal" type is suited to the needs of the
182  * implementation.
183  * \endinternal
184  */
185 typedef struct ALT_SPI_DEV_s
186 {
187  void * location;
189  alt_freq_t clock_freq;
191  uint32_t last_slave_mask;
193  uint32_t last_transfer_mode;
195  ALT_SPI_OP_MODE_t op_mode;
197 } ALT_SPI_DEV_t;
198 
203 typedef struct ALT_SPI_CONFIG_s
204 {
239  bool slave_output_enable;
261  bool loopback_mode;
277 
285 typedef enum ALT_SPI_MW_MODE_e
286 {
290 
295 typedef enum ALT_SPI_SS_e
296 {
297  ALT_SPI_SS0 = 1UL << 0,
298  ALT_SPI_SS1 = 1UL << 1,
299  ALT_SPI_SS2 = 1UL << 2,
300  ALT_SPI_SS3 = 1UL << 3
301 } ALT_SPI_SS_t;
302 
308 typedef enum ALT_SPI_MW_DIR_e
309 {
318 
322 #define ALT_SPI_MW_CTL_FRAME_SIZE_MAX (16)
323 
328 typedef struct ALT_SPI_MW_CONFIG_s
329 {
330  uint32_t ctl_frame_size;
346  bool handshake_enabled;
359 
386 ALT_STATUS_CODE alt_spi_init(const ALT_SPI_CTLR_t spi, ALT_SPI_DEV_t *spi_dev);
387 
406 ALT_STATUS_CODE alt_spi_reset(ALT_SPI_DEV_t * spi_dev);
407 
427 ALT_STATUS_CODE alt_spi_uninit(ALT_SPI_DEV_t *spi_dev);
428 
446 ALT_STATUS_CODE alt_spi_disable(ALT_SPI_DEV_t *spi_dev);
447 
461 ALT_STATUS_CODE alt_spi_enable(ALT_SPI_DEV_t *spi_dev);
462 
477 ALT_STATUS_CODE alt_spi_is_enabled(ALT_SPI_DEV_t *spi_dev);
478 
498 ALT_STATUS_CODE alt_spi_is_busy(ALT_SPI_DEV_t *spi_dev);
499 
517 ALT_STATUS_CODE alt_spi_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_CONFIG_t *cfg);
518 
536 ALT_STATUS_CODE alt_spi_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_CONFIG_t *cfg);
537 
557 ALT_STATUS_CODE alt_spi_mw_config_get(ALT_SPI_DEV_t *spi_dev, ALT_SPI_MW_CONFIG_t *cfg);
558 
576 ALT_STATUS_CODE alt_spi_mw_config_set(ALT_SPI_DEV_t *spi_dev, const ALT_SPI_MW_CONFIG_t *cfg);
577 
581 #define ALT_SPI_SLAVE_MASK_ALL 0xF
582 
603 ALT_STATUS_CODE alt_spi_slave_select_disable(ALT_SPI_DEV_t *spi_dev,
604  const uint32_t mask);
605 
630 ALT_STATUS_CODE alt_spi_slave_select_enable(ALT_SPI_DEV_t *spi_dev,
631  const uint32_t mask);
632 
652 ALT_STATUS_CODE alt_spi_divider_get(ALT_SPI_DEV_t *spi_dev, uint32_t *div);
653 
684 ALT_STATUS_CODE alt_spi_divider_set(ALT_SPI_DEV_t *spi_dev, const uint32_t div);
685 
705 ALT_STATUS_CODE alt_spi_speed_get(ALT_SPI_DEV_t * spi_dev,
706  uint32_t * speed_in_hz);
707 
724 ALT_STATUS_CODE alt_spi_speed_set(ALT_SPI_DEV_t * spi_dev,
725  uint32_t speed_in_hz);
726 
744 ALT_STATUS_CODE alt_spi_num_data_frames_get(ALT_SPI_DEV_t *spi_dev, uint32_t *num_data_frames);
745 
772 ALT_STATUS_CODE alt_spi_num_data_frames_set(ALT_SPI_DEV_t *spi_dev, const uint32_t num_data_frames);
773 
774 /******************************************************************************/
829 typedef enum ALT_SPI_STATUS_e
830 {
831  ALT_SPI_STATUS_TXEI = 1UL << 0,
832  ALT_SPI_STATUS_TXOI = 1UL << 1,
833  ALT_SPI_STATUS_RXUI = 1UL << 2,
834  ALT_SPI_STATUS_RXOI = 1UL << 3,
835  ALT_SPI_STATUS_RXFI = 1UL << 4,
838 
860 ALT_STATUS_CODE alt_spi_int_status_get(ALT_SPI_DEV_t *spi_dev,
861  uint32_t *status);
862 
885 ALT_STATUS_CODE alt_spi_int_raw_status_get(ALT_SPI_DEV_t *spi_dev,
886  uint32_t *status);
887 
915 ALT_STATUS_CODE alt_spi_int_clear(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
916 
945 ALT_STATUS_CODE alt_spi_int_disable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
946 
975 ALT_STATUS_CODE alt_spi_int_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t mask);
976 
979 /******************************************************************************/
997 #define ALT_SPI_RXD_SAMPLE_DELAY_MAX 4
998 
1015 ALT_STATUS_CODE alt_spi_rx_sample_delay_get(ALT_SPI_DEV_t *spi_dev, uint32_t *delay);
1016 
1033 ALT_STATUS_CODE alt_spi_rx_sample_delay_set(ALT_SPI_DEV_t *spi_dev, const uint32_t delay);
1034 
1037 /******************************************************************************/
1055 #define ALT_SPI_RX_FIFO_NUM_ENTRIES 256
1056 
1076 ALT_STATUS_CODE alt_spi_rx_fifo_deq(ALT_SPI_DEV_t *spi_dev, uint16_t *data);
1077 
1091 ALT_STATUS_CODE alt_spi_rx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev);
1092 
1106 ALT_STATUS_CODE alt_spi_rx_fifo_is_full(ALT_SPI_DEV_t *spi_dev);
1107 
1124 ALT_STATUS_CODE alt_spi_rx_fifo_level_get(ALT_SPI_DEV_t *spi_dev,
1125  uint32_t *num_entries);
1126 
1143 ALT_STATUS_CODE alt_spi_rx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev,
1144  uint8_t *threshold);
1145 
1162 ALT_STATUS_CODE alt_spi_rx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev,
1163  const uint8_t threshold);
1164 
1167 /******************************************************************************/
1185 #define ALT_SPI_TX_FIFO_NUM_ENTRIES 256
1186 
1208 ALT_STATUS_CODE alt_spi_tx_fifo_enq(ALT_SPI_DEV_t *spi_dev, const uint16_t data);
1209 
1223 ALT_STATUS_CODE alt_spi_tx_fifo_is_empty(ALT_SPI_DEV_t *spi_dev);
1224 
1238 ALT_STATUS_CODE alt_spi_tx_fifo_is_full(ALT_SPI_DEV_t *spi_dev);
1239 
1256 ALT_STATUS_CODE alt_spi_tx_fifo_level_get(ALT_SPI_DEV_t *spi_dev,
1257  uint32_t *num_entries);
1258 
1275 ALT_STATUS_CODE alt_spi_tx_fifo_threshold_get(ALT_SPI_DEV_t *spi_dev,
1276  uint8_t *threshold);
1277 
1294 ALT_STATUS_CODE alt_spi_tx_fifo_threshold_set(ALT_SPI_DEV_t *spi_dev,
1295  const uint8_t threshold);
1296 
1299 /******************************************************************************/
1324 /******************************************************************************/
1377 ALT_STATUS_CODE alt_spi_master_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1378  const uint32_t slave_select,
1379  const size_t num_frames,
1380  const uint16_t * tx_buf,
1381  uint16_t * rx_buf);
1382 
1419 ALT_STATUS_CODE alt_spi_master_tx_transfer(ALT_SPI_DEV_t *spi_dev,
1420  const uint32_t slave_select,
1421  const size_t num_frames,
1422  const uint16_t * tx_buf);
1423 
1459 ALT_STATUS_CODE alt_spi_master_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1460  const uint32_t slave_select,
1461  const size_t num_frames,
1462  uint16_t * rx_buf);
1463 
1509 ALT_STATUS_CODE alt_spi_master_eeprom_transfer(ALT_SPI_DEV_t *spi_dev,
1510  const uint32_t slave_select,
1511  const uint8_t opcode,
1512  const uint16_t eeprom_addr,
1513  const size_t num_frames,
1514  uint16_t * rx_buf);
1515 
1518 /******************************************************************************/
1567 ALT_STATUS_CODE alt_spi_slave_tx_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1568  const uint16_t * tx_buf,
1569  uint16_t * rx_buf,
1570  const size_t buf_len);
1571 
1604 ALT_STATUS_CODE alt_spi_slave_tx_transfer(ALT_SPI_DEV_t *spi_dev,
1605  const uint16_t * tx_buf,
1606  const size_t buf_len);
1607 
1640 ALT_STATUS_CODE alt_spi_slave_rx_transfer(ALT_SPI_DEV_t *spi_dev,
1641  uint16_t * rx_buf,
1642  const size_t buf_len);
1643 
1648 /******************************************************************************/
1679 ALT_STATUS_CODE alt_spi_dma_tx_disable(ALT_SPI_DEV_t *spi_dev);
1680 
1702 ALT_STATUS_CODE alt_spi_dma_tx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level);
1703 
1717 ALT_STATUS_CODE alt_spi_dma_rx_disable(ALT_SPI_DEV_t *spi_dev);
1718 
1740 ALT_STATUS_CODE alt_spi_dma_rx_enable(ALT_SPI_DEV_t *spi_dev, const uint32_t level);
1741 
1746 #ifdef __cplusplus
1747 }
1748 #endif /* __cplusplus */
1749 #endif /* __ALT_SPI_H__ */