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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register instructs the controller to put the DRAM into a power down state. Note that some commands are only valid for certain memory types.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | Unknown | Deep Power Down Request |
[2:1] | RW | Unknown | Deep Power Down Chip Select Mask |
[3] | RW | Unknown | Self-refresh Request |
[5:4] | RW | Unknown | Self-refresh Chip Select Mask |
[31:6] | ??? | 0x0 | UNDEFINED |
Field : Deep Power Down Request - deeppwrdnreq | |
Write a one to this bit to request a deep power down. This bit should only be written with LPDDR2 DRAMs, DDR3 DRAMs do not support deep power down. Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET(value) (((value) << 0) & 0x00000001) |
Field : Deep Power Down Chip Select Mask - deeppwrdnmask | |
Write ones to this register to select which DRAM chip selects will be powered down. Typical usage is to set both of these bits when deeppwrdnreq is set but the controller does support putting a single chip into deep power down and keeping the other chip running. Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET(value) (((value) & 0x00000006) >> 1) |
#define | ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET(value) (((value) << 1) & 0x00000006) |
Field : Self-refresh Request - selfrshreq | |
Write a one to this bit to request the RAM be put into a self refresh state. This bit is treated as a static value so the RAM will remain in self-refresh as long as this register bit is set to a one. This power down mode can be selected for all DRAMs supported by the controller. Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET(value) (((value) << 3) & 0x00000008) |
Field : Self-refresh Chip Select Mask - selfrfshmask | |
Write a one to each bit of this field to have a self refresh request apply to both chips. Field Access Macros: | |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET(value) (((value) & 0x00000030) >> 4) |
#define | ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET(value) (((value) << 4) & 0x00000030) |
Data Structures | |
struct | ALT_SDR_CTL_LOWPWREQ_s |
Macros | |
#define | ALT_SDR_CTL_LOWPWREQ_OFST 0x54 |
Typedefs | |
typedef struct ALT_SDR_CTL_LOWPWREQ_s | ALT_SDR_CTL_LOWPWREQ_t |
struct ALT_SDR_CTL_LOWPWREQ_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDR_CTL_LOWPWREQ.
Data Fields | ||
---|---|---|
uint32_t | deeppwrdnreq: 1 | Deep Power Down Request |
uint32_t | deeppwrdnmask: 2 | Deep Power Down Chip Select Mask |
uint32_t | selfrshreq: 1 | Self-refresh Request |
uint32_t | selfrfshmask: 2 | Self-refresh Chip Select Mask |
uint32_t | __pad0__: 26 | UNDEFINED |
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET_MSK 0x00000001 |
The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ field value from a register.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNREQ register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_WIDTH 2 |
The width in bits of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET_MSK 0x00000006 |
The mask used to set the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_CLR_MSK 0xfffffff9 |
The mask used to clear the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_GET | ( | value | ) | (((value) & 0x00000006) >> 1) |
Extracts the ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK field value from a register.
#define ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK_SET | ( | value | ) | (((value) << 1) & 0x00000006) |
Produces a ALT_SDR_CTL_LOWPWREQ_DEEPPWRDNMSK register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_WIDTH 1 |
The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET_MSK 0x00000008 |
The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ field value from a register.
#define ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SDR_CTL_LOWPWREQ_SELFRSHREQ register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_WIDTH 2 |
The width in bits of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET_MSK 0x00000030 |
The mask used to set the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_CLR_MSK 0xffffffcf |
The mask used to clear the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_RESET 0x0 |
The reset value of the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field is UNKNOWN.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_GET | ( | value | ) | (((value) & 0x00000030) >> 4) |
Extracts the ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK field value from a register.
#define ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK_SET | ( | value | ) | (((value) << 4) & 0x00000030) |
Produces a ALT_SDR_CTL_LOWPWREQ_SELFRFSHMSK register field value suitable for setting the register.
#define ALT_SDR_CTL_LOWPWREQ_OFST 0x54 |
The byte offset of the ALT_SDR_CTL_LOWPWREQ register from the beginning of the component.
typedef struct ALT_SDR_CTL_LOWPWREQ_s ALT_SDR_CTL_LOWPWREQ_t |
The typedef declaration for register ALT_SDR_CTL_LOWPWREQ.