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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This register is used to enable ECC on the EMAC0 RAM. ECC errors can be injected into the write path using bits in this register. This register contains interrupt status of the ECC single/double bit error.
Only reset by a cold reset (ignores warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | EMAC0 RAM ECC Enable |
[1] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject single, correctable Error |
[2] | RW | 0x0 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error |
[3] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject single, correctable Error |
[4] | RW | 0x0 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error |
[5] | RW | 0x0 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status |
[6] | RW | 0x0 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status |
[7] | RW | 0x0 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status |
[8] | RW | 0x0 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status |
[31:9] | ??? | 0x0 | UNDEFINED |
Field : EMAC0 RAM ECC Enable - en | |
Enable ECC for EMAC0 RAM Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 |
#define | ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 |
#define | ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 |
#define | ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe |
#define | ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SYSMGR_ECC_EMAC0_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : EMAC0 TXFIFO RAM ECC inject single, correctable Error - txfifoinjs | |
Changing this bit from zero to one injects a single, correctable error into the EMAC0 TXFIFO RAM. This only injects one error into the EMAC0 TXFIFO RAM. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET(value) (((value) << 1) & 0x00000002) |
Field : EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error - txfifoinjd | |
Changing this bit from zero to one injects a double, non-correctable error into the EMAC0 TXFIFO RAM. This only injects one double bit error into the EMAC0 TXFIFO RAM. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET(value) (((value) << 2) & 0x00000004) |
Field : EMAC0 RXFIFO RAM ECC inject single, correctable Error - rxfifoinjs | |
Changing this bit from zero to one injects a single, correctable error into the EMAC0 RXFIFO RAM. This only injects one error into the EMAC0 RXFIFO RAM. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET(value) (((value) << 3) & 0x00000008) |
Field : EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error - rxfifoinjd | |
Changing this bit from zero to one injects a double, non-correctable error into the EMAC0 RXFIFO RAM. This only injects one double bit error into the EMAC0 RXFIFO RAM. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET(value) (((value) << 4) & 0x00000010) |
Field : EMAC0 TXFIFO RAM ECC single, correctable error interrupt status - txfifoserr | |
This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET(value) (((value) << 5) & 0x00000020) |
Field : EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status - txfifoderr | |
This bit is an interrupt status bit for EMAC0 TXFIFO RAM ECC double bit, non- correctable error. It is set by hardware when double bit, non-correctable error occurs in EMAC0 TXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET(value) (((value) << 6) & 0x00000040) |
Field : EMAC0 RXFIFO RAM ECC single, correctable error interrupt status - rxfifoserr | |
This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC single, correctable error. It is set by hardware when single, correctable error occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET(value) (((value) << 7) & 0x00000080) |
Field : EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status - rxfifoderr | |
This bit is an interrupt status bit for EMAC0 RXFIFO RAM ECC double bit, non- correctable error. It is set by hardware when double bit, non-correctable error occurs in EMAC0 RXFIFO RAM. Software needs to write 1 into this bit to clear the interrupt status. Field Access Macros: | |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET(value) (((value) << 8) & 0x00000100) |
Data Structures | |
struct | ALT_SYSMGR_ECC_EMAC0_s |
Macros | |
#define | ALT_SYSMGR_ECC_EMAC0_OFST 0x10 |
Typedefs | |
typedef struct ALT_SYSMGR_ECC_EMAC0_s | ALT_SYSMGR_ECC_EMAC0_t |
struct ALT_SYSMGR_ECC_EMAC0_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_ECC_EMAC0.
Data Fields | ||
---|---|---|
uint32_t | en: 1 | EMAC0 RAM ECC Enable |
uint32_t | txfifoinjs: 1 | EMAC0 TXFIFO RAM ECC inject single, correctable Error |
uint32_t | txfifoinjd: 1 | EMAC0 TXFIFO RAM ECC inject double bit, non-correctable error |
uint32_t | rxfifoinjs: 1 | EMAC0 RXFIFO RAM ECC inject single, correctable Error |
uint32_t | rxfifoinjd: 1 | EMAC0 RXFIFO RAM ECC inject double bit, non-correctable error |
uint32_t | txfifoserr: 1 | EMAC0 TXFIFO RAM ECC single, correctable error interrupt status |
uint32_t | txfifoderr: 1 | EMAC0 TXFIFO RAM ECC double bit, non-correctable error interrupt status |
uint32_t | rxfifoserr: 1 | EMAC0 RXFIFO RAM ECC single, correctable error interrupt status |
uint32_t | rxfifoderr: 1 | EMAC0 RXFIFO RAM ECC double bit, non-correctable error interrupt status |
uint32_t | __pad0__: 23 | UNDEFINED |
#define ALT_SYSMGR_ECC_EMAC0_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field.
#define ALT_SYSMGR_ECC_EMAC0_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_EN register field.
#define ALT_SYSMGR_ECC_EMAC0_EN_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_EN register field.
#define ALT_SYSMGR_ECC_EMAC0_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_EN register field value.
#define ALT_SYSMGR_ECC_EMAC0_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_EN register field value.
#define ALT_SYSMGR_ECC_EMAC0_EN_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_EN register field.
#define ALT_SYSMGR_ECC_EMAC0_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_ECC_EMAC0_EN field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_ECC_EMAC0_EN register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET_MSK 0x00000002 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJS register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET_MSK 0x00000004 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOINJD register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET_MSK 0x00000008 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJS register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOINJD register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET_MSK 0x00000020 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFOSERR register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET_MSK 0x00000040 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_SYSMGR_ECC_EMAC0_TXFIFODERR field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_TXFIFODERR_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_SYSMGR_ECC_EMAC0_TXFIFODERR register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET_MSK 0x00000080 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFOSERR register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_WIDTH 1 |
The width in bits of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET_MSK 0x00000100 |
The mask used to set the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_RESET 0x0 |
The reset value of the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SYSMGR_ECC_EMAC0_RXFIFODERR field value from a register.
#define ALT_SYSMGR_ECC_EMAC0_RXFIFODERR_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SYSMGR_ECC_EMAC0_RXFIFODERR register field value suitable for setting the register.
#define ALT_SYSMGR_ECC_EMAC0_OFST 0x10 |
The byte offset of the ALT_SYSMGR_ECC_EMAC0 register from the beginning of the component.
typedef struct ALT_SYSMGR_ECC_EMAC0_s ALT_SYSMGR_ECC_EMAC0_t |
The typedef declaration for register ALT_SYSMGR_ECC_EMAC0.