Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dma_intr_en

Description

Enables corresponding interrupt bit in dma interrupt register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR
[1] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0
[2] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1
[3] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2
[4] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3
[5] ??? Unknown UNDEFINED
[6] RW 0x0 ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE
[31:7] ??? Unknown UNDEFINED

Field : target_error

Controller initiator interface received an ERROR target response for a transaction.

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB   0
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB   0
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK   0x00000001
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK   0xfffffffe
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET(value)   (((value) << 0) & 0x00000001)
 

Field : desc_comp_channel0

Enable bit to indicates CMD-DMA channel 0 descriptor execution done (updated when interrupt bit in cmd flags set).

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK   0x00000002
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK   0xfffffffd
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET(value)   (((value) << 1) & 0x00000002)
 

Field : desc_comp_channel1

Enable bit to indicates CMD-DMA channel 1 descriptor execution done (updated when interrupt bit in cmd flags set).

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB   2
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB   2
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK   0x00000004
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK   0xfffffffb
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET(value)   (((value) << 2) & 0x00000004)
 

Field : desc_comp_channel2

Enable bit to indicates CMD-DMA channel 2 descriptor execution done (updated when interrupt bit in cmd flags set).

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB   3
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB   3
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK   0x00000008
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK   0xfffffff7
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET(value)   (((value) << 3) & 0x00000008)
 

Field : desc_comp_channel3

Enable bit to indicates CMD-DMA channel 3 descriptor execution done (updated when interrupt bit in cmd flags set).

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB   4
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB   4
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK   0x00000010
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK   0xffffffef
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET(value)   (((value) << 4) & 0x00000010)
 

Field : cmddma_idle

Interrupt processor when command DMA becomes IDLE after completing all

descriptors.

Field Access Macros:

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB   6
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB   6
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH   1
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK   0x00000040
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK   0xffffffbf
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET   0x0
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET(value)   (((value) << 6) & 0x00000040)
 

Data Structures

struct  ALT_NAND_DMA_DMA_INTR_EN_s
 

Macros

#define ALT_NAND_DMA_DMA_INTR_EN_RESET   0x00000000
 
#define ALT_NAND_DMA_DMA_INTR_EN_OFST   0x30
 

Typedefs

typedef struct
ALT_NAND_DMA_DMA_INTR_EN_s 
ALT_NAND_DMA_DMA_INTR_EN_t
 

Data Structure Documentation

struct ALT_NAND_DMA_DMA_INTR_EN_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NAND_DMA_DMA_INTR_EN.

Data Fields
uint32_t target_error: 1 ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR
uint32_t desc_comp_channel0: 1 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0
uint32_t desc_comp_channel1: 1 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1
uint32_t desc_comp_channel2: 1 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2
uint32_t desc_comp_channel3: 1 ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3
uint32_t __pad0__: 1 UNDEFINED
uint32_t cmddma_idle: 1 ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE
uint32_t __pad1__: 25 UNDEFINED

Macro Definitions

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_LSB   0

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_MSB   0

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET_MSK   0x00000001

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_CLR_MSK   0xfffffffe

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_NAND_DMA_DMA_INTR_EN_TGT_ERROR register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_LSB   1

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_MSB   1

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET_MSK   0x00000002

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_CLR_MSK   0xfffffffd

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL0 register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_LSB   2

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_MSB   2

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET_MSK   0x00000004

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_CLR_MSK   0xfffffffb

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL1 register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_LSB   3

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_MSB   3

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET_MSK   0x00000008

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_CLR_MSK   0xfffffff7

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL2 register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_LSB   4

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_MSB   4

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET_MSK   0x00000010

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_CLR_MSK   0xffffffef

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_NAND_DMA_DMA_INTR_EN_DESC_COMP_CHANNEL3 register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_LSB   6

The Least Significant Bit (LSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_MSB   6

The Most Significant Bit (MSB) position of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_WIDTH   1

The width in bits of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET_MSK   0x00000040

The mask used to set the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_CLR_MSK   0xffffffbf

The mask used to clear the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_RESET   0x0

The reset value of the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE field value from a register.

#define ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_NAND_DMA_DMA_INTR_EN_CMDDMA_IDLE register field value suitable for setting the register.

#define ALT_NAND_DMA_DMA_INTR_EN_RESET   0x00000000

The reset value of the ALT_NAND_DMA_DMA_INTR_EN register.

#define ALT_NAND_DMA_DMA_INTR_EN_OFST   0x30

The byte offset of the ALT_NAND_DMA_DMA_INTR_EN register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NAND_DMA_DMA_INTR_EN.