![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Clock Enable Register
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_EN |
[15:1] | ??? | 0x0 | UNDEFINED |
[16] | RW | 0x0 | ALT_SDMMC_CLKENA_CCLK_LOW_POWER |
[31:17] | ??? | 0x0 | UNDEFINED |
Field : cclk_enable | ||||||||||
Clock-enable control for up to 16 SD card clocks and one MMC card clock supported. 0-Clock disabled 1-Clock enabled In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_enable[0] is used. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_LSB 0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_MSB 0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_EN_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : cclk_low_power | ||||||||||
Low-power control for up to 16 SD card clocks and one MMC card clock supported. 0-Non-low-power mode 1-Low-power mode; stop clock when card in IDLE (should be normally set to only MMC and SD memory cards; for SDIO cards, if interrupts must be detected, clock should not be stopped). In MMC-Ver3.3-only mode, since there is only one cclk_out, only cclk_low_power[0] is used. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0 | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET(value) (((value) & 0x00010000) >> 16) | |||||||||
#define | ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET(value) (((value) << 16) & 0x00010000) | |||||||||
Data Structures | |
struct | ALT_SDMMC_CLKENA_s |
Macros | |
#define | ALT_SDMMC_CLKENA_RESET 0x00000000 |
#define | ALT_SDMMC_CLKENA_OFST 0x10 |
Typedefs | |
typedef struct ALT_SDMMC_CLKENA_s | ALT_SDMMC_CLKENA_t |
struct ALT_SDMMC_CLKENA_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SDMMC_CLKENA.
Data Fields | ||
---|---|---|
uint32_t | cclk_enable: 1 | ALT_SDMMC_CLKENA_CCLK_EN |
uint32_t | __pad0__: 15 | UNDEFINED |
uint32_t | cclk_low_power: 1 | ALT_SDMMC_CLKENA_CCLK_LOW_POWER |
uint32_t | __pad1__: 15 | UNDEFINED |
#define ALT_SDMMC_CLKENA_CCLK_EN_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
SD/MMC Disable
#define ALT_SDMMC_CLKENA_CCLK_EN_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_EN
SD/MMC Enable
#define ALT_SDMMC_CLKENA_CCLK_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field.
#define ALT_SDMMC_CLKENA_CCLK_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_EN register field.
#define ALT_SDMMC_CLKENA_CCLK_EN_WIDTH 1 |
The width in bits of the ALT_SDMMC_CLKENA_CCLK_EN register field.
#define ALT_SDMMC_CLKENA_CCLK_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_SDMMC_CLKENA_CCLK_EN register field value.
#define ALT_SDMMC_CLKENA_CCLK_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SDMMC_CLKENA_CCLK_EN register field value.
#define ALT_SDMMC_CLKENA_CCLK_EN_RESET 0x0 |
The reset value of the ALT_SDMMC_CLKENA_CCLK_EN register field.
#define ALT_SDMMC_CLKENA_CCLK_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SDMMC_CLKENA_CCLK_EN field value from a register.
#define ALT_SDMMC_CLKENA_CCLK_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SDMMC_CLKENA_CCLK_EN register field value suitable for setting the register.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_DISD 0x0 |
Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
Non-low-power mode
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_E_END 0x1 |
Enumerated value for register field ALT_SDMMC_CLKENA_CCLK_LOW_POWER
Low-power mode
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_WIDTH 1 |
The width in bits of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET_MSK 0x00010000 |
The mask used to set the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_RESET 0x0 |
The reset value of the ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_SDMMC_CLKENA_CCLK_LOW_POWER field value from a register.
#define ALT_SDMMC_CLKENA_CCLK_LOW_POWER_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_SDMMC_CLKENA_CCLK_LOW_POWER register field value suitable for setting the register.
#define ALT_SDMMC_CLKENA_RESET 0x00000000 |
The reset value of the ALT_SDMMC_CLKENA register.
#define ALT_SDMMC_CLKENA_OFST 0x10 |
The byte offset of the ALT_SDMMC_CLKENA register from the beginning of the component.
typedef struct ALT_SDMMC_CLKENA_s ALT_SDMMC_CLKENA_t |
The typedef declaration for register ALT_SDMMC_CLKENA.