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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
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[15:0] | R | 0x0 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL |
[31:16] | ??? | Unknown | UNDEFINED |
Field : COUNTERS_0_VAL | |
Register Val is a read-only register that is always present. The register containsthe statistics counter value either pending StatAlarm output, or when statisticscollection is suspended subsequent to triggers or signal statSuspend. Field Access Macros: | |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET(value) (((value) & 0x0000ffff) >> 0) |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET(value) (((value) << 0) & 0x0000ffff) |
Data Structures | |
struct | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_s |
Macros | |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_RESET 0x00000000 |
#define | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_OFST 0x140 |
Typedefs | |
typedef struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_s | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_t |
struct ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL.
Data Fields | ||
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const uint32_t | COUNTERS_0_VAL: 16 | ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL |
uint32_t | __pad0__: 16 | UNDEFINED |
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_WIDTH 16 |
The width in bits of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET_MSK 0x0000ffff |
The mask used to set the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_CLR_MSK 0xffff0000 |
The mask used to clear the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_RESET 0x0 |
The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_GET | ( | value | ) | (((value) & 0x0000ffff) >> 0) |
Extracts the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL field value from a register.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL_SET | ( | value | ) | (((value) << 0) & 0x0000ffff) |
Produces a ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_CNTRS_0_VAL register field value suitable for setting the register.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_RESET 0x00000000 |
The reset value of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL register.
#define ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL_OFST 0x140 |
The byte offset of the ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL register from the beginning of the component.
The typedef declaration for register ALT_NOC_MPU_PRB_EMACS_MAIN_CNTRS_0_VAL.