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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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This is a multi-function register. This register holds receives and transmit data and controls the least-signficant 8 bits of the baud rate divisor.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[7:0] | RW | 0x0 | Value |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : Value - value | |
Receive Buffer Register: This register contains the data byte received on the serial input port (uart_rxd). The data in this register is valid only if the Data Ready ( bit [0] in the Line Status Register(LSR)) is set to 1. If FIFOs are disabled(bit[0] of Register FCR is set to 0) the data in the RBR must be read before the next data arrives, otherwise it will be overwritten, resulting in an overrun error. If FIFOs are enabled(bit [0] of Register FCR is set to 1) this register accesses the head of the receive FIFO. If the receive FIFO is full, and this register is not read before the next data character arrives, then the data already in the FIFO will be preserved but any incoming data will be lost. An overrun error will also occur. Transmit Holding Register: This register contains data to be transmitted on the serial output port. Data should only be written to the THR when the THR Empty bit [5] of the LSR Register is set to 1. If FIFOs are disabled (bit [0] of Register FCR) is set to 0 and THRE is set to 1, writing a single character to the THR clears the THRE. Any additional writes to the THR before the THRE is set again causes the THR data to be overwritten. If FIFO's are enabled bit [0] of Register FCR is set to 1 and THRE is set up to 128 characters of data may be written to the THR before the FIFO is full. Any attempt to write data when the FIFO is full results in the write data being lost. Divisor Latch Low: This register makes up the lower 8-bits of a 16-bit, Read/write, Divisor Latch register that contains the baud rate divisor for the UART. This register may only be accessed when the DLAB bit [7] of the LCR Register is set to 1. The output baud rate is equal to the serial clock l4_sp_clk frequency divided by sixteen times the value of the baud rate divisor, as follows: baud rate = (serial clock freq) / (16 * divisor) Note that with the Divisor Latch Registers (DLL and DLH) set to zero, the baud clock is disabled and no serial communications will occur. Also, once the DLL is set, at least 8 l4_sp_clk clock cycles should be allowed to pass before transmitting or receiving data. Field Access Macros: | |
#define | ALT_UART_RBR_THR_DLL_VALUE_LSB 0 |
#define | ALT_UART_RBR_THR_DLL_VALUE_MSB 7 |
#define | ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 |
#define | ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff |
#define | ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 |
#define | ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 |
#define | ALT_UART_RBR_THR_DLL_VALUE_GET(value) (((value) & 0x000000ff) >> 0) |
#define | ALT_UART_RBR_THR_DLL_VALUE_SET(value) (((value) << 0) & 0x000000ff) |
Data Structures | |
struct | ALT_UART_RBR_THR_DLL_s |
Macros | |
#define | ALT_UART_RBR_THR_DLL_OFST 0x0 |
#define | ALT_UART_RBR_THR_DLL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) |
Typedefs | |
typedef struct ALT_UART_RBR_THR_DLL_s | ALT_UART_RBR_THR_DLL_t |
struct ALT_UART_RBR_THR_DLL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_UART_RBR_THR_DLL.
Data Fields | ||
---|---|---|
uint32_t | value: 8 | Value |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_UART_RBR_THR_DLL_VALUE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field.
#define ALT_UART_RBR_THR_DLL_VALUE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_UART_RBR_THR_DLL_VALUE register field.
#define ALT_UART_RBR_THR_DLL_VALUE_WIDTH 8 |
The width in bits of the ALT_UART_RBR_THR_DLL_VALUE register field.
#define ALT_UART_RBR_THR_DLL_VALUE_SET_MSK 0x000000ff |
The mask used to set the ALT_UART_RBR_THR_DLL_VALUE register field value.
#define ALT_UART_RBR_THR_DLL_VALUE_CLR_MSK 0xffffff00 |
The mask used to clear the ALT_UART_RBR_THR_DLL_VALUE register field value.
#define ALT_UART_RBR_THR_DLL_VALUE_RESET 0x0 |
The reset value of the ALT_UART_RBR_THR_DLL_VALUE register field.
#define ALT_UART_RBR_THR_DLL_VALUE_GET | ( | value | ) | (((value) & 0x000000ff) >> 0) |
Extracts the ALT_UART_RBR_THR_DLL_VALUE field value from a register.
#define ALT_UART_RBR_THR_DLL_VALUE_SET | ( | value | ) | (((value) << 0) & 0x000000ff) |
Produces a ALT_UART_RBR_THR_DLL_VALUE register field value suitable for setting the register.
#define ALT_UART_RBR_THR_DLL_OFST 0x0 |
The byte offset of the ALT_UART_RBR_THR_DLL register from the beginning of the component.
#define ALT_UART_RBR_THR_DLL_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_RBR_THR_DLL_OFST)) |
The address of the ALT_UART_RBR_THR_DLL register.
typedef struct ALT_UART_RBR_THR_DLL_s ALT_UART_RBR_THR_DLL_t |
The typedef declaration for register ALT_UART_RBR_THR_DLL.