Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 0 (MAC Configuration Register) - MAC_Configuration

Description

The MAC Configuration register establishes receive and transmit operating modes.

Register Layout

Bits Access Reset Description
[1:0] RW 0x0 Preamble Length for Transmit Frames
[2] RW 0x0 Receiver Enable
[3] RW 0x0 Transmitter Enable
[4] RW 0x0 Deferral Check
[6:5] RW 0x0 Back-Off Limit
[7] RW 0x0 Automatic Pad or CRC Stripping
[8] RW 0x0 Link Up or Down
[9] RW 0x0 Disable Retry
[10] RW 0x0 Checksum Offload
[11] RW 0x0 Duplex Mode
[12] RW 0x0 Loopback Mode
[13] RW 0x0 Disable Receive Own
[14] RW 0x0 Speed
[15] RW 0x0 Port Select
[16] RW 0x0 Disable Carrier Sense During Transmission
[19:17] RW 0x0 Inter-Frame Gap
[20] RW 0x0 Jumbo Frame Enable
[21] RW 0x0 Frame Burst Enable
[22] RW 0x0 Jabber Disable
[23] RW 0x0 Watchdog Disable
[24] RW 0x0 Transmit Configuration in RGMII, SGMII, or SMII
[25] RW 0x0 CRC Stripping of Type Frames
[26] ??? 0x0 UNDEFINED
[27] RW 0x0 IEEE 802.3as support for 2K packets Enable
[31:28] ??? 0x0 UNDEFINED

Field : Preamble Length for Transmit Frames - prelen

These bits control the number of preamble bytes that are added to the beginning of every Transmit frame. The preamble reduction occurs only when the MAC is operating

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES 0x0 Preamble 7 Bytes
ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES 0x1 Preamble 5 Bytes
ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES 0x2 Preamble 3 Bytes

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB   0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB   1
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH   2
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK   0x00000003
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK   0xfffffffc
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET(value)   (((value) << 0) & 0x00000003)
 

Field : Receiver Enable - re

When this bit is set, the receiver state machine of the MAC is enabled for receiving frames from the GMII or MII. When this bit is reset, the MAC receive state machine is disabled after the completion of the reception of the current frame, and does not receive any further frames from the GMII or MII.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD 0x0 MAC receive state machine disabled
ALT_EMAC_GMAC_MAC_CFG_RE_E_END 0x1 MAC receive state machine enabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB   2
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB   2
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_MAC_CFG_RE_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Transmitter Enable - te

When this bit is set, the transmit state machine of the MAC is enabled for transmission on the GMII or MII. When this bit is reset, the MAC transmit state machine is disabled after the completion of the transmission of the current frame, and does not transmit any further frames.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD 0x0 MAC transmit state machine disabled
ALT_EMAC_GMAC_MAC_CFG_TE_E_END 0x1 MAC transmit state machine disabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB   3
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB   3
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_MAC_CFG_TE_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Deferral Check - dc

When this bit is set, the deferral check function is enabled in the MAC. The MAC issues a Frame Abort status, along with the excessive deferral error bit set in the transmit frame status, when the transmit state machine is deferred for more than 24,288 bit times in the 10 or 100 Mbps mode. If the MAC is configured for 1000 Mbps operation, or if the Jumbo frame mode is enabled in the 10 or 100 Mbps mode, the threshold for deferral is 155,680 bits times. Deferral begins when the transmitter is ready to transmit, but is prevented because of an active carrier sense signal (CRS) on GMII or MII. Defer time is not cumulative. When the transmitter defers for 10,000 bit times, it transmits, collides, backs off, and then defers again after completion of back-off. The deferral timer resets to 0 and restarts.

When this bit is reset, the deferral check function is disabled and the MAC defers until the CRS signal goes inactive. This bit is applicable only in the half-duplex mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_DC_E_END 0x1 Deferral Check Enabled
ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD 0x0 Deferral Check Disabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB   4
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB   4
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_MAC_CFG_DC_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Back-Off Limit - bl

The Back-Off limit determines the random integer number (r) of slot time delays (4,096 bit times for 1000 Mbps and 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after a collision. This bit is applicable only in the half-duplex mode.

  • 00: k = min (n, 10)
  • 01: k = min (n, 8)
  • 10: k = min (n, 4)
  • 11: k = min (n, 1)

where n = retransmission attempt. The random integer r takes the value in the

range 0 <= r < kth power of 2

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10 0x0 k = min (n, 10)
ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8 0x1 k = min (n, 8)
ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4 0x2 k = min (n, 4)
ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1 0x3 k = min (n, 1)

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1   0x3
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB   5
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB   6
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH   2
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK   0x00000060
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK   0xffffff9f
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_GET(value)   (((value) & 0x00000060) >> 5)
 
#define ALT_EMAC_GMAC_MAC_CFG_BL_SET(value)   (((value) << 5) & 0x00000060)
 

Field : Automatic Pad or CRC Stripping - acs

When this bit is set, the MAC strips the Pad or FCS field on the incoming frames only if the value of the length field is less than 1,536 bytes. All received frames with length field greater than or equal to 1,536 bytes are passed to the application without stripping the Pad or FCS field.

When this bit is reset, the MAC passes all incoming frames, without modifying them, to the Host.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD 0x0 Disable Automatic Pad CRC Stripping
ALT_EMAC_GMAC_MAC_CFG_ACS_E_END 0x1 Enable Automatic Pad CRC Stripping

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB   7
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB   7
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK   0x00000080
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Link Up or Down - lud

This bit indicates whether the link is up or down during the transmission of configuration in the RGMII, SGMII, or SMII interface

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD 0x0 Link Down
ALT_EMAC_GMAC_MAC_CFG_LUD_E_END 0x1 Link Up

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB   8
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB   8
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Disable Retry - dr

When this bit is set, the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface, the MAC ignores the current frame transmission and reports a Frame Abort with excessive collision error in the transmit frame status.

When this bit is reset, the MAC attempts retries based on the settings of the BL field (Bits [6:5]). This bit is applicable only in the half-duplex mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD 0x1 MAC attempts one transmission
ALT_EMAC_GMAC_MAC_CFG_DR_E_END 0x0 MAC attempts retries per bl Field

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB   9
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB   9
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_MAC_CFG_DR_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Checksum Offload - ipc

When this bit is set, the MAC calculates the 16-bit ones complement of the ones complement sum of all received Ethernet frame payloads. It also checks whether the IPv4 Header checksum (assumed to be bytes 2526 or 2930 (VLAN-tagged) of the received Ethernet frame) is correct for the received frame and gives the status in the receive status word. The MAC also appends the 16-bit checksum calculated for the IP header datagram payload (bytes after the IPv4 header) and appends it to the Ethernet frame transferred to the application (when Type 2 COE is deselected).

When this bit is reset, this function is disabled.

When Type 2 COE is selected, this bit, when set, enables the IPv4 header checksum checking and IPv4 or IPv6 TCP, UDP, or ICMP payload checksum checking. When this bit is reset, the COE function in the receiver is disabled and the corresponding PCE and IP HCE status bits are always cleared.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_IPC_E_END 0x1 Checksum Enabled
ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD 0x0 Checksum Disabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB   10
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB   10
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Duplex Mode - dm

When this bit is set, the MAC operates in the full-duplex mode where it can transmit and receive simultaneously.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_DM_E_END 0x1 MAC Full Duplex Enabled
ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD 0x0 MAC Full Duplex Disabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB   11
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB   11
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_MAC_CFG_DM_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Loopback Mode - lm

When this bit is set, the MAC operates in the loopback mode at GMII or MII. The (G)MII Receive clock input is required for the loopback to work properly, because the Transmit clock is not looped-back internally.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD 0x0 Disable Loop Back
ALT_EMAC_GMAC_MAC_CFG_LM_E_END 0x1 Enable Loop Back

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB   12
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB   12
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_MAC_CFG_LM_SET(value)   (((value) << 12) & 0x00001000)
 

Field : Disable Receive Own - do

When this bit is set, the MAC disables the reception of frames when the gmii_txen_o is asserted in the half-duplex mode.

When this bit is reset, the MAC receives all packets that are given by the PHY while transmitting.

This bit is not applicable if the MAC is operating in the full-duplex mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_DO_E_END 0x0 MAC Enables Reception of Frames
ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD 0x1 MAC Disables Reception of Frames

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB   13
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB   13
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_MAC_CFG_DO_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Speed - fes

This bit selects the speed in the RMII/RGMII interface:

  • 0: 10 Mbps
  • 1: 100 Mbps

This bit generates link speed encoding when TC (Bit 24) is set in the RGMII, SMII, or SGMII mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10 0x0 Speed = 10 Mbps
ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100 0x1 Speed = 100 Mbps

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB   14
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB   14
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK   0x00004000
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_GMAC_MAC_CFG_FES_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Port Select - ps

This bit selects between GMII and MII

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL 0x0 GMII 1000 Mbps
ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL 0x1 MII 10/100 Mbps

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB   15
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB   15
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK   0x00008000
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_GMAC_MAC_CFG_PS_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Disable Carrier Sense During Transmission - dcrs

When set high, this bit makes the MAC transmitter ignore the (G)MII CRS signal during frame transmission in the half-duplex mode. This request results in no errors generated because of Loss of Carrier or No Carrier during such transmission. When this bit is low, the MAC transmitter generates such errors because of Carrier Sense and can even abort the transmissions.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD 0x0 MAC Tx Gen. Err. No Carrier
ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END 0x1 MAC Tx Ignores (G)MII Crs Signal

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB   16
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB   16
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Inter-Frame Gap - ifg

These bits control the minimum IFG between frames during transmission.

In the half-duplex mode, the minimum IFG can be configured only for 64 bit times (IFG = 100). Lower values are not considered. In the 1000-Mbps mode, the minimum IFG supported is 80 bit times (and above).

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES 0x0 Inter Frame Gap 96 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES 0x1 Inter Frame Gap 88 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES 0x2 Inter Frame Gap 80 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES 0x3 Inter Frame Gap 72 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES 0x4 Inter Frame Gap 64 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES 0x5 Inter Frame Gap 56 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES 0x6 Inter Frame Gap 48 bit times
ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES 0x7 Inter Frame Gap 40 bit times

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES   0x2
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES   0x3
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES   0x4
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES   0x5
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES   0x6
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES   0x7
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB   17
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB   19
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH   3
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK   0x000e0000
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK   0xfff1ffff
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : Jumbo Frame Enable - je

When this bit is set, the MAC allows Jumbo frames of 9,018 bytes (9,022 bytes for VLAN tagged frames) without reporting a giant frame error in the receive frame status.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD 0x0 Report Jumbo Frame Error
ALT_EMAC_GMAC_MAC_CFG_JE_E_END 0x1 Ignore Jumbo Frame Error

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB   20
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB   20
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_MAC_CFG_JE_SET(value)   (((value) << 20) & 0x00100000)
 

Field : Frame Burst Enable - be

When this bit is set, the MAC allows frame bursting during transmission in the GMII half-duplex mode.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD 0x0 Frame Burst Enable OFF
ALT_EMAC_GMAC_MAC_CFG_BE_E_END 0x1 Frame Burst Enable ON

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB   21
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB   21
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_MAC_CFG_BE_SET(value)   (((value) << 21) & 0x00200000)
 

Field : Jabber Disable - jd

When this bit is set, the MAC disables the jabber timer on the transmitter. The MAC can transfer frames of up to 16,384 bytes.

When this bit is reset, the MAC cuts off the transmitter if the application sends out more than 2,048 bytes of data (10,240 if JE is set high) during transmission.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_JD_E_END 0x0 MAC cuts off TX > 2048
ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD 0x1 Jabber Timer Disabled

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB   22
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB   22
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK   0x00400000
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_GMAC_MAC_CFG_JD_SET(value)   (((value) << 22) & 0x00400000)
 

Field : Watchdog Disable - wd

When this bit is set, the MAC disables the watchdog timer on the receiver. The MAC can receive frames of up to 16,384 bytes.

When this bit is reset, the MAC does not allow more than 2,048 bytes (10,240 if JE is set high) of the frame being received. The MAC cuts off any bytes received after 2,048 bytes.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_WD_E_END 0x0 Enable MAC cutoff > 2048Bytes
ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD 0x1 Disable Watchdog

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB   23
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB   23
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK   0x00800000
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_GMAC_MAC_CFG_WD_SET(value)   (((value) << 23) & 0x00800000)
 

Field : Transmit Configuration in RGMII, SGMII, or SMII - tc

When set, this bit enables the transmission of duplex mode, link speed, and link up or down information to the PHY in the RGMII. When this bit is reset, no such information is driven to the PHY.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_TC_E_END 0x1 Enables Transmission of duplex
ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD 0x0 Disables Transmission to Phy

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB   24
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB   24
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_MAC_CFG_TC_SET(value)   (((value) << 24) & 0x01000000)
 

Field : CRC Stripping of Type Frames - cst

When set, the last 4 bytes (FCS) of all frames of Ether type (type field greater than 0x0600) are stripped and dropped before forwarding the frame to the application. This function is not valid when the IP Checksum Engine (Type 1) is enabled in the MAC receiver.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD 0x0 Strip Ether Frames Off
ALT_EMAC_GMAC_MAC_CFG_CST_E_END 0x1 Strip Ether Frames On

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END   0x1
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB   25
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB   25
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_MAC_CFG_CST_SET(value)   (((value) << 25) & 0x02000000)
 

Field : IEEE 802.3as support for 2K packets Enable - twokpe

When set, the MAC considers all frames, with up to 2,000 bytes length, as normal packets. When Bit 20 (Jumbo Enable) is not set, the MAC considers all received frames of size more than 2K bytes as Giant frames.

When this bit is reset and Bit 20 (Jumbo Enable) is not set, the MAC considers all received frames of size more than 1,518 bytes (1,522 bytes for tagged) as Giant frames.

When Bit 20 (Jumbo Enable) is set, setting this bit has no effect on Giant Frame status.

Field Access Macros:

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB   27
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB   27
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH   1
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK   0x08000000
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK   0xf7ffffff
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET(value)   (((value) << 27) & 0x08000000)
 

Data Structures

struct  ALT_EMAC_GMAC_MAC_CFG_s
 

Macros

#define ALT_EMAC_GMAC_MAC_CFG_OFST   0x0
 
#define ALT_EMAC_GMAC_MAC_CFG_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_MAC_CFG_s 
ALT_EMAC_GMAC_MAC_CFG_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_MAC_CFG_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_MAC_CFG.

Data Fields
uint32_t prelen: 2 Preamble Length for Transmit Frames
uint32_t re: 1 Receiver Enable
uint32_t te: 1 Transmitter Enable
uint32_t dc: 1 Deferral Check
uint32_t bl: 2 Back-Off Limit
uint32_t acs: 1 Automatic Pad or CRC Stripping
uint32_t lud: 1 Link Up or Down
uint32_t dr: 1 Disable Retry
uint32_t ipc: 1 Checksum Offload
uint32_t dm: 1 Duplex Mode
uint32_t lm: 1 Loopback Mode
uint32_t do_: 1 Disable Receive Own
uint32_t fes: 1 Speed
uint32_t ps: 1 Port Select
uint32_t dcrs: 1 Disable Carrier Sense During Transmission
uint32_t ifg: 3 Inter-Frame Gap
uint32_t je: 1 Jumbo Frame Enable
uint32_t be: 1 Frame Burst Enable
uint32_t jd: 1 Jabber Disable
uint32_t wd: 1 Watchdog Disable
uint32_t tc: 1 Transmit Configuration in RGMII, SGMII, or SMII
uint32_t cst: 1 CRC Stripping of Type Frames
uint32_t __pad0__: 1 UNDEFINED
uint32_t twokpe: 1 IEEE 802.3as support for 2K packets Enable
uint32_t __pad1__: 4 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM7BYTES   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

Preamble 7 Bytes

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM5BYTES   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

Preamble 5 Bytes

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_E_PREAM3BYTES   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PRELEN

Preamble 3 Bytes

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET_MSK   0x00000003

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_CLR_MSK   0xfffffffc

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_PRELEN register field.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_EMAC_GMAC_MAC_CFG_PRELEN field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_PRELEN_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_EMAC_GMAC_MAC_CFG_PRELEN register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE

MAC receive state machine disabled

#define ALT_EMAC_GMAC_MAC_CFG_RE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_RE

MAC receive state machine enabled

#define ALT_EMAC_GMAC_MAC_CFG_RE_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_RE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RE_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_RE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_RE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_RE register field.

#define ALT_EMAC_GMAC_MAC_CFG_RE_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_MAC_CFG_RE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_RE_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_MAC_CFG_RE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE

MAC transmit state machine disabled

#define ALT_EMAC_GMAC_MAC_CFG_TE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TE

MAC transmit state machine disabled

#define ALT_EMAC_GMAC_MAC_CFG_TE_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TE_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TE_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TE_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_MAC_CFG_TE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC

Deferral Check Enabled

#define ALT_EMAC_GMAC_MAC_CFG_DC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DC

Deferral Check Disabled

#define ALT_EMAC_GMAC_MAC_CFG_DC_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DC_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DC register field.

#define ALT_EMAC_GMAC_MAC_CFG_DC_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DC_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_MAC_CFG_DC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMTR10   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

k = min (n, 10)

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMIRT8   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

k = min (n, 8)

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR4   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

k = min (n, 4)

#define ALT_EMAC_GMAC_MAC_CFG_BL_E_BACKLIMITR1   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BL

k = min (n, 1)

#define ALT_EMAC_GMAC_MAC_CFG_BL_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_SET_MSK   0x00000060

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BL register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BL_CLR_MSK   0xffffff9f

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BL register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BL_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_BL register field.

#define ALT_EMAC_GMAC_MAC_CFG_BL_GET (   value)    (((value) & 0x00000060) >> 5)

Extracts the ALT_EMAC_GMAC_MAC_CFG_BL field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_BL_SET (   value)    (((value) << 5) & 0x00000060)

Produces a ALT_EMAC_GMAC_MAC_CFG_BL register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS

Disable Automatic Pad CRC Stripping

#define ALT_EMAC_GMAC_MAC_CFG_ACS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_ACS

Enable Automatic Pad CRC Stripping

#define ALT_EMAC_GMAC_MAC_CFG_ACS_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_ACS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_ACS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_ACS register field.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_GMAC_MAC_CFG_ACS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_ACS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_GMAC_MAC_CFG_ACS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD

Link Down

#define ALT_EMAC_GMAC_MAC_CFG_LUD_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LUD

Link Up

#define ALT_EMAC_GMAC_MAC_CFG_LUD_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LUD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LUD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_LUD register field.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_MAC_CFG_LUD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_LUD_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_MAC_CFG_LUD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR

MAC attempts one transmission

#define ALT_EMAC_GMAC_MAC_CFG_DR_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DR

MAC attempts retries per bl Field

#define ALT_EMAC_GMAC_MAC_CFG_DR_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DR_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DR register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DR register field.

#define ALT_EMAC_GMAC_MAC_CFG_DR_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DR field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DR_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_MAC_CFG_DR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC

Checksum Enabled

#define ALT_EMAC_GMAC_MAC_CFG_IPC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IPC

Checksum Disabled

#define ALT_EMAC_GMAC_MAC_CFG_IPC_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IPC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IPC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_IPC register field.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_MAC_CFG_IPC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_IPC_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_MAC_CFG_IPC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM

MAC Full Duplex Enabled

#define ALT_EMAC_GMAC_MAC_CFG_DM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DM

MAC Full Duplex Disabled

#define ALT_EMAC_GMAC_MAC_CFG_DM_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DM_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DM register field.

#define ALT_EMAC_GMAC_MAC_CFG_DM_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DM field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DM_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_MAC_CFG_DM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM

Disable Loop Back

#define ALT_EMAC_GMAC_MAC_CFG_LM_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_LM

Enable Loop Back

#define ALT_EMAC_GMAC_MAC_CFG_LM_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_LM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LM_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_LM register field value.

#define ALT_EMAC_GMAC_MAC_CFG_LM_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_LM register field.

#define ALT_EMAC_GMAC_MAC_CFG_LM_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_MAC_CFG_LM field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_LM_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_MAC_CFG_LM register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO

MAC Enables Reception of Frames

#define ALT_EMAC_GMAC_MAC_CFG_DO_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DO

MAC Disables Reception of Frames

#define ALT_EMAC_GMAC_MAC_CFG_DO_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DO register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DO_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DO register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DO_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DO register field.

#define ALT_EMAC_GMAC_MAC_CFG_DO_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DO field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DO_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_MAC_CFG_DO register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED10   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES

Speed = 10 Mbps

#define ALT_EMAC_GMAC_MAC_CFG_FES_E_SPEED100   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_FES

Speed = 100 Mbps

#define ALT_EMAC_GMAC_MAC_CFG_FES_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_FES register field value.

#define ALT_EMAC_GMAC_MAC_CFG_FES_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_FES register field value.

#define ALT_EMAC_GMAC_MAC_CFG_FES_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_FES register field.

#define ALT_EMAC_GMAC_MAC_CFG_FES_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_GMAC_MAC_CFG_FES field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_FES_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_GMAC_MAC_CFG_FES register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_GMII1000SEL   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS

GMII 1000 Mbps

#define ALT_EMAC_GMAC_MAC_CFG_PS_E_MII10100SEL   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_PS

MII 10/100 Mbps

#define ALT_EMAC_GMAC_MAC_CFG_PS_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_PS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PS_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_PS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_PS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_PS register field.

#define ALT_EMAC_GMAC_MAC_CFG_PS_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_GMAC_MAC_CFG_PS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_PS_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_GMAC_MAC_CFG_PS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS

MAC Tx Gen. Err. No Carrier

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_DCRS

MAC Tx Ignores (G)MII Crs Signal

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_DCRS register field value.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_DCRS register field.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_MAC_CFG_DCRS field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_DCRS_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_MAC_CFG_DCRS register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG96BITTIMES   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 96 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG88BITTIMES   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 88 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG80BITTIMES   0x2

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 80 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG72BITTIMES   0x3

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 72 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG64BITTIMES   0x4

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 64 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG56BITTIMES   0x5

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 56 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG48BITTIMES   0x6

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 48 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_E_IFG40BITTIMES   0x7

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_IFG

Inter Frame Gap 40 bit times

#define ALT_EMAC_GMAC_MAC_CFG_IFG_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_WIDTH   3

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET_MSK   0x000e0000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_IFG register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_IFG register field value.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_IFG register field.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_EMAC_GMAC_MAC_CFG_IFG field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_IFG_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_EMAC_GMAC_MAC_CFG_IFG register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE

Report Jumbo Frame Error

#define ALT_EMAC_GMAC_MAC_CFG_JE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JE

Ignore Jumbo Frame Error

#define ALT_EMAC_GMAC_MAC_CFG_JE_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JE_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_JE register field.

#define ALT_EMAC_GMAC_MAC_CFG_JE_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_MAC_CFG_JE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_JE_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_MAC_CFG_JE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE

Frame Burst Enable OFF

#define ALT_EMAC_GMAC_MAC_CFG_BE_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_BE

Frame Burst Enable ON

#define ALT_EMAC_GMAC_MAC_CFG_BE_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_BE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BE_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_BE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_BE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_BE register field.

#define ALT_EMAC_GMAC_MAC_CFG_BE_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_MAC_CFG_BE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_BE_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_MAC_CFG_BE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD

MAC cuts off TX > 2048

#define ALT_EMAC_GMAC_MAC_CFG_JD_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_JD

Jabber Timer Disabled

#define ALT_EMAC_GMAC_MAC_CFG_JD_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_JD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JD_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_JD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_JD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_JD register field.

#define ALT_EMAC_GMAC_MAC_CFG_JD_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_GMAC_MAC_CFG_JD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_JD_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_GMAC_MAC_CFG_JD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_END   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD

Enable MAC cutoff > 2048Bytes

#define ALT_EMAC_GMAC_MAC_CFG_WD_E_DISD   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_WD

Disable Watchdog

#define ALT_EMAC_GMAC_MAC_CFG_WD_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_WD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_WD_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_WD register field value.

#define ALT_EMAC_GMAC_MAC_CFG_WD_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_WD register field.

#define ALT_EMAC_GMAC_MAC_CFG_WD_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_GMAC_MAC_CFG_WD field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_WD_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_GMAC_MAC_CFG_WD register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC

Enables Transmission of duplex

#define ALT_EMAC_GMAC_MAC_CFG_TC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_TC

Disables Transmission to Phy

#define ALT_EMAC_GMAC_MAC_CFG_TC_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TC_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TC register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TC register field.

#define ALT_EMAC_GMAC_MAC_CFG_TC_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TC field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TC_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_TC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST

Strip Ether Frames Off

#define ALT_EMAC_GMAC_MAC_CFG_CST_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_MAC_CFG_CST

Strip Ether Frames On

#define ALT_EMAC_GMAC_MAC_CFG_CST_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_CST register field value.

#define ALT_EMAC_GMAC_MAC_CFG_CST_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_CST register field value.

#define ALT_EMAC_GMAC_MAC_CFG_CST_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_CST register field.

#define ALT_EMAC_GMAC_MAC_CFG_CST_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_MAC_CFG_CST field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_CST_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_CST register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_LSB   27

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_MSB   27

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET_MSK   0x08000000

The mask used to set the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_RESET   0x0

The reset value of the ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_EMAC_GMAC_MAC_CFG_TWOKPE field value from a register.

#define ALT_EMAC_GMAC_MAC_CFG_TWOKPE_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_EMAC_GMAC_MAC_CFG_TWOKPE register field value suitable for setting the register.

#define ALT_EMAC_GMAC_MAC_CFG_OFST   0x0

The byte offset of the ALT_EMAC_GMAC_MAC_CFG register from the beginning of the component.

#define ALT_EMAC_GMAC_MAC_CFG_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_MAC_CFG_OFST))

The address of the ALT_EMAC_GMAC_MAC_CFG register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_MAC_CFG.