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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[3:0] | RW | 0xf | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE |
[23:4] | ??? | Unknown | UNDEFINED |
[24] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP |
[27:25] | ??? | Unknown | UNDEFINED |
[28] | RW | 0x0 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC |
[31:29] | ??? | Unknown | UNDEFINED |
Field : value | |
Indicates the first block of next LUN. This information is used for extracting the target LUN during LUN interleaving. After Initialization, if the controller detects an ONFi device, this field is automatically updated by the controller. For other devices, software will need to write to this register for proper interleaving. The value in this register is interpreted as follows- [list][*]0 - Next LUN starts from 1024. [*]1 - Next LUN starts from 2048. [*]2 - Next LUN starts from 4096 and so on... [/list] Field Access Macros: | |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET(value) (((value) & 0x0000000f) >> 0) |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET(value) (((value) << 0) & 0x0000000f) |
Field : issue_read_before_sync | |
Issue LOAD cmd to flash core even if SYNC condition is not satisfied. But the data is read from the device (for this load) only after the SYNC condition has been satisfied. If this value is 0, CMD DMA waits for SYNC before issuing a READ command. This bit should be set to 0 if the controller is being accessed in non-Command DMA mode. Field Access Macros: | |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_LSB 28 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_MSB 28 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_WIDTH 1 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET_MSK 0x10000000 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_CLR_MSK 0xefffffff |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_RESET 0x0 |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_GET(value) (((value) & 0x10000000) >> 28) |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET(value) (((value) << 28) & 0x10000000) |
Data Structures | |
struct | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s |
Macros | |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f |
#define | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0 |
Typedefs | |
typedef struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_t |
struct ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN.
Data Fields | ||
---|---|---|
uint32_t | value: 4 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE |
uint32_t | __pad0__: 20 | UNDEFINED |
uint32_t | update_sync_before_prog_comp: 1 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP |
uint32_t | __pad1__: 3 | UNDEFINED |
uint32_t | issue_read_before_sync: 1 | ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC |
uint32_t | __pad2__: 3 | UNDEFINED |
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_WIDTH 4 |
The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET_MSK 0x0000000f |
The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_CLR_MSK 0xfffffff0 |
The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_RESET 0xf |
The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_GET | ( | value | ) | (((value) & 0x0000000f) >> 0) |
Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE field value from a register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE_SET | ( | value | ) | (((value) << 0) & 0x0000000f) |
Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_VALUE register field value suitable for setting the register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET_MSK 0x01000000 |
The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_RESET 0x0 |
The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP field value from a register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_UPDATE_SYNC_BEFORE_PROG_COMP register field value suitable for setting the register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_WIDTH 1 |
The width in bits of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET_MSK 0x10000000 |
The mask used to set the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_CLR_MSK 0xefffffff |
The mask used to clear the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_RESET 0x0 |
The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC field value from a register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_ISSUE_RD_BEFORE_SYNC register field value suitable for setting the register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_RESET 0x0000000f |
The reset value of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register.
#define ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN_OFST 0xa0 |
The byte offset of the ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN register from the beginning of the component.
The typedef declaration for register ALT_NAND_DMA_NO_OF_BLOCKS_PER_LUN.