Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Flash Clock Source Register - src

Description

Contains fields that select the source clocks for the flash controllers.

Fields are only reset by a cold reset.

Register Layout

Bits Access Reset Description
[1:0] RW 0x1 SDMMC Clock Source
[3:2] RW 0x1 NAND Clock Source
[5:4] RW 0x1 QSPI Clock Source
[31:6] ??? 0x0 UNDEFINED

Field : SDMMC Clock Source - sdmmc

Selects the source clock for the SDMMC.

Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK 0x0 f2s_periph_ref_clk
ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK 0x1 main_nand_sdmmc_clk
ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK 0x2 periph_nand_sdmmc_clk

Field Access Macros:

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK   0x0
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK   0x2
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB   0
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB   1
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH   2
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK   0x00000003
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK   0xfffffffc
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET(value)   (((value) << 0) & 0x00000003)
 

Field : NAND Clock Source - nand

Selects the source clock for the NAND.

Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK 0x0 f2s_periph_ref_clk
ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK 0x1 main_nand_sdmmc_clk
ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK 0x2 periph_nand_sdmmc_clk

Field Access Macros:

#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK   0x0
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK   0x2
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB   2
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB   3
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH   2
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK   0x0000000c
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK   0xfffffff3
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_GET(value)   (((value) & 0x0000000c) >> 2)
 
#define ALT_CLKMGR_PERPLL_SRC_NAND_SET(value)   (((value) << 2) & 0x0000000c)
 

Field : QSPI Clock Source - qspi

Selects the source clock for the QSPI.

Qsys and user documenation refer to f2s_periph_ref_clk as f2h_periph_ref_clk.

Field Enumeration Values:

Enum Value Description
ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK 0x0 f2s_periph_ref_clk
ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK 0x1 main_qspi_clk
ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK 0x2 periph_qspi_clk

Field Access Macros:

#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK   0x0
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK   0x2
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB   4
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB   5
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH   2
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK   0x00000030
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK   0xffffffcf
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET   0x1
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET(value)   (((value) << 4) & 0x00000030)
 

Data Structures

struct  ALT_CLKMGR_PERPLL_SRC_s
 

Macros

#define ALT_CLKMGR_PERPLL_SRC_OFST   0x2c
 

Typedefs

typedef struct
ALT_CLKMGR_PERPLL_SRC_s 
ALT_CLKMGR_PERPLL_SRC_t
 

Data Structure Documentation

struct ALT_CLKMGR_PERPLL_SRC_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_CLKMGR_PERPLL_SRC.

Data Fields
uint32_t sdmmc: 2 SDMMC Clock Source
uint32_t nand: 2 NAND Clock Source
uint32_t qspi: 2 QSPI Clock Source
uint32_t __pad0__: 26 UNDEFINED

Macro Definitions

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_F2S_PERIPH_REF_CLK   0x0

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC

f2s_periph_ref_clk

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_MAIN_NAND_CLK   0x1

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC

main_nand_sdmmc_clk

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_E_PERIPH_NAND_CLK   0x2

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_SDMMC

periph_nand_sdmmc_clk

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_LSB   0

The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_MSB   1

The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_WIDTH   2

The width in bits of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET_MSK   0x00000003

The mask used to set the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_CLR_MSK   0xfffffffc

The mask used to clear the ALT_CLKMGR_PERPLL_SRC_SDMMC register field value.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_RESET   0x1

The reset value of the ALT_CLKMGR_PERPLL_SRC_SDMMC register field.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_CLKMGR_PERPLL_SRC_SDMMC field value from a register.

#define ALT_CLKMGR_PERPLL_SRC_SDMMC_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_CLKMGR_PERPLL_SRC_SDMMC register field value suitable for setting the register.

#define ALT_CLKMGR_PERPLL_SRC_NAND_E_F2S_PERIPH_REF_CLK   0x0

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND

f2s_periph_ref_clk

#define ALT_CLKMGR_PERPLL_SRC_NAND_E_MAIN_NAND_CLK   0x1

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND

main_nand_sdmmc_clk

#define ALT_CLKMGR_PERPLL_SRC_NAND_E_PERIPH_NAND_CLK   0x2

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_NAND

periph_nand_sdmmc_clk

#define ALT_CLKMGR_PERPLL_SRC_NAND_LSB   2

The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field.

#define ALT_CLKMGR_PERPLL_SRC_NAND_MSB   3

The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_NAND register field.

#define ALT_CLKMGR_PERPLL_SRC_NAND_WIDTH   2

The width in bits of the ALT_CLKMGR_PERPLL_SRC_NAND register field.

#define ALT_CLKMGR_PERPLL_SRC_NAND_SET_MSK   0x0000000c

The mask used to set the ALT_CLKMGR_PERPLL_SRC_NAND register field value.

#define ALT_CLKMGR_PERPLL_SRC_NAND_CLR_MSK   0xfffffff3

The mask used to clear the ALT_CLKMGR_PERPLL_SRC_NAND register field value.

#define ALT_CLKMGR_PERPLL_SRC_NAND_RESET   0x1

The reset value of the ALT_CLKMGR_PERPLL_SRC_NAND register field.

#define ALT_CLKMGR_PERPLL_SRC_NAND_GET (   value)    (((value) & 0x0000000c) >> 2)

Extracts the ALT_CLKMGR_PERPLL_SRC_NAND field value from a register.

#define ALT_CLKMGR_PERPLL_SRC_NAND_SET (   value)    (((value) << 2) & 0x0000000c)

Produces a ALT_CLKMGR_PERPLL_SRC_NAND register field value suitable for setting the register.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_F2S_PERIPH_REF_CLK   0x0

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI

f2s_periph_ref_clk

#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_MAIN_QSPI_CLK   0x1

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI

main_qspi_clk

#define ALT_CLKMGR_PERPLL_SRC_QSPI_E_PERIPH_QSPI_CLK   0x2

Enumerated value for register field ALT_CLKMGR_PERPLL_SRC_QSPI

periph_qspi_clk

#define ALT_CLKMGR_PERPLL_SRC_QSPI_LSB   4

The Least Significant Bit (LSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_MSB   5

The Most Significant Bit (MSB) position of the ALT_CLKMGR_PERPLL_SRC_QSPI register field.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_WIDTH   2

The width in bits of the ALT_CLKMGR_PERPLL_SRC_QSPI register field.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET_MSK   0x00000030

The mask used to set the ALT_CLKMGR_PERPLL_SRC_QSPI register field value.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_CLR_MSK   0xffffffcf

The mask used to clear the ALT_CLKMGR_PERPLL_SRC_QSPI register field value.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_RESET   0x1

The reset value of the ALT_CLKMGR_PERPLL_SRC_QSPI register field.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_CLKMGR_PERPLL_SRC_QSPI field value from a register.

#define ALT_CLKMGR_PERPLL_SRC_QSPI_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_CLKMGR_PERPLL_SRC_QSPI register field value suitable for setting the register.

#define ALT_CLKMGR_PERPLL_SRC_OFST   0x2c

The byte offset of the ALT_CLKMGR_PERPLL_SRC register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_CLKMGR_PERPLL_SRC.