Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Hand Shake Time Out - hdsktimeout

Description

The Warm Reset handshake timeout will default to 10,240 which at 100 MHz for l4_sys_free_clk will 102.4 micro-seconds. This value will be a 25 bit programmable value in SW. The reason for this is the HMC adaptor may need a longer time to clear all outstanding SDRAM transactions. The maximum programmable value would be 20.97 msec

Register Layout

Bits Access Reset Description
[24:0] RW 0x2800 handshake timeout
[31:25] ??? 0x0 UNDEFINED

Field : handshake timeout - val

hand shake timeout

Field Access Macros:

#define ALT_RSTMGR_HDSKTMO_VAL_LSB   0
 
#define ALT_RSTMGR_HDSKTMO_VAL_MSB   24
 
#define ALT_RSTMGR_HDSKTMO_VAL_WIDTH   25
 
#define ALT_RSTMGR_HDSKTMO_VAL_SET_MSK   0x01ffffff
 
#define ALT_RSTMGR_HDSKTMO_VAL_CLR_MSK   0xfe000000
 
#define ALT_RSTMGR_HDSKTMO_VAL_RESET   0x2800
 
#define ALT_RSTMGR_HDSKTMO_VAL_GET(value)   (((value) & 0x01ffffff) >> 0)
 
#define ALT_RSTMGR_HDSKTMO_VAL_SET(value)   (((value) << 0) & 0x01ffffff)
 

Data Structures

struct  ALT_RSTMGR_HDSKTMO_s
 

Macros

#define ALT_RSTMGR_HDSKTMO_RESET   0x00002800
 
#define ALT_RSTMGR_HDSKTMO_OFST   0x64
 

Typedefs

typedef struct ALT_RSTMGR_HDSKTMO_s ALT_RSTMGR_HDSKTMO_t
 

Data Structure Documentation

struct ALT_RSTMGR_HDSKTMO_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_RSTMGR_HDSKTMO.

Data Fields
uint32_t val: 25 handshake timeout
uint32_t __pad0__: 7 UNDEFINED

Macro Definitions

#define ALT_RSTMGR_HDSKTMO_VAL_LSB   0

The Least Significant Bit (LSB) position of the ALT_RSTMGR_HDSKTMO_VAL register field.

#define ALT_RSTMGR_HDSKTMO_VAL_MSB   24

The Most Significant Bit (MSB) position of the ALT_RSTMGR_HDSKTMO_VAL register field.

#define ALT_RSTMGR_HDSKTMO_VAL_WIDTH   25

The width in bits of the ALT_RSTMGR_HDSKTMO_VAL register field.

#define ALT_RSTMGR_HDSKTMO_VAL_SET_MSK   0x01ffffff

The mask used to set the ALT_RSTMGR_HDSKTMO_VAL register field value.

#define ALT_RSTMGR_HDSKTMO_VAL_CLR_MSK   0xfe000000

The mask used to clear the ALT_RSTMGR_HDSKTMO_VAL register field value.

#define ALT_RSTMGR_HDSKTMO_VAL_RESET   0x2800

The reset value of the ALT_RSTMGR_HDSKTMO_VAL register field.

#define ALT_RSTMGR_HDSKTMO_VAL_GET (   value)    (((value) & 0x01ffffff) >> 0)

Extracts the ALT_RSTMGR_HDSKTMO_VAL field value from a register.

#define ALT_RSTMGR_HDSKTMO_VAL_SET (   value)    (((value) << 0) & 0x01ffffff)

Produces a ALT_RSTMGR_HDSKTMO_VAL register field value suitable for setting the register.

#define ALT_RSTMGR_HDSKTMO_RESET   0x00002800

The reset value of the ALT_RSTMGR_HDSKTMO register.

#define ALT_RSTMGR_HDSKTMO_OFST   0x64

The byte offset of the ALT_RSTMGR_HDSKTMO register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_RSTMGR_HDSKTMO.