Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Component Parameter Register - cpr

Description

Describes various fixed hardware setups states.

Register Layout

Bits Access Reset Description
[1:0] R 0x2 APB DATA WIDTH
[3:2] ??? 0x0 UNDEFINED
[4] R 0x1 Auto Flow Control
[5] R 0x1 THRE MODE
[6] R 0x0 SIR MODE Unsupported
[7] R 0x0 SIR LP MODE Unsupported
[8] R 0x1 ADDITIONAL FEATURES Supported
[9] R 0x1 FIFO ACCESS Supported
[10] R 0x1 FIFO STAT Supported
[11] R 0x1 SHADOW Supported
[12] R 0x1 Configuartion ID Register Present
[13] R 0x1 DMA EXTRA Supported
[15:14] ??? 0x0 UNDEFINED
[23:16] R 0x37 FIFO Depth
[31:24] ??? 0x0 UNDEFINED

Field : APB DATA WIDTH - apbdatawidth

Fixed to support an ABP data bus width of 32-bits.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS 0x2 APB Data Width = 32-bits

Field Access Macros:

#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS   0x2
 
#define ALT_UART_CPR_APBDATAWIDTH_LSB   0
 
#define ALT_UART_CPR_APBDATAWIDTH_MSB   1
 
#define ALT_UART_CPR_APBDATAWIDTH_WIDTH   2
 
#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK   0x00000003
 
#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK   0xfffffffc
 
#define ALT_UART_CPR_APBDATAWIDTH_RESET   0x2
 
#define ALT_UART_CPR_APBDATAWIDTH_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_UART_CPR_APBDATAWIDTH_SET(value)   (((value) << 0) & 0x00000003)
 

Field : Auto Flow Control - afce_mode

Allows auto flow control.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_AFCE_MOD_E_END 0x1 Auto Flow

Field Access Macros:

#define ALT_UART_CPR_AFCE_MOD_E_END   0x1
 
#define ALT_UART_CPR_AFCE_MOD_LSB   4
 
#define ALT_UART_CPR_AFCE_MOD_MSB   4
 
#define ALT_UART_CPR_AFCE_MOD_WIDTH   1
 
#define ALT_UART_CPR_AFCE_MOD_SET_MSK   0x00000010
 
#define ALT_UART_CPR_AFCE_MOD_CLR_MSK   0xffffffef
 
#define ALT_UART_CPR_AFCE_MOD_RESET   0x1
 
#define ALT_UART_CPR_AFCE_MOD_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_UART_CPR_AFCE_MOD_SET(value)   (((value) << 4) & 0x00000010)
 

Field : THRE MODE - thre_mode

Programmable Transmitter Hold Register Empty interrupt

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_THRE_MOD_E_END 0x1 Programmable Tx Hold Reg. Empty interrupt
: present

Field Access Macros:

#define ALT_UART_CPR_THRE_MOD_E_END   0x1
 
#define ALT_UART_CPR_THRE_MOD_LSB   5
 
#define ALT_UART_CPR_THRE_MOD_MSB   5
 
#define ALT_UART_CPR_THRE_MOD_WIDTH   1
 
#define ALT_UART_CPR_THRE_MOD_SET_MSK   0x00000020
 
#define ALT_UART_CPR_THRE_MOD_CLR_MSK   0xffffffdf
 
#define ALT_UART_CPR_THRE_MOD_RESET   0x1
 
#define ALT_UART_CPR_THRE_MOD_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_UART_CPR_THRE_MOD_SET(value)   (((value) << 5) & 0x00000020)
 

Field : SIR MODE Unsupported - sir_mode

Sir mode not used in this application.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_SIR_MOD_E_DISD 0x0 Sir Mode Not Supported

Field Access Macros:

#define ALT_UART_CPR_SIR_MOD_E_DISD   0x0
 
#define ALT_UART_CPR_SIR_MOD_LSB   6
 
#define ALT_UART_CPR_SIR_MOD_MSB   6
 
#define ALT_UART_CPR_SIR_MOD_WIDTH   1
 
#define ALT_UART_CPR_SIR_MOD_SET_MSK   0x00000040
 
#define ALT_UART_CPR_SIR_MOD_CLR_MSK   0xffffffbf
 
#define ALT_UART_CPR_SIR_MOD_RESET   0x0
 
#define ALT_UART_CPR_SIR_MOD_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_UART_CPR_SIR_MOD_SET(value)   (((value) << 6) & 0x00000040)
 

Field : SIR LP MODE Unsupported - sir_lp_mode

LP Sir Mode not used in this application.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_SIR_LP_MOD_E_DISD 0x0 LP Sir Mode Not Supported

Field Access Macros:

#define ALT_UART_CPR_SIR_LP_MOD_E_DISD   0x0
 
#define ALT_UART_CPR_SIR_LP_MOD_LSB   7
 
#define ALT_UART_CPR_SIR_LP_MOD_MSB   7
 
#define ALT_UART_CPR_SIR_LP_MOD_WIDTH   1
 
#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK   0x00000080
 
#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK   0xffffff7f
 
#define ALT_UART_CPR_SIR_LP_MOD_RESET   0x0
 
#define ALT_UART_CPR_SIR_LP_MOD_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_UART_CPR_SIR_LP_MOD_SET(value)   (((value) << 7) & 0x00000080)
 

Field : ADDITIONAL FEATURES Supported - additional_feat

Configures the uart to include fifo status register, shadow registers and encoded parameter register.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_ADDITIONAL_FEAT_E_END 0x1 Additional Features Supported

Field Access Macros:

#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END   0x1
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB   8
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB   8
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH   1
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK   0x00000100
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK   0xfffffeff
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET   0x1
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_UART_CPR_ADDITIONAL_FEAT_SET(value)   (((value) << 8) & 0x00000100)
 

Field : FIFO ACCESS Supported - fifo_access

Configures the peripheral to have a programmable FIFO access mode. This is used for test purposes, to allow the receiver FIFO to be written and the transmit FIFO to be read when FIFOs are implemented and enabled.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_FIFO_ACCESS_E_END 0x1 FIFO Access Supported

Field Access Macros:

#define ALT_UART_CPR_FIFO_ACCESS_E_END   0x1
 
#define ALT_UART_CPR_FIFO_ACCESS_LSB   9
 
#define ALT_UART_CPR_FIFO_ACCESS_MSB   9
 
#define ALT_UART_CPR_FIFO_ACCESS_WIDTH   1
 
#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK   0x00000200
 
#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK   0xfffffdff
 
#define ALT_UART_CPR_FIFO_ACCESS_RESET   0x1
 
#define ALT_UART_CPR_FIFO_ACCESS_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_UART_CPR_FIFO_ACCESS_SET(value)   (((value) << 9) & 0x00000200)
 

Field : FIFO STAT Supported - fifo_stat

Configures the peripheral to have three additional FIFO status registers.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_FIFO_STAT_E_END 0x1 FIFO Stat Supported

Field Access Macros:

#define ALT_UART_CPR_FIFO_STAT_E_END   0x1
 
#define ALT_UART_CPR_FIFO_STAT_LSB   10
 
#define ALT_UART_CPR_FIFO_STAT_MSB   10
 
#define ALT_UART_CPR_FIFO_STAT_WIDTH   1
 
#define ALT_UART_CPR_FIFO_STAT_SET_MSK   0x00000400
 
#define ALT_UART_CPR_FIFO_STAT_CLR_MSK   0xfffffbff
 
#define ALT_UART_CPR_FIFO_STAT_RESET   0x1
 
#define ALT_UART_CPR_FIFO_STAT_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_UART_CPR_FIFO_STAT_SET(value)   (((value) << 10) & 0x00000400)
 

Field : SHADOW Supported - shadow

Configures the peripheral to have seven additional registers that shadow some of the existing register bits that are regularly modified by software. These can be used to reduce the software overhead that is introduced by having to perform read-modify writes.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_SHADOW_E_END 0x1 Shadow Supported

Field Access Macros:

#define ALT_UART_CPR_SHADOW_E_END   0x1
 
#define ALT_UART_CPR_SHADOW_LSB   11
 
#define ALT_UART_CPR_SHADOW_MSB   11
 
#define ALT_UART_CPR_SHADOW_WIDTH   1
 
#define ALT_UART_CPR_SHADOW_SET_MSK   0x00000800
 
#define ALT_UART_CPR_SHADOW_CLR_MSK   0xfffff7ff
 
#define ALT_UART_CPR_SHADOW_RESET   0x1
 
#define ALT_UART_CPR_SHADOW_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_UART_CPR_SHADOW_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Configuartion ID Register Present - uart_add_encoded_param

Configures the peripheral to have a configuration identification register.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END 0x1 ID register present

Field Access Macros:

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END   0x1
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB   12
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB   12
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH   1
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK   0x00001000
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK   0xffffefff
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET   0x1
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET(value)   (((value) << 12) & 0x00001000)
 

Field : DMA EXTRA Supported - dma_extra

Configures the peripheral to have four additional DMA signals on the interface.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_DMA_EXTRA_E_END 0x1 DMA Extra Supported

Field Access Macros:

#define ALT_UART_CPR_DMA_EXTRA_E_END   0x1
 
#define ALT_UART_CPR_DMA_EXTRA_LSB   13
 
#define ALT_UART_CPR_DMA_EXTRA_MSB   13
 
#define ALT_UART_CPR_DMA_EXTRA_WIDTH   1
 
#define ALT_UART_CPR_DMA_EXTRA_SET_MSK   0x00002000
 
#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK   0xffffdfff
 
#define ALT_UART_CPR_DMA_EXTRA_RESET   0x1
 
#define ALT_UART_CPR_DMA_EXTRA_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_UART_CPR_DMA_EXTRA_SET(value)   (((value) << 13) & 0x00002000)
 

Field : FIFO Depth - fifo_mode

Receiver and Transmitter FIFO depth in bytes.

Field Enumeration Values:

Enum Value Description
ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES 0x80 FIFO Depth 128 bytes

Field Access Macros:

#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES   0x80
 
#define ALT_UART_CPR_FIFO_MOD_LSB   16
 
#define ALT_UART_CPR_FIFO_MOD_MSB   23
 
#define ALT_UART_CPR_FIFO_MOD_WIDTH   8
 
#define ALT_UART_CPR_FIFO_MOD_SET_MSK   0x00ff0000
 
#define ALT_UART_CPR_FIFO_MOD_CLR_MSK   0xff00ffff
 
#define ALT_UART_CPR_FIFO_MOD_RESET   0x37
 
#define ALT_UART_CPR_FIFO_MOD_GET(value)   (((value) & 0x00ff0000) >> 16)
 
#define ALT_UART_CPR_FIFO_MOD_SET(value)   (((value) << 16) & 0x00ff0000)
 

Data Structures

struct  ALT_UART_CPR_s
 

Macros

#define ALT_UART_CPR_OFST   0xf4
 
#define ALT_UART_CPR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))
 

Typedefs

typedef struct ALT_UART_CPR_s ALT_UART_CPR_t
 

Data Structure Documentation

struct ALT_UART_CPR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_CPR.

Data Fields
const uint32_t apbdatawidth: 2 APB DATA WIDTH
uint32_t __pad0__: 2 UNDEFINED
const uint32_t afce_mode: 1 Auto Flow Control
const uint32_t thre_mode: 1 THRE MODE
const uint32_t sir_mode: 1 SIR MODE Unsupported
const uint32_t sir_lp_mode: 1 SIR LP MODE Unsupported
const uint32_t additional_feat: 1 ADDITIONAL FEATURES Supported
const uint32_t fifo_access: 1 FIFO ACCESS Supported
const uint32_t fifo_stat: 1 FIFO STAT Supported
const uint32_t shadow: 1 SHADOW Supported
const uint32_t uart_add_encoded_param: 1 Configuartion ID Register Present
const uint32_t dma_extra: 1 DMA EXTRA Supported
uint32_t __pad1__: 2 UNDEFINED
const uint32_t fifo_mode: 8 FIFO Depth
uint32_t __pad2__: 8 UNDEFINED

Macro Definitions

#define ALT_UART_CPR_APBDATAWIDTH_E_WIDTH32BITS   0x2

Enumerated value for register field ALT_UART_CPR_APBDATAWIDTH

APB Data Width = 32-bits

#define ALT_UART_CPR_APBDATAWIDTH_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_CPR_APBDATAWIDTH register field.

#define ALT_UART_CPR_APBDATAWIDTH_MSB   1

The Most Significant Bit (MSB) position of the ALT_UART_CPR_APBDATAWIDTH register field.

#define ALT_UART_CPR_APBDATAWIDTH_WIDTH   2

The width in bits of the ALT_UART_CPR_APBDATAWIDTH register field.

#define ALT_UART_CPR_APBDATAWIDTH_SET_MSK   0x00000003

The mask used to set the ALT_UART_CPR_APBDATAWIDTH register field value.

#define ALT_UART_CPR_APBDATAWIDTH_CLR_MSK   0xfffffffc

The mask used to clear the ALT_UART_CPR_APBDATAWIDTH register field value.

#define ALT_UART_CPR_APBDATAWIDTH_RESET   0x2

The reset value of the ALT_UART_CPR_APBDATAWIDTH register field.

#define ALT_UART_CPR_APBDATAWIDTH_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_UART_CPR_APBDATAWIDTH field value from a register.

#define ALT_UART_CPR_APBDATAWIDTH_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_UART_CPR_APBDATAWIDTH register field value suitable for setting the register.

#define ALT_UART_CPR_AFCE_MOD_E_END   0x1

Enumerated value for register field ALT_UART_CPR_AFCE_MOD

Auto Flow

#define ALT_UART_CPR_AFCE_MOD_LSB   4

The Least Significant Bit (LSB) position of the ALT_UART_CPR_AFCE_MOD register field.

#define ALT_UART_CPR_AFCE_MOD_MSB   4

The Most Significant Bit (MSB) position of the ALT_UART_CPR_AFCE_MOD register field.

#define ALT_UART_CPR_AFCE_MOD_WIDTH   1

The width in bits of the ALT_UART_CPR_AFCE_MOD register field.

#define ALT_UART_CPR_AFCE_MOD_SET_MSK   0x00000010

The mask used to set the ALT_UART_CPR_AFCE_MOD register field value.

#define ALT_UART_CPR_AFCE_MOD_CLR_MSK   0xffffffef

The mask used to clear the ALT_UART_CPR_AFCE_MOD register field value.

#define ALT_UART_CPR_AFCE_MOD_RESET   0x1

The reset value of the ALT_UART_CPR_AFCE_MOD register field.

#define ALT_UART_CPR_AFCE_MOD_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_UART_CPR_AFCE_MOD field value from a register.

#define ALT_UART_CPR_AFCE_MOD_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_UART_CPR_AFCE_MOD register field value suitable for setting the register.

#define ALT_UART_CPR_THRE_MOD_E_END   0x1

Enumerated value for register field ALT_UART_CPR_THRE_MOD

Programmable Tx Hold Reg. Empty interrupt present

#define ALT_UART_CPR_THRE_MOD_LSB   5

The Least Significant Bit (LSB) position of the ALT_UART_CPR_THRE_MOD register field.

#define ALT_UART_CPR_THRE_MOD_MSB   5

The Most Significant Bit (MSB) position of the ALT_UART_CPR_THRE_MOD register field.

#define ALT_UART_CPR_THRE_MOD_WIDTH   1

The width in bits of the ALT_UART_CPR_THRE_MOD register field.

#define ALT_UART_CPR_THRE_MOD_SET_MSK   0x00000020

The mask used to set the ALT_UART_CPR_THRE_MOD register field value.

#define ALT_UART_CPR_THRE_MOD_CLR_MSK   0xffffffdf

The mask used to clear the ALT_UART_CPR_THRE_MOD register field value.

#define ALT_UART_CPR_THRE_MOD_RESET   0x1

The reset value of the ALT_UART_CPR_THRE_MOD register field.

#define ALT_UART_CPR_THRE_MOD_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_UART_CPR_THRE_MOD field value from a register.

#define ALT_UART_CPR_THRE_MOD_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_UART_CPR_THRE_MOD register field value suitable for setting the register.

#define ALT_UART_CPR_SIR_MOD_E_DISD   0x0

Enumerated value for register field ALT_UART_CPR_SIR_MOD

Sir Mode Not Supported

#define ALT_UART_CPR_SIR_MOD_LSB   6

The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_MOD register field.

#define ALT_UART_CPR_SIR_MOD_MSB   6

The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_MOD register field.

#define ALT_UART_CPR_SIR_MOD_WIDTH   1

The width in bits of the ALT_UART_CPR_SIR_MOD register field.

#define ALT_UART_CPR_SIR_MOD_SET_MSK   0x00000040

The mask used to set the ALT_UART_CPR_SIR_MOD register field value.

#define ALT_UART_CPR_SIR_MOD_CLR_MSK   0xffffffbf

The mask used to clear the ALT_UART_CPR_SIR_MOD register field value.

#define ALT_UART_CPR_SIR_MOD_RESET   0x0

The reset value of the ALT_UART_CPR_SIR_MOD register field.

#define ALT_UART_CPR_SIR_MOD_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_UART_CPR_SIR_MOD field value from a register.

#define ALT_UART_CPR_SIR_MOD_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_UART_CPR_SIR_MOD register field value suitable for setting the register.

#define ALT_UART_CPR_SIR_LP_MOD_E_DISD   0x0

Enumerated value for register field ALT_UART_CPR_SIR_LP_MOD

LP Sir Mode Not Supported

#define ALT_UART_CPR_SIR_LP_MOD_LSB   7

The Least Significant Bit (LSB) position of the ALT_UART_CPR_SIR_LP_MOD register field.

#define ALT_UART_CPR_SIR_LP_MOD_MSB   7

The Most Significant Bit (MSB) position of the ALT_UART_CPR_SIR_LP_MOD register field.

#define ALT_UART_CPR_SIR_LP_MOD_WIDTH   1

The width in bits of the ALT_UART_CPR_SIR_LP_MOD register field.

#define ALT_UART_CPR_SIR_LP_MOD_SET_MSK   0x00000080

The mask used to set the ALT_UART_CPR_SIR_LP_MOD register field value.

#define ALT_UART_CPR_SIR_LP_MOD_CLR_MSK   0xffffff7f

The mask used to clear the ALT_UART_CPR_SIR_LP_MOD register field value.

#define ALT_UART_CPR_SIR_LP_MOD_RESET   0x0

The reset value of the ALT_UART_CPR_SIR_LP_MOD register field.

#define ALT_UART_CPR_SIR_LP_MOD_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_UART_CPR_SIR_LP_MOD field value from a register.

#define ALT_UART_CPR_SIR_LP_MOD_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_UART_CPR_SIR_LP_MOD register field value suitable for setting the register.

#define ALT_UART_CPR_ADDITIONAL_FEAT_E_END   0x1

Enumerated value for register field ALT_UART_CPR_ADDITIONAL_FEAT

Additional Features Supported

#define ALT_UART_CPR_ADDITIONAL_FEAT_LSB   8

The Least Significant Bit (LSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field.

#define ALT_UART_CPR_ADDITIONAL_FEAT_MSB   8

The Most Significant Bit (MSB) position of the ALT_UART_CPR_ADDITIONAL_FEAT register field.

#define ALT_UART_CPR_ADDITIONAL_FEAT_WIDTH   1

The width in bits of the ALT_UART_CPR_ADDITIONAL_FEAT register field.

#define ALT_UART_CPR_ADDITIONAL_FEAT_SET_MSK   0x00000100

The mask used to set the ALT_UART_CPR_ADDITIONAL_FEAT register field value.

#define ALT_UART_CPR_ADDITIONAL_FEAT_CLR_MSK   0xfffffeff

The mask used to clear the ALT_UART_CPR_ADDITIONAL_FEAT register field value.

#define ALT_UART_CPR_ADDITIONAL_FEAT_RESET   0x1

The reset value of the ALT_UART_CPR_ADDITIONAL_FEAT register field.

#define ALT_UART_CPR_ADDITIONAL_FEAT_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_UART_CPR_ADDITIONAL_FEAT field value from a register.

#define ALT_UART_CPR_ADDITIONAL_FEAT_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_UART_CPR_ADDITIONAL_FEAT register field value suitable for setting the register.

#define ALT_UART_CPR_FIFO_ACCESS_E_END   0x1

Enumerated value for register field ALT_UART_CPR_FIFO_ACCESS

FIFO Access Supported

#define ALT_UART_CPR_FIFO_ACCESS_LSB   9

The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_ACCESS register field.

#define ALT_UART_CPR_FIFO_ACCESS_MSB   9

The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_ACCESS register field.

#define ALT_UART_CPR_FIFO_ACCESS_WIDTH   1

The width in bits of the ALT_UART_CPR_FIFO_ACCESS register field.

#define ALT_UART_CPR_FIFO_ACCESS_SET_MSK   0x00000200

The mask used to set the ALT_UART_CPR_FIFO_ACCESS register field value.

#define ALT_UART_CPR_FIFO_ACCESS_CLR_MSK   0xfffffdff

The mask used to clear the ALT_UART_CPR_FIFO_ACCESS register field value.

#define ALT_UART_CPR_FIFO_ACCESS_RESET   0x1

The reset value of the ALT_UART_CPR_FIFO_ACCESS register field.

#define ALT_UART_CPR_FIFO_ACCESS_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_UART_CPR_FIFO_ACCESS field value from a register.

#define ALT_UART_CPR_FIFO_ACCESS_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_UART_CPR_FIFO_ACCESS register field value suitable for setting the register.

#define ALT_UART_CPR_FIFO_STAT_E_END   0x1

Enumerated value for register field ALT_UART_CPR_FIFO_STAT

FIFO Stat Supported

#define ALT_UART_CPR_FIFO_STAT_LSB   10

The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_STAT register field.

#define ALT_UART_CPR_FIFO_STAT_MSB   10

The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_STAT register field.

#define ALT_UART_CPR_FIFO_STAT_WIDTH   1

The width in bits of the ALT_UART_CPR_FIFO_STAT register field.

#define ALT_UART_CPR_FIFO_STAT_SET_MSK   0x00000400

The mask used to set the ALT_UART_CPR_FIFO_STAT register field value.

#define ALT_UART_CPR_FIFO_STAT_CLR_MSK   0xfffffbff

The mask used to clear the ALT_UART_CPR_FIFO_STAT register field value.

#define ALT_UART_CPR_FIFO_STAT_RESET   0x1

The reset value of the ALT_UART_CPR_FIFO_STAT register field.

#define ALT_UART_CPR_FIFO_STAT_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_UART_CPR_FIFO_STAT field value from a register.

#define ALT_UART_CPR_FIFO_STAT_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_UART_CPR_FIFO_STAT register field value suitable for setting the register.

#define ALT_UART_CPR_SHADOW_E_END   0x1

Enumerated value for register field ALT_UART_CPR_SHADOW

Shadow Supported

#define ALT_UART_CPR_SHADOW_LSB   11

The Least Significant Bit (LSB) position of the ALT_UART_CPR_SHADOW register field.

#define ALT_UART_CPR_SHADOW_MSB   11

The Most Significant Bit (MSB) position of the ALT_UART_CPR_SHADOW register field.

#define ALT_UART_CPR_SHADOW_WIDTH   1

The width in bits of the ALT_UART_CPR_SHADOW register field.

#define ALT_UART_CPR_SHADOW_SET_MSK   0x00000800

The mask used to set the ALT_UART_CPR_SHADOW register field value.

#define ALT_UART_CPR_SHADOW_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_UART_CPR_SHADOW register field value.

#define ALT_UART_CPR_SHADOW_RESET   0x1

The reset value of the ALT_UART_CPR_SHADOW register field.

#define ALT_UART_CPR_SHADOW_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_UART_CPR_SHADOW field value from a register.

#define ALT_UART_CPR_SHADOW_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_UART_CPR_SHADOW register field value suitable for setting the register.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_E_END   0x1

Enumerated value for register field ALT_UART_CPR_UART_ADD_ENC_PARAM

ID register present

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_LSB   12

The Least Significant Bit (LSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_MSB   12

The Most Significant Bit (MSB) position of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_WIDTH   1

The width in bits of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET_MSK   0x00001000

The mask used to set the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_CLR_MSK   0xffffefff

The mask used to clear the ALT_UART_CPR_UART_ADD_ENC_PARAM register field value.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_RESET   0x1

The reset value of the ALT_UART_CPR_UART_ADD_ENC_PARAM register field.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_UART_CPR_UART_ADD_ENC_PARAM field value from a register.

#define ALT_UART_CPR_UART_ADD_ENC_PARAM_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_UART_CPR_UART_ADD_ENC_PARAM register field value suitable for setting the register.

#define ALT_UART_CPR_DMA_EXTRA_E_END   0x1

Enumerated value for register field ALT_UART_CPR_DMA_EXTRA

DMA Extra Supported

#define ALT_UART_CPR_DMA_EXTRA_LSB   13

The Least Significant Bit (LSB) position of the ALT_UART_CPR_DMA_EXTRA register field.

#define ALT_UART_CPR_DMA_EXTRA_MSB   13

The Most Significant Bit (MSB) position of the ALT_UART_CPR_DMA_EXTRA register field.

#define ALT_UART_CPR_DMA_EXTRA_WIDTH   1

The width in bits of the ALT_UART_CPR_DMA_EXTRA register field.

#define ALT_UART_CPR_DMA_EXTRA_SET_MSK   0x00002000

The mask used to set the ALT_UART_CPR_DMA_EXTRA register field value.

#define ALT_UART_CPR_DMA_EXTRA_CLR_MSK   0xffffdfff

The mask used to clear the ALT_UART_CPR_DMA_EXTRA register field value.

#define ALT_UART_CPR_DMA_EXTRA_RESET   0x1

The reset value of the ALT_UART_CPR_DMA_EXTRA register field.

#define ALT_UART_CPR_DMA_EXTRA_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_UART_CPR_DMA_EXTRA field value from a register.

#define ALT_UART_CPR_DMA_EXTRA_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_UART_CPR_DMA_EXTRA register field value suitable for setting the register.

#define ALT_UART_CPR_FIFO_MOD_E_FIFO128BYTES   0x80

Enumerated value for register field ALT_UART_CPR_FIFO_MOD

FIFO Depth 128 bytes

#define ALT_UART_CPR_FIFO_MOD_LSB   16

The Least Significant Bit (LSB) position of the ALT_UART_CPR_FIFO_MOD register field.

#define ALT_UART_CPR_FIFO_MOD_MSB   23

The Most Significant Bit (MSB) position of the ALT_UART_CPR_FIFO_MOD register field.

#define ALT_UART_CPR_FIFO_MOD_WIDTH   8

The width in bits of the ALT_UART_CPR_FIFO_MOD register field.

#define ALT_UART_CPR_FIFO_MOD_SET_MSK   0x00ff0000

The mask used to set the ALT_UART_CPR_FIFO_MOD register field value.

#define ALT_UART_CPR_FIFO_MOD_CLR_MSK   0xff00ffff

The mask used to clear the ALT_UART_CPR_FIFO_MOD register field value.

#define ALT_UART_CPR_FIFO_MOD_RESET   0x37

The reset value of the ALT_UART_CPR_FIFO_MOD register field.

#define ALT_UART_CPR_FIFO_MOD_GET (   value)    (((value) & 0x00ff0000) >> 16)

Extracts the ALT_UART_CPR_FIFO_MOD field value from a register.

#define ALT_UART_CPR_FIFO_MOD_SET (   value)    (((value) << 16) & 0x00ff0000)

Produces a ALT_UART_CPR_FIFO_MOD register field value suitable for setting the register.

#define ALT_UART_CPR_OFST   0xf4

The byte offset of the ALT_UART_CPR register from the beginning of the component.

#define ALT_UART_CPR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_CPR_OFST))

The address of the ALT_UART_CPR register.

Typedef Documentation

The typedef declaration for register ALT_UART_CPR.