Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : L4 SP Peripherals Security - l4sp

Description

Controls security settings for L4 SP peripherals.

Register Layout

Bits Access Reset Description
[0] W 0x0 SDRAM Registers Security
[1] W 0x0 SP Timer 0 Security
[2] W 0x0 I2C0 Security
[3] W 0x0 I2C1 Security
[4] W 0x0 I2C2 (EMAC 0) Security
[5] W 0x0 I2C3 (EMAC 1) Security
[6] W 0x0 UART 0 Security
[7] W 0x0 UART 1 Security
[8] W 0x0 CAN 0 Security
[9] W 0x0 CAN 1 Security
[10] W 0x0 SP Timer 1 Security
[31:11] ??? 0x0 UNDEFINED

Field : SDRAM Registers Security - sdrregs

Controls whether secure or non-secure masters can access the SDRAM Registers slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_SDRREGS_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_SDRREGS_LSB   0
 
#define ALT_L3_SEC_L4SP_SDRREGS_MSB   0
 
#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH   1
 
#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK   0x00000001
 
#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK   0xfffffffe
 
#define ALT_L3_SEC_L4SP_SDRREGS_RESET   0x0
 
#define ALT_L3_SEC_L4SP_SDRREGS_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L3_SEC_L4SP_SDRREGS_SET(value)   (((value) << 0) & 0x00000001)
 

Field : SP Timer 0 Security - sptimer0

Controls whether secure or non-secure masters can access the SP Timer 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_SPTMR0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_SPTMR0_LSB   1
 
#define ALT_L3_SEC_L4SP_SPTMR0_MSB   1
 
#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH   1
 
#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK   0x00000002
 
#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK   0xfffffffd
 
#define ALT_L3_SEC_L4SP_SPTMR0_RESET   0x0
 
#define ALT_L3_SEC_L4SP_SPTMR0_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L3_SEC_L4SP_SPTMR0_SET(value)   (((value) << 1) & 0x00000002)
 

Field : I2C0 Security - i2c0

Controls whether secure or non-secure masters can access the I2C0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_I2C0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_I2C0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_I2C0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_I2C0_LSB   2
 
#define ALT_L3_SEC_L4SP_I2C0_MSB   2
 
#define ALT_L3_SEC_L4SP_I2C0_WIDTH   1
 
#define ALT_L3_SEC_L4SP_I2C0_SET_MSK   0x00000004
 
#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK   0xfffffffb
 
#define ALT_L3_SEC_L4SP_I2C0_RESET   0x0
 
#define ALT_L3_SEC_L4SP_I2C0_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_L3_SEC_L4SP_I2C0_SET(value)   (((value) << 2) & 0x00000004)
 

Field : I2C1 Security - i2c1

Controls whether secure or non-secure masters can access the I2C1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_I2C1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_I2C1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_I2C1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_I2C1_LSB   3
 
#define ALT_L3_SEC_L4SP_I2C1_MSB   3
 
#define ALT_L3_SEC_L4SP_I2C1_WIDTH   1
 
#define ALT_L3_SEC_L4SP_I2C1_SET_MSK   0x00000008
 
#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK   0xfffffff7
 
#define ALT_L3_SEC_L4SP_I2C1_RESET   0x0
 
#define ALT_L3_SEC_L4SP_I2C1_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_L3_SEC_L4SP_I2C1_SET(value)   (((value) << 3) & 0x00000008)
 

Field : I2C2 (EMAC 0) Security - i2c2

Controls whether secure or non-secure masters can access the I2C2 (EMAC 0) slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_I2C2_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_I2C2_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_I2C2_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_I2C2_LSB   4
 
#define ALT_L3_SEC_L4SP_I2C2_MSB   4
 
#define ALT_L3_SEC_L4SP_I2C2_WIDTH   1
 
#define ALT_L3_SEC_L4SP_I2C2_SET_MSK   0x00000010
 
#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK   0xffffffef
 
#define ALT_L3_SEC_L4SP_I2C2_RESET   0x0
 
#define ALT_L3_SEC_L4SP_I2C2_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_L3_SEC_L4SP_I2C2_SET(value)   (((value) << 4) & 0x00000010)
 

Field : I2C3 (EMAC 1) Security - i2c3

Controls whether secure or non-secure masters can access the I2C3 (EMAC 1) slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_I2C3_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_I2C3_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_I2C3_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_I2C3_LSB   5
 
#define ALT_L3_SEC_L4SP_I2C3_MSB   5
 
#define ALT_L3_SEC_L4SP_I2C3_WIDTH   1
 
#define ALT_L3_SEC_L4SP_I2C3_SET_MSK   0x00000020
 
#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK   0xffffffdf
 
#define ALT_L3_SEC_L4SP_I2C3_RESET   0x0
 
#define ALT_L3_SEC_L4SP_I2C3_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_L3_SEC_L4SP_I2C3_SET(value)   (((value) << 5) & 0x00000020)
 

Field : UART 0 Security - uart0

Controls whether secure or non-secure masters can access the UART 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_UART0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_UART0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_UART0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_UART0_LSB   6
 
#define ALT_L3_SEC_L4SP_UART0_MSB   6
 
#define ALT_L3_SEC_L4SP_UART0_WIDTH   1
 
#define ALT_L3_SEC_L4SP_UART0_SET_MSK   0x00000040
 
#define ALT_L3_SEC_L4SP_UART0_CLR_MSK   0xffffffbf
 
#define ALT_L3_SEC_L4SP_UART0_RESET   0x0
 
#define ALT_L3_SEC_L4SP_UART0_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_L3_SEC_L4SP_UART0_SET(value)   (((value) << 6) & 0x00000040)
 

Field : UART 1 Security - uart1

Controls whether secure or non-secure masters can access the UART 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_UART1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_UART1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_UART1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_UART1_LSB   7
 
#define ALT_L3_SEC_L4SP_UART1_MSB   7
 
#define ALT_L3_SEC_L4SP_UART1_WIDTH   1
 
#define ALT_L3_SEC_L4SP_UART1_SET_MSK   0x00000080
 
#define ALT_L3_SEC_L4SP_UART1_CLR_MSK   0xffffff7f
 
#define ALT_L3_SEC_L4SP_UART1_RESET   0x0
 
#define ALT_L3_SEC_L4SP_UART1_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_L3_SEC_L4SP_UART1_SET(value)   (((value) << 7) & 0x00000080)
 

Field : CAN 0 Security - can0

Controls whether secure or non-secure masters can access the CAN 0 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_CAN0_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_CAN0_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_CAN0_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_CAN0_LSB   8
 
#define ALT_L3_SEC_L4SP_CAN0_MSB   8
 
#define ALT_L3_SEC_L4SP_CAN0_WIDTH   1
 
#define ALT_L3_SEC_L4SP_CAN0_SET_MSK   0x00000100
 
#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK   0xfffffeff
 
#define ALT_L3_SEC_L4SP_CAN0_RESET   0x0
 
#define ALT_L3_SEC_L4SP_CAN0_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_L3_SEC_L4SP_CAN0_SET(value)   (((value) << 8) & 0x00000100)
 

Field : CAN 1 Security - can1

Controls whether secure or non-secure masters can access the CAN 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_CAN1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_CAN1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_CAN1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_CAN1_LSB   9
 
#define ALT_L3_SEC_L4SP_CAN1_MSB   9
 
#define ALT_L3_SEC_L4SP_CAN1_WIDTH   1
 
#define ALT_L3_SEC_L4SP_CAN1_SET_MSK   0x00000200
 
#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK   0xfffffdff
 
#define ALT_L3_SEC_L4SP_CAN1_RESET   0x0
 
#define ALT_L3_SEC_L4SP_CAN1_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_L3_SEC_L4SP_CAN1_SET(value)   (((value) << 9) & 0x00000200)
 

Field : SP Timer 1 Security - sptimer1

Controls whether secure or non-secure masters can access the SP Timer 1 slave.

Field Enumeration Values:

Enum Value Description
ALT_L3_SEC_L4SP_SPTMR1_E_SECURE 0x0 The slave can only be accessed by a secure
: master.
ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE 0x1 The slave can only be accessed by a secure or
: non-secure masters.

Field Access Macros:

#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE   0x0
 
#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE   0x1
 
#define ALT_L3_SEC_L4SP_SPTMR1_LSB   10
 
#define ALT_L3_SEC_L4SP_SPTMR1_MSB   10
 
#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH   1
 
#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK   0x00000400
 
#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK   0xfffffbff
 
#define ALT_L3_SEC_L4SP_SPTMR1_RESET   0x0
 
#define ALT_L3_SEC_L4SP_SPTMR1_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_L3_SEC_L4SP_SPTMR1_SET(value)   (((value) << 10) & 0x00000400)
 

Data Structures

struct  ALT_L3_SEC_L4SP_s
 

Macros

#define ALT_L3_SEC_L4SP_OFST   0x4
 

Typedefs

typedef struct ALT_L3_SEC_L4SP_s ALT_L3_SEC_L4SP_t
 

Data Structure Documentation

struct ALT_L3_SEC_L4SP_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L3_SEC_L4SP.

Data Fields
uint32_t sdrregs: 1 SDRAM Registers Security
uint32_t sptimer0: 1 SP Timer 0 Security
uint32_t i2c0: 1 I2C0 Security
uint32_t i2c1: 1 I2C1 Security
uint32_t i2c2: 1 I2C2 (EMAC 0) Security
uint32_t i2c3: 1 I2C3 (EMAC 1) Security
uint32_t uart0: 1 UART 0 Security
uint32_t uart1: 1 UART 1 Security
uint32_t can0: 1 CAN 0 Security
uint32_t can1: 1 CAN 1 Security
uint32_t sptimer1: 1 SP Timer 1 Security
uint32_t __pad0__: 21 UNDEFINED

Macro Definitions

#define ALT_L3_SEC_L4SP_SDRREGS_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_SDRREGS_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_SDRREGS

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_SDRREGS_LSB   0

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field.

#define ALT_L3_SEC_L4SP_SDRREGS_MSB   0

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SDRREGS register field.

#define ALT_L3_SEC_L4SP_SDRREGS_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_SDRREGS register field.

#define ALT_L3_SEC_L4SP_SDRREGS_SET_MSK   0x00000001

The mask used to set the ALT_L3_SEC_L4SP_SDRREGS register field value.

#define ALT_L3_SEC_L4SP_SDRREGS_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L3_SEC_L4SP_SDRREGS register field value.

#define ALT_L3_SEC_L4SP_SDRREGS_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_SDRREGS register field.

#define ALT_L3_SEC_L4SP_SDRREGS_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L3_SEC_L4SP_SDRREGS field value from a register.

#define ALT_L3_SEC_L4SP_SDRREGS_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L3_SEC_L4SP_SDRREGS register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_SPTMR0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_SPTMR0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_SPTMR0_LSB   1

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field.

#define ALT_L3_SEC_L4SP_SPTMR0_MSB   1

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR0 register field.

#define ALT_L3_SEC_L4SP_SPTMR0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_SPTMR0 register field.

#define ALT_L3_SEC_L4SP_SPTMR0_SET_MSK   0x00000002

The mask used to set the ALT_L3_SEC_L4SP_SPTMR0 register field value.

#define ALT_L3_SEC_L4SP_SPTMR0_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L3_SEC_L4SP_SPTMR0 register field value.

#define ALT_L3_SEC_L4SP_SPTMR0_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_SPTMR0 register field.

#define ALT_L3_SEC_L4SP_SPTMR0_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L3_SEC_L4SP_SPTMR0 field value from a register.

#define ALT_L3_SEC_L4SP_SPTMR0_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L3_SEC_L4SP_SPTMR0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_I2C0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_I2C0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_I2C0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_I2C0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_I2C0_LSB   2

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C0 register field.

#define ALT_L3_SEC_L4SP_I2C0_MSB   2

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C0 register field.

#define ALT_L3_SEC_L4SP_I2C0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_I2C0 register field.

#define ALT_L3_SEC_L4SP_I2C0_SET_MSK   0x00000004

The mask used to set the ALT_L3_SEC_L4SP_I2C0 register field value.

#define ALT_L3_SEC_L4SP_I2C0_CLR_MSK   0xfffffffb

The mask used to clear the ALT_L3_SEC_L4SP_I2C0 register field value.

#define ALT_L3_SEC_L4SP_I2C0_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_I2C0 register field.

#define ALT_L3_SEC_L4SP_I2C0_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_L3_SEC_L4SP_I2C0 field value from a register.

#define ALT_L3_SEC_L4SP_I2C0_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_L3_SEC_L4SP_I2C0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_I2C1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_I2C1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_I2C1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_I2C1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_I2C1_LSB   3

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C1 register field.

#define ALT_L3_SEC_L4SP_I2C1_MSB   3

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C1 register field.

#define ALT_L3_SEC_L4SP_I2C1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_I2C1 register field.

#define ALT_L3_SEC_L4SP_I2C1_SET_MSK   0x00000008

The mask used to set the ALT_L3_SEC_L4SP_I2C1 register field value.

#define ALT_L3_SEC_L4SP_I2C1_CLR_MSK   0xfffffff7

The mask used to clear the ALT_L3_SEC_L4SP_I2C1 register field value.

#define ALT_L3_SEC_L4SP_I2C1_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_I2C1 register field.

#define ALT_L3_SEC_L4SP_I2C1_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_L3_SEC_L4SP_I2C1 field value from a register.

#define ALT_L3_SEC_L4SP_I2C1_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_L3_SEC_L4SP_I2C1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_I2C2_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_I2C2

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_I2C2_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_I2C2

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_I2C2_LSB   4

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C2 register field.

#define ALT_L3_SEC_L4SP_I2C2_MSB   4

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C2 register field.

#define ALT_L3_SEC_L4SP_I2C2_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_I2C2 register field.

#define ALT_L3_SEC_L4SP_I2C2_SET_MSK   0x00000010

The mask used to set the ALT_L3_SEC_L4SP_I2C2 register field value.

#define ALT_L3_SEC_L4SP_I2C2_CLR_MSK   0xffffffef

The mask used to clear the ALT_L3_SEC_L4SP_I2C2 register field value.

#define ALT_L3_SEC_L4SP_I2C2_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_I2C2 register field.

#define ALT_L3_SEC_L4SP_I2C2_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_L3_SEC_L4SP_I2C2 field value from a register.

#define ALT_L3_SEC_L4SP_I2C2_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_L3_SEC_L4SP_I2C2 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_I2C3_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_I2C3

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_I2C3_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_I2C3

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_I2C3_LSB   5

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_I2C3 register field.

#define ALT_L3_SEC_L4SP_I2C3_MSB   5

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_I2C3 register field.

#define ALT_L3_SEC_L4SP_I2C3_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_I2C3 register field.

#define ALT_L3_SEC_L4SP_I2C3_SET_MSK   0x00000020

The mask used to set the ALT_L3_SEC_L4SP_I2C3 register field value.

#define ALT_L3_SEC_L4SP_I2C3_CLR_MSK   0xffffffdf

The mask used to clear the ALT_L3_SEC_L4SP_I2C3 register field value.

#define ALT_L3_SEC_L4SP_I2C3_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_I2C3 register field.

#define ALT_L3_SEC_L4SP_I2C3_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_L3_SEC_L4SP_I2C3 field value from a register.

#define ALT_L3_SEC_L4SP_I2C3_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_L3_SEC_L4SP_I2C3 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_UART0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_UART0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_UART0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_UART0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_UART0_LSB   6

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART0 register field.

#define ALT_L3_SEC_L4SP_UART0_MSB   6

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART0 register field.

#define ALT_L3_SEC_L4SP_UART0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_UART0 register field.

#define ALT_L3_SEC_L4SP_UART0_SET_MSK   0x00000040

The mask used to set the ALT_L3_SEC_L4SP_UART0 register field value.

#define ALT_L3_SEC_L4SP_UART0_CLR_MSK   0xffffffbf

The mask used to clear the ALT_L3_SEC_L4SP_UART0 register field value.

#define ALT_L3_SEC_L4SP_UART0_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_UART0 register field.

#define ALT_L3_SEC_L4SP_UART0_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_L3_SEC_L4SP_UART0 field value from a register.

#define ALT_L3_SEC_L4SP_UART0_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_L3_SEC_L4SP_UART0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_UART1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_UART1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_UART1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_UART1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_UART1_LSB   7

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_UART1 register field.

#define ALT_L3_SEC_L4SP_UART1_MSB   7

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_UART1 register field.

#define ALT_L3_SEC_L4SP_UART1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_UART1 register field.

#define ALT_L3_SEC_L4SP_UART1_SET_MSK   0x00000080

The mask used to set the ALT_L3_SEC_L4SP_UART1 register field value.

#define ALT_L3_SEC_L4SP_UART1_CLR_MSK   0xffffff7f

The mask used to clear the ALT_L3_SEC_L4SP_UART1 register field value.

#define ALT_L3_SEC_L4SP_UART1_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_UART1 register field.

#define ALT_L3_SEC_L4SP_UART1_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_L3_SEC_L4SP_UART1 field value from a register.

#define ALT_L3_SEC_L4SP_UART1_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_L3_SEC_L4SP_UART1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_CAN0_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_CAN0

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_CAN0_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_CAN0

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_CAN0_LSB   8

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN0 register field.

#define ALT_L3_SEC_L4SP_CAN0_MSB   8

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN0 register field.

#define ALT_L3_SEC_L4SP_CAN0_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_CAN0 register field.

#define ALT_L3_SEC_L4SP_CAN0_SET_MSK   0x00000100

The mask used to set the ALT_L3_SEC_L4SP_CAN0 register field value.

#define ALT_L3_SEC_L4SP_CAN0_CLR_MSK   0xfffffeff

The mask used to clear the ALT_L3_SEC_L4SP_CAN0 register field value.

#define ALT_L3_SEC_L4SP_CAN0_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_CAN0 register field.

#define ALT_L3_SEC_L4SP_CAN0_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_L3_SEC_L4SP_CAN0 field value from a register.

#define ALT_L3_SEC_L4SP_CAN0_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_L3_SEC_L4SP_CAN0 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_CAN1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_CAN1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_CAN1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_CAN1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_CAN1_LSB   9

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_CAN1 register field.

#define ALT_L3_SEC_L4SP_CAN1_MSB   9

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_CAN1 register field.

#define ALT_L3_SEC_L4SP_CAN1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_CAN1 register field.

#define ALT_L3_SEC_L4SP_CAN1_SET_MSK   0x00000200

The mask used to set the ALT_L3_SEC_L4SP_CAN1 register field value.

#define ALT_L3_SEC_L4SP_CAN1_CLR_MSK   0xfffffdff

The mask used to clear the ALT_L3_SEC_L4SP_CAN1 register field value.

#define ALT_L3_SEC_L4SP_CAN1_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_CAN1 register field.

#define ALT_L3_SEC_L4SP_CAN1_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_L3_SEC_L4SP_CAN1 field value from a register.

#define ALT_L3_SEC_L4SP_CAN1_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_L3_SEC_L4SP_CAN1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_SPTMR1_E_SECURE   0x0

Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1

The slave can only be accessed by a secure master.

#define ALT_L3_SEC_L4SP_SPTMR1_E_NONSECURE   0x1

Enumerated value for register field ALT_L3_SEC_L4SP_SPTMR1

The slave can only be accessed by a secure or non-secure masters.

#define ALT_L3_SEC_L4SP_SPTMR1_LSB   10

The Least Significant Bit (LSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field.

#define ALT_L3_SEC_L4SP_SPTMR1_MSB   10

The Most Significant Bit (MSB) position of the ALT_L3_SEC_L4SP_SPTMR1 register field.

#define ALT_L3_SEC_L4SP_SPTMR1_WIDTH   1

The width in bits of the ALT_L3_SEC_L4SP_SPTMR1 register field.

#define ALT_L3_SEC_L4SP_SPTMR1_SET_MSK   0x00000400

The mask used to set the ALT_L3_SEC_L4SP_SPTMR1 register field value.

#define ALT_L3_SEC_L4SP_SPTMR1_CLR_MSK   0xfffffbff

The mask used to clear the ALT_L3_SEC_L4SP_SPTMR1 register field value.

#define ALT_L3_SEC_L4SP_SPTMR1_RESET   0x0

The reset value of the ALT_L3_SEC_L4SP_SPTMR1 register field.

#define ALT_L3_SEC_L4SP_SPTMR1_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_L3_SEC_L4SP_SPTMR1 field value from a register.

#define ALT_L3_SEC_L4SP_SPTMR1_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_L3_SEC_L4SP_SPTMR1 register field value suitable for setting the register.

#define ALT_L3_SEC_L4SP_OFST   0x4

The byte offset of the ALT_L3_SEC_L4SP register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_L3_SEC_L4SP.