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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD |
[11:6] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP |
[17:12] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG |
[23:18] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR |
[29:24] | RW | 0x0 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP |
[31:30] | ??? | 0x0 | UNDEFINED |
Field : cfg_t_param_rd_to_rd | |
Read to read command timing on same bank Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET(value) (((value) << 0) & 0x0000003f) |
Field : cfg_t_param_rd_to_rd_diff_chip | |
Read to read command timing on different chips Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET(value) (((value) & 0x00000fc0) >> 6) |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET(value) (((value) << 6) & 0x00000fc0) |
Field : cfg_t_param_rd_to_rd_diff_bg | |
Read to read command timing on different chips Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET(value) (((value) & 0x0003f000) >> 12) |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET(value) (((value) << 12) & 0x0003f000) |
Field : cfg_t_param_rd_to_wr | |
Write to read command timing on same bank Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET(value) (((value) & 0x00fc0000) >> 18) |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET(value) (((value) << 18) & 0x00fc0000) |
Field : cfg_t_param_rd_to_wr_diff_chip | |
Read to write command timing on different chips Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET(value) (((value) & 0x3f000000) >> 24) |
#define | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET(value) (((value) << 24) & 0x3f000000) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_CALTIMING1_s |
Macros | |
#define | ALT_IO48_HMC_MMR_CALTIMING1_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_CALTIMING1_OFST 0x80 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_CALTIMING1_s | ALT_IO48_HMC_MMR_CALTIMING1_t |
struct ALT_IO48_HMC_MMR_CALTIMING1_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_CALTIMING1.
Data Fields | ||
---|---|---|
uint32_t | cfg_t_param_rd_to_rd: 6 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD |
uint32_t | cfg_t_param_rd_to_rd_diff_chip: 6 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP |
uint32_t | cfg_t_param_rd_to_rd_diff_bg: 6 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG |
uint32_t | cfg_t_param_rd_to_wr: 6 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR |
uint32_t | cfg_t_param_rd_to_wr_diff_chip: 6 | ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP |
uint32_t | __pad0__: 2 | UNDEFINED |
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_WIDTH 6 |
The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET_MSK 0x0000003f |
The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD field value from a register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH 6 |
The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET_MSK 0x00000fc0 |
The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_CLR_MSK 0xfffff03f |
The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_GET | ( | value | ) | (((value) & 0x00000fc0) >> 6) |
Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP field value from a register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP_SET | ( | value | ) | (((value) << 6) & 0x00000fc0) |
Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_CHIP register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_WIDTH 6 |
The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET_MSK 0x0003f000 |
The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_CLR_MSK 0xfffc0fff |
The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_GET | ( | value | ) | (((value) & 0x0003f000) >> 12) |
Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG field value from a register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG_SET | ( | value | ) | (((value) << 12) & 0x0003f000) |
Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_RD_DIFF_BG register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_WIDTH 6 |
The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET_MSK 0x00fc0000 |
The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_CLR_MSK 0xff03ffff |
The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_GET | ( | value | ) | (((value) & 0x00fc0000) >> 18) |
Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR field value from a register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_SET | ( | value | ) | (((value) << 18) & 0x00fc0000) |
Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_MSB 29 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH 6 |
The width in bits of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET_MSK 0x3f000000 |
The mask used to set the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_CLR_MSK 0xc0ffffff |
The mask used to clear the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_GET | ( | value | ) | (((value) & 0x3f000000) >> 24) |
Extracts the ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP field value from a register.
#define ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP_SET | ( | value | ) | (((value) << 24) & 0x3f000000) |
Produces a ALT_IO48_HMC_MMR_CALTIMING1_CFG_T_PARAM_RD_TO_WR_DIFF_CHIP register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CALTIMING1_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_CALTIMING1 register.
#define ALT_IO48_HMC_MMR_CALTIMING1_OFST 0x80 |
The byte offset of the ALT_IO48_HMC_MMR_CALTIMING1 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_CALTIMING1_s ALT_IO48_HMC_MMR_CALTIMING1_t |
The typedef declaration for register ALT_IO48_HMC_MMR_CALTIMING1.