Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : sbcfg7

Description

Register Layout

Bits Access Reset Description
[6:0] RW 0x0 ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD
[31:7] ??? 0x0 UNDEFINED

Field : cfg_rfsh_warn_threshold

Threshold to warn a refresh is needed within the number of controller clock cycles specified by the threshold

Field Access Macros:

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB   0
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB   6
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH   7
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK   0x0000007f
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK   0xffffff80
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET(value)   (((value) & 0x0000007f) >> 0)
 
#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET(value)   (((value) << 0) & 0x0000007f)
 

Data Structures

struct  ALT_IO48_HMC_MMR_SBCFG7_s
 

Macros

#define ALT_IO48_HMC_MMR_SBCFG7_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_SBCFG7_OFST   0x78
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_SBCFG7_s 
ALT_IO48_HMC_MMR_SBCFG7_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_SBCFG7_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_SBCFG7.

Data Fields
uint32_t cfg_rfsh_warn_threshold: 7 ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD
uint32_t __pad0__: 25 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_MSB   6

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_WIDTH   7

The width in bits of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET_MSK   0x0000007f

The mask used to set the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_CLR_MSK   0xffffff80

The mask used to clear the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_GET (   value)    (((value) & 0x0000007f) >> 0)

Extracts the ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD field value from a register.

#define ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD_SET (   value)    (((value) << 0) & 0x0000007f)

Produces a ALT_IO48_HMC_MMR_SBCFG7_CFG_RFSH_WARN_THRESHOLD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_SBCFG7_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_SBCFG7 register.

#define ALT_IO48_HMC_MMR_SBCFG7_OFST   0x78

The byte offset of the ALT_IO48_HMC_MMR_SBCFG7 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_SBCFG7.