Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : wdt_cr

Description

Control Register

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_L4WD_CR_WDT_EN
[1] RW 0x0 ALT_L4WD_CR_RMOD
[4:2] RW 0x0 ALT_L4WD_CR_RPL
[31:5] ??? 0x0 UNDEFINED

Field : wdt_en

WDT enable. Writable when the configuration parameter

WDT_ALWAYS_EN = 0, otherwise, it is readable. This bit is

used to enable and disable the DW_apb_wdt. When disabled, the

counter does not decrement. Thus, no interrupts or system resets

are generated. Once this bit has been enabled, it can be cleared

only by a system reset.

0 = WDT disabled.

1 = WDT enabled.

Field Enumeration Values:

Enum Value Description
ALT_L4WD_CR_WDT_EN_E_DISD 0x0 Watchdog disabled
ALT_L4WD_CR_WDT_EN_E_END 0x1 Watchdog enabled

Field Access Macros:

#define ALT_L4WD_CR_WDT_EN_E_DISD   0x0
 
#define ALT_L4WD_CR_WDT_EN_E_END   0x1
 
#define ALT_L4WD_CR_WDT_EN_LSB   0
 
#define ALT_L4WD_CR_WDT_EN_MSB   0
 
#define ALT_L4WD_CR_WDT_EN_WIDTH   1
 
#define ALT_L4WD_CR_WDT_EN_SET_MSK   0x00000001
 
#define ALT_L4WD_CR_WDT_EN_CLR_MSK   0xfffffffe
 
#define ALT_L4WD_CR_WDT_EN_RESET   0x0
 
#define ALT_L4WD_CR_WDT_EN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_L4WD_CR_WDT_EN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : rmod

Response mode. Writes have no effect when the parameter

WDT_HC_RMOD = 1, thus this register becomes read-only.

Selects the output response generated to a timeout.

0 = Generate a system reset.

1 = First generate an interrupt and if it is not cleared by the time

a second timeout occurs then generate a system reset.

Field Enumeration Values:

Enum Value Description
ALT_L4WD_CR_RMOD_E_RST 0x0 Generate a warm reset request
ALT_L4WD_CR_RMOD_E_IRQRST 0x1 First generate an interrupt, and if it is not
: cleared by the time a second timeout occurs,
: then generate a warm reset request.

Field Access Macros:

#define ALT_L4WD_CR_RMOD_E_RST   0x0
 
#define ALT_L4WD_CR_RMOD_E_IRQRST   0x1
 
#define ALT_L4WD_CR_RMOD_LSB   1
 
#define ALT_L4WD_CR_RMOD_MSB   1
 
#define ALT_L4WD_CR_RMOD_WIDTH   1
 
#define ALT_L4WD_CR_RMOD_SET_MSK   0x00000002
 
#define ALT_L4WD_CR_RMOD_CLR_MSK   0xfffffffd
 
#define ALT_L4WD_CR_RMOD_RESET   0x0
 
#define ALT_L4WD_CR_RMOD_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_L4WD_CR_RMOD_SET(value)   (((value) << 1) & 0x00000002)
 

Field : rpl

Reset pulse length. Writes have no effect when the configuration parameter

WDT_HC_RPL is 1, making the register bits read-only. This is used to select

the number of pclk cycles for which the system reset stays asserted. The

range of values available is 2 to 256 pclk cycles.

000 - 2 pclk cycles

001 - 4 pclk cycles

010 - 8 pclk cycles

011 - 16 pclk cycles

100 - 32 pclk cycles

101 - 64 pclk cycles

110 - 128 pclk cycles

111 - 256 pclk cycles

Field Access Macros:

#define ALT_L4WD_CR_RPL_LSB   2
 
#define ALT_L4WD_CR_RPL_MSB   4
 
#define ALT_L4WD_CR_RPL_WIDTH   3
 
#define ALT_L4WD_CR_RPL_SET_MSK   0x0000001c
 
#define ALT_L4WD_CR_RPL_CLR_MSK   0xffffffe3
 
#define ALT_L4WD_CR_RPL_RESET   0x0
 
#define ALT_L4WD_CR_RPL_GET(value)   (((value) & 0x0000001c) >> 2)
 
#define ALT_L4WD_CR_RPL_SET(value)   (((value) << 2) & 0x0000001c)
 

Data Structures

struct  ALT_L4WD_CR_s
 

Macros

#define ALT_L4WD_CR_RESET   0x00000000
 
#define ALT_L4WD_CR_OFST   0x0
 
#define ALT_L4WD_CR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CR_OFST))
 

Typedefs

typedef struct ALT_L4WD_CR_s ALT_L4WD_CR_t
 

Data Structure Documentation

struct ALT_L4WD_CR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_L4WD_CR.

Data Fields
uint32_t wdt_en: 1 ALT_L4WD_CR_WDT_EN
uint32_t rmod: 1 ALT_L4WD_CR_RMOD
uint32_t rpl: 3 ALT_L4WD_CR_RPL
uint32_t __pad0__: 27 UNDEFINED

Macro Definitions

#define ALT_L4WD_CR_WDT_EN_E_DISD   0x0

Enumerated value for register field ALT_L4WD_CR_WDT_EN

Watchdog disabled

#define ALT_L4WD_CR_WDT_EN_E_END   0x1

Enumerated value for register field ALT_L4WD_CR_WDT_EN

Watchdog enabled

#define ALT_L4WD_CR_WDT_EN_LSB   0

The Least Significant Bit (LSB) position of the ALT_L4WD_CR_WDT_EN register field.

#define ALT_L4WD_CR_WDT_EN_MSB   0

The Most Significant Bit (MSB) position of the ALT_L4WD_CR_WDT_EN register field.

#define ALT_L4WD_CR_WDT_EN_WIDTH   1

The width in bits of the ALT_L4WD_CR_WDT_EN register field.

#define ALT_L4WD_CR_WDT_EN_SET_MSK   0x00000001

The mask used to set the ALT_L4WD_CR_WDT_EN register field value.

#define ALT_L4WD_CR_WDT_EN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_L4WD_CR_WDT_EN register field value.

#define ALT_L4WD_CR_WDT_EN_RESET   0x0

The reset value of the ALT_L4WD_CR_WDT_EN register field.

#define ALT_L4WD_CR_WDT_EN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_L4WD_CR_WDT_EN field value from a register.

#define ALT_L4WD_CR_WDT_EN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_L4WD_CR_WDT_EN register field value suitable for setting the register.

#define ALT_L4WD_CR_RMOD_E_RST   0x0

Enumerated value for register field ALT_L4WD_CR_RMOD

Generate a warm reset request

#define ALT_L4WD_CR_RMOD_E_IRQRST   0x1

Enumerated value for register field ALT_L4WD_CR_RMOD

First generate an interrupt, and if it is not cleared by the time a second timeout occurs, then generate a warm reset request.

#define ALT_L4WD_CR_RMOD_LSB   1

The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RMOD register field.

#define ALT_L4WD_CR_RMOD_MSB   1

The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RMOD register field.

#define ALT_L4WD_CR_RMOD_WIDTH   1

The width in bits of the ALT_L4WD_CR_RMOD register field.

#define ALT_L4WD_CR_RMOD_SET_MSK   0x00000002

The mask used to set the ALT_L4WD_CR_RMOD register field value.

#define ALT_L4WD_CR_RMOD_CLR_MSK   0xfffffffd

The mask used to clear the ALT_L4WD_CR_RMOD register field value.

#define ALT_L4WD_CR_RMOD_RESET   0x0

The reset value of the ALT_L4WD_CR_RMOD register field.

#define ALT_L4WD_CR_RMOD_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_L4WD_CR_RMOD field value from a register.

#define ALT_L4WD_CR_RMOD_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_L4WD_CR_RMOD register field value suitable for setting the register.

#define ALT_L4WD_CR_RPL_LSB   2

The Least Significant Bit (LSB) position of the ALT_L4WD_CR_RPL register field.

#define ALT_L4WD_CR_RPL_MSB   4

The Most Significant Bit (MSB) position of the ALT_L4WD_CR_RPL register field.

#define ALT_L4WD_CR_RPL_WIDTH   3

The width in bits of the ALT_L4WD_CR_RPL register field.

#define ALT_L4WD_CR_RPL_SET_MSK   0x0000001c

The mask used to set the ALT_L4WD_CR_RPL register field value.

#define ALT_L4WD_CR_RPL_CLR_MSK   0xffffffe3

The mask used to clear the ALT_L4WD_CR_RPL register field value.

#define ALT_L4WD_CR_RPL_RESET   0x0

The reset value of the ALT_L4WD_CR_RPL register field.

#define ALT_L4WD_CR_RPL_GET (   value)    (((value) & 0x0000001c) >> 2)

Extracts the ALT_L4WD_CR_RPL field value from a register.

#define ALT_L4WD_CR_RPL_SET (   value)    (((value) << 2) & 0x0000001c)

Produces a ALT_L4WD_CR_RPL register field value suitable for setting the register.

#define ALT_L4WD_CR_RESET   0x00000000

The reset value of the ALT_L4WD_CR register.

#define ALT_L4WD_CR_OFST   0x0

The byte offset of the ALT_L4WD_CR register from the beginning of the component.

#define ALT_L4WD_CR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_L4WD_CR_OFST))

The address of the ALT_L4WD_CR register.

Typedef Documentation

typedef struct ALT_L4WD_CR_s ALT_L4WD_CR_t

The typedef declaration for register ALT_L4WD_CR.