Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Power and Clock Gating Control Register - pcgcctl

Description

This register is available in Host and Device modes. The application can use this register to control the core's power-down and clock gating features. Because the CSR module is turned off during power-down, this register is implemented in the AHB Slave BIU module.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Stop Pclk
[2:1] ??? 0x0 UNDEFINED
[3] RW 0x0 Reset Power-Down Modules
[5:4] ??? 0x0 UNDEFINED
[6] R 0x0 PHY In Sleep
[7] R 0x0 Deep Sleep
[31:8] ??? 0x0 UNDEFINED

Field : Stop Pclk - stoppclk

The application sets this bit to stop the PHY clock (phy_clk) when the USB is suspended, the session is not valid, or the device is disconnected. The application clears this bit when the USB is resumed or a new session starts.

Field Enumeration Values:

Enum Value Description
ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD 0x0 Disable Stop Pclk
ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END 0x1 Enable Stop Pclk

Field Access Macros:

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END   0x1
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB   0
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB   0
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH   1
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK   0x00000001
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK   0xfffffffe
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Reset Power-Down Modules - rstpdwnmodule

This bit is valid only in Partial Power-Down mode. Theapplication sets this bit when the power is turned off. The application clears this bit after the power is turned on and the PHY clock is up. The R/W of all core registers are possible only when this bit is set to 1b0.

Field Enumeration Values:

Enum Value Description
ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON 0x0 Power is turned on
ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF 0x1 Power is turned off

Field Access Macros:

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF   0x1
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB   3
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB   3
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH   1
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK   0x00000008
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK   0xfffffff7
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET(value)   (((value) << 3) & 0x00000008)
 

Field : PHY In Sleep - physleep

Indicates that the PHY is in Sleep State.

Field Enumeration Values:

Enum Value Description
ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT 0x0 Phy non-sleep
ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT 0x1 Phy sleep state

Field Access Macros:

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT   0x1
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB   6
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB   6
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH   1
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK   0x00000040
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK   0xffffffbf
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Deep Sleep - l1suspended

Indicates that the PHY is in deep sleep when in L1 state.

Field Enumeration Values:

Enum Value Description
ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT 0x0 Non Deep Sleep
ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT 0x1 Deep Sleep active

Field Access Macros:

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT   0x1
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB   7
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB   7
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH   1
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK   0x00000080
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK   0xffffff7f
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET(value)   (((value) << 7) & 0x00000080)
 

Data Structures

struct  ALT_USB_PWRCLK_PCGCCTL_s
 

Macros

#define ALT_USB_PWRCLK_PCGCCTL_OFST   0x0
 
#define ALT_USB_PWRCLK_PCGCCTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST))
 

Typedefs

typedef struct
ALT_USB_PWRCLK_PCGCCTL_s 
ALT_USB_PWRCLK_PCGCCTL_t
 

Data Structure Documentation

struct ALT_USB_PWRCLK_PCGCCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_USB_PWRCLK_PCGCCTL.

Data Fields
uint32_t stoppclk: 1 Stop Pclk
uint32_t __pad0__: 2 UNDEFINED
uint32_t rstpdwnmodule: 1 Reset Power-Down Modules
uint32_t __pad1__: 2 UNDEFINED
const uint32_t physleep: 1 PHY In Sleep
const uint32_t l1suspended: 1 Deep Sleep
uint32_t __pad2__: 24 UNDEFINED

Macro Definitions

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_DISD   0x0

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK

Disable Stop Pclk

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_E_END   0x1

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_STOPPCLK

Enable Stop Pclk

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_LSB   0

The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_MSB   0

The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_WIDTH   1

The width in bits of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET_MSK   0x00000001

The mask used to set the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_CLR_MSK   0xfffffffe

The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_RESET   0x0

The reset value of the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_USB_PWRCLK_PCGCCTL_STOPPCLK field value from a register.

#define ALT_USB_PWRCLK_PCGCCTL_STOPPCLK_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_USB_PWRCLK_PCGCCTL_STOPPCLK register field value suitable for setting the register.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_ON   0x0

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE

Power is turned on

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_E_OFF   0x1

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE

Power is turned off

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_LSB   3

The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_MSB   3

The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_WIDTH   1

The width in bits of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET_MSK   0x00000008

The mask used to set the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_CLR_MSK   0xfffffff7

The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_RESET   0x0

The reset value of the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE field value from a register.

#define ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_USB_PWRCLK_PCGCCTL_RSTPDWNMODULE register field value suitable for setting the register.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_INACT   0x0

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP

Phy non-sleep

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_E_ACT   0x1

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP

Phy sleep state

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_LSB   6

The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_MSB   6

The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_WIDTH   1

The width in bits of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET_MSK   0x00000040

The mask used to set the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_CLR_MSK   0xffffffbf

The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_RESET   0x0

The reset value of the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP field value from a register.

#define ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_USB_PWRCLK_PCGCCTL_PHYSLEEP register field value suitable for setting the register.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_INACT   0x0

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED

Non Deep Sleep

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_E_ACT   0x1

Enumerated value for register field ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED

Deep Sleep active

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_LSB   7

The Least Significant Bit (LSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_MSB   7

The Most Significant Bit (MSB) position of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_WIDTH   1

The width in bits of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET_MSK   0x00000080

The mask used to set the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_CLR_MSK   0xffffff7f

The mask used to clear the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_RESET   0x0

The reset value of the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED field value from a register.

#define ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_USB_PWRCLK_PCGCCTL_L1SUSPENDED register field value suitable for setting the register.

#define ALT_USB_PWRCLK_PCGCCTL_OFST   0x0

The byte offset of the ALT_USB_PWRCLK_PCGCCTL register from the beginning of the component.

#define ALT_USB_PWRCLK_PCGCCTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_PWRCLK_PCGCCTL_OFST))

The address of the ALT_USB_PWRCLK_PCGCCTL register.

Typedef Documentation

The typedef declaration for register ALT_USB_PWRCLK_PCGCCTL.