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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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The NRSTWARMMASK register is used by software to mask the assertion of module reset signals for hardware sequenced warm resets. There is a writeable bit for each module reset signal that is asserted by default on a hardware sequenced warm reset. If the bit is 1, the module reset signal is asserted by a hardware sequenced warm reset. If the bit is 0, the module reset signal is not changed by a hardware sequenced warm reset. The bit assignments of the *WARMMASK registers match the corresponding *MODRST registers. Any module reset signals that are never asserted by a warm reset have reserved bit offsets and are tied to 0 (read as 0, writes are ignored).
All fields are only reset by a cold reset.
Fields in the MISCMODRST register associated with cold reset or debug domain reset aren't present in the MISCWARMMASK register and are reserved.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | nRST Pin OE |
[31:1] | ??? | 0x0 | UNDEFINED |
Field : nRST Pin OE - nrstpinoe | |
Masks hardware sequenced warm reset for nrst_pin_oe Field Access Macros: | |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_LSB 0 |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_MSB 0 |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_WIDTH 1 |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET_MSK 0x00000001 |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_CLR_MSK 0xfffffffe |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_RESET 0x1 |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET(value) (((value) << 0) & 0x00000001) |
Data Structures | |
struct | ALT_RSTMGR_NRSTWARMMSK_s |
Macros | |
#define | ALT_RSTMGR_NRSTWARMMSK_RESET 0x00000001 |
#define | ALT_RSTMGR_NRSTWARMMSK_OFST 0x54 |
Typedefs | |
typedef struct ALT_RSTMGR_NRSTWARMMSK_s | ALT_RSTMGR_NRSTWARMMSK_t |
struct ALT_RSTMGR_NRSTWARMMSK_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_RSTMGR_NRSTWARMMSK.
Data Fields | ||
---|---|---|
uint32_t | nrstpinoe: 1 | nRST Pin OE |
uint32_t | __pad0__: 31 | UNDEFINED |
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_WIDTH 1 |
The width in bits of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET_MSK 0x00000001 |
The mask used to set the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_RESET 0x1 |
The reset value of the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE field value from a register.
#define ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_RSTMGR_NRSTWARMMSK_NRSTPINOE register field value suitable for setting the register.
#define ALT_RSTMGR_NRSTWARMMSK_RESET 0x00000001 |
The reset value of the ALT_RSTMGR_NRSTWARMMSK register.
#define ALT_RSTMGR_NRSTWARMMSK_OFST 0x54 |
The byte offset of the ALT_RSTMGR_NRSTWARMMSK register from the beginning of the component.
typedef struct ALT_RSTMGR_NRSTWARMMSK_s ALT_RSTMGR_NRSTWARMMSK_t |
The typedef declaration for register ALT_RSTMGR_NRSTWARMMSK.