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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Registers used by the EMACs. All fields are reset by a cold or warm reset.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[1:0] | RW | 0x2 | PHY Interface Select |
[3:2] | RW | 0x2 | PHY Interface Select |
[4] | RW | 0x0 | PTP Clock Select |
[5] | RW | 0x0 | PTP Clock Select |
[31:6] | ??? | 0x0 | UNDEFINED |
Field : PHY Interface Select - physel_0 | |||||||||||||
Controls the PHY interface selection of the EMACs. This is sampled by an EMAC module when it exits from reset. The associated enum defines the allowed values. The field array index corresponds to the EMAC index. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET(value) (((value) & 0x00000003) >> 0) | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET(value) (((value) << 0) & 0x00000003) | ||||||||||||
Field : PHY Interface Select - physel_1 | |||||||||||||
Controls the PHY interface selection of the EMACs. This is sampled by an EMAC module when it exits from reset. The associated enum defines the allowed values. The field array index corresponds to the EMAC index. Field Enumeration Values:
Field Access Macros: | |||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET(value) (((value) & 0x0000000c) >> 2) | ||||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET(value) (((value) << 2) & 0x0000000c) | ||||||||||||
Field : PTP Clock Select - ptpclksel_0 | ||||||||||
Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC module when it exits from reset. The field array index corresponds to the EMAC index. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : PTP Clock Select - ptpclksel_1 | ||||||||||
Selects the source of the 1588 PTP reference clock. This is sampled by an EMAC module when it exits from reset. The field array index corresponds to the EMAC index. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Data Structures | |
struct | ALT_SYSMGR_EMAC_CTL_s |
Macros | |
#define | ALT_SYSMGR_EMAC_CTL_OFST 0x0 |
Typedefs | |
typedef struct ALT_SYSMGR_EMAC_CTL_s | ALT_SYSMGR_EMAC_CTL_t |
struct ALT_SYSMGR_EMAC_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_EMAC_CTL.
Data Fields | ||
---|---|---|
uint32_t | physel_0: 2 | PHY Interface Select |
uint32_t | physel_1: 2 | PHY Interface Select |
uint32_t | ptpclksel_0: 1 | PTP Clock Select |
uint32_t | ptpclksel_1: 1 | PTP Clock Select |
uint32_t | __pad0__: 26 | UNDEFINED |
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_GMII_MII 0x0 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
Select GMII/MII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RGMII 0x1 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
Select RGMII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_E_RMII 0x2 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_0
Select RMII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_WIDTH 2 |
The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET_MSK 0x00000003 |
The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_CLR_MSK 0xfffffffc |
The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_RESET 0x2 |
The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_GET | ( | value | ) | (((value) & 0x00000003) >> 0) |
Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_0 field value from a register.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_0_SET | ( | value | ) | (((value) << 0) & 0x00000003) |
Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_0 register field value suitable for setting the register.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_GMII_MII 0x0 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
Select GMII/MII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RGMII 0x1 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
Select RGMII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_E_RMII 0x2 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PHYSEL_1
Select RMII PHY interface
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_WIDTH 2 |
The width in bits of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET_MSK 0x0000000c |
The mask used to set the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_CLR_MSK 0xfffffff3 |
The mask used to clear the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_RESET 0x2 |
The reset value of the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_GET | ( | value | ) | (((value) & 0x0000000c) >> 2) |
Extracts the ALT_SYSMGR_EMAC_CTL_PHYSEL_1 field value from a register.
#define ALT_SYSMGR_EMAC_CTL_PHYSEL_1_SET | ( | value | ) | (((value) << 2) & 0x0000000c) |
Produces a ALT_SYSMGR_EMAC_CTL_PHYSEL_1 register field value suitable for setting the register.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_OSC1_CLK 0x0 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
Selects osc1_clk
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_E_FPGA_PTP_REF_CLK 0x1 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0
Selects fpga_ptp_ref_clk
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_WIDTH 1 |
The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET_MSK 0x00000010 |
The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_CLR_MSK 0xffffffef |
The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_RESET 0x0 |
The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 field value from a register.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_0 register field value suitable for setting the register.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_OSC1_CLK 0x0 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
Selects osc1_clk
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_E_FPGA_PTP_REF_CLK 0x1 |
Enumerated value for register field ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1
Selects fpga_ptp_ref_clk
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_WIDTH 1 |
The width in bits of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET_MSK 0x00000020 |
The mask used to set the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_RESET 0x0 |
The reset value of the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 field value from a register.
#define ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_SYSMGR_EMAC_CTL_PTPCLKSEL_1 register field value suitable for setting the register.
#define ALT_SYSMGR_EMAC_CTL_OFST 0x0 |
The byte offset of the ALT_SYSMGR_EMAC_CTL register from the beginning of the component.
typedef struct ALT_SYSMGR_EMAC_CTL_s ALT_SYSMGR_EMAC_CTL_t |
The typedef declaration for register ALT_SYSMGR_EMAC_CTL.