![]() |
Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
|
Interrupt status register for bank 3
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR |
[1] | ??? | Unknown | UNDEFINED |
[2] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP |
[3] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_TIME_OUT |
[4] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL |
[5] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL |
[6] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LD_COMP |
[7] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP |
[8] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP |
[9] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP |
[10] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK |
[11] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD |
[12] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_INT_ACT |
[13] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_RST_COMP |
[14] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR |
[15] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC |
[16] | RW | 0x0 | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE |
[31:17] | ??? | Unknown | UNDEFINED |
Field : ecc_uncor_err | |
Ecc logic detected uncorrectable error while reading data from flash device. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0 |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0 |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001 |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET(value) (((value) << 0) & 0x00000001) |
Field : dma_cmd_comp | |
A data DMA command has completed on this bank Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2 |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2 |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004 |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET(value) (((value) << 2) & 0x00000004) |
Field : time_out | |
Watchdog timer has triggered in the controller due to one of the reasons like device not responding or controller state machine did not get back to idle Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET(value) (((value) << 3) & 0x00000008) |
Field : program_fail | |
Program failure occurred in the device on issuance of a program command. err_block_addr and err_page_addr contain the block address and page address that failed program operation. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET(value) (((value) << 4) & 0x00000010) |
Field : erase_fail | |
Erase failure occurred in the device on issuance of a erase command. err_block_addr and err_page_addr contain the block address and page address that failed erase operation. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET(value) (((value) << 5) & 0x00000020) |
Field : load_comp | |
Device finished the last issued load command. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6 |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6 |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040 |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET(value) (((value) & 0x00000040) >> 6) |
#define | ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET(value) (((value) << 6) & 0x00000040) |
Field : program_comp | |
Device finished the last issued program command. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET(value) (((value) << 7) & 0x00000080) |
Field : erase_comp | |
Device erase operation complete Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET(value) (((value) << 8) & 0x00000100) |
Field : pipe_cpybck_cmd_comp | |
A pipeline command or a copyback bank command has completed on this particular bank Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET(value) (((value) << 9) & 0x00000200) |
Field : locked_blk | |
The address to program or erase operation is to a locked block and the operation failed due to this reason Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10 |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10 |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400 |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET(value) (((value) << 10) & 0x00000400) |
Field : unsup_cmd | |
An unsupported command was received. This interrupt is set when an invalid command is received, or when a command sequence is broken. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11 |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11 |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800 |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET(value) (((value) << 11) & 0x00000800) |
Field : int_act | |
R/B pin of device transitioned from low to high Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12 |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12 |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000 |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET(value) (((value) << 12) & 0x00001000) |
Field : rst_comp | |
The Cadence NAND Flash Memory Controller has completed its reset and initialization process Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13 |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13 |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000 |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET(value) (((value) << 13) & 0x00002000) |
Field : pipe_cmd_err | |
A pipeline command sequence has been violated. This occurs when Map 01 page read/write address does not match the corresponding expected address from the pipeline commands issued earlier. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET(value) (((value) << 14) & 0x00004000) |
Field : page_xfer_inc | |
For every page of data transfer to or from the device, this bit will be set. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15 |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15 |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000 |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET(value) (((value) << 15) & 0x00008000) |
Field : erased_page | |
If an erased page is detected on reads, this bit will be set. The detection of erased page is based on the number of 0's in the page. If the number of 0's in the page being read is less than the value in the erase_threshold (programmable register), an erased page is inferred and no un-correctable error will be flagged for that page. If ECC is disabled, the erased_page interrupt shall be set as explained above. If ECC is enabled, in addition to the above condition, only when the ECC logic detects an un-correctable error for that page will the erased_page interrupt be flagged. If the ECC logic detects a no-error or correctable error page, this erased page interrupt will not be set. Field Access Macros: | |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_LSB 16 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_MSB 16 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_WIDTH 1 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET_MSK 0x00010000 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_CLR_MSK 0xfffeffff |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_RESET 0x0 |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET(value) (((value) << 16) & 0x00010000) |
Data Structures | |
struct | ALT_NAND_STAT_INTR_STAT3_s |
Macros | |
#define | ALT_NAND_STAT_INTR_STAT3_RESET 0x00000000 |
#define | ALT_NAND_STAT_INTR_STAT3_OFST 0x100 |
Typedefs | |
typedef struct ALT_NAND_STAT_INTR_STAT3_s | ALT_NAND_STAT_INTR_STAT3_t |
struct ALT_NAND_STAT_INTR_STAT3_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_STAT_INTR_STAT3.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET_MSK 0x00000001 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_NAND_STAT_INTR_STAT3_ECC_UNCOR_ERR register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET_MSK 0x00000004 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_NAND_STAT_INTR_STAT3_DMA_CMD_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET_MSK 0x00000008 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_NAND_STAT_INTR_STAT3_TIME_OUT field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_TIME_OUT_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_NAND_STAT_INTR_STAT3_TIME_OUT register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET_MSK 0x00000010 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_CLR_MSK 0xffffffef |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_FAIL register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET_MSK 0x00000020 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_FAIL register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET_MSK 0x00000040 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_CLR_MSK 0xffffffbf |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_LD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_GET | ( | value | ) | (((value) & 0x00000040) >> 6) |
Extracts the ALT_NAND_STAT_INTR_STAT3_LD_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_LD_COMP_SET | ( | value | ) | (((value) << 6) & 0x00000040) |
Produces a ALT_NAND_STAT_INTR_STAT3_LD_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET_MSK 0x00000080 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_NAND_STAT_INTR_STAT3_PROGRAM_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET_MSK 0x00000100 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_NAND_STAT_INTR_STAT3_ERASE_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_ERASE_COMP_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_NAND_STAT_INTR_STAT3_ERASE_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET_MSK 0x00000200 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CPYBCK_CMD_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET_MSK 0x00000400 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_NAND_STAT_INTR_STAT3_LOCKED_BLK register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET_MSK 0x00000800 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_NAND_STAT_INTR_STAT3_UNSUP_CMD register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET_MSK 0x00001000 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_CLR_MSK 0xffffefff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_INT_ACT register field.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_NAND_STAT_INTR_STAT3_INT_ACT field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_INT_ACT_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_NAND_STAT_INTR_STAT3_INT_ACT register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET_MSK 0x00002000 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_RST_COMP register field.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_NAND_STAT_INTR_STAT3_RST_COMP field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_RST_COMP_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_NAND_STAT_INTR_STAT3_RST_COMP register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET_MSK 0x00004000 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_NAND_STAT_INTR_STAT3_PIPE_CMD_ERR register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET_MSK 0x00008000 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_NAND_STAT_INTR_STAT3_PAGE_XFER_INC register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_WIDTH 1 |
The width in bits of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET_MSK 0x00010000 |
The mask used to set the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_RESET 0x0 |
The reset value of the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE field value from a register.
#define ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_NAND_STAT_INTR_STAT3_ERASED_PAGE register field value suitable for setting the register.
#define ALT_NAND_STAT_INTR_STAT3_RESET 0x00000000 |
The reset value of the ALT_NAND_STAT_INTR_STAT3 register.
#define ALT_NAND_STAT_INTR_STAT3_OFST 0x100 |
The byte offset of the ALT_NAND_STAT_INTR_STAT3 register from the beginning of the component.
typedef struct ALT_NAND_STAT_INTR_STAT3_s ALT_NAND_STAT_INTR_STAT3_t |
The typedef declaration for register ALT_NAND_STAT_INTR_STAT3.