Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : ecc_intmask_value

Description

ECC interrupt mask register.

This is a read/write register.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Interrupt Mask Set
[1] RW 0x0 Interrupt Mask Set
[2] RW 0x0 Interrupt Mask Set
[3] RW 0x0 Interrupt Mask Set
[4] RW 0x0 Interrupt Mask Set
[5] RW 0x0 Interrupt Mask Set
[6] RW 0x0 Interrupt Mask Set
[7] RW 0x0 Interrupt Mask Set
[8] RW 0x0 Interrupt Mask Set
[9] RW 0x0 Interrupt Mask Set
[10] RW 0x0 Interrupt Mask Set
[11] RW 0x0 Interrupt Mask Set
[12] RW 0x0 Interrupt Mask Set
[13] RW 0x0 Interrupt Mask Set
[14] RW 0x0 Interrupt Mask Set
[15] RW 0x0 Interrupt Mask Set
[16] RW 0x0 Interrupt Mask Set
[17] RW 0x0 Interrupt Mask Set
[18] RW 0x0 Interrupt Mask Set
[31:19] ??? 0x0 UNDEFINED

Field : Interrupt Mask Set - l2

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_LSB   0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_MSB   0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET_MSK   0x00000001
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_CLR_MSK   0xfffffffe
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Interrupt Mask Set - ocram

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_LSB   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_MSB   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET_MSK   0x00000002
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_CLR_MSK   0xfffffffd
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Interrupt Mask Set - usb0

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_LSB   2
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_MSB   2
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET_MSK   0x00000004
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_CLR_MSK   0xfffffffb
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Interrupt Mask Set - usb1

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_LSB   3
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_MSB   3
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET_MSK   0x00000008
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_CLR_MSK   0xfffffff7
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Interrupt Mask Set - emac0_rx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_LSB   4
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_MSB   4
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET_MSK   0x00000010
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_CLR_MSK   0xffffffef
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Interrupt Mask Set - emac0_tx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_LSB   5
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_MSB   5
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET_MSK   0x00000020
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_CLR_MSK   0xffffffdf
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Interrupt Mask Set - emac1_rx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_LSB   6
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_MSB   6
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET_MSK   0x00000040
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_CLR_MSK   0xffffffbf
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET(value)   (((value) << 6) & 0x00000040)
 

Field : Interrupt Mask Set - emac1_tx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_LSB   7
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_MSB   7
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET_MSK   0x00000080
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_CLR_MSK   0xffffff7f
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET(value)   (((value) << 7) & 0x00000080)
 

Field : Interrupt Mask Set - emac2_rx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_LSB   8
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_MSB   8
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET_MSK   0x00000100
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_CLR_MSK   0xfffffeff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Interrupt Mask Set - emac2_tx

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_LSB   9
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_MSB   9
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET_MSK   0x00000200
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_CLR_MSK   0xfffffdff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Interrupt Mask Set - dma

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_LSB   10
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_MSB   10
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET_MSK   0x00000400
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_CLR_MSK   0xfffffbff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Interrupt Mask Set - nand_buf

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_LSB   11
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_MSB   11
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET_MSK   0x00000800
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_CLR_MSK   0xfffff7ff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Interrupt Mask Set - nand_wr

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_LSB   12
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_MSB   12
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET_MSK   0x00001000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_CLR_MSK   0xffffefff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET(value)   (((value) << 12) & 0x00001000)
 

Field : Interrupt Mask Set - nand_rd

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_LSB   13
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_MSB   13
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET_MSK   0x00002000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_CLR_MSK   0xffffdfff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Interrupt Mask Set - qspi

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_LSB   14
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_MSB   14
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET_MSK   0x00004000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_CLR_MSK   0xffffbfff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Interrupt Mask Set - sdmmca

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_LSB   15
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_MSB   15
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET_MSK   0x00008000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_CLR_MSK   0xffff7fff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Interrupt Mask Set - sdmmcb

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_LSB   16
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_MSB   16
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET_MSK   0x00010000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_CLR_MSK   0xfffeffff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Interrupt Mask Set - ddr0

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_LSB   17
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_MSB   17
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET_MSK   0x00020000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_CLR_MSK   0xfffdffff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET(value)   (((value) << 17) & 0x00020000)
 

Field : Interrupt Mask Set - ddr1

Field Access Macros:

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_LSB   18
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_MSB   18
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_WIDTH   1
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET_MSK   0x00040000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_CLR_MSK   0xfffbffff
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_RESET   0x0
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET(value)   (((value) << 18) & 0x00040000)
 

Data Structures

struct  ALT_SYSMGR_ECC_INTMSK_VALUE_s
 

Macros

#define ALT_SYSMGR_ECC_INTMSK_VALUE_RESET   0x00000000
 
#define ALT_SYSMGR_ECC_INTMSK_VALUE_OFST   0x90
 

Typedefs

typedef struct
ALT_SYSMGR_ECC_INTMSK_VALUE_s 
ALT_SYSMGR_ECC_INTMSK_VALUE_t
 

Data Structure Documentation

struct ALT_SYSMGR_ECC_INTMSK_VALUE_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_ECC_INTMSK_VALUE.

Data Fields
uint32_t l2: 1 Interrupt Mask Set
uint32_t ocram: 1 Interrupt Mask Set
uint32_t usb0: 1 Interrupt Mask Set
uint32_t usb1: 1 Interrupt Mask Set
uint32_t emac0_rx: 1 Interrupt Mask Set
uint32_t emac0_tx: 1 Interrupt Mask Set
uint32_t emac1_rx: 1 Interrupt Mask Set
uint32_t emac1_tx: 1 Interrupt Mask Set
uint32_t emac2_rx: 1 Interrupt Mask Set
uint32_t emac2_tx: 1 Interrupt Mask Set
uint32_t dma: 1 Interrupt Mask Set
uint32_t nand_buf: 1 Interrupt Mask Set
uint32_t nand_wr: 1 Interrupt Mask Set
uint32_t nand_rd: 1 Interrupt Mask Set
uint32_t qspi: 1 Interrupt Mask Set
uint32_t sdmmca: 1 Interrupt Mask Set
uint32_t sdmmcb: 1 Interrupt Mask Set
uint32_t ddr0: 1 Interrupt Mask Set
uint32_t ddr1: 1 Interrupt Mask Set
uint32_t __pad0__: 13 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_MSB   0

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET_MSK   0x00000001

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_CLR_MSK   0xfffffffe

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_L2 field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_L2_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_L2 register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_LSB   1

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_MSB   1

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET_MSK   0x00000002

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_CLR_MSK   0xfffffffd

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_OCRAM register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_LSB   2

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_MSB   2

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET_MSK   0x00000004

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_CLR_MSK   0xfffffffb

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB0_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_USB0 register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_LSB   3

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_MSB   3

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET_MSK   0x00000008

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_CLR_MSK   0xfffffff7

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_USB1_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_USB1 register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_LSB   4

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_MSB   4

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET_MSK   0x00000010

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_CLR_MSK   0xffffffef

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_RX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_LSB   5

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_MSB   5

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET_MSK   0x00000020

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_CLR_MSK   0xffffffdf

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC0_TX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_LSB   6

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_MSB   6

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET_MSK   0x00000040

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_CLR_MSK   0xffffffbf

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_RX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_LSB   7

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET_MSK   0x00000080

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_CLR_MSK   0xffffff7f

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC1_TX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_MSB   8

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET_MSK   0x00000100

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_CLR_MSK   0xfffffeff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_RX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_LSB   9

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_MSB   9

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET_MSK   0x00000200

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_CLR_MSK   0xfffffdff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_EMAC2_TX register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_LSB   10

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_MSB   10

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET_MSK   0x00000400

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_CLR_MSK   0xfffffbff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DMA field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DMA_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DMA register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_LSB   11

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_MSB   11

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET_MSK   0x00000800

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_BUF register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_LSB   12

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_MSB   12

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET_MSK   0x00001000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_CLR_MSK   0xffffefff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_WR register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_LSB   13

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_MSB   13

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET_MSK   0x00002000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_CLR_MSK   0xffffdfff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_NAND_RD register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_LSB   14

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_MSB   14

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET_MSK   0x00004000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_CLR_MSK   0xffffbfff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_QSPI register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_LSB   15

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_MSB   15

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET_MSK   0x00008000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_CLR_MSK   0xffff7fff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCA register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_LSB   16

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_MSB   16

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET_MSK   0x00010000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_CLR_MSK   0xfffeffff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_SDMMCB register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_LSB   17

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_MSB   17

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET_MSK   0x00020000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_CLR_MSK   0xfffdffff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DDR0 register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_LSB   18

The Least Significant Bit (LSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_MSB   18

The Most Significant Bit (MSB) position of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_WIDTH   1

The width in bits of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET_MSK   0x00040000

The mask used to set the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_CLR_MSK   0xfffbffff

The mask used to clear the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_RESET   0x0

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 field value from a register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_SYSMGR_ECC_INTMSK_VALUE_DDR1 register field value suitable for setting the register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_RESET   0x00000000

The reset value of the ALT_SYSMGR_ECC_INTMSK_VALUE register.

#define ALT_SYSMGR_ECC_INTMSK_VALUE_OFST   0x90

The byte offset of the ALT_SYSMGR_ECC_INTMSK_VALUE register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_SYSMGR_ECC_INTMSK_VALUE.