Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Register 292 (Layer 3 and Layer 4 Control Register 3) - L3_L4_Control3

Description

This register controls the operations of the filter 0 of Layer 3 and Layer 4.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Layer 3 Protocol Enable
[1] ??? 0x0 UNDEFINED
[2] RW 0x0 Layer 3 IP SA Match Enable
[3] RW 0x0 Layer 3 IP SA Inverse Match Enable
[4] RW 0x0 Layer 3 IP DA Match Enable
[5] RW 0x0 Layer 3 IP DA Inverse Match Enable
[10:6] RW 0x0 Layer 3 IP SA Higher Bits Match
[15:11] RW 0x0 ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3
[16] RW 0x0 Layer 4 Protocol Enable
[17] ??? 0x0 UNDEFINED
[18] RW 0x0 Layer 4 Source Port Match Enable
[19] RW 0x0 Layer 4 Source Port Inverse Match Enable
[20] RW 0x0 Layer 4 Destination Port Match Enable
[21] RW 0x0 Layer 4 Destination Port Inverse Match Enable
[31:22] ??? 0x0 UNDEFINED

Field : Layer 3 Protocol Enable - l3pen3

When set, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv6 frames. When reset, this bit indicates that the Layer 3 IP Source or Destination Address matching is enabled for the IPv4 frames.

The Layer 3 matching is done only when either L3SAM3 or L3DAM3 bit is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB   0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB   0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Layer 3 IP SA Match Enable - l3sam3

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Source Address field for matching.

Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 4 (L3DAM3) because either IPv6 SA or DA can be checked for filtering.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB   2
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB   2
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Layer 3 IP SA Inverse Match Enable - l3saim3

When set, this bit indicates that the Layer 3 IP Source Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Source Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 2 (L3SAM3) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB   3
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB   3
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Layer 3 IP DA Match Enable - l3dam3

When set, this bit indicates that Layer 3 IP Destination Address field is enabled for matching. When reset, the MAC ignores the Layer 3 IP Destination Address field for matching.

Note: When Bit 0 (L3PEN3) is set, you should set either this bit or Bit 2 (L3SAM3) because either IPv6 DA or SA can be checked for filtering.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB   4
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB   4
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Layer 3 IP DA Inverse Match Enable - l3daim3

When set, this bit indicates that the Layer 3 IP Destination Address field is enabled for inverse matching. When reset, this bit indicates that the Layer 3 IP Destination Address field is enabled for perfect matching.

This bit is valid and applicable only when Bit 4 (L3DAM3) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Layer 3 IP SA Higher Bits Match - l3hsbm3

IPv4 Frames:

This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 frames. The following list describes the values of this field:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 31: All bits except MSb are masked.

IPv6 Frames:

This field contains Bits [4:0] of the field that indicates the number of higher bits of IP Source or Destination Address matched in the IPv6 frames.

This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB   6
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB   10
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK   0x000007c0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK   0xfffff83f
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET(value)   (((value) & 0x000007c0) >> 6)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET(value)   (((value) << 6) & 0x000007c0)
 

Field : l3hdbm3

Layer 3 IP DA Higher Bits Match

IPv4 Frames:

This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 frames. The following list describes the values of this field:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 31: All bits except MSb are masked.

IPv6 Frames:

Bits [12:11] of this field correspond to Bits [6:5] of L3HSBM3, which indicate the number of lower bits of IP Source or Destination Address that are masked in the IPv6 frames. The following list describes the concatenated values of the L3HDBM3[1:0] and L3HSBM3 bits:

  • 0: No bits are masked.
  • 1: LSb[0] is masked.
  • 2: Two LSbs [1:0] are masked.
  • ...
  • 127: All bits except MSb are masked.

This field is valid and applicable only if L3DAM3 or L3SAM3 is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB   11
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB   15
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH   5
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK   0x0000f800
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK   0xffff07ff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET(value)   (((value) & 0x0000f800) >> 11)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET(value)   (((value) << 11) & 0x0000f800)
 

Field : Layer 4 Protocol Enable - l4pen3

When set, this bit indicates that the Source and Destination Port number fields for UDP frames are used for matching. When reset, this bit indicates that the Source and Destination Port number fields for TCP frames are used for matching.

The Layer 4 matching is done only when either L4SPM3 or L4DPM3 bit is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB   16
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB   16
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK   0x00010000
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK   0xfffeffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET(value)   (((value) << 16) & 0x00010000)
 

Field : Layer 4 Source Port Match Enable - l4spm3

When set, this bit indicates that the Layer 4 Source Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Source Port number field for matching.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB   18
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB   18
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET(value)   (((value) << 18) & 0x00040000)
 

Field : Layer 4 Source Port Inverse Match Enable - l4spim3

When set, this bit indicates that the Layer 4 Source Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Source Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 18 (L4SPM3) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB   19
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB   19
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK   0x00080000
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK   0xfff7ffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET(value)   (((value) << 19) & 0x00080000)
 

Field : Layer 4 Destination Port Match Enable - l4dpm3

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for matching. When reset, the MAC ignores the Layer 4 Destination Port number field for matching.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB   20
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB   20
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK   0x00100000
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK   0xffefffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET(value)   (((value) << 20) & 0x00100000)
 

Field : Layer 4 Destination Port Inverse Match Enable - l4dpim3

When set, this bit indicates that the Layer 4 Destination Port number field is enabled for inverse matching. When reset, this bit indicates that the Layer 4 Destination Port number field is enabled for perfect matching.

This bit is valid and applicable only when Bit 20 (L4DPM3) is set high.

Field Access Macros:

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB   21
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB   21
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH   1
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK   0x00200000
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET   0x0
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET(value)   (((value) << 21) & 0x00200000)
 

Data Structures

struct  ALT_EMAC_GMAC_L3_L4_CTL3_s
 

Macros

#define ALT_EMAC_GMAC_L3_L4_CTL3_OFST   0x490
 
#define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_L3_L4_CTL3_s 
ALT_EMAC_GMAC_L3_L4_CTL3_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_L3_L4_CTL3_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_L3_L4_CTL3.

Data Fields
uint32_t l3pen3: 1 Layer 3 Protocol Enable
uint32_t __pad0__: 1 UNDEFINED
uint32_t l3sam3: 1 Layer 3 IP SA Match Enable
uint32_t l3saim3: 1 Layer 3 IP SA Inverse Match Enable
uint32_t l3dam3: 1 Layer 3 IP DA Match Enable
uint32_t l3daim3: 1 Layer 3 IP DA Inverse Match Enable
uint32_t l3hsbm3: 5 Layer 3 IP SA Higher Bits Match
uint32_t l3hdbm3: 5 ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3
uint32_t l4pen3: 1 Layer 4 Protocol Enable
uint32_t __pad1__: 1 UNDEFINED
uint32_t l4spm3: 1 Layer 4 Source Port Match Enable
uint32_t l4spim3: 1 Layer 4 Source Port Inverse Match Enable
uint32_t l4dpm3: 1 Layer 4 Destination Port Match Enable
uint32_t l4dpim3: 1 Layer 4 Destination Port Inverse Match Enable
uint32_t __pad2__: 10 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3PEN3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3SAIM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3DAIM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET_MSK   0x000007c0

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_CLR_MSK   0xfffff83f

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_GET (   value)    (((value) & 0x000007c0) >> 6)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3_SET (   value)    (((value) << 6) & 0x000007c0)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HSBM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_WIDTH   5

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET_MSK   0x0000f800

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_CLR_MSK   0xffff07ff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_GET (   value)    (((value) & 0x0000f800) >> 11)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3_SET (   value)    (((value) << 11) & 0x0000f800)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L3HDBM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET_MSK   0x00010000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_CLR_MSK   0xfffeffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4PEN3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_LSB   19

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET_MSK   0x00080000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4SPIM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_RESET   0x0

The reset value of the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 field value from a register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_GMAC_L3_L4_CTL3_L4DPIM3 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_L3_L4_CTL3_OFST   0x490

The byte offset of the ALT_EMAC_GMAC_L3_L4_CTL3 register from the beginning of the component.

#define ALT_EMAC_GMAC_L3_L4_CTL3_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_L3_L4_CTL3_OFST))

The address of the ALT_EMAC_GMAC_L3_L4_CTL3 register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_L3_L4_CTL3.