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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | Start Indirect Read |
[1] | RW | 0x0 | Cancel Indirect Read |
[2] | R | Unknown | Indirect Read Status |
[3] | RW | Unknown | SRAM Full |
[4] | R | Unknown | Queued Indirect Read Operations |
[5] | RW | Unknown | Indirect Completion Status |
[7:6] | R | Unknown | Completed Indirect Operations |
[31:8] | ??? | 0x0 | UNDEFINED |
Field : Start Indirect Read - start | ||||||||||
When this bit is enabled, it will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_START_E_END 0x1 | |||||||||
#define | ALT_QSPI_INDRD_START_E_DISD 0x0 | |||||||||
#define | ALT_QSPI_INDRD_START_LSB 0 | |||||||||
#define | ALT_QSPI_INDRD_START_MSB 0 | |||||||||
#define | ALT_QSPI_INDRD_START_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_START_SET_MSK 0x00000001 | |||||||||
#define | ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe | |||||||||
#define | ALT_QSPI_INDRD_START_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_START_GET(value) (((value) & 0x00000001) >> 0) | |||||||||
#define | ALT_QSPI_INDRD_START_SET(value) (((value) << 0) & 0x00000001) | |||||||||
Field : Cancel Indirect Read - cancel | ||||||||||
This bit will cancel all ongoing indirect read operations. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_LSB 1 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_MSB 1 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_GET(value) (((value) & 0x00000002) >> 1) | |||||||||
#define | ALT_QSPI_INDRD_CANCEL_SET(value) (((value) << 1) & 0x00000002) | |||||||||
Field : Indirect Read Status - rd_status | ||||||||||
Indirect read operation in progress (status) Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_LSB 2 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_MSB 2 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_GET(value) (((value) & 0x00000004) >> 2) | |||||||||
#define | ALT_QSPI_INDRD_RD_STAT_SET(value) (((value) << 2) & 0x00000004) | |||||||||
Field : SRAM Full - sram_full | ||||||||||
SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it. ; indirect operation (status) Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_LSB 3 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_MSB 3 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_GET(value) (((value) & 0x00000008) >> 3) | |||||||||
#define | ALT_QSPI_INDRD_SRAM_FULL_SET(value) (((value) << 3) & 0x00000008) | |||||||||
Field : Queued Indirect Read Operations - rd_queued | ||||||||||
Two indirect read operations have been queued Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_LSB 4 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_MSB 4 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_GET(value) (((value) & 0x00000010) >> 4) | |||||||||
#define | ALT_QSPI_INDRD_RD_QUEUED_SET(value) (((value) << 4) & 0x00000010) | |||||||||
Field : Indirect Completion Status - ind_ops_done_status | ||||||||||
This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it. Field Enumeration Values:
Field Access Macros: | ||||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET(value) (((value) & 0x00000020) >> 5) | |||||||||
#define | ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET(value) (((value) << 5) & 0x00000020) | |||||||||
Field : Completed Indirect Operations - num_ind_ops_done | |
This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). Field Access Macros: | |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET(value) (((value) & 0x000000c0) >> 6) |
#define | ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET(value) (((value) << 6) & 0x000000c0) |
Data Structures | |
struct | ALT_QSPI_INDRD_s |
Macros | |
#define | ALT_QSPI_INDRD_OFST 0x60 |
Typedefs | |
typedef struct ALT_QSPI_INDRD_s | ALT_QSPI_INDRD_t |
struct ALT_QSPI_INDRD_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_QSPI_INDRD.
Data Fields | ||
---|---|---|
uint32_t | start: 1 | Start Indirect Read |
uint32_t | cancel: 1 | Cancel Indirect Read |
const uint32_t | rd_status: 1 | Indirect Read Status |
uint32_t | sram_full: 1 | SRAM Full |
const uint32_t | rd_queued: 1 | Queued Indirect Read Operations |
uint32_t | ind_ops_done_status: 1 | Indirect Completion Status |
const uint32_t | num_ind_ops_done: 2 | Completed Indirect Operations |
uint32_t | __pad0__: 24 | UNDEFINED |
#define ALT_QSPI_INDRD_START_E_END 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_START
Trigger Indirect Read
#define ALT_QSPI_INDRD_START_E_DISD 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_START
No Indirect Read
#define ALT_QSPI_INDRD_START_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_START register field.
#define ALT_QSPI_INDRD_START_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_START register field.
#define ALT_QSPI_INDRD_START_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_START register field.
#define ALT_QSPI_INDRD_START_SET_MSK 0x00000001 |
The mask used to set the ALT_QSPI_INDRD_START register field value.
#define ALT_QSPI_INDRD_START_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_QSPI_INDRD_START register field value.
#define ALT_QSPI_INDRD_START_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_START register field.
#define ALT_QSPI_INDRD_START_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_QSPI_INDRD_START field value from a register.
#define ALT_QSPI_INDRD_START_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_QSPI_INDRD_START register field value suitable for setting the register.
#define ALT_QSPI_INDRD_CANCEL_E_CANCEL 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_CANCEL
Cancel Indirect Read
#define ALT_QSPI_INDRD_CANCEL_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_CANCEL
Do Not Cancel Indirect Read
#define ALT_QSPI_INDRD_CANCEL_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_CANCEL register field.
#define ALT_QSPI_INDRD_CANCEL_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_CANCEL register field.
#define ALT_QSPI_INDRD_CANCEL_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_CANCEL register field.
#define ALT_QSPI_INDRD_CANCEL_SET_MSK 0x00000002 |
The mask used to set the ALT_QSPI_INDRD_CANCEL register field value.
#define ALT_QSPI_INDRD_CANCEL_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_QSPI_INDRD_CANCEL register field value.
#define ALT_QSPI_INDRD_CANCEL_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_CANCEL register field.
#define ALT_QSPI_INDRD_CANCEL_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_QSPI_INDRD_CANCEL field value from a register.
#define ALT_QSPI_INDRD_CANCEL_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_QSPI_INDRD_CANCEL register field value suitable for setting the register.
#define ALT_QSPI_INDRD_RD_STAT_E_RDOP 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
Read Operation in progress
#define ALT_QSPI_INDRD_RD_STAT_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_RD_STAT
No read operation in progress
#define ALT_QSPI_INDRD_RD_STAT_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_STAT register field.
#define ALT_QSPI_INDRD_RD_STAT_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_STAT register field.
#define ALT_QSPI_INDRD_RD_STAT_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_RD_STAT register field.
#define ALT_QSPI_INDRD_RD_STAT_SET_MSK 0x00000004 |
The mask used to set the ALT_QSPI_INDRD_RD_STAT register field value.
#define ALT_QSPI_INDRD_RD_STAT_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_QSPI_INDRD_RD_STAT register field value.
#define ALT_QSPI_INDRD_RD_STAT_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_RD_STAT register field is UNKNOWN.
#define ALT_QSPI_INDRD_RD_STAT_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_QSPI_INDRD_RD_STAT field value from a register.
#define ALT_QSPI_INDRD_RD_STAT_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_QSPI_INDRD_RD_STAT register field value suitable for setting the register.
#define ALT_QSPI_INDRD_SRAM_FULL_E_SRAMFULL 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
Sram Full- Cant complete operation
#define ALT_QSPI_INDRD_SRAM_FULL_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_SRAM_FULL
SRram Not Full
#define ALT_QSPI_INDRD_SRAM_FULL_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field.
#define ALT_QSPI_INDRD_SRAM_FULL_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_SRAM_FULL register field.
#define ALT_QSPI_INDRD_SRAM_FULL_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_SRAM_FULL register field.
#define ALT_QSPI_INDRD_SRAM_FULL_SET_MSK 0x00000008 |
The mask used to set the ALT_QSPI_INDRD_SRAM_FULL register field value.
#define ALT_QSPI_INDRD_SRAM_FULL_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_QSPI_INDRD_SRAM_FULL register field value.
#define ALT_QSPI_INDRD_SRAM_FULL_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_SRAM_FULL register field is UNKNOWN.
#define ALT_QSPI_INDRD_SRAM_FULL_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_QSPI_INDRD_SRAM_FULL field value from a register.
#define ALT_QSPI_INDRD_SRAM_FULL_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_QSPI_INDRD_SRAM_FULL register field value suitable for setting the register.
#define ALT_QSPI_INDRD_RD_QUEUED_E_QUINDIRECTRD 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
Queued Indirect Read
#define ALT_QSPI_INDRD_RD_QUEUED_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_RD_QUEUED
No Queued Read
#define ALT_QSPI_INDRD_RD_QUEUED_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field.
#define ALT_QSPI_INDRD_RD_QUEUED_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_RD_QUEUED register field.
#define ALT_QSPI_INDRD_RD_QUEUED_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_RD_QUEUED register field.
#define ALT_QSPI_INDRD_RD_QUEUED_SET_MSK 0x00000010 |
The mask used to set the ALT_QSPI_INDRD_RD_QUEUED register field value.
#define ALT_QSPI_INDRD_RD_QUEUED_CLR_MSK 0xffffffef |
The mask used to clear the ALT_QSPI_INDRD_RD_QUEUED register field value.
#define ALT_QSPI_INDRD_RD_QUEUED_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_RD_QUEUED register field is UNKNOWN.
#define ALT_QSPI_INDRD_RD_QUEUED_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_QSPI_INDRD_RD_QUEUED field value from a register.
#define ALT_QSPI_INDRD_RD_QUEUED_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_QSPI_INDRD_RD_QUEUED register field value suitable for setting the register.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_INDCOMP 0x1 |
Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
Indirect Op Complete operation
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_E_NOACTION 0x0 |
Enumerated value for register field ALT_QSPI_INDRD_IND_OPS_DONE_STAT
Indirect Op Not Complete
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_WIDTH 1 |
The width in bits of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET_MSK 0x00000020 |
The mask used to set the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field is UNKNOWN.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_QSPI_INDRD_IND_OPS_DONE_STAT field value from a register.
#define ALT_QSPI_INDRD_IND_OPS_DONE_STAT_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_QSPI_INDRD_IND_OPS_DONE_STAT register field value suitable for setting the register.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_WIDTH 2 |
The width in bits of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET_MSK 0x000000c0 |
The mask used to set the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_CLR_MSK 0xffffff3f |
The mask used to clear the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_RESET 0x0 |
The reset value of the ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field is UNKNOWN.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_GET | ( | value | ) | (((value) & 0x000000c0) >> 6) |
Extracts the ALT_QSPI_INDRD_NUM_IND_OPS_DONE field value from a register.
#define ALT_QSPI_INDRD_NUM_IND_OPS_DONE_SET | ( | value | ) | (((value) << 6) & 0x000000c0) |
Produces a ALT_QSPI_INDRD_NUM_IND_OPS_DONE register field value suitable for setting the register.
#define ALT_QSPI_INDRD_OFST 0x60 |
The byte offset of the ALT_QSPI_INDRD register from the beginning of the component.
typedef struct ALT_QSPI_INDRD_s ALT_QSPI_INDRD_t |
The typedef declaration for register ALT_QSPI_INDRD.