Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : fcr

Description

FIFO Control Register

Register Layout

Bits Access Reset Description
[0] W 0x0 ALT_UART_FCR_FIFOE
[1] W 0x0 ALT_UART_FCR_RFIFOR
[2] W 0x0 ALT_UART_FCR_XFIFOR
[3] W 0x0 ALT_UART_FCR_DMAM
[5:4] W 0x0 ALT_UART_FCR_TET
[7:6] W 0x0 ALT_UART_FCR_RT
[31:8] ??? 0x0 UNDEFINED

Field : fifoe

Bit[0], FIFO Enable (or FIFOE):

This enables/disables the transmit (XMIT) and receive (RCVR) FIFO's. Whenever the

value of this bit is changed both the XMIT and RCVR controller portion of FIFO's

will be reset.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_FIFOE_E_DISD 0x0 FIFO disabled
ALT_UART_FCR_FIFOE_E_END 0x1 FIFO enabled

Field Access Macros:

#define ALT_UART_FCR_FIFOE_E_DISD   0x0
 
#define ALT_UART_FCR_FIFOE_E_END   0x1
 
#define ALT_UART_FCR_FIFOE_LSB   0
 
#define ALT_UART_FCR_FIFOE_MSB   0
 
#define ALT_UART_FCR_FIFOE_WIDTH   1
 
#define ALT_UART_FCR_FIFOE_SET_MSK   0x00000001
 
#define ALT_UART_FCR_FIFOE_CLR_MSK   0xfffffffe
 
#define ALT_UART_FCR_FIFOE_RESET   0x0
 
#define ALT_UART_FCR_FIFOE_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_UART_FCR_FIFOE_SET(value)   (((value) << 0) & 0x00000001)
 

Field : rfifor

Bit[1], RCVR FIFO Reset (or RFIFOR):

This resets the control portion of the receive FIFO and treats the FIFO as empty.

This will also de-assert the DMA RX request and single signals when additional

DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is

'self-clearing' and it is not necessary to clear this bit.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_RFIFOR_E_RST 0x1 Receive FIFO reset

Field Access Macros:

#define ALT_UART_FCR_RFIFOR_E_RST   0x1
 
#define ALT_UART_FCR_RFIFOR_LSB   1
 
#define ALT_UART_FCR_RFIFOR_MSB   1
 
#define ALT_UART_FCR_RFIFOR_WIDTH   1
 
#define ALT_UART_FCR_RFIFOR_SET_MSK   0x00000002
 
#define ALT_UART_FCR_RFIFOR_CLR_MSK   0xfffffffd
 
#define ALT_UART_FCR_RFIFOR_RESET   0x0
 
#define ALT_UART_FCR_RFIFOR_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_UART_FCR_RFIFOR_SET(value)   (((value) << 1) & 0x00000002)
 

Field : xfifor

Bit[2], XMIT FIFO Reset (or XFIFOR):

This resets the control portion of the transmit FIFO and treats the FIFO as empty.

This will also de-assert the DMA TX request and single signals when additional

DMA handshaking signals are selected (DMA_EXTRA == YES). Note that this bit is

'self-clearing' and it is not necessary to clear this bit.

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_XFIFOR_E_RST 0x1 Transmit FIFO reset

Field Access Macros:

#define ALT_UART_FCR_XFIFOR_E_RST   0x1
 
#define ALT_UART_FCR_XFIFOR_LSB   2
 
#define ALT_UART_FCR_XFIFOR_MSB   2
 
#define ALT_UART_FCR_XFIFOR_WIDTH   1
 
#define ALT_UART_FCR_XFIFOR_SET_MSK   0x00000004
 
#define ALT_UART_FCR_XFIFOR_CLR_MSK   0xfffffffb
 
#define ALT_UART_FCR_XFIFOR_RESET   0x0
 
#define ALT_UART_FCR_XFIFOR_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_UART_FCR_XFIFOR_SET(value)   (((value) << 2) & 0x00000004)
 

Field : dmam

Bit[3], DMA Mode (or DMAM):

This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n

output signals when additional DMA handshaking signals are not selected

(DMA_EXTRA == NO). See section 5.9 on page 56 for details on DMA support.

0 = mode 0

1 = mode 1

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_DMAM_E_MOD0 0x0 Mode 0
ALT_UART_FCR_DMAM_E_MOD1 0x1 Mode 1

Field Access Macros:

#define ALT_UART_FCR_DMAM_E_MOD0   0x0
 
#define ALT_UART_FCR_DMAM_E_MOD1   0x1
 
#define ALT_UART_FCR_DMAM_LSB   3
 
#define ALT_UART_FCR_DMAM_MSB   3
 
#define ALT_UART_FCR_DMAM_WIDTH   1
 
#define ALT_UART_FCR_DMAM_SET_MSK   0x00000008
 
#define ALT_UART_FCR_DMAM_CLR_MSK   0xfffffff7
 
#define ALT_UART_FCR_DMAM_RESET   0x0
 
#define ALT_UART_FCR_DMAM_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_UART_FCR_DMAM_SET(value)   (((value) << 3) & 0x00000008)
 

Field : tet

Bits[5:4], TX Empty Trigger (or TET):

Writes will have no effect when THRE_MODE_USER == Disabled. This is used to select

the empty threshold level at which the THRE Interrupts will be generated when the

mode is active. It also determines when the dma_tx_req_n signal will be asserted when

in certain modes of operation. See section 5.9 on page 56 for details on DMA support.

The following trigger levels are supported:

00 = FIFO empty

01 = 2 characters in the FIFO

10 = FIFO 1/4 full

11 = FIFO full

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_TET_E_FIFO_EMPTY 0x0 FIFO empty
ALT_UART_FCR_TET_E_FIFO_CHAR_2 0x1 2 characters in FIFO
ALT_UART_FCR_TET_E_FIFO_QUARTER_FULL 0x2 FIFO 1/4 full
ALT_UART_FCR_TET_E_FIFO_HALF_FULL 0x3 FIFO 1/2 full

Field Access Macros:

#define ALT_UART_FCR_TET_E_FIFO_EMPTY   0x0
 
#define ALT_UART_FCR_TET_E_FIFO_CHAR_2   0x1
 
#define ALT_UART_FCR_TET_E_FIFO_QUARTER_FULL   0x2
 
#define ALT_UART_FCR_TET_E_FIFO_HALF_FULL   0x3
 
#define ALT_UART_FCR_TET_LSB   4
 
#define ALT_UART_FCR_TET_MSB   5
 
#define ALT_UART_FCR_TET_WIDTH   2
 
#define ALT_UART_FCR_TET_SET_MSK   0x00000030
 
#define ALT_UART_FCR_TET_CLR_MSK   0xffffffcf
 
#define ALT_UART_FCR_TET_RESET   0x0
 
#define ALT_UART_FCR_TET_GET(value)   (((value) & 0x00000030) >> 4)
 
#define ALT_UART_FCR_TET_SET(value)   (((value) << 4) & 0x00000030)
 

Field : rt

Bits[7:6], RCVR Trigger (or RT):.

This is used to select the trigger level in the receiver FIFO at which the

Received Data Available Interrupt will be generated. In auto flow control mode

it is used to determine when the rts_n signal will be de-asserted. It also

determines when the dma_rx_req_n signal will be asserted when in certain modes

of operation. See section 5.9 on page 56 for details on DMA support. The

following trigger levels are supported:

00 = 1 character in the FIFO

01 = FIFO 1/4 full

10 = FIFO 1/2 full

11 = FIFO 2 less than full

Field Enumeration Values:

Enum Value Description
ALT_UART_FCR_RT_E_FIFO_CHAR_1 0x0 1 character in FIFO
ALT_UART_FCR_RT_E_FIFO_QUARTER_FULL 0x1 FIFO 1/4 full
ALT_UART_FCR_RT_E_FIFO_HALF_FULL 0x2 FIFO 1/2 full
ALT_UART_FCR_RT_E_FIFO_FULL_2 0x3 FIFO 2 less than full

Field Access Macros:

#define ALT_UART_FCR_RT_E_FIFO_CHAR_1   0x0
 
#define ALT_UART_FCR_RT_E_FIFO_QUARTER_FULL   0x1
 
#define ALT_UART_FCR_RT_E_FIFO_HALF_FULL   0x2
 
#define ALT_UART_FCR_RT_E_FIFO_FULL_2   0x3
 
#define ALT_UART_FCR_RT_LSB   6
 
#define ALT_UART_FCR_RT_MSB   7
 
#define ALT_UART_FCR_RT_WIDTH   2
 
#define ALT_UART_FCR_RT_SET_MSK   0x000000c0
 
#define ALT_UART_FCR_RT_CLR_MSK   0xffffff3f
 
#define ALT_UART_FCR_RT_RESET   0x0
 
#define ALT_UART_FCR_RT_GET(value)   (((value) & 0x000000c0) >> 6)
 
#define ALT_UART_FCR_RT_SET(value)   (((value) << 6) & 0x000000c0)
 

Data Structures

struct  ALT_UART_FCR_s
 

Macros

#define ALT_UART_FCR_RESET   0x00000000
 
#define ALT_UART_FCR_OFST   0x8
 
#define ALT_UART_FCR_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))
 

Typedefs

typedef struct ALT_UART_FCR_s ALT_UART_FCR_t
 

Data Structure Documentation

struct ALT_UART_FCR_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_UART_FCR.

Data Fields
uint32_t fifoe: 1 ALT_UART_FCR_FIFOE
uint32_t rfifor: 1 ALT_UART_FCR_RFIFOR
uint32_t xfifor: 1 ALT_UART_FCR_XFIFOR
uint32_t dmam: 1 ALT_UART_FCR_DMAM
uint32_t tet: 2 ALT_UART_FCR_TET
uint32_t rt: 2 ALT_UART_FCR_RT
uint32_t __pad0__: 24 UNDEFINED

Macro Definitions

#define ALT_UART_FCR_FIFOE_E_DISD   0x0

Enumerated value for register field ALT_UART_FCR_FIFOE

FIFO disabled

#define ALT_UART_FCR_FIFOE_E_END   0x1

Enumerated value for register field ALT_UART_FCR_FIFOE

FIFO enabled

#define ALT_UART_FCR_FIFOE_LSB   0

The Least Significant Bit (LSB) position of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_MSB   0

The Most Significant Bit (MSB) position of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_WIDTH   1

The width in bits of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_SET_MSK   0x00000001

The mask used to set the ALT_UART_FCR_FIFOE register field value.

#define ALT_UART_FCR_FIFOE_CLR_MSK   0xfffffffe

The mask used to clear the ALT_UART_FCR_FIFOE register field value.

#define ALT_UART_FCR_FIFOE_RESET   0x0

The reset value of the ALT_UART_FCR_FIFOE register field.

#define ALT_UART_FCR_FIFOE_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_UART_FCR_FIFOE field value from a register.

#define ALT_UART_FCR_FIFOE_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_UART_FCR_FIFOE register field value suitable for setting the register.

#define ALT_UART_FCR_RFIFOR_E_RST   0x1

Enumerated value for register field ALT_UART_FCR_RFIFOR

Receive FIFO reset

#define ALT_UART_FCR_RFIFOR_LSB   1

The Least Significant Bit (LSB) position of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_MSB   1

The Most Significant Bit (MSB) position of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_WIDTH   1

The width in bits of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_SET_MSK   0x00000002

The mask used to set the ALT_UART_FCR_RFIFOR register field value.

#define ALT_UART_FCR_RFIFOR_CLR_MSK   0xfffffffd

The mask used to clear the ALT_UART_FCR_RFIFOR register field value.

#define ALT_UART_FCR_RFIFOR_RESET   0x0

The reset value of the ALT_UART_FCR_RFIFOR register field.

#define ALT_UART_FCR_RFIFOR_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_UART_FCR_RFIFOR field value from a register.

#define ALT_UART_FCR_RFIFOR_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_UART_FCR_RFIFOR register field value suitable for setting the register.

#define ALT_UART_FCR_XFIFOR_E_RST   0x1

Enumerated value for register field ALT_UART_FCR_XFIFOR

Transmit FIFO reset

#define ALT_UART_FCR_XFIFOR_LSB   2

The Least Significant Bit (LSB) position of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_MSB   2

The Most Significant Bit (MSB) position of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_WIDTH   1

The width in bits of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_SET_MSK   0x00000004

The mask used to set the ALT_UART_FCR_XFIFOR register field value.

#define ALT_UART_FCR_XFIFOR_CLR_MSK   0xfffffffb

The mask used to clear the ALT_UART_FCR_XFIFOR register field value.

#define ALT_UART_FCR_XFIFOR_RESET   0x0

The reset value of the ALT_UART_FCR_XFIFOR register field.

#define ALT_UART_FCR_XFIFOR_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_UART_FCR_XFIFOR field value from a register.

#define ALT_UART_FCR_XFIFOR_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_UART_FCR_XFIFOR register field value suitable for setting the register.

#define ALT_UART_FCR_DMAM_E_MOD0   0x0

Enumerated value for register field ALT_UART_FCR_DMAM

Mode 0

#define ALT_UART_FCR_DMAM_E_MOD1   0x1

Enumerated value for register field ALT_UART_FCR_DMAM

Mode 1

#define ALT_UART_FCR_DMAM_LSB   3

The Least Significant Bit (LSB) position of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_MSB   3

The Most Significant Bit (MSB) position of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_WIDTH   1

The width in bits of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_SET_MSK   0x00000008

The mask used to set the ALT_UART_FCR_DMAM register field value.

#define ALT_UART_FCR_DMAM_CLR_MSK   0xfffffff7

The mask used to clear the ALT_UART_FCR_DMAM register field value.

#define ALT_UART_FCR_DMAM_RESET   0x0

The reset value of the ALT_UART_FCR_DMAM register field.

#define ALT_UART_FCR_DMAM_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_UART_FCR_DMAM field value from a register.

#define ALT_UART_FCR_DMAM_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_UART_FCR_DMAM register field value suitable for setting the register.

#define ALT_UART_FCR_TET_E_FIFO_EMPTY   0x0

Enumerated value for register field ALT_UART_FCR_TET

FIFO empty

#define ALT_UART_FCR_TET_E_FIFO_CHAR_2   0x1

Enumerated value for register field ALT_UART_FCR_TET

2 characters in FIFO

#define ALT_UART_FCR_TET_E_FIFO_QUARTER_FULL   0x2

Enumerated value for register field ALT_UART_FCR_TET

FIFO 1/4 full

#define ALT_UART_FCR_TET_E_FIFO_HALF_FULL   0x3

Enumerated value for register field ALT_UART_FCR_TET

FIFO 1/2 full

#define ALT_UART_FCR_TET_LSB   4

The Least Significant Bit (LSB) position of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_MSB   5

The Most Significant Bit (MSB) position of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_WIDTH   2

The width in bits of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_SET_MSK   0x00000030

The mask used to set the ALT_UART_FCR_TET register field value.

#define ALT_UART_FCR_TET_CLR_MSK   0xffffffcf

The mask used to clear the ALT_UART_FCR_TET register field value.

#define ALT_UART_FCR_TET_RESET   0x0

The reset value of the ALT_UART_FCR_TET register field.

#define ALT_UART_FCR_TET_GET (   value)    (((value) & 0x00000030) >> 4)

Extracts the ALT_UART_FCR_TET field value from a register.

#define ALT_UART_FCR_TET_SET (   value)    (((value) << 4) & 0x00000030)

Produces a ALT_UART_FCR_TET register field value suitable for setting the register.

#define ALT_UART_FCR_RT_E_FIFO_CHAR_1   0x0

Enumerated value for register field ALT_UART_FCR_RT

1 character in FIFO

#define ALT_UART_FCR_RT_E_FIFO_QUARTER_FULL   0x1

Enumerated value for register field ALT_UART_FCR_RT

FIFO 1/4 full

#define ALT_UART_FCR_RT_E_FIFO_HALF_FULL   0x2

Enumerated value for register field ALT_UART_FCR_RT

FIFO 1/2 full

#define ALT_UART_FCR_RT_E_FIFO_FULL_2   0x3

Enumerated value for register field ALT_UART_FCR_RT

FIFO 2 less than full

#define ALT_UART_FCR_RT_LSB   6

The Least Significant Bit (LSB) position of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_MSB   7

The Most Significant Bit (MSB) position of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_WIDTH   2

The width in bits of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_SET_MSK   0x000000c0

The mask used to set the ALT_UART_FCR_RT register field value.

#define ALT_UART_FCR_RT_CLR_MSK   0xffffff3f

The mask used to clear the ALT_UART_FCR_RT register field value.

#define ALT_UART_FCR_RT_RESET   0x0

The reset value of the ALT_UART_FCR_RT register field.

#define ALT_UART_FCR_RT_GET (   value)    (((value) & 0x000000c0) >> 6)

Extracts the ALT_UART_FCR_RT field value from a register.

#define ALT_UART_FCR_RT_SET (   value)    (((value) << 6) & 0x000000c0)

Produces a ALT_UART_FCR_RT register field value suitable for setting the register.

#define ALT_UART_FCR_RESET   0x00000000

The reset value of the ALT_UART_FCR register.

#define ALT_UART_FCR_OFST   0x8

The byte offset of the ALT_UART_FCR register from the beginning of the component.

#define ALT_UART_FCR_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_UART_FCR_OFST))

The address of the ALT_UART_FCR register.

Typedef Documentation

The typedef declaration for register ALT_UART_FCR.