Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Select source for UART0 signals (HPS Pins or FPGA Interface) - pinmux_uart0_usefpga

Description

Selection between HPS Pin and FPGA Interface for UART0 signals

Only reset by a cold reset (ignores warm reset).

NOTE: These registers should not be modified after IO configuration.There is no support for dynamically changing the Pin Mux selections.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Selection for UART0 signals
[31:1] R 0x0 ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD

Field : Selection for UART0 signals - sel

Select connection for UART0.

0 : UART0 uses HPS IO Pins.

1 : UART0 uses the FPGA Inteface.

Field Access Macros:

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_LSB   0
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_MSB   0
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_WIDTH   1
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET_MSK   0x00000001
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_CLR_MSK   0xfffffffe
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_RESET   0x0
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Reserved

Reserved

Field Access Macros:

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_LSB   1
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_MSB   31
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_WIDTH   31
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET_MSK   0xfffffffe
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_CLR_MSK   0x00000001
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_RESET   0x0
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_GET(value)   (((value) & 0xfffffffe) >> 1)
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET(value)   (((value) << 1) & 0xfffffffe)
 

Data Structures

struct  ALT_PINMUX_FPGA_UART0_USEFPGA_s
 

Macros

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RESET   0x00000000
 
#define ALT_PINMUX_FPGA_UART0_USEFPGA_OFST   0x3c
 

Typedefs

typedef struct
ALT_PINMUX_FPGA_UART0_USEFPGA_s 
ALT_PINMUX_FPGA_UART0_USEFPGA_t
 

Data Structure Documentation

struct ALT_PINMUX_FPGA_UART0_USEFPGA_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_PINMUX_FPGA_UART0_USEFPGA.

Data Fields
uint32_t sel: 1 Selection for UART0 signals
const uint32_t Reserved: 31 ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD

Macro Definitions

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_MSB   0

The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_WIDTH   1

The width in bits of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET_MSK   0x00000001

The mask used to set the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_CLR_MSK   0xfffffffe

The mask used to clear the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_RESET   0x0

The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_PINMUX_FPGA_UART0_USEFPGA_SEL field value from a register.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_SEL_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_PINMUX_FPGA_UART0_USEFPGA_SEL register field value suitable for setting the register.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_LSB   1

The Least Significant Bit (LSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_MSB   31

The Most Significant Bit (MSB) position of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_WIDTH   31

The width in bits of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET_MSK   0xfffffffe

The mask used to set the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_CLR_MSK   0x00000001

The mask used to clear the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_RESET   0x0

The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_GET (   value)    (((value) & 0xfffffffe) >> 1)

Extracts the ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD field value from a register.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD_SET (   value)    (((value) << 1) & 0xfffffffe)

Produces a ALT_PINMUX_FPGA_UART0_USEFPGA_RSVD register field value suitable for setting the register.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_RESET   0x00000000

The reset value of the ALT_PINMUX_FPGA_UART0_USEFPGA register.

#define ALT_PINMUX_FPGA_UART0_USEFPGA_OFST   0x3c

The byte offset of the ALT_PINMUX_FPGA_UART0_USEFPGA register from the beginning of the component.

Typedef Documentation