Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dbgcfg0

Description

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL
[1] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL
[2] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL
[3] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN
[4] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL
[8:5] RW 0x0 ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD
[31:9] ??? 0x0 UNDEFINED

Field : cfg_wdata_driver_sel

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB   0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB   0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK   0x00000001
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK   0xfffffffe
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET(value)   (((value) << 0) & 0x00000001)
 

Field : cfg_prbs_ctrl_sel

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_LSB   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_MSB   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET_MSK   0x00000002
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_CLR_MSK   0xfffffffd
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET(value)   (((value) << 1) & 0x00000002)
 

Field : cfg_mmr_driver_sel

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_LSB   2
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_MSB   2
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET_MSK   0x00000004
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_CLR_MSK   0xfffffffb
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET(value)   (((value) << 2) & 0x00000004)
 

Field : cfg_loopback_en

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_LSB   3
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_MSB   3
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK   0x00000008
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK   0xfffffff7
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET(value)   (((value) << 3) & 0x00000008)
 

Field : cfg_cmd_driver_sel

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB   4
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB   4
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH   1
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK   0x00000010
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK   0xffffffef
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET(value)   (((value) << 4) & 0x00000010)
 

Field : cfg_dbg_mode

TBD

Field Access Macros:

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_LSB   5
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_MSB   8
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_WIDTH   4
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET_MSK   0x000001e0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_CLR_MSK   0xfffffe1f
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_GET(value)   (((value) & 0x000001e0) >> 5)
 
#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET(value)   (((value) << 5) & 0x000001e0)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DBGCFG0_s
 

Macros

#define ALT_IO48_HMC_MMR_DBGCFG0_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DBGCFG0_OFST   0x0
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DBGCFG0_s 
ALT_IO48_HMC_MMR_DBGCFG0_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DBGCFG0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DBGCFG0.

Data Fields
uint32_t cfg_wdata_driver_sel: 1 ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL
uint32_t cfg_prbs_ctrl_sel: 1 ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL
uint32_t cfg_mmr_driver_sel: 1 ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL
uint32_t cfg_loopback_en: 1 ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN
uint32_t cfg_cmd_driver_sel: 1 ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL
uint32_t cfg_dbg_mode: 4 ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD
uint32_t __pad0__: 23 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_MSB   0

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET_MSK   0x00000001

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_CLR_MSK   0xfffffffe

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_WDATA_DRIVER_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_LSB   1

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_MSB   1

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET_MSK   0x00000002

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_CLR_MSK   0xfffffffd

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_PRBS_CTL_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_LSB   2

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_MSB   2

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET_MSK   0x00000004

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_CLR_MSK   0xfffffffb

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_MMR_DRIVER_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_LSB   3

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_MSB   3

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET_MSK   0x00000008

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_CLR_MSK   0xfffffff7

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_LOOPBACK_EN register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_LSB   4

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_MSB   4

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_WIDTH   1

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET_MSK   0x00000010

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_CLR_MSK   0xffffffef

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_CMD_DRIVER_SEL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_LSB   5

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_MSB   8

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_WIDTH   4

The width in bits of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET_MSK   0x000001e0

The mask used to set the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_CLR_MSK   0xfffffe1f

The mask used to clear the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_GET (   value)    (((value) & 0x000001e0) >> 5)

Extracts the ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD field value from a register.

#define ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD_SET (   value)    (((value) << 5) & 0x000001e0)

Produces a ALT_IO48_HMC_MMR_DBGCFG0_CFG_DBG_MOD register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DBGCFG0_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DBGCFG0 register.

#define ALT_IO48_HMC_MMR_DBGCFG0_OFST   0x0

The byte offset of the ALT_IO48_HMC_MMR_DBGCFG0 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DBGCFG0.