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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 55 (Watchdog Timeout Register)
This register controls the watchdog timeout for received frames.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[13:0] | RW | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_WTO |
[15:14] | R | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 |
[16] | RW | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_PWE |
[31:17] | R | 0x0 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 |
Field : wto | |
Watchdog Timeout When Bit 16 (PWE) is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, this field is used as watchdog timeout for a received frame. If the length of a received frame exceeds the value of this field, such frame is terminated and declared as an error frame. Note: When Bit 16 (PWE) is set, the value in this field should be more than 1,522 (0x05F2). Otherwise, the IEEE Std 802.3-specified valid tagged frames are declared as error frames and are dropped. Field Access Macros: | |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_LSB 0 |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_MSB 13 |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_WIDTH 14 |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_SET_MSK 0x00003fff |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_CLR_MSK 0xffffc000 |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_RESET 0x0 |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_GET(value) (((value) & 0x00003fff) >> 0) |
#define | ALT_EMAC_GMAC_WDOG_TMO_WTO_SET(value) (((value) << 0) & 0x00003fff) |
Field : reserved_15_14 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_LSB 14 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_MSB 15 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_WIDTH 2 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET_MSK 0x0000c000 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_CLR_MSK 0xffff3fff |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_RESET 0x0 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_GET(value) (((value) & 0x0000c000) >> 14) |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET(value) (((value) << 14) & 0x0000c000) |
Field : pwe | |
Programmable Watchdog Enable When this bit is set and Bit 23 (WD) of Register 0 (MAC Configuration Register) is reset, the WTO field (Bits[13:0]) is used as watchdog timeout for a received frame. When this bit is cleared, the watchdog timeout for a received frame is controlled by the setting of Bit 23 (WD) and Bit 20 (JE) in Register 0 (MAC Configuration Register). Field Access Macros: | |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_LSB 16 |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_MSB 16 |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_WIDTH 1 |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_RESET 0x0 |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_WDOG_TMO_PWE_SET(value) (((value) << 16) & 0x00010000) |
Field : reserved_31_17 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_LSB 17 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_MSB 31 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_WIDTH 15 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET_MSK 0xfffe0000 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_CLR_MSK 0x0001ffff |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_RESET 0x0 |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_GET(value) (((value) & 0xfffe0000) >> 17) |
#define | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET(value) (((value) << 17) & 0xfffe0000) |
Data Structures | |
struct | ALT_EMAC_GMAC_WDOG_TMO_s |
Macros | |
#define | ALT_EMAC_GMAC_WDOG_TMO_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_WDOG_TMO_OFST 0xdc |
#define | ALT_EMAC_GMAC_WDOG_TMO_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_WDOG_TMO_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_WDOG_TMO_s | ALT_EMAC_GMAC_WDOG_TMO_t |
struct ALT_EMAC_GMAC_WDOG_TMO_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_WDOG_TMO.
Data Fields | ||
---|---|---|
uint32_t | wto: 14 | ALT_EMAC_GMAC_WDOG_TMO_WTO |
const uint32_t | reserved_15_14: 2 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 |
uint32_t | pwe: 1 | ALT_EMAC_GMAC_WDOG_TMO_PWE |
const uint32_t | reserved_31_17: 15 | ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 |
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_WIDTH 14 |
The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_SET_MSK 0x00003fff |
The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_WTO register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_CLR_MSK 0xffffc000 |
The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_WTO register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_WDOG_TMO_WTO register field.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_GET | ( | value | ) | (((value) & 0x00003fff) >> 0) |
Extracts the ALT_EMAC_GMAC_WDOG_TMO_WTO field value from a register.
#define ALT_EMAC_GMAC_WDOG_TMO_WTO_SET | ( | value | ) | (((value) << 0) & 0x00003fff) |
Produces a ALT_EMAC_GMAC_WDOG_TMO_WTO register field value suitable for setting the register.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET_MSK 0x0000c000 |
The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_CLR_MSK 0xffff3fff |
The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_GET | ( | value | ) | (((value) & 0x0000c000) >> 14) |
Extracts the ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 field value from a register.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14_SET | ( | value | ) | (((value) << 14) & 0x0000c000) |
Produces a ALT_EMAC_GMAC_WDOG_TMO_RSVD_15_14 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_PWE register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_PWE register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_WDOG_TMO_PWE register field.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_WDOG_TMO_PWE field value from a register.
#define ALT_EMAC_GMAC_WDOG_TMO_PWE_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_WDOG_TMO_PWE register field value suitable for setting the register.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_WIDTH 15 |
The width in bits of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET_MSK 0xfffe0000 |
The mask used to set the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_CLR_MSK 0x0001ffff |
The mask used to clear the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_GET | ( | value | ) | (((value) & 0xfffe0000) >> 17) |
Extracts the ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 field value from a register.
#define ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17_SET | ( | value | ) | (((value) << 17) & 0xfffe0000) |
Produces a ALT_EMAC_GMAC_WDOG_TMO_RSVD_31_17 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_WDOG_TMO_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_WDOG_TMO register.
#define ALT_EMAC_GMAC_WDOG_TMO_OFST 0xdc |
The byte offset of the ALT_EMAC_GMAC_WDOG_TMO register from the beginning of the component.
#define ALT_EMAC_GMAC_WDOG_TMO_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_WDOG_TMO_OFST)) |
The address of the ALT_EMAC_GMAC_WDOG_TMO register.
typedef struct ALT_EMAC_GMAC_WDOG_TMO_s ALT_EMAC_GMAC_WDOG_TMO_t |
The typedef declaration for register ALT_EMAC_GMAC_WDOG_TMO.