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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Used to disable individual interfaces between the FPGA and HPS.
This register is reset only on a cold reset (ignores warm reset).
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x1 | Reset Request Interface |
[7:1] | ??? | 0x7f | UNDEFINED |
[8] | RW | 0x1 | CONFIG_IO Interface |
[15:9] | ??? | 0x7f | UNDEFINED |
[16] | RW | 0x1 | Boundary-Scan Interface |
[31:17] | ??? | 0x7fff | UNDEFINED |
Field : Reset Request Interface - rstreq | |
Used to disable the reset request interface. This interface allows logic in the FPGA fabric to request HPS resets. This field disables the following reset request signals from the FPGA fabric to HPS:[list][*]f2s_cold_rst_req - Triggers a cold reset of the HPS[*]f2s_warm_rst_req - Triggers a warm reset of the HPS[*]f2s_dbg_rst_req - Triggers a debug reset of the HPS[/list] Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_LSB 0 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_MSB 0 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET_MSK 0x00000001 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_CLR_MSK 0xfffffffe |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_RESET 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET(value) (((value) << 0) & 0x00000001) |
Field : CONFIG_IO Interface - cfgio | |
Used to disable the CONFIG_IO interface. This interface allows the FPGA JTAG TAP controller to execute the CONFIG_IO instruction and configure all device I/Os (FPGA and HPS). This is typically done before executing boundary-scan instructions. The CONFIG_IO interface must be enabled before attempting to send the CONFIG_IO instruction to the FPGA JTAG TAP controller. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_LSB 8 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_MSB 8 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET_MSK 0x00000100 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_CLR_MSK 0xfffffeff |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_RESET 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET(value) (((value) << 8) & 0x00000100) |
Field : Boundary-Scan Interface - bscan | |
Used to disable the boundary-scan interface. This interface allows the FPGA JTAG TAP controller to execute boundary-scan instructions such as SAMPLE/PRELOAD, EXTEST, and HIGHZ. The boundary-scan interface must be enabled before attempting to send the boundary-scan instructions to the FPGA JTAG TAP controller. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS | 0x0 | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN | 0x1 | Field Access Macros: | |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS 0x0 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_LSB 16 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_MSB 16 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_WIDTH 1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET_MSK 0x00010000 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_CLR_MSK 0xfffeffff |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_RESET 0x1 |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET(value) (((value) << 16) & 0x00010000) |
Data Structures | |
struct | ALT_SYSMGR_FPGAINTF_EN_0_s |
Macros | |
#define | ALT_SYSMGR_FPGAINTF_EN_0_RESET 0xffffffff |
#define | ALT_SYSMGR_FPGAINTF_EN_0_OFST 0x64 |
Typedefs | |
typedef struct ALT_SYSMGR_FPGAINTF_EN_0_s | ALT_SYSMGR_FPGAINTF_EN_0_t |
struct ALT_SYSMGR_FPGAINTF_EN_0_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_SYSMGR_FPGAINTF_EN_0.
Data Fields | ||
---|---|---|
uint32_t | rstreq: 1 | Reset Request Interface |
uint32_t | __pad0__: 7 | UNDEFINED |
uint32_t | cfgio: 1 | CONFIG_IO Interface |
uint32_t | __pad1__: 7 | UNDEFINED |
uint32_t | bscan: 1 | Boundary-Scan Interface |
uint32_t | __pad2__: 15 | UNDEFINED |
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET_MSK 0x00000001 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_RESET 0x1 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_SYSMGR_FPGAINTF_EN_0_RSTREQ register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_CFGIO
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_CFGIO
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET_MSK 0x00000100 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_RESET 0x1 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_0_CFGIO field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_0_CFGIO_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_SYSMGR_FPGAINTF_EN_0_CFGIO register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_DIS 0x0 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_BSCAN
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_E_EN 0x1 |
Enumerated value for register field ALT_SYSMGR_FPGAINTF_EN_0_BSCAN
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_WIDTH 1 |
The width in bits of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET_MSK 0x00010000 |
The mask used to set the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_RESET 0x1 |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_SYSMGR_FPGAINTF_EN_0_BSCAN field value from a register.
#define ALT_SYSMGR_FPGAINTF_EN_0_BSCAN_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_SYSMGR_FPGAINTF_EN_0_BSCAN register field value suitable for setting the register.
#define ALT_SYSMGR_FPGAINTF_EN_0_RESET 0xffffffff |
The reset value of the ALT_SYSMGR_FPGAINTF_EN_0 register.
#define ALT_SYSMGR_FPGAINTF_EN_0_OFST 0x64 |
The byte offset of the ALT_SYSMGR_FPGAINTF_EN_0 register from the beginning of the component.
typedef struct ALT_SYSMGR_FPGAINTF_EN_0_s ALT_SYSMGR_FPGAINTF_EN_0_t |
The typedef declaration for register ALT_SYSMGR_FPGAINTF_EN_0.