Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : Register 448 (Timestamp Control Register) - Timestamp_Control

Description

This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.

Register Layout

Bits Access Reset Description
[0] RW 0x0 Timestamp Enable
[1] RW 0x0 Timestamp Fine or Coarse Update
[2] RW 0x0 Timestamp Initialize
[3] RW 0x0 Timestamp Update
[4] RW 0x0 Timestamp Interrupt Trigger Enable
[5] RW 0x0 Addend Reg Update
[7:6] ??? 0x0 UNDEFINED
[8] RW 0x0 Enable Timestamp for All Frames
[9] RW 0x0 Timestamp Digital or Binary Rollover Control
[10] RW 0x0 Enable PTP packet Processing for Version 2 Format
[11] RW 0x0 Enable Processing of PTP over Ethernet Frames
[12] RW 0x0 Enable Processing of PTP Frames Sent Over IPv6-UDP
[13] RW 0x1 Enable Processing of PTP Frames Sent over IPv4-UDP
[14] RW 0x0 Enable Timestamp Snapshot for Event Messages
[15] RW 0x0 Enable Snapshot for Messages Relevant to Master
[17:16] RW 0x0 Select PTP packets for Taking Snapshots
[18] RW 0x0 Enable MAC address for PTP Frame Filtering
[23:19] ??? 0x0 UNDEFINED
[24] RW 0x0 Auxiliary Snapshot FIFO Clear
[25] RW 0x0 Auxiliary Snapshot 0 Enable
[31:26] ??? 0x0 UNDEFINED

Field : Timestamp Enable - tsena

When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode.

On the receive side, the MAC processes the 1588 frames only if this bit is set.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0 Timestamp not added
ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1 Timestamp added for transmit and receive

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB   0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB   0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK   0x00000001
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Timestamp Fine or Coarse Update - tscfupdt

When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0 Timestamp Coarse
ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1 Timestamp Fine

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK   0x00000002
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value)   (((value) << 1) & 0x00000002)
 

Field : Timestamp Initialize - tsinit

When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register).

This bit should be read zero before updating it. This bit is reset when the initialization is complete. The Timestamp Higher Word register can only be initialized.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0 Timestamp not initialized (overwritten) by
: values in Register 452 and Register 453
ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1 Timestamp initialized (overwritten) by values in
: Register 452 and Register 453

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB   2
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB   2
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK   0x00000004
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value)   (((value) << 2) & 0x00000004)
 

Field : Timestamp Update - tsupdt

When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register).

This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The Timestamp Higher Word register is not updated.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0 Timestamp not updated (added or subtracted) with
: values in Register 452 and Register 453
ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1 Timestamp updated (added or subtracted) with
: values in Register 452 and Register 453

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB   3
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB   3
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK   0x00000008
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK   0xfffffff7
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value)   (((value) << 3) & 0x00000008)
 

Field : Timestamp Interrupt Trigger Enable - tstrig

When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0 Timestamp not generated
ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1 Timestamp generated

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB   4
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB   4
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK   0x00000010
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK   0xffffffef
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value)   (((value) << 4) & 0x00000010)
 

Field : Addend Reg Update - tsaddreg

When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0 Timestamp Addend register is not updated
ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1 Timestamp Addend register is updated

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB   5
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB   5
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK   0x00000020
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value)   (((value) << 5) & 0x00000020)
 

Field : Enable Timestamp for All Frames - tsenall

When set, the timestamp snapshot is enabled for all frames received by the MAC.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0 Timestamp snapshot disabled
ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1 Timestamp snapshot enabled

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB   8
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB   8
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK   0x00000100
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value)   (((value) << 8) & 0x00000100)
 

Field : Timestamp Digital or Binary Rollover Control - tsctrlssr

When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0 Timestamp Low register rolls over at 0x7FFF_FFFF
ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1 Timestamp Low register rolls over at 1ns

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB   9
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB   9
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK   0x00000200
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK   0xfffffdff
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value)   (((value) << 9) & 0x00000200)
 

Field : Enable PTP packet Processing for Version 2 Format - tsver2ena

When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0 PTP packets processed with 1588 version 1 format
ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1 PTP packets processed with 1588 version 2 format

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB   10
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB   10
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK   0x00000400
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK   0xfffffbff
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value)   (((value) << 10) & 0x00000400)
 

Field : Enable Processing of PTP over Ethernet Frames - tsipena

When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0 Don't process PTP packets in Ethernet frames
ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1 Process PTP packets in Ethernet frames

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB   11
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB   11
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK   0x00000800
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK   0xfffff7ff
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value)   (((value) << 11) & 0x00000800)
 

Field : Enable Processing of PTP Frames Sent Over IPv6-UDP - tsipv6ena

When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP- IPv6 packets.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0 Don't process PTP packets in UDP over IPv6
ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1 Process PTP packets in UDP over IPv6

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB   12
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB   12
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK   0x00001000
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK   0xffffefff
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value)   (((value) << 12) & 0x00001000)
 

Field : Enable Processing of PTP Frames Sent over IPv4-UDP - tsipv4ena

When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0 Don't process PTP packets in UDP over IPv4
ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1 Process PTP packets in UDP over IPv4

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB   13
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB   13
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK   0x00002000
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value)   (((value) << 13) & 0x00002000)
 

Field : Enable Timestamp Snapshot for Event Messages - tsevntena

When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0 Timestamp snapshot disabled for event messages
ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1 Timestamp snapshot only for event messages

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB   14
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB   14
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK   0x00004000
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK   0xffffbfff
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value)   (((value) << 14) & 0x00004000)
 

Field : Enable Snapshot for Messages Relevant to Master - tsmstrena

When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0 Timestamp snapshot taken for messages relevant
: to slave node
ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1 Timestamp snapshot taken for messages relevant
: to master node

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB   15
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB   15
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK   0x00008000
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK   0xffff7fff
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value)   (((value) << 15) & 0x00008000)
 

Field : Select PTP packets for Taking Snapshots - snaptypsel

These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken.

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB   16
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB   17
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH   2
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK   0x00030000
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK   0xfffcffff
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value)   (((value) & 0x00030000) >> 16)
 
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value)   (((value) << 16) & 0x00030000)
 

Field : Enable MAC address for PTP Frame Filtering - tsenmacaddr

When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0 DA MAC address doesn't filter PTP frames
ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1 DA MAC address filters PTP frames

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB   18
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB   18
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK   0x00040000
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK   0xfffbffff
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value)   (((value) << 18) & 0x00040000)
 

Field : Auxiliary Snapshot FIFO Clear - atsfc

When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0 Don't reset Auxiliary Snapshot FIFO pointers
ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1 Reset Auxiliary Snapshot FIFO pointers

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB   24
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB   24
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK   0x01000000
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value)   (((value) << 24) & 0x01000000)
 

Field : Auxiliary Snapshot 0 Enable - atsen0

This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored.

Field Enumeration Values:

Enum Value Description
ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0 Auxiliary snapshot of event on ptp_aux_trig_i[0]
: input is disabled.
ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1 Auxiliary snapshot of event on ptp_aux_trig_i[0]
: input is enabled.

Field Access Macros:

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END   0x1
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB   25
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB   25
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH   1
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK   0x02000000
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET   0x0
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value)   (((value) << 25) & 0x02000000)
 

Data Structures

struct  ALT_EMAC_GMAC_TS_CTL_s
 

Macros

#define ALT_EMAC_GMAC_TS_CTL_OFST   0x700
 
#define ALT_EMAC_GMAC_TS_CTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST))
 

Typedefs

typedef struct
ALT_EMAC_GMAC_TS_CTL_s 
ALT_EMAC_GMAC_TS_CTL_t
 

Data Structure Documentation

struct ALT_EMAC_GMAC_TS_CTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_GMAC_TS_CTL.

Data Fields
uint32_t tsena: 1 Timestamp Enable
uint32_t tscfupdt: 1 Timestamp Fine or Coarse Update
uint32_t tsinit: 1 Timestamp Initialize
uint32_t tsupdt: 1 Timestamp Update
uint32_t tstrig: 1 Timestamp Interrupt Trigger Enable
uint32_t tsaddreg: 1 Addend Reg Update
uint32_t __pad0__: 2 UNDEFINED
uint32_t tsenall: 1 Enable Timestamp for All Frames
uint32_t tsctrlssr: 1 Timestamp Digital or Binary Rollover Control
uint32_t tsver2ena: 1 Enable PTP packet Processing for Version 2 Format
uint32_t tsipena: 1 Enable Processing of PTP over Ethernet Frames
uint32_t tsipv6ena: 1 Enable Processing of PTP Frames Sent Over IPv6-UDP
uint32_t tsipv4ena: 1 Enable Processing of PTP Frames Sent over IPv4-UDP
uint32_t tsevntena: 1 Enable Timestamp Snapshot for Event Messages
uint32_t tsmstrena: 1 Enable Snapshot for Messages Relevant to Master
uint32_t snaptypsel: 2 Select PTP packets for Taking Snapshots
uint32_t tsenmacaddr: 1 Enable MAC address for PTP Frame Filtering
uint32_t __pad1__: 5 UNDEFINED
uint32_t atsfc: 1 Auxiliary Snapshot FIFO Clear
uint32_t atsen0: 1 Auxiliary Snapshot 0 Enable
uint32_t __pad2__: 6 UNDEFINED

Macro Definitions

#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA

Timestamp not added

#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA

Timestamp added for transmit and receive

#define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT

Timestamp Coarse

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT

Timestamp Fine

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT

Timestamp not initialized (overwritten) by values in Register 452 and Register 453

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT

Timestamp initialized (overwritten) by values in Register 452 and Register 453

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT

Timestamp not updated (added or subtracted) with values in Register 452 and Register 453

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT

Timestamp updated (added or subtracted) with values in Register 452 and Register 453

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB   3

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK   0x00000008

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK   0xfffffff7

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG

Timestamp not generated

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG

Timestamp generated

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB   4

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK   0x00000010

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK   0xffffffef

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG

Timestamp Addend register is not updated

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG

Timestamp Addend register is updated

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL

Timestamp snapshot disabled

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL

Timestamp snapshot enabled

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR

Timestamp Low register rolls over at 0x7FFF_FFFF

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR

Timestamp Low register rolls over at 1ns

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB   9

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK   0x00000200

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK   0xfffffdff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA

PTP packets processed with 1588 version 1 format

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA

PTP packets processed with 1588 version 2 format

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB   10

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK   0x00000400

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK   0xfffffbff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA

Don't process PTP packets in Ethernet frames

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA

Process PTP packets in Ethernet frames

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB   11

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK   0x00000800

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA

Don't process PTP packets in UDP over IPv6

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA

Process PTP packets in UDP over IPv6

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB   12

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK   0x00001000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK   0xffffefff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA

Don't process PTP packets in UDP over IPv4

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA

Process PTP packets in UDP over IPv4

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET   0x1

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA

Timestamp snapshot disabled for event messages

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA

Timestamp snapshot only for event messages

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB   14

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK   0x00004000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK   0xffffbfff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA

Timestamp snapshot taken for messages relevant to slave node

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA

Timestamp snapshot taken for messages relevant to master node

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB   15

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB   15

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK   0x00008000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK   0xffff7fff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB   16

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB   17

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH   2

The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK   0x00030000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK   0xfffcffff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET (   value)    (((value) & 0x00030000) >> 16)

Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET (   value)    (((value) << 16) & 0x00030000)

Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR

DA MAC address doesn't filter PTP frames

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR

DA MAC address filters PTP frames

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB   18

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB   18

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK   0x00040000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK   0xfffbffff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC

Don't reset Auxiliary Snapshot FIFO pointers

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC

Reset Auxiliary Snapshot FIFO pointers

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD   0x0

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0

Auxiliary snapshot of event on ptp_aux_trig_i[0] input is disabled.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END   0x1

Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0

Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH   1

The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET   0x0

The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register.

#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register.

#define ALT_EMAC_GMAC_TS_CTL_OFST   0x700

The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component.

#define ALT_EMAC_GMAC_TS_CTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST))

The address of the ALT_EMAC_GMAC_TS_CTL register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_GMAC_TS_CTL.