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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Name: I2C Receive Data Level Register
Size: log2(IC_RX_BUFFER_DEPTH) bits
Address Offset: 0x90
Read/Write Access: Read/Write
This register is only valid when DW_apb_i2c
is configured with a set of DMA interface signals
(IC_HAS_DMA = 1). When DW_apb_i2c is not configured
for DMA operation, this register does not exist;
writing to its address has no effect; reading from
its address returns zero.
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x0 | ALT_I2C_DMA_RDLR_DMARDL |
[31:6] | ??? | 0x0 | UNDEFINED |
Field : dmardl | |
Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO. Reset value: 0x0 Field Access Macros: | |
#define | ALT_I2C_DMA_RDLR_DMARDL_LSB 0 |
#define | ALT_I2C_DMA_RDLR_DMARDL_MSB 5 |
#define | ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 |
#define | ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f |
#define | ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 |
#define | ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 |
#define | ALT_I2C_DMA_RDLR_DMARDL_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_I2C_DMA_RDLR_DMARDL_SET(value) (((value) << 0) & 0x0000003f) |
Data Structures | |
struct | ALT_I2C_DMA_RDLR_s |
Macros | |
#define | ALT_I2C_DMA_RDLR_RESET 0x00000000 |
#define | ALT_I2C_DMA_RDLR_OFST 0x90 |
#define | ALT_I2C_DMA_RDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) |
Typedefs | |
typedef struct ALT_I2C_DMA_RDLR_s | ALT_I2C_DMA_RDLR_t |
struct ALT_I2C_DMA_RDLR_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_I2C_DMA_RDLR.
Data Fields | ||
---|---|---|
uint32_t | dmardl: 6 | ALT_I2C_DMA_RDLR_DMARDL |
uint32_t | __pad0__: 26 | UNDEFINED |
#define ALT_I2C_DMA_RDLR_DMARDL_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field.
#define ALT_I2C_DMA_RDLR_DMARDL_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_I2C_DMA_RDLR_DMARDL register field.
#define ALT_I2C_DMA_RDLR_DMARDL_WIDTH 6 |
The width in bits of the ALT_I2C_DMA_RDLR_DMARDL register field.
#define ALT_I2C_DMA_RDLR_DMARDL_SET_MSK 0x0000003f |
The mask used to set the ALT_I2C_DMA_RDLR_DMARDL register field value.
#define ALT_I2C_DMA_RDLR_DMARDL_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_I2C_DMA_RDLR_DMARDL register field value.
#define ALT_I2C_DMA_RDLR_DMARDL_RESET 0x0 |
The reset value of the ALT_I2C_DMA_RDLR_DMARDL register field.
#define ALT_I2C_DMA_RDLR_DMARDL_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_I2C_DMA_RDLR_DMARDL field value from a register.
#define ALT_I2C_DMA_RDLR_DMARDL_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_I2C_DMA_RDLR_DMARDL register field value suitable for setting the register.
#define ALT_I2C_DMA_RDLR_RESET 0x00000000 |
The reset value of the ALT_I2C_DMA_RDLR register.
#define ALT_I2C_DMA_RDLR_OFST 0x90 |
The byte offset of the ALT_I2C_DMA_RDLR register from the beginning of the component.
#define ALT_I2C_DMA_RDLR_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_DMA_RDLR_OFST)) |
The address of the ALT_I2C_DMA_RDLR register.
typedef struct ALT_I2C_DMA_RDLR_s ALT_I2C_DMA_RDLR_t |
The typedef declaration for register ALT_I2C_DMA_RDLR.