Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Probe_SoC2FPGA_main_Probe_Filters_1_Opcode

Description

Packet Probe register Opcode is a 4-bit register that selects candidate packets based on packet opcodes (0 disables the filter):

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN
[1] RW 0x0 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN
[2] RW 0x0 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN
[3] RW 0x0 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN
[31:4] ??? Unknown UNDEFINED

Field : RDEN

Selects RD packets.

Field Access Macros:

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_LSB   0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_MSB   0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_WIDTH   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK   0x00000001
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK   0xfffffffe
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_RESET   0x0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET(value)   (((value) << 0) & 0x00000001)
 

Field : WREN

Selects WR packets.

Field Access Macros:

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_LSB   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_MSB   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_WIDTH   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET_MSK   0x00000002
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK   0xfffffffd
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_RESET   0x0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET(value)   (((value) << 1) & 0x00000002)
 

Field : LOCKEN

Selects RDX-WR, RDL, WRC and Linked sequence.

Field Access Macros:

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_LSB   2
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_MSB   2
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK   0x00000004
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK   0xfffffffb
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_RESET   0x0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET(value)   (((value) << 2) & 0x00000004)
 

Field : URGEN

Selects URG packets (urgency).

Field Access Macros:

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_LSB   3
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_MSB   3
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_WIDTH   1
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK   0x00000008
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK   0xfffffff7
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_RESET   0x0
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET(value)   (((value) << 3) & 0x00000008)
 

Data Structures

struct  ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_s
 

Macros

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RESET   0x00000000
 
#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_OFST   0x9c
 

Typedefs

typedef struct
ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_s 
ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_t
 

Data Structure Documentation

struct ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE.

Data Fields
uint32_t RDEN: 1 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN
uint32_t WREN: 1 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN
uint32_t LOCKEN: 1 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN
uint32_t URGEN: 1 ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN
uint32_t __pad0__: 28 UNDEFINED

Macro Definitions

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_MSB   0

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_WIDTH   1

The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET_MSK   0x00000001

The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_CLR_MSK   0xfffffffe

The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_RESET   0x0

The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN field value from a register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RDEN register field value suitable for setting the register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_LSB   1

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_MSB   1

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_WIDTH   1

The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET_MSK   0x00000002

The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_CLR_MSK   0xfffffffd

The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_RESET   0x0

The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN field value from a register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_WREN register field value suitable for setting the register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_LSB   2

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_MSB   2

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_WIDTH   1

The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET_MSK   0x00000004

The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_CLR_MSK   0xfffffffb

The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_RESET   0x0

The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN field value from a register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_LOCKEN register field value suitable for setting the register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_LSB   3

The Least Significant Bit (LSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_MSB   3

The Most Significant Bit (MSB) position of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_WIDTH   1

The width in bits of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET_MSK   0x00000008

The mask used to set the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_CLR_MSK   0xfffffff7

The mask used to clear the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_RESET   0x0

The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN field value from a register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_URGEN register field value suitable for setting the register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_RESET   0x00000000

The reset value of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE register.

#define ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE_OFST   0x9c

The byte offset of the ALT_NOC_MPU_PRB_H2F_MAIN_FLTS_1_OPCODE register from the beginning of the component.

Typedef Documentation