Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : Reset Register - grstctl

Description

The application uses this register to reset various hardware features inside the core

Register Layout

Bits Access Reset Description
[0] R 0x0 Core Soft Reset
[1] ??? 0x0 UNDEFINED
[2] R 0x0 Host Frame Counter Reset
[3] ??? 0x0 UNDEFINED
[4] R 0x0 RxFIFO Flush
[5] R 0x0 TxFIFO Flush
[10:6] RW 0x0 TxFIFO Number
[29:11] ??? 0x0 UNDEFINED
[30] R 0x0 DMA Request Signal
[31] R 0x1 AHB Master Idle

Field : Core Soft Reset - csftrst

Mode:Host and Device. Resets the hclk and phy_clock domains as follows:Clears the interrupts and all the CSR registers except the following register bits:

  • PCGCCTL.RstPdwnModule
  • PCGCCTL.GateHclk
  • PCGCCTL.PwrClmp
  • PCGCCTL.StopPPhyLPwrClkSelclk
  • GUSBCFG.PhyLPwrClkSel
  • GUSBCFG.DDRSel
  • GUSBCFG.PHYSel
  • GUSBCFG.FSIntf
  • GUSBCFG.ULPI_UTMI_Sel
  • GUSBCFG.PHYIf
  • HCFG.FSLSPclkSel
  • DCFG.DevSpd
  • GGPIO
  • GPWRDN
  • GADPCTL

All module state machines (except the AHB Slave Unit) are reset to the IDLE state, and all the transmit FIFOs and the receive FIFO are flushed. Any transactions on the AHB Master are terminated as soonas possible, after gracefully completing the last data phase of an AHB transfer. Any transactions on the USB are terminated immediately. When Hibernation or ADP feature is enabled, the PMU module is not reset by the Core Soft Reset.The application can write to this bit any time it wants to reset the core. This is a self-clearing bit and the core clears this bit after all the necessary logic is reset in the core, which can take several clocks, depending on the current state of the core. Once this bit is cleared software must wait at least 3 PHY clocks before doing any access to the PHY domain (synchronization delay). Software must also must check that bit 31 of this register is 1 (AHB Master is IDLE) before starting any operation.Typically software reset is used during software development and also when you dynamically change the PHY selection bits in the USB configuration registers listed above. When you change the PHY, the corresponding clock for the PHY is selected and used in the PHY domain. Once a new clock is selected, the PHY domain has to be reset for proper operation.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT 0x0 No reset
ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT 0x1 Resets hclk and phy_clock domains

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB   0
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB   0
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK   0x00000001
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK   0xfffffffe
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET(value)   (((value) << 0) & 0x00000001)
 

Field : Host Frame Counter Reset - frmcntrrst

Mode:Host only. The application writes this bit to reset the (micro)frame number counter inside the core. When the (micro)frame counter is reset, the subsequent SOF sent out by the core has a (micro)frame number of 0. When application writes 1 to the bit, it might not be able to read back the value as it will get cleared by the core in a few clock cycles.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT 0x0 No reset
ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT 0x1 Host Frame Counter Reset

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB   2
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB   2
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK   0x00000004
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK   0xfffffffb
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET(value)   (((value) << 2) & 0x00000004)
 

Field : RxFIFO Flush - rxfflsh

Mode:Host and Device. The application can flush the entire RxFIFO using this bit, but must first ensure that the core is not in the middle of a transaction. The application must only write to this bit after checking that the core is neither reading from the RxFIFO nor writing to the RxFIFO. The application must wait until the bit is cleared before performing any other operations. This bit requires 8 clocks (slowest of PHY or AHB clock) to clear.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT 0x0 no flush the entire RxFIFO
ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT 0x1 flush the entire RxFIFO

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB   4
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB   4
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK   0x00000010
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK   0xffffffef
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET(value)   (((value) << 4) & 0x00000010)
 

Field : TxFIFO Flush - txfflsh

Mode:Host and Device. This bit selectively flushes a single or all transmit FIFOs, but cannot do so If the core is in the midst of a transaction. The application must write this bit only after checking that the core is neither writing to the TxFIFO nor reading from the TxFIFO. Verify using these registers: ReadNAK Effective Interrupt ensures the core is notreading from the FIFO WriteGRSTCTL.AHBIdle ensures the core is not writinganything to the FIFO. Flushing is normally recommended when FIFOs are reconfigured or when switching between Shared FIFO and Dedicated Transmit FIFO operation. FIFO flushing is also recommended during device endpoint disable. The application must wait until the core clears this bit before performing any operations. This bit takes eight clocks to clear, using the slower clock of phy_clk or hclk.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT 0x0 No Flush
ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT 0x1 selectively flushes a single or all transmit
: FIFOs

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB   5
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB   5
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK   0x00000020
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK   0xffffffdf
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET(value)   (((value) << 5) & 0x00000020)
 

Field : TxFIFO Number - txfnum

Mode:Host and Device. This is the FIFO number that must be flushed using the TxFIFO Flush bit. This field must not be changed until the core clears the TxFIFO Flush bit.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0 0x0 - Non-periodic TxFIFO flush in Host mode - Non-
: periodic TxFIFO flush in device mode when in
: shared FIFO operation
ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1 0x1 - Periodic TxFIFO flush in Host mode - Periodic
: TxFIFO 1 flush in Device mode when in sharedFIFO
: operation
ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2 0x2 - Periodic TxFIFO 2 flush in Device mode when in
: sharedFIFO operation- TXFIFO 2 flush in device
: mode when in dedicated FIFO mode
ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15 0xf - Periodic TxFIFO 15 flush in Device mode when
: in shared FIFO operation - TXFIFO 15 flush in
: device mode when in dedicated FIFO mode
ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16 0x10 Flush all the transmit FIFOs in device or host
: mode.

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0   0x0
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1   0x1
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2   0x2
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15   0xf
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16   0x10
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB   6
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB   10
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH   5
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK   0x000007c0
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK   0xfffff83f
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET(value)   (((value) & 0x000007c0) >> 6)
 
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET(value)   (((value) << 6) & 0x000007c0)
 

Field : DMA Request Signal - dmareq

Mode:Host and Device. Indicates that the DMA request is in progress. Used for debug.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT 0x0 No DMA request
ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT 0x1 DMA request is in progress

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB   30
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB   30
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK   0x40000000
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK   0xbfffffff
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET   0x0
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET(value)   (((value) << 30) & 0x40000000)
 

Field : AHB Master Idle - ahbidle

Mode:Host and Device. Indicates that the AHB Master State Machine is in the IDLE condition.

Field Enumeration Values:

Enum Value Description
ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT 0x0 Not Idle
ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT 0x1 AHB Master Idle

Field Access Macros:

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT   0x0
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT   0x1
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB   31
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB   31
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH   1
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK   0x80000000
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK   0x7fffffff
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET   0x1
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET(value)   (((value) & 0x80000000) >> 31)
 
#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET(value)   (((value) << 31) & 0x80000000)
 

Data Structures

struct  ALT_USB_GLOB_GRSTCTL_s
 

Macros

#define ALT_USB_GLOB_GRSTCTL_OFST   0x10
 
#define ALT_USB_GLOB_GRSTCTL_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST))
 

Typedefs

typedef struct
ALT_USB_GLOB_GRSTCTL_s 
ALT_USB_GLOB_GRSTCTL_t
 

Data Structure Documentation

struct ALT_USB_GLOB_GRSTCTL_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_USB_GLOB_GRSTCTL.

Data Fields
const uint32_t csftrst: 1 Core Soft Reset
uint32_t __pad0__: 1 UNDEFINED
const uint32_t frmcntrrst: 1 Host Frame Counter Reset
uint32_t __pad1__: 1 UNDEFINED
const uint32_t rxfflsh: 1 RxFIFO Flush
const uint32_t txfflsh: 1 TxFIFO Flush
uint32_t txfnum: 5 TxFIFO Number
uint32_t __pad2__: 19 UNDEFINED
const uint32_t dmareq: 1 DMA Request Signal
const uint32_t ahbidle: 1 AHB Master Idle

Macro Definitions

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_NOTACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST

No reset

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_CSFTRST

Resets hclk and phy_clock domains

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_LSB   0

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_MSB   0

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET_MSK   0x00000001

The mask used to set the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_CLR_MSK   0xfffffffe

The mask used to clear the ALT_USB_GLOB_GRSTCTL_CSFTRST register field value.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_CSFTRST register field.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_USB_GLOB_GRSTCTL_CSFTRST field value from a register.

#define ALT_USB_GLOB_GRSTCTL_CSFTRST_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_USB_GLOB_GRSTCTL_CSFTRST register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_NOTACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST

No reset

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_FRMCNTRRST

Host Frame Counter Reset

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_LSB   2

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_MSB   2

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET_MSK   0x00000004

The mask used to set the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_CLR_MSK   0xfffffffb

The mask used to clear the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_USB_GLOB_GRSTCTL_FRMCNTRRST field value from a register.

#define ALT_USB_GLOB_GRSTCTL_FRMCNTRRST_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_USB_GLOB_GRSTCTL_FRMCNTRRST register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_INACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH

no flush the entire RxFIFO

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_RXFFLSH

flush the entire RxFIFO

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_LSB   4

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_MSB   4

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET_MSK   0x00000010

The mask used to set the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_CLR_MSK   0xffffffef

The mask used to clear the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_RXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_USB_GLOB_GRSTCTL_RXFFLSH field value from a register.

#define ALT_USB_GLOB_GRSTCTL_RXFFLSH_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_USB_GLOB_GRSTCTL_RXFFLSH register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_INACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH

No Flush

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFFLSH

selectively flushes a single or all transmit FIFOs

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_LSB   5

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_MSB   5

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET_MSK   0x00000020

The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_CLR_MSK   0xffffffdf

The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_TXFFLSH register field.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_USB_GLOB_GRSTCTL_TXFFLSH field value from a register.

#define ALT_USB_GLOB_GRSTCTL_TXFFLSH_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_USB_GLOB_GRSTCTL_TXFFLSH register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF0   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM

  • Non-periodic TxFIFO flush in Host mode
  • Non-periodic TxFIFO flush in device mode when in shared FIFO operation
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF1   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM

  • Periodic TxFIFO flush in Host mode
  • Periodic TxFIFO 1 flush in Device mode when in sharedFIFO operation
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF2   0x2

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM

  • Periodic TxFIFO 2 flush in Device mode when in sharedFIFO operation- TXFIFO 2 flush in device mode when in dedicated FIFO mode
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF15   0xf

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM

  • Periodic TxFIFO 15 flush in Device mode when in shared FIFO operation
  • TXFIFO 15 flush in device mode when in dedicated FIFO mode
#define ALT_USB_GLOB_GRSTCTL_TXFNUM_E_TXF16   0x10

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_TXFNUM

Flush all the transmit FIFOs in device or host mode.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_LSB   6

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_MSB   10

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_WIDTH   5

The width in bits of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET_MSK   0x000007c0

The mask used to set the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_CLR_MSK   0xfffff83f

The mask used to clear the ALT_USB_GLOB_GRSTCTL_TXFNUM register field value.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_TXFNUM register field.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_GET (   value)    (((value) & 0x000007c0) >> 6)

Extracts the ALT_USB_GLOB_GRSTCTL_TXFNUM field value from a register.

#define ALT_USB_GLOB_GRSTCTL_TXFNUM_SET (   value)    (((value) << 6) & 0x000007c0)

Produces a ALT_USB_GLOB_GRSTCTL_TXFNUM register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_INACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ

No DMA request

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_DMAREQ

DMA request is in progress

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_LSB   30

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_MSB   30

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET_MSK   0x40000000

The mask used to set the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_CLR_MSK   0xbfffffff

The mask used to clear the ALT_USB_GLOB_GRSTCTL_DMAREQ register field value.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_RESET   0x0

The reset value of the ALT_USB_GLOB_GRSTCTL_DMAREQ register field.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_USB_GLOB_GRSTCTL_DMAREQ field value from a register.

#define ALT_USB_GLOB_GRSTCTL_DMAREQ_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_USB_GLOB_GRSTCTL_DMAREQ register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_INACT   0x0

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE

Not Idle

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_E_ACT   0x1

Enumerated value for register field ALT_USB_GLOB_GRSTCTL_AHBIDLE

AHB Master Idle

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_LSB   31

The Least Significant Bit (LSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_MSB   31

The Most Significant Bit (MSB) position of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_WIDTH   1

The width in bits of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET_MSK   0x80000000

The mask used to set the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_CLR_MSK   0x7fffffff

The mask used to clear the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_RESET   0x1

The reset value of the ALT_USB_GLOB_GRSTCTL_AHBIDLE register field.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_GET (   value)    (((value) & 0x80000000) >> 31)

Extracts the ALT_USB_GLOB_GRSTCTL_AHBIDLE field value from a register.

#define ALT_USB_GLOB_GRSTCTL_AHBIDLE_SET (   value)    (((value) << 31) & 0x80000000)

Produces a ALT_USB_GLOB_GRSTCTL_AHBIDLE register field value suitable for setting the register.

#define ALT_USB_GLOB_GRSTCTL_OFST   0x10

The byte offset of the ALT_USB_GLOB_GRSTCTL register from the beginning of the component.

#define ALT_USB_GLOB_GRSTCTL_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_USB_GLOB_GRSTCTL_OFST))

The address of the ALT_USB_GLOB_GRSTCTL register.

Typedef Documentation

The typedef declaration for register ALT_USB_GLOB_GRSTCTL.