Altera HWLIB  16.0
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alt_mmu.h
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32 
33 /*
34  * $Id: //depot/embedded/rel/15.0/ip/hps/altera_hps/hwlib/include/alt_mmu.h#1 $
35  */
36 
41 #ifndef __ALT_MMU_H__
42 #define __ALT_MMU_H__
43 
44 #include "hwlib.h"
45 
46 #ifdef __cplusplus
47 extern "C"
48 {
49 #endif /* __cplusplus */
50 
51 /******************************************************************************/
101 typedef enum ALT_MMU_TTB_S_e
102 {
106 
107 
115 typedef enum ALT_MMU_TTB_NS_e
116 {
120 
126 typedef enum ALT_MMU_TTB_XN_e
127 {
142 
147 typedef enum ALT_MMU_DAP_e
148 {
161 } ALT_MMU_DAP_t;
162 
189 {
196 };
199 
248 {
278 };
281 
282 
283 /******************************************************************************/
308 #define ALT_MMU_SUPERSECTION_SIZE (1UL << 24)
309 
313 #define ALT_MMU_SECTION_SIZE (1UL << 20)
314 
318 #define ALT_MMU_LARGE_PAGE_SIZE (1UL << 16)
319 
323 #define ALT_MMU_SMALL_PAGE_SIZE (1UL << 12)
324 
329 #define ALT_MMU_TTB1_SIZE 16384
330 
335 #define ALT_MMU_TTB2_SIZE 1024
336 
337 /******************************************************************************/
367 #define ALT_MMU_TTB1_TYPE_MASK 0x00000003
368 #define ALT_MMU_TTB1_TYPE_GET(desc) (((desc) & ALT_MMU_TTB1_TYPE_MASK) >> 0)
369 #define ALT_MMU_TTB1_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB1_TYPE_MASK)
370 
378 #define ALT_MMU_TTB1_PAGE_TBL_NS_MASK 0x00000008
379 #define ALT_MMU_TTB1_PAGE_TBL_NS_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK) >> 3)
380 #define ALT_MMU_TTB1_PAGE_TBL_NS_SET(val) (((val) << 3) & ALT_MMU_TTB1_PAGE_TBL_NS_MASK)
381 
390 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK 0x000001e0
391 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK) >> 5)
392 #define ALT_MMU_TTB1_PAGE_TBL_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_PAGE_TBL_DOMAIN_MASK)
393 
399 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK 0xfffffc00
400 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK) >> 10)
401 #define ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_SET(val) (((val) << 10) & ALT_MMU_TTB1_PAGE_TBL_BASE_ADDR_MASK)
402 
411 #define ALT_MMU_TTB1_SECTION_B_MASK 0x00000004
412 #define ALT_MMU_TTB1_SECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_B_MASK) >> 2)
413 #define ALT_MMU_TTB1_SECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SECTION_B_MASK)
414 
423 #define ALT_MMU_TTB1_SECTION_C_MASK 0x00000008
424 #define ALT_MMU_TTB1_SECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_C_MASK) >> 3)
425 #define ALT_MMU_TTB1_SECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SECTION_C_MASK)
426 
435 #define ALT_MMU_TTB1_SECTION_XN_MASK 0x00000010
436 #define ALT_MMU_TTB1_SECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_XN_MASK) >> 4)
437 #define ALT_MMU_TTB1_SECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SECTION_XN_MASK)
438 
446 #define ALT_MMU_TTB1_SECTION_DOMAIN_MASK 0x000001e0
447 #define ALT_MMU_TTB1_SECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK) >> 5)
448 #define ALT_MMU_TTB1_SECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SECTION_DOMAIN_MASK)
449 
457 #define ALT_MMU_TTB1_SECTION_AP_MASK 0x00008c00
458 #define ALT_MMU_TTB1_SECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
459 #define ALT_MMU_TTB1_SECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
460 
469 #define ALT_MMU_TTB1_SECTION_TEX_MASK 0x00007000
470 #define ALT_MMU_TTB1_SECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_TEX_MASK) >> 12)
471 #define ALT_MMU_TTB1_SECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SECTION_TEX_MASK)
472 
480 #define ALT_MMU_TTB1_SECTION_S_MASK 0x00010000
481 #define ALT_MMU_TTB1_SECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_S_MASK) >> 16)
482 #define ALT_MMU_TTB1_SECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SECTION_S_MASK)
483 
491 #define ALT_MMU_TTB1_SECTION_NG_MASK 0x00020000
492 #define ALT_MMU_TTB1_SECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NG_MASK) >> 17)
493 #define ALT_MMU_TTB1_SECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SECTION_NG_MASK)
494 
503 #define ALT_MMU_TTB1_SECTION_NS_MASK 0x00080000
504 #define ALT_MMU_TTB1_SECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_NS_MASK) >> 19)
505 #define ALT_MMU_TTB1_SECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SECTION_NS_MASK)
506 
512 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK 0xfff00000
513 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK) >> 20)
514 #define ALT_MMU_TTB1_SECTION_BASE_ADDR_SET(val) (((val) << 20) & ALT_MMU_TTB1_SECTION_BASE_ADDR_MASK)
515 
524 #define ALT_MMU_TTB1_SUPERSECTION_B_MASK 0x00000004
525 #define ALT_MMU_TTB1_SUPERSECTION_B_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_B_MASK) >> 2)
526 #define ALT_MMU_TTB1_SUPERSECTION_B_SET(val) (((val) << 2) & ALT_MMU_TTB1_SUPERSECTION_B_MASK)
527 
536 #define ALT_MMU_TTB1_SUPERSECTION_C_MASK 0x00000008
537 #define ALT_MMU_TTB1_SUPERSECTION_C_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_C_MASK) >> 3)
538 #define ALT_MMU_TTB1_SUPERSECTION_C_SET(val) (((val) << 3) & ALT_MMU_TTB1_SUPERSECTION_C_MASK)
539 
548 #define ALT_MMU_TTB1_SUPERSECTION_XN_MASK 0x00000010
549 #define ALT_MMU_TTB1_SUPERSECTION_XN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK) >> 4)
550 #define ALT_MMU_TTB1_SUPERSECTION_XN_SET(val) (((val) << 4) & ALT_MMU_TTB1_SUPERSECTION_XN_MASK)
551 
559 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK 0x000001e0
560 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK) >> 5)
561 #define ALT_MMU_TTB1_SUPERSECTION_DOMAIN_SET(val) (((val) << 5) & ALT_MMU_TTB1_SUPERSECTION_DOMAIN_MASK)
562 
570 #define ALT_MMU_TTB1_SUPERSECTION_AP_MASK 0x00008c00
571 #define ALT_MMU_TTB1_SUPERSECTION_AP_GET(desc) ((((desc) & 0x00008000) >> 13) | (((desc) & 0x00000c00) >> 10))
572 #define ALT_MMU_TTB1_SUPERSECTION_AP_SET(val) ((((val) << 13) & 0x00008000) | (((val) << 10) & 0x00000c00))
573 
582 #define ALT_MMU_TTB1_SUPERSECTION_TEX_MASK 0x00007000
583 #define ALT_MMU_TTB1_SUPERSECTION_TEX_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK) >> 12)
584 #define ALT_MMU_TTB1_SUPERSECTION_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB1_SUPERSECTION_TEX_MASK)
585 
593 #define ALT_MMU_TTB1_SUPERSECTION_S_MASK 0x00010000
594 #define ALT_MMU_TTB1_SUPERSECTION_S_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_S_MASK) >> 16)
595 #define ALT_MMU_TTB1_SUPERSECTION_S_SET(val) (((val) << 16) & ALT_MMU_TTB1_SUPERSECTION_S_MASK)
596 
604 #define ALT_MMU_TTB1_SUPERSECTION_NG_MASK 0x00020000
605 #define ALT_MMU_TTB1_SUPERSECTION_NG_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK) >> 17)
606 #define ALT_MMU_TTB1_SUPERSECTION_NG_SET(val) (((val) << 17) & ALT_MMU_TTB1_SUPERSECTION_NG_MASK)
607 
616 #define ALT_MMU_TTB1_SUPERSECTION_NS_MASK 0x00080000
617 #define ALT_MMU_TTB1_SUPERSECTION_NS_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK) >> 19)
618 #define ALT_MMU_TTB1_SUPERSECTION_NS_SET(val) (((val) << 19) & ALT_MMU_TTB1_SUPERSECTION_NS_MASK)
619 
624 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK 0xff000000
625 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK) >> 24)
626 #define ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_SET(val) (((val) << 24) & ALT_MMU_TTB1_SUPERSECTION_BASE_ADDR_MASK)
627 
631 /******************************************************************************/
659 #define ALT_MMU_TTB2_TYPE_MASK 0x00000003
660 #define ALT_MMU_TTB2_TYPE_GET(desc) (((desc) & ALT_MMU_TTB2_TYPE_MASK) >> 0)
661 #define ALT_MMU_TTB2_TYPE_SET(val) (((val) << 0) & ALT_MMU_TTB2_TYPE_MASK)
662 
670 #define ALT_MMU_TTB2_LARGE_PAGE_B_MASK 0x00000004
671 #define ALT_MMU_TTB2_LARGE_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK) >> 2)
672 #define ALT_MMU_TTB2_LARGE_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_LARGE_PAGE_B_MASK)
673 
682 #define ALT_MMU_TTB2_LARGE_PAGE_C_MASK 0x00000008
683 #define ALT_MMU_TTB2_LARGE_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK) >> 3)
684 #define ALT_MMU_TTB2_LARGE_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_LARGE_PAGE_C_MASK)
685 
693 #define ALT_MMU_TTB2_LARGE_PAGE_AP_MASK 0x00000230
694 #define ALT_MMU_TTB2_LARGE_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
695 #define ALT_MMU_TTB2_LARGE_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
696 
704 #define ALT_MMU_TTB2_LARGE_PAGE_S_MASK 0x00000400
705 #define ALT_MMU_TTB2_LARGE_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK) >> 10)
706 #define ALT_MMU_TTB2_LARGE_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_LARGE_PAGE_S_MASK)
707 
715 #define ALT_MMU_TTB2_LARGE_PAGE_NG_MASK 0x00000800
716 #define ALT_MMU_TTB2_LARGE_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK) >> 11)
717 #define ALT_MMU_TTB2_LARGE_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_LARGE_PAGE_NG_MASK)
718 
727 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK 0x00007000
728 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK) >> 12)
729 #define ALT_MMU_TTB2_LARGE_PAGE_TEX_SET(val) (((val) << 12) & ALT_MMU_TTB2_LARGE_PAGE_TEX_MASK)
730 
739 #define ALT_MMU_TTB2_LARGE_PAGE_XN_MASK 0x00008000
740 #define ALT_MMU_TTB2_LARGE_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK) >> 15)
741 #define ALT_MMU_TTB2_LARGE_PAGE_XN_SET(val) (((val) << 15) & ALT_MMU_TTB2_LARGE_PAGE_XN_MASK)
742 
748 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK 0xffff0000
749 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK) >> 16)
750 #define ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_SET(val) (((val) << 16) & ALT_MMU_TTB2_LARGE_PAGE_BASE_ADDR_MASK)
751 
760 #define ALT_MMU_TTB2_SMALL_PAGE_XN_MASK 0x00000001
761 #define ALT_MMU_TTB2_SMALL_PAGE_XN_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK) >> 0)
762 #define ALT_MMU_TTB2_SMALL_PAGE_XN_SET(val) (((val) << 0) & ALT_MMU_TTB2_SMALL_PAGE_XN_MASK)
763 
772 #define ALT_MMU_TTB2_SMALL_PAGE_B_MASK 0x00000004
773 #define ALT_MMU_TTB2_SMALL_PAGE_B_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK) >> 2)
774 #define ALT_MMU_TTB2_SMALL_PAGE_B_SET(val) (((val) << 2) & ALT_MMU_TTB2_SMALL_PAGE_B_MASK)
775 
784 #define ALT_MMU_TTB2_SMALL_PAGE_C_MASK 0x00000008
785 #define ALT_MMU_TTB2_SMALL_PAGE_C_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK) >> 3)
786 #define ALT_MMU_TTB2_SMALL_PAGE_C_SET(val) (((val) << 3) & ALT_MMU_TTB2_SMALL_PAGE_C_MASK)
787 
795 #define ALT_MMU_TTB2_SMALL_PAGE_AP_MASK 0x00000230
796 #define ALT_MMU_TTB2_SMALL_PAGE_AP_GET(desc) ((((desc) & 0x00000200) >> 7) | (((desc) & 0x00000030) >> 4))
797 #define ALT_MMU_TTB2_SMALL_PAGE_AP_SET(val) ((((val) << 7) & 0x00000200) | (((val) << 4) & 0x00000030))
798 
807 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK 0x000001c0
808 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK) >> 6)
809 #define ALT_MMU_TTB2_SMALL_PAGE_TEX_SET(val) (((val) << 6) & ALT_MMU_TTB2_SMALL_PAGE_TEX_MASK)
810 
818 #define ALT_MMU_TTB2_SMALL_PAGE_S_MASK 0x00000400
819 #define ALT_MMU_TTB2_SMALL_PAGE_S_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK) >> 10)
820 #define ALT_MMU_TTB2_SMALL_PAGE_S_SET(val) (((val) << 10) & ALT_MMU_TTB2_SMALL_PAGE_S_MASK)
821 
829 #define ALT_MMU_TTB2_SMALL_PAGE_NG_MASK 0x00000800
830 #define ALT_MMU_TTB2_SMALL_PAGE_NG_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK) >> 11)
831 #define ALT_MMU_TTB2_SMALL_PAGE_NG_SET(val) (((val) << 11) & ALT_MMU_TTB2_SMALL_PAGE_NG_MASK)
832 
838 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK 0xfffff000
839 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_GET(desc) (((desc) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK) >> 12)
840 #define ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_SET(val) (((val) << 12) & ALT_MMU_TTB2_SMALL_PAGE_BASE_ADDR_MASK)
841 
846 /******************************************************************************/
862 typedef struct ALT_MMU_TTB1_FAULT_s
863 {
864  uint32_t type : 2;
865  uint32_t : 30;
867 
873 {
875  uint32_t raw;
877 
883 {
884  uint32_t type : 2;
885  uint32_t : 1;
886  uint32_t ns : 1;
890  uint32_t : 1;
891  uint32_t domain : 4;
895  uint32_t : 1;
896  uint32_t base_addr : 22;
898 
904 {
906  uint32_t raw;
908 
913 {
914  uint32_t type : 2;
915  uint32_t b : 1;
919  uint32_t c : 1;
924  uint32_t xn : 1;
928  uint32_t domain : 4;
929  uint32_t : 1;
930  uint32_t ap_1_0 : 2;
931  uint32_t tex : 3;
935  uint32_t ap_2 : 1;
936  uint32_t s : 1;
939  uint32_t ng : 1;
942  uint32_t : 1;
943  uint32_t ns : 1;
947  uint32_t base_addr : 12;
949 
955 {
957  uint32_t raw;
959 
965 {
966  uint32_t type : 2;
967  uint32_t b : 1;
971  uint32_t c : 1;
976  uint32_t xn : 1;
980  uint32_t domain : 4;
981  uint32_t : 1;
982  uint32_t ap_1_0 : 2;
983  uint32_t tex : 3;
987  uint32_t ap_2 : 1;
988  uint32_t s : 1;
991  uint32_t ng : 1;
994  uint32_t : 1;
995  uint32_t ns : 1;
999  uint32_t : 4;
1000  uint32_t base_addr : 8;
1002 
1008 {
1010  uint32_t raw;
1012 
1015 /******************************************************************************/
1031 typedef struct ALT_MMU_TTB2_FAULT_s
1032 {
1033  uint32_t type : 2; // b00
1034  uint32_t : 30; // IGNORE
1036 
1042 {
1044  uint32_t raw;
1046 
1052 {
1053  uint32_t : 2;
1054  uint32_t b : 1;
1058  uint32_t c : 1;
1062  uint32_t ap_1_0 : 2;
1063  uint32_t : 3; // SBZ - b000
1064  uint32_t ap_2 : 1;
1065  uint32_t s : 1;
1068  uint32_t ng : 1;
1071  uint32_t tex : 3;
1075  uint32_t xn : 1;
1079  uint32_t base_addr : 16;
1081 
1087 {
1089  uint32_t raw;
1091 
1097 {
1098  uint32_t xn : 1;
1102  uint32_t : 1;
1103  uint32_t b : 1;
1107  uint32_t c : 1;
1111  uint32_t ap_1_0 : 2;
1112  uint32_t tex : 3;
1116  uint32_t ap_2 : 1;
1117  uint32_t s : 1;
1120  uint32_t ng : 1;
1123  uint32_t base_addr : 20;
1125 
1131 {
1133  uint32_t raw;
1135 
1138 /******************************************************************************/
1145 ALT_STATUS_CODE alt_mmu_init(void);
1146 
1147 /******************************************************************************/
1154 ALT_STATUS_CODE alt_mmu_uninit(void);
1155 
1156 /******************************************************************************/
1177 ALT_STATUS_CODE alt_mmu_ttb1_init(uint32_t* ttb1);
1178 
1179 /******************************************************************************/
1214 ALT_STATUS_CODE alt_mmu_ttb1_desc_set(uint32_t* ttb1,
1215  const void* va,
1216  const uint32_t desc);
1217 
1218 /******************************************************************************/
1254 ALT_STATUS_CODE alt_mmu_ttb2_desc_set(const uint32_t* ttb1,
1255  const void* va,
1256  const uint32_t desc);
1257 
1258 /******************************************************************************/
1265 ALT_STATUS_CODE alt_mmu_disable(void);
1266 
1267 /******************************************************************************/
1286 ALT_STATUS_CODE alt_mmu_enable(void);
1287 
1288 /******************************************************************************/
1294 void *alt_mmu_TTBR0_get(void);
1295 
1296 /******************************************************************************/
1313 ALT_STATUS_CODE alt_mmu_TTBR0_set(const void* addr);
1314 
1315 /******************************************************************************/
1321 void *alt_mmu_TTBR1_get(void);
1322 
1323 /******************************************************************************/
1338 ALT_STATUS_CODE alt_mmu_TTBR1_set(const void* addr);
1339 
1340 /******************************************************************************/
1374 ALT_STATUS_CODE alt_mmu_TTBCR_set(const bool enable_ttbr0_walk,
1375  const bool enable_ttbr1_walk,
1376  const uint32_t base_addr_width);
1377 
1378 /******************************************************************************/
1394 ALT_STATUS_CODE alt_mmu_DACR_set(const ALT_MMU_DAP_t domain_ap[],
1395  const size_t num_elem);
1396 
1397 /******************************************************************************/
1416 ALT_STATUS_CODE alt_mmu_CONTEXTIDR_set(const uint32_t procid, const uint32_t asid);
1417 
1418 /******************************************************************************/
1425 ALT_STATUS_CODE alt_mmu_tlb_invalidate(void);
1426 
1427 /******************************************************************************/
1437 ALT_STATUS_CODE alt_mmu_tlb_invalidate_is(void);
1438 
1441 /******************************************************************************/
1479 /******************************************************************************/
1487 typedef struct ALT_MMU_MEM_REGION_s
1488 {
1489  void * va;
1493  void * pa;
1498  uint32_t size;
1502  ALT_MMU_AP_t access;
1503  ALT_MMU_ATTR_t attributes;
1517 
1547 typedef void* (*alt_mmu_ttb_alloc_t)(const size_t size, void * context);
1548 
1549 /******************************************************************************/
1572  const size_t num_mem_regions);
1573 
1574 /******************************************************************************/
1611 ALT_STATUS_CODE alt_mmu_va_space_create(uint32_t ** ttb1,
1612  const ALT_MMU_MEM_REGION_t* mem_regions,
1613  const size_t num_mem_regions,
1614  alt_mmu_ttb_alloc_t ttb_alloc,
1615  void * ttb_alloc_context);
1616 
1617 /******************************************************************************/
1641 ALT_STATUS_CODE alt_mmu_va_space_enable(const uint32_t * ttb1);
1642 
1687 uintptr_t alt_mmu_va_to_pa(const void * va, uint32_t * seglength, uint32_t * dfsr);
1688 
1693 #ifdef __cplusplus
1694 }
1695 #endif /* __cplusplus */
1696 #endif /* __ALT_MMU_H__ */