Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dramodt0

Description

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP
[31:16] RW 0x0 ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP

Field : cfg_write_odt_chip

ODT scheme setting for write command. Setting seperated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_LSB   0
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_MSB   15
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_WIDTH   16
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_CLR_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : cfg_read_odt_chip

ODT scheme setting for read command. Setting seperated into 4 sections: [CS3][CS2][CS1][CS0] Each section consists of 4 bits to indicate which chip should ODT be asserted when write occurs on current CS. Eg: if we set to 16

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_LSB   16
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_MSB   31
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_WIDTH   16
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET_MSK   0xffff0000
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_CLR_MSK   0x0000ffff
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DRAMODT0_s
 

Macros

#define ALT_IO48_HMC_MMR_DRAMODT0_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DRAMODT0_OFST   0x54
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DRAMODT0_s 
ALT_IO48_HMC_MMR_DRAMODT0_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DRAMODT0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DRAMODT0.

Data Fields
uint32_t cfg_write_odt_chip: 16 ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP
uint32_t cfg_read_odt_chip: 16 ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP

Macro Definitions

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_MSB   15

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET_MSK   0x0000ffff

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_CLR_MSK   0xffff0000

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_IO48_HMC_MMR_DRAMODT0_CFG_WR_ODT_CHIP register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_LSB   16

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_MSB   31

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_WIDTH   16

The width in bits of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET_MSK   0xffff0000

The mask used to set the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_CLR_MSK   0x0000ffff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP field value from a register.

#define ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_IO48_HMC_MMR_DRAMODT0_CFG_RD_ODT_CHIP register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMODT0_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DRAMODT0 register.

#define ALT_IO48_HMC_MMR_DRAMODT0_OFST   0x54

The byte offset of the ALT_IO48_HMC_MMR_DRAMODT0 register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_IO48_HMC_MMR_DRAMODT0.