Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
 All Data Structures Variables Typedefs Groups
Register : l4_priv

Description

This register controls access to various Peripherals depending on the privilege setting. By default, all slaves will be assumed as Privileged. To allow non- Privileged access to a slave, the corresponding bit for the slave must be set. Once set, both Privilege and non-Privileged transactions are allowed to the Slave. Note that the privilege filter only checks for transaction Privilege level, transaction Security is left to Firewalls. Firewalls therefore may still block transaction to Peripherals depending on Security configurations.

Register Layout

Bits Access Reset Description
[0] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG
[1] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA
[2] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA
[3] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG
[4] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG
[5] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE
[6] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE
[7] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0
[8] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1
[9] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0
[10] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1
[11] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0
[12] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1
[13] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2
[14] RW Unknown ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3
[15] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI
[16] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC
[17] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0
[18] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1
[19] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2
[20] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0
[21] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1
[22] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2
[23] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3
[24] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4
[25] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0
[26] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1
[27] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0
[28] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1
[29] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F
[30] RW 0x0 ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F
[31] ??? Unknown UNDEFINED

Field : nand_register

Privilege bit for nand register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_LSB   0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_MSB   0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET_MSK   0x00000001
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_CLR_MSK   0xfffffffe
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET(value)   (((value) << 0) & 0x00000001)
 

Field : nand_data

Privilege bit for nand_data. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_LSB   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_MSB   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET_MSK   0x00000002
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_CLR_MSK   0xfffffffd
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET(value)   (((value) << 1) & 0x00000002)
 

Field : qspi_data

Privilege bit for qspi_data. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_LSB   2
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_MSB   2
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET_MSK   0x00000004
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_CLR_MSK   0xfffffffb
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET(value)   (((value) << 2) & 0x00000004)
 

Field : usb0_register

Privilege bit for usb0_register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_LSB   3
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_MSB   3
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET_MSK   0x00000008
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_CLR_MSK   0xfffffff7
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_GET(value)   (((value) & 0x00000008) >> 3)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET(value)   (((value) << 3) & 0x00000008)
 

Field : usb1_register

Privilege bit for usb1_register. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_LSB   4
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_MSB   4
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET_MSK   0x00000010
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_CLR_MSK   0xffffffef
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET(value)   (((value) << 4) & 0x00000010)
 

Field : dma_nonsecure

Privilege bit for dma_nonsecure. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_LSB   5
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_MSB   5
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET_MSK   0x00000020
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_CLR_MSK   0xffffffdf
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET(value)   (((value) << 5) & 0x00000020)
 

Field : dma_secure

Privilege bit for dma_secure. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_LSB   6
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_MSB   6
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET_MSK   0x00000040
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_CLR_MSK   0xffffffbf
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET(value)   (((value) << 6) & 0x00000040)
 

Field : spi_master0

Privilege bit for spi_master0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_LSB   7
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_MSB   7
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET_MSK   0x00000080
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_CLR_MSK   0xffffff7f
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET(value)   (((value) << 7) & 0x00000080)
 

Field : spi_master1

Privilege bit for spi_master1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_LSB   8
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_MSB   8
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET_MSK   0x00000100
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_CLR_MSK   0xfffffeff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET(value)   (((value) << 8) & 0x00000100)
 

Field : spi_slave0

Privilege bit for spi_slave0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_LSB   9
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_MSB   9
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET_MSK   0x00000200
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_CLR_MSK   0xfffffdff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_GET(value)   (((value) & 0x00000200) >> 9)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET(value)   (((value) << 9) & 0x00000200)
 

Field : spi_slave1

Privilege bit for spi_slave1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_LSB   10
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_MSB   10
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET_MSK   0x00000400
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_CLR_MSK   0xfffffbff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_GET(value)   (((value) & 0x00000400) >> 10)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET(value)   (((value) << 10) & 0x00000400)
 

Field : emac0

Privilege bit for emac0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_LSB   11
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_MSB   11
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET_MSK   0x00000800
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_CLR_MSK   0xfffff7ff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_GET(value)   (((value) & 0x00000800) >> 11)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET(value)   (((value) << 11) & 0x00000800)
 

Field : emac1

Privilege bit for emac1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_LSB   12
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_MSB   12
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET_MSK   0x00001000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_CLR_MSK   0xffffefff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_GET(value)   (((value) & 0x00001000) >> 12)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET(value)   (((value) << 12) & 0x00001000)
 

Field : emac2

Privilege bit for emac2. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_LSB   13
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_MSB   13
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET_MSK   0x00002000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_CLR_MSK   0xffffdfff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET(value)   (((value) << 13) & 0x00002000)
 

Field : emac3

Privilege bit for emac3. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_LSB   14
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_MSB   14
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET_MSK   0x00004000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_CLR_MSK   0xffffbfff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_GET(value)   (((value) & 0x00004000) >> 14)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET(value)   (((value) << 14) & 0x00004000)
 

Field : qspi

Privilege bit for qspi. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_LSB   15
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_MSB   15
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET_MSK   0x00008000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_CLR_MSK   0xffff7fff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_GET(value)   (((value) & 0x00008000) >> 15)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET(value)   (((value) << 15) & 0x00008000)
 

Field : sdmmc

Privilege bit for sdmmc. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_LSB   16
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_MSB   16
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET_MSK   0x00010000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_CLR_MSK   0xfffeffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_GET(value)   (((value) & 0x00010000) >> 16)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET(value)   (((value) << 16) & 0x00010000)
 

Field : gpio0

Privilege bit for gpio0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_LSB   17
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_MSB   17
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET_MSK   0x00020000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_CLR_MSK   0xfffdffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_GET(value)   (((value) & 0x00020000) >> 17)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET(value)   (((value) << 17) & 0x00020000)
 

Field : gpio1

Privilege bit for gpio1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_LSB   18
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_MSB   18
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET_MSK   0x00040000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_CLR_MSK   0xfffbffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_GET(value)   (((value) & 0x00040000) >> 18)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET(value)   (((value) << 18) & 0x00040000)
 

Field : gpio2

Privilege bit for gpio2. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_LSB   19
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_MSB   19
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET_MSK   0x00080000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_CLR_MSK   0xfff7ffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_GET(value)   (((value) & 0x00080000) >> 19)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET(value)   (((value) << 19) & 0x00080000)
 

Field : i2c0

Privilege bit for i2c0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_LSB   20
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_MSB   20
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET_MSK   0x00100000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_CLR_MSK   0xffefffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET(value)   (((value) << 20) & 0x00100000)
 

Field : i2c1

Privilege bit for i2c1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_LSB   21
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_MSB   21
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET_MSK   0x00200000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_CLR_MSK   0xffdfffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET(value)   (((value) << 21) & 0x00200000)
 

Field : i2c2

Privilege bit for i2c2. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_LSB   22
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_MSB   22
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET_MSK   0x00400000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_CLR_MSK   0xffbfffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET(value)   (((value) << 22) & 0x00400000)
 

Field : i2c3

Privilege bit for i2c3. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_LSB   23
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_MSB   23
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET_MSK   0x00800000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_CLR_MSK   0xff7fffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET(value)   (((value) << 23) & 0x00800000)
 

Field : i2c4

Privilege bit for i2c4. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_LSB   24
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_MSB   24
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET_MSK   0x01000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_CLR_MSK   0xfeffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET(value)   (((value) << 24) & 0x01000000)
 

Field : sp_timer0

Privilege bit for sp_timer0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_LSB   25
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_MSB   25
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET_MSK   0x02000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_CLR_MSK   0xfdffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET(value)   (((value) << 25) & 0x02000000)
 

Field : sp_timer1

Privilege bit for sp_timer1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_LSB   26
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_MSB   26
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET_MSK   0x04000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_CLR_MSK   0xfbffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET(value)   (((value) << 26) & 0x04000000)
 

Field : uart0

Privilege bit for uart0. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_LSB   27
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_MSB   27
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET_MSK   0x08000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_CLR_MSK   0xf7ffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_GET(value)   (((value) & 0x08000000) >> 27)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET(value)   (((value) << 27) & 0x08000000)
 

Field : uart1

Privilege bit for uart1. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_LSB   28
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_MSB   28
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET_MSK   0x10000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_CLR_MSK   0xefffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_GET(value)   (((value) & 0x10000000) >> 28)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET(value)   (((value) << 28) & 0x10000000)
 

Field : lwsoc2fpga

Privilege bit for Lightweight SOC2FPGA. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_LSB   29
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_MSB   29
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET_MSK   0x20000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_CLR_MSK   0xdfffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_GET(value)   (((value) & 0x20000000) >> 29)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET(value)   (((value) << 29) & 0x20000000)
 

Field : soc2fpga

Privilege bit for SOC2FPGA. When 0, only privileged transactions are allowed to slave. When 1, both privileged and non-privileged transactions are allowed to slave

Field Access Macros:

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_LSB   30
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_MSB   30
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_WIDTH   1
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET_MSK   0x40000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_CLR_MSK   0xbfffffff
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_RESET   0x0
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_GET(value)   (((value) & 0x40000000) >> 30)
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET(value)   (((value) << 30) & 0x40000000)
 

Data Structures

struct  ALT_NOC_L4_PRIV_FLT_L4_PRIV_s
 

Macros

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_RESET   0x00000000
 
#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_OFST   0x0
 

Typedefs

typedef struct
ALT_NOC_L4_PRIV_FLT_L4_PRIV_s 
ALT_NOC_L4_PRIV_FLT_L4_PRIV_t
 

Data Structure Documentation

struct ALT_NOC_L4_PRIV_FLT_L4_PRIV_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV.

Data Fields
uint32_t nand_register: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG
uint32_t nand_data: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA
uint32_t qspi_data: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA
uint32_t usb0_register: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG
uint32_t usb1_register: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG
uint32_t dma_nonsecure: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE
uint32_t dma_secure: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE
uint32_t spi_master0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0
uint32_t spi_master1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1
uint32_t spi_slave0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0
uint32_t spi_slave1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1
uint32_t emac0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0
uint32_t emac1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1
uint32_t emac2: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2
uint32_t emac3: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3
uint32_t qspi: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI
uint32_t sdmmc: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC
uint32_t gpio0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0
uint32_t gpio1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1
uint32_t gpio2: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2
uint32_t i2c0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0
uint32_t i2c1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1
uint32_t i2c2: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2
uint32_t i2c3: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3
uint32_t i2c4: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4
uint32_t sp_timer0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0
uint32_t sp_timer1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1
uint32_t uart0: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0
uint32_t uart1: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1
uint32_t lwsoc2fpga: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F
uint32_t soc2fpga: 1 ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F
uint32_t __pad0__: 1 UNDEFINED

Macro Definitions

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_LSB   0

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_MSB   0

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET_MSK   0x00000001

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_CLR_MSK   0xfffffffe

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_REG register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_LSB   1

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_MSB   1

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET_MSK   0x00000002

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_CLR_MSK   0xfffffffd

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_NAND_DATA register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_LSB   2

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_MSB   2

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET_MSK   0x00000004

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_CLR_MSK   0xfffffffb

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_DATA register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_LSB   3

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_MSB   3

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET_MSK   0x00000008

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_CLR_MSK   0xfffffff7

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_GET (   value)    (((value) & 0x00000008) >> 3)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG_SET (   value)    (((value) << 3) & 0x00000008)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB0_REG register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_LSB   4

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_MSB   4

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET_MSK   0x00000010

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_CLR_MSK   0xffffffef

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_USB1_REG register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_LSB   5

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_MSB   5

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET_MSK   0x00000020

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_CLR_MSK   0xffffffdf

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_NONSECURE register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_LSB   6

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_MSB   6

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET_MSK   0x00000040

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_CLR_MSK   0xffffffbf

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_DMA_SECURE register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_LSB   7

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_MSB   7

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET_MSK   0x00000080

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_CLR_MSK   0xffffff7f

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_LSB   8

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_MSB   8

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET_MSK   0x00000100

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_CLR_MSK   0xfffffeff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_MST1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_LSB   9

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_MSB   9

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET_MSK   0x00000200

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_CLR_MSK   0xfffffdff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_GET (   value)    (((value) & 0x00000200) >> 9)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0_SET (   value)    (((value) << 9) & 0x00000200)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_LSB   10

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_MSB   10

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET_MSK   0x00000400

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_CLR_MSK   0xfffffbff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_GET (   value)    (((value) & 0x00000400) >> 10)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1_SET (   value)    (((value) << 10) & 0x00000400)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SPI_SLV1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_LSB   11

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_MSB   11

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET_MSK   0x00000800

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_CLR_MSK   0xfffff7ff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_GET (   value)    (((value) & 0x00000800) >> 11)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0_SET (   value)    (((value) << 11) & 0x00000800)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_LSB   12

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_MSB   12

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET_MSK   0x00001000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_CLR_MSK   0xffffefff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_GET (   value)    (((value) & 0x00001000) >> 12)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1_SET (   value)    (((value) << 12) & 0x00001000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_LSB   13

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_MSB   13

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET_MSK   0x00002000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_CLR_MSK   0xffffdfff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC2 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_LSB   14

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_MSB   14

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET_MSK   0x00004000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_CLR_MSK   0xffffbfff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field is UNKNOWN.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_GET (   value)    (((value) & 0x00004000) >> 14)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3_SET (   value)    (((value) << 14) & 0x00004000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_EMAC3 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_LSB   15

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_MSB   15

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET_MSK   0x00008000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_CLR_MSK   0xffff7fff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_GET (   value)    (((value) & 0x00008000) >> 15)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI_SET (   value)    (((value) << 15) & 0x00008000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_QSPI register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_LSB   16

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_MSB   16

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET_MSK   0x00010000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_CLR_MSK   0xfffeffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_GET (   value)    (((value) & 0x00010000) >> 16)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC_SET (   value)    (((value) << 16) & 0x00010000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SDMMC register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_LSB   17

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_MSB   17

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET_MSK   0x00020000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_CLR_MSK   0xfffdffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_GET (   value)    (((value) & 0x00020000) >> 17)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0_SET (   value)    (((value) << 17) & 0x00020000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_LSB   18

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_MSB   18

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET_MSK   0x00040000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_CLR_MSK   0xfffbffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_GET (   value)    (((value) & 0x00040000) >> 18)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1_SET (   value)    (((value) << 18) & 0x00040000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_LSB   19

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_MSB   19

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET_MSK   0x00080000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_CLR_MSK   0xfff7ffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_GET (   value)    (((value) & 0x00080000) >> 19)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2_SET (   value)    (((value) << 19) & 0x00080000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_GPIO2 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_LSB   20

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_MSB   20

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET_MSK   0x00100000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_CLR_MSK   0xffefffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_LSB   21

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_MSB   21

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET_MSK   0x00200000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_CLR_MSK   0xffdfffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_LSB   22

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_MSB   22

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET_MSK   0x00400000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_CLR_MSK   0xffbfffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C2 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_LSB   23

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_MSB   23

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET_MSK   0x00800000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_CLR_MSK   0xff7fffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C3 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_LSB   24

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_MSB   24

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET_MSK   0x01000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_CLR_MSK   0xfeffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_I2C4 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_LSB   25

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_MSB   25

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET_MSK   0x02000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_CLR_MSK   0xfdffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_LSB   26

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_MSB   26

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET_MSK   0x04000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_CLR_MSK   0xfbffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_SP_TMR1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_LSB   27

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_MSB   27

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET_MSK   0x08000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_CLR_MSK   0xf7ffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_GET (   value)    (((value) & 0x08000000) >> 27)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0_SET (   value)    (((value) << 27) & 0x08000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART0 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_LSB   28

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_MSB   28

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET_MSK   0x10000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_CLR_MSK   0xefffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_GET (   value)    (((value) & 0x10000000) >> 28)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1_SET (   value)    (((value) << 28) & 0x10000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_UART1 register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_LSB   29

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_MSB   29

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET_MSK   0x20000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_CLR_MSK   0xdfffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_GET (   value)    (((value) & 0x20000000) >> 29)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F_SET (   value)    (((value) << 29) & 0x20000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_LWH2F register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_LSB   30

The Least Significant Bit (LSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_MSB   30

The Most Significant Bit (MSB) position of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_WIDTH   1

The width in bits of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET_MSK   0x40000000

The mask used to set the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_CLR_MSK   0xbfffffff

The mask used to clear the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_RESET   0x0

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_GET (   value)    (((value) & 0x40000000) >> 30)

Extracts the ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F field value from a register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F_SET (   value)    (((value) << 30) & 0x40000000)

Produces a ALT_NOC_L4_PRIV_FLT_L4_PRIV_H2F register field value suitable for setting the register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_RESET   0x00000000

The reset value of the ALT_NOC_L4_PRIV_FLT_L4_PRIV register.

#define ALT_NOC_L4_PRIV_FLT_L4_PRIV_OFST   0x0

The byte offset of the ALT_NOC_L4_PRIV_FLT_L4_PRIV register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_NOC_L4_PRIV_FLT_L4_PRIV.