Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dmagrp_operation_mode

Description

Register 6 (Operation Mode Register)

The Operation Mode register establishes the Transmit and Receive operating modes and commands. This register should be the last CSR to be written as part of the DMA initialization. This register is also present in the GMAC-MTL configuration with unused and reserved bits 24, 13, 2, and 1.

Register Layout

Bits Access Reset Description
[0] R 0x0 ALT_EMAC_DMA_OP_MOD_RSVD_0
[1] RW 0x0 ALT_EMAC_DMA_OP_MOD_SR
[2] RW 0x0 ALT_EMAC_DMA_OP_MOD_OSF
[4:3] RW 0x0 ALT_EMAC_DMA_OP_MOD_RTC
[5] RW 0x0 ALT_EMAC_DMA_OP_MOD_DGF
[6] RW 0x0 ALT_EMAC_DMA_OP_MOD_FUF
[7] RW 0x0 ALT_EMAC_DMA_OP_MOD_FEF
[8] R 0x0 ALT_EMAC_DMA_OP_MOD_EFC
[10:9] R 0x0 ALT_EMAC_DMA_OP_MOD_RFA
[12:11] R 0x0 ALT_EMAC_DMA_OP_MOD_RFD
[13] RW 0x0 ALT_EMAC_DMA_OP_MOD_ST
[16:14] RW 0x0 ALT_EMAC_DMA_OP_MOD_TTC
[19:17] R 0x0 ALT_EMAC_DMA_OP_MOD_RSVD_19_17
[20] RW 0x0 ALT_EMAC_DMA_OP_MOD_FTF
[21] RW 0x0 ALT_EMAC_DMA_OP_MOD_TSF
[22] R 0x0 ALT_EMAC_DMA_OP_MOD_RFD_2
[23] R 0x0 ALT_EMAC_DMA_OP_MOD_RFA_2
[24] RW 0x0 ALT_EMAC_DMA_OP_MOD_DFF
[25] RW 0x0 ALT_EMAC_DMA_OP_MOD_RSF
[26] RW 0x0 ALT_EMAC_DMA_OP_MOD_DT
[31:27] R 0x0 ALT_EMAC_DMA_OP_MOD_RSVD_31_27

Field : reserved_0

Reserved

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_LSB   0
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_MSB   0
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET_MSK   0x00000001
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_CLR_MSK   0xfffffffe
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_GET(value)   (((value) & 0x00000001) >> 0)
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET(value)   (((value) << 0) & 0x00000001)
 

Field : sr

Start or Stop Receive

When this bit is set, the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames. The descriptor acquisition is attempted from the current position in the list, which is the address set by Register 3 (Receive Descriptor List Address Register) or the position retained when the Receive process was previously stopped. If the DMA does not own the descriptor, reception is suspended and Bit 7 (Receive Buffer Unavailable) of Register 5 (Status Register) is set. The Start Receive command is effective only when the reception has stopped. If the command is issued before setting Register 3 (Receive Descriptor List Address Register), the DMA behavior is unpredictable.

When this bit is cleared, the Rx DMA operation is stopped after the transfer of the current frame. The next descriptor position in the Receive list is saved and becomes the current position after the Receive process is restarted. The Stop Receive command is effective only when the Receive process is in either the Running (waiting for receive packet) or in the Suspended state.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_SR_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_SR_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_SR_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_SR_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_SR_LSB   1
 
#define ALT_EMAC_DMA_OP_MOD_SR_MSB   1
 
#define ALT_EMAC_DMA_OP_MOD_SR_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK   0x00000002
 
#define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK   0xfffffffd
 
#define ALT_EMAC_DMA_OP_MOD_SR_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_SR_GET(value)   (((value) & 0x00000002) >> 1)
 
#define ALT_EMAC_DMA_OP_MOD_SR_SET(value)   (((value) << 1) & 0x00000002)
 

Field : osf

Operate on Second Frame

When this bit is set, it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_OSF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_OSF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_OSF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_OSF_LSB   2
 
#define ALT_EMAC_DMA_OP_MOD_OSF_MSB   2
 
#define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK   0x00000004
 
#define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK   0xfffffffb
 
#define ALT_EMAC_DMA_OP_MOD_OSF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_OSF_GET(value)   (((value) & 0x00000004) >> 2)
 
#define ALT_EMAC_DMA_OP_MOD_OSF_SET(value)   (((value) << 2) & 0x00000004)
 

Field : rtc

Receive Threshold Control

These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. In addition, full frames with length less than the threshold are transferred automatically.

The value of 11 is not applicable if the configured Receive FIFO size is 128 bytes. These bits are valid only when the RSF bit is zero, and are ignored when the RSF bit is set to 1.

  • 00: 64
  • 01: 32
  • 10: 96
  • 11: 128

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64 | 0x0 | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32 | 0x1 | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96 | 0x2 | ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128 | 0x3 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32   0x1
 
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96   0x2
 
#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128   0x3
 
#define ALT_EMAC_DMA_OP_MOD_RTC_LSB   3
 
#define ALT_EMAC_DMA_OP_MOD_RTC_MSB   4
 
#define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH   2
 
#define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK   0x00000018
 
#define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK   0xffffffe7
 
#define ALT_EMAC_DMA_OP_MOD_RTC_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RTC_GET(value)   (((value) & 0x00000018) >> 3)
 
#define ALT_EMAC_DMA_OP_MOD_RTC_SET(value)   (((value) << 3) & 0x00000018)
 

Field : dgf

Drop Giant Frames

When set, the MAC drops the received giant frames in the Rx FIFO, that is, frames that are larger than the computed giant frame limit. When reset, the MAC does not drop the giant frames in the Rx FIFO.

Note: This bit is available in the following configurations in which the giant frame status is not provided in Rx status and giant frames are not dropped by default:

  • Configurations in which IP Checksum Offload (Type 1) is selected in Rx
  • Configurations in which the IPC Full Checksum Offload Engine (Type 2) is selected in Rx with normal descriptor format
  • Configurations in which the Advanced Timestamp feature is selected

In all other configurations, this bit is not used (reserved and always reset).

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_DGF_LSB   5
 
#define ALT_EMAC_DMA_OP_MOD_DGF_MSB   5
 
#define ALT_EMAC_DMA_OP_MOD_DGF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_DGF_SET_MSK   0x00000020
 
#define ALT_EMAC_DMA_OP_MOD_DGF_CLR_MSK   0xffffffdf
 
#define ALT_EMAC_DMA_OP_MOD_DGF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_DGF_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_EMAC_DMA_OP_MOD_DGF_SET(value)   (((value) << 5) & 0x00000020)
 

Field : fuf

Forward Undersized Good Frames

When set, the Rx FIFO forwards Undersized frames (frames with no Error and length less than 64 bytes) including pad-bytes and CRC.

When reset, the Rx FIFO drops all frames of less than 64 bytes, unless a frame is already transferred because of the lower value of Receive Threshold, for example, RTC = 01.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_FUF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_FUF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FUF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_FUF_LSB   6
 
#define ALT_EMAC_DMA_OP_MOD_FUF_MSB   6
 
#define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK   0x00000040
 
#define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK   0xffffffbf
 
#define ALT_EMAC_DMA_OP_MOD_FUF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FUF_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_EMAC_DMA_OP_MOD_FUF_SET(value)   (((value) << 6) & 0x00000040)
 

Field : fef

Forward Error Frames

When this bit is reset, the Rx FIFO drops frames with error status (CRC error, collision error, GMII_ER, giant frame, watchdog timeout, or overflow). However, if the start byte (write) pointer of a frame is already transferred to the read controller side (in Threshold mode), then the frame is not dropped.

In the GMAC-MTL configuration in which the Frame Length FIFO is also enabled during core configuration, the Rx FIFO drops the error frames if that frame's start byte is not transferred (output) on the ARI bus.

When the FEF bit is set, all frames except runt error frames are forwarded to the DMA. If the Bit 25 (RSF) is set and the Rx FIFO overflows when a partial frame is written, then the frame is dropped irrespective of the FEF bit setting. However, if the Bit 25 (RSF) is reset and the Rx FIFO overflows when a partial frame is

written, then a partial frame may be forwarded to the DMA.

Note: When FEF bit is reset, the giant frames are dropped if the giant frame status is given in Rx Status in the following configurations:

  • The IP checksum engine (Type 1) and full checksum offload engine (Type 2) are not selected.
  • The advanced timestamp feature is not selected but the extended status is selected. The extended status is available with the following features:

    • L3-L4 filter in GMAC-CORE or GMAC-MTL configurations
    • Full checksum offload engine (Type 2) with enhanced descriptor format in the GMAC-DMA, GMAC-AHB, or GMAC-AXI configurations.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_FEF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_FEF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FEF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_FEF_LSB   7
 
#define ALT_EMAC_DMA_OP_MOD_FEF_MSB   7
 
#define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK   0x00000080
 
#define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK   0xffffff7f
 
#define ALT_EMAC_DMA_OP_MOD_FEF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FEF_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_EMAC_DMA_OP_MOD_FEF_SET(value)   (((value) << 7) & 0x00000080)
 

Field : efc

Reserved

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_EFC_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_EFC_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_EFC_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_EFC_LSB   8
 
#define ALT_EMAC_DMA_OP_MOD_EFC_MSB   8
 
#define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK   0x00000100
 
#define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK   0xfffffeff
 
#define ALT_EMAC_DMA_OP_MOD_EFC_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_EFC_GET(value)   (((value) & 0x00000100) >> 8)
 
#define ALT_EMAC_DMA_OP_MOD_EFC_SET(value)   (((value) << 8) & 0x00000100)
 

Field : rfa

Threshold for Activating Flow Control (in half-duplex and full-duplex)

These bits control the threshold (Fill level of Rx FIFO) at which the flow control is activated.

  • 00: Full minus 1 KB, that is, FULL - 1KB
  • 01: Full minus 2 KB, that is, FULL - 2KB
  • 10: Full minus 3 KB, that is, FULL - 3KB
  • 11: Full minus 4 KB, that is, FULL - 4KB

These values are applicable only to Rx FIFOs of 4 KB or more and when Bit 8 (EFC) is set high. If the Rx FIFO is 8 KB or more, an additional Bit (RFA_2) is used for more threshold levels as described in Bit 23. These bits are reserved and read-only when the depth of Rx FIFO is less than 4 KB.

Note: When FIFO size is exactly 4 KB, although the DWC_gmac allows you to program the value of these bits to 11, the software should not program these bits to 2'b11. The value 2'b11 means flow control on FIFO empty condition.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K | 0x0 | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K | 0x1 | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K | 0x2 | ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K | 0x3 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K   0x1
 
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K   0x2
 
#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K   0x3
 
#define ALT_EMAC_DMA_OP_MOD_RFA_LSB   9
 
#define ALT_EMAC_DMA_OP_MOD_RFA_MSB   10
 
#define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH   2
 
#define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK   0x00000600
 
#define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK   0xfffff9ff
 
#define ALT_EMAC_DMA_OP_MOD_RFA_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFA_GET(value)   (((value) & 0x00000600) >> 9)
 
#define ALT_EMAC_DMA_OP_MOD_RFA_SET(value)   (((value) << 9) & 0x00000600)
 

Field : rfd

Threshold for Deactivating Flow Control (in half-duplex and full-duplex)

These bits control the threshold (Fill-level of Rx FIFO) at which the flow control is de-asserted after activation.

  • 00: Full minus 1 KB, that is, FULL - 1KB
  • 01: Full minus 2 KB, that is, FULL - 2KB
  • 10: Full minus 3 KB, that is, FULL - 3KB
  • 11: Full minus 4 KB, that is, FULL - 4KB

The de-assertion is effective only after flow control is asserted. If the Rx FIFO is 8 KB or more, an additional bit (RFD_2) is used for more threshold levels as described in Bit 22. These bits are reserved and read-only when the Rx FIFO depth is less than 4 KB.

Note: For proper flow control, the value programmed in the "RFD_2, RFD" fields should be equal to or more than the value programmed in the "RFA_2, RFA" fields.

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K | 0x0 | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K | 0x1 | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K | 0x2 | ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K | 0x3 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K   0x1
 
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K   0x2
 
#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K   0x3
 
#define ALT_EMAC_DMA_OP_MOD_RFD_LSB   11
 
#define ALT_EMAC_DMA_OP_MOD_RFD_MSB   12
 
#define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH   2
 
#define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK   0x00001800
 
#define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK   0xffffe7ff
 
#define ALT_EMAC_DMA_OP_MOD_RFD_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFD_GET(value)   (((value) & 0x00001800) >> 11)
 
#define ALT_EMAC_DMA_OP_MOD_RFD_SET(value)   (((value) << 11) & 0x00001800)
 

Field : st

Start or Stop Transmission Command

When this bit is set, transmission is placed in the Running state, and the DMA checks the Transmit List at the current position for a frame to be transmitted. Descriptor acquisition is attempted either from the current position in the list, which is the Transmit List Base Address set by Register 4 (Transmit Descriptor List Address Register), or from the position retained when transmission was stopped previously. If the DMA does not own the current descriptor, transmission enters the Suspended state and Bit 2 (Transmit Buffer Unavailable) of Register 5 (Status Register) is set. The Start Transmission command is effective only when transmission is stopped. If the command is issued before setting Register 4 (Transmit Descriptor List Address Register), then the DMA behavior is unpredictable.

When this bit is reset, the transmission process is placed in the Stopped state after completing the transmission of the current frame. The Next Descriptor position in the Transmit List is saved, and it becomes the current position when transmission is restarted. To change the list address, you need to program Register 4 (Transmit Descriptor List Address Register) with a new value when this bit is reset. The new value is considered when this bit is set again. The stop transmission command is effective only when the transmission of the current frame is complete or the transmission is in the Suspended state.

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_ST_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_ST_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_ST_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_ST_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_ST_LSB   13
 
#define ALT_EMAC_DMA_OP_MOD_ST_MSB   13
 
#define ALT_EMAC_DMA_OP_MOD_ST_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK   0x00002000
 
#define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK   0xffffdfff
 
#define ALT_EMAC_DMA_OP_MOD_ST_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_ST_GET(value)   (((value) & 0x00002000) >> 13)
 
#define ALT_EMAC_DMA_OP_MOD_ST_SET(value)   (((value) << 13) & 0x00002000)
 

Field : ttc

Transmit Threshold Control

These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition, full frames with a length less than the threshold are also transmitted. These bits are used only when Bit 21 (TSF) is reset.

  • 000: 64
  • 001: 128
  • 010: 192
  • 011: 256
  • 100: 40
  • 101: 32
  • 110: 24
  • 111: 16

Field Enumeration Values:

Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64 | 0x0 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128 | 0x1 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192 | 0x2 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256 | 0x3 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40 | 0x4 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32 | 0x5 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24 | 0x6 | ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16 | 0x7 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64   0x0
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128   0x1
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192   0x2
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256   0x3
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40   0x4
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32   0x5
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24   0x6
 
#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16   0x7
 
#define ALT_EMAC_DMA_OP_MOD_TTC_LSB   14
 
#define ALT_EMAC_DMA_OP_MOD_TTC_MSB   16
 
#define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH   3
 
#define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK   0x0001c000
 
#define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK   0xfffe3fff
 
#define ALT_EMAC_DMA_OP_MOD_TTC_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_TTC_GET(value)   (((value) & 0x0001c000) >> 14)
 
#define ALT_EMAC_DMA_OP_MOD_TTC_SET(value)   (((value) << 14) & 0x0001c000)
 

Field : reserved_19_17

Reserved

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_LSB   17
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_MSB   19
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_WIDTH   3
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET_MSK   0x000e0000
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_CLR_MSK   0xfff1ffff
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_GET(value)   (((value) & 0x000e0000) >> 17)
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET(value)   (((value) << 17) & 0x000e0000)
 

Field : ftf

Flush Transmit FIFO

When this bit is set, the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is completed. The Operation Mode register should not be written to until this bit is cleared. The data which is already accepted by the MAC transmitter is not flushed. It is scheduled for transmission and results in underflow and runt frame transmission.

Note: The flush operation is complete only when the Tx FIFO is emptied of its contents and all the pending Transmit Status of the transmitted frames are accepted by the host. To complete this flush operation, the PHY transmit clock (clk_tx_i) is required to be active.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_FTF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_FTF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FTF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_FTF_LSB   20
 
#define ALT_EMAC_DMA_OP_MOD_FTF_MSB   20
 
#define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK   0x00100000
 
#define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK   0xffefffff
 
#define ALT_EMAC_DMA_OP_MOD_FTF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_FTF_GET(value)   (((value) & 0x00100000) >> 20)
 
#define ALT_EMAC_DMA_OP_MOD_FTF_SET(value)   (((value) << 20) & 0x00100000)
 

Field : tsf

Transmit Store and Forward

When this bit is set, transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set, the TTC values specified in Bits[16:14] are ignored. This bit should be changed only when the transmission is stopped.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_TSF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_TSF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_TSF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_TSF_LSB   21
 
#define ALT_EMAC_DMA_OP_MOD_TSF_MSB   21
 
#define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK   0x00200000
 
#define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK   0xffdfffff
 
#define ALT_EMAC_DMA_OP_MOD_TSF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_TSF_GET(value)   (((value) & 0x00200000) >> 21)
 
#define ALT_EMAC_DMA_OP_MOD_TSF_SET(value)   (((value) << 21) & 0x00200000)
 

Field : rfd_2

MSB of Threshold for Deactivating Flow Control

If the DWC_gmac is configured for Rx FIFO size of 8 KB or more, this bit (when set) provides additional threshold levels for deactivating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFD (Bits[12:11]) gives the following thresholds for deactivating flow control:

  • 100: Full minus 5 KB, that is, FULL - 5KB
  • 101: Full minus 6 KB, that is, FULL - 6KB
  • 110: Full minus 7 KB, that is, FULL - 7KB
  • 111: Reserved

This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RFD_2_LSB   22
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_MSB   22
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_SET_MSK   0x00400000
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_CLR_MSK   0xffbfffff
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_GET(value)   (((value) & 0x00400000) >> 22)
 
#define ALT_EMAC_DMA_OP_MOD_RFD_2_SET(value)   (((value) << 22) & 0x00400000)
 

Field : rfa_2

MSB of Threshold for Activating Flow Control

If the DWC_gmac is configured for an Rx FIFO depth of 8 KB or more, this bit (when set) provides additional threshold levels for activating the flow control in both half-duplex and full-duplex modes. This bit (as Most Significant Bit) along with the RFA (Bits[10:9]) gives the following thresholds for activating flow control:

  • 100: Full minus 5 KB, that is, FULL - 5KB
  • 101: Full minus 6 KB, that is, FULL - 6KB
  • 110: Full minus 7 KB, that is, FULL - 7KB
  • 111: Reserved

This bit is reserved (and RO) if the Rx FIFO is 4 KB or less deep.

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RFA_2_LSB   23
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_MSB   23
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_SET_MSK   0x00800000
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_CLR_MSK   0xff7fffff
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_GET(value)   (((value) & 0x00800000) >> 23)
 
#define ALT_EMAC_DMA_OP_MOD_RFA_2_SET(value)   (((value) << 23) & 0x00800000)
 

Field : dff

Disable Flushing of Received Frames

When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset.

This bit is reserved (and RO) in the GMAC-MTL configuration.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_DFF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_DFF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_DFF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_DFF_LSB   24
 
#define ALT_EMAC_DMA_OP_MOD_DFF_MSB   24
 
#define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK   0x01000000
 
#define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK   0xfeffffff
 
#define ALT_EMAC_DMA_OP_MOD_DFF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_DFF_GET(value)   (((value) & 0x01000000) >> 24)
 
#define ALT_EMAC_DMA_OP_MOD_DFF_SET(value)   (((value) << 24) & 0x01000000)
 

Field : rsf

Receive Store and Forward

When this bit is set, the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it, ignoring the RTC bits. When this bit is reset, the Rx FIFO operates in the cut-through mode, subject to the threshold specified by the RTC bits.

Field Enumeration Values:

Enum | Value | Description :--------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_RSF_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_RSF_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RSF_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_RSF_LSB   25
 
#define ALT_EMAC_DMA_OP_MOD_RSF_MSB   25
 
#define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK   0x02000000
 
#define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK   0xfdffffff
 
#define ALT_EMAC_DMA_OP_MOD_RSF_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RSF_GET(value)   (((value) & 0x02000000) >> 25)
 
#define ALT_EMAC_DMA_OP_MOD_RSF_SET(value)   (((value) << 25) & 0x02000000)
 

Field : dt

Disable Dropping of TCP/IP Checksum Error Frames

When this bit is set, the MAC does not drop the frames which only have errors detected by the Receive Checksum Offload engine. Such frames do not have any errors (including FCS error) in the Ethernet frame received by the MAC but have errors only in the encapsulated payload. When this bit is reset, all error frames are dropped if the FEF bit is reset.

If the IPC Full Checksum Offload Engine (Type 2) is disabled, this bit is reserved (RO with value 1'b0).

Field Enumeration Values:

Enum | Value | Description :------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_DMA_OP_MOD_DT_E_DISD | 0x0 | ALT_EMAC_DMA_OP_MOD_DT_E_END | 0x1 |

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_DT_E_DISD   0x0
 
#define ALT_EMAC_DMA_OP_MOD_DT_E_END   0x1
 
#define ALT_EMAC_DMA_OP_MOD_DT_LSB   26
 
#define ALT_EMAC_DMA_OP_MOD_DT_MSB   26
 
#define ALT_EMAC_DMA_OP_MOD_DT_WIDTH   1
 
#define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK   0x04000000
 
#define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK   0xfbffffff
 
#define ALT_EMAC_DMA_OP_MOD_DT_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_DT_GET(value)   (((value) & 0x04000000) >> 26)
 
#define ALT_EMAC_DMA_OP_MOD_DT_SET(value)   (((value) << 26) & 0x04000000)
 

Field : reserved_31_27

Reserved

Field Access Macros:

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_LSB   27
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_MSB   31
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_WIDTH   5
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET_MSK   0xf8000000
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_CLR_MSK   0x07ffffff
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_RESET   0x0
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_GET(value)   (((value) & 0xf8000000) >> 27)
 
#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET(value)   (((value) << 27) & 0xf8000000)
 

Data Structures

struct  ALT_EMAC_DMA_OP_MOD_s
 

Macros

#define ALT_EMAC_DMA_OP_MOD_RESET   0x00000000
 
#define ALT_EMAC_DMA_OP_MOD_OFST   0x1018
 
#define ALT_EMAC_DMA_OP_MOD_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST))
 

Typedefs

typedef struct
ALT_EMAC_DMA_OP_MOD_s 
ALT_EMAC_DMA_OP_MOD_t
 

Data Structure Documentation

struct ALT_EMAC_DMA_OP_MOD_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_EMAC_DMA_OP_MOD.

Data Fields
const uint32_t reserved_0: 1 ALT_EMAC_DMA_OP_MOD_RSVD_0
uint32_t sr: 1 ALT_EMAC_DMA_OP_MOD_SR
uint32_t osf: 1 ALT_EMAC_DMA_OP_MOD_OSF
uint32_t rtc: 2 ALT_EMAC_DMA_OP_MOD_RTC
uint32_t dgf: 1 ALT_EMAC_DMA_OP_MOD_DGF
uint32_t fuf: 1 ALT_EMAC_DMA_OP_MOD_FUF
uint32_t fef: 1 ALT_EMAC_DMA_OP_MOD_FEF
const uint32_t efc: 1 ALT_EMAC_DMA_OP_MOD_EFC
const uint32_t rfa: 2 ALT_EMAC_DMA_OP_MOD_RFA
const uint32_t rfd: 2 ALT_EMAC_DMA_OP_MOD_RFD
uint32_t st: 1 ALT_EMAC_DMA_OP_MOD_ST
uint32_t ttc: 3 ALT_EMAC_DMA_OP_MOD_TTC
const uint32_t reserved_19_17: 3 ALT_EMAC_DMA_OP_MOD_RSVD_19_17
uint32_t ftf: 1 ALT_EMAC_DMA_OP_MOD_FTF
uint32_t tsf: 1 ALT_EMAC_DMA_OP_MOD_TSF
const uint32_t rfd_2: 1 ALT_EMAC_DMA_OP_MOD_RFD_2
const uint32_t rfa_2: 1 ALT_EMAC_DMA_OP_MOD_RFA_2
uint32_t dff: 1 ALT_EMAC_DMA_OP_MOD_DFF
uint32_t rsf: 1 ALT_EMAC_DMA_OP_MOD_RSF
uint32_t dt: 1 ALT_EMAC_DMA_OP_MOD_DT
const uint32_t reserved_31_27: 5 ALT_EMAC_DMA_OP_MOD_RSVD_31_27

Macro Definitions

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_LSB   0

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_MSB   0

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET_MSK   0x00000001

The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_CLR_MSK   0xfffffffe

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_0 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_GET (   value)    (((value) & 0x00000001) >> 0)

Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_0 field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RSVD_0_SET (   value)    (((value) << 0) & 0x00000001)

Produces a ALT_EMAC_DMA_OP_MOD_RSVD_0 register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_SR_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR

#define ALT_EMAC_DMA_OP_MOD_SR_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_SR

#define ALT_EMAC_DMA_OP_MOD_SR_LSB   1

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field.

#define ALT_EMAC_DMA_OP_MOD_SR_MSB   1

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_SR register field.

#define ALT_EMAC_DMA_OP_MOD_SR_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_SR register field.

#define ALT_EMAC_DMA_OP_MOD_SR_SET_MSK   0x00000002

The mask used to set the ALT_EMAC_DMA_OP_MOD_SR register field value.

#define ALT_EMAC_DMA_OP_MOD_SR_CLR_MSK   0xfffffffd

The mask used to clear the ALT_EMAC_DMA_OP_MOD_SR register field value.

#define ALT_EMAC_DMA_OP_MOD_SR_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_SR register field.

#define ALT_EMAC_DMA_OP_MOD_SR_GET (   value)    (((value) & 0x00000002) >> 1)

Extracts the ALT_EMAC_DMA_OP_MOD_SR field value from a register.

#define ALT_EMAC_DMA_OP_MOD_SR_SET (   value)    (((value) << 1) & 0x00000002)

Produces a ALT_EMAC_DMA_OP_MOD_SR register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_OSF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF

#define ALT_EMAC_DMA_OP_MOD_OSF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_OSF

#define ALT_EMAC_DMA_OP_MOD_OSF_LSB   2

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field.

#define ALT_EMAC_DMA_OP_MOD_OSF_MSB   2

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_OSF register field.

#define ALT_EMAC_DMA_OP_MOD_OSF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_OSF register field.

#define ALT_EMAC_DMA_OP_MOD_OSF_SET_MSK   0x00000004

The mask used to set the ALT_EMAC_DMA_OP_MOD_OSF register field value.

#define ALT_EMAC_DMA_OP_MOD_OSF_CLR_MSK   0xfffffffb

The mask used to clear the ALT_EMAC_DMA_OP_MOD_OSF register field value.

#define ALT_EMAC_DMA_OP_MOD_OSF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_OSF register field.

#define ALT_EMAC_DMA_OP_MOD_OSF_GET (   value)    (((value) & 0x00000004) >> 2)

Extracts the ALT_EMAC_DMA_OP_MOD_OSF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_OSF_SET (   value)    (((value) << 2) & 0x00000004)

Produces a ALT_EMAC_DMA_OP_MOD_OSF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO64   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC

#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO32   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC

#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO96   0x2

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC

#define ALT_EMAC_DMA_OP_MOD_RTC_E_THRFIFO128   0x3

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RTC

#define ALT_EMAC_DMA_OP_MOD_RTC_LSB   3

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field.

#define ALT_EMAC_DMA_OP_MOD_RTC_MSB   4

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RTC register field.

#define ALT_EMAC_DMA_OP_MOD_RTC_WIDTH   2

The width in bits of the ALT_EMAC_DMA_OP_MOD_RTC register field.

#define ALT_EMAC_DMA_OP_MOD_RTC_SET_MSK   0x00000018

The mask used to set the ALT_EMAC_DMA_OP_MOD_RTC register field value.

#define ALT_EMAC_DMA_OP_MOD_RTC_CLR_MSK   0xffffffe7

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RTC register field value.

#define ALT_EMAC_DMA_OP_MOD_RTC_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RTC register field.

#define ALT_EMAC_DMA_OP_MOD_RTC_GET (   value)    (((value) & 0x00000018) >> 3)

Extracts the ALT_EMAC_DMA_OP_MOD_RTC field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RTC_SET (   value)    (((value) << 3) & 0x00000018)

Produces a ALT_EMAC_DMA_OP_MOD_RTC register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_DGF_LSB   5

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DGF register field.

#define ALT_EMAC_DMA_OP_MOD_DGF_MSB   5

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DGF register field.

#define ALT_EMAC_DMA_OP_MOD_DGF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_DGF register field.

#define ALT_EMAC_DMA_OP_MOD_DGF_SET_MSK   0x00000020

The mask used to set the ALT_EMAC_DMA_OP_MOD_DGF register field value.

#define ALT_EMAC_DMA_OP_MOD_DGF_CLR_MSK   0xffffffdf

The mask used to clear the ALT_EMAC_DMA_OP_MOD_DGF register field value.

#define ALT_EMAC_DMA_OP_MOD_DGF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_DGF register field.

#define ALT_EMAC_DMA_OP_MOD_DGF_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_EMAC_DMA_OP_MOD_DGF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_DGF_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_EMAC_DMA_OP_MOD_DGF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_FUF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF

#define ALT_EMAC_DMA_OP_MOD_FUF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FUF

#define ALT_EMAC_DMA_OP_MOD_FUF_LSB   6

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field.

#define ALT_EMAC_DMA_OP_MOD_FUF_MSB   6

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FUF register field.

#define ALT_EMAC_DMA_OP_MOD_FUF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_FUF register field.

#define ALT_EMAC_DMA_OP_MOD_FUF_SET_MSK   0x00000040

The mask used to set the ALT_EMAC_DMA_OP_MOD_FUF register field value.

#define ALT_EMAC_DMA_OP_MOD_FUF_CLR_MSK   0xffffffbf

The mask used to clear the ALT_EMAC_DMA_OP_MOD_FUF register field value.

#define ALT_EMAC_DMA_OP_MOD_FUF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_FUF register field.

#define ALT_EMAC_DMA_OP_MOD_FUF_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_EMAC_DMA_OP_MOD_FUF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_FUF_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_EMAC_DMA_OP_MOD_FUF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_FEF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF

#define ALT_EMAC_DMA_OP_MOD_FEF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FEF

#define ALT_EMAC_DMA_OP_MOD_FEF_LSB   7

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field.

#define ALT_EMAC_DMA_OP_MOD_FEF_MSB   7

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FEF register field.

#define ALT_EMAC_DMA_OP_MOD_FEF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_FEF register field.

#define ALT_EMAC_DMA_OP_MOD_FEF_SET_MSK   0x00000080

The mask used to set the ALT_EMAC_DMA_OP_MOD_FEF register field value.

#define ALT_EMAC_DMA_OP_MOD_FEF_CLR_MSK   0xffffff7f

The mask used to clear the ALT_EMAC_DMA_OP_MOD_FEF register field value.

#define ALT_EMAC_DMA_OP_MOD_FEF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_FEF register field.

#define ALT_EMAC_DMA_OP_MOD_FEF_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_EMAC_DMA_OP_MOD_FEF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_FEF_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_EMAC_DMA_OP_MOD_FEF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_EFC_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC

#define ALT_EMAC_DMA_OP_MOD_EFC_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_EFC

#define ALT_EMAC_DMA_OP_MOD_EFC_LSB   8

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field.

#define ALT_EMAC_DMA_OP_MOD_EFC_MSB   8

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_EFC register field.

#define ALT_EMAC_DMA_OP_MOD_EFC_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_EFC register field.

#define ALT_EMAC_DMA_OP_MOD_EFC_SET_MSK   0x00000100

The mask used to set the ALT_EMAC_DMA_OP_MOD_EFC register field value.

#define ALT_EMAC_DMA_OP_MOD_EFC_CLR_MSK   0xfffffeff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_EFC register field value.

#define ALT_EMAC_DMA_OP_MOD_EFC_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_EFC register field.

#define ALT_EMAC_DMA_OP_MOD_EFC_GET (   value)    (((value) & 0x00000100) >> 8)

Extracts the ALT_EMAC_DMA_OP_MOD_EFC field value from a register.

#define ALT_EMAC_DMA_OP_MOD_EFC_SET (   value)    (((value) << 8) & 0x00000100)

Produces a ALT_EMAC_DMA_OP_MOD_EFC register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_1K   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA

#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_2K   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA

#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_3K   0x2

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA

#define ALT_EMAC_DMA_OP_MOD_RFA_E_FIFOFULL_4K   0x3

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFA

#define ALT_EMAC_DMA_OP_MOD_RFA_LSB   9

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_MSB   10

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_WIDTH   2

The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_SET_MSK   0x00000600

The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA register field value.

#define ALT_EMAC_DMA_OP_MOD_RFA_CLR_MSK   0xfffff9ff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA register field value.

#define ALT_EMAC_DMA_OP_MOD_RFA_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RFA register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_GET (   value)    (((value) & 0x00000600) >> 9)

Extracts the ALT_EMAC_DMA_OP_MOD_RFA field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RFA_SET (   value)    (((value) << 9) & 0x00000600)

Produces a ALT_EMAC_DMA_OP_MOD_RFA register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_1K   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD

#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_2K   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD

#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_3K   0x2

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD

#define ALT_EMAC_DMA_OP_MOD_RFD_E_FIFOFULL_4K   0x3

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RFD

#define ALT_EMAC_DMA_OP_MOD_RFD_LSB   11

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_MSB   12

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_WIDTH   2

The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_SET_MSK   0x00001800

The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD register field value.

#define ALT_EMAC_DMA_OP_MOD_RFD_CLR_MSK   0xffffe7ff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD register field value.

#define ALT_EMAC_DMA_OP_MOD_RFD_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RFD register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_GET (   value)    (((value) & 0x00001800) >> 11)

Extracts the ALT_EMAC_DMA_OP_MOD_RFD field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RFD_SET (   value)    (((value) << 11) & 0x00001800)

Produces a ALT_EMAC_DMA_OP_MOD_RFD register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_ST_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST

#define ALT_EMAC_DMA_OP_MOD_ST_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_ST

#define ALT_EMAC_DMA_OP_MOD_ST_LSB   13

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field.

#define ALT_EMAC_DMA_OP_MOD_ST_MSB   13

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_ST register field.

#define ALT_EMAC_DMA_OP_MOD_ST_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_ST register field.

#define ALT_EMAC_DMA_OP_MOD_ST_SET_MSK   0x00002000

The mask used to set the ALT_EMAC_DMA_OP_MOD_ST register field value.

#define ALT_EMAC_DMA_OP_MOD_ST_CLR_MSK   0xffffdfff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_ST register field value.

#define ALT_EMAC_DMA_OP_MOD_ST_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_ST register field.

#define ALT_EMAC_DMA_OP_MOD_ST_GET (   value)    (((value) & 0x00002000) >> 13)

Extracts the ALT_EMAC_DMA_OP_MOD_ST field value from a register.

#define ALT_EMAC_DMA_OP_MOD_ST_SET (   value)    (((value) << 13) & 0x00002000)

Produces a ALT_EMAC_DMA_OP_MOD_ST register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHESH64   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES128   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES192   0x2

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES256   0x3

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES40   0x4

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES32   0x5

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES24   0x6

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_E_TTCTHRES16   0x7

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TTC

#define ALT_EMAC_DMA_OP_MOD_TTC_LSB   14

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field.

#define ALT_EMAC_DMA_OP_MOD_TTC_MSB   16

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TTC register field.

#define ALT_EMAC_DMA_OP_MOD_TTC_WIDTH   3

The width in bits of the ALT_EMAC_DMA_OP_MOD_TTC register field.

#define ALT_EMAC_DMA_OP_MOD_TTC_SET_MSK   0x0001c000

The mask used to set the ALT_EMAC_DMA_OP_MOD_TTC register field value.

#define ALT_EMAC_DMA_OP_MOD_TTC_CLR_MSK   0xfffe3fff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_TTC register field value.

#define ALT_EMAC_DMA_OP_MOD_TTC_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_TTC register field.

#define ALT_EMAC_DMA_OP_MOD_TTC_GET (   value)    (((value) & 0x0001c000) >> 14)

Extracts the ALT_EMAC_DMA_OP_MOD_TTC field value from a register.

#define ALT_EMAC_DMA_OP_MOD_TTC_SET (   value)    (((value) << 14) & 0x0001c000)

Produces a ALT_EMAC_DMA_OP_MOD_TTC register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_LSB   17

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_MSB   19

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_WIDTH   3

The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET_MSK   0x000e0000

The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_CLR_MSK   0xfff1ffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_GET (   value)    (((value) & 0x000e0000) >> 17)

Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_19_17 field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RSVD_19_17_SET (   value)    (((value) << 17) & 0x000e0000)

Produces a ALT_EMAC_DMA_OP_MOD_RSVD_19_17 register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_FTF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF

#define ALT_EMAC_DMA_OP_MOD_FTF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_FTF

#define ALT_EMAC_DMA_OP_MOD_FTF_LSB   20

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field.

#define ALT_EMAC_DMA_OP_MOD_FTF_MSB   20

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_FTF register field.

#define ALT_EMAC_DMA_OP_MOD_FTF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_FTF register field.

#define ALT_EMAC_DMA_OP_MOD_FTF_SET_MSK   0x00100000

The mask used to set the ALT_EMAC_DMA_OP_MOD_FTF register field value.

#define ALT_EMAC_DMA_OP_MOD_FTF_CLR_MSK   0xffefffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_FTF register field value.

#define ALT_EMAC_DMA_OP_MOD_FTF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_FTF register field.

#define ALT_EMAC_DMA_OP_MOD_FTF_GET (   value)    (((value) & 0x00100000) >> 20)

Extracts the ALT_EMAC_DMA_OP_MOD_FTF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_FTF_SET (   value)    (((value) << 20) & 0x00100000)

Produces a ALT_EMAC_DMA_OP_MOD_FTF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_TSF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF

#define ALT_EMAC_DMA_OP_MOD_TSF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_TSF

#define ALT_EMAC_DMA_OP_MOD_TSF_LSB   21

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field.

#define ALT_EMAC_DMA_OP_MOD_TSF_MSB   21

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_TSF register field.

#define ALT_EMAC_DMA_OP_MOD_TSF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_TSF register field.

#define ALT_EMAC_DMA_OP_MOD_TSF_SET_MSK   0x00200000

The mask used to set the ALT_EMAC_DMA_OP_MOD_TSF register field value.

#define ALT_EMAC_DMA_OP_MOD_TSF_CLR_MSK   0xffdfffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_TSF register field value.

#define ALT_EMAC_DMA_OP_MOD_TSF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_TSF register field.

#define ALT_EMAC_DMA_OP_MOD_TSF_GET (   value)    (((value) & 0x00200000) >> 21)

Extracts the ALT_EMAC_DMA_OP_MOD_TSF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_TSF_SET (   value)    (((value) << 21) & 0x00200000)

Produces a ALT_EMAC_DMA_OP_MOD_TSF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_LSB   22

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_MSB   22

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_SET_MSK   0x00400000

The mask used to set the ALT_EMAC_DMA_OP_MOD_RFD_2 register field value.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_CLR_MSK   0xffbfffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFD_2 register field value.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RFD_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_GET (   value)    (((value) & 0x00400000) >> 22)

Extracts the ALT_EMAC_DMA_OP_MOD_RFD_2 field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RFD_2_SET (   value)    (((value) << 22) & 0x00400000)

Produces a ALT_EMAC_DMA_OP_MOD_RFD_2 register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_LSB   23

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_MSB   23

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_SET_MSK   0x00800000

The mask used to set the ALT_EMAC_DMA_OP_MOD_RFA_2 register field value.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_CLR_MSK   0xff7fffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RFA_2 register field value.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RFA_2 register field.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_GET (   value)    (((value) & 0x00800000) >> 23)

Extracts the ALT_EMAC_DMA_OP_MOD_RFA_2 field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RFA_2_SET (   value)    (((value) << 23) & 0x00800000)

Produces a ALT_EMAC_DMA_OP_MOD_RFA_2 register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_DFF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF

#define ALT_EMAC_DMA_OP_MOD_DFF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DFF

#define ALT_EMAC_DMA_OP_MOD_DFF_LSB   24

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field.

#define ALT_EMAC_DMA_OP_MOD_DFF_MSB   24

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DFF register field.

#define ALT_EMAC_DMA_OP_MOD_DFF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_DFF register field.

#define ALT_EMAC_DMA_OP_MOD_DFF_SET_MSK   0x01000000

The mask used to set the ALT_EMAC_DMA_OP_MOD_DFF register field value.

#define ALT_EMAC_DMA_OP_MOD_DFF_CLR_MSK   0xfeffffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_DFF register field value.

#define ALT_EMAC_DMA_OP_MOD_DFF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_DFF register field.

#define ALT_EMAC_DMA_OP_MOD_DFF_GET (   value)    (((value) & 0x01000000) >> 24)

Extracts the ALT_EMAC_DMA_OP_MOD_DFF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_DFF_SET (   value)    (((value) << 24) & 0x01000000)

Produces a ALT_EMAC_DMA_OP_MOD_DFF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RSF_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF

#define ALT_EMAC_DMA_OP_MOD_RSF_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_RSF

#define ALT_EMAC_DMA_OP_MOD_RSF_LSB   25

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field.

#define ALT_EMAC_DMA_OP_MOD_RSF_MSB   25

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSF register field.

#define ALT_EMAC_DMA_OP_MOD_RSF_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_RSF register field.

#define ALT_EMAC_DMA_OP_MOD_RSF_SET_MSK   0x02000000

The mask used to set the ALT_EMAC_DMA_OP_MOD_RSF register field value.

#define ALT_EMAC_DMA_OP_MOD_RSF_CLR_MSK   0xfdffffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSF register field value.

#define ALT_EMAC_DMA_OP_MOD_RSF_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RSF register field.

#define ALT_EMAC_DMA_OP_MOD_RSF_GET (   value)    (((value) & 0x02000000) >> 25)

Extracts the ALT_EMAC_DMA_OP_MOD_RSF field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RSF_SET (   value)    (((value) << 25) & 0x02000000)

Produces a ALT_EMAC_DMA_OP_MOD_RSF register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_DT_E_DISD   0x0

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT

#define ALT_EMAC_DMA_OP_MOD_DT_E_END   0x1

Enumerated value for register field ALT_EMAC_DMA_OP_MOD_DT

#define ALT_EMAC_DMA_OP_MOD_DT_LSB   26

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field.

#define ALT_EMAC_DMA_OP_MOD_DT_MSB   26

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_DT register field.

#define ALT_EMAC_DMA_OP_MOD_DT_WIDTH   1

The width in bits of the ALT_EMAC_DMA_OP_MOD_DT register field.

#define ALT_EMAC_DMA_OP_MOD_DT_SET_MSK   0x04000000

The mask used to set the ALT_EMAC_DMA_OP_MOD_DT register field value.

#define ALT_EMAC_DMA_OP_MOD_DT_CLR_MSK   0xfbffffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_DT register field value.

#define ALT_EMAC_DMA_OP_MOD_DT_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_DT register field.

#define ALT_EMAC_DMA_OP_MOD_DT_GET (   value)    (((value) & 0x04000000) >> 26)

Extracts the ALT_EMAC_DMA_OP_MOD_DT field value from a register.

#define ALT_EMAC_DMA_OP_MOD_DT_SET (   value)    (((value) << 26) & 0x04000000)

Produces a ALT_EMAC_DMA_OP_MOD_DT register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_LSB   27

The Least Significant Bit (LSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_MSB   31

The Most Significant Bit (MSB) position of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_WIDTH   5

The width in bits of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET_MSK   0xf8000000

The mask used to set the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_CLR_MSK   0x07ffffff

The mask used to clear the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_RESET   0x0

The reset value of the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_GET (   value)    (((value) & 0xf8000000) >> 27)

Extracts the ALT_EMAC_DMA_OP_MOD_RSVD_31_27 field value from a register.

#define ALT_EMAC_DMA_OP_MOD_RSVD_31_27_SET (   value)    (((value) << 27) & 0xf8000000)

Produces a ALT_EMAC_DMA_OP_MOD_RSVD_31_27 register field value suitable for setting the register.

#define ALT_EMAC_DMA_OP_MOD_RESET   0x00000000

The reset value of the ALT_EMAC_DMA_OP_MOD register.

#define ALT_EMAC_DMA_OP_MOD_OFST   0x1018

The byte offset of the ALT_EMAC_DMA_OP_MOD register from the beginning of the component.

#define ALT_EMAC_DMA_OP_MOD_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_DMA_OP_MOD_OFST))

The address of the ALT_EMAC_DMA_OP_MOD register.

Typedef Documentation

The typedef declaration for register ALT_EMAC_DMA_OP_MOD.