Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : TX FIFO Write - jtag_data_w

Description

A write to this field initiates a write to the TxFifo with the value provided. Please note that this is always a 32bit write, and lower 16 of these bits will be transferred over TDI and upper 16 of these bits will be transferred over TMS once the transfer is initiated. A write to this fifo when full will just be ignored. Also it is allowed to keep writing this fifo without actually intiating a transfer. A typical scenario where this is applicable is if the software want to keep a fixed number of bits ready for JTAG interface before kicking it off.

Both the fifos are 8 words deep. So you can have up to 128 bits buffered in the FIFOs. If you have more than 128 bits to be transferred, and want continuous transfer software should make sure proper data flow to avoid a Tx-Fifo under-run or Rx-Fifo over-run. A Rx-Fifo over-run will cause silent data loss, and a Tx- Fifo under-run will stop the transfer, and will stop the TCK toggles, till another transfer is initiated by software.

At 5MHz jtag clock 16x100/5 = 320 cycles of FPGA manager clock to transfer 1 word of data

At 25Mhz jtag clock 16x100/25 = 64 cycles of FPGA manager clock to transfer 1 word of data.

Register Layout

Bits Access Reset Description
[15:0] RW 0x0 TDI Data
[31:16] RW 0x0 TMS Data

Field : TDI Data - tdiData

Field Access Macros:

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_LSB   0
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_MSB   15
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_WIDTH   16
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET_MSK   0x0000ffff
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_CLR_MSK   0xffff0000
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_RESET   0x0
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_GET(value)   (((value) & 0x0000ffff) >> 0)
 
#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET(value)   (((value) << 0) & 0x0000ffff)
 

Field : TMS Data - tmsData

Data to be transferred over TMS.

Field Access Macros:

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_LSB   16
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_MSB   31
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_WIDTH   16
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET_MSK   0xffff0000
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_CLR_MSK   0x0000ffff
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_RESET   0x0
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_GET(value)   (((value) & 0xffff0000) >> 16)
 
#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET(value)   (((value) << 16) & 0xffff0000)
 

Data Structures

struct  ALT_FPGAMGR_JTAG_DATA_W_s
 

Macros

#define ALT_FPGAMGR_JTAG_DATA_W_RESET   0x00000000
 
#define ALT_FPGAMGR_JTAG_DATA_W_OFST   0x60
 

Typedefs

typedef struct
ALT_FPGAMGR_JTAG_DATA_W_s 
ALT_FPGAMGR_JTAG_DATA_W_t
 

Data Structure Documentation

struct ALT_FPGAMGR_JTAG_DATA_W_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_FPGAMGR_JTAG_DATA_W.

Data Fields
uint32_t tdiData: 16 TDI Data
uint32_t tmsData: 16 TMS Data

Macro Definitions

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_LSB   0

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_MSB   15

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_WIDTH   16

The width in bits of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET_MSK   0x0000ffff

The mask used to set the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_CLR_MSK   0xffff0000

The mask used to clear the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_RESET   0x0

The reset value of the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_GET (   value)    (((value) & 0x0000ffff) >> 0)

Extracts the ALT_FPGAMGR_JTAG_DATA_W_TDIDATA field value from a register.

#define ALT_FPGAMGR_JTAG_DATA_W_TDIDATA_SET (   value)    (((value) << 0) & 0x0000ffff)

Produces a ALT_FPGAMGR_JTAG_DATA_W_TDIDATA register field value suitable for setting the register.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_LSB   16

The Least Significant Bit (LSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_MSB   31

The Most Significant Bit (MSB) position of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_WIDTH   16

The width in bits of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET_MSK   0xffff0000

The mask used to set the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_CLR_MSK   0x0000ffff

The mask used to clear the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_RESET   0x0

The reset value of the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_GET (   value)    (((value) & 0xffff0000) >> 16)

Extracts the ALT_FPGAMGR_JTAG_DATA_W_TMSDATA field value from a register.

#define ALT_FPGAMGR_JTAG_DATA_W_TMSDATA_SET (   value)    (((value) << 16) & 0xffff0000)

Produces a ALT_FPGAMGR_JTAG_DATA_W_TMSDATA register field value suitable for setting the register.

#define ALT_FPGAMGR_JTAG_DATA_W_RESET   0x00000000

The reset value of the ALT_FPGAMGR_JTAG_DATA_W register.

#define ALT_FPGAMGR_JTAG_DATA_W_OFST   0x60

The byte offset of the ALT_FPGAMGR_JTAG_DATA_W register from the beginning of the component.

Typedef Documentation

The typedef declaration for register ALT_FPGAMGR_JTAG_DATA_W.