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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[5:0] | RW | 0x32 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA |
[7:6] | ??? | 0x0 | UNDEFINED |
[13:8] | RW | 0x14 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW |
[31:14] | ??? | 0x0 | UNDEFINED |
Field : addr_2_data | |
Signifies the number of bus interface nand_mp_clk clocks that should be introduced between address latch enable going low to write enable going low. The number of clocks is the function of device parameter Tadl and controller clock frequency. Field Access Macros: | |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET(value) (((value) & 0x0000003f) >> 0) |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET(value) (((value) << 0) & 0x0000003f) |
Field : tcwaw | |
Signifies the number of controller clocks that should be introduced between the command cycle of a random data input command to the address cycle of the random data input command. Field Access Macros: | |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14 |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET(value) (((value) & 0x00003f00) >> 8) |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET(value) (((value) << 8) & 0x00003f00) |
Data Structures | |
struct | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s |
Macros | |
#define | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110 |
Typedefs | |
typedef struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_t |
struct ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA.
Data Fields | ||
---|---|---|
uint32_t | addr_2_data: 6 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA |
uint32_t | __pad0__: 2 | UNDEFINED |
uint32_t | tcwaw: 6 | ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW |
uint32_t | __pad1__: 18 | UNDEFINED |
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_WIDTH 6 |
The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET_MSK 0x0000003f |
The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_CLR_MSK 0xffffffc0 |
The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_RESET 0x32 |
The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_GET | ( | value | ) | (((value) & 0x0000003f) >> 0) |
Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA field value from a register.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA_SET | ( | value | ) | (((value) << 0) & 0x0000003f) |
Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_ADDR_2_DATA register field value suitable for setting the register.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_WIDTH 6 |
The width in bits of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET_MSK 0x00003f00 |
The mask used to set the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_CLR_MSK 0xffffc0ff |
The mask used to clear the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_RESET 0x14 |
The reset value of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_GET | ( | value | ) | (((value) & 0x00003f00) >> 8) |
Extracts the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW field value from a register.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW_SET | ( | value | ) | (((value) << 8) & 0x00003f00) |
Produces a ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_TCWAW register field value suitable for setting the register.
#define ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA_OFST 0x110 |
The byte offset of the ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA register from the beginning of the component.
The typedef declaration for register ALT_NAND_CFG_TCWAW_AND_ADDR_2_DATA.