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alt_spim.h
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/***********************************************************************************
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* *
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* Copyright 2013-2015 Altera Corporation. All Rights Reserved. *
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* *
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* Redistribution and use in source and binary forms, with or without *
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* modification, are permitted provided that the following conditions are met: *
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* *
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* 1. Redistributions of source code must retain the above copyright notice, *
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* this list of conditions and the following disclaimer. *
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* *
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* 2. Redistributions in binary form must reproduce the above copyright notice, *
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* this list of conditions and the following disclaimer in the documentation *
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* and/or other materials provided with the distribution. *
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* *
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* 3. Neither the name of the copyright holder nor the names of its contributors *
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* may be used to endorse or promote products derived from this software without *
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* specific prior written permission. *
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* *
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE *
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE *
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE *
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR *
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF *
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS *
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN *
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) *
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE *
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* POSSIBILITY OF SUCH DAMAGE. *
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* *
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***********************************************************************************/
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#ifndef __ALTERA_ALT_SPIM_H__
36
#define __ALTERA_ALT_SPIM_H__
37
38
#ifdef __cplusplus
39
extern
"C"
40
{
41
#endif
/* __cplusplus */
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101
#define ALT_SPIM_CTLR0_DFS_E_WIDTH4BIT 0x3
102
107
#define ALT_SPIM_CTLR0_DFS_E_WIDTH5BIT 0x4
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#define ALT_SPIM_CTLR0_DFS_E_WIDTH6BIT 0x5
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#define ALT_SPIM_CTLR0_DFS_E_WIDTH7BIT 0x6
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#define ALT_SPIM_CTLR0_DFS_E_WIDTH8BIT 0x7
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#define ALT_SPIM_CTLR0_DFS_E_WIDTH9BIT 0x8
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#define ALT_SPIM_CTLR0_DFS_E_WIDTH10BIT 0x9
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#define ALT_SPIM_CTLR0_DFS_LSB 0
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#define ALT_SPIM_CTLR0_DFS_MSB 3
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#define ALT_SPIM_CTLR0_DFS_WIDTH 4
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#define ALT_SPIM_CTLR0_DFS_SET_MSK 0x0000000f
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#define ALT_SPIM_CTLR0_DFS_CLR_MSK 0xfffffff0
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#define ALT_SPIM_CTLR0_DFS_RESET 0x7
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#define ALT_SPIM_CTLR0_DFS_GET(value) (((value) & 0x0000000f) >> 0)
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#define ALT_SPIM_CTLR0_DFS_SET(value) (((value) << 0) & 0x0000000f)
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#define ALT_SPIM_CTLR0_FRF_E_MOTSPI 0x0
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#define ALT_SPIM_CTLR0_FRF_E_TISSP 0x1
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#define ALT_SPIM_CTLR0_FRF_E_NATMW 0x2
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#define ALT_SPIM_CTLR0_FRF_LSB 4
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#define ALT_SPIM_CTLR0_FRF_MSB 5
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#define ALT_SPIM_CTLR0_FRF_WIDTH 2
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#define ALT_SPIM_CTLR0_FRF_SET_MSK 0x00000030
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#define ALT_SPIM_CTLR0_FRF_CLR_MSK 0xffffffcf
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#define ALT_SPIM_CTLR0_FRF_RESET 0x0
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#define ALT_SPIM_CTLR0_FRF_GET(value) (((value) & 0x00000030) >> 4)
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#define ALT_SPIM_CTLR0_FRF_SET(value) (((value) << 4) & 0x00000030)
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#define ALT_SPIM_CTLR0_SCPH_E_MIDBIT 0x0
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#define ALT_SPIM_CTLR0_SCPH_E_STARTBIT 0x1
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#define ALT_SPIM_CTLR0_SCPH_LSB 6
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#define ALT_SPIM_CTLR0_SCPH_MSB 6
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#define ALT_SPIM_CTLR0_SCPH_WIDTH 1
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#define ALT_SPIM_CTLR0_SCPH_SET_MSK 0x00000040
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#define ALT_SPIM_CTLR0_SCPH_CLR_MSK 0xffffffbf
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#define ALT_SPIM_CTLR0_SCPH_RESET 0x0
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#define ALT_SPIM_CTLR0_SCPH_GET(value) (((value) & 0x00000040) >> 6)
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#define ALT_SPIM_CTLR0_SCPH_SET(value) (((value) << 6) & 0x00000040)
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279
#define ALT_SPIM_CTLR0_SCPOL_E_INACTLOW 0x0
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#define ALT_SPIM_CTLR0_SCPOL_E_INACTHIGH 0x1
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#define ALT_SPIM_CTLR0_SCPOL_LSB 7
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#define ALT_SPIM_CTLR0_SCPOL_MSB 7
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#define ALT_SPIM_CTLR0_SCPOL_WIDTH 1
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#define ALT_SPIM_CTLR0_SCPOL_SET_MSK 0x00000080
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#define ALT_SPIM_CTLR0_SCPOL_CLR_MSK 0xffffff7f
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#define ALT_SPIM_CTLR0_SCPOL_RESET 0x0
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#define ALT_SPIM_CTLR0_SCPOL_GET(value) (((value) & 0x00000080) >> 7)
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#define ALT_SPIM_CTLR0_SCPOL_SET(value) (((value) << 7) & 0x00000080)
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#define ALT_SPIM_CTLR0_TMOD_E_TXRX 0x0
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#define ALT_SPIM_CTLR0_TMOD_E_TXONLY 0x1
342
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#define ALT_SPIM_CTLR0_TMOD_E_RXONLY 0x2
348
353
#define ALT_SPIM_CTLR0_TMOD_E_EERD 0x3
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#define ALT_SPIM_CTLR0_TMOD_LSB 8
357
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#define ALT_SPIM_CTLR0_TMOD_MSB 9
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#define ALT_SPIM_CTLR0_TMOD_WIDTH 2
361
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#define ALT_SPIM_CTLR0_TMOD_SET_MSK 0x00000300
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#define ALT_SPIM_CTLR0_TMOD_CLR_MSK 0xfffffcff
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#define ALT_SPIM_CTLR0_TMOD_RESET 0x0
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#define ALT_SPIM_CTLR0_TMOD_GET(value) (((value) & 0x00000300) >> 8)
369
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#define ALT_SPIM_CTLR0_TMOD_SET(value) (((value) << 8) & 0x00000300)
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#define ALT_SPIM_CTLR0_SRL_E_NORMMOD 0x0
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#define ALT_SPIM_CTLR0_SRL_E_TESTMOD 0x1
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402
#define ALT_SPIM_CTLR0_SRL_LSB 11
403
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#define ALT_SPIM_CTLR0_SRL_MSB 11
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#define ALT_SPIM_CTLR0_SRL_WIDTH 1
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#define ALT_SPIM_CTLR0_SRL_SET_MSK 0x00000800
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#define ALT_SPIM_CTLR0_SRL_CLR_MSK 0xfffff7ff
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#define ALT_SPIM_CTLR0_SRL_RESET 0x0
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#define ALT_SPIM_CTLR0_SRL_GET(value) (((value) & 0x00000800) >> 11)
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#define ALT_SPIM_CTLR0_SRL_SET(value) (((value) << 11) & 0x00000800)
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#define ALT_SPIM_CTLR0_CFS_LSB 12
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#define ALT_SPIM_CTLR0_CFS_MSB 15
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#define ALT_SPIM_CTLR0_CFS_WIDTH 4
433
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#define ALT_SPIM_CTLR0_CFS_SET_MSK 0x0000f000
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#define ALT_SPIM_CTLR0_CFS_CLR_MSK 0xffff0fff
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#define ALT_SPIM_CTLR0_CFS_RESET 0x0
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#define ALT_SPIM_CTLR0_CFS_GET(value) (((value) & 0x0000f000) >> 12)
441
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#define ALT_SPIM_CTLR0_CFS_SET(value) (((value) << 12) & 0x0000f000)
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#ifndef __ASSEMBLY__
445
455
struct
ALT_SPIM_CTLR0_s
456
{
457
uint32_t
dfs
: 4;
458
uint32_t
frf
: 2;
459
uint32_t
scph
: 1;
460
uint32_t
scpol
: 1;
461
uint32_t
tmod
: 2;
462
uint32_t : 1;
463
uint32_t
srl
: 1;
464
uint32_t
cfs
: 4;
465
uint32_t : 16;
466
};
467
469
typedef
volatile
struct
ALT_SPIM_CTLR0_s
ALT_SPIM_CTLR0_t
;
470
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIM_CTLR0_OFST 0x0
474
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#define ALT_SPIM_CTLR0_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR0_OFST))
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#define ALT_SPIM_CTLR1_NDF_LSB 0
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#define ALT_SPIM_CTLR1_NDF_MSB 15
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#define ALT_SPIM_CTLR1_NDF_WIDTH 16
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#define ALT_SPIM_CTLR1_NDF_SET_MSK 0x0000ffff
513
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#define ALT_SPIM_CTLR1_NDF_CLR_MSK 0xffff0000
515
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#define ALT_SPIM_CTLR1_NDF_RESET 0x0
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#define ALT_SPIM_CTLR1_NDF_GET(value) (((value) & 0x0000ffff) >> 0)
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#define ALT_SPIM_CTLR1_NDF_SET(value) (((value) << 0) & 0x0000ffff)
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522
#ifndef __ASSEMBLY__
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struct
ALT_SPIM_CTLR1_s
534
{
535
uint32_t
ndf
: 16;
536
uint32_t : 16;
537
};
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540
typedef
volatile
struct
ALT_SPIM_CTLR1_s
ALT_SPIM_CTLR1_t
;
541
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIM_CTLR1_OFST 0x4
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#define ALT_SPIM_CTLR1_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_CTLR1_OFST))
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#define ALT_SPIM_SPIENR_SPI_EN_E_DISD 0x0
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#define ALT_SPIM_SPIENR_SPI_EN_E_END 0x1
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#define ALT_SPIM_SPIENR_SPI_EN_LSB 0
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#define ALT_SPIM_SPIENR_SPI_EN_MSB 0
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#define ALT_SPIM_SPIENR_SPI_EN_WIDTH 1
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#define ALT_SPIM_SPIENR_SPI_EN_SET_MSK 0x00000001
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#define ALT_SPIM_SPIENR_SPI_EN_CLR_MSK 0xfffffffe
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#define ALT_SPIM_SPIENR_SPI_EN_RESET 0x0
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#define ALT_SPIM_SPIENR_SPI_EN_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SPIM_SPIENR_SPI_EN_SET(value) (((value) << 0) & 0x00000001)
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#ifndef __ASSEMBLY__
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620
struct
ALT_SPIM_SPIENR_s
621
{
622
uint32_t
spi_en
: 1;
623
uint32_t : 31;
624
};
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627
typedef
volatile
struct
ALT_SPIM_SPIENR_s
ALT_SPIM_SPIENR_t
;
628
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIM_SPIENR_OFST 0x8
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#define ALT_SPIM_SPIENR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPIENR_OFST))
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#define ALT_SPIM_MWCR_MWMOD_E_NONSEQ 0x0
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#define ALT_SPIM_MWCR_MWMOD_E_SEQ 0x1
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#define ALT_SPIM_MWCR_MWMOD_LSB 0
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#define ALT_SPIM_MWCR_MWMOD_MSB 0
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#define ALT_SPIM_MWCR_MWMOD_WIDTH 1
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#define ALT_SPIM_MWCR_MWMOD_SET_MSK 0x00000001
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#define ALT_SPIM_MWCR_MWMOD_CLR_MSK 0xfffffffe
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#define ALT_SPIM_MWCR_MWMOD_RESET 0x0
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#define ALT_SPIM_MWCR_MWMOD_GET(value) (((value) & 0x00000001) >> 0)
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#define ALT_SPIM_MWCR_MWMOD_SET(value) (((value) << 0) & 0x00000001)
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#define ALT_SPIM_MWCR_MDD_E_RXMOD 0x0
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#define ALT_SPIM_MWCR_MDD_E_TXMOD 0x1
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#define ALT_SPIM_MWCR_MDD_LSB 1
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#define ALT_SPIM_MWCR_MDD_MSB 1
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#define ALT_SPIM_MWCR_MDD_WIDTH 1
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#define ALT_SPIM_MWCR_MDD_SET_MSK 0x00000002
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#define ALT_SPIM_MWCR_MDD_CLR_MSK 0xfffffffd
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#define ALT_SPIM_MWCR_MDD_RESET 0x0
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#define ALT_SPIM_MWCR_MDD_GET(value) (((value) & 0x00000002) >> 1)
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#define ALT_SPIM_MWCR_MDD_SET(value) (((value) << 1) & 0x00000002)
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#define ALT_SPIM_MWCR_MHS_E_DISD 0x0
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#define ALT_SPIM_MWCR_MHS_E_END 0x1
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#define ALT_SPIM_MWCR_MHS_LSB 2
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#define ALT_SPIM_MWCR_MHS_MSB 2
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#define ALT_SPIM_MWCR_MHS_WIDTH 1
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#define ALT_SPIM_MWCR_MHS_SET_MSK 0x00000004
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#define ALT_SPIM_MWCR_MHS_CLR_MSK 0xfffffffb
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#define ALT_SPIM_MWCR_MHS_RESET 0x0
790
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#define ALT_SPIM_MWCR_MHS_GET(value) (((value) & 0x00000004) >> 2)
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#define ALT_SPIM_MWCR_MHS_SET(value) (((value) << 2) & 0x00000004)
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795
#ifndef __ASSEMBLY__
796
806
struct
ALT_SPIM_MWCR_s
807
{
808
uint32_t
mwmod
: 1;
809
uint32_t
mdd
: 1;
810
uint32_t
mhs
: 1;
811
uint32_t : 29;
812
};
813
815
typedef
volatile
struct
ALT_SPIM_MWCR_s
ALT_SPIM_MWCR_t
;
816
#endif
/* __ASSEMBLY__ */
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#define ALT_SPIM_MWCR_OFST 0xc
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#define ALT_SPIM_MWCR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_MWCR_OFST))
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#define ALT_SPIM_SER_SER_E_NOTSELECTED 0x0
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#define ALT_SPIM_SER_SER_E_SELECTED 0x1
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#define ALT_SPIM_SER_SER_LSB 0
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#define ALT_SPIM_SER_SER_MSB 3
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#define ALT_SPIM_SER_SER_WIDTH 4
879
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#define ALT_SPIM_SER_SER_SET_MSK 0x0000000f
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#define ALT_SPIM_SER_SER_CLR_MSK 0xfffffff0
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#define ALT_SPIM_SER_SER_RESET 0x0
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#define ALT_SPIM_SER_SER_GET(value) (((value) & 0x0000000f) >> 0)
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#define ALT_SPIM_SER_SER_SET(value) (((value) << 0) & 0x0000000f)
889
890
#ifndef __ASSEMBLY__
891
901
struct
ALT_SPIM_SER_s
902
{
903
uint32_t
ser
: 4;
904
uint32_t : 28;
905
};
906
908
typedef
volatile
struct
ALT_SPIM_SER_s
ALT_SPIM_SER_t
;
909
#endif
/* __ASSEMBLY__ */
910
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#define ALT_SPIM_SER_OFST 0x10
913
914
#define ALT_SPIM_SER_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SER_OFST))
915
952
#define ALT_SPIM_BAUDR_SCKDV_LSB 0
953
954
#define ALT_SPIM_BAUDR_SCKDV_MSB 15
955
956
#define ALT_SPIM_BAUDR_SCKDV_WIDTH 16
957
958
#define ALT_SPIM_BAUDR_SCKDV_SET_MSK 0x0000ffff
959
960
#define ALT_SPIM_BAUDR_SCKDV_CLR_MSK 0xffff0000
961
962
#define ALT_SPIM_BAUDR_SCKDV_RESET 0x0
963
964
#define ALT_SPIM_BAUDR_SCKDV_GET(value) (((value) & 0x0000ffff) >> 0)
965
966
#define ALT_SPIM_BAUDR_SCKDV_SET(value) (((value) << 0) & 0x0000ffff)
967
968
#ifndef __ASSEMBLY__
969
979
struct
ALT_SPIM_BAUDR_s
980
{
981
uint32_t
sckdv
: 16;
982
uint32_t : 16;
983
};
984
986
typedef
volatile
struct
ALT_SPIM_BAUDR_s
ALT_SPIM_BAUDR_t
;
987
#endif
/* __ASSEMBLY__ */
988
990
#define ALT_SPIM_BAUDR_OFST 0x14
991
992
#define ALT_SPIM_BAUDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_BAUDR_OFST))
993
1020
#define ALT_SPIM_TXFTLR_TFT_LSB 0
1021
1022
#define ALT_SPIM_TXFTLR_TFT_MSB 7
1023
1024
#define ALT_SPIM_TXFTLR_TFT_WIDTH 8
1025
1026
#define ALT_SPIM_TXFTLR_TFT_SET_MSK 0x000000ff
1027
1028
#define ALT_SPIM_TXFTLR_TFT_CLR_MSK 0xffffff00
1029
1030
#define ALT_SPIM_TXFTLR_TFT_RESET 0x0
1031
1032
#define ALT_SPIM_TXFTLR_TFT_GET(value) (((value) & 0x000000ff) >> 0)
1033
1034
#define ALT_SPIM_TXFTLR_TFT_SET(value) (((value) << 0) & 0x000000ff)
1035
1036
#ifndef __ASSEMBLY__
1037
1047
struct
ALT_SPIM_TXFTLR_s
1048
{
1049
uint32_t
tft
: 8;
1050
uint32_t : 24;
1051
};
1052
1054
typedef
volatile
struct
ALT_SPIM_TXFTLR_s
ALT_SPIM_TXFTLR_t
;
1055
#endif
/* __ASSEMBLY__ */
1056
1058
#define ALT_SPIM_TXFTLR_OFST 0x18
1059
1060
#define ALT_SPIM_TXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFTLR_OFST))
1061
1088
#define ALT_SPIM_RXFTLR_RFT_LSB 0
1089
1090
#define ALT_SPIM_RXFTLR_RFT_MSB 7
1091
1092
#define ALT_SPIM_RXFTLR_RFT_WIDTH 8
1093
1094
#define ALT_SPIM_RXFTLR_RFT_SET_MSK 0x000000ff
1095
1096
#define ALT_SPIM_RXFTLR_RFT_CLR_MSK 0xffffff00
1097
1098
#define ALT_SPIM_RXFTLR_RFT_RESET 0x0
1099
1100
#define ALT_SPIM_RXFTLR_RFT_GET(value) (((value) & 0x000000ff) >> 0)
1101
1102
#define ALT_SPIM_RXFTLR_RFT_SET(value) (((value) << 0) & 0x000000ff)
1103
1104
#ifndef __ASSEMBLY__
1105
1115
struct
ALT_SPIM_RXFTLR_s
1116
{
1117
uint32_t
rft
: 8;
1118
uint32_t : 24;
1119
};
1120
1122
typedef
volatile
struct
ALT_SPIM_RXFTLR_s
ALT_SPIM_RXFTLR_t
;
1123
#endif
/* __ASSEMBLY__ */
1124
1126
#define ALT_SPIM_RXFTLR_OFST 0x1c
1127
1128
#define ALT_SPIM_RXFTLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFTLR_OFST))
1129
1153
#define ALT_SPIM_TXFLR_TXTFL_LSB 0
1154
1155
#define ALT_SPIM_TXFLR_TXTFL_MSB 8
1156
1157
#define ALT_SPIM_TXFLR_TXTFL_WIDTH 9
1158
1159
#define ALT_SPIM_TXFLR_TXTFL_SET_MSK 0x000001ff
1160
1161
#define ALT_SPIM_TXFLR_TXTFL_CLR_MSK 0xfffffe00
1162
1163
#define ALT_SPIM_TXFLR_TXTFL_RESET 0x0
1164
1165
#define ALT_SPIM_TXFLR_TXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1166
1167
#define ALT_SPIM_TXFLR_TXTFL_SET(value) (((value) << 0) & 0x000001ff)
1168
1169
#ifndef __ASSEMBLY__
1170
1180
struct
ALT_SPIM_TXFLR_s
1181
{
1182
const
uint32_t
txtfl
: 9;
1183
uint32_t : 23;
1184
};
1185
1187
typedef
volatile
struct
ALT_SPIM_TXFLR_s
ALT_SPIM_TXFLR_t
;
1188
#endif
/* __ASSEMBLY__ */
1189
1191
#define ALT_SPIM_TXFLR_OFST 0x20
1192
1193
#define ALT_SPIM_TXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXFLR_OFST))
1194
1218
#define ALT_SPIM_RXFLR_RXTFL_LSB 0
1219
1220
#define ALT_SPIM_RXFLR_RXTFL_MSB 8
1221
1222
#define ALT_SPIM_RXFLR_RXTFL_WIDTH 9
1223
1224
#define ALT_SPIM_RXFLR_RXTFL_SET_MSK 0x000001ff
1225
1226
#define ALT_SPIM_RXFLR_RXTFL_CLR_MSK 0xfffffe00
1227
1228
#define ALT_SPIM_RXFLR_RXTFL_RESET 0x0
1229
1230
#define ALT_SPIM_RXFLR_RXTFL_GET(value) (((value) & 0x000001ff) >> 0)
1231
1232
#define ALT_SPIM_RXFLR_RXTFL_SET(value) (((value) << 0) & 0x000001ff)
1233
1234
#ifndef __ASSEMBLY__
1235
1245
struct
ALT_SPIM_RXFLR_s
1246
{
1247
const
uint32_t
rxtfl
: 9;
1248
uint32_t : 23;
1249
};
1250
1252
typedef
volatile
struct
ALT_SPIM_RXFLR_s
ALT_SPIM_RXFLR_t
;
1253
#endif
/* __ASSEMBLY__ */
1254
1256
#define ALT_SPIM_RXFLR_OFST 0x24
1257
1258
#define ALT_SPIM_RXFLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXFLR_OFST))
1259
1299
#define ALT_SPIM_SR_BUSY_E_INACT 0x0
1300
1305
#define ALT_SPIM_SR_BUSY_E_ACT 0x1
1306
1308
#define ALT_SPIM_SR_BUSY_LSB 0
1309
1310
#define ALT_SPIM_SR_BUSY_MSB 0
1311
1312
#define ALT_SPIM_SR_BUSY_WIDTH 1
1313
1314
#define ALT_SPIM_SR_BUSY_SET_MSK 0x00000001
1315
1316
#define ALT_SPIM_SR_BUSY_CLR_MSK 0xfffffffe
1317
1318
#define ALT_SPIM_SR_BUSY_RESET 0x0
1319
1320
#define ALT_SPIM_SR_BUSY_GET(value) (((value) & 0x00000001) >> 0)
1321
1322
#define ALT_SPIM_SR_BUSY_SET(value) (((value) << 0) & 0x00000001)
1323
1344
#define ALT_SPIM_SR_TFNF_E_FULL 0x0
1345
1350
#define ALT_SPIM_SR_TFNF_E_NOTFULL 0x1
1351
1353
#define ALT_SPIM_SR_TFNF_LSB 1
1354
1355
#define ALT_SPIM_SR_TFNF_MSB 1
1356
1357
#define ALT_SPIM_SR_TFNF_WIDTH 1
1358
1359
#define ALT_SPIM_SR_TFNF_SET_MSK 0x00000002
1360
1361
#define ALT_SPIM_SR_TFNF_CLR_MSK 0xfffffffd
1362
1363
#define ALT_SPIM_SR_TFNF_RESET 0x1
1364
1365
#define ALT_SPIM_SR_TFNF_GET(value) (((value) & 0x00000002) >> 1)
1366
1367
#define ALT_SPIM_SR_TFNF_SET(value) (((value) << 1) & 0x00000002)
1368
1389
#define ALT_SPIM_SR_TFE_E_EMPTY 0x1
1390
1395
#define ALT_SPIM_SR_TFE_E_NOTEMPTY 0x0
1396
1398
#define ALT_SPIM_SR_TFE_LSB 2
1399
1400
#define ALT_SPIM_SR_TFE_MSB 2
1401
1402
#define ALT_SPIM_SR_TFE_WIDTH 1
1403
1404
#define ALT_SPIM_SR_TFE_SET_MSK 0x00000004
1405
1406
#define ALT_SPIM_SR_TFE_CLR_MSK 0xfffffffb
1407
1408
#define ALT_SPIM_SR_TFE_RESET 0x1
1409
1410
#define ALT_SPIM_SR_TFE_GET(value) (((value) & 0x00000004) >> 2)
1411
1412
#define ALT_SPIM_SR_TFE_SET(value) (((value) << 2) & 0x00000004)
1413
1434
#define ALT_SPIM_SR_RFNE_E_EMPTY 0x0
1435
1440
#define ALT_SPIM_SR_RFNE_E_NOTEMPTY 0x1
1441
1443
#define ALT_SPIM_SR_RFNE_LSB 3
1444
1445
#define ALT_SPIM_SR_RFNE_MSB 3
1446
1447
#define ALT_SPIM_SR_RFNE_WIDTH 1
1448
1449
#define ALT_SPIM_SR_RFNE_SET_MSK 0x00000008
1450
1451
#define ALT_SPIM_SR_RFNE_CLR_MSK 0xfffffff7
1452
1453
#define ALT_SPIM_SR_RFNE_RESET 0x0
1454
1455
#define ALT_SPIM_SR_RFNE_GET(value) (((value) & 0x00000008) >> 3)
1456
1457
#define ALT_SPIM_SR_RFNE_SET(value) (((value) << 3) & 0x00000008)
1458
1479
#define ALT_SPIM_SR_RFF_E_NOTFULL 0x0
1480
1485
#define ALT_SPIM_SR_RFF_E_FULL 0x1
1486
1488
#define ALT_SPIM_SR_RFF_LSB 4
1489
1490
#define ALT_SPIM_SR_RFF_MSB 4
1491
1492
#define ALT_SPIM_SR_RFF_WIDTH 1
1493
1494
#define ALT_SPIM_SR_RFF_SET_MSK 0x00000010
1495
1496
#define ALT_SPIM_SR_RFF_CLR_MSK 0xffffffef
1497
1498
#define ALT_SPIM_SR_RFF_RESET 0x0
1499
1500
#define ALT_SPIM_SR_RFF_GET(value) (((value) & 0x00000010) >> 4)
1501
1502
#define ALT_SPIM_SR_RFF_SET(value) (((value) << 4) & 0x00000010)
1503
1504
#ifndef __ASSEMBLY__
1505
1515
struct
ALT_SPIM_SR_s
1516
{
1517
const
uint32_t
busy
: 1;
1518
const
uint32_t
tfnf
: 1;
1519
const
uint32_t
tfe
: 1;
1520
const
uint32_t
rfne
: 1;
1521
const
uint32_t
rff
: 1;
1522
uint32_t : 27;
1523
};
1524
1526
typedef
volatile
struct
ALT_SPIM_SR_s
ALT_SPIM_SR_t
;
1527
#endif
/* __ASSEMBLY__ */
1528
1530
#define ALT_SPIM_SR_OFST 0x28
1531
1532
#define ALT_SPIM_SR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SR_OFST))
1533
1571
#define ALT_SPIM_IMR_TXEIM_E_MSKED 0x0
1572
1577
#define ALT_SPIM_IMR_TXEIM_E_END 0x1
1578
1580
#define ALT_SPIM_IMR_TXEIM_LSB 0
1581
1582
#define ALT_SPIM_IMR_TXEIM_MSB 0
1583
1584
#define ALT_SPIM_IMR_TXEIM_WIDTH 1
1585
1586
#define ALT_SPIM_IMR_TXEIM_SET_MSK 0x00000001
1587
1588
#define ALT_SPIM_IMR_TXEIM_CLR_MSK 0xfffffffe
1589
1590
#define ALT_SPIM_IMR_TXEIM_RESET 0x1
1591
1592
#define ALT_SPIM_IMR_TXEIM_GET(value) (((value) & 0x00000001) >> 0)
1593
1594
#define ALT_SPIM_IMR_TXEIM_SET(value) (((value) << 0) & 0x00000001)
1595
1616
#define ALT_SPIM_IMR_TXOIM_E_MSKED 0x0
1617
1622
#define ALT_SPIM_IMR_TXOIM_E_END 0x1
1623
1625
#define ALT_SPIM_IMR_TXOIM_LSB 1
1626
1627
#define ALT_SPIM_IMR_TXOIM_MSB 1
1628
1629
#define ALT_SPIM_IMR_TXOIM_WIDTH 1
1630
1631
#define ALT_SPIM_IMR_TXOIM_SET_MSK 0x00000002
1632
1633
#define ALT_SPIM_IMR_TXOIM_CLR_MSK 0xfffffffd
1634
1635
#define ALT_SPIM_IMR_TXOIM_RESET 0x1
1636
1637
#define ALT_SPIM_IMR_TXOIM_GET(value) (((value) & 0x00000002) >> 1)
1638
1639
#define ALT_SPIM_IMR_TXOIM_SET(value) (((value) << 1) & 0x00000002)
1640
1661
#define ALT_SPIM_IMR_RXUIM_E_MSKED 0x0
1662
1667
#define ALT_SPIM_IMR_RXUIM_E_END 0x1
1668
1670
#define ALT_SPIM_IMR_RXUIM_LSB 2
1671
1672
#define ALT_SPIM_IMR_RXUIM_MSB 2
1673
1674
#define ALT_SPIM_IMR_RXUIM_WIDTH 1
1675
1676
#define ALT_SPIM_IMR_RXUIM_SET_MSK 0x00000004
1677
1678
#define ALT_SPIM_IMR_RXUIM_CLR_MSK 0xfffffffb
1679
1680
#define ALT_SPIM_IMR_RXUIM_RESET 0x1
1681
1682
#define ALT_SPIM_IMR_RXUIM_GET(value) (((value) & 0x00000004) >> 2)
1683
1684
#define ALT_SPIM_IMR_RXUIM_SET(value) (((value) << 2) & 0x00000004)
1685
1706
#define ALT_SPIM_IMR_RXOIM_E_MSKED 0x0
1707
1712
#define ALT_SPIM_IMR_RXOIM_E_END 0x1
1713
1715
#define ALT_SPIM_IMR_RXOIM_LSB 3
1716
1717
#define ALT_SPIM_IMR_RXOIM_MSB 3
1718
1719
#define ALT_SPIM_IMR_RXOIM_WIDTH 1
1720
1721
#define ALT_SPIM_IMR_RXOIM_SET_MSK 0x00000008
1722
1723
#define ALT_SPIM_IMR_RXOIM_CLR_MSK 0xfffffff7
1724
1725
#define ALT_SPIM_IMR_RXOIM_RESET 0x1
1726
1727
#define ALT_SPIM_IMR_RXOIM_GET(value) (((value) & 0x00000008) >> 3)
1728
1729
#define ALT_SPIM_IMR_RXOIM_SET(value) (((value) << 3) & 0x00000008)
1730
1751
#define ALT_SPIM_IMR_RXFIM_E_MSKED 0x0
1752
1757
#define ALT_SPIM_IMR_RXFIM_E_END 0x1
1758
1760
#define ALT_SPIM_IMR_RXFIM_LSB 4
1761
1762
#define ALT_SPIM_IMR_RXFIM_MSB 4
1763
1764
#define ALT_SPIM_IMR_RXFIM_WIDTH 1
1765
1766
#define ALT_SPIM_IMR_RXFIM_SET_MSK 0x00000010
1767
1768
#define ALT_SPIM_IMR_RXFIM_CLR_MSK 0xffffffef
1769
1770
#define ALT_SPIM_IMR_RXFIM_RESET 0x1
1771
1772
#define ALT_SPIM_IMR_RXFIM_GET(value) (((value) & 0x00000010) >> 4)
1773
1774
#define ALT_SPIM_IMR_RXFIM_SET(value) (((value) << 4) & 0x00000010)
1775
1776
#ifndef __ASSEMBLY__
1777
1787
struct
ALT_SPIM_IMR_s
1788
{
1789
uint32_t
txeim
: 1;
1790
uint32_t
txoim
: 1;
1791
uint32_t
rxuim
: 1;
1792
uint32_t
rxoim
: 1;
1793
uint32_t
rxfim
: 1;
1794
uint32_t : 27;
1795
};
1796
1798
typedef
volatile
struct
ALT_SPIM_IMR_s
ALT_SPIM_IMR_t
;
1799
#endif
/* __ASSEMBLY__ */
1800
1802
#define ALT_SPIM_IMR_OFST 0x2c
1803
1804
#define ALT_SPIM_IMR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IMR_OFST))
1805
1846
#define ALT_SPIM_ISR_TXEIS_E_INACT 0x0
1847
1852
#define ALT_SPIM_ISR_TXEIS_E_ACT 0x1
1853
1855
#define ALT_SPIM_ISR_TXEIS_LSB 0
1856
1857
#define ALT_SPIM_ISR_TXEIS_MSB 0
1858
1859
#define ALT_SPIM_ISR_TXEIS_WIDTH 1
1860
1861
#define ALT_SPIM_ISR_TXEIS_SET_MSK 0x00000001
1862
1863
#define ALT_SPIM_ISR_TXEIS_CLR_MSK 0xfffffffe
1864
1865
#define ALT_SPIM_ISR_TXEIS_RESET 0x0
1866
1867
#define ALT_SPIM_ISR_TXEIS_GET(value) (((value) & 0x00000001) >> 0)
1868
1869
#define ALT_SPIM_ISR_TXEIS_SET(value) (((value) << 0) & 0x00000001)
1870
1892
#define ALT_SPIM_ISR_TXOIS_E_INACT 0x0
1893
1898
#define ALT_SPIM_ISR_TXOIS_E_ACT 0x1
1899
1901
#define ALT_SPIM_ISR_TXOIS_LSB 1
1902
1903
#define ALT_SPIM_ISR_TXOIS_MSB 1
1904
1905
#define ALT_SPIM_ISR_TXOIS_WIDTH 1
1906
1907
#define ALT_SPIM_ISR_TXOIS_SET_MSK 0x00000002
1908
1909
#define ALT_SPIM_ISR_TXOIS_CLR_MSK 0xfffffffd
1910
1911
#define ALT_SPIM_ISR_TXOIS_RESET 0x0
1912
1913
#define ALT_SPIM_ISR_TXOIS_GET(value) (((value) & 0x00000002) >> 1)
1914
1915
#define ALT_SPIM_ISR_TXOIS_SET(value) (((value) << 1) & 0x00000002)
1916
1938
#define ALT_SPIM_ISR_RXUIS_E_INACT 0x0
1939
1944
#define ALT_SPIM_ISR_RXUIS_E_ACT 0x1
1945
1947
#define ALT_SPIM_ISR_RXUIS_LSB 2
1948
1949
#define ALT_SPIM_ISR_RXUIS_MSB 2
1950
1951
#define ALT_SPIM_ISR_RXUIS_WIDTH 1
1952
1953
#define ALT_SPIM_ISR_RXUIS_SET_MSK 0x00000004
1954
1955
#define ALT_SPIM_ISR_RXUIS_CLR_MSK 0xfffffffb
1956
1957
#define ALT_SPIM_ISR_RXUIS_RESET 0x0
1958
1959
#define ALT_SPIM_ISR_RXUIS_GET(value) (((value) & 0x00000004) >> 2)
1960
1961
#define ALT_SPIM_ISR_RXUIS_SET(value) (((value) << 2) & 0x00000004)
1962
1984
#define ALT_SPIM_ISR_RXOIS_E_INACT 0x0
1985
1990
#define ALT_SPIM_ISR_RXOIS_E_ACT 0x1
1991
1993
#define ALT_SPIM_ISR_RXOIS_LSB 3
1994
1995
#define ALT_SPIM_ISR_RXOIS_MSB 3
1996
1997
#define ALT_SPIM_ISR_RXOIS_WIDTH 1
1998
1999
#define ALT_SPIM_ISR_RXOIS_SET_MSK 0x00000008
2000
2001
#define ALT_SPIM_ISR_RXOIS_CLR_MSK 0xfffffff7
2002
2003
#define ALT_SPIM_ISR_RXOIS_RESET 0x0
2004
2005
#define ALT_SPIM_ISR_RXOIS_GET(value) (((value) & 0x00000008) >> 3)
2006
2007
#define ALT_SPIM_ISR_RXOIS_SET(value) (((value) << 3) & 0x00000008)
2008
2030
#define ALT_SPIM_ISR_RXFIS_E_INACT 0x0
2031
2036
#define ALT_SPIM_ISR_RXFIS_E_ACT 0x1
2037
2039
#define ALT_SPIM_ISR_RXFIS_LSB 4
2040
2041
#define ALT_SPIM_ISR_RXFIS_MSB 4
2042
2043
#define ALT_SPIM_ISR_RXFIS_WIDTH 1
2044
2045
#define ALT_SPIM_ISR_RXFIS_SET_MSK 0x00000010
2046
2047
#define ALT_SPIM_ISR_RXFIS_CLR_MSK 0xffffffef
2048
2049
#define ALT_SPIM_ISR_RXFIS_RESET 0x0
2050
2051
#define ALT_SPIM_ISR_RXFIS_GET(value) (((value) & 0x00000010) >> 4)
2052
2053
#define ALT_SPIM_ISR_RXFIS_SET(value) (((value) << 4) & 0x00000010)
2054
2077
#define ALT_SPIM_ISR_MSTIS_E_INACT 0x0
2078
2083
#define ALT_SPIM_ISR_MSTIS_E_ACT 0x1
2084
2086
#define ALT_SPIM_ISR_MSTIS_LSB 5
2087
2088
#define ALT_SPIM_ISR_MSTIS_MSB 5
2089
2090
#define ALT_SPIM_ISR_MSTIS_WIDTH 1
2091
2092
#define ALT_SPIM_ISR_MSTIS_SET_MSK 0x00000020
2093
2094
#define ALT_SPIM_ISR_MSTIS_CLR_MSK 0xffffffdf
2095
2096
#define ALT_SPIM_ISR_MSTIS_RESET 0x0
2097
2098
#define ALT_SPIM_ISR_MSTIS_GET(value) (((value) & 0x00000020) >> 5)
2099
2100
#define ALT_SPIM_ISR_MSTIS_SET(value) (((value) << 5) & 0x00000020)
2101
2102
#ifndef __ASSEMBLY__
2103
2113
struct
ALT_SPIM_ISR_s
2114
{
2115
const
uint32_t
txeis
: 1;
2116
const
uint32_t
txois
: 1;
2117
const
uint32_t
rxuis
: 1;
2118
const
uint32_t
rxois
: 1;
2119
const
uint32_t
rxfis
: 1;
2120
const
uint32_t
mstis
: 1;
2121
uint32_t : 26;
2122
};
2123
2125
typedef
volatile
struct
ALT_SPIM_ISR_s
ALT_SPIM_ISR_t
;
2126
#endif
/* __ASSEMBLY__ */
2127
2129
#define ALT_SPIM_ISR_OFST 0x30
2130
2131
#define ALT_SPIM_ISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ISR_OFST))
2132
2171
#define ALT_SPIM_RISR_TXEIR_E_INACT 0x0
2172
2177
#define ALT_SPIM_RISR_TXEIR_E_ACT 0x1
2178
2180
#define ALT_SPIM_RISR_TXEIR_LSB 0
2181
2182
#define ALT_SPIM_RISR_TXEIR_MSB 0
2183
2184
#define ALT_SPIM_RISR_TXEIR_WIDTH 1
2185
2186
#define ALT_SPIM_RISR_TXEIR_SET_MSK 0x00000001
2187
2188
#define ALT_SPIM_RISR_TXEIR_CLR_MSK 0xfffffffe
2189
2190
#define ALT_SPIM_RISR_TXEIR_RESET 0x0
2191
2192
#define ALT_SPIM_RISR_TXEIR_GET(value) (((value) & 0x00000001) >> 0)
2193
2194
#define ALT_SPIM_RISR_TXEIR_SET(value) (((value) << 0) & 0x00000001)
2195
2217
#define ALT_SPIM_RISR_TXOIR_E_INACT 0x0
2218
2223
#define ALT_SPIM_RISR_TXOIR_E_ACT 0x1
2224
2226
#define ALT_SPIM_RISR_TXOIR_LSB 1
2227
2228
#define ALT_SPIM_RISR_TXOIR_MSB 1
2229
2230
#define ALT_SPIM_RISR_TXOIR_WIDTH 1
2231
2232
#define ALT_SPIM_RISR_TXOIR_SET_MSK 0x00000002
2233
2234
#define ALT_SPIM_RISR_TXOIR_CLR_MSK 0xfffffffd
2235
2236
#define ALT_SPIM_RISR_TXOIR_RESET 0x0
2237
2238
#define ALT_SPIM_RISR_TXOIR_GET(value) (((value) & 0x00000002) >> 1)
2239
2240
#define ALT_SPIM_RISR_TXOIR_SET(value) (((value) << 1) & 0x00000002)
2241
2264
#define ALT_SPIM_RISR_RXUIR_E_INACT 0x0
2265
2270
#define ALT_SPIM_RISR_RXUIR_E_ACT 0x1
2271
2273
#define ALT_SPIM_RISR_RXUIR_LSB 2
2274
2275
#define ALT_SPIM_RISR_RXUIR_MSB 2
2276
2277
#define ALT_SPIM_RISR_RXUIR_WIDTH 1
2278
2279
#define ALT_SPIM_RISR_RXUIR_SET_MSK 0x00000004
2280
2281
#define ALT_SPIM_RISR_RXUIR_CLR_MSK 0xfffffffb
2282
2283
#define ALT_SPIM_RISR_RXUIR_RESET 0x0
2284
2285
#define ALT_SPIM_RISR_RXUIR_GET(value) (((value) & 0x00000004) >> 2)
2286
2287
#define ALT_SPIM_RISR_RXUIR_SET(value) (((value) << 2) & 0x00000004)
2288
2310
#define ALT_SPIM_RISR_RXOIR_E_INACTOVE 0x0
2311
2316
#define ALT_SPIM_RISR_RXOIR_E_ACT 0x1
2317
2319
#define ALT_SPIM_RISR_RXOIR_LSB 3
2320
2321
#define ALT_SPIM_RISR_RXOIR_MSB 3
2322
2323
#define ALT_SPIM_RISR_RXOIR_WIDTH 1
2324
2325
#define ALT_SPIM_RISR_RXOIR_SET_MSK 0x00000008
2326
2327
#define ALT_SPIM_RISR_RXOIR_CLR_MSK 0xfffffff7
2328
2329
#define ALT_SPIM_RISR_RXOIR_RESET 0x0
2330
2331
#define ALT_SPIM_RISR_RXOIR_GET(value) (((value) & 0x00000008) >> 3)
2332
2333
#define ALT_SPIM_RISR_RXOIR_SET(value) (((value) << 3) & 0x00000008)
2334
2357
#define ALT_SPIM_RISR_RXFIR_E_INACT 0x0
2358
2363
#define ALT_SPIM_RISR_RXFIR_E_ACT 0x1
2364
2366
#define ALT_SPIM_RISR_RXFIR_LSB 4
2367
2368
#define ALT_SPIM_RISR_RXFIR_MSB 4
2369
2370
#define ALT_SPIM_RISR_RXFIR_WIDTH 1
2371
2372
#define ALT_SPIM_RISR_RXFIR_SET_MSK 0x00000010
2373
2374
#define ALT_SPIM_RISR_RXFIR_CLR_MSK 0xffffffef
2375
2376
#define ALT_SPIM_RISR_RXFIR_RESET 0x0
2377
2378
#define ALT_SPIM_RISR_RXFIR_GET(value) (((value) & 0x00000010) >> 4)
2379
2380
#define ALT_SPIM_RISR_RXFIR_SET(value) (((value) << 4) & 0x00000010)
2381
2382
#ifndef __ASSEMBLY__
2383
2393
struct
ALT_SPIM_RISR_s
2394
{
2395
const
uint32_t
txeir
: 1;
2396
const
uint32_t
txoir
: 1;
2397
const
uint32_t
rxuir
: 1;
2398
const
uint32_t
rxoir
: 1;
2399
const
uint32_t
rxfir
: 1;
2400
uint32_t : 27;
2401
};
2402
2404
typedef
volatile
struct
ALT_SPIM_RISR_s
ALT_SPIM_RISR_t
;
2405
#endif
/* __ASSEMBLY__ */
2406
2408
#define ALT_SPIM_RISR_OFST 0x34
2409
2410
#define ALT_SPIM_RISR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RISR_OFST))
2411
2435
#define ALT_SPIM_TXOICR_TXOICR_LSB 0
2436
2437
#define ALT_SPIM_TXOICR_TXOICR_MSB 0
2438
2439
#define ALT_SPIM_TXOICR_TXOICR_WIDTH 1
2440
2441
#define ALT_SPIM_TXOICR_TXOICR_SET_MSK 0x00000001
2442
2443
#define ALT_SPIM_TXOICR_TXOICR_CLR_MSK 0xfffffffe
2444
2445
#define ALT_SPIM_TXOICR_TXOICR_RESET 0x0
2446
2447
#define ALT_SPIM_TXOICR_TXOICR_GET(value) (((value) & 0x00000001) >> 0)
2448
2449
#define ALT_SPIM_TXOICR_TXOICR_SET(value) (((value) << 0) & 0x00000001)
2450
2451
#ifndef __ASSEMBLY__
2452
2462
struct
ALT_SPIM_TXOICR_s
2463
{
2464
const
uint32_t
txoicr
: 1;
2465
uint32_t : 31;
2466
};
2467
2469
typedef
volatile
struct
ALT_SPIM_TXOICR_s
ALT_SPIM_TXOICR_t
;
2470
#endif
/* __ASSEMBLY__ */
2471
2473
#define ALT_SPIM_TXOICR_OFST 0x38
2474
2475
#define ALT_SPIM_TXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_TXOICR_OFST))
2476
2500
#define ALT_SPIM_RXOICR_RXOICR_LSB 0
2501
2502
#define ALT_SPIM_RXOICR_RXOICR_MSB 0
2503
2504
#define ALT_SPIM_RXOICR_RXOICR_WIDTH 1
2505
2506
#define ALT_SPIM_RXOICR_RXOICR_SET_MSK 0x00000001
2507
2508
#define ALT_SPIM_RXOICR_RXOICR_CLR_MSK 0xfffffffe
2509
2510
#define ALT_SPIM_RXOICR_RXOICR_RESET 0x0
2511
2512
#define ALT_SPIM_RXOICR_RXOICR_GET(value) (((value) & 0x00000001) >> 0)
2513
2514
#define ALT_SPIM_RXOICR_RXOICR_SET(value) (((value) << 0) & 0x00000001)
2515
2516
#ifndef __ASSEMBLY__
2517
2527
struct
ALT_SPIM_RXOICR_s
2528
{
2529
const
uint32_t
rxoicr
: 1;
2530
uint32_t : 31;
2531
};
2532
2534
typedef
volatile
struct
ALT_SPIM_RXOICR_s
ALT_SPIM_RXOICR_t
;
2535
#endif
/* __ASSEMBLY__ */
2536
2538
#define ALT_SPIM_RXOICR_OFST 0x3c
2539
2540
#define ALT_SPIM_RXOICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXOICR_OFST))
2541
2565
#define ALT_SPIM_RXUICR_RXUICR_LSB 0
2566
2567
#define ALT_SPIM_RXUICR_RXUICR_MSB 0
2568
2569
#define ALT_SPIM_RXUICR_RXUICR_WIDTH 1
2570
2571
#define ALT_SPIM_RXUICR_RXUICR_SET_MSK 0x00000001
2572
2573
#define ALT_SPIM_RXUICR_RXUICR_CLR_MSK 0xfffffffe
2574
2575
#define ALT_SPIM_RXUICR_RXUICR_RESET 0x0
2576
2577
#define ALT_SPIM_RXUICR_RXUICR_GET(value) (((value) & 0x00000001) >> 0)
2578
2579
#define ALT_SPIM_RXUICR_RXUICR_SET(value) (((value) << 0) & 0x00000001)
2580
2581
#ifndef __ASSEMBLY__
2582
2592
struct
ALT_SPIM_RXUICR_s
2593
{
2594
const
uint32_t
rxuicr
: 1;
2595
uint32_t : 31;
2596
};
2597
2599
typedef
volatile
struct
ALT_SPIM_RXUICR_s
ALT_SPIM_RXUICR_t
;
2600
#endif
/* __ASSEMBLY__ */
2601
2603
#define ALT_SPIM_RXUICR_OFST 0x40
2604
2605
#define ALT_SPIM_RXUICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RXUICR_OFST))
2606
2631
#define ALT_SPIM_ICR_ICR_LSB 0
2632
2633
#define ALT_SPIM_ICR_ICR_MSB 0
2634
2635
#define ALT_SPIM_ICR_ICR_WIDTH 1
2636
2637
#define ALT_SPIM_ICR_ICR_SET_MSK 0x00000001
2638
2639
#define ALT_SPIM_ICR_ICR_CLR_MSK 0xfffffffe
2640
2641
#define ALT_SPIM_ICR_ICR_RESET 0x0
2642
2643
#define ALT_SPIM_ICR_ICR_GET(value) (((value) & 0x00000001) >> 0)
2644
2645
#define ALT_SPIM_ICR_ICR_SET(value) (((value) << 0) & 0x00000001)
2646
2647
#ifndef __ASSEMBLY__
2648
2658
struct
ALT_SPIM_ICR_s
2659
{
2660
const
uint32_t
icr
: 1;
2661
uint32_t : 31;
2662
};
2663
2665
typedef
volatile
struct
ALT_SPIM_ICR_s
ALT_SPIM_ICR_t
;
2666
#endif
/* __ASSEMBLY__ */
2667
2669
#define ALT_SPIM_ICR_OFST 0x48
2670
2671
#define ALT_SPIM_ICR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_ICR_OFST))
2672
2707
#define ALT_SPIM_DMACR_RDMAE_E_DISD 0x0
2708
2713
#define ALT_SPIM_DMACR_RDMAE_E_END 0x1
2714
2716
#define ALT_SPIM_DMACR_RDMAE_LSB 0
2717
2718
#define ALT_SPIM_DMACR_RDMAE_MSB 0
2719
2720
#define ALT_SPIM_DMACR_RDMAE_WIDTH 1
2721
2722
#define ALT_SPIM_DMACR_RDMAE_SET_MSK 0x00000001
2723
2724
#define ALT_SPIM_DMACR_RDMAE_CLR_MSK 0xfffffffe
2725
2726
#define ALT_SPIM_DMACR_RDMAE_RESET 0x0
2727
2728
#define ALT_SPIM_DMACR_RDMAE_GET(value) (((value) & 0x00000001) >> 0)
2729
2730
#define ALT_SPIM_DMACR_RDMAE_SET(value) (((value) << 0) & 0x00000001)
2731
2752
#define ALT_SPIM_DMACR_TDMAE_E_DISD 0x0
2753
2758
#define ALT_SPIM_DMACR_TDMAE_E_END 0x1
2759
2761
#define ALT_SPIM_DMACR_TDMAE_LSB 1
2762
2763
#define ALT_SPIM_DMACR_TDMAE_MSB 1
2764
2765
#define ALT_SPIM_DMACR_TDMAE_WIDTH 1
2766
2767
#define ALT_SPIM_DMACR_TDMAE_SET_MSK 0x00000002
2768
2769
#define ALT_SPIM_DMACR_TDMAE_CLR_MSK 0xfffffffd
2770
2771
#define ALT_SPIM_DMACR_TDMAE_RESET 0x0
2772
2773
#define ALT_SPIM_DMACR_TDMAE_GET(value) (((value) & 0x00000002) >> 1)
2774
2775
#define ALT_SPIM_DMACR_TDMAE_SET(value) (((value) << 1) & 0x00000002)
2776
2777
#ifndef __ASSEMBLY__
2778
2788
struct
ALT_SPIM_DMACR_s
2789
{
2790
uint32_t
rdmae
: 1;
2791
uint32_t
tdmae
: 1;
2792
uint32_t : 30;
2793
};
2794
2796
typedef
volatile
struct
ALT_SPIM_DMACR_s
ALT_SPIM_DMACR_t
;
2797
#endif
/* __ASSEMBLY__ */
2798
2800
#define ALT_SPIM_DMACR_OFST 0x4c
2801
2802
#define ALT_SPIM_DMACR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMACR_OFST))
2803
2829
#define ALT_SPIM_DMATDLR_DMATDL_LSB 0
2830
2831
#define ALT_SPIM_DMATDLR_DMATDL_MSB 7
2832
2833
#define ALT_SPIM_DMATDLR_DMATDL_WIDTH 8
2834
2835
#define ALT_SPIM_DMATDLR_DMATDL_SET_MSK 0x000000ff
2836
2837
#define ALT_SPIM_DMATDLR_DMATDL_CLR_MSK 0xffffff00
2838
2839
#define ALT_SPIM_DMATDLR_DMATDL_RESET 0x0
2840
2841
#define ALT_SPIM_DMATDLR_DMATDL_GET(value) (((value) & 0x000000ff) >> 0)
2842
2843
#define ALT_SPIM_DMATDLR_DMATDL_SET(value) (((value) << 0) & 0x000000ff)
2844
2845
#ifndef __ASSEMBLY__
2846
2856
struct
ALT_SPIM_DMATDLR_s
2857
{
2858
uint32_t
dmatdl
: 8;
2859
uint32_t : 24;
2860
};
2861
2863
typedef
volatile
struct
ALT_SPIM_DMATDLR_s
ALT_SPIM_DMATDLR_t
;
2864
#endif
/* __ASSEMBLY__ */
2865
2867
#define ALT_SPIM_DMATDLR_OFST 0x50
2868
2869
#define ALT_SPIM_DMATDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMATDLR_OFST))
2870
2896
#define ALT_SPIM_DMARDLR_DMARDL_LSB 0
2897
2898
#define ALT_SPIM_DMARDLR_DMARDL_MSB 7
2899
2900
#define ALT_SPIM_DMARDLR_DMARDL_WIDTH 8
2901
2902
#define ALT_SPIM_DMARDLR_DMARDL_SET_MSK 0x000000ff
2903
2904
#define ALT_SPIM_DMARDLR_DMARDL_CLR_MSK 0xffffff00
2905
2906
#define ALT_SPIM_DMARDLR_DMARDL_RESET 0x0
2907
2908
#define ALT_SPIM_DMARDLR_DMARDL_GET(value) (((value) & 0x000000ff) >> 0)
2909
2910
#define ALT_SPIM_DMARDLR_DMARDL_SET(value) (((value) << 0) & 0x000000ff)
2911
2912
#ifndef __ASSEMBLY__
2913
2923
struct
ALT_SPIM_DMARDLR_s
2924
{
2925
uint32_t
dmardl
: 8;
2926
uint32_t : 24;
2927
};
2928
2930
typedef
volatile
struct
ALT_SPIM_DMARDLR_s
ALT_SPIM_DMARDLR_t
;
2931
#endif
/* __ASSEMBLY__ */
2932
2934
#define ALT_SPIM_DMARDLR_OFST 0x54
2935
2936
#define ALT_SPIM_DMARDLR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DMARDLR_OFST))
2937
2959
#define ALT_SPIM_IDR_IDR_LSB 0
2960
2961
#define ALT_SPIM_IDR_IDR_MSB 31
2962
2963
#define ALT_SPIM_IDR_IDR_WIDTH 32
2964
2965
#define ALT_SPIM_IDR_IDR_SET_MSK 0xffffffff
2966
2967
#define ALT_SPIM_IDR_IDR_CLR_MSK 0x00000000
2968
2969
#define ALT_SPIM_IDR_IDR_RESET 0x5510000
2970
2971
#define ALT_SPIM_IDR_IDR_GET(value) (((value) & 0xffffffff) >> 0)
2972
2973
#define ALT_SPIM_IDR_IDR_SET(value) (((value) << 0) & 0xffffffff)
2974
2975
#ifndef __ASSEMBLY__
2976
2986
struct
ALT_SPIM_IDR_s
2987
{
2988
const
uint32_t
idr
: 32;
2989
};
2990
2992
typedef
volatile
struct
ALT_SPIM_IDR_s
ALT_SPIM_IDR_t
;
2993
#endif
/* __ASSEMBLY__ */
2994
2996
#define ALT_SPIM_IDR_OFST 0x58
2997
2998
#define ALT_SPIM_IDR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_IDR_OFST))
2999
3022
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_LSB 0
3023
3024
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_MSB 31
3025
3026
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_WIDTH 32
3027
3028
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET_MSK 0xffffffff
3029
3030
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_CLR_MSK 0x00000000
3031
3032
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_RESET 0x3332302a
3033
3034
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_GET(value) (((value) & 0xffffffff) >> 0)
3035
3036
#define ALT_SPIM_SPI_VER_ID_SPI_VER_ID_SET(value) (((value) << 0) & 0xffffffff)
3037
3038
#ifndef __ASSEMBLY__
3039
3049
struct
ALT_SPIM_SPI_VER_ID_s
3050
{
3051
uint32_t
spi_version_id
: 32;
3052
};
3053
3055
typedef
volatile
struct
ALT_SPIM_SPI_VER_ID_s
ALT_SPIM_SPI_VER_ID_t
;
3056
#endif
/* __ASSEMBLY__ */
3057
3059
#define ALT_SPIM_SPI_VER_ID_OFST 0x5c
3060
3061
#define ALT_SPIM_SPI_VER_ID_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_SPI_VER_ID_OFST))
3062
3097
#define ALT_SPIM_DR_DR_LSB 0
3098
3099
#define ALT_SPIM_DR_DR_MSB 15
3100
3101
#define ALT_SPIM_DR_DR_WIDTH 16
3102
3103
#define ALT_SPIM_DR_DR_SET_MSK 0x0000ffff
3104
3105
#define ALT_SPIM_DR_DR_CLR_MSK 0xffff0000
3106
3107
#define ALT_SPIM_DR_DR_RESET 0x0
3108
3109
#define ALT_SPIM_DR_DR_GET(value) (((value) & 0x0000ffff) >> 0)
3110
3111
#define ALT_SPIM_DR_DR_SET(value) (((value) << 0) & 0x0000ffff)
3112
3113
#ifndef __ASSEMBLY__
3114
3124
struct
ALT_SPIM_DR_s
3125
{
3126
uint32_t
dr
: 16;
3127
uint32_t : 16;
3128
};
3129
3131
typedef
volatile
struct
ALT_SPIM_DR_s
ALT_SPIM_DR_t
;
3132
#endif
/* __ASSEMBLY__ */
3133
3135
#define ALT_SPIM_DR_OFST 0x60
3136
3137
#define ALT_SPIM_DR_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_DR_OFST))
3138
3168
#define ALT_SPIM_RX_SMPL_DLY_RSD_LSB 0
3169
3170
#define ALT_SPIM_RX_SMPL_DLY_RSD_MSB 6
3171
3172
#define ALT_SPIM_RX_SMPL_DLY_RSD_WIDTH 7
3173
3174
#define ALT_SPIM_RX_SMPL_DLY_RSD_SET_MSK 0x0000007f
3175
3176
#define ALT_SPIM_RX_SMPL_DLY_RSD_CLR_MSK 0xffffff80
3177
3178
#define ALT_SPIM_RX_SMPL_DLY_RSD_RESET 0x0
3179
3180
#define ALT_SPIM_RX_SMPL_DLY_RSD_GET(value) (((value) & 0x0000007f) >> 0)
3181
3182
#define ALT_SPIM_RX_SMPL_DLY_RSD_SET(value) (((value) << 0) & 0x0000007f)
3183
3184
#ifndef __ASSEMBLY__
3185
3195
struct
ALT_SPIM_RX_SMPL_DLY_s
3196
{
3197
uint32_t
rsd
: 7;
3198
uint32_t : 25;
3199
};
3200
3202
typedef
volatile
struct
ALT_SPIM_RX_SMPL_DLY_s
ALT_SPIM_RX_SMPL_DLY_t
;
3203
#endif
/* __ASSEMBLY__ */
3204
3206
#define ALT_SPIM_RX_SMPL_DLY_OFST 0xf0
3207
3208
#define ALT_SPIM_RX_SMPL_DLY_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_SPIM_RX_SMPL_DLY_OFST))
3209
3210
#ifndef __ASSEMBLY__
3211
3221
struct
ALT_SPIM_s
3222
{
3223
volatile
ALT_SPIM_CTLR0_t
ctrlr0
;
3224
volatile
ALT_SPIM_CTLR1_t
ctrlr1
;
3225
volatile
ALT_SPIM_SPIENR_t
spienr
;
3226
volatile
ALT_SPIM_MWCR_t
mwcr
;
3227
volatile
ALT_SPIM_SER_t
ser
;
3228
volatile
ALT_SPIM_BAUDR_t
baudr
;
3229
volatile
ALT_SPIM_TXFTLR_t
txftlr
;
3230
volatile
ALT_SPIM_RXFTLR_t
rxftlr
;
3231
volatile
ALT_SPIM_TXFLR_t
txflr
;
3232
volatile
ALT_SPIM_RXFLR_t
rxflr
;
3233
volatile
ALT_SPIM_SR_t
sr
;
3234
volatile
ALT_SPIM_IMR_t
imr
;
3235
volatile
ALT_SPIM_ISR_t
isr
;
3236
volatile
ALT_SPIM_RISR_t
risr
;
3237
volatile
ALT_SPIM_TXOICR_t
txoicr
;
3238
volatile
ALT_SPIM_RXOICR_t
rxoicr
;
3239
volatile
ALT_SPIM_RXUICR_t
rxuicr
;
3240
volatile
uint32_t
_pad_0x44_0x47
;
3241
volatile
ALT_SPIM_ICR_t
icr
;
3242
volatile
ALT_SPIM_DMACR_t
dmacr
;
3243
volatile
ALT_SPIM_DMATDLR_t
dmatdlr
;
3244
volatile
ALT_SPIM_DMARDLR_t
dmardlr
;
3245
volatile
ALT_SPIM_IDR_t
idr
;
3246
volatile
ALT_SPIM_SPI_VER_ID_t
spi_version_id
;
3247
volatile
ALT_SPIM_DR_t
dr
;
3248
volatile
uint32_t
_pad_0x64_0xef
[35];
3249
volatile
ALT_SPIM_RX_SMPL_DLY_t
rx_sample_dly
;
3250
volatile
uint32_t
_pad_0xf4_0x100
[3];
3251
};
3252
3254
typedef
volatile
struct
ALT_SPIM_s
ALT_SPIM_t
;
3256
struct
ALT_SPIM_raw_s
3257
{
3258
volatile
uint32_t
ctrlr0
;
3259
volatile
uint32_t
ctrlr1
;
3260
volatile
uint32_t
spienr
;
3261
volatile
uint32_t
mwcr
;
3262
volatile
uint32_t
ser
;
3263
volatile
uint32_t
baudr
;
3264
volatile
uint32_t
txftlr
;
3265
volatile
uint32_t
rxftlr
;
3266
volatile
uint32_t
txflr
;
3267
volatile
uint32_t
rxflr
;
3268
volatile
uint32_t
sr
;
3269
volatile
uint32_t
imr
;
3270
volatile
uint32_t
isr
;
3271
volatile
uint32_t
risr
;
3272
volatile
uint32_t
txoicr
;
3273
volatile
uint32_t
rxoicr
;
3274
volatile
uint32_t
rxuicr
;
3275
volatile
uint32_t
_pad_0x44_0x47
;
3276
volatile
uint32_t
icr
;
3277
volatile
uint32_t
dmacr
;
3278
volatile
uint32_t
dmatdlr
;
3279
volatile
uint32_t
dmardlr
;
3280
volatile
uint32_t
idr
;
3281
volatile
uint32_t
spi_version_id
;
3282
volatile
uint32_t
dr
;
3283
volatile
uint32_t
_pad_0x64_0xef
[35];
3284
volatile
uint32_t
rx_sample_dly
;
3285
volatile
uint32_t
_pad_0xf4_0x100
[3];
3286
};
3287
3289
typedef
volatile
struct
ALT_SPIM_raw_s
ALT_SPIM_raw_t
;
3290
#endif
/* __ASSEMBLY__ */
3291
3293
#ifdef __cplusplus
3294
}
3295
#endif
/* __cplusplus */
3296
#endif
/* __ALTERA_ALT_SPIM_H__ */
3297
include
soc_cv_av
socal
alt_spim.h
Generated on Tue Sep 8 2015 13:28:44 for Altera SoCAL by
1.8.2