Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : mpu_set_l1_parity

Description

Parity status set bit.

A write to 1 of a specific bit sets the curresponding parity status bit.

This register is used only to check the specific ISR routine.

A read of this register should not return an error, but the actual read value is undefined.

[17] CPU1 SCU parity error

[16] CPU0 SCU parity error

[15] CPU1 BTAC parity error

[14] CPU1 GHB parity error

[13] CPU1 instruction tag RAM parity error

[12] CPU1 instruction data RAM parity error

[11] CPU1 main TLB parity error

[10] CPU1 data outer RAM parity error

[9] CPU1 data tag RAM parity error

[8] CPU1 data data RAM parity error.

[7] CPU0 BTAC parity error

[6] CPU0 GHB parity error

[5] CPU0 instruction tag RAM parity error

[4] CPU0 instruction data RAM parity error

[3] CPU0 main TLB parity error

[2] CPU0 data outer RAM parity error

[1] CPU0 data tag RAM parity error

[0] CPU0 data data RAM parity error.

Register Layout

Bits Access Reset Description
[7:0] RW 0x0 ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0
[15:8] RW 0x0 ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1
[17:16] RW 0x0 ALT_SYSMGR_MPU_SET_L1_PARITY_SCU
[31:18] ??? 0x0 UNDEFINED

Field : cpu0

CPU0 L1 parity interrupt set. Write 1 to Set

Field Access Macros:

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_LSB   0
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_MSB   7
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_WIDTH   8
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET_MSK   0x000000ff
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_CLR_MSK   0xffffff00
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_RESET   0x0
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_GET(value)   (((value) & 0x000000ff) >> 0)
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET(value)   (((value) << 0) & 0x000000ff)
 

Field : cpu1

CPU1 L1 parity interrupt set. Write 1 to Set

Field Access Macros:

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_LSB   8
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_MSB   15
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_WIDTH   8
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET_MSK   0x0000ff00
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_CLR_MSK   0xffff00ff
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_RESET   0x0
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_GET(value)   (((value) & 0x0000ff00) >> 8)
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET(value)   (((value) << 8) & 0x0000ff00)
 

Field : scu

SCU parity interrupt set. Write 1 to Set

Field Access Macros:

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_LSB   16
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_MSB   17
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_WIDTH   2
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET_MSK   0x00030000
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_CLR_MSK   0xfffcffff
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_RESET   0x0
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_GET(value)   (((value) & 0x00030000) >> 16)
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET(value)   (((value) << 16) & 0x00030000)
 

Data Structures

struct  ALT_SYSMGR_MPU_SET_L1_PARITY_s
 

Macros

#define ALT_SYSMGR_MPU_SET_L1_PARITY_RESET   0x00000000
 
#define ALT_SYSMGR_MPU_SET_L1_PARITY_OFST   0xb4
 

Typedefs

typedef struct
ALT_SYSMGR_MPU_SET_L1_PARITY_s 
ALT_SYSMGR_MPU_SET_L1_PARITY_t
 

Data Structure Documentation

struct ALT_SYSMGR_MPU_SET_L1_PARITY_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_SYSMGR_MPU_SET_L1_PARITY.

Data Fields
uint32_t cpu0: 8 ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0
uint32_t cpu1: 8 ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1
uint32_t scu: 2 ALT_SYSMGR_MPU_SET_L1_PARITY_SCU
uint32_t __pad0__: 14 UNDEFINED

Macro Definitions

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_LSB   0

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_MSB   7

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_WIDTH   8

The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET_MSK   0x000000ff

The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_CLR_MSK   0xffffff00

The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_GET (   value)    (((value) & 0x000000ff) >> 0)

Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 field value from a register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0_SET (   value)    (((value) << 0) & 0x000000ff)

Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_CPU0 register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_LSB   8

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_MSB   15

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_WIDTH   8

The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET_MSK   0x0000ff00

The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_CLR_MSK   0xffff00ff

The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_GET (   value)    (((value) & 0x0000ff00) >> 8)

Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 field value from a register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1_SET (   value)    (((value) << 8) & 0x0000ff00)

Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_CPU1 register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_LSB   16

The Least Significant Bit (LSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_MSB   17

The Most Significant Bit (MSB) position of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_WIDTH   2

The width in bits of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET_MSK   0x00030000

The mask used to set the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_CLR_MSK   0xfffcffff

The mask used to clear the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_RESET   0x0

The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_GET (   value)    (((value) & 0x00030000) >> 16)

Extracts the ALT_SYSMGR_MPU_SET_L1_PARITY_SCU field value from a register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_SCU_SET (   value)    (((value) << 16) & 0x00030000)

Produces a ALT_SYSMGR_MPU_SET_L1_PARITY_SCU register field value suitable for setting the register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_RESET   0x00000000

The reset value of the ALT_SYSMGR_MPU_SET_L1_PARITY register.

#define ALT_SYSMGR_MPU_SET_L1_PARITY_OFST   0xb4

The byte offset of the ALT_SYSMGR_MPU_SET_L1_PARITY register from the beginning of the component.

Typedef Documentation