Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : dramtiming0

Description

Register Layout

Bits Access Reset Description
[6:0] RW 0x0 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL
[12:7] RW 0x0 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES
[18:13] RW 0x0 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES
[31:19] ??? 0x0 UNDEFINED

Field : cfg_tcl

Memory read latency.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_LSB   0
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_MSB   6
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_WIDTH   7
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET_MSK   0x0000007f
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_CLR_MSK   0xffffff80
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_GET(value)   (((value) & 0x0000007f) >> 0)
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET(value)   (((value) << 0) & 0x0000007f)
 

Field : cfg_power_saving_exit_cycles

The minimum number of cycles to stay in a low power state. This applies to both power down and self-refresh and should be set to the greater of tPD and tCKESR.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB   7
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB   12
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK   0x00001f80
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK   0xffffe07f
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET(value)   (((value) & 0x00001f80) >> 7)
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET(value)   (((value) << 7) & 0x00001f80)
 

Field : cfg_mem_clk_disable_entry_cycles

Set to a the number of clocks after the execution of an self-refresh to stop the clock. This register is generally set based on PHY design latency and should generally not be changed.

Field Access Macros:

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_LSB   13
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_MSB   18
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_WIDTH   6
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET_MSK   0x0007e000
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_CLR_MSK   0xfff81fff
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_RESET   0x0
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_GET(value)   (((value) & 0x0007e000) >> 13)
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET(value)   (((value) << 13) & 0x0007e000)
 

Data Structures

struct  ALT_IO48_HMC_MMR_DRAMTIMING0_s
 

Macros

#define ALT_IO48_HMC_MMR_DRAMTIMING0_RESET   0x00000000
 
#define ALT_IO48_HMC_MMR_DRAMTIMING0_OFST   0x50
 

Typedefs

typedef struct
ALT_IO48_HMC_MMR_DRAMTIMING0_s 
ALT_IO48_HMC_MMR_DRAMTIMING0_t
 

Data Structure Documentation

struct ALT_IO48_HMC_MMR_DRAMTIMING0_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_IO48_HMC_MMR_DRAMTIMING0.

Data Fields
uint32_t cfg_tcl: 7 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL
uint32_t cfg_power_saving_exit_cycles: 6 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES
uint32_t cfg_mem_clk_disable_entry_cycles: 6 ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES
uint32_t __pad0__: 13 UNDEFINED

Macro Definitions

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_LSB   0

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_MSB   6

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_WIDTH   7

The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET_MSK   0x0000007f

The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_CLR_MSK   0xffffff80

The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_GET (   value)    (((value) & 0x0000007f) >> 0)

Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL field value from a register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL_SET (   value)    (((value) << 0) & 0x0000007f)

Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_TCL register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_LSB   7

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_MSB   12

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET_MSK   0x00001f80

The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_CLR_MSK   0xffffe07f

The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_GET (   value)    (((value) & 0x00001f80) >> 7)

Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES field value from a register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES_SET (   value)    (((value) << 7) & 0x00001f80)

Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_POWER_SAVING_EXIT_CYCLES register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_LSB   13

The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_MSB   18

The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_WIDTH   6

The width in bits of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET_MSK   0x0007e000

The mask used to set the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_CLR_MSK   0xfff81fff

The mask used to clear the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_RESET   0x0

The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_GET (   value)    (((value) & 0x0007e000) >> 13)

Extracts the ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES field value from a register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES_SET (   value)    (((value) << 13) & 0x0007e000)

Produces a ALT_IO48_HMC_MMR_DRAMTIMING0_CFG_MEM_CLK_DIS_ENTRY_CYCLES register field value suitable for setting the register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_RESET   0x00000000

The reset value of the ALT_IO48_HMC_MMR_DRAMTIMING0 register.

#define ALT_IO48_HMC_MMR_DRAMTIMING0_OFST   0x50

The byte offset of the ALT_IO48_HMC_MMR_DRAMTIMING0 register from the beginning of the component.

Typedef Documentation