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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 448 (Timestamp Control Register)
This register controls the operation of the System Time generator and the processing of PTP packets for timestamping in the Receiver.
Note:
Register Layout
Field : tsena | |
Timestamp Enable When set, the timestamp is added for the transmit and receive frames. When disabled, timestamp is not added for the transmit and receive frames and the Timestamp Generator is also suspended. You need to initialize the Timestamp (system time) after enabling this mode. On the receive side, the MAC processes the 1588 frames only if this bit is set. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_LSB 0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_MSB 0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_TS_CTL_TSENA_SET(value) (((value) << 0) & 0x00000001) |
Field : tscfupdt | |
Timestamp Fine or Coarse Update When set, this bit indicates that the system times update should be done using the fine update method. When reset, it indicates the system timestamp update should be done using the Coarse method. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK 0x00000002 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK 0xfffffffd |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET(value) (((value) << 1) & 0x00000002) |
Field : tsinit | |
Timestamp Initialize When set, the system time is initialized (overwritten) with the value specified in the Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the initialization is complete. The Timestamp Higher Word register (if enabled during core configuration) can only be initialized. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB 2 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB 2 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK 0x00000004 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK 0xfffffffb |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_EMAC_GMAC_TS_CTL_TSINIT_SET(value) (((value) << 2) & 0x00000004) |
Field : tsupdt | |
Timestamp Update When set, the system time is updated (added or subtracted) with the value specified in Register 452 (System Time - Seconds Update Register) and Register 453 (System Time - Nanoseconds Update Register). This bit should be read zero before updating it. This bit is reset when the update is completed in hardware. The Timestamp Higher Word register (if enabled during core configuration) is not updated. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB 3 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB 3 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET(value) (((value) << 3) & 0x00000008) |
Field : tstrig | |
Timestamp Interrupt Trigger Enable When set, the timestamp interrupt is generated when the System Time becomes greater than the value written in the Target Time register. This bit is reset after the generation of the Timestamp Trigger Interrupt. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB 4 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB 4 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK 0x00000010 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK 0xffffffef |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET(value) (((value) << 4) & 0x00000010) |
Field : tsaddreg | |
Addend Reg Update When set, the content of the Timestamp Addend register is updated in the PTP block for fine correction. This is cleared when the update is completed. This register bit should be zero before setting it. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB 5 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB 5 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK 0x00000020 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK 0xffffffdf |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET(value) (((value) & 0x00000020) >> 5) |
#define | ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET(value) (((value) << 5) & 0x00000020) |
Field : reserved_7_6 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_LSB 6 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_MSB 7 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_WIDTH 2 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET_MSK 0x000000c0 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_CLR_MSK 0xffffff3f |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_GET(value) (((value) & 0x000000c0) >> 6) |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET(value) (((value) << 6) & 0x000000c0) |
Field : tsenall | |
Enable Timestamp for All Frames When set, the timestamp snapshot is enabled for all frames received by the MAC. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB 8 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB 8 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK 0x00000100 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK 0xfffffeff |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_GET(value) (((value) & 0x00000100) >> 8) |
#define | ALT_EMAC_GMAC_TS_CTL_TSENALL_SET(value) (((value) << 8) & 0x00000100) |
Field : tsctrlssr | |
Timestamp Digital or Binary Rollover Control When set, the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments the timestamp (High) seconds. When reset, the rollover value of sub-second register is 0x7FFF_FFFF. The sub-second increment has to be programmed correctly depending on the PTP reference clock frequency and the value of this bit. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB 9 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB 9 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK 0x00000200 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK 0xfffffdff |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET(value) (((value) & 0x00000200) >> 9) |
#define | ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET(value) (((value) << 9) & 0x00000200) |
Field : tsver2ena | |
Enable PTP packet Processing for Version 2 Format When set, the PTP packets are processed using the 1588 version 2 format. Otherwise, the PTP packets are processed using the version 1 format. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB 10 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB 10 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK 0x00000400 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK 0xfffffbff |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET(value) (((value) & 0x00000400) >> 10) |
#define | ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET(value) (((value) << 10) & 0x00000400) |
Field : tsipena | |
Enable Processing of PTP over Ethernet Frames When set, the MAC receiver processes the PTP packets encapsulated directly in the Ethernet frames. When this bit is clear, the MAC ignores the PTP over Ethernet packets. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB 11 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB 11 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK 0x00000800 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK 0xfffff7ff |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET(value) (((value) & 0x00000800) >> 11) |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET(value) (((value) << 11) & 0x00000800) |
Field : tsipv6ena | |
Enable Processing of PTP Frames Sent Over IPv6-UDP When set, the MAC receiver processes PTP packets encapsulated in UDP over IPv6 packets. When this bit is clear, the MAC ignores the PTP transported over UDP- IPv6 packets. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB 12 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB 12 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK 0x00001000 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK 0xffffefff |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET(value) (((value) & 0x00001000) >> 12) |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET(value) (((value) << 12) & 0x00001000) |
Field : tsipv4ena | |
Enable Processing of PTP Frames Sent over IPv4-UDP When set, the MAC receiver processes the PTP packets encapsulated in UDP over IPv4 packets. When this bit is clear, the MAC ignores the PTP transported over UDP-IPv4 packets. This bit is set by default. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB 13 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB 13 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK 0x00002000 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK 0xffffdfff |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET(value) (((value) & 0x00002000) >> 13) |
#define | ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET(value) (((value) << 13) & 0x00002000) |
Field : tsevntena | |
Enable Timestamp Snapshot for Event Messages When set, the timestamp snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp). When reset, the snapshot is taken for all messages except Announce, Management, and Signaling. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB 14 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB 14 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK 0x00004000 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK 0xffffbfff |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET(value) (((value) & 0x00004000) >> 14) |
#define | ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET(value) (((value) << 14) & 0x00004000) |
Field : tsmstrena | |
Enable Snapshot for Messages Relevant to Master When set, the snapshot is taken only for the messages relevant to the master node. Otherwise, the snapshot is taken for the messages relevant to the slave node. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB 15 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB 15 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK 0x00008000 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK 0xffff7fff |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET(value) (((value) & 0x00008000) >> 15) |
#define | ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET(value) (((value) << 15) & 0x00008000) |
Field : snaptypsel | |
Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB 16 |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB 17 |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH 2 |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK 0x00030000 |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK 0xfffcffff |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET(value) (((value) & 0x00030000) >> 16) |
#define | ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET(value) (((value) << 16) & 0x00030000) |
Field : tsenmacaddr | |
Enable MAC address for PTP Frame Filtering When set, the DA MAC address (that matches any MAC Address register) is used to filter the PTP frames when PTP is directly sent over Ethernet. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD | 0x0 | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB 18 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB 18 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK 0x00040000 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK 0xfffbffff |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET(value) (((value) & 0x00040000) >> 18) |
#define | ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET(value) (((value) << 18) & 0x00040000) |
Field : reserved_23_19 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_LSB 19 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_MSB 23 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_WIDTH 5 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET_MSK 0x00f80000 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_CLR_MSK 0xff07ffff |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_GET(value) (((value) & 0x00f80000) >> 19) |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET(value) (((value) << 19) & 0x00f80000) |
Field : atsfc | |
Auxiliary Snapshot FIFO Clear When set, it resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high, auxiliary snapshots get stored in the FIFO. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB 24 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB 24 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK 0x01000000 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK 0xfeffffff |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_EMAC_GMAC_TS_CTL_ATSFC_SET(value) (((value) << 24) & 0x01000000) |
Field : atsen0 | |
Auxiliary Snapshot 0 Enable This field controls capturing the Auxiliary Snapshot Trigger 0. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[0] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD | 0x0 | ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB 25 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB 25 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK 0x02000000 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK 0xfdffffff |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET(value) (((value) << 25) & 0x02000000) |
Field : atsen1 | |
Auxiliary Snapshot 1 Enable This field controls capturing the Auxiliary Snapshot Trigger 1. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[1] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than two. Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_LSB 26 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_MSB 26 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET_MSK 0x04000000 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_CLR_MSK 0xfbffffff |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_GET(value) (((value) & 0x04000000) >> 26) |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET(value) (((value) << 26) & 0x04000000) |
Field : atsen2 | |
Auxiliary Snapshot 2 Enable This field controls capturing the Auxiliary Snapshot Trigger 2. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[2] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than three. Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_LSB 27 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_MSB 27 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET_MSK 0x08000000 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_CLR_MSK 0xf7ffffff |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_GET(value) (((value) & 0x08000000) >> 27) |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET(value) (((value) << 27) & 0x08000000) |
Field : atsen3 | |
Auxiliary Snapshot 3 Enable This field controls capturing the Auxiliary Snapshot Trigger 3. When this bit is set, the Auxiliary snapshot of event on ptp_aux_trig_i[3] input is enabled. When this bit is reset, the events on this input are ignored. This bit is reserved when the Add IEEE 1588 Auxiliary Snapshot option is not selected during core configuration or the selected number in the Number of IEEE 1588 Auxiliary Snapshot Inputs option is less than four. Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_LSB 28 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_MSB 28 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_WIDTH 1 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET_MSK 0x10000000 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_CLR_MSK 0xefffffff |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_GET(value) (((value) & 0x10000000) >> 28) |
#define | ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET(value) (((value) << 28) & 0x10000000) |
Field : reserved_31_29 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_LSB 29 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_MSB 31 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_WIDTH 3 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET_MSK 0xe0000000 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_CLR_MSK 0x1fffffff |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_RESET 0x0 |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_GET(value) (((value) & 0xe0000000) >> 29) |
#define | ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET(value) (((value) << 29) & 0xe0000000) |
Data Structures | |
struct | ALT_EMAC_GMAC_TS_CTL_s |
Macros | |
#define | ALT_EMAC_GMAC_TS_CTL_RESET 0x00002000 |
#define | ALT_EMAC_GMAC_TS_CTL_OFST 0x700 |
#define | ALT_EMAC_GMAC_TS_CTL_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_TS_CTL_s | ALT_EMAC_GMAC_TS_CTL_t |
struct ALT_EMAC_GMAC_TS_CTL_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_TS_CTL.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_NOTS 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
#define ALT_EMAC_GMAC_TS_CTL_TSENA_E_TS 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENA
#define ALT_EMAC_GMAC_TS_CTL_TSENA_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSENA_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_COARSE 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_E_TS_FINE 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCFUPDT
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET_MSK 0x00000002 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSCFUPDT field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSCFUPDT_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSCFUPDT register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_NOTS_INIT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_E_TS_INIT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSINIT
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET_MSK 0x00000004 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSINIT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSINIT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSINIT field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSINIT_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSINIT register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_NOTS_UPDATED 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_E_TS_UPDATED 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSUPDT
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSUPDT register field.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSUPDT field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSUPDT_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSUPDT register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_NOTS_INTR_TRIG_EN 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_E_TS_INTR_TRIG_EN 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSTRIG
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSTRIG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSTRIG field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSTRIG_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSTRIG register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_NOTS_ADDEND_UPDATED 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_E_TS_ADDEND_UPDATED 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSADDREG
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_MSB 5 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET_MSK 0x00000020 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_CLR_MSK 0xffffffdf |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSADDREG register field.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_GET | ( | value | ) | (((value) & 0x00000020) >> 5) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSADDREG field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSADDREG_SET | ( | value | ) | (((value) << 5) & 0x00000020) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSADDREG register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_LSB 6 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET_MSK 0x000000c0 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_CLR_MSK 0xffffff3f |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_GET | ( | value | ) | (((value) & 0x000000c0) >> 6) |
Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_7_6_SET | ( | value | ) | (((value) << 6) & 0x000000c0) |
Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_7_6 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENALL
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_MSB 8 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET_MSK 0x00000100 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_CLR_MSK 0xfffffeff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENALL register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENALL register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_GET | ( | value | ) | (((value) & 0x00000100) >> 8) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSENALL field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSENALL_SET | ( | value | ) | (((value) << 8) & 0x00000100) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSENALL register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_NOTS_LOW_ROLL_MAX 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_E_TS_LOW_ROLL_1NS 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSCTLSSR
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_LSB 9 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET_MSK 0x00000200 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_CLR_MSK 0xfffffdff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_GET | ( | value | ) | (((value) & 0x00000200) >> 9) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSCTLSSR field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSCTLSSR_SET | ( | value | ) | (((value) << 9) & 0x00000200) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSCTLSSR register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER1 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_E_PTP_1588_VER2 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSVER2ENA
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_MSB 10 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET_MSK 0x00000400 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_CLR_MSK 0xfffffbff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_GET | ( | value | ) | (((value) & 0x00000400) >> 10) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSVER2ENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSVER2ENA_SET | ( | value | ) | (((value) << 10) & 0x00000400) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSVER2ENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_NO_PROCESS_PTP 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_E_PROCESS_PTP 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_LSB 11 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_MSB 11 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET_MSK 0x00000800 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_CLR_MSK 0xfffff7ff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_GET | ( | value | ) | (((value) & 0x00000800) >> 11) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPENA_SET | ( | value | ) | (((value) << 11) & 0x00000800) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSIPENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_NO_PROCESS_PTP 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_E_PROCESS_PTP 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_LSB 12 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_MSB 12 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET_MSK 0x00001000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_CLR_MSK 0xffffefff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_GET | ( | value | ) | (((value) & 0x00001000) >> 12) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA_SET | ( | value | ) | (((value) << 12) & 0x00001000) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV6ENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_NO_PROCESS_PTP 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_E_PROCESS_PTP 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_LSB 13 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_MSB 13 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET_MSK 0x00002000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_CLR_MSK 0xffffdfff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_RESET 0x1 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_GET | ( | value | ) | (((value) & 0x00002000) >> 13) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA_SET | ( | value | ) | (((value) << 13) & 0x00002000) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSIPV4ENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSEVNTENA
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_LSB 14 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_MSB 14 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET_MSK 0x00004000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_CLR_MSK 0xffffbfff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_GET | ( | value | ) | (((value) & 0x00004000) >> 14) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSEVNTENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSEVNTENA_SET | ( | value | ) | (((value) << 14) & 0x00004000) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSEVNTENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_SLV 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_E_MST 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSMSTRENA
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_LSB 15 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET_MSK 0x00008000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_CLR_MSK 0xffff7fff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_GET | ( | value | ) | (((value) & 0x00008000) >> 15) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSMSTRENA field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSMSTRENA_SET | ( | value | ) | (((value) << 15) & 0x00008000) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSMSTRENA register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_MSB 17 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET_MSK 0x00030000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_CLR_MSK 0xfffcffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_GET | ( | value | ) | (((value) & 0x00030000) >> 16) |
Extracts the ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL_SET | ( | value | ) | (((value) << 16) & 0x00030000) |
Produces a ALT_EMAC_GMAC_TS_CTL_SNAPTYPSEL register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_TSENMACADDR
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_LSB 18 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET_MSK 0x00040000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_CLR_MSK 0xfffbffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_GET | ( | value | ) | (((value) & 0x00040000) >> 18) |
Extracts the ALT_EMAC_GMAC_TS_CTL_TSENMACADDR field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_TSENMACADDR_SET | ( | value | ) | (((value) << 18) & 0x00040000) |
Produces a ALT_EMAC_GMAC_TS_CTL_TSENMACADDR register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_WIDTH 5 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET_MSK 0x00f80000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_CLR_MSK 0xff07ffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_GET | ( | value | ) | (((value) & 0x00f80000) >> 19) |
Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_23_19_SET | ( | value | ) | (((value) << 19) & 0x00f80000) |
Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_23_19 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSFC
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSFC register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSFC register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_GMAC_TS_CTL_ATSFC field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_ATSFC_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_ATSFC register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_TS_CTL_ATSEN0
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN0 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN0_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN0 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_MSB 26 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET_MSK 0x04000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_CLR_MSK 0xfbffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_GET | ( | value | ) | (((value) & 0x04000000) >> 26) |
Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN1 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN1_SET | ( | value | ) | (((value) << 26) & 0x04000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN1 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_LSB 27 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_MSB 27 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET_MSK 0x08000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_CLR_MSK 0xf7ffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_GET | ( | value | ) | (((value) & 0x08000000) >> 27) |
Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN2 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN2_SET | ( | value | ) | (((value) << 27) & 0x08000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN2 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_LSB 28 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_MSB 28 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET_MSK 0x10000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_CLR_MSK 0xefffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_GET | ( | value | ) | (((value) & 0x10000000) >> 28) |
Extracts the ALT_EMAC_GMAC_TS_CTL_ATSEN3 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_ATSEN3_SET | ( | value | ) | (((value) << 28) & 0x10000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_ATSEN3 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_LSB 29 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_WIDTH 3 |
The width in bits of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET_MSK 0xe0000000 |
The mask used to set the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_CLR_MSK 0x1fffffff |
The mask used to clear the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_GET | ( | value | ) | (((value) & 0xe0000000) >> 29) |
Extracts the ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 field value from a register.
#define ALT_EMAC_GMAC_TS_CTL_RSVD_31_29_SET | ( | value | ) | (((value) << 29) & 0xe0000000) |
Produces a ALT_EMAC_GMAC_TS_CTL_RSVD_31_29 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_TS_CTL_RESET 0x00002000 |
The reset value of the ALT_EMAC_GMAC_TS_CTL register.
#define ALT_EMAC_GMAC_TS_CTL_OFST 0x700 |
The byte offset of the ALT_EMAC_GMAC_TS_CTL register from the beginning of the component.
#define ALT_EMAC_GMAC_TS_CTL_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_TS_CTL_OFST)) |
The address of the ALT_EMAC_GMAC_TS_CTL register.
typedef struct ALT_EMAC_GMAC_TS_CTL_s ALT_EMAC_GMAC_TS_CTL_t |
The typedef declaration for register ALT_EMAC_GMAC_TS_CTL.