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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN |
[1] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV |
[2] | RW | 0x0 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN |
[31:3] | ??? | 0x0 | UNDEFINED |
Field : cfg_3ds_en | |
Setting to 1 to enable #DS support for DDR4 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_LSB 0 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_MSB 0 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET_MSK 0x00000001 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET(value) (((value) << 0) & 0x00000001) |
Field : cfg_ck_inv | |
Use to program CK polarity. 1 Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_LSB 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_MSB 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET_MSK 0x00000002 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_GET(value) (((value) & 0x00000002) >> 1) |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET(value) (((value) << 1) & 0x00000002) |
Field : cfg_addr_mplx_en | |
Setting to 1 enables RLD3 address mulplex mode Field Access Macros: | |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_LSB 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_MSB 2 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_WIDTH 1 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET_MSK 0x00000004 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_CLR_MSK 0xfffffffb |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_RESET 0x0 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_GET(value) (((value) & 0x00000004) >> 2) |
#define | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET(value) (((value) << 2) & 0x00000004) |
Data Structures | |
struct | ALT_IO48_HMC_MMR_CTLCFG8_s |
Macros | |
#define | ALT_IO48_HMC_MMR_CTLCFG8_RESET 0x00000000 |
#define | ALT_IO48_HMC_MMR_CTLCFG8_OFST 0x48 |
Typedefs | |
typedef struct ALT_IO48_HMC_MMR_CTLCFG8_s | ALT_IO48_HMC_MMR_CTLCFG8_t |
struct ALT_IO48_HMC_MMR_CTLCFG8_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_IO48_HMC_MMR_CTLCFG8.
Data Fields | ||
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uint32_t | cfg_3ds_en: 1 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN |
uint32_t | cfg_ck_inv: 1 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV |
uint32_t | cfg_addr_mplx_en: 1 | ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN |
uint32_t | __pad0__: 29 | UNDEFINED |
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET_MSK 0x00000001 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_3DS_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_MSB 1 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET_MSK 0x00000002 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_CLR_MSK 0xfffffffd |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_GET | ( | value | ) | (((value) & 0x00000002) >> 1) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV_SET | ( | value | ) | (((value) << 1) & 0x00000002) |
Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_CK_INV register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_LSB 2 |
The Least Significant Bit (LSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_WIDTH 1 |
The width in bits of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET_MSK 0x00000004 |
The mask used to set the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_CLR_MSK 0xfffffffb |
The mask used to clear the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_RESET 0x0 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_GET | ( | value | ) | (((value) & 0x00000004) >> 2) |
Extracts the ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN field value from a register.
#define ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN_SET | ( | value | ) | (((value) << 2) & 0x00000004) |
Produces a ALT_IO48_HMC_MMR_CTLCFG8_CFG_ADDR_MPLX_EN register field value suitable for setting the register.
#define ALT_IO48_HMC_MMR_CTLCFG8_RESET 0x00000000 |
The reset value of the ALT_IO48_HMC_MMR_CTLCFG8 register.
#define ALT_IO48_HMC_MMR_CTLCFG8_OFST 0x48 |
The byte offset of the ALT_IO48_HMC_MMR_CTLCFG8 register from the beginning of the component.
typedef struct ALT_IO48_HMC_MMR_CTLCFG8_s ALT_IO48_HMC_MMR_CTLCFG8_t |
The typedef declaration for register ALT_IO48_HMC_MMR_CTLCFG8.