Altera SoCAL  16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register : ic_comp_param_1

Description

Name: Component Parameter Register 1

Size: 32 bits

Address Offset: 0xf4

Read/Write Access: Read

Note

This is a constant read-only register that contains

encoded information about the component's parameter settings.

The reset value depends on coreConsultant parameter(s).

Register Layout

Bits Access Reset Description
[1:0] R 0x2 ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
[3:2] R 0x2 ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
[4] R 0x0 ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
[5] R 0x1 ALT_I2C_COMP_PARAM_1_INTR_IO
[6] R 0x1 ALT_I2C_COMP_PARAM_1_HAS_DMA
[7] R 0x1 ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
[15:8] R 0x3f ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
[23:16] R 0x3f ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
[31:24] ??? 0x0 UNDEFINED

Field : apb_data_width

The value of this register is

derived from the APB_DATA_WIDTH coreConsultant

parameter.

0x0: 8 bits

0x1: 16 bits

0x2: 32 bits

0x3: Reserved

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS 0x2 APB Data Width is 32 Bits

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS   0x2
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB   0
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB   1
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH   2
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK   0x00000003
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK   0xfffffffc
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET   0x2
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET(value)   (((value) & 0x00000003) >> 0)
 
#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET(value)   (((value) << 0) & 0x00000003)
 

Field : max_speed_mode

The value of this register is

derived from the IC_MAX_SPEED_MODE coreConsultant

parameter.

0x0: Reserved

0x1: Standard

0x2: Fast

0x3: High

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST 0x2 Fast Mode (400 kbit/s)

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST   0x2
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB   2
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB   3
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH   2
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK   0x0000000c
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK   0xfffffff3
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET   0x2
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET(value)   (((value) & 0x0000000c) >> 2)
 
#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET(value)   (((value) << 2) & 0x0000000c)
 

Field : hc_count_values

The value of this register is

derived from the IC_HC_COUNT VALUES coreConsultant

parameter

0: False

1: True

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR 0x0 *CNT registers read/write

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR   0x0
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB   4
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB   4
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH   1
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK   0x00000010
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK   0xffffffef
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET   0x0
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET(value)   (((value) & 0x00000010) >> 4)
 
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET(value)   (((value) << 4) & 0x00000010)
 

Field : intr_io

The value of this register is

derived from the IC_INTR_IO coreConsultant

parameter

0: Individual

1: Combined

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED 0x1 Combined Interrupt Output

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED   0x1
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB   5
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB   5
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH   1
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK   0x00000020
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK   0xffffffdf
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET   0x1
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET(value)   (((value) & 0x00000020) >> 5)
 
#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET(value)   (((value) << 5) & 0x00000020)
 

Field : has_dma

The value of this register is

derived from the IC_HAS_DMA coreConsultant

parameter

0: False

1: True

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT 0x1 Has DMA

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT   0x1
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB   6
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB   6
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH   1
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK   0x00000040
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK   0xffffffbf
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET   0x1
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET(value)   (((value) & 0x00000040) >> 6)
 
#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET(value)   (((value) << 6) & 0x00000040)
 

Field : add_encoded_params

The value of this register is derived

from the IC_ADD_ENCODED_PARAMS coreConsultant

parameter.

Reading 1 in this bit means that the capability

of reading these encoded parameters via software has been

included. Otherwise, the entire register is 0 regardless of

the setting of any other parameters that are encoded in the

bits.

0: False

1: True

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS 0x1 Add Encoded Params

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS   0x1
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB   7
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB   7
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH   1
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK   0x00000080
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK   0xffffff7f
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET   0x1
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET(value)   (((value) & 0x00000080) >> 7)
 
#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET(value)   (((value) << 7) & 0x00000080)
 

Field : rx_buffer_depth

The value of this register is

derived from the IC_RX_BUFFER_DEPTH coreConsultant

parameter.

0x00: Reserved

0x01: 2

0x02: 3

to

0xFF: 256

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES 0x40 Rx Fifo Depth 64 Entries

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES   0x40
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB   8
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB   15
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH   8
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK   0x0000ff00
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK   0xffff00ff
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET   0x3f
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET(value)   (((value) & 0x0000ff00) >> 8)
 
#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET(value)   (((value) << 8) & 0x0000ff00)
 

Field : tx_buffer_depth

The value of this register is derived

from the IC_TX_BUFFER_DEPTH coreConsultant

parameter.

0x00 = Reserved

0x01 = 2

0x02 = 3

to

0xFF = 256

Field Enumeration Values:

Enum Value Description
ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES 0x40 Tx Buffer Depth 64 Entries

Field Access Macros:

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES   0x40
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB   16
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB   23
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH   8
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK   0x00ff0000
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK   0xff00ffff
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET   0x3f
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET(value)   (((value) & 0x00ff0000) >> 16)
 
#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET(value)   (((value) << 16) & 0x00ff0000)
 

Data Structures

struct  ALT_I2C_COMP_PARAM_1_s
 

Macros

#define ALT_I2C_COMP_PARAM_1_RESET   0x003f3fea
 
#define ALT_I2C_COMP_PARAM_1_OFST   0xf4
 
#define ALT_I2C_COMP_PARAM_1_ADDR(base)   ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))
 

Typedefs

typedef struct
ALT_I2C_COMP_PARAM_1_s 
ALT_I2C_COMP_PARAM_1_t
 

Data Structure Documentation

struct ALT_I2C_COMP_PARAM_1_s

WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.

The struct declaration for register ALT_I2C_COMP_PARAM_1.

Data Fields
const uint32_t apb_data_width: 2 ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH
const uint32_t max_speed_mode: 2 ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD
const uint32_t hc_count_values: 1 ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES
const uint32_t intr_io: 1 ALT_I2C_COMP_PARAM_1_INTR_IO
const uint32_t has_dma: 1 ALT_I2C_COMP_PARAM_1_HAS_DMA
const uint32_t add_encoded_params: 1 ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS
const uint32_t rx_buffer_depth: 8 ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH
const uint32_t tx_buffer_depth: 8 ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH
uint32_t __pad0__: 8 UNDEFINED

Macro Definitions

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_E_WIDTH32BITS   0x2

Enumerated value for register field ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH

APB Data Width is 32 Bits

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_LSB   0

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_MSB   1

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_WIDTH   2

The width in bits of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET_MSK   0x00000003

The mask used to set the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_CLR_MSK   0xfffffffc

The mask used to clear the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_RESET   0x2

The reset value of the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_GET (   value)    (((value) & 0x00000003) >> 0)

Extracts the ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH field value from a register.

#define ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH_SET (   value)    (((value) << 0) & 0x00000003)

Produces a ALT_I2C_COMP_PARAM_1_APB_DATA_WIDTH register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_E_FAST   0x2

Enumerated value for register field ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD

Fast Mode (400 kbit/s)

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_LSB   2

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_MSB   3

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_WIDTH   2

The width in bits of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET_MSK   0x0000000c

The mask used to set the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_CLR_MSK   0xfffffff3

The mask used to clear the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_RESET   0x2

The reset value of the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_GET (   value)    (((value) & 0x0000000c) >> 2)

Extracts the ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD field value from a register.

#define ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD_SET (   value)    (((value) << 2) & 0x0000000c)

Produces a ALT_I2C_COMP_PARAM_1_MAX_SPEED_MOD register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_E_RDWR   0x0

Enumerated value for register field ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES

  • CNT registers read/write
#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_LSB   4

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_MSB   4

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_WIDTH   1

The width in bits of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET_MSK   0x00000010

The mask used to set the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_CLR_MSK   0xffffffef

The mask used to clear the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_RESET   0x0

The reset value of the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_GET (   value)    (((value) & 0x00000010) >> 4)

Extracts the ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES field value from a register.

#define ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES_SET (   value)    (((value) << 4) & 0x00000010)

Produces a ALT_I2C_COMP_PARAM_1_HC_COUNT_VALUES register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_E_COMBINED   0x1

Enumerated value for register field ALT_I2C_COMP_PARAM_1_INTR_IO

Combined Interrupt Output

#define ALT_I2C_COMP_PARAM_1_INTR_IO_LSB   5

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_MSB   5

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_INTR_IO register field.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_WIDTH   1

The width in bits of the ALT_I2C_COMP_PARAM_1_INTR_IO register field.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET_MSK   0x00000020

The mask used to set the ALT_I2C_COMP_PARAM_1_INTR_IO register field value.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_CLR_MSK   0xffffffdf

The mask used to clear the ALT_I2C_COMP_PARAM_1_INTR_IO register field value.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_RESET   0x1

The reset value of the ALT_I2C_COMP_PARAM_1_INTR_IO register field.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_GET (   value)    (((value) & 0x00000020) >> 5)

Extracts the ALT_I2C_COMP_PARAM_1_INTR_IO field value from a register.

#define ALT_I2C_COMP_PARAM_1_INTR_IO_SET (   value)    (((value) << 5) & 0x00000020)

Produces a ALT_I2C_COMP_PARAM_1_INTR_IO register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_E_PRESENT   0x1

Enumerated value for register field ALT_I2C_COMP_PARAM_1_HAS_DMA

Has DMA

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_LSB   6

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_MSB   6

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_WIDTH   1

The width in bits of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET_MSK   0x00000040

The mask used to set the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_CLR_MSK   0xffffffbf

The mask used to clear the ALT_I2C_COMP_PARAM_1_HAS_DMA register field value.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_RESET   0x1

The reset value of the ALT_I2C_COMP_PARAM_1_HAS_DMA register field.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_GET (   value)    (((value) & 0x00000040) >> 6)

Extracts the ALT_I2C_COMP_PARAM_1_HAS_DMA field value from a register.

#define ALT_I2C_COMP_PARAM_1_HAS_DMA_SET (   value)    (((value) << 6) & 0x00000040)

Produces a ALT_I2C_COMP_PARAM_1_HAS_DMA register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_E_ADDENCPARAMS   0x1

Enumerated value for register field ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS

Add Encoded Params

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_LSB   7

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_MSB   7

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_WIDTH   1

The width in bits of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET_MSK   0x00000080

The mask used to set the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_CLR_MSK   0xffffff7f

The mask used to clear the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_RESET   0x1

The reset value of the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_GET (   value)    (((value) & 0x00000080) >> 7)

Extracts the ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS field value from a register.

#define ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS_SET (   value)    (((value) << 7) & 0x00000080)

Produces a ALT_I2C_COMP_PARAM_1_ADD_ENC_PARAMS register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_E_FIFO64BYTES   0x40

Enumerated value for register field ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH

Rx Fifo Depth 64 Entries

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_LSB   8

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_MSB   15

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_WIDTH   8

The width in bits of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET_MSK   0x0000ff00

The mask used to set the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_CLR_MSK   0xffff00ff

The mask used to clear the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_RESET   0x3f

The reset value of the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_GET (   value)    (((value) & 0x0000ff00) >> 8)

Extracts the ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH field value from a register.

#define ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH_SET (   value)    (((value) << 8) & 0x0000ff00)

Produces a ALT_I2C_COMP_PARAM_1_RX_BUF_DEPTH register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_E_FIFO64BYTES   0x40

Enumerated value for register field ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH

Tx Buffer Depth 64 Entries

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_LSB   16

The Least Significant Bit (LSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_MSB   23

The Most Significant Bit (MSB) position of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_WIDTH   8

The width in bits of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET_MSK   0x00ff0000

The mask used to set the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_CLR_MSK   0xff00ffff

The mask used to clear the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_RESET   0x3f

The reset value of the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_GET (   value)    (((value) & 0x00ff0000) >> 16)

Extracts the ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH field value from a register.

#define ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH_SET (   value)    (((value) << 16) & 0x00ff0000)

Produces a ALT_I2C_COMP_PARAM_1_TX_BUF_DEPTH register field value suitable for setting the register.

#define ALT_I2C_COMP_PARAM_1_RESET   0x003f3fea

The reset value of the ALT_I2C_COMP_PARAM_1 register.

#define ALT_I2C_COMP_PARAM_1_OFST   0xf4

The byte offset of the ALT_I2C_COMP_PARAM_1 register from the beginning of the component.

#define ALT_I2C_COMP_PARAM_1_ADDR (   base)    ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_I2C_COMP_PARAM_1_OFST))

The address of the ALT_I2C_COMP_PARAM_1 register.

Typedef Documentation

The typedef declaration for register ALT_I2C_COMP_PARAM_1.