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Altera SoCAL
16.0
The Altera SoC Abstraction Layer (SoCAL) API Reference Manual
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Register 9 (Debug Register)
The Debug register gives the status of all main modules of the transmit and receive data-paths and the FIFOs. An all-zero status indicates that the MAC is in idle state (and FIFOs are empty) and no activity is going on in the data- paths.
Note:
The reset values, given for the Debug register, are valid only if the following clocks are present during the reset operation:
Register Layout
Bits | Access | Reset | Description |
---|---|---|---|
[0] | R | 0x0 | ALT_EMAC_GMAC_DBG_RPESTS |
[2:1] | R | 0x0 | ALT_EMAC_GMAC_DBG_RFCFCSTS |
[3] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_3 |
[4] | R | 0x0 | ALT_EMAC_GMAC_DBG_RWCSTS |
[6:5] | R | 0x0 | ALT_EMAC_GMAC_DBG_RRCSTS |
[7] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_7 |
[9:8] | R | 0x0 | ALT_EMAC_GMAC_DBG_RXFSTS |
[15:10] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_15_10 |
[16] | R | 0x0 | ALT_EMAC_GMAC_DBG_TPESTS |
[18:17] | R | 0x0 | ALT_EMAC_GMAC_DBG_TFCSTS |
[19] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXPAUSED |
[21:20] | R | 0x0 | ALT_EMAC_GMAC_DBG_TRCSTS |
[22] | R | 0x0 | ALT_EMAC_GMAC_DBG_TWCSTS |
[23] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_23 |
[24] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXFSTS |
[25] | R | 0x0 | ALT_EMAC_GMAC_DBG_TXSTSFSTS |
[31:26] | R | 0x0 | ALT_EMAC_GMAC_DBG_RSVD_31_26 |
Field : rpests | |
MAC GMII or MII Receive Protocol Engine Status When high, this bit indicates that the MAC GMII or MII receive protocol engine is actively receiving data and not in IDLE state. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_RPESTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_RPESTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RPESTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_LSB 0 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_MSB 0 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK 0x00000001 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK 0xfffffffe |
#define | ALT_EMAC_GMAC_DBG_RPESTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RPESTS_GET(value) (((value) & 0x00000001) >> 0) |
#define | ALT_EMAC_GMAC_DBG_RPESTS_SET(value) (((value) << 0) & 0x00000001) |
Field : rfcfcsts | |
MAC Receive Frame Controller FIFO Status When high, this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Frame Controller Module. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB 1 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB 2 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH 2 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK 0x00000006 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK 0xfffffff9 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_GET(value) (((value) & 0x00000006) >> 1) |
#define | ALT_EMAC_GMAC_DBG_RFCFCSTS_SET(value) (((value) << 1) & 0x00000006) |
Field : reserved_3 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_LSB 3 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_MSB 3 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_SET_MSK 0x00000008 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_CLR_MSK 0xfffffff7 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_GET(value) (((value) & 0x00000008) >> 3) |
#define | ALT_EMAC_GMAC_DBG_RSVD_3_SET(value) (((value) << 3) & 0x00000008) |
Field : rwcsts | |
MTL Rx FIFO Write Controller Active Status When high, this bit indicates that the MTL Rx FIFO Write Controller is active and is transferring a received frame to the FIFO. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_LSB 4 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_MSB 4 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK 0x00000010 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK 0xffffffef |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_GET(value) (((value) & 0x00000010) >> 4) |
#define | ALT_EMAC_GMAC_DBG_RWCSTS_SET(value) (((value) << 4) & 0x00000010) |
Field : rrcsts | |
MTL Rx FIFO Read Controller State This field gives the state of the Rx FIFO read Controller:
Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE | 0x0 | ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA | 0x1 | ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT | 0x2 | ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS | 0x3 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE 0x0 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA 0x1 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT 0x2 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS 0x3 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_LSB 5 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_MSB 6 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH 2 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK 0x00000060 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK 0xffffff9f |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_GET(value) (((value) & 0x00000060) >> 5) |
#define | ALT_EMAC_GMAC_DBG_RRCSTS_SET(value) (((value) << 5) & 0x00000060) |
Field : reserved_7 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_LSB 7 |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_MSB 7 |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_SET_MSK 0x00000080 |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_CLR_MSK 0xffffff7f |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_GET(value) (((value) & 0x00000080) >> 7) |
#define | ALT_EMAC_GMAC_DBG_RSVD_7_SET(value) (((value) << 7) & 0x00000080) |
Field : rxfsts | |
MTL Rx FIFO Fill-level Status This field gives the status of the fill-level of the Rx FIFO:
Field Enumeration Values: Enum | Value | Description :--------------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY | 0x0 | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL | 0x1 | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL | 0x2 | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL | 0x3 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY 0x0 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL 0x2 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL 0x3 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_LSB 8 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_MSB 9 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH 2 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK 0x00000300 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK 0xfffffcff |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_GET(value) (((value) & 0x00000300) >> 8) |
#define | ALT_EMAC_GMAC_DBG_RXFSTS_SET(value) (((value) << 8) & 0x00000300) |
Field : reserved_15_10 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_LSB 10 |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_MSB 15 |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_WIDTH 6 |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_SET_MSK 0x0000fc00 |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_CLR_MSK 0xffff03ff |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_GET(value) (((value) & 0x0000fc00) >> 10) |
#define | ALT_EMAC_GMAC_DBG_RSVD_15_10_SET(value) (((value) << 10) & 0x0000fc00) |
Field : tpests | |
MAC GMII or MII Transmit Protocol Engine Status When high, this bit indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and is not in the IDLE state. Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TPESTS_E_DISD | 0x0 | ALT_EMAC_GMAC_DBG_TPESTS_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_E_END 0x1 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_LSB 16 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_MSB 16 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK 0x00010000 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK 0xfffeffff |
#define | ALT_EMAC_GMAC_DBG_TPESTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TPESTS_GET(value) (((value) & 0x00010000) >> 16) |
#define | ALT_EMAC_GMAC_DBG_TPESTS_SET(value) (((value) << 16) & 0x00010000) |
Field : tfcsts | |
MAC Transmit Frame Controller Status This field indicates the state of the MAC Transmit Frame Controller module:
Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE | 0x0 | ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG | 0x1 | ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE | 0x2 | ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM | 0x3 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE 0x0 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG 0x1 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE 0x2 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM 0x3 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_LSB 17 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_MSB 18 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH 2 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK 0x00060000 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK 0xfff9ffff |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_GET(value) (((value) & 0x00060000) >> 17) |
#define | ALT_EMAC_GMAC_DBG_TFCSTS_SET(value) (((value) << 17) & 0x00060000) |
Field : txpaused | |
MAC transmitter in PAUSE When high, this bit indicates that the MAC transmitter is in the PAUSE condition (in the full-duplex only mode) and hence does not schedule any frame for transmission. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS | 0x0 | ALT_EMAC_GMAC_DBG_TXPAUSED_E_END | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_E_END 0x1 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_LSB 19 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_MSB 19 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK 0x00080000 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK 0xfff7ffff |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_GET(value) (((value) & 0x00080000) >> 19) |
#define | ALT_EMAC_GMAC_DBG_TXPAUSED_SET(value) (((value) << 19) & 0x00080000) |
Field : trcsts | |
MTL Tx FIFO Read Controller Status This field indicates the state of the Tx FIFO Read Controller:
Field Enumeration Values: Enum | Value | Description :----------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE | 0x0 | ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE | 0x1 | ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT | 0x2 | ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT | 0x3 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE 0x0 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE 0x1 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT 0x2 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT 0x3 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_LSB 20 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_MSB 21 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH 2 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK 0x00300000 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK 0xffcfffff |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_GET(value) (((value) & 0x00300000) >> 20) |
#define | ALT_EMAC_GMAC_DBG_TRCSTS_SET(value) (((value) << 20) & 0x00300000) |
Field : twcsts | |
MTL Tx FIFO Write Controller Active Status When high, this bit indicates that the MTL Tx FIFO Write Controller is active and transferring data to the Tx FIFO. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_LSB 22 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_MSB 22 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK 0x00400000 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK 0xffbfffff |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_GET(value) (((value) & 0x00400000) >> 22) |
#define | ALT_EMAC_GMAC_DBG_TWCSTS_SET(value) (((value) << 22) & 0x00400000) |
Field : reserved_23 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_LSB 23 |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_MSB 23 |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_SET_MSK 0x00800000 |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_CLR_MSK 0xff7fffff |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_GET(value) (((value) & 0x00800000) >> 23) |
#define | ALT_EMAC_GMAC_DBG_RSVD_23_SET(value) (((value) << 23) & 0x00800000) |
Field : txfsts | |
MTL Tx FIFO Not Empty Status When high, this bit indicates that the MTL Tx FIFO is not empty and some data is left for transmission. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_LSB 24 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_MSB 24 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK 0x01000000 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK 0xfeffffff |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_GET(value) (((value) & 0x01000000) >> 24) |
#define | ALT_EMAC_GMAC_DBG_TXFSTS_SET(value) (((value) << 24) & 0x01000000) |
Field : txstsfsts | |
MTL TxStatus FIFO Full Status When high, this bit indicates that the MTL TxStatus FIFO is full. Therefore, the MTL cannot accept any more frames for transmission. This bit is reserved in the GMAC-AHB and GMAC-DMA configurations. Field Enumeration Values: Enum | Value | Description :------------------------------------------------------------------------------—|:---—|:---------— ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT | 0x0 | ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT | 0x1 | Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT 0x1 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB 25 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB 25 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH 1 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK 0x02000000 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK 0xfdffffff |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET(value) (((value) & 0x02000000) >> 25) |
#define | ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET(value) (((value) << 25) & 0x02000000) |
Field : reserved_31_26 | |
Reserved Field Access Macros: | |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_LSB 26 |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_MSB 31 |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_WIDTH 6 |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_SET_MSK 0xfc000000 |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_CLR_MSK 0x03ffffff |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_RESET 0x0 |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_GET(value) (((value) & 0xfc000000) >> 26) |
#define | ALT_EMAC_GMAC_DBG_RSVD_31_26_SET(value) (((value) << 26) & 0xfc000000) |
Data Structures | |
struct | ALT_EMAC_GMAC_DBG_s |
Macros | |
#define | ALT_EMAC_GMAC_DBG_RESET 0x00000000 |
#define | ALT_EMAC_GMAC_DBG_OFST 0x24 |
#define | ALT_EMAC_GMAC_DBG_ADDR(base) ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST)) |
Typedefs | |
typedef struct ALT_EMAC_GMAC_DBG_s | ALT_EMAC_GMAC_DBG_t |
struct ALT_EMAC_GMAC_DBG_s |
WARNING: The C register and register group struct declarations are provided for convenience and illustrative purposes. They should, however, be used with caution as the C language standard provides no guarantees about the alignment or atomicity of device memory accesses. The recommended practice for writing hardware drivers is to use the SoCAL access macros and alt_read_word() and alt_write_word() functions.
The struct declaration for register ALT_EMAC_GMAC_DBG.
Data Fields | ||
---|---|---|
const uint32_t | rpests: 1 | ALT_EMAC_GMAC_DBG_RPESTS |
const uint32_t | rfcfcsts: 2 | ALT_EMAC_GMAC_DBG_RFCFCSTS |
const uint32_t | reserved_3: 1 | ALT_EMAC_GMAC_DBG_RSVD_3 |
const uint32_t | rwcsts: 1 | ALT_EMAC_GMAC_DBG_RWCSTS |
const uint32_t | rrcsts: 2 | ALT_EMAC_GMAC_DBG_RRCSTS |
const uint32_t | reserved_7: 1 | ALT_EMAC_GMAC_DBG_RSVD_7 |
const uint32_t | rxfsts: 2 | ALT_EMAC_GMAC_DBG_RXFSTS |
const uint32_t | reserved_15_10: 6 | ALT_EMAC_GMAC_DBG_RSVD_15_10 |
const uint32_t | tpests: 1 | ALT_EMAC_GMAC_DBG_TPESTS |
const uint32_t | tfcsts: 2 | ALT_EMAC_GMAC_DBG_TFCSTS |
const uint32_t | txpaused: 1 | ALT_EMAC_GMAC_DBG_TXPAUSED |
const uint32_t | trcsts: 2 | ALT_EMAC_GMAC_DBG_TRCSTS |
const uint32_t | twcsts: 1 | ALT_EMAC_GMAC_DBG_TWCSTS |
const uint32_t | reserved_23: 1 | ALT_EMAC_GMAC_DBG_RSVD_23 |
const uint32_t | txfsts: 1 | ALT_EMAC_GMAC_DBG_TXFSTS |
const uint32_t | txstsfsts: 1 | ALT_EMAC_GMAC_DBG_TXSTSFSTS |
const uint32_t | reserved_31_26: 6 | ALT_EMAC_GMAC_DBG_RSVD_31_26 |
#define ALT_EMAC_GMAC_DBG_RPESTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
#define ALT_EMAC_GMAC_DBG_RPESTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RPESTS
#define ALT_EMAC_GMAC_DBG_RPESTS_LSB 0 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field.
#define ALT_EMAC_GMAC_DBG_RPESTS_MSB 0 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RPESTS register field.
#define ALT_EMAC_GMAC_DBG_RPESTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_RPESTS register field.
#define ALT_EMAC_GMAC_DBG_RPESTS_SET_MSK 0x00000001 |
The mask used to set the ALT_EMAC_GMAC_DBG_RPESTS register field value.
#define ALT_EMAC_GMAC_DBG_RPESTS_CLR_MSK 0xfffffffe |
The mask used to clear the ALT_EMAC_GMAC_DBG_RPESTS register field value.
#define ALT_EMAC_GMAC_DBG_RPESTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RPESTS register field.
#define ALT_EMAC_GMAC_DBG_RPESTS_GET | ( | value | ) | (((value) & 0x00000001) >> 0) |
Extracts the ALT_EMAC_GMAC_DBG_RPESTS field value from a register.
#define ALT_EMAC_GMAC_DBG_RPESTS_SET | ( | value | ) | (((value) << 0) & 0x00000001) |
Produces a ALT_EMAC_GMAC_DBG_RPESTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RFCFCSTS
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_LSB 1 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_MSB 2 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET_MSK 0x00000006 |
The mask used to set the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_CLR_MSK 0xfffffff9 |
The mask used to clear the ALT_EMAC_GMAC_DBG_RFCFCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RFCFCSTS register field.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_GET | ( | value | ) | (((value) & 0x00000006) >> 1) |
Extracts the ALT_EMAC_GMAC_DBG_RFCFCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_RFCFCSTS_SET | ( | value | ) | (((value) << 1) & 0x00000006) |
Produces a ALT_EMAC_GMAC_DBG_RFCFCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RSVD_3_LSB 3 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_3 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_3_MSB 3 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_3 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_3_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_3 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_3_SET_MSK 0x00000008 |
The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_3 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_3_CLR_MSK 0xfffffff7 |
The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_3 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_3_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RSVD_3 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_3_GET | ( | value | ) | (((value) & 0x00000008) >> 3) |
Extracts the ALT_EMAC_GMAC_DBG_RSVD_3 field value from a register.
#define ALT_EMAC_GMAC_DBG_RSVD_3_SET | ( | value | ) | (((value) << 3) & 0x00000008) |
Produces a ALT_EMAC_GMAC_DBG_RSVD_3 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RWCSTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
#define ALT_EMAC_GMAC_DBG_RWCSTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RWCSTS
#define ALT_EMAC_GMAC_DBG_RWCSTS_LSB 4 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field.
#define ALT_EMAC_GMAC_DBG_RWCSTS_MSB 4 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RWCSTS register field.
#define ALT_EMAC_GMAC_DBG_RWCSTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_RWCSTS register field.
#define ALT_EMAC_GMAC_DBG_RWCSTS_SET_MSK 0x00000010 |
The mask used to set the ALT_EMAC_GMAC_DBG_RWCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RWCSTS_CLR_MSK 0xffffffef |
The mask used to clear the ALT_EMAC_GMAC_DBG_RWCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RWCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RWCSTS register field.
#define ALT_EMAC_GMAC_DBG_RWCSTS_GET | ( | value | ) | (((value) & 0x00000010) >> 4) |
Extracts the ALT_EMAC_GMAC_DBG_RWCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_RWCSTS_SET | ( | value | ) | (((value) << 4) & 0x00000010) |
Produces a ALT_EMAC_GMAC_DBG_RWCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_IDLE 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMDATA 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_RDFRMSTAT 0x2 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
#define ALT_EMAC_GMAC_DBG_RRCSTS_E_FLUSHFRDS 0x3 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RRCSTS
#define ALT_EMAC_GMAC_DBG_RRCSTS_LSB 5 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field.
#define ALT_EMAC_GMAC_DBG_RRCSTS_MSB 6 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RRCSTS register field.
#define ALT_EMAC_GMAC_DBG_RRCSTS_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_DBG_RRCSTS register field.
#define ALT_EMAC_GMAC_DBG_RRCSTS_SET_MSK 0x00000060 |
The mask used to set the ALT_EMAC_GMAC_DBG_RRCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RRCSTS_CLR_MSK 0xffffff9f |
The mask used to clear the ALT_EMAC_GMAC_DBG_RRCSTS register field value.
#define ALT_EMAC_GMAC_DBG_RRCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RRCSTS register field.
#define ALT_EMAC_GMAC_DBG_RRCSTS_GET | ( | value | ) | (((value) & 0x00000060) >> 5) |
Extracts the ALT_EMAC_GMAC_DBG_RRCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_RRCSTS_SET | ( | value | ) | (((value) << 5) & 0x00000060) |
Produces a ALT_EMAC_GMAC_DBG_RRCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RSVD_7_LSB 7 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_7 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_7_MSB 7 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_7 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_7_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_7 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_7_SET_MSK 0x00000080 |
The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_7 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_7_CLR_MSK 0xffffff7f |
The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_7 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_7_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RSVD_7 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_7_GET | ( | value | ) | (((value) & 0x00000080) >> 7) |
Extracts the ALT_EMAC_GMAC_DBG_RSVD_7 field value from a register.
#define ALT_EMAC_GMAC_DBG_RSVD_7_SET | ( | value | ) | (((value) << 7) & 0x00000080) |
Produces a ALT_EMAC_GMAC_DBG_RSVD_7 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOEMPTY 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOBELLVL 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOABLVL 0x2 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
#define ALT_EMAC_GMAC_DBG_RXFSTS_E_RXFIFOFULL 0x3 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_RXFSTS
#define ALT_EMAC_GMAC_DBG_RXFSTS_LSB 8 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field.
#define ALT_EMAC_GMAC_DBG_RXFSTS_MSB 9 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RXFSTS register field.
#define ALT_EMAC_GMAC_DBG_RXFSTS_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_DBG_RXFSTS register field.
#define ALT_EMAC_GMAC_DBG_RXFSTS_SET_MSK 0x00000300 |
The mask used to set the ALT_EMAC_GMAC_DBG_RXFSTS register field value.
#define ALT_EMAC_GMAC_DBG_RXFSTS_CLR_MSK 0xfffffcff |
The mask used to clear the ALT_EMAC_GMAC_DBG_RXFSTS register field value.
#define ALT_EMAC_GMAC_DBG_RXFSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RXFSTS register field.
#define ALT_EMAC_GMAC_DBG_RXFSTS_GET | ( | value | ) | (((value) & 0x00000300) >> 8) |
Extracts the ALT_EMAC_GMAC_DBG_RXFSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_RXFSTS_SET | ( | value | ) | (((value) << 8) & 0x00000300) |
Produces a ALT_EMAC_GMAC_DBG_RXFSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_LSB 10 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_MSB 15 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_WIDTH 6 |
The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_SET_MSK 0x0000fc00 |
The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_CLR_MSK 0xffff03ff |
The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RSVD_15_10 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_GET | ( | value | ) | (((value) & 0x0000fc00) >> 10) |
Extracts the ALT_EMAC_GMAC_DBG_RSVD_15_10 field value from a register.
#define ALT_EMAC_GMAC_DBG_RSVD_15_10_SET | ( | value | ) | (((value) << 10) & 0x0000fc00) |
Produces a ALT_EMAC_GMAC_DBG_RSVD_15_10 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TPESTS_E_DISD 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
#define ALT_EMAC_GMAC_DBG_TPESTS_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TPESTS
#define ALT_EMAC_GMAC_DBG_TPESTS_LSB 16 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field.
#define ALT_EMAC_GMAC_DBG_TPESTS_MSB 16 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TPESTS register field.
#define ALT_EMAC_GMAC_DBG_TPESTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_TPESTS register field.
#define ALT_EMAC_GMAC_DBG_TPESTS_SET_MSK 0x00010000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TPESTS register field value.
#define ALT_EMAC_GMAC_DBG_TPESTS_CLR_MSK 0xfffeffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TPESTS register field value.
#define ALT_EMAC_GMAC_DBG_TPESTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TPESTS register field.
#define ALT_EMAC_GMAC_DBG_TPESTS_GET | ( | value | ) | (((value) & 0x00010000) >> 16) |
Extracts the ALT_EMAC_GMAC_DBG_TPESTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TPESTS_SET | ( | value | ) | (((value) << 16) & 0x00010000) |
Produces a ALT_EMAC_GMAC_DBG_TPESTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_IDLE 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_WAITIFG 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTPAUSE 0x2 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
#define ALT_EMAC_GMAC_DBG_TFCSTS_E_XTINFRM 0x3 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TFCSTS
#define ALT_EMAC_GMAC_DBG_TFCSTS_LSB 17 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field.
#define ALT_EMAC_GMAC_DBG_TFCSTS_MSB 18 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TFCSTS register field.
#define ALT_EMAC_GMAC_DBG_TFCSTS_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_DBG_TFCSTS register field.
#define ALT_EMAC_GMAC_DBG_TFCSTS_SET_MSK 0x00060000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TFCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TFCSTS_CLR_MSK 0xfff9ffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TFCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TFCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TFCSTS register field.
#define ALT_EMAC_GMAC_DBG_TFCSTS_GET | ( | value | ) | (((value) & 0x00060000) >> 17) |
Extracts the ALT_EMAC_GMAC_DBG_TFCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TFCSTS_SET | ( | value | ) | (((value) << 17) & 0x00060000) |
Produces a ALT_EMAC_GMAC_DBG_TFCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_DIS 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
#define ALT_EMAC_GMAC_DBG_TXPAUSED_E_END 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXPAUSED
#define ALT_EMAC_GMAC_DBG_TXPAUSED_LSB 19 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_MSB 19 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXPAUSED register field.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_TXPAUSED register field.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET_MSK 0x00080000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TXPAUSED register field value.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_CLR_MSK 0xfff7ffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TXPAUSED register field value.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TXPAUSED register field.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_GET | ( | value | ) | (((value) & 0x00080000) >> 19) |
Extracts the ALT_EMAC_GMAC_DBG_TXPAUSED field value from a register.
#define ALT_EMAC_GMAC_DBG_TXPAUSED_SET | ( | value | ) | (((value) << 19) & 0x00080000) |
Produces a ALT_EMAC_GMAC_DBG_TXPAUSED register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_IDLE 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_RDSTATE 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WAITTXSTAT 0x2 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
#define ALT_EMAC_GMAC_DBG_TRCSTS_E_WRTXSTAT 0x3 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TRCSTS
#define ALT_EMAC_GMAC_DBG_TRCSTS_LSB 20 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field.
#define ALT_EMAC_GMAC_DBG_TRCSTS_MSB 21 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TRCSTS register field.
#define ALT_EMAC_GMAC_DBG_TRCSTS_WIDTH 2 |
The width in bits of the ALT_EMAC_GMAC_DBG_TRCSTS register field.
#define ALT_EMAC_GMAC_DBG_TRCSTS_SET_MSK 0x00300000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TRCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TRCSTS_CLR_MSK 0xffcfffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TRCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TRCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TRCSTS register field.
#define ALT_EMAC_GMAC_DBG_TRCSTS_GET | ( | value | ) | (((value) & 0x00300000) >> 20) |
Extracts the ALT_EMAC_GMAC_DBG_TRCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TRCSTS_SET | ( | value | ) | (((value) << 20) & 0x00300000) |
Produces a ALT_EMAC_GMAC_DBG_TRCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TWCSTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
#define ALT_EMAC_GMAC_DBG_TWCSTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TWCSTS
#define ALT_EMAC_GMAC_DBG_TWCSTS_LSB 22 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field.
#define ALT_EMAC_GMAC_DBG_TWCSTS_MSB 22 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TWCSTS register field.
#define ALT_EMAC_GMAC_DBG_TWCSTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_TWCSTS register field.
#define ALT_EMAC_GMAC_DBG_TWCSTS_SET_MSK 0x00400000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TWCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TWCSTS_CLR_MSK 0xffbfffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TWCSTS register field value.
#define ALT_EMAC_GMAC_DBG_TWCSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TWCSTS register field.
#define ALT_EMAC_GMAC_DBG_TWCSTS_GET | ( | value | ) | (((value) & 0x00400000) >> 22) |
Extracts the ALT_EMAC_GMAC_DBG_TWCSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TWCSTS_SET | ( | value | ) | (((value) << 22) & 0x00400000) |
Produces a ALT_EMAC_GMAC_DBG_TWCSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RSVD_23_LSB 23 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_23 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_23_MSB 23 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_23 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_23_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_23 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_23_SET_MSK 0x00800000 |
The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_23 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_23_CLR_MSK 0xff7fffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_23 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_23_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RSVD_23 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_23_GET | ( | value | ) | (((value) & 0x00800000) >> 23) |
Extracts the ALT_EMAC_GMAC_DBG_RSVD_23 field value from a register.
#define ALT_EMAC_GMAC_DBG_RSVD_23_SET | ( | value | ) | (((value) << 23) & 0x00800000) |
Produces a ALT_EMAC_GMAC_DBG_RSVD_23 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TXFSTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
#define ALT_EMAC_GMAC_DBG_TXFSTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXFSTS
#define ALT_EMAC_GMAC_DBG_TXFSTS_LSB 24 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXFSTS_MSB 24 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXFSTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_TXFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXFSTS_SET_MSK 0x01000000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TXFSTS register field value.
#define ALT_EMAC_GMAC_DBG_TXFSTS_CLR_MSK 0xfeffffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TXFSTS register field value.
#define ALT_EMAC_GMAC_DBG_TXFSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TXFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXFSTS_GET | ( | value | ) | (((value) & 0x01000000) >> 24) |
Extracts the ALT_EMAC_GMAC_DBG_TXFSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TXFSTS_SET | ( | value | ) | (((value) << 24) & 0x01000000) |
Produces a ALT_EMAC_GMAC_DBG_TXFSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_INACT 0x0 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_E_ACT 0x1 |
Enumerated value for register field ALT_EMAC_GMAC_DBG_TXSTSFSTS
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_LSB 25 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_MSB 25 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_WIDTH 1 |
The width in bits of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET_MSK 0x02000000 |
The mask used to set the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_CLR_MSK 0xfdffffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_TXSTSFSTS register field.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_GET | ( | value | ) | (((value) & 0x02000000) >> 25) |
Extracts the ALT_EMAC_GMAC_DBG_TXSTSFSTS field value from a register.
#define ALT_EMAC_GMAC_DBG_TXSTSFSTS_SET | ( | value | ) | (((value) << 25) & 0x02000000) |
Produces a ALT_EMAC_GMAC_DBG_TXSTSFSTS register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_LSB 26 |
The Least Significant Bit (LSB) position of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_MSB 31 |
The Most Significant Bit (MSB) position of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_WIDTH 6 |
The width in bits of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_SET_MSK 0xfc000000 |
The mask used to set the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_CLR_MSK 0x03ffffff |
The mask used to clear the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_RESET 0x0 |
The reset value of the ALT_EMAC_GMAC_DBG_RSVD_31_26 register field.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_GET | ( | value | ) | (((value) & 0xfc000000) >> 26) |
Extracts the ALT_EMAC_GMAC_DBG_RSVD_31_26 field value from a register.
#define ALT_EMAC_GMAC_DBG_RSVD_31_26_SET | ( | value | ) | (((value) << 26) & 0xfc000000) |
Produces a ALT_EMAC_GMAC_DBG_RSVD_31_26 register field value suitable for setting the register.
#define ALT_EMAC_GMAC_DBG_RESET 0x00000000 |
The reset value of the ALT_EMAC_GMAC_DBG register.
#define ALT_EMAC_GMAC_DBG_OFST 0x24 |
The byte offset of the ALT_EMAC_GMAC_DBG register from the beginning of the component.
#define ALT_EMAC_GMAC_DBG_ADDR | ( | base | ) | ALT_CAST(void *, (ALT_CAST(char *, (base)) + ALT_EMAC_GMAC_DBG_OFST)) |
The address of the ALT_EMAC_GMAC_DBG register.
typedef struct ALT_EMAC_GMAC_DBG_s ALT_EMAC_GMAC_DBG_t |
The typedef declaration for register ALT_EMAC_GMAC_DBG.