ALTERA DOES NOT WARRANT THAT THE FUNCTIONS CONTAINED IN THIS PATCH WILL MEET YOUR REQUIREMENTS, OR THAT THE OPERATION OF THIS PATCH WILL BE UNINTERRUPTED OR ERROR-FREE. //**************************************************************** quartus-12.0-2.dp4-readme.txt Readme file for Quartus II 12.0 SP2 Patch 2.dp4 Copyright (C) Altera Corporation 2012 All right reserved. Patch created on September 7 2012 Patch case#: 70292 //**************************************************************** Please note, this patch is meant to address known software issues for Stratix V, Arria V and Cyclone V devices in the Quartus II software version 12.0 SP2. The device patches are cumulative. ====================================== The following were addressed in 2.dp2: ====================================== -------------------- Issue 1 (case 65815) -------------------- This patch allows designs to see the association between the DSP enable signal and the input registers for Arria V devices. -------------------- Issue 2 (case 66224) -------------------- This patch enables POF support for Stratix V 5SGXEB5, 5SGXEB6, 5SGXMB5, and 5SGXMB6 devices. -------------------- Issue 3 (case 66618) -------------------- If an Arria V GX parts has both datarate larger than 3125Mbps and smaller than 3125Mbps, the transceiver voltage is 1.1V for datarate smaller than 3125Mbps and 1.15V for datarate larger than 3125Mbps. This resulted a clash of voltages on VCCR/VCCT when using datarate above and below 3125Mbps. -------------------- Issue 4 (case 67678) -------------------- This patch updates Stratix V OCT calibration block settings in Quartus II software to match changes in Rref resistance from 2 KOhm to 1.8 KOhm. New settings also applies to Stratix V GT channels. Instructions: User must regenerate Quartus II Software IP files and recompile his/her design for this patch to take effect: 1.On a Qsys-based design, by opening the design in Qsys, (re)generating the files and recompiling. 2.On a Megawizard-based design, by opening the existing Megawizard design, (re)generating the files and recompiling. -------------------- Issue 5 (case 69027) -------------------- This patch enables POF support for Arria V 500GT/GX devices. -------------------- Issue 6 (case 69480) -------------------- The Fitter may not consistently promote all clock edges in a clock domain to use dedicated clock routing, if any of its destination registers are used to generate additional clock or control signals. This patch addresses this issue, and should reduce clock skew on the affected clock domain(s). The following INI is required to enable this change: fsv_adjust_clock_promotion_behavior=on -------------------- Issue 7 (case 69534) -------------------- Quartus II triggers the following Internal Error in Fitter stage: Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_mint_dq_grouping.cpp Line: 1179 (*group_query).second == id -------------------- Issue 8 (case 69608) -------------------- This patch enables POF support for Stratix V 5SGXEB5R2F43I3 device ====================================== The following were addressed in 2.dp3: ====================================== -------------------- Issue 9 (case 71185) -------------------- This patch fixes connectivity from CLKPINs to right-corner QCLKs on Cyclone V devices. -------------------- Issue 10 (case 69809) -------------------- Many checks are done on RAM blocks to ensure LUTRAM conversion is possible. One of these checks is done to prevent functional differences between the converted LUTRAM and the original block RAM. There is an issue caught in 12.0sp2 so the RAM blocks that have their read address clock set to clock1 are disabled. This may cause designs which used to rely on LUTRAM conversion for these type of RAM blocks to no-fit. This issue affects Stratix III/IV/V, Arria V, Cyclone V devices. This patch provides two fixes for this issue: 1. There is actually no functional difference if both clock0 and clock1 were driven by the same clock signal. Thus the constraint is relaxed to allow for this case. 2. The functional difference only occurs during a rare accidental read-during-write. If you are aware of the differences between block RAMs and LUTRAMs, Altera provides the ability to turn this constraint off by using the following INI: allow_port_b_read_address_clk_for_lutram_conversion=on -------------------- Issue 11 (case 70771) -------------------- This patch enables POF support for Arria V 360 GT/GX devices. -------------------- Issue 12 (case 69659) -------------------- Some circuits may experience non-optimal pipeline placement. In some scenario, the final placement does not have the pipeline registers evenly spaced out, and may lead to timing failure on the pipeline transfer that is placed farther apart. This patch provides an enhancement on the pipeline placement, such that fitter will be trying to balance the register pipelines more intelligently. This enhancement is INI-protected. You need to use the following INI to enable this feature: vpr_place_enable_sr_dynamic_adjustment=on -------------------- Issue 13 (case 69532) -------------------- This patch allows you to select high-effort as well as power-based exploration options in DSE for projects targeting Cyclone IV, Cyclone V, and Arria V devices. ====================================== The following were addressed in 2.dp4: ====================================== -------------------- Issue 14 (case 68707) -------------------- This patch supports -4 timing model for Arria V B3 ES devices. -------------------- Issue 15 (case 70109) -------------------- For Stratix V ddio_out functional simulation, user may encounter visible glitches due to delta cycle delays. This patch removes the glitch from functional simulation model. -------------------- Issue 16 (case 71749) -------------------- The tx pulse will be correctly stretched when simulating the Seriallite-III IP. This applies to Stratix V devices only. -------------------- Issue 17 (case 72574) -------------------- Quartus II software triggers the following Internal Error when running compilation after doing "Update Symbol or Block..." in Block Editor. Internal Error: Sub-system: DBMUI, File: /quartus/db/dbmui/dbmui_manager.cpp, Line: 1179 Attempt made to free all hierarchy databases but the following callers are still accessing it: GEDQ_VIEW::get_sld_hdb_iname, Caution - You must either have previously installed the Quartus II 12.0 SP2 software or must install the Quartus II 12.0 SP2 software before installing this patch. Otherwise, the patch will not be installed correctly and the Quartus II software will not run properly.